4968 lines
298 KiB
XML
4968 lines
298 KiB
XML
<?xml version='1.0' encoding='utf-8'?>
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<com.csky.cds.peripheral>
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<config Version="0.0.1">
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<Peripheral Name="glb">
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<Register Name="clk_cfg0" Authority="RW" Address="0x40000000" Width="32" Description="clk_cfg0.">
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<Bit Name="glb_id" Authority="RW" Bits="31-28" />
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<Bit Name="chip_rdy" Authority="RW" Bits="27" />
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<Bit Name="fclk_sw_state" Authority="RW" Bits="26-24" />
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<Bit Name="reg_bclk_div" Authority="RW" Bits="23-16" />
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<Bit Name="reg_hclk_div" Authority="RW" Bits="15-8" />
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<Bit Name="hbn_root_clk_sel" Authority="RW" Bits="7-6" />
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<Bit Name="reg_pll_sel" Authority="RW" Bits="5-4" />
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<Bit Name="reg_bclk_en" Authority="RW" Bits="3" />
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<Bit Name="reg_hclk_en" Authority="RW" Bits="2" />
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<Bit Name="reg_fclk_en" Authority="RW" Bits="1" />
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<Bit Name="reg_pll_en" Authority="RW" Bits="0" />
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</Register>
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<Register Name="clk_cfg1" Authority="RW" Address="0x40000004" Width="32" Description="clk_cfg1.">
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<Bit Name="reg_cam_ref_clk_div" Authority="RW" Bits="31-30" />
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<Bit Name="reg_cam_ref_clk_src_sel" Authority="RW" Bits="29" />
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<Bit Name="reg_cam_ref_clk_en" Authority="RW" Bits="28" />
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<Bit Name="m154_zbEn" Authority="RW" Bits="25" />
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<Bit Name="ble_en" Authority="RW" Bits="24" />
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<Bit Name="ble_clk_sel" Authority="RW" Bits="21-16" />
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<Bit Name="reg_i2s_0_ref_clk_oe" Authority="RW" Bits="14" />
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<Bit Name="reg_i2s0_clk_en" Authority="RW" Bits="13" />
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<Bit Name="reg_i2s_clk_sel" Authority="RW" Bits="12" />
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<Bit Name="dll_48m_div_en" Authority="RW" Bits="9" />
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<Bit Name="usb_clk_en" Authority="RW" Bits="8" />
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<Bit Name="qdec_clk_sel" Authority="RW" Bits="7" />
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<Bit Name="qdec_clk_div" Authority="RW" Bits="4-0" />
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</Register>
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<Register Name="clk_cfg2" Authority="RW" Address="0x40000008" Width="32" Description="clk_cfg2.">
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<Bit Name="dma_clk_en" Authority="RW" Bits="31-24" />
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<Bit Name="ir_clk_en" Authority="RW" Bits="23" />
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<Bit Name="ir_clk_div" Authority="RW" Bits="21-16" />
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<Bit Name="sf_clk_sel2" Authority="RW" Bits="15-14" />
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<Bit Name="sf_clk_sel" Authority="RW" Bits="13-12" />
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<Bit Name="sf_clk_en" Authority="RW" Bits="11" />
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<Bit Name="sf_clk_div" Authority="RW" Bits="10-8" />
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<Bit Name="hbn_uart_clk_sel" Authority="RW" Bits="7" />
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<Bit Name="uart_clk_en" Authority="RW" Bits="4" />
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<Bit Name="uart_clk_div" Authority="RW" Bits="2-0" />
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</Register>
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<Register Name="clk_cfg3" Authority="RW" Address="0x4000000C" Width="32" Description="clk_cfg3.">
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<Bit Name="chip_clk_out_1_sel" Authority="RW" Bits="31-30" />
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<Bit Name="chip_clk_out_0_sel" Authority="RW" Bits="29-28" />
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<Bit Name="i2c_clk_en" Authority="RW" Bits="24" />
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<Bit Name="i2c_clk_div" Authority="RW" Bits="23-16" />
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<Bit Name="cfg_inv_eth_rx_clk" Authority="RW" Bits="10" />
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<Bit Name="cfg_inv_rf_test_clk_o" Authority="RW" Bits="9" />
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<Bit Name="spi_clk_en" Authority="RW" Bits="8" />
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<Bit Name="cfg_inv_eth_tx_clk" Authority="RW" Bits="7" />
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<Bit Name="cfg_inv_eth_ref_clk_o" Authority="RW" Bits="6" />
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<Bit Name="cfg_sel_eth_ref_clk_o" Authority="RW" Bits="5" />
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<Bit Name="spi_clk_div" Authority="RW" Bits="4-0" />
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</Register>
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<Register Name="swrst_cfg0" Authority="RW" Address="0x40000010" Width="32" Description="swrst_cfg0.">
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<Bit Name="swrst_s30" Authority="RW" Bits="8" />
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<Bit Name="swrst_s20" Authority="RW" Bits="4" />
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<Bit Name="swrst_s01" Authority="RW" Bits="1" />
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<Bit Name="swrst_s00" Authority="RW" Bits="0" />
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</Register>
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<Register Name="swrst_cfg1" Authority="RW" Address="0x40000014" Width="32" Description="swrst_cfg1.">
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<Bit Name="swrst_s1ae" Authority="RW" Bits="30" />
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<Bit Name="swrst_s1ad" Authority="RW" Bits="29" />
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<Bit Name="swrst_s1ac" Authority="RW" Bits="28" />
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<Bit Name="swrst_s1ab" Authority="RW" Bits="27" />
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<Bit Name="swrst_s1aa" Authority="RW" Bits="26" />
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<Bit Name="swrst_s1a9" Authority="RW" Bits="25" />
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<Bit Name="swrst_s1a8" Authority="RW" Bits="24" />
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<Bit Name="swrst_s1a7" Authority="RW" Bits="23" />
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<Bit Name="swrst_s1a6" Authority="RW" Bits="22" />
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<Bit Name="swrst_s1a5" Authority="RW" Bits="21" />
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<Bit Name="swrst_s1a4" Authority="RW" Bits="20" />
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<Bit Name="swrst_s1a3" Authority="RW" Bits="19" />
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<Bit Name="swrst_s1a2" Authority="RW" Bits="18" />
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<Bit Name="swrst_s1a1" Authority="RW" Bits="17" />
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<Bit Name="swrst_s1a0" Authority="RW" Bits="16" />
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<Bit Name="swrst_s1f" Authority="RW" Bits="15" />
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<Bit Name="swrst_s1e" Authority="RW" Bits="14" />
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<Bit Name="swrst_s1d" Authority="RW" Bits="13" />
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<Bit Name="swrst_s1c" Authority="RW" Bits="12" />
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<Bit Name="swrst_s1b" Authority="RW" Bits="11" />
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<Bit Name="swrst_s1a" Authority="RW" Bits="10" />
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<Bit Name="swrst_s19" Authority="RW" Bits="9" />
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<Bit Name="swrst_s18" Authority="RW" Bits="8" />
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<Bit Name="swrst_s17" Authority="RW" Bits="7" />
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<Bit Name="swrst_s16" Authority="RW" Bits="6" />
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<Bit Name="swrst_s15" Authority="RW" Bits="5" />
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<Bit Name="swrst_s14" Authority="RW" Bits="4" />
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<Bit Name="swrst_s13" Authority="RW" Bits="3" />
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<Bit Name="swrst_s12" Authority="RW" Bits="2" />
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<Bit Name="swrst_s11" Authority="RW" Bits="1" />
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<Bit Name="swrst_s10" Authority="RW" Bits="0" />
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</Register>
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<Register Name="swrst_cfg2" Authority="RW" Address="0x40000018" Width="32" Description="swrst_cfg2.">
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<Bit Name="pka_clk_sel" Authority="RW" Bits="24" />
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<Bit Name="reg_ctrl_reset_dummy" Authority="RW" Bits="7-4" />
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<Bit Name="reg_ctrl_sys_reset" Authority="RW" Bits="2" />
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<Bit Name="reg_ctrl_cpu_reset" Authority="RW" Bits="1" />
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<Bit Name="reg_ctrl_pwron_rst" Authority="RW" Bits="0" />
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</Register>
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<Register Name="swrst_cfg3" Authority="RW" Address="0x4000001C" Width="32" Description="swrst_cfg3." />
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<Register Name="cgen_cfg0" Authority="RW" Address="0x40000020" Width="32" Description="cgen_cfg0.">
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<Bit Name="cgen_m" Authority="RW" Bits="7-0" />
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</Register>
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<Register Name="cgen_cfg1" Authority="RW" Address="0x40000024" Width="32" Description="cgen_cfg1.">
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<Bit Name="cgen_s1a" Authority="RW" Bits="31-16" />
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<Bit Name="cgen_s1" Authority="RW" Bits="15-0" />
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</Register>
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<Register Name="cgen_cfg2" Authority="RW" Address="0x40000028" Width="32" Description="cgen_cfg2.">
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<Bit Name="cgen_s3" Authority="RW" Bits="4" />
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<Bit Name="cgen_s2" Authority="RW" Bits="0" />
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</Register>
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<Register Name="cgen_cfg3" Authority="RW" Address="0x40000x2C" Width="32" Description="cgen_cfg3." />
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<Register Name="MBIST_CTL" Authority="RW" Address="0x40000030" Width="32" Description="MBIST_CTL.">
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<Bit Name="reg_mbist_rst_n" Authority="RW" Bits="31" />
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<Bit Name="em_ram_mbist_mode" Authority="RW" Bits="5" />
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<Bit Name="ocram_mbist_mode" Authority="RW" Bits="4" />
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<Bit Name="tag_mbist_mode" Authority="RW" Bits="3" />
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<Bit Name="hsram_cache_mbist_mode" Authority="RW" Bits="2" />
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<Bit Name="hsram_mem_mbist_mode" Authority="RW" Bits="1" />
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<Bit Name="irom_mbist_mode" Authority="RW" Bits="0" />
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</Register>
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<Register Name="MBIST_STAT" Authority="RW" Address="0x40000034" Width="32" Description="MBIST_STAT.">
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<Bit Name="em_ram_mbist_fail" Authority="RW" Bits="21" />
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<Bit Name="ocram_mbist_fail" Authority="RW" Bits="20" />
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<Bit Name="tag_mbist_fail" Authority="RW" Bits="19" />
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<Bit Name="hsram_cache_mbist_fail" Authority="RW" Bits="18" />
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<Bit Name="hsram_mem_mbist_fail" Authority="RW" Bits="17" />
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<Bit Name="irom_mbist_fail" Authority="RW" Bits="16" />
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<Bit Name="em_ram_mbist_done" Authority="RW" Bits="5" />
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<Bit Name="ocram_mbist_done" Authority="RW" Bits="4" />
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<Bit Name="tag_mbist_done" Authority="RW" Bits="3" />
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<Bit Name="hsram_cache_mbist_done" Authority="RW" Bits="2" />
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<Bit Name="hsram_mem_mbist_done" Authority="RW" Bits="1" />
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<Bit Name="irom_mbist_done" Authority="RW" Bits="0" />
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</Register>
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<Register Name="bmx_cfg1" Authority="RW" Address="0x40000050" Width="32" Description="bmx_cfg1.">
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<Bit Name="hbn_apb_cfg" Authority="RW" Bits="31-24" />
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<Bit Name="pds_apb_cfg" Authority="RW" Bits="23-16" />
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<Bit Name="hsel_option" Authority="RW" Bits="15-12" />
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<Bit Name="bmx_gating_dis" Authority="RW" Bits="10" />
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<Bit Name="bmx_busy_option_dis" Authority="RW" Bits="9" />
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<Bit Name="bmx_err_en" Authority="RW" Bits="8" />
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<Bit Name="bmx_arb_mode" Authority="RW" Bits="5-4" />
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<Bit Name="bmx_timeout_en" Authority="RW" Bits="3-0" />
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</Register>
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<Register Name="bmx_cfg2" Authority="RW" Address="0x40000054" Width="32" Description="bmx_cfg2.">
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<Bit Name="bmx_dbg_sel" Authority="RW" Bits="31-28" />
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<Bit Name="reg_w_thre_l1c" Authority="RW" Bits="11-10" />
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<Bit Name="reg_w_thre_bmx" Authority="RW" Bits="9-8" />
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<Bit Name="bmx_err_tz" Authority="RW" Bits="5" />
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<Bit Name="bmx_err_dec" Authority="RW" Bits="4" />
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<Bit Name="bmx_err_addr_dis" Authority="RW" Bits="0" />
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</Register>
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<Register Name="bmx_err_addr" Authority="RW" Address="0x40000058" Width="32" Description="bmx_err_addr.">
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<Bit Name="bmx_err_addr" Authority="RW" Bits="31-0" />
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</Register>
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<Register Name="bmx_dbg_out" Authority="RW" Address="0x40000x5C" Width="32" Description="bmx_dbg_out.">
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<Bit Name="bmx_dbg_out" Authority="RW" Bits="31-0" />
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</Register>
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<Register Name="rsv0" Authority="RW" Address="0x40000060" Width="32" Description="rsv0.">
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<Bit Name="rsvd_31_0" Authority="RW" Bits="31-0" />
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</Register>
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<Register Name="rsv1" Authority="RW" Address="0x40000064" Width="32" Description="rsv1.">
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<Bit Name="rsvd_31_0" Authority="RW" Bits="31-0" />
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</Register>
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<Register Name="rsv2" Authority="RW" Address="0x40000068" Width="32" Description="rsv2.">
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<Bit Name="rsvd_31_0" Authority="RW" Bits="31-0" />
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</Register>
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<Register Name="rsv3" Authority="RW" Address="0x40000x6C" Width="32" Description="rsv3.">
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<Bit Name="rsvd_31_0" Authority="RW" Bits="31-0" />
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</Register>
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<Register Name="sram_ret" Authority="RW" Address="0x40000070" Width="32" Description="sram_ret.">
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<Bit Name="reg_sram_ret" Authority="RW" Bits="31-0" />
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</Register>
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<Register Name="sram_slp" Authority="RW" Address="0x40000074" Width="32" Description="sram_slp.">
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<Bit Name="reg_sram_slp" Authority="RW" Bits="31-0" />
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</Register>
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<Register Name="sram_parm" Authority="RW" Address="0x40000078" Width="32" Description="sram_parm.">
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<Bit Name="reg_sram_parm" Authority="RW" Bits="31-0" />
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</Register>
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<Register Name="seam_misc" Authority="RW" Address="0x4000007C" Width="32" Description="seam_misc.">
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<Bit Name="em_sel" Authority="RW" Bits="3-0" />
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</Register>
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<Register Name="glb_parm" Authority="RW" Address="0x40000080" Width="32" Description="glb_parm.">
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<Bit Name="pin_sel_emac_cam" Authority="RW" Bits="31" />
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<Bit Name="reg_ext_rst_smt" Authority="RW" Bits="30" />
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<Bit Name="reg_kys_drv_val" Authority="RW" Bits="29" />
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<Bit Name="uart_swap_set" Authority="RW" Bits="27-24" />
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<Bit Name="p6_jtag_use_io_0_2_7" Authority="RW" Bits="23" />
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<Bit Name="p5_dac_test_with_jtag" Authority="RW" Bits="21" />
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<Bit Name="p4_adc_test_with_jtag" Authority="RW" Bits="20" />
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<Bit Name="p3_cci_use_io_0_2_7" Authority="RW" Bits="19" />
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<Bit Name="p2_dac_test_with_cci" Authority="RW" Bits="18" />
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<Bit Name="p1_adc_test_with_cci" Authority="RW" Bits="17" />
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<Bit Name="reg_cci_use_jtag_pin" Authority="RW" Bits="16" />
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<Bit Name="reg_spi_0_swap" Authority="RW" Bits="13" />
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<Bit Name="reg_spi_0_master_mode" Authority="RW" Bits="12" />
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<Bit Name="cfg_flash_scenario" Authority="RW" Bits="11-10" />
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<Bit Name="cfg_sflash2_swap_cs_io2" Authority="RW" Bits="9" />
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<Bit Name="cfg_sflash2_swap_io0_io3" Authority="RW" Bits="8" />
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<Bit Name="jtag_swap_set" Authority="RW" Bits="7-0" />
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</Register>
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<Register Name="PDM_CLK_CTRL" Authority="RW" Address="0x40000084" Width="32" Description="PDM_CLK_CTRL.">
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<Bit Name="reg_pdm0_clk_en" Authority="RW" Bits="7" />
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<Bit Name="reg_pdm0_clk_div" Authority="RW" Bits="5-0" />
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</Register>
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<Register Name="GPIO_USE_PSRAM__IO" Authority="RW" Address="0x40000088" Width="32" Description="GPIO_USE_PSRAM__IO.">
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<Bit Name="cfg_gpio_use_psram_io" Authority="RW" Bits="5-0" />
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</Register>
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<Register Name="CPU_CLK_CFG" Authority="RW" Address="0x40000090" Width="32" Description="CPU_CLK_CFG.">
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<Bit Name="debug_ndreset_gate" Authority="RW" Bits="20" />
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<Bit Name="cpu_rtc_sel" Authority="RW" Bits="19" />
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<Bit Name="cpu_rtc_en" Authority="RW" Bits="18" />
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<Bit Name="cpu_rtc_div" Authority="RW" Bits="16-0" />
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</Register>
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<Register Name="GPADC_32M_SRC_CTRL" Authority="RW" Address="0x400000A4" Width="32" Description="GPADC_32M_SRC_CTRL.">
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<Bit Name="gpadc_32m_div_en" Authority="RW" Bits="8" />
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<Bit Name="gpadc_32m_clk_sel" Authority="RW" Bits="7" />
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<Bit Name="gpadc_32m_clk_div" Authority="RW" Bits="5-0" />
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</Register>
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<Register Name="DIG32K_WAKEUP_CTRL" Authority="RW" Address="0x400000A8" Width="32" Description="DIG32K_WAKEUP_CTRL.">
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<Bit Name="reg_en_platform_wakeup" Authority="RW" Bits="31" />
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<Bit Name="dig_clk_src_sel" Authority="RW" Bits="29-28" />
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<Bit Name="dig_512k_comp" Authority="RW" Bits="25" />
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<Bit Name="dig_512k_en" Authority="RW" Bits="24" />
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<Bit Name="dig_512k_div" Authority="RW" Bits="22-16" />
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<Bit Name="dig_32k_comp" Authority="RW" Bits="13" />
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<Bit Name="dig_32k_en" Authority="RW" Bits="12" />
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<Bit Name="dig_32k_div" Authority="RW" Bits="10-0" />
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</Register>
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<Register Name="WIFI_BT_COEX_CTRL" Authority="RW" Address="0x400000AC" Width="32" Description="WIFI_BT_COEX_CTRL.">
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<Bit Name="en_gpio_bt_coex" Authority="RW" Bits="12" />
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<Bit Name="coex_bt_bw" Authority="RW" Bits="11" />
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<Bit Name="coex_bt_pti" Authority="RW" Bits="10-7" />
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<Bit Name="coex_bt_channel" Authority="RW" Bits="6-0" />
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</Register>
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<Register Name="BZ_COEX_CTRL" Authority="RW" Address="0x400000B0" Width="32" Description="BZ_COEX_CTRL.">
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<Bit Name="coex_arb" Authority="RW" Bits="31-28" />
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<Bit Name="ble_tx_abort_dis" Authority="RW" Bits="27" />
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<Bit Name="ble_rx_abort_dis" Authority="RW" Bits="26" />
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<Bit Name="m154_tx_abort_dis" Authority="RW" Bits="25" />
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<Bit Name="m154_rx_abort_dis" Authority="RW" Bits="24" />
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<Bit Name="coex_force_ch" Authority="RW" Bits="22-16" />
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<Bit Name="coex_option" Authority="RW" Bits="15" />
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<Bit Name="force_ble_win" Authority="RW" Bits="14" />
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<Bit Name="force_m154_win" Authority="RW" Bits="13" />
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<Bit Name="coex_pri" Authority="RW" Bits="12" />
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<Bit Name="bz_abort_pol" Authority="RW" Bits="11" />
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<Bit Name="bz_active_pol" Authority="RW" Bits="10" />
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<Bit Name="bz_pri_pol" Authority="RW" Bits="9" />
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<Bit Name="bz_pri_en" Authority="RW" Bits="8" />
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<Bit Name="bz_pri_thr" Authority="RW" Bits="7-4" />
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<Bit Name="m154_rx_ignore" Authority="RW" Bits="3" />
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<Bit Name="ble_rx_ignore" Authority="RW" Bits="2" />
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<Bit Name="wlan_en" Authority="RW" Bits="1" />
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<Bit Name="coex_en" Authority="RW" Bits="0" />
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</Register>
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<Register Name="UART_SIG_SEL_0" Authority="RW" Address="0x400000C0" Width="32" Description="UART_SIG_SEL_0.">
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<Bit Name="uart_sig_7_sel" Authority="RW" Bits="31-28" />
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<Bit Name="uart_sig_6_sel" Authority="RW" Bits="27-24" />
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<Bit Name="uart_sig_5_sel" Authority="RW" Bits="23-20" />
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<Bit Name="uart_sig_4_sel" Authority="RW" Bits="19-16" />
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<Bit Name="uart_sig_3_sel" Authority="RW" Bits="15-12" />
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<Bit Name="uart_sig_2_sel" Authority="RW" Bits="11-8" />
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<Bit Name="uart_sig_1_sel" Authority="RW" Bits="7-4" />
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<Bit Name="uart_sig_0_sel" Authority="RW" Bits="3-0" />
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</Register>
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<Register Name="DBG_SEL_LL" Authority="RW" Address="0x400000D0" Width="32" Description="DBG_SEL_LL.">
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<Bit Name="reg_dbg_ll_ctrl" Authority="RW" Bits="31-0" />
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</Register>
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<Register Name="DBG_SEL_LH" Authority="RW" Address="0x400000D4" Width="32" Description="DBG_SEL_LH.">
|
|
<Bit Name="reg_dbg_lh_ctrl" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DBG_SEL_HL" Authority="RW" Address="0x400000D8" Width="32" Description="DBG_SEL_HL.">
|
|
<Bit Name="reg_dbg_hl_ctrl" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DBG_SEL_HH" Authority="RW" Address="0x400000DC" Width="32" Description="DBG_SEL_HH.">
|
|
<Bit Name="reg_dbg_hh_ctrl" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="debug" Authority="RW" Address="0x400000E0" Width="32" Description="debug.">
|
|
<Bit Name="debug_i" Authority="RW" Bits="31-1" />
|
|
<Bit Name="debug_oe" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL0" Authority="RW" Address="0x40000100" Width="32" Description="GPIO_CFGCTL0.">
|
|
<Bit Name="reg_gpio_1_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_1_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_1_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_1_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_1_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_1_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_0_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_0_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_0_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_0_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_0_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_0_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL1" Authority="RW" Address="0x40000104" Width="32" Description="GPIO_CFGCTL1.">
|
|
<Bit Name="reg_gpio_3_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_3_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_3_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_3_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_3_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_3_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_2_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_2_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_2_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_2_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_2_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_2_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL2" Authority="RW" Address="0x40000108" Width="32" Description="GPIO_CFGCTL2.">
|
|
<Bit Name="reg_gpio_5_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_5_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_5_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_5_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_5_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_5_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_4_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_4_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_4_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_4_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_4_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_4_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL3" Authority="RW" Address="0x4000010C" Width="32" Description="GPIO_CFGCTL3.">
|
|
<Bit Name="reg_gpio_7_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_7_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_7_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_7_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_7_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_7_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_6_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_6_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_6_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_6_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_6_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_6_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL4" Authority="RW" Address="0x40000110" Width="32" Description="GPIO_CFGCTL4.">
|
|
<Bit Name="reg_gpio_9_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_9_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_9_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_9_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_9_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_9_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_8_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_8_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_8_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_8_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_8_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_8_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL5" Authority="RW" Address="0x40000114" Width="32" Description="GPIO_CFGCTL5.">
|
|
<Bit Name="reg_gpio_11_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_11_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_11_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_11_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_11_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_11_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_10_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_10_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_10_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_10_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_10_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_10_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL6" Authority="RW" Address="0x40000118" Width="32" Description="GPIO_CFGCTL6.">
|
|
<Bit Name="reg_gpio_13_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_13_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_13_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_13_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_13_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_13_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_12_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_12_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_12_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_12_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_12_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_12_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL7" Authority="RW" Address="0x4000011C" Width="32" Description="GPIO_CFGCTL7.">
|
|
<Bit Name="reg_gpio_15_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_15_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_15_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_15_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_15_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_15_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_14_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_14_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_14_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_14_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_14_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_14_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL8" Authority="RW" Address="0x40000120" Width="32" Description="GPIO_CFGCTL8.">
|
|
<Bit Name="reg_gpio_17_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_17_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_17_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_17_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_17_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_17_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_16_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_16_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_16_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_16_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_16_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_16_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL9" Authority="RW" Address="0x40000124" Width="32" Description="GPIO_CFGCTL9.">
|
|
<Bit Name="reg_gpio_19_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_19_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_19_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_19_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_19_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_19_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_18_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_18_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_18_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_18_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_18_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_18_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL10" Authority="RW" Address="0x40000128" Width="32" Description="GPIO_CFGCTL10.">
|
|
<Bit Name="reg_gpio_21_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_21_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_21_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_21_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_21_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_21_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_20_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_20_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_20_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_20_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_20_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_20_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL11" Authority="RW" Address="0x4000012C" Width="32" Description="GPIO_CFGCTL11.">
|
|
<Bit Name="reg_gpio_23_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_23_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_23_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_23_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_23_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_23_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_22_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_22_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_22_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_22_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_22_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_22_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL12" Authority="RW" Address="0x40000130" Width="32" Description="GPIO_CFGCTL12.">
|
|
<Bit Name="reg_gpio_25_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_25_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_25_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_25_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_25_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_25_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_24_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_24_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_24_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_24_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_24_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_24_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL13" Authority="RW" Address="0x40000134" Width="32" Description="GPIO_CFGCTL13.">
|
|
<Bit Name="reg_gpio_27_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_27_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_27_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_27_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_27_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_27_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_26_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_26_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_26_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_26_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_26_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_26_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL14" Authority="RW" Address="0x40000138" Width="32" Description="GPIO_CFGCTL14.">
|
|
<Bit Name="reg_gpio_29_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_29_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_29_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_29_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_29_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_29_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_28_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_28_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_28_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_28_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_28_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_28_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL15" Authority="RW" Address="0x4000013C" Width="32" Description="GPIO_CFGCTL15.">
|
|
<Bit Name="reg_gpio_31_func_sel" Authority="RW" Bits="28-24" />
|
|
<Bit Name="reg_gpio_31_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_31_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_31_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_31_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_31_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_30_func_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="reg_gpio_30_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_30_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_30_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_30_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_30_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL16" Authority="RW" Address="0x40000140" Width="32" Description="GPIO_CFGCTL16.">
|
|
<Bit Name="reg_gpio_33_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_33_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_33_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_33_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_33_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_32_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_32_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_32_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_32_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_32_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL17" Authority="RW" Address="0x40000144" Width="32" Description="GPIO_CFGCTL17.">
|
|
<Bit Name="reg_gpio_35_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_35_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_35_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_35_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_35_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_34_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_34_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_34_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_34_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_34_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL18" Authority="RW" Address="0x40000148" Width="32" Description="GPIO_CFGCTL18.">
|
|
<Bit Name="reg_gpio_37_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_37_pu" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_37_drv" Authority="RW" Bits="19-18" />
|
|
<Bit Name="reg_gpio_37_smt" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_37_ie" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_36_pd" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_36_pu" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_36_drv" Authority="RW" Bits="3-2" />
|
|
<Bit Name="reg_gpio_36_smt" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_36_ie" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL30" Authority="RW" Address="0x40000180" Width="32" Description="GPIO_CFGCTL30.">
|
|
<Bit Name="reg_gpio_31_i" Authority="RW" Bits="31" />
|
|
<Bit Name="reg_gpio_30_i" Authority="RW" Bits="30" />
|
|
<Bit Name="reg_gpio_29_i" Authority="RW" Bits="29" />
|
|
<Bit Name="reg_gpio_28_i" Authority="RW" Bits="28" />
|
|
<Bit Name="reg_gpio_27_i" Authority="RW" Bits="27" />
|
|
<Bit Name="reg_gpio_26_i" Authority="RW" Bits="26" />
|
|
<Bit Name="reg_gpio_25_i" Authority="RW" Bits="25" />
|
|
<Bit Name="reg_gpio_24_i" Authority="RW" Bits="24" />
|
|
<Bit Name="reg_gpio_23_i" Authority="RW" Bits="23" />
|
|
<Bit Name="reg_gpio_22_i" Authority="RW" Bits="22" />
|
|
<Bit Name="reg_gpio_21_i" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_20_i" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_19_i" Authority="RW" Bits="19" />
|
|
<Bit Name="reg_gpio_18_i" Authority="RW" Bits="18" />
|
|
<Bit Name="reg_gpio_17_i" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_16_i" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_15_i" Authority="RW" Bits="15" />
|
|
<Bit Name="reg_gpio_14_i" Authority="RW" Bits="14" />
|
|
<Bit Name="reg_gpio_13_i" Authority="RW" Bits="13" />
|
|
<Bit Name="reg_gpio_12_i" Authority="RW" Bits="12" />
|
|
<Bit Name="reg_gpio_11_i" Authority="RW" Bits="11" />
|
|
<Bit Name="reg_gpio_10_i" Authority="RW" Bits="10" />
|
|
<Bit Name="reg_gpio_9_i" Authority="RW" Bits="9" />
|
|
<Bit Name="reg_gpio_8_i" Authority="RW" Bits="8" />
|
|
<Bit Name="reg_gpio_7_i" Authority="RW" Bits="7" />
|
|
<Bit Name="reg_gpio_6_i" Authority="RW" Bits="6" />
|
|
<Bit Name="reg_gpio_5_i" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_4_i" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_3_i" Authority="RW" Bits="3" />
|
|
<Bit Name="reg_gpio_2_i" Authority="RW" Bits="2" />
|
|
<Bit Name="reg_gpio_1_i" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_0_i" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL31" Authority="RW" Address="0x40000184" Width="32" Description="GPIO_CFGCTL31." />
|
|
<Register Name="GPIO_CFGCTL32" Authority="RW" Address="0x40000188" Width="32" Description="GPIO_CFGCTL32.">
|
|
<Bit Name="reg_gpio_31_o" Authority="RW" Bits="31" />
|
|
<Bit Name="reg_gpio_30_o" Authority="RW" Bits="30" />
|
|
<Bit Name="reg_gpio_29_o" Authority="RW" Bits="29" />
|
|
<Bit Name="reg_gpio_28_o" Authority="RW" Bits="28" />
|
|
<Bit Name="reg_gpio_27_o" Authority="RW" Bits="27" />
|
|
<Bit Name="reg_gpio_26_o" Authority="RW" Bits="26" />
|
|
<Bit Name="reg_gpio_25_o" Authority="RW" Bits="25" />
|
|
<Bit Name="reg_gpio_24_o" Authority="RW" Bits="24" />
|
|
<Bit Name="reg_gpio_23_o" Authority="RW" Bits="23" />
|
|
<Bit Name="reg_gpio_22_o" Authority="RW" Bits="22" />
|
|
<Bit Name="reg_gpio_21_o" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_20_o" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_19_o" Authority="RW" Bits="19" />
|
|
<Bit Name="reg_gpio_18_o" Authority="RW" Bits="18" />
|
|
<Bit Name="reg_gpio_17_o" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_16_o" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_15_o" Authority="RW" Bits="15" />
|
|
<Bit Name="reg_gpio_14_o" Authority="RW" Bits="14" />
|
|
<Bit Name="reg_gpio_13_o" Authority="RW" Bits="13" />
|
|
<Bit Name="reg_gpio_12_o" Authority="RW" Bits="12" />
|
|
<Bit Name="reg_gpio_11_o" Authority="RW" Bits="11" />
|
|
<Bit Name="reg_gpio_10_o" Authority="RW" Bits="10" />
|
|
<Bit Name="reg_gpio_9_o" Authority="RW" Bits="9" />
|
|
<Bit Name="reg_gpio_8_o" Authority="RW" Bits="8" />
|
|
<Bit Name="reg_gpio_7_o" Authority="RW" Bits="7" />
|
|
<Bit Name="reg_gpio_6_o" Authority="RW" Bits="6" />
|
|
<Bit Name="reg_gpio_5_o" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_4_o" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_3_o" Authority="RW" Bits="3" />
|
|
<Bit Name="reg_gpio_2_o" Authority="RW" Bits="2" />
|
|
<Bit Name="reg_gpio_1_o" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_0_o" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL33" Authority="RW" Address="0x4000018C" Width="32" Description="GPIO_CFGCTL33." />
|
|
<Register Name="GPIO_CFGCTL34" Authority="RW" Address="0x40000190" Width="32" Description="GPIO_CFGCTL34.">
|
|
<Bit Name="reg_gpio_31_oe" Authority="RW" Bits="31" />
|
|
<Bit Name="reg_gpio_30_oe" Authority="RW" Bits="30" />
|
|
<Bit Name="reg_gpio_29_oe" Authority="RW" Bits="29" />
|
|
<Bit Name="reg_gpio_28_oe" Authority="RW" Bits="28" />
|
|
<Bit Name="reg_gpio_27_oe" Authority="RW" Bits="27" />
|
|
<Bit Name="reg_gpio_26_oe" Authority="RW" Bits="26" />
|
|
<Bit Name="reg_gpio_25_oe" Authority="RW" Bits="25" />
|
|
<Bit Name="reg_gpio_24_oe" Authority="RW" Bits="24" />
|
|
<Bit Name="reg_gpio_23_oe" Authority="RW" Bits="23" />
|
|
<Bit Name="reg_gpio_22_oe" Authority="RW" Bits="22" />
|
|
<Bit Name="reg_gpio_21_oe" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_gpio_20_oe" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_gpio_19_oe" Authority="RW" Bits="19" />
|
|
<Bit Name="reg_gpio_18_oe" Authority="RW" Bits="18" />
|
|
<Bit Name="reg_gpio_17_oe" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_gpio_16_oe" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_gpio_15_oe" Authority="RW" Bits="15" />
|
|
<Bit Name="reg_gpio_14_oe" Authority="RW" Bits="14" />
|
|
<Bit Name="reg_gpio_13_oe" Authority="RW" Bits="13" />
|
|
<Bit Name="reg_gpio_12_oe" Authority="RW" Bits="12" />
|
|
<Bit Name="reg_gpio_11_oe" Authority="RW" Bits="11" />
|
|
<Bit Name="reg_gpio_10_oe" Authority="RW" Bits="10" />
|
|
<Bit Name="reg_gpio_9_oe" Authority="RW" Bits="9" />
|
|
<Bit Name="reg_gpio_8_oe" Authority="RW" Bits="8" />
|
|
<Bit Name="reg_gpio_7_oe" Authority="RW" Bits="7" />
|
|
<Bit Name="reg_gpio_6_oe" Authority="RW" Bits="6" />
|
|
<Bit Name="reg_gpio_5_oe" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_gpio_4_oe" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_gpio_3_oe" Authority="RW" Bits="3" />
|
|
<Bit Name="reg_gpio_2_oe" Authority="RW" Bits="2" />
|
|
<Bit Name="reg_gpio_1_oe" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_gpio_0_oe" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="GPIO_CFGCTL35" Authority="RW" Address="0x40000194" Width="32" Description="GPIO_CFGCTL35." />
|
|
<Register Name="GPIO_INT_MASK1" Authority="RW" Address="0x400001A0" Width="32" Description="GPIO_INT_MASK1.">
|
|
<Bit Name="reg_gpio_int_mask1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="GPIO_INT_STAT1" Authority="RW" Address="0x400001A8" Width="32" Description="GPIO_INT_STAT1.">
|
|
<Bit Name="gpio_int_stat1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="GPIO_INT_CLR1" Authority="RW" Address="0x400001B0" Width="32" Description="GPIO_INT_CLR1.">
|
|
<Bit Name="reg_gpio_int_clr1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="GPIO_INT_MODE_SET1" Authority="RW" Address="0x400001C0" Width="32" Description="GPIO_INT_MODE_SET1.">
|
|
<Bit Name="reg_gpio_int_mode_set1" Authority="RW" Bits="29-0" />
|
|
</Register>
|
|
<Register Name="GPIO_INT_MODE_SET2" Authority="RW" Address="0x400001C4" Width="32" Description="GPIO_INT_MODE_SET2.">
|
|
<Bit Name="reg_gpio_int_mode_set2" Authority="RW" Bits="29-0" />
|
|
</Register>
|
|
<Register Name="GPIO_INT_MODE_SET3" Authority="RW" Address="0x400001C8" Width="32" Description="GPIO_INT_MODE_SET3.">
|
|
<Bit Name="reg_gpio_int_mode_set3" Authority="RW" Bits="29-0" />
|
|
</Register>
|
|
<Register Name="GPIO_INT_MODE_SET4" Authority="RW" Address="0x400001CC" Width="32" Description="GPIO_INT_MODE_SET4.">
|
|
<Bit Name="reg_gpio_int_mode_set4" Authority="RW" Bits="5-0" />
|
|
</Register>
|
|
<Register Name="GPIO_INT2_MASK1" Authority="RW" Address="0x400001D0" Width="32" Description="GPIO_INT2_MASK1.">
|
|
<Bit Name="reg_gpio_int2_mask1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="GPIO_INT2_STAT1" Authority="RW" Address="0x400001D4" Width="32" Description="GPIO_INT2_STAT1.">
|
|
<Bit Name="gpio_int2_stat1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="GPIO_INT2_CLR1" Authority="RW" Address="0x400001D8" Width="32" Description="GPIO_INT2_CLR1.">
|
|
<Bit Name="reg_gpio_int2_clr1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="GPIO_INT2_MODE_SET1" Authority="RW" Address="0x400001DC" Width="32" Description="GPIO_INT2_MODE_SET1.">
|
|
<Bit Name="reg_gpio_int2_mode_set1" Authority="RW" Bits="29-0" />
|
|
</Register>
|
|
<Register Name="GPIO_INT2_MODE_SET2" Authority="RW" Address="0x400001E0" Width="32" Description="GPIO_INT2_MODE_SET2.">
|
|
<Bit Name="reg_gpio_int2_mode_set2" Authority="RW" Bits="29-0" />
|
|
</Register>
|
|
<Register Name="GPIO_INT2_MODE_SET3" Authority="RW" Address="0x400001E4" Width="32" Description="GPIO_INT2_MODE_SET3.">
|
|
<Bit Name="reg_gpio_int2_mode_set3" Authority="RW" Bits="29-0" />
|
|
</Register>
|
|
<Register Name="GPIO_INT2_MODE_SET4" Authority="RW" Address="0x400001E8" Width="32" Description="GPIO_INT2_MODE_SET4.">
|
|
<Bit Name="reg_gpio_int2_mode_set4" Authority="RW" Bits="5-0" />
|
|
</Register>
|
|
<Register Name="dll" Authority="RW" Address="0x40000200" Width="32" Description="dll.">
|
|
<Bit Name="ppu_dll" Authority="RW" Bits="31" />
|
|
<Bit Name="pu_dll" Authority="RW" Bits="30" />
|
|
<Bit Name="dll_reset" Authority="RW" Bits="29" />
|
|
<Bit Name="dll_refclk_sel" Authority="RW" Bits="28" />
|
|
<Bit Name="dll_cp_hiz" Authority="RW" Bits="23" />
|
|
<Bit Name="dll_cp_op_en" Authority="RW" Bits="22" />
|
|
<Bit Name="dll_delay_sel" Authority="RW" Bits="21-20" />
|
|
<Bit Name="dll_post_div" Authority="RW" Bits="19-16" />
|
|
<Bit Name="dll_vctrl_force_en" Authority="RW" Bits="15" />
|
|
<Bit Name="dll_prechg_en" Authority="RW" Bits="14" />
|
|
<Bit Name="dll_prechg_reg" Authority="RW" Bits="13" />
|
|
<Bit Name="dll_prechg_sel" Authority="RW" Bits="12" />
|
|
<Bit Name="dll_vctrl_sel" Authority="RW" Bits="10-8" />
|
|
<Bit Name="dll_clk_57p6M_en" Authority="RW" Bits="7" />
|
|
<Bit Name="dll_clk_96M_en" Authority="RW" Bits="6" />
|
|
<Bit Name="dll_clk_144M_en" Authority="RW" Bits="5" />
|
|
<Bit Name="dll_clk_288M_en" Authority="RW" Bits="4" />
|
|
<Bit Name="dll_clk_mmdiv_en" Authority="RW" Bits="3" />
|
|
<Bit Name="ten_dll" Authority="RW" Bits="2" />
|
|
<Bit Name="dtest_en_dll_outclk" Authority="RW" Bits="1" />
|
|
<Bit Name="dtest_en_dll_refclk" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="led_driver" Authority="RW" Address="0x40000224" Width="32" Description="led_driver.">
|
|
<Bit Name="pu_leddrv" Authority="RW" Bits="31" />
|
|
<Bit Name="leddrv_out_en" Authority="RW" Bits="29-28" />
|
|
<Bit Name="ir_rx_gpio_sel" Authority="RW" Bits="11-8" />
|
|
<Bit Name="leddrv_ibias" Authority="RW" Bits="7-4" />
|
|
<Bit Name="led_din_polarity_sel" Authority="RW" Bits="2" />
|
|
<Bit Name="led_din_sel" Authority="RW" Bits="1" />
|
|
<Bit Name="led_din_reg" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="usb_xcvr" Authority="RW" Address="0x40000228" Width="32" Description="usb_xcvr.">
|
|
<Bit Name="usb_rcv" Authority="RW" Bits="27" />
|
|
<Bit Name="usb_vip" Authority="RW" Bits="26" />
|
|
<Bit Name="usb_vim" Authority="RW" Bits="25" />
|
|
<Bit Name="usb_bd" Authority="RW" Bits="24" />
|
|
<Bit Name="pu_usb" Authority="RW" Bits="23" />
|
|
<Bit Name="usb_sus" Authority="RW" Bits="22" />
|
|
<Bit Name="usb_spd" Authority="RW" Bits="21" />
|
|
<Bit Name="usb_enum" Authority="RW" Bits="20" />
|
|
<Bit Name="usb_data_convert" Authority="RW" Bits="16" />
|
|
<Bit Name="usb_oeb" Authority="RW" Bits="14" />
|
|
<Bit Name="usb_oeb_reg" Authority="RW" Bits="13" />
|
|
<Bit Name="usb_oeb_sel" Authority="RW" Bits="12" />
|
|
<Bit Name="usb_rout_pmos" Authority="RW" Bits="10-8" />
|
|
<Bit Name="usb_rout_nmos" Authority="RW" Bits="6-4" />
|
|
<Bit Name="pu_usb_ldo" Authority="RW" Bits="3" />
|
|
<Bit Name="usb_ldo_vfb" Authority="RW" Bits="2-0" />
|
|
</Register>
|
|
<Register Name="usb_xcvr_config" Authority="RW" Address="0x4000022C" Width="32" Description="usb_xcvr_config.">
|
|
<Bit Name="usb_slewrate_p_rise" Authority="RW" Bits="30-28" />
|
|
<Bit Name="usb_slewrate_p_fall" Authority="RW" Bits="26-24" />
|
|
<Bit Name="usb_slewrate_m_rise" Authority="RW" Bits="22-20" />
|
|
<Bit Name="usb_slewrate_m_fall" Authority="RW" Bits="18-16" />
|
|
<Bit Name="usb_res_pullup_tune" Authority="RW" Bits="14-12" />
|
|
<Bit Name="reg_usb_use_ctrl" Authority="RW" Bits="11" />
|
|
<Bit Name="usb_str_drv" Authority="RW" Bits="10-8" />
|
|
<Bit Name="reg_usb_use_xcvr" Authority="RW" Bits="7" />
|
|
<Bit Name="usb_bd_vth" Authority="RW" Bits="6-4" />
|
|
<Bit Name="usb_v_hys_p" Authority="RW" Bits="3-2" />
|
|
<Bit Name="usb_v_hys_m" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="gpdac_ctrl" Authority="RW" Address="0x40000308" Width="32" Description="gpdac_ctrl.">
|
|
<Bit Name="gpdac_reserved" Authority="RW" Bits="31-24" />
|
|
<Bit Name="gpdac_test_sel" Authority="RW" Bits="11-9" />
|
|
<Bit Name="gpdac_ref_sel" Authority="RW" Bits="8" />
|
|
<Bit Name="gpdac_test_en" Authority="RW" Bits="7" />
|
|
<Bit Name="gpdacb_rstn_ana" Authority="RW" Bits="1" />
|
|
<Bit Name="gpdaca_rstn_ana" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="gpdac_actrl" Authority="RW" Address="0x4000030C" Width="32" Description="gpdac_actrl.">
|
|
<Bit Name="gpdac_a_outmux" Authority="RW" Bits="22-20" />
|
|
<Bit Name="gpdac_a_rng" Authority="RW" Bits="19-18" />
|
|
<Bit Name="gpdac_ioa_en" Authority="RW" Bits="1" />
|
|
<Bit Name="gpdac_a_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="gpdac_bctrl" Authority="RW" Address="0x40000310" Width="32" Description="gpdac_bctrl.">
|
|
<Bit Name="gpdac_b_outmux" Authority="RW" Bits="22-20" />
|
|
<Bit Name="gpdac_b_rng" Authority="RW" Bits="19-18" />
|
|
<Bit Name="gpdac_iob_en" Authority="RW" Bits="1" />
|
|
<Bit Name="gpdac_b_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="gpdac_data" Authority="RW" Address="0x40000314" Width="32" Description="gpdac_data.">
|
|
<Bit Name="gpdac_a_data" Authority="RW" Bits="25-16" />
|
|
<Bit Name="gpdac_b_data" Authority="RW" Bits="9-0" />
|
|
</Register>
|
|
<Register Name="chip_revision" Authority="RW" Address="0x40000E00" Width="32" Description="chip_revision.">
|
|
<Bit Name="chip_rev" Authority="RW" Bits="3-0" />
|
|
</Register>
|
|
<Register Name="tzc_glb_ctrl_0" Authority="RW" Address="0x40000F00" Width="32" Description="tzc_glb_ctrl_0.">
|
|
<Bit Name="tzc_glb_clk_lock" Authority="RW" Bits="31" />
|
|
<Bit Name="tzc_glb_mbist_lock" Authority="RW" Bits="30" />
|
|
<Bit Name="tzc_glb_dbg_lock" Authority="RW" Bits="29" />
|
|
<Bit Name="tzc_glb_bmx_lock" Authority="RW" Bits="28" />
|
|
<Bit Name="tzc_glb_l2c_lock" Authority="RW" Bits="27" />
|
|
<Bit Name="tzc_glb_sram_lock" Authority="RW" Bits="26" />
|
|
<Bit Name="tzc_glb_misc_lock" Authority="RW" Bits="25" />
|
|
<Bit Name="tzc_glb_ctrl_ungated_ap_lock" Authority="RW" Bits="15" />
|
|
<Bit Name="tzc_glb_ctrl_sys_reset_lock" Authority="RW" Bits="14" />
|
|
<Bit Name="tzc_glb_ctrl_cpu_reset_lock" Authority="RW" Bits="13" />
|
|
<Bit Name="tzc_glb_ctrl_pwron_rst_lock" Authority="RW" Bits="12" />
|
|
<Bit Name="tzc_glb_swrst_s30_lock" Authority="RW" Bits="8" />
|
|
<Bit Name="tzc_glb_swrst_s01_lock" Authority="RW" Bits="1" />
|
|
<Bit Name="tzc_glb_swrst_s00_lock" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="tzc_glb_ctrl_1" Authority="RW" Address="0x40000F04" Width="32" Description="tzc_glb_ctrl_1.">
|
|
<Bit Name="tzc_glb_swrst_s1f_lock" Authority="RW" Bits="31" />
|
|
<Bit Name="tzc_glb_swrst_s1e_lock" Authority="RW" Bits="30" />
|
|
<Bit Name="tzc_glb_swrst_s1d_lock" Authority="RW" Bits="29" />
|
|
<Bit Name="tzc_glb_swrst_s1c_lock" Authority="RW" Bits="28" />
|
|
<Bit Name="tzc_glb_swrst_s1b_lock" Authority="RW" Bits="27" />
|
|
<Bit Name="tzc_glb_swrst_s1a_lock" Authority="RW" Bits="26" />
|
|
<Bit Name="tzc_glb_swrst_s19_lock" Authority="RW" Bits="25" />
|
|
<Bit Name="tzc_glb_swrst_s18_lock" Authority="RW" Bits="24" />
|
|
<Bit Name="tzc_glb_swrst_s17_lock" Authority="RW" Bits="23" />
|
|
<Bit Name="tzc_glb_swrst_s16_lock" Authority="RW" Bits="22" />
|
|
<Bit Name="tzc_glb_swrst_s15_lock" Authority="RW" Bits="21" />
|
|
<Bit Name="tzc_glb_swrst_s14_lock" Authority="RW" Bits="20" />
|
|
<Bit Name="tzc_glb_swrst_s13_lock" Authority="RW" Bits="19" />
|
|
<Bit Name="tzc_glb_swrst_s12_lock" Authority="RW" Bits="18" />
|
|
<Bit Name="tzc_glb_swrst_s11_lock" Authority="RW" Bits="17" />
|
|
<Bit Name="tzc_glb_swrst_s10_lock" Authority="RW" Bits="16" />
|
|
<Bit Name="tzc_glb_swrst_s2f_lock" Authority="RW" Bits="15" />
|
|
<Bit Name="tzc_glb_swrst_s2e_lock" Authority="RW" Bits="14" />
|
|
<Bit Name="tzc_glb_swrst_s2d_lock" Authority="RW" Bits="13" />
|
|
<Bit Name="tzc_glb_swrst_s2c_lock" Authority="RW" Bits="12" />
|
|
<Bit Name="tzc_glb_swrst_s2b_lock" Authority="RW" Bits="11" />
|
|
<Bit Name="tzc_glb_swrst_s2a_lock" Authority="RW" Bits="10" />
|
|
<Bit Name="tzc_glb_swrst_s29_lock" Authority="RW" Bits="9" />
|
|
<Bit Name="tzc_glb_swrst_s28_lock" Authority="RW" Bits="8" />
|
|
<Bit Name="tzc_glb_swrst_s27_lock" Authority="RW" Bits="7" />
|
|
<Bit Name="tzc_glb_swrst_s26_lock" Authority="RW" Bits="6" />
|
|
<Bit Name="tzc_glb_swrst_s25_lock" Authority="RW" Bits="5" />
|
|
<Bit Name="tzc_glb_swrst_s24_lock" Authority="RW" Bits="4" />
|
|
<Bit Name="tzc_glb_swrst_s23_lock" Authority="RW" Bits="3" />
|
|
<Bit Name="tzc_glb_swrst_s22_lock" Authority="RW" Bits="2" />
|
|
<Bit Name="tzc_glb_swrst_s21_lock" Authority="RW" Bits="1" />
|
|
<Bit Name="tzc_glb_swrst_s20_lock" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="tzc_glb_ctrl_2" Authority="RW" Address="0x40000F08" Width="32" Description="tzc_glb_ctrl_2.">
|
|
<Bit Name="tzc_glb_gpio_31_lock" Authority="RW" Bits="31" />
|
|
<Bit Name="tzc_glb_gpio_30_lock" Authority="RW" Bits="30" />
|
|
<Bit Name="tzc_glb_gpio_29_lock" Authority="RW" Bits="29" />
|
|
<Bit Name="tzc_glb_gpio_28_lock" Authority="RW" Bits="28" />
|
|
<Bit Name="tzc_glb_gpio_27_lock" Authority="RW" Bits="27" />
|
|
<Bit Name="tzc_glb_gpio_26_lock" Authority="RW" Bits="26" />
|
|
<Bit Name="tzc_glb_gpio_25_lock" Authority="RW" Bits="25" />
|
|
<Bit Name="tzc_glb_gpio_24_lock" Authority="RW" Bits="24" />
|
|
<Bit Name="tzc_glb_gpio_23_lock" Authority="RW" Bits="23" />
|
|
<Bit Name="tzc_glb_gpio_22_lock" Authority="RW" Bits="22" />
|
|
<Bit Name="tzc_glb_gpio_21_lock" Authority="RW" Bits="21" />
|
|
<Bit Name="tzc_glb_gpio_20_lock" Authority="RW" Bits="20" />
|
|
<Bit Name="tzc_glb_gpio_19_lock" Authority="RW" Bits="19" />
|
|
<Bit Name="tzc_glb_gpio_18_lock" Authority="RW" Bits="18" />
|
|
<Bit Name="tzc_glb_gpio_17_lock" Authority="RW" Bits="17" />
|
|
<Bit Name="tzc_glb_gpio_16_lock" Authority="RW" Bits="16" />
|
|
<Bit Name="tzc_glb_gpio_15_lock" Authority="RW" Bits="15" />
|
|
<Bit Name="tzc_glb_gpio_14_lock" Authority="RW" Bits="14" />
|
|
<Bit Name="tzc_glb_gpio_13_lock" Authority="RW" Bits="13" />
|
|
<Bit Name="tzc_glb_gpio_12_lock" Authority="RW" Bits="12" />
|
|
<Bit Name="tzc_glb_gpio_11_lock" Authority="RW" Bits="11" />
|
|
<Bit Name="tzc_glb_gpio_10_lock" Authority="RW" Bits="10" />
|
|
<Bit Name="tzc_glb_gpio_9_lock" Authority="RW" Bits="9" />
|
|
<Bit Name="tzc_glb_gpio_8_lock" Authority="RW" Bits="8" />
|
|
<Bit Name="tzc_glb_gpio_7_lock" Authority="RW" Bits="7" />
|
|
<Bit Name="tzc_glb_gpio_6_lock" Authority="RW" Bits="6" />
|
|
<Bit Name="tzc_glb_gpio_5_lock" Authority="RW" Bits="5" />
|
|
<Bit Name="tzc_glb_gpio_4_lock" Authority="RW" Bits="4" />
|
|
<Bit Name="tzc_glb_gpio_3_lock" Authority="RW" Bits="3" />
|
|
<Bit Name="tzc_glb_gpio_2_lock" Authority="RW" Bits="2" />
|
|
<Bit Name="tzc_glb_gpio_1_lock" Authority="RW" Bits="1" />
|
|
<Bit Name="tzc_glb_gpio_0_lock" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="tzc_glb_ctrl_3" Authority="RW" Address="0x40000F0C" Width="32" Description="tzc_glb_ctrl_3.">
|
|
<Bit Name="tzc_glb_gpio_37_lock" Authority="RW" Bits="5" />
|
|
<Bit Name="tzc_glb_gpio_36_lock" Authority="RW" Bits="4" />
|
|
<Bit Name="tzc_glb_gpio_35_lock" Authority="RW" Bits="3" />
|
|
<Bit Name="tzc_glb_gpio_34_lock" Authority="RW" Bits="2" />
|
|
<Bit Name="tzc_glb_gpio_33_lock" Authority="RW" Bits="1" />
|
|
<Bit Name="tzc_glb_gpio_32_lock" Authority="RW" Bits="0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="gpip">
|
|
<Register Name="gpadc_config" Authority="RW" Address="0x40002000" Width="32" Description="gpadc_config.">
|
|
<Bit Name="rsvd_31_24" Authority="RW" Bits="31-24" />
|
|
<Bit Name="gpadc_fifo_thl" Authority="RW" Bits="23-22" />
|
|
<Bit Name="gpadc_fifo_data_count" Authority="RW" Bits="21-16" />
|
|
<Bit Name="gpadc_fifo_rdy_mask" Authority="RW" Bits="15" />
|
|
<Bit Name="gpadc_fifo_underrun_mask" Authority="RW" Bits="14" />
|
|
<Bit Name="gpadc_fifo_overrun_mask" Authority="RW" Bits="13" />
|
|
<Bit Name="gpadc_rdy_mask" Authority="RW" Bits="12" />
|
|
<Bit Name="gpadc_fifo_underrun_clr" Authority="RW" Bits="10" />
|
|
<Bit Name="gpadc_fifo_overrun_clr" Authority="RW" Bits="9" />
|
|
<Bit Name="gpadc_rdy_clr" Authority="RW" Bits="8" />
|
|
<Bit Name="gpadc_fifo_rdy" Authority="RW" Bits="7" />
|
|
<Bit Name="gpadc_fifo_underrun" Authority="RW" Bits="6" />
|
|
<Bit Name="gpadc_fifo_overrun" Authority="RW" Bits="5" />
|
|
<Bit Name="gpadc_rdy" Authority="RW" Bits="4" />
|
|
<Bit Name="gpadc_fifo_full" Authority="RW" Bits="3" />
|
|
<Bit Name="gpadc_fifo_ne" Authority="RW" Bits="2" />
|
|
<Bit Name="gpadc_fifo_clr" Authority="RW" Bits="1" />
|
|
<Bit Name="gpadc_dma_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="gpadc_dma_rdata" Authority="RW" Address="0x40002004" Width="32" Description="gpadc_dma_rdata.">
|
|
<Bit Name="rsvd_31_26" Authority="RW" Bits="31-26" />
|
|
<Bit Name="gpadc_dma_rdata" Authority="RW" Bits="25-0" />
|
|
</Register>
|
|
<Register Name="gpdac_config" Authority="RW" Address="0x40002040" Width="32" Description="gpdac_config.">
|
|
<Bit Name="rsvd_31_24" Authority="RW" Bits="31-24" />
|
|
<Bit Name="gpdac_ch_b_sel" Authority="RW" Bits="23-20" />
|
|
<Bit Name="gpdac_ch_a_sel" Authority="RW" Bits="19-16" />
|
|
<Bit Name="gpdac_mode" Authority="RW" Bits="10-8" />
|
|
<Bit Name="dsm_mode" Authority="RW" Bits="5-4" />
|
|
<Bit Name="gpdac_en2" Authority="RW" Bits="1" />
|
|
<Bit Name="gpdac_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="gpdac_dma_config" Authority="RW" Address="0x40002044" Width="32" Description="gpdac_dma_config.">
|
|
<Bit Name="gpdac_dma_format" Authority="RW" Bits="5-4" />
|
|
<Bit Name="gpdac_dma_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="gpdac_dma_wdata" Authority="RW" Address="0x40002048" Width="32" Description="gpdac_dma_wdata.">
|
|
<Bit Name="gpdac_dma_wdata" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="gpdac_tx_fifo_status" Authority="RW" Address="0x40002x4C" Width="32" Description="gpdac_tx_fifo_status.">
|
|
<Bit Name="TxFifoWrPtr" Authority="RW" Bits="9-8" />
|
|
<Bit Name="TxFifoRdPtr" Authority="RW" Bits="6-4" />
|
|
<Bit Name="tx_cs" Authority="RW" Bits="3-2" />
|
|
<Bit Name="tx_fifo_full" Authority="RW" Bits="1" />
|
|
<Bit Name="tx_fifo_empty" Authority="RW" Bits="0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="sec_dbg">
|
|
<Register Name="sd_chip_id_low" Authority="RW" Address="0x40003000" Width="32" Description="sd_chip_id_low.">
|
|
<Bit Name="sd_chip_id_low" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sd_chip_id_high" Authority="RW" Address="0x40003004" Width="32" Description="sd_chip_id_high.">
|
|
<Bit Name="sd_chip_id_high" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sd_wifi_mac_low" Authority="RW" Address="0x40003008" Width="32" Description="sd_wifi_mac_low.">
|
|
<Bit Name="sd_wifi_mac_low" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sd_wifi_mac_high" Authority="RW" Address="0x4000300C" Width="32" Description="sd_wifi_mac_high.">
|
|
<Bit Name="sd_wifi_mac_high" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sd_dbg_pwd_low" Authority="RW" Address="0x40003010" Width="32" Description="sd_dbg_pwd_low.">
|
|
<Bit Name="sd_dbg_pwd_low" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sd_dbg_pwd_high" Authority="RW" Address="0x40003014" Width="32" Description="sd_dbg_pwd_high.">
|
|
<Bit Name="sd_dbg_pwd_high" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sd_status" Authority="RW" Address="0x40003018" Width="32" Description="sd_status.">
|
|
<Bit Name="sd_dbg_ena" Authority="RW" Bits="31-28" />
|
|
<Bit Name="sd_dbg_mode" Authority="RW" Bits="27-24" />
|
|
<Bit Name="sd_dbg_pwd_cnt" Authority="RW" Bits="23-4" />
|
|
<Bit Name="sd_dbg_cci_clk_sel" Authority="RW" Bits="3" />
|
|
<Bit Name="sd_dbg_cci_read_en" Authority="RW" Bits="2" />
|
|
<Bit Name="sd_dbg_pwd_trig" Authority="RW" Bits="1" />
|
|
<Bit Name="sd_dbg_pwd_busy" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="sd_dbg_reserved" Authority="RW" Address="0x4000301C" Width="32" Description="sd_dbg_reserved.">
|
|
<Bit Name="sd_dbg_reserved" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="sec_eng">
|
|
<Register Name="se_sha_0_ctrl" Authority="RW" Address="0x40004000" Width="32" Description="se_sha_0_ctrl.">
|
|
<Bit Name="se_sha_0_msg_len" Authority="RW" Bits="31-16" />
|
|
<Bit Name="se_sha_0_link_mode" Authority="RW" Bits="15" />
|
|
<Bit Name="se_sha_0_int_mask" Authority="RW" Bits="11" />
|
|
<Bit Name="se_sha_0_int_set_1t" Authority="RW" Bits="10" />
|
|
<Bit Name="se_sha_0_int_clr_1t" Authority="RW" Bits="9" />
|
|
<Bit Name="se_sha_0_int" Authority="RW" Bits="8" />
|
|
<Bit Name="se_sha_0_hash_sel" Authority="RW" Bits="6" />
|
|
<Bit Name="se_sha_0_en" Authority="RW" Bits="5" />
|
|
<Bit Name="se_sha_0_mode" Authority="RW" Bits="4-2" />
|
|
<Bit Name="se_sha_0_trig_1t" Authority="RW" Bits="1" />
|
|
<Bit Name="se_sha_0_busy" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_msa" Authority="RW" Address="0x40004004" Width="32" Description="se_sha_0_msa.">
|
|
<Bit Name="se_sha_0_msa" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_status" Authority="RW" Address="0x40004008" Width="32" Description="se_sha_0_status.">
|
|
<Bit Name="se_sha_0_status" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_endian" Authority="RW" Address="0x4000400C" Width="32" Description="se_sha_0_endian.">
|
|
<Bit Name="se_sha_0_dout_endian" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_l_0" Authority="RW" Address="0x40004010" Width="32" Description="se_sha_0_hash_l_0.">
|
|
<Bit Name="se_sha_0_hash_l_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_l_1" Authority="RW" Address="0x40004014" Width="32" Description="se_sha_0_hash_l_1.">
|
|
<Bit Name="se_sha_0_hash_l_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_l_2" Authority="RW" Address="0x40004018" Width="32" Description="se_sha_0_hash_l_2.">
|
|
<Bit Name="se_sha_0_hash_l_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_l_3" Authority="RW" Address="0x4000401C" Width="32" Description="se_sha_0_hash_l_3.">
|
|
<Bit Name="se_sha_0_hash_l_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_l_4" Authority="RW" Address="0x40004020" Width="32" Description="se_sha_0_hash_l_4.">
|
|
<Bit Name="se_sha_0_hash_l_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_l_5" Authority="RW" Address="0x40004024" Width="32" Description="se_sha_0_hash_l_5.">
|
|
<Bit Name="se_sha_0_hash_l_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_l_6" Authority="RW" Address="0x40004028" Width="32" Description="se_sha_0_hash_l_6.">
|
|
<Bit Name="se_sha_0_hash_l_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_l_7" Authority="RW" Address="0x40004x2C" Width="32" Description="se_sha_0_hash_l_7.">
|
|
<Bit Name="se_sha_0_hash_l_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_h_0" Authority="RW" Address="0x40004030" Width="32" Description="se_sha_0_hash_h_0.">
|
|
<Bit Name="se_sha_0_hash_h_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_h_1" Authority="RW" Address="0x40004034" Width="32" Description="se_sha_0_hash_h_1.">
|
|
<Bit Name="se_sha_0_hash_h_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_h_2" Authority="RW" Address="0x40004038" Width="32" Description="se_sha_0_hash_h_2.">
|
|
<Bit Name="se_sha_0_hash_h_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_h_3" Authority="RW" Address="0x40004x3C" Width="32" Description="se_sha_0_hash_h_3.">
|
|
<Bit Name="se_sha_0_hash_h_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_h_4" Authority="RW" Address="0x40004040" Width="32" Description="se_sha_0_hash_h_4.">
|
|
<Bit Name="se_sha_0_hash_h_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_h_5" Authority="RW" Address="0x40004044" Width="32" Description="se_sha_0_hash_h_5.">
|
|
<Bit Name="se_sha_0_hash_h_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_h_6" Authority="RW" Address="0x40004048" Width="32" Description="se_sha_0_hash_h_6.">
|
|
<Bit Name="se_sha_0_hash_h_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_hash_h_7" Authority="RW" Address="0x40004x4C" Width="32" Description="se_sha_0_hash_h_7.">
|
|
<Bit Name="se_sha_0_hash_h_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_link" Authority="RW" Address="0x40004050" Width="32" Description="se_sha_0_link.">
|
|
<Bit Name="se_sha_0_lca" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_sha_0_ctrl_prot" Authority="RW" Address="0x400040FC" Width="32" Description="se_sha_0_ctrl_prot.">
|
|
<Bit Name="se_sha_id1_en" Authority="RW" Bits="2" />
|
|
<Bit Name="se_sha_id0_en" Authority="RW" Bits="1" />
|
|
<Bit Name="se_sha_prot_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_ctrl" Authority="RW" Address="0x40004100" Width="32" Description="se_aes_0_ctrl.">
|
|
<Bit Name="se_aes_0_msg_len" Authority="RW" Bits="31-16" />
|
|
<Bit Name="se_aes_0_link_mode" Authority="RW" Bits="15" />
|
|
<Bit Name="se_aes_0_iv_sel" Authority="RW" Bits="14" />
|
|
<Bit Name="se_aes_0_block_mode" Authority="RW" Bits="13-12" />
|
|
<Bit Name="se_aes_0_int_mask" Authority="RW" Bits="11" />
|
|
<Bit Name="se_aes_0_int_set_1t" Authority="RW" Bits="10" />
|
|
<Bit Name="se_aes_0_int_clr_1t" Authority="RW" Bits="9" />
|
|
<Bit Name="se_aes_0_int" Authority="RW" Bits="8" />
|
|
<Bit Name="se_aes_0_hw_key_en" Authority="RW" Bits="7" />
|
|
<Bit Name="se_aes_0_dec_key_sel" Authority="RW" Bits="6" />
|
|
<Bit Name="se_aes_0_dec_en" Authority="RW" Bits="5" />
|
|
<Bit Name="se_aes_0_mode" Authority="RW" Bits="4-3" />
|
|
<Bit Name="se_aes_0_en" Authority="RW" Bits="2" />
|
|
<Bit Name="se_aes_0_trig_1t" Authority="RW" Bits="1" />
|
|
<Bit Name="se_aes_0_busy" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_msa" Authority="RW" Address="0x40004104" Width="32" Description="se_aes_0_msa.">
|
|
<Bit Name="se_aes_0_msa" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_mda" Authority="RW" Address="0x40004108" Width="32" Description="se_aes_0_mda.">
|
|
<Bit Name="se_aes_0_mda" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_status" Authority="RW" Address="0x4000410C" Width="32" Description="se_aes_0_status.">
|
|
<Bit Name="se_aes_0_status" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_iv_0" Authority="RW" Address="0x40004110" Width="32" Description="se_aes_0_iv_0.">
|
|
<Bit Name="se_aes_0_iv_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_iv_1" Authority="RW" Address="0x40004114" Width="32" Description="se_aes_0_iv_1.">
|
|
<Bit Name="se_aes_0_iv_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_iv_2" Authority="RW" Address="0x40004118" Width="32" Description="se_aes_0_iv_2.">
|
|
<Bit Name="se_aes_0_iv_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_iv_3" Authority="RW" Address="0x4000411C" Width="32" Description="se_aes_0_iv_3.">
|
|
<Bit Name="se_aes_0_iv_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_key_0" Authority="RW" Address="0x40004120" Width="32" Description="se_aes_0_key_0.">
|
|
<Bit Name="se_aes_0_key_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_key_1" Authority="RW" Address="0x40004124" Width="32" Description="se_aes_0_key_1.">
|
|
<Bit Name="se_aes_0_key_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_key_2" Authority="RW" Address="0x40004128" Width="32" Description="se_aes_0_key_2.">
|
|
<Bit Name="se_aes_0_key_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_key_3" Authority="RW" Address="0x4000412C" Width="32" Description="se_aes_0_key_3.">
|
|
<Bit Name="se_aes_0_key_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_key_4" Authority="RW" Address="0x40004130" Width="32" Description="se_aes_0_key_4.">
|
|
<Bit Name="se_aes_0_key_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_key_5" Authority="RW" Address="0x40004134" Width="32" Description="se_aes_0_key_5.">
|
|
<Bit Name="se_aes_0_key_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_key_6" Authority="RW" Address="0x40004138" Width="32" Description="se_aes_0_key_6.">
|
|
<Bit Name="se_aes_0_key_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_key_7" Authority="RW" Address="0x4000413C" Width="32" Description="se_aes_0_key_7.">
|
|
<Bit Name="se_aes_0_key_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_key_sel_0" Authority="RW" Address="0x40004140" Width="32" Description="se_aes_0_key_sel_0.">
|
|
<Bit Name="se_aes_0_key_sel_0" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_key_sel_1" Authority="RW" Address="0x40004144" Width="32" Description="se_aes_0_key_sel_1.">
|
|
<Bit Name="se_aes_0_key_sel_1" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_endian" Authority="RW" Address="0x40004148" Width="32" Description="se_aes_0_endian.">
|
|
<Bit Name="se_aes_0_ctr_len" Authority="RW" Bits="31-30" />
|
|
<Bit Name="se_aes_0_iv_endian" Authority="RW" Bits="3" />
|
|
<Bit Name="se_aes_0_key_endian" Authority="RW" Bits="2" />
|
|
<Bit Name="se_aes_0_din_endian" Authority="RW" Bits="1" />
|
|
<Bit Name="se_aes_0_dout_endian" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_sboot" Authority="RW" Address="0x4000414C" Width="32" Description="se_aes_0_sboot.">
|
|
<Bit Name="se_aes_0_sboot_key_sel" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_link" Authority="RW" Address="0x40004150" Width="32" Description="se_aes_0_link.">
|
|
<Bit Name="se_aes_0_lca" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_aes_0_ctrl_prot" Authority="RW" Address="0x400041FC" Width="32" Description="se_aes_0_ctrl_prot.">
|
|
<Bit Name="se_aes_id1_en" Authority="RW" Bits="2" />
|
|
<Bit Name="se_aes_id0_en" Authority="RW" Bits="1" />
|
|
<Bit Name="se_aes_prot_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_ctrl_0" Authority="RW" Address="0x40004200" Width="32" Description="se_trng_0_ctrl_0.">
|
|
<Bit Name="se_trng_0_manual_en" Authority="RW" Bits="15" />
|
|
<Bit Name="se_trng_0_manual_reseed" Authority="RW" Bits="14" />
|
|
<Bit Name="se_trng_0_manual_fun_sel" Authority="RW" Bits="13" />
|
|
<Bit Name="se_trng_0_int_mask" Authority="RW" Bits="11" />
|
|
<Bit Name="se_trng_0_int_set_1t" Authority="RW" Bits="10" />
|
|
<Bit Name="se_trng_0_int_clr_1t" Authority="RW" Bits="9" />
|
|
<Bit Name="se_trng_0_int" Authority="RW" Bits="8" />
|
|
<Bit Name="se_trng_0_ht_error" Authority="RW" Bits="4" />
|
|
<Bit Name="se_trng_0_dout_clr_1t" Authority="RW" Bits="3" />
|
|
<Bit Name="se_trng_0_en" Authority="RW" Bits="2" />
|
|
<Bit Name="se_trng_0_trig_1t" Authority="RW" Bits="1" />
|
|
<Bit Name="se_trng_0_busy" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_status" Authority="RW" Address="0x40004204" Width="32" Description="se_trng_0_status.">
|
|
<Bit Name="se_trng_0_status" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_dout_0" Authority="RW" Address="0x40004208" Width="32" Description="se_trng_0_dout_0.">
|
|
<Bit Name="se_trng_0_dout_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_dout_1" Authority="RW" Address="0x4000420C" Width="32" Description="se_trng_0_dout_1.">
|
|
<Bit Name="se_trng_0_dout_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_dout_2" Authority="RW" Address="0x40004210" Width="32" Description="se_trng_0_dout_2.">
|
|
<Bit Name="se_trng_0_dout_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_dout_3" Authority="RW" Address="0x40004214" Width="32" Description="se_trng_0_dout_3.">
|
|
<Bit Name="se_trng_0_dout_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_dout_4" Authority="RW" Address="0x40004218" Width="32" Description="se_trng_0_dout_4.">
|
|
<Bit Name="se_trng_0_dout_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_dout_5" Authority="RW" Address="0x4000421C" Width="32" Description="se_trng_0_dout_5.">
|
|
<Bit Name="se_trng_0_dout_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_dout_6" Authority="RW" Address="0x40004220" Width="32" Description="se_trng_0_dout_6.">
|
|
<Bit Name="se_trng_0_dout_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_dout_7" Authority="RW" Address="0x40004224" Width="32" Description="se_trng_0_dout_7.">
|
|
<Bit Name="se_trng_0_dout_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_test" Authority="RW" Address="0x40004228" Width="32" Description="se_trng_0_test.">
|
|
<Bit Name="se_trng_0_ht_alarm_n" Authority="RW" Bits="11-4" />
|
|
<Bit Name="se_trng_0_ht_dis" Authority="RW" Bits="3" />
|
|
<Bit Name="se_trng_0_cp_bypass" Authority="RW" Bits="2" />
|
|
<Bit Name="se_trng_0_cp_test_en" Authority="RW" Bits="1" />
|
|
<Bit Name="se_trng_0_test_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_ctrl_1" Authority="RW" Address="0x4000422C" Width="32" Description="se_trng_0_ctrl_1.">
|
|
<Bit Name="se_trng_0_reseed_n_lsb" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_ctrl_2" Authority="RW" Address="0x40004230" Width="32" Description="se_trng_0_ctrl_2.">
|
|
<Bit Name="se_trng_0_reseed_n_msb" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_ctrl_3" Authority="RW" Address="0x40004234" Width="32" Description="se_trng_0_ctrl_3.">
|
|
<Bit Name="se_trng_0_rosc_en" Authority="RW" Bits="31" />
|
|
<Bit Name="se_trng_0_ht_od_en" Authority="RW" Bits="26" />
|
|
<Bit Name="se_trng_0_ht_apt_c" Authority="RW" Bits="25-16" />
|
|
<Bit Name="se_trng_0_ht_rct_c" Authority="RW" Bits="15-8" />
|
|
<Bit Name="se_trng_0_cp_ratio" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_test_out_0" Authority="RW" Address="0x40004240" Width="32" Description="se_trng_0_test_out_0.">
|
|
<Bit Name="se_trng_0_test_out_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_test_out_1" Authority="RW" Address="0x40004244" Width="32" Description="se_trng_0_test_out_1.">
|
|
<Bit Name="se_trng_0_test_out_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_test_out_2" Authority="RW" Address="0x40004248" Width="32" Description="se_trng_0_test_out_2.">
|
|
<Bit Name="se_trng_0_test_out_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_test_out_3" Authority="RW" Address="0x4000424C" Width="32" Description="se_trng_0_test_out_3.">
|
|
<Bit Name="se_trng_0_test_out_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_trng_0_ctrl_prot" Authority="RW" Address="0x400042FC" Width="32" Description="se_trng_0_ctrl_prot.">
|
|
<Bit Name="se_trng_id1_en" Authority="RW" Bits="2" />
|
|
<Bit Name="se_trng_id0_en" Authority="RW" Bits="1" />
|
|
<Bit Name="se_trng_prot_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_pka_0_ctrl_0" Authority="RW" Address="0x40004300" Width="32" Description="se_pka_0_ctrl_0.">
|
|
<Bit Name="se_pka_0_status" Authority="RW" Bits="31-16" />
|
|
<Bit Name="se_pka_0_status_clr_1t" Authority="RW" Bits="15" />
|
|
<Bit Name="se_pka_0_ram_clr_md" Authority="RW" Bits="13" />
|
|
<Bit Name="se_pka_0_endian" Authority="RW" Bits="12" />
|
|
<Bit Name="se_pka_0_int_mask" Authority="RW" Bits="11" />
|
|
<Bit Name="se_pka_0_int_set" Authority="RW" Bits="10" />
|
|
<Bit Name="se_pka_0_int_clr_1t" Authority="RW" Bits="9" />
|
|
<Bit Name="se_pka_0_int" Authority="RW" Bits="8" />
|
|
<Bit Name="se_pka_0_prot_md" Authority="RW" Bits="7-4" />
|
|
<Bit Name="se_pka_0_en" Authority="RW" Bits="3" />
|
|
<Bit Name="se_pka_0_busy" Authority="RW" Bits="2" />
|
|
<Bit Name="se_pka_0_done_clr_1t" Authority="RW" Bits="1" />
|
|
<Bit Name="se_pka_0_done" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_pka_0_seed" Authority="RW" Address="0x4000430C" Width="32" Description="se_pka_0_seed.">
|
|
<Bit Name="se_pka_0_seed" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_pka_0_ctrl_1" Authority="RW" Address="0x40004310" Width="32" Description="se_pka_0_ctrl_1.">
|
|
<Bit Name="se_pka_0_hbypass" Authority="RW" Bits="3" />
|
|
<Bit Name="se_pka_0_hburst" Authority="RW" Bits="2-0" />
|
|
</Register>
|
|
<Register Name="se_pka_0_rw" Authority="RW" Address="0x40004340" Width="32" Description="se_pka_0_rw." />
|
|
<Register Name="se_pka_0_rw_burst" Authority="RW" Address="0x40004360" Width="32" Description="se_pka_0_rw_burst." />
|
|
<Register Name="se_pka_0_ctrl_prot" Authority="RW" Address="0x400043FC" Width="32" Description="se_pka_0_ctrl_prot.">
|
|
<Bit Name="se_pka_id1_en" Authority="RW" Bits="2" />
|
|
<Bit Name="se_pka_id0_en" Authority="RW" Bits="1" />
|
|
<Bit Name="se_pka_prot_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_cdet_0_ctrl_0" Authority="RW" Address="0x40004400" Width="32" Description="se_cdet_0_ctrl_0.">
|
|
<Bit Name="se_cdet_0_g_loop_min" Authority="RW" Bits="31-24" />
|
|
<Bit Name="se_cdet_0_g_loop_max" Authority="RW" Bits="23-16" />
|
|
<Bit Name="se_cdet_0_status" Authority="RW" Bits="15-2" />
|
|
<Bit Name="se_cdet_0_error" Authority="RW" Bits="1" />
|
|
<Bit Name="se_cdet_0_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_cdet_0_ctrl_1" Authority="RW" Address="0x40004404" Width="32" Description="se_cdet_0_ctrl_1.">
|
|
<Bit Name="se_cdet_0_g_slp_n" Authority="RW" Bits="23-16" />
|
|
<Bit Name="se_cdet_0_t_dly_n" Authority="RW" Bits="15-8" />
|
|
<Bit Name="se_cdet_0_t_loop_n" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="se_cdet_0_ctrl_prot" Authority="RW" Address="0x400044FC" Width="32" Description="se_cdet_0_ctrl_prot.">
|
|
<Bit Name="se_cdet_id1_en" Authority="RW" Bits="2" />
|
|
<Bit Name="se_cdet_id0_en" Authority="RW" Bits="1" />
|
|
<Bit Name="se_cdet_prot_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_gmac_0_ctrl_0" Authority="RW" Address="0x40004500" Width="32" Description="se_gmac_0_ctrl_0.">
|
|
<Bit Name="se_gmac_0_x_endian" Authority="RW" Bits="14" />
|
|
<Bit Name="se_gmac_0_h_endian" Authority="RW" Bits="13" />
|
|
<Bit Name="se_gmac_0_t_endian" Authority="RW" Bits="12" />
|
|
<Bit Name="se_gmac_0_int_mask" Authority="RW" Bits="11" />
|
|
<Bit Name="se_gmac_0_int_set_1t" Authority="RW" Bits="10" />
|
|
<Bit Name="se_gmac_0_int_clr_1t" Authority="RW" Bits="9" />
|
|
<Bit Name="se_gmac_0_int" Authority="RW" Bits="8" />
|
|
<Bit Name="se_gmac_0_en" Authority="RW" Bits="2" />
|
|
<Bit Name="se_gmac_0_trig_1t" Authority="RW" Bits="1" />
|
|
<Bit Name="se_gmac_0_busy" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_gmac_0_lca" Authority="RW" Address="0x40004504" Width="32" Description="se_gmac_0_lca.">
|
|
<Bit Name="se_gmac_0_lca" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_gmac_0_status" Authority="RW" Address="0x40004508" Width="32" Description="se_gmac_0_status.">
|
|
<Bit Name="se_gmac_0_status" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_gmac_0_ctrl_prot" Authority="RW" Address="0x400045FC" Width="32" Description="se_gmac_0_ctrl_prot.">
|
|
<Bit Name="se_gmac_id1_en" Authority="RW" Bits="2" />
|
|
<Bit Name="se_gmac_id0_en" Authority="RW" Bits="1" />
|
|
<Bit Name="se_gmac_prot_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_ctrl_prot_rd" Authority="RW" Address="0x40004F00" Width="32" Description="se_ctrl_prot_rd.">
|
|
<Bit Name="se_dbg_dis" Authority="RW" Bits="31" />
|
|
<Bit Name="se_gmac_id1_en_rd" Authority="RW" Bits="22" />
|
|
<Bit Name="se_gmac_id0_en_rd" Authority="RW" Bits="21" />
|
|
<Bit Name="se_gmac_prot_en_rd" Authority="RW" Bits="20" />
|
|
<Bit Name="se_cdet_id1_en_rd" Authority="RW" Bits="18" />
|
|
<Bit Name="se_cdet_id0_en_rd" Authority="RW" Bits="17" />
|
|
<Bit Name="se_cdet_prot_en_rd" Authority="RW" Bits="16" />
|
|
<Bit Name="se_pka_id1_en_rd" Authority="RW" Bits="14" />
|
|
<Bit Name="se_pka_id0_en_rd" Authority="RW" Bits="13" />
|
|
<Bit Name="se_pka_prot_en_rd" Authority="RW" Bits="12" />
|
|
<Bit Name="se_trng_id1_en_rd" Authority="RW" Bits="10" />
|
|
<Bit Name="se_trng_id0_en_rd" Authority="RW" Bits="9" />
|
|
<Bit Name="se_trng_prot_en_rd" Authority="RW" Bits="8" />
|
|
<Bit Name="se_aes_id1_en_rd" Authority="RW" Bits="6" />
|
|
<Bit Name="se_aes_id0_en_rd" Authority="RW" Bits="5" />
|
|
<Bit Name="se_aes_prot_en_rd" Authority="RW" Bits="4" />
|
|
<Bit Name="se_sha_id1_en_rd" Authority="RW" Bits="2" />
|
|
<Bit Name="se_sha_id0_en_rd" Authority="RW" Bits="1" />
|
|
<Bit Name="se_sha_prot_en_rd" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="se_ctrl_reserved_0" Authority="RW" Address="0x40004F04" Width="32" Description="se_ctrl_reserved_0.">
|
|
<Bit Name="se_ctrl_reserved_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_ctrl_reserved_1" Authority="RW" Address="0x40004F08" Width="32" Description="se_ctrl_reserved_1.">
|
|
<Bit Name="se_ctrl_reserved_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="se_ctrl_reserved_2" Authority="RW" Address="0x40004F0C" Width="32" Description="se_ctrl_reserved_2.">
|
|
<Bit Name="se_ctrl_reserved_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="tzc_sec">
|
|
<Register Name="tzc_rom_ctrl" Authority="RW" Address="0x40005040" Width="32" Description="tzc_rom_ctrl.">
|
|
<Bit Name="tzc_sboot_done" Authority="RW" Bits="31-28" />
|
|
<Bit Name="tzc_rom1_r1_lock" Authority="RW" Bits="27" />
|
|
<Bit Name="tzc_rom1_r0_lock" Authority="RW" Bits="26" />
|
|
<Bit Name="tzc_rom0_r1_lock" Authority="RW" Bits="25" />
|
|
<Bit Name="tzc_rom0_r0_lock" Authority="RW" Bits="24" />
|
|
<Bit Name="tzc_rom1_r1_en" Authority="RW" Bits="19" />
|
|
<Bit Name="tzc_rom1_r0_en" Authority="RW" Bits="18" />
|
|
<Bit Name="tzc_rom0_r1_en" Authority="RW" Bits="17" />
|
|
<Bit Name="tzc_rom0_r0_en" Authority="RW" Bits="16" />
|
|
<Bit Name="tzc_rom1_r1_id1_en" Authority="RW" Bits="11" />
|
|
<Bit Name="tzc_rom1_r0_id1_en" Authority="RW" Bits="10" />
|
|
<Bit Name="tzc_rom0_r1_id1_en" Authority="RW" Bits="9" />
|
|
<Bit Name="tzc_rom0_r0_id1_en" Authority="RW" Bits="8" />
|
|
<Bit Name="tzc_rom1_r1_id0_en" Authority="RW" Bits="3" />
|
|
<Bit Name="tzc_rom1_r0_id0_en" Authority="RW" Bits="2" />
|
|
<Bit Name="tzc_rom0_r1_id0_en" Authority="RW" Bits="1" />
|
|
<Bit Name="tzc_rom0_r0_id0_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="tzc_rom0_r0" Authority="RW" Address="0x40005044" Width="32" Description="tzc_rom0_r0.">
|
|
<Bit Name="tzc_rom0_r0_start" Authority="RW" Bits="31-16" />
|
|
<Bit Name="tzc_rom0_r0_end" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="tzc_rom0_r1" Authority="RW" Address="0x40005048" Width="32" Description="tzc_rom0_r1.">
|
|
<Bit Name="tzc_rom0_r1_start" Authority="RW" Bits="31-16" />
|
|
<Bit Name="tzc_rom0_r1_end" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="tzc_rom1_r0" Authority="RW" Address="0x40005x4C" Width="32" Description="tzc_rom1_r0.">
|
|
<Bit Name="tzc_rom1_r0_start" Authority="RW" Bits="31-16" />
|
|
<Bit Name="tzc_rom1_r0_end" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="tzc_rom1_r1" Authority="RW" Address="0x40005050" Width="32" Description="tzc_rom1_r1.">
|
|
<Bit Name="tzc_rom1_r1_start" Authority="RW" Bits="31-16" />
|
|
<Bit Name="tzc_rom1_r1_end" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="tzc_nsec">
|
|
<Register Name="tzc_rom_ctrl" Authority="RW" Address="0x40006040" Width="32" Description="tzc_rom_ctrl.">
|
|
<Bit Name="tzc_sboot_done" Authority="RW" Bits="31-28" />
|
|
<Bit Name="tzc_rom1_r1_lock" Authority="RW" Bits="27" />
|
|
<Bit Name="tzc_rom1_r0_lock" Authority="RW" Bits="26" />
|
|
<Bit Name="tzc_rom0_r1_lock" Authority="RW" Bits="25" />
|
|
<Bit Name="tzc_rom0_r0_lock" Authority="RW" Bits="24" />
|
|
<Bit Name="tzc_rom1_r1_en" Authority="RW" Bits="19" />
|
|
<Bit Name="tzc_rom1_r0_en" Authority="RW" Bits="18" />
|
|
<Bit Name="tzc_rom0_r1_en" Authority="RW" Bits="17" />
|
|
<Bit Name="tzc_rom0_r0_en" Authority="RW" Bits="16" />
|
|
<Bit Name="tzc_rom1_r1_id1_en" Authority="RW" Bits="11" />
|
|
<Bit Name="tzc_rom1_r0_id1_en" Authority="RW" Bits="10" />
|
|
<Bit Name="tzc_rom0_r1_id1_en" Authority="RW" Bits="9" />
|
|
<Bit Name="tzc_rom0_r0_id1_en" Authority="RW" Bits="8" />
|
|
<Bit Name="tzc_rom1_r1_id0_en" Authority="RW" Bits="3" />
|
|
<Bit Name="tzc_rom1_r0_id0_en" Authority="RW" Bits="2" />
|
|
<Bit Name="tzc_rom0_r1_id0_en" Authority="RW" Bits="1" />
|
|
<Bit Name="tzc_rom0_r0_id0_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="tzc_rom0_r0" Authority="RW" Address="0x40006044" Width="32" Description="tzc_rom0_r0.">
|
|
<Bit Name="tzc_rom0_r0_start" Authority="RW" Bits="31-16" />
|
|
<Bit Name="tzc_rom0_r0_end" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="tzc_rom0_r1" Authority="RW" Address="0x40006048" Width="32" Description="tzc_rom0_r1.">
|
|
<Bit Name="tzc_rom0_r1_start" Authority="RW" Bits="31-16" />
|
|
<Bit Name="tzc_rom0_r1_end" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="tzc_rom1_r0" Authority="RW" Address="0x40006x4C" Width="32" Description="tzc_rom1_r0.">
|
|
<Bit Name="tzc_rom1_r0_start" Authority="RW" Bits="31-16" />
|
|
<Bit Name="tzc_rom1_r0_end" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="tzc_rom1_r1" Authority="RW" Address="0x40006050" Width="32" Description="tzc_rom1_r1.">
|
|
<Bit Name="tzc_rom1_r1_start" Authority="RW" Bits="31-16" />
|
|
<Bit Name="tzc_rom1_r1_end" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="ef_data_0">
|
|
<Register Name="ef_cfg_0" Authority="RW" Address="0x40007000" Width="32" Description="ef_cfg_0.">
|
|
<Bit Name="ef_dbg_mode" Authority="RW" Bits="31-28" />
|
|
<Bit Name="ef_dbg_jtag_0_dis" Authority="RW" Bits="27-26" />
|
|
<Bit Name="ef_dbg_jtag_1_dis" Authority="RW" Bits="25-24" />
|
|
<Bit Name="ef_efuse_dbg_dis" Authority="RW" Bits="23" />
|
|
<Bit Name="ef_se_dbg_dis" Authority="RW" Bits="22" />
|
|
<Bit Name="ef_cpu_rst_dbg_dis" Authority="RW" Bits="21" />
|
|
<Bit Name="ef_cpu1_dis" Authority="RW" Bits="20" />
|
|
<Bit Name="ef_sf_dis" Authority="RW" Bits="19" />
|
|
<Bit Name="ef_cam_dis" Authority="RW" Bits="18" />
|
|
<Bit Name="ef_0_key_enc_en" Authority="RW" Bits="17" />
|
|
<Bit Name="ef_wifi_dis" Authority="RW" Bits="16" />
|
|
<Bit Name="ef_ble_dis" Authority="RW" Bits="15" />
|
|
<Bit Name="ef_sdu_dis" Authority="RW" Bits="14" />
|
|
<Bit Name="ef_sf_key_0_sel" Authority="RW" Bits="13-12" />
|
|
<Bit Name="ef_boot_sel" Authority="RW" Bits="11-8" />
|
|
<Bit Name="ef_cpu0_enc_en" Authority="RW" Bits="7" />
|
|
<Bit Name="ef_cpu1_enc_en" Authority="RW" Bits="6" />
|
|
<Bit Name="ef_sboot_en" Authority="RW" Bits="5-4" />
|
|
<Bit Name="ef_sboot_sign_mode" Authority="RW" Bits="3-2" />
|
|
<Bit Name="ef_sf_aes_mode" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="ef_dbg_pwd_low" Authority="RW" Address="0x40007004" Width="32" Description="ef_dbg_pwd_low.">
|
|
<Bit Name="ef_dbg_pwd_low" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_dbg_pwd_high" Authority="RW" Address="0x40007008" Width="32" Description="ef_dbg_pwd_high.">
|
|
<Bit Name="ef_dbg_pwd_high" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_ana_trim_0" Authority="RW" Address="0x4000700C" Width="32" Description="ef_ana_trim_0.">
|
|
<Bit Name="ef_ana_trim_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_sw_usage_0" Authority="RW" Address="0x40007010" Width="32" Description="ef_sw_usage_0.">
|
|
<Bit Name="ef_sw_usage_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_wifi_mac_low" Authority="RW" Address="0x40007014" Width="32" Description="ef_wifi_mac_low.">
|
|
<Bit Name="ef_wifi_mac_low" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_wifi_mac_high" Authority="RW" Address="0x40007018" Width="32" Description="ef_wifi_mac_high.">
|
|
<Bit Name="ef_wifi_mac_high" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_0_w0" Authority="RW" Address="0x4000701C" Width="32" Description="ef_key_slot_0_w0.">
|
|
<Bit Name="ef_key_slot_0_w0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_0_w1" Authority="RW" Address="0x40007020" Width="32" Description="ef_key_slot_0_w1.">
|
|
<Bit Name="ef_key_slot_0_w1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_0_w2" Authority="RW" Address="0x40007024" Width="32" Description="ef_key_slot_0_w2.">
|
|
<Bit Name="ef_key_slot_0_w2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_0_w3" Authority="RW" Address="0x40007028" Width="32" Description="ef_key_slot_0_w3.">
|
|
<Bit Name="ef_key_slot_0_w3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_1_w0" Authority="RW" Address="0x40007x2C" Width="32" Description="ef_key_slot_1_w0.">
|
|
<Bit Name="ef_key_slot_1_w0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_1_w1" Authority="RW" Address="0x40007030" Width="32" Description="ef_key_slot_1_w1.">
|
|
<Bit Name="ef_key_slot_1_w1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_1_w2" Authority="RW" Address="0x40007034" Width="32" Description="ef_key_slot_1_w2.">
|
|
<Bit Name="ef_key_slot_1_w2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_1_w3" Authority="RW" Address="0x40007038" Width="32" Description="ef_key_slot_1_w3.">
|
|
<Bit Name="ef_key_slot_1_w3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_2_w0" Authority="RW" Address="0x40007x3C" Width="32" Description="ef_key_slot_2_w0.">
|
|
<Bit Name="ef_key_slot_2_w0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_2_w1" Authority="RW" Address="0x40007040" Width="32" Description="ef_key_slot_2_w1.">
|
|
<Bit Name="ef_key_slot_2_w1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_2_w2" Authority="RW" Address="0x40007044" Width="32" Description="ef_key_slot_2_w2.">
|
|
<Bit Name="ef_key_slot_2_w2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_2_w3" Authority="RW" Address="0x40007048" Width="32" Description="ef_key_slot_2_w3.">
|
|
<Bit Name="ef_key_slot_2_w3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_3_w0" Authority="RW" Address="0x40007x4C" Width="32" Description="ef_key_slot_3_w0.">
|
|
<Bit Name="ef_key_slot_3_w0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_3_w1" Authority="RW" Address="0x40007050" Width="32" Description="ef_key_slot_3_w1.">
|
|
<Bit Name="ef_key_slot_3_w1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_3_w2" Authority="RW" Address="0x40007054" Width="32" Description="ef_key_slot_3_w2.">
|
|
<Bit Name="ef_key_slot_3_w2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_3_w3" Authority="RW" Address="0x40007058" Width="32" Description="ef_key_slot_3_w3.">
|
|
<Bit Name="ef_key_slot_3_w3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_4_w0" Authority="RW" Address="0x40007x5C" Width="32" Description="ef_key_slot_4_w0.">
|
|
<Bit Name="ef_key_slot_4_w0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_4_w1" Authority="RW" Address="0x40007060" Width="32" Description="ef_key_slot_4_w1.">
|
|
<Bit Name="ef_key_slot_4_w1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_4_w2" Authority="RW" Address="0x40007064" Width="32" Description="ef_key_slot_4_w2.">
|
|
<Bit Name="ef_key_slot_4_w2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_4_w3" Authority="RW" Address="0x40007068" Width="32" Description="ef_key_slot_4_w3.">
|
|
<Bit Name="ef_key_slot_4_w3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_5_w0" Authority="RW" Address="0x40007x6C" Width="32" Description="ef_key_slot_5_w0.">
|
|
<Bit Name="ef_key_slot_5_w0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_5_w1" Authority="RW" Address="0x40007070" Width="32" Description="ef_key_slot_5_w1.">
|
|
<Bit Name="ef_key_slot_5_w1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_5_w2" Authority="RW" Address="0x40007074" Width="32" Description="ef_key_slot_5_w2.">
|
|
<Bit Name="ef_key_slot_5_w2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_key_slot_5_w3" Authority="RW" Address="0x40007078" Width="32" Description="ef_key_slot_5_w3.">
|
|
<Bit Name="ef_key_slot_5_w3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_data_0_lock" Authority="RW" Address="0x4000707C" Width="32" Description="ef_data_0_lock.">
|
|
<Bit Name="rd_lock_key_slot_5" Authority="RW" Bits="31" />
|
|
<Bit Name="rd_lock_key_slot_4" Authority="RW" Bits="30" />
|
|
<Bit Name="rd_lock_key_slot_3" Authority="RW" Bits="29" />
|
|
<Bit Name="rd_lock_key_slot_2" Authority="RW" Bits="28" />
|
|
<Bit Name="rd_lock_key_slot_1" Authority="RW" Bits="27" />
|
|
<Bit Name="rd_lock_key_slot_0" Authority="RW" Bits="26" />
|
|
<Bit Name="rd_lock_dbg_pwd" Authority="RW" Bits="25" />
|
|
<Bit Name="wr_lock_key_slot_5_h" Authority="RW" Bits="24" />
|
|
<Bit Name="wr_lock_key_slot_4_h" Authority="RW" Bits="23" />
|
|
<Bit Name="wr_lock_key_slot_3" Authority="RW" Bits="22" />
|
|
<Bit Name="wr_lock_key_slot_2" Authority="RW" Bits="21" />
|
|
<Bit Name="wr_lock_key_slot_1" Authority="RW" Bits="20" />
|
|
<Bit Name="wr_lock_key_slot_0" Authority="RW" Bits="19" />
|
|
<Bit Name="wr_lock_wifi_mac" Authority="RW" Bits="18" />
|
|
<Bit Name="wr_lock_sw_usage_0" Authority="RW" Bits="17" />
|
|
<Bit Name="wr_lock_dbg_pwd" Authority="RW" Bits="16" />
|
|
<Bit Name="wr_lock_boot_mode" Authority="RW" Bits="15" />
|
|
<Bit Name="wr_lock_key_slot_5_l" Authority="RW" Bits="14" />
|
|
<Bit Name="wr_lock_key_slot_4_l" Authority="RW" Bits="13" />
|
|
<Bit Name="ef_ana_trim_1" Authority="RW" Bits="12-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="ef_data_1">
|
|
<Register Name="reg_key_slot_6_w0" Authority="RW" Address="0x40007080" Width="32" Description="reg_key_slot_6_w0.">
|
|
<Bit Name="reg_key_slot_6_w0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_6_w1" Authority="RW" Address="0x40007084" Width="32" Description="reg_key_slot_6_w1.">
|
|
<Bit Name="reg_key_slot_6_w1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_6_w2" Authority="RW" Address="0x40007088" Width="32" Description="reg_key_slot_6_w2.">
|
|
<Bit Name="reg_key_slot_6_w2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_6_w3" Authority="RW" Address="0x4000708C" Width="32" Description="reg_key_slot_6_w3.">
|
|
<Bit Name="reg_key_slot_6_w3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_7_w0" Authority="RW" Address="0x40007090" Width="32" Description="reg_key_slot_7_w0.">
|
|
<Bit Name="reg_key_slot_7_w0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_7_w1" Authority="RW" Address="0x40007094" Width="32" Description="reg_key_slot_7_w1.">
|
|
<Bit Name="reg_key_slot_7_w1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_7_w2" Authority="RW" Address="0x40007098" Width="32" Description="reg_key_slot_7_w2.">
|
|
<Bit Name="reg_key_slot_7_w2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_7_w3" Authority="RW" Address="0x4000709C" Width="32" Description="reg_key_slot_7_w3.">
|
|
<Bit Name="reg_key_slot_7_w3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_8_w0" Authority="RW" Address="0x400070A0" Width="32" Description="reg_key_slot_8_w0.">
|
|
<Bit Name="reg_key_slot_8_w0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_8_w1" Authority="RW" Address="0x400070A4" Width="32" Description="reg_key_slot_8_w1.">
|
|
<Bit Name="reg_key_slot_8_w1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_8_w2" Authority="RW" Address="0x400070A8" Width="32" Description="reg_key_slot_8_w2.">
|
|
<Bit Name="reg_key_slot_8_w2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_8_w3" Authority="RW" Address="0x400070AC" Width="32" Description="reg_key_slot_8_w3.">
|
|
<Bit Name="reg_key_slot_8_w3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_9_w0" Authority="RW" Address="0x400070B0" Width="32" Description="reg_key_slot_9_w0.">
|
|
<Bit Name="reg_key_slot_9_w0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_9_w1" Authority="RW" Address="0x400070B4" Width="32" Description="reg_key_slot_9_w1.">
|
|
<Bit Name="reg_key_slot_9_w1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_9_w2" Authority="RW" Address="0x400070B8" Width="32" Description="reg_key_slot_9_w2.">
|
|
<Bit Name="reg_key_slot_9_w2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_9_w3" Authority="RW" Address="0x400070BC" Width="32" Description="reg_key_slot_9_w3.">
|
|
<Bit Name="reg_key_slot_9_w3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="reg_key_slot_10_w0" Authority="RW" Address="0x400070C0" Width="32" Description="reg_key_slot_10_w0." />
|
|
<Register Name="reg_key_slot_10_w1" Authority="RW" Address="0x400070C4" Width="32" Description="reg_key_slot_10_w1." />
|
|
<Register Name="reg_key_slot_10_w2" Authority="RW" Address="0x400070C8" Width="32" Description="reg_key_slot_10_w2." />
|
|
<Register Name="reg_key_slot_10_w3" Authority="RW" Address="0x400070CC" Width="32" Description="reg_key_slot_10_w3." />
|
|
<Register Name="reg_key_slot_11_w0" Authority="RW" Address="0x400070D0" Width="32" Description="reg_key_slot_11_w0." />
|
|
<Register Name="reg_key_slot_11_w1" Authority="RW" Address="0x400070D4" Width="32" Description="reg_key_slot_11_w1." />
|
|
<Register Name="reg_key_slot_11_w2" Authority="RW" Address="0x400070D8" Width="32" Description="reg_key_slot_11_w2." />
|
|
<Register Name="reg_key_slot_11_w3" Authority="RW" Address="0x400070DC" Width="32" Description="reg_key_slot_11_w3." />
|
|
<Register Name="reg_data_1_lock" Authority="RW" Address="0x400070E0" Width="32" Description="reg_data_1_lock.">
|
|
<Bit Name="rd_lock_key_slot_9" Authority="RW" Bits="29" />
|
|
<Bit Name="rd_lock_key_slot_8" Authority="RW" Bits="28" />
|
|
<Bit Name="rd_lock_key_slot_7" Authority="RW" Bits="27" />
|
|
<Bit Name="rd_lock_key_slot_6" Authority="RW" Bits="26" />
|
|
<Bit Name="RESERVED_25_16" Authority="RW" Bits="25-16" />
|
|
<Bit Name="wr_lock_key_slot_9" Authority="RW" Bits="13" />
|
|
<Bit Name="wr_lock_key_slot_8" Authority="RW" Bits="12" />
|
|
<Bit Name="wr_lock_key_slot_7" Authority="RW" Bits="11" />
|
|
<Bit Name="wr_lock_key_slot_6" Authority="RW" Bits="10" />
|
|
<Bit Name="RESERVED_9_0" Authority="RW" Bits="9-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="ef_ctrl">
|
|
<Register Name="ef_if_ctrl_0" Authority="RW" Address="0x40007800" Width="32" Description="ef_if_ctrl_0.">
|
|
<Bit Name="ef_if_prot_code_cyc" Authority="RW" Bits="31-24" />
|
|
<Bit Name="ef_if_0_int_set" Authority="RW" Bits="22" />
|
|
<Bit Name="ef_if_0_int_clr" Authority="RW" Bits="21" />
|
|
<Bit Name="ef_if_0_int" Authority="RW" Bits="20" />
|
|
<Bit Name="ef_if_cyc_modify_lock" Authority="RW" Bits="19" />
|
|
<Bit Name="ef_if_auto_rd_en" Authority="RW" Bits="18" />
|
|
<Bit Name="ef_clk_sahb_data_gate" Authority="RW" Bits="17" />
|
|
<Bit Name="ef_if_por_dig" Authority="RW" Bits="16" />
|
|
<Bit Name="ef_if_prot_code_ctrl" Authority="RW" Bits="15-8" />
|
|
<Bit Name="ef_clk_sahb_data_sel" Authority="RW" Bits="7" />
|
|
<Bit Name="ef_if_0_cyc_modify" Authority="RW" Bits="6" />
|
|
<Bit Name="ef_if_0_manual_en" Authority="RW" Bits="5" />
|
|
<Bit Name="ef_if_0_trig" Authority="RW" Bits="4" />
|
|
<Bit Name="ef_if_0_rw" Authority="RW" Bits="3" />
|
|
<Bit Name="ef_if_0_busy" Authority="RW" Bits="2" />
|
|
<Bit Name="ef_if_0_autoload_done" Authority="RW" Bits="1" />
|
|
<Bit Name="ef_if_0_autoload_p1_done" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ef_if_cyc_0" Authority="RW" Address="0x40007804" Width="32" Description="ef_if_cyc_0.">
|
|
<Bit Name="ef_if_cyc_pd_cs_s" Authority="RW" Bits="31-24" />
|
|
<Bit Name="ef_if_cyc_cs" Authority="RW" Bits="23-18" />
|
|
<Bit Name="ef_if_cyc_rd_adr" Authority="RW" Bits="17-12" />
|
|
<Bit Name="ef_if_cyc_rd_dat" Authority="RW" Bits="11-6" />
|
|
<Bit Name="ef_if_cyc_rd_dmy" Authority="RW" Bits="5-0" />
|
|
</Register>
|
|
<Register Name="ef_if_cyc_1" Authority="RW" Address="0x40007808" Width="32" Description="ef_if_cyc_1.">
|
|
<Bit Name="ef_if_cyc_pd_cs_h" Authority="RW" Bits="31-26" />
|
|
<Bit Name="ef_if_cyc_ps_cs" Authority="RW" Bits="25-20" />
|
|
<Bit Name="ef_if_cyc_wr_adr" Authority="RW" Bits="19-14" />
|
|
<Bit Name="ef_if_cyc_pp" Authority="RW" Bits="13-6" />
|
|
<Bit Name="ef_if_cyc_pi" Authority="RW" Bits="5-0" />
|
|
</Register>
|
|
<Register Name="ef_if_0_manual" Authority="RW" Address="0x4000780C" Width="32" Description="ef_if_0_manual.">
|
|
<Bit Name="ef_if_prot_code_manual" Authority="RW" Bits="31-24" />
|
|
<Bit Name="ef_if_0_q" Authority="RW" Bits="23-16" />
|
|
<Bit Name="ef_if_csb" Authority="RW" Bits="15" />
|
|
<Bit Name="ef_if_load" Authority="RW" Bits="14" />
|
|
<Bit Name="ef_if_pgenb" Authority="RW" Bits="13" />
|
|
<Bit Name="ef_if_strobe" Authority="RW" Bits="12" />
|
|
<Bit Name="ef_if_ps" Authority="RW" Bits="11" />
|
|
<Bit Name="ef_if_pd" Authority="RW" Bits="10" />
|
|
<Bit Name="ef_if_a" Authority="RW" Bits="9-0" />
|
|
</Register>
|
|
<Register Name="ef_if_0_status" Authority="RW" Address="0x40007810" Width="32" Description="ef_if_0_status.">
|
|
<Bit Name="ef_if_0_status" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_if_cfg_0" Authority="RW" Address="0x40007814" Width="32" Description="ef_if_cfg_0.">
|
|
<Bit Name="ef_if_dbg_mode" Authority="RW" Bits="31-28" />
|
|
<Bit Name="ef_if_dbg_jtag_0_dis" Authority="RW" Bits="27-26" />
|
|
<Bit Name="ef_if_dbg_jtag_1_dis" Authority="RW" Bits="25-24" />
|
|
<Bit Name="ef_if_efuse_dbg_dis" Authority="RW" Bits="23" />
|
|
<Bit Name="ef_if_se_dbg_dis" Authority="RW" Bits="22" />
|
|
<Bit Name="ef_if_cpu_rst_dbg_dis" Authority="RW" Bits="21" />
|
|
<Bit Name="ef_if_cpu1_dis" Authority="RW" Bits="20" />
|
|
<Bit Name="ef_if_sf_dis" Authority="RW" Bits="19" />
|
|
<Bit Name="ef_if_cam_dis" Authority="RW" Bits="18" />
|
|
<Bit Name="ef_if_0_key_enc_en" Authority="RW" Bits="17" />
|
|
<Bit Name="ef_if_wifi_dis" Authority="RW" Bits="16" />
|
|
<Bit Name="ef_if_ble_dis" Authority="RW" Bits="15" />
|
|
<Bit Name="ef_if_sdu_dis" Authority="RW" Bits="14" />
|
|
<Bit Name="ef_if_sf_key_0_sel" Authority="RW" Bits="13-12" />
|
|
<Bit Name="ef_if_boot_sel" Authority="RW" Bits="11-8" />
|
|
<Bit Name="ef_if_cpu0_enc_en" Authority="RW" Bits="7" />
|
|
<Bit Name="ef_if_cpu1_enc_en" Authority="RW" Bits="6" />
|
|
<Bit Name="ef_if_sboot_en" Authority="RW" Bits="5-4" />
|
|
<Bit Name="ef_if_sboot_sign_mode" Authority="RW" Bits="3-2" />
|
|
<Bit Name="ef_if_sf_aes_mode" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="ef_sw_cfg_0" Authority="RW" Address="0x40007818" Width="32" Description="ef_sw_cfg_0.">
|
|
<Bit Name="ef_sw_dbg_mode" Authority="RW" Bits="31-28" />
|
|
<Bit Name="ef_sw_dbg_jtag_0_dis" Authority="RW" Bits="27-26" />
|
|
<Bit Name="ef_sw_dbg_jtag_1_dis" Authority="RW" Bits="25-24" />
|
|
<Bit Name="ef_sw_efuse_dbg_dis" Authority="RW" Bits="23" />
|
|
<Bit Name="ef_sw_se_dbg_dis" Authority="RW" Bits="22" />
|
|
<Bit Name="ef_sw_cpu_rst_dbg_dis" Authority="RW" Bits="21" />
|
|
<Bit Name="ef_sw_cpu1_dis" Authority="RW" Bits="20" />
|
|
<Bit Name="ef_sw_sf_dis" Authority="RW" Bits="19" />
|
|
<Bit Name="ef_sw_cam_dis" Authority="RW" Bits="18" />
|
|
<Bit Name="ef_sw_0_key_enc_en" Authority="RW" Bits="17" />
|
|
<Bit Name="ef_sw_wifi_dis" Authority="RW" Bits="16" />
|
|
<Bit Name="ef_sw_ble_dis" Authority="RW" Bits="15" />
|
|
<Bit Name="ef_sw_sdu_dis" Authority="RW" Bits="14" />
|
|
<Bit Name="ef_sw_sf_key_0_sel" Authority="RW" Bits="13-12" />
|
|
<Bit Name="ef_sw_cpu0_enc_en" Authority="RW" Bits="7" />
|
|
<Bit Name="ef_sw_cpu1_enc_en" Authority="RW" Bits="6" />
|
|
<Bit Name="ef_sw_sboot_en" Authority="RW" Bits="5-4" />
|
|
<Bit Name="ef_sw_sboot_sign_mode" Authority="RW" Bits="3-2" />
|
|
<Bit Name="ef_sw_sf_aes_mode" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="ef_reserved" Authority="RW" Address="0x4000781C" Width="32" Description="ef_reserved.">
|
|
<Bit Name="ef_reserved" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_if_ana_trim_0" Authority="RW" Address="0x40007820" Width="32" Description="ef_if_ana_trim_0.">
|
|
<Bit Name="ef_if_ana_trim_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_if_sw_usage_0" Authority="RW" Address="0x40007824" Width="32" Description="ef_if_sw_usage_0.">
|
|
<Bit Name="ef_if_sw_usage_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_crc_ctrl_0" Authority="RW" Address="0x40007A00" Width="32" Description="ef_crc_ctrl_0.">
|
|
<Bit Name="ef_crc_slp_n" Authority="RW" Bits="31-16" />
|
|
<Bit Name="ef_crc_lock" Authority="RW" Bits="11" />
|
|
<Bit Name="ef_crc_int_set" Authority="RW" Bits="10" />
|
|
<Bit Name="ef_crc_int_clr" Authority="RW" Bits="9" />
|
|
<Bit Name="ef_crc_int" Authority="RW" Bits="8" />
|
|
<Bit Name="ef_crc_din_endian" Authority="RW" Bits="7" />
|
|
<Bit Name="ef_crc_dout_endian" Authority="RW" Bits="6" />
|
|
<Bit Name="ef_crc_dout_inv_en" Authority="RW" Bits="5" />
|
|
<Bit Name="ef_crc_error" Authority="RW" Bits="4" />
|
|
<Bit Name="ef_crc_mode" Authority="RW" Bits="3" />
|
|
<Bit Name="ef_crc_en" Authority="RW" Bits="2" />
|
|
<Bit Name="ef_crc_trig" Authority="RW" Bits="1" />
|
|
<Bit Name="ef_crc_busy" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ef_crc_ctrl_1" Authority="RW" Address="0x40007A04" Width="32" Description="ef_crc_ctrl_1.">
|
|
<Bit Name="ef_crc_data_0_en" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_crc_ctrl_2" Authority="RW" Address="0x40007A08" Width="32" Description="ef_crc_ctrl_2.">
|
|
<Bit Name="ef_crc_data_1_en" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_crc_ctrl_3" Authority="RW" Address="0x40007A0C" Width="32" Description="ef_crc_ctrl_3.">
|
|
<Bit Name="ef_crc_iv" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_crc_ctrl_4" Authority="RW" Address="0x40007A10" Width="32" Description="ef_crc_ctrl_4.">
|
|
<Bit Name="ef_crc_golden" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="ef_crc_ctrl_5" Authority="RW" Address="0x40007A14" Width="32" Description="ef_crc_ctrl_5.">
|
|
<Bit Name="ef_crc_dout" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="cci">
|
|
<Register Name="cci_cfg" Authority="RW" Address="0x40008000" Width="32" Description="cci_cfg.">
|
|
<Bit Name="reg_mcci_clk_inv" Authority="RW" Bits="9" />
|
|
<Bit Name="reg_scci_clk_inv" Authority="RW" Bits="8" />
|
|
<Bit Name="cfg_cci1_pre_read" Authority="RW" Bits="7" />
|
|
<Bit Name="reg_div_m_cci_sclk" Authority="RW" Bits="6-5" />
|
|
<Bit Name="reg_m_cci_sclk_en" Authority="RW" Bits="4" />
|
|
<Bit Name="cci_mas_hw_mode" Authority="RW" Bits="3" />
|
|
<Bit Name="cci_mas_sel_cci2" Authority="RW" Bits="2" />
|
|
<Bit Name="cci_slv_sel_cci2" Authority="RW" Bits="1" />
|
|
<Bit Name="cci_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="cci_addr" Authority="RW" Address="0x40008004" Width="32" Description="cci_addr.">
|
|
<Bit Name="apb_cci_addr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="cci_wdata" Authority="RW" Address="0x40008008" Width="32" Description="cci_wdata.">
|
|
<Bit Name="apb_cci_wdata" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="cci_rdata" Authority="RW" Address="0x4000800C" Width="32" Description="cci_rdata.">
|
|
<Bit Name="apb_cci_rdata" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="cci_ctl" Authority="RW" Address="0x40008010" Width="32" Description="cci_ctl.">
|
|
<Bit Name="ahb_state" Authority="RW" Bits="3-2" />
|
|
<Bit Name="cci_read_flag" Authority="RW" Bits="1" />
|
|
<Bit Name="cci_write_flag" Authority="RW" Bits="0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="l1c">
|
|
<Register Name="l1c_config" Authority="RW" Address="0x40009000" Width="32" Description="l1c_config.">
|
|
<Bit Name="reserved_31_30" Authority="RW" Bits="31-30" />
|
|
<Bit Name="l1c_flush_done" Authority="RW" Bits="29" />
|
|
<Bit Name="l1c_flush_en" Authority="RW" Bits="28" />
|
|
<Bit Name="wrap_dis" Authority="RW" Bits="26" />
|
|
<Bit Name="early_resp_dis" Authority="RW" Bits="25" />
|
|
<Bit Name="l1c_bmx_busy_option_dis" Authority="RW" Bits="24" />
|
|
<Bit Name="l1c_bmx_timeout_en" Authority="RW" Bits="23-20" />
|
|
<Bit Name="l1c_bmx_arb_mode" Authority="RW" Bits="17-16" />
|
|
<Bit Name="l1c_bmx_err_en" Authority="RW" Bits="15" />
|
|
<Bit Name="l1c_bypass" Authority="RW" Bits="14" />
|
|
<Bit Name="irom_2t_access" Authority="RW" Bits="12" />
|
|
<Bit Name="l1c_way_dis" Authority="RW" Bits="11-8" />
|
|
<Bit Name="l1c_wa_en" Authority="RW" Bits="6" />
|
|
<Bit Name="l1c_wb_en" Authority="RW" Bits="5" />
|
|
<Bit Name="l1c_wt_en" Authority="RW" Bits="4" />
|
|
<Bit Name="l1c_invalid_done" Authority="RW" Bits="3" />
|
|
<Bit Name="l1c_invalid_en" Authority="RW" Bits="2" />
|
|
<Bit Name="l1c_cnt_en" Authority="RW" Bits="1" />
|
|
<Bit Name="l1c_cacheable" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="hit_cnt_lsb" Authority="RW" Address="0x40009004" Width="32" Description="hit_cnt_lsb.">
|
|
<Bit Name="hit_cnt_lsb" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="hit_cnt_msb" Authority="RW" Address="0x40009008" Width="32" Description="hit_cnt_msb.">
|
|
<Bit Name="hit_cnt_msb" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="miss_cnt" Authority="RW" Address="0x4000900C" Width="32" Description="miss_cnt.">
|
|
<Bit Name="miss_cnt" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="l1c_misc" Authority="RW" Address="0x40009010" Width="32" Description="l1c_misc.">
|
|
<Bit Name="l1c_fsm" Authority="RW" Bits="30-28" />
|
|
</Register>
|
|
<Register Name="l1c_bmx_err_addr_en" Authority="RW" Address="0x40009200" Width="32" Description="l1c_bmx_err_addr_en.">
|
|
<Bit Name="l1c_hsel_option" Authority="RW" Bits="19-16" />
|
|
<Bit Name="l1c_bmx_err_tz" Authority="RW" Bits="5" />
|
|
<Bit Name="l1c_bmx_err_dec" Authority="RW" Bits="4" />
|
|
<Bit Name="l1c_bmx_err_addr_dis" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="l1c_bmx_err_addr" Authority="RW" Address="0x40009204" Width="32" Description="l1c_bmx_err_addr.">
|
|
<Bit Name="l1c_bmx_err_addr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irom1_misr_dataout_0" Authority="RW" Address="0x40009208" Width="32" Description="irom1_misr_dataout_0.">
|
|
<Bit Name="irom1_misr_dataout_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irom1_misr_dataout_1" Authority="RW" Address="0x4000920C" Width="32" Description="irom1_misr_dataout_1.">
|
|
<Bit Name="irom1_misr_dataout_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="cpu_clk_gate" Authority="RW" Address="0x40009210" Width="32" Description="cpu_clk_gate.">
|
|
<Bit Name="force_e21_clock_on_2" Authority="RW" Bits="2" />
|
|
<Bit Name="force_e21_clock_on_1" Authority="RW" Bits="1" />
|
|
<Bit Name="force_e21_clock_on_0" Authority="RW" Bits="0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="uart">
|
|
<Register Name="utx_config" Authority="RW" Address="0x4000A000" Width="32" Description="utx_config.">
|
|
<Bit Name="cr_utx_len" Authority="RW" Bits="31-16" />
|
|
<Bit Name="cr_utx_bit_cnt_b" Authority="RW" Bits="15-13" />
|
|
<Bit Name="cr_utx_bit_cnt_p" Authority="RW" Bits="12-11" />
|
|
<Bit Name="cr_utx_bit_cnt_d" Authority="RW" Bits="10-8" />
|
|
<Bit Name="cr_utx_ir_inv" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_utx_ir_en" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_utx_prt_sel" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_utx_prt_en" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_utx_lin_en" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_utx_frm_en" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_utx_cts_en" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_utx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="urx_config" Authority="RW" Address="0x4000A004" Width="32" Description="urx_config.">
|
|
<Bit Name="cr_urx_len" Authority="RW" Bits="31-16" />
|
|
<Bit Name="cr_urx_deg_cnt" Authority="RW" Bits="15-12" />
|
|
<Bit Name="cr_urx_deg_en" Authority="RW" Bits="11" />
|
|
<Bit Name="cr_urx_bit_cnt_d" Authority="RW" Bits="10-8" />
|
|
<Bit Name="cr_urx_ir_inv" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_urx_ir_en" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_urx_prt_sel" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_urx_prt_en" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_urx_lin_en" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_urx_abr_en" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_urx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="uart_bit_prd" Authority="RW" Address="0x4000A008" Width="32" Description="uart_bit_prd.">
|
|
<Bit Name="cr_urx_bit_prd" Authority="RW" Bits="31-16" />
|
|
<Bit Name="cr_utx_bit_prd" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="data_config" Authority="RW" Address="0x4000A00C" Width="32" Description="data_config.">
|
|
<Bit Name="cr_uart_bit_inv" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="utx_ir_position" Authority="RW" Address="0x4000A010" Width="32" Description="utx_ir_position.">
|
|
<Bit Name="cr_utx_ir_pos_p" Authority="RW" Bits="31-16" />
|
|
<Bit Name="cr_utx_ir_pos_s" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="urx_ir_position" Authority="RW" Address="0x4000A014" Width="32" Description="urx_ir_position.">
|
|
<Bit Name="cr_urx_ir_pos_s" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="urx_rto_timer" Authority="RW" Address="0x4000A018" Width="32" Description="urx_rto_timer.">
|
|
<Bit Name="cr_urx_rto_value" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="uart_sw_mode" Authority="RW" Address="0x4000A01C" Width="32" Description="uart_sw_mode.">
|
|
<Bit Name="cr_urx_rts_sw_val" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_urx_rts_sw_mode" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_utx_txd_sw_val" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_utx_txd_sw_mode" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="uart_int_sts" Authority="RW" Address="0x4000A020" Width="32" Description="UART interrupt status">
|
|
<Bit Name="urx_lse_int" Authority="RW" Bits="8" />
|
|
<Bit Name="urx_fer_int" Authority="RW" Bits="7" />
|
|
<Bit Name="utx_fer_int" Authority="RW" Bits="6" />
|
|
<Bit Name="urx_pce_int" Authority="RW" Bits="5" />
|
|
<Bit Name="urx_rto_int" Authority="RW" Bits="4" />
|
|
<Bit Name="urx_fifo_int" Authority="RW" Bits="3" />
|
|
<Bit Name="utx_fifo_int" Authority="RW" Bits="2" />
|
|
<Bit Name="urx_end_int" Authority="RW" Bits="1" />
|
|
<Bit Name="utx_end_int" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="uart_int_mask" Authority="RW" Address="0x4000A024" Width="32" Description="UART interrupt mask">
|
|
<Bit Name="cr_urx_lse_mask" Authority="RW" Bits="8" />
|
|
<Bit Name="cr_urx_fer_mask" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_utx_fer_mask" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_urx_pce_mask" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_urx_rto_mask" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_urx_fifo_mask" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_utx_fifo_mask" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_urx_end_mask" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_utx_end_mask" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="uart_int_clear" Authority="RW" Address="0x4000A028" Width="32" Description="UART interrupt clear">
|
|
<Bit Name="cr_urx_lse_clr" Authority="RW" Bits="8" />
|
|
<Bit Name="rsvd_7" Authority="RW" Bits="7" />
|
|
<Bit Name="rsvd_6" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_urx_pce_clr" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_urx_rto_clr" Authority="RW" Bits="4" />
|
|
<Bit Name="rsvd_3" Authority="RW" Bits="3" />
|
|
<Bit Name="rsvd_2" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_urx_end_clr" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_utx_end_clr" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="uart_int_en" Authority="RW" Address="0x4000Ax2C" Width="32" Description="UART interrupt enable">
|
|
<Bit Name="cr_urx_lse_en" Authority="RW" Bits="8" />
|
|
<Bit Name="cr_urx_fer_en" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_utx_fer_en" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_urx_pce_en" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_urx_rto_en" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_urx_fifo_en" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_utx_fifo_en" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_urx_end_en" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_utx_end_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="uart_status" Authority="RW" Address="0x4000A030" Width="32" Description="uart_status.">
|
|
<Bit Name="sts_urx_bus_busy" Authority="RW" Bits="1" />
|
|
<Bit Name="sts_utx_bus_busy" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="sts_urx_abr_prd" Authority="RW" Address="0x4000A034" Width="32" Description="sts_urx_abr_prd.">
|
|
<Bit Name="sts_urx_abr_prd_0x55" Authority="RW" Bits="31-16" />
|
|
<Bit Name="sts_urx_abr_prd_start" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="uart_fifo_config_0" Authority="RW" Address="0x4000A080" Width="32" Description="uart_fifo_config_0.">
|
|
<Bit Name="rx_fifo_underflow" Authority="RW" Bits="7" />
|
|
<Bit Name="rx_fifo_overflow" Authority="RW" Bits="6" />
|
|
<Bit Name="tx_fifo_underflow" Authority="RW" Bits="5" />
|
|
<Bit Name="tx_fifo_overflow" Authority="RW" Bits="4" />
|
|
<Bit Name="rx_fifo_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="tx_fifo_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="uart_dma_rx_en" Authority="RW" Bits="1" />
|
|
<Bit Name="uart_dma_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="uart_fifo_config_1" Authority="RW" Address="0x4000A084" Width="32" Description="uart_fifo_config_1.">
|
|
<Bit Name="rx_fifo_th" Authority="RW" Bits="30-24" />
|
|
<Bit Name="tx_fifo_th" Authority="RW" Bits="22-16" />
|
|
<Bit Name="rx_fifo_cnt" Authority="RW" Bits="15-8" />
|
|
<Bit Name="tx_fifo_cnt" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="uart_fifo_wdata" Authority="RW" Address="0x4000A088" Width="32" Description="uart_fifo_wdata.">
|
|
<Bit Name="uart_fifo_wdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="uart_fifo_rdata" Authority="RW" Address="0x4000A08C" Width="32" Description="uart_fifo_rdata.">
|
|
<Bit Name="uart_fifo_rdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="spi">
|
|
<Register Name="spi_config" Authority="RW" Address="0x4000A000" Width="32" Description="spi_config.">
|
|
<Bit Name="cr_spi_deg_cnt" Authority="RW" Bits="15-12" />
|
|
<Bit Name="cr_spi_deg_en" Authority="RW" Bits="11" />
|
|
<Bit Name="cr_spi_m_cont_en" Authority="RW" Bits="9" />
|
|
<Bit Name="cr_spi_rxd_ignr_en" Authority="RW" Bits="8" />
|
|
<Bit Name="cr_spi_byte_inv" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_spi_bit_inv" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_spi_sclk_ph" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_spi_sclk_pol" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_spi_frame_size" Authority="RW" Bits="3-2" />
|
|
<Bit Name="cr_spi_s_en" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_spi_m_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="spi_int_sts" Authority="RW" Address="0x4000A004" Width="32" Description="spi_int_sts.">
|
|
<Bit Name="cr_spi_fer_en" Authority="RW" Bits="29" />
|
|
<Bit Name="cr_spi_txu_en" Authority="RW" Bits="28" />
|
|
<Bit Name="cr_spi_sto_en" Authority="RW" Bits="27" />
|
|
<Bit Name="cr_spi_rxf_en" Authority="RW" Bits="26" />
|
|
<Bit Name="cr_spi_txf_en" Authority="RW" Bits="25" />
|
|
<Bit Name="cr_spi_end_en" Authority="RW" Bits="24" />
|
|
<Bit Name="rsvd_21" Authority="RW" Bits="21" />
|
|
<Bit Name="cr_spi_txu_clr" Authority="RW" Bits="20" />
|
|
<Bit Name="cr_spi_sto_clr" Authority="RW" Bits="19" />
|
|
<Bit Name="rsvd_18" Authority="RW" Bits="18" />
|
|
<Bit Name="rsvd_17" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_spi_end_clr" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_spi_fer_mask" Authority="RW" Bits="13" />
|
|
<Bit Name="cr_spi_txu_mask" Authority="RW" Bits="12" />
|
|
<Bit Name="cr_spi_sto_mask" Authority="RW" Bits="11" />
|
|
<Bit Name="cr_spi_rxf_mask" Authority="RW" Bits="10" />
|
|
<Bit Name="cr_spi_txf_mask" Authority="RW" Bits="9" />
|
|
<Bit Name="cr_spi_end_mask" Authority="RW" Bits="8" />
|
|
<Bit Name="spi_fer_int" Authority="RW" Bits="5" />
|
|
<Bit Name="spi_txu_int" Authority="RW" Bits="4" />
|
|
<Bit Name="spi_sto_int" Authority="RW" Bits="3" />
|
|
<Bit Name="spi_rxf_int" Authority="RW" Bits="2" />
|
|
<Bit Name="spi_txf_int" Authority="RW" Bits="1" />
|
|
<Bit Name="spi_end_int" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="spi_bus_busy" Authority="RW" Address="0x4000A008" Width="32" Description="spi_bus_busy.">
|
|
<Bit Name="sts_spi_bus_busy" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="spi_prd_0" Authority="RW" Address="0x4000A010" Width="32" Description="spi_prd_0.">
|
|
<Bit Name="cr_spi_prd_d_ph_1" Authority="RW" Bits="31-24" />
|
|
<Bit Name="cr_spi_prd_d_ph_0" Authority="RW" Bits="23-16" />
|
|
<Bit Name="cr_spi_prd_p" Authority="RW" Bits="15-8" />
|
|
<Bit Name="cr_spi_prd_s" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="spi_prd_1" Authority="RW" Address="0x4000A014" Width="32" Description="spi_prd_1.">
|
|
<Bit Name="cr_spi_prd_i" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="spi_rxd_ignr" Authority="RW" Address="0x4000A018" Width="32" Description="spi_rxd_ignr.">
|
|
<Bit Name="cr_spi_rxd_ignr_s" Authority="RW" Bits="20-16" />
|
|
<Bit Name="cr_spi_rxd_ignr_p" Authority="RW" Bits="4-0" />
|
|
</Register>
|
|
<Register Name="spi_sto_value" Authority="RW" Address="0x4000A01C" Width="32" Description="spi_sto_value.">
|
|
<Bit Name="cr_spi_sto_value" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="spi_fifo_config_0" Authority="RW" Address="0x4000A080" Width="32" Description="spi_fifo_config_0.">
|
|
<Bit Name="rx_fifo_underflow" Authority="RW" Bits="7" />
|
|
<Bit Name="rx_fifo_overflow" Authority="RW" Bits="6" />
|
|
<Bit Name="tx_fifo_underflow" Authority="RW" Bits="5" />
|
|
<Bit Name="tx_fifo_overflow" Authority="RW" Bits="4" />
|
|
<Bit Name="rx_fifo_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="tx_fifo_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="spi_dma_rx_en" Authority="RW" Bits="1" />
|
|
<Bit Name="spi_dma_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="spi_fifo_config_1" Authority="RW" Address="0x4000A084" Width="32" Description="spi_fifo_config_1.">
|
|
<Bit Name="rx_fifo_th" Authority="RW" Bits="25-24" />
|
|
<Bit Name="tx_fifo_th" Authority="RW" Bits="17-16" />
|
|
<Bit Name="rx_fifo_cnt" Authority="RW" Bits="10-8" />
|
|
<Bit Name="tx_fifo_cnt" Authority="RW" Bits="2-0" />
|
|
</Register>
|
|
<Register Name="spi_fifo_wdata" Authority="RW" Address="0x4000A088" Width="32" Description="spi_fifo_wdata.">
|
|
<Bit Name="spi_fifo_wdata" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="spi_fifo_rdata" Authority="RW" Address="0x4000A08C" Width="32" Description="spi_fifo_rdata.">
|
|
<Bit Name="spi_fifo_rdata" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="i2c">
|
|
<Register Name="i2c_config" Authority="RW" Address="0x4000A000" Width="32" Description="i2c_config.">
|
|
<Bit Name="cr_i2c_deg_cnt" Authority="RW" Bits="31-28" />
|
|
<Bit Name="cr_i2c_pkt_len" Authority="RW" Bits="23-16" />
|
|
<Bit Name="cr_i2c_slv_addr" Authority="RW" Bits="14-8" />
|
|
<Bit Name="cr_i2c_sub_addr_bc" Authority="RW" Bits="6-5" />
|
|
<Bit Name="cr_i2c_sub_addr_en" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_i2c_scl_sync_en" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_i2c_deg_en" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_i2c_pkt_dir" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_i2c_m_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="i2c_int_sts" Authority="RW" Address="0x4000A004" Width="32" Description="i2c_int_sts.">
|
|
<Bit Name="cr_i2c_fer_en" Authority="RW" Bits="29" />
|
|
<Bit Name="cr_i2c_arb_en" Authority="RW" Bits="28" />
|
|
<Bit Name="cr_i2c_nak_en" Authority="RW" Bits="27" />
|
|
<Bit Name="cr_i2c_rxf_en" Authority="RW" Bits="26" />
|
|
<Bit Name="cr_i2c_txf_en" Authority="RW" Bits="25" />
|
|
<Bit Name="cr_i2c_end_en" Authority="RW" Bits="24" />
|
|
<Bit Name="rsvd_21" Authority="RW" Bits="21" />
|
|
<Bit Name="cr_i2c_arb_clr" Authority="RW" Bits="20" />
|
|
<Bit Name="cr_i2c_nak_clr" Authority="RW" Bits="19" />
|
|
<Bit Name="rsvd_18" Authority="RW" Bits="18" />
|
|
<Bit Name="rsvd_17" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_i2c_end_clr" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_i2c_fer_mask" Authority="RW" Bits="13" />
|
|
<Bit Name="cr_i2c_arb_mask" Authority="RW" Bits="12" />
|
|
<Bit Name="cr_i2c_nak_mask" Authority="RW" Bits="11" />
|
|
<Bit Name="cr_i2c_rxf_mask" Authority="RW" Bits="10" />
|
|
<Bit Name="cr_i2c_txf_mask" Authority="RW" Bits="9" />
|
|
<Bit Name="cr_i2c_end_mask" Authority="RW" Bits="8" />
|
|
<Bit Name="i2c_fer_int" Authority="RW" Bits="5" />
|
|
<Bit Name="i2c_arb_int" Authority="RW" Bits="4" />
|
|
<Bit Name="i2c_nak_int" Authority="RW" Bits="3" />
|
|
<Bit Name="i2c_rxf_int" Authority="RW" Bits="2" />
|
|
<Bit Name="i2c_txf_int" Authority="RW" Bits="1" />
|
|
<Bit Name="i2c_end_int" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="i2c_sub_addr" Authority="RW" Address="0x4000A008" Width="32" Description="i2c_sub_addr.">
|
|
<Bit Name="cr_i2c_sub_addr_b3" Authority="RW" Bits="31-24" />
|
|
<Bit Name="cr_i2c_sub_addr_b2" Authority="RW" Bits="23-16" />
|
|
<Bit Name="cr_i2c_sub_addr_b1" Authority="RW" Bits="15-8" />
|
|
<Bit Name="cr_i2c_sub_addr_b0" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="i2c_bus_busy" Authority="RW" Address="0x4000A00C" Width="32" Description="i2c_bus_busy.">
|
|
<Bit Name="cr_i2c_bus_busy_clr" Authority="RW" Bits="1" />
|
|
<Bit Name="sts_i2c_bus_busy" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="i2c_prd_start" Authority="RW" Address="0x4000A010" Width="32" Description="i2c_prd_start.">
|
|
<Bit Name="cr_i2c_prd_s_ph_3" Authority="RW" Bits="31-24" />
|
|
<Bit Name="cr_i2c_prd_s_ph_2" Authority="RW" Bits="23-16" />
|
|
<Bit Name="cr_i2c_prd_s_ph_1" Authority="RW" Bits="15-8" />
|
|
<Bit Name="cr_i2c_prd_s_ph_0" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="i2c_prd_stop" Authority="RW" Address="0x4000A014" Width="32" Description="i2c_prd_stop.">
|
|
<Bit Name="cr_i2c_prd_p_ph_3" Authority="RW" Bits="31-24" />
|
|
<Bit Name="cr_i2c_prd_p_ph_2" Authority="RW" Bits="23-16" />
|
|
<Bit Name="cr_i2c_prd_p_ph_1" Authority="RW" Bits="15-8" />
|
|
<Bit Name="cr_i2c_prd_p_ph_0" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="i2c_prd_data" Authority="RW" Address="0x4000A018" Width="32" Description="i2c_prd_data.">
|
|
<Bit Name="cr_i2c_prd_d_ph_3" Authority="RW" Bits="31-24" />
|
|
<Bit Name="cr_i2c_prd_d_ph_2" Authority="RW" Bits="23-16" />
|
|
<Bit Name="cr_i2c_prd_d_ph_1" Authority="RW" Bits="15-8" />
|
|
<Bit Name="cr_i2c_prd_d_ph_0" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="i2c_fifo_config_0" Authority="RW" Address="0x4000A080" Width="32" Description="i2c_fifo_config_0.">
|
|
<Bit Name="rx_fifo_underflow" Authority="RW" Bits="7" />
|
|
<Bit Name="rx_fifo_overflow" Authority="RW" Bits="6" />
|
|
<Bit Name="tx_fifo_underflow" Authority="RW" Bits="5" />
|
|
<Bit Name="tx_fifo_overflow" Authority="RW" Bits="4" />
|
|
<Bit Name="rx_fifo_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="tx_fifo_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="i2c_dma_rx_en" Authority="RW" Bits="1" />
|
|
<Bit Name="i2c_dma_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="i2c_fifo_config_1" Authority="RW" Address="0x4000A084" Width="32" Description="i2c_fifo_config_1.">
|
|
<Bit Name="rx_fifo_th" Authority="RW" Bits="24" />
|
|
<Bit Name="tx_fifo_th" Authority="RW" Bits="16" />
|
|
<Bit Name="rx_fifo_cnt" Authority="RW" Bits="9-8" />
|
|
<Bit Name="tx_fifo_cnt" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="i2c_fifo_wdata" Authority="RW" Address="0x4000A088" Width="32" Description="i2c_fifo_wdata.">
|
|
<Bit Name="i2c_fifo_wdata" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="i2c_fifo_rdata" Authority="RW" Address="0x4000A08C" Width="32" Description="i2c_fifo_rdata.">
|
|
<Bit Name="i2c_fifo_rdata" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="pwm">
|
|
<Register Name="pwm_int_config" Authority="RW" Address="0x4000A000" Width="32" Description="pwm_int_config.">
|
|
<Bit Name="pwm_int_clear" Authority="RW" Bits="13-8" />
|
|
<Bit Name="pwm_interrupt_sts" Authority="RW" Bits="5-0" />
|
|
</Register>
|
|
<Register Name="pwm0_clkdiv" Authority="RW" Address="0x4000A020" Width="32" Description="pwm0_clkdiv.">
|
|
<Bit Name="pwm_clk_div" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm0_thre1" Authority="RW" Address="0x4000A024" Width="32" Description="pwm0_thre1.">
|
|
<Bit Name="pwm_thre1" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm0_thre2" Authority="RW" Address="0x4000A028" Width="32" Description="pwm0_thre2.">
|
|
<Bit Name="pwm_thre2" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm0_period" Authority="RW" Address="0x4000Ax2C" Width="32" Description="pwm0_period.">
|
|
<Bit Name="pwm_period" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm0_config" Authority="RW" Address="0x4000A030" Width="32" Description="pwm0_config.">
|
|
<Bit Name="pwm_sts_top" Authority="RW" Bits="7" />
|
|
<Bit Name="pwm_stop_en" Authority="RW" Bits="6" />
|
|
<Bit Name="pwm_sw_mode" Authority="RW" Bits="5" />
|
|
<Bit Name="pwm_sw_force_val" Authority="RW" Bits="4" />
|
|
<Bit Name="pwm_stop_mode" Authority="RW" Bits="3" />
|
|
<Bit Name="pwm_out_inv" Authority="RW" Bits="2" />
|
|
<Bit Name="reg_clk_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="pwm0_interrupt" Authority="RW" Address="0x4000A034" Width="32" Description="pwm0_interrupt.">
|
|
<Bit Name="pwm_int_enable" Authority="RW" Bits="16" />
|
|
<Bit Name="pwm_int_period_cnt" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm1_clkdiv" Authority="RW" Address="0x4000A040" Width="32" Description="pwm1_clkdiv.">
|
|
<Bit Name="pwm_clk_div" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm1_thre1" Authority="RW" Address="0x4000A044" Width="32" Description="pwm1_thre1.">
|
|
<Bit Name="pwm_thre1" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm1_thre2" Authority="RW" Address="0x4000A048" Width="32" Description="pwm1_thre2.">
|
|
<Bit Name="pwm_thre2" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm1_period" Authority="RW" Address="0x4000Ax4C" Width="32" Description="pwm1_period.">
|
|
<Bit Name="pwm_period" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm1_config" Authority="RW" Address="0x4000A050" Width="32" Description="pwm1_config.">
|
|
<Bit Name="pwm_sts_top" Authority="RW" Bits="7" />
|
|
<Bit Name="pwm_stop_en" Authority="RW" Bits="6" />
|
|
<Bit Name="pwm_sw_mode" Authority="RW" Bits="5" />
|
|
<Bit Name="pwm_sw_force_val" Authority="RW" Bits="4" />
|
|
<Bit Name="pwm_stop_mode" Authority="RW" Bits="3" />
|
|
<Bit Name="pwm_out_inv" Authority="RW" Bits="2" />
|
|
<Bit Name="reg_clk_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="pwm1_interrupt" Authority="RW" Address="0x4000A054" Width="32" Description="pwm1_interrupt.">
|
|
<Bit Name="pwm_int_enable" Authority="RW" Bits="16" />
|
|
<Bit Name="pwm_int_period_cnt" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm2_clkdiv" Authority="RW" Address="0x4000A060" Width="32" Description="pwm2_clkdiv.">
|
|
<Bit Name="pwm_clk_div" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm2_thre1" Authority="RW" Address="0x4000A064" Width="32" Description="pwm2_thre1.">
|
|
<Bit Name="pwm_thre1" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm2_thre2" Authority="RW" Address="0x4000A068" Width="32" Description="pwm2_thre2.">
|
|
<Bit Name="pwm_thre2" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm2_period" Authority="RW" Address="0x4000Ax6C" Width="32" Description="pwm2_period.">
|
|
<Bit Name="pwm_period" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm2_config" Authority="RW" Address="0x4000A070" Width="32" Description="pwm2_config.">
|
|
<Bit Name="pwm_sts_top" Authority="RW" Bits="7" />
|
|
<Bit Name="pwm_stop_en" Authority="RW" Bits="6" />
|
|
<Bit Name="pwm_sw_mode" Authority="RW" Bits="5" />
|
|
<Bit Name="pwm_sw_force_val" Authority="RW" Bits="4" />
|
|
<Bit Name="pwm_stop_mode" Authority="RW" Bits="3" />
|
|
<Bit Name="pwm_out_inv" Authority="RW" Bits="2" />
|
|
<Bit Name="reg_clk_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="pwm2_interrupt" Authority="RW" Address="0x4000A074" Width="32" Description="pwm2_interrupt.">
|
|
<Bit Name="pwm_int_enable" Authority="RW" Bits="16" />
|
|
<Bit Name="pwm_int_period_cnt" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm3_clkdiv" Authority="RW" Address="0x4000A080" Width="32" Description="pwm3_clkdiv.">
|
|
<Bit Name="pwm_clk_div" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm3_thre1" Authority="RW" Address="0x4000A084" Width="32" Description="pwm3_thre1.">
|
|
<Bit Name="pwm_thre1" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm3_thre2" Authority="RW" Address="0x4000A088" Width="32" Description="pwm3_thre2.">
|
|
<Bit Name="pwm_thre2" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm3_period" Authority="RW" Address="0x4000A08C" Width="32" Description="pwm3_period.">
|
|
<Bit Name="pwm_period" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm3_config" Authority="RW" Address="0x4000A090" Width="32" Description="pwm3_config.">
|
|
<Bit Name="pwm_sts_top" Authority="RW" Bits="7" />
|
|
<Bit Name="pwm_stop_en" Authority="RW" Bits="6" />
|
|
<Bit Name="pwm_sw_mode" Authority="RW" Bits="5" />
|
|
<Bit Name="pwm_sw_force_val" Authority="RW" Bits="4" />
|
|
<Bit Name="pwm_stop_mode" Authority="RW" Bits="3" />
|
|
<Bit Name="pwm_out_inv" Authority="RW" Bits="2" />
|
|
<Bit Name="reg_clk_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="pwm3_interrupt" Authority="RW" Address="0x4000A094" Width="32" Description="pwm3_interrupt.">
|
|
<Bit Name="pwm_int_enable" Authority="RW" Bits="16" />
|
|
<Bit Name="pwm_int_period_cnt" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm4_clkdiv" Authority="RW" Address="0x4000A0A0" Width="32" Description="pwm4_clkdiv.">
|
|
<Bit Name="pwm_clk_div" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm4_thre1" Authority="RW" Address="0x4000A0A4" Width="32" Description="pwm4_thre1.">
|
|
<Bit Name="pwm_thre1" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm4_thre2" Authority="RW" Address="0x4000A0A8" Width="32" Description="pwm4_thre2.">
|
|
<Bit Name="pwm_thre2" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm4_period" Authority="RW" Address="0x4000A0AC" Width="32" Description="pwm4_period.">
|
|
<Bit Name="pwm_period" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="pwm4_config" Authority="RW" Address="0x4000A0B0" Width="32" Description="pwm4_config.">
|
|
<Bit Name="pwm_sts_top" Authority="RW" Bits="7" />
|
|
<Bit Name="pwm_stop_en" Authority="RW" Bits="6" />
|
|
<Bit Name="pwm_sw_mode" Authority="RW" Bits="5" />
|
|
<Bit Name="pwm_sw_force_val" Authority="RW" Bits="4" />
|
|
<Bit Name="pwm_stop_mode" Authority="RW" Bits="3" />
|
|
<Bit Name="pwm_out_inv" Authority="RW" Bits="2" />
|
|
<Bit Name="reg_clk_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="pwm4_interrupt" Authority="RW" Address="0x4000A0B4" Width="32" Description="pwm4_interrupt.">
|
|
<Bit Name="pwm_int_enable" Authority="RW" Bits="16" />
|
|
<Bit Name="pwm_int_period_cnt" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="timer">
|
|
<Register Name="TCCR" Authority="RW" Address="0x4000A000" Width="32" Description="TCCR.">
|
|
<Bit Name="cs_wdt" Authority="RW" Bits="9-8" />
|
|
<Bit Name="RESERVED_7" Authority="RW" Bits="7" />
|
|
<Bit Name="cs_2" Authority="RW" Bits="6-5" />
|
|
<Bit Name="RESERVED_4" Authority="RW" Bits="4" />
|
|
<Bit Name="cs_1" Authority="RW" Bits="3-2" />
|
|
</Register>
|
|
<Register Name="TMR2_0" Authority="RW" Address="0x4000A010" Width="32" Description="TMR2_0.">
|
|
<Bit Name="tmr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TMR2_1" Authority="RW" Address="0x4000A014" Width="32" Description="TMR2_1.">
|
|
<Bit Name="tmr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TMR2_2" Authority="RW" Address="0x4000A018" Width="32" Description="TMR2_2.">
|
|
<Bit Name="tmr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TMR3_0" Authority="RW" Address="0x4000A01C" Width="32" Description="TMR3_0.">
|
|
<Bit Name="tmr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TMR3_1" Authority="RW" Address="0x4000A020" Width="32" Description="TMR3_1.">
|
|
<Bit Name="tmr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TMR3_2" Authority="RW" Address="0x4000A024" Width="32" Description="TMR3_2.">
|
|
<Bit Name="tmr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TCR2" Authority="RW" Address="0x4000Ax2C" Width="32" Description="TCR2.">
|
|
<Bit Name="tcr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TCR3" Authority="RW" Address="0x4000A030" Width="32" Description="TCR3.">
|
|
<Bit Name="tcr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TMSR2" Authority="RW" Address="0x4000A038" Width="32" Description="TMSR2.">
|
|
<Bit Name="tmsr_2" Authority="RW" Bits="2" />
|
|
<Bit Name="tmsr_1" Authority="RW" Bits="1" />
|
|
<Bit Name="tmsr_0" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="TMSR3" Authority="RW" Address="0x4000Ax3C" Width="32" Description="TMSR3.">
|
|
<Bit Name="tmsr_2" Authority="RW" Bits="2" />
|
|
<Bit Name="tmsr_1" Authority="RW" Bits="1" />
|
|
<Bit Name="tmsr_0" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="TIER2" Authority="RW" Address="0x4000A044" Width="32" Description="TIER2.">
|
|
<Bit Name="tier_2" Authority="RW" Bits="2" />
|
|
<Bit Name="tier_1" Authority="RW" Bits="1" />
|
|
<Bit Name="tier_0" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="TIER3" Authority="RW" Address="0x4000A048" Width="32" Description="TIER3.">
|
|
<Bit Name="tier_2" Authority="RW" Bits="2" />
|
|
<Bit Name="tier_1" Authority="RW" Bits="1" />
|
|
<Bit Name="tier_0" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="TPLVR2" Authority="RW" Address="0x4000A050" Width="32" Description="TPLVR2.">
|
|
<Bit Name="tplvr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TPLVR3" Authority="RW" Address="0x4000A054" Width="32" Description="TPLVR3.">
|
|
<Bit Name="tplvr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TPLCR2" Authority="RW" Address="0x4000Ax5C" Width="32" Description="TPLCR2.">
|
|
<Bit Name="tplcr" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="TPLCR3" Authority="RW" Address="0x4000A060" Width="32" Description="TPLCR3.">
|
|
<Bit Name="tplcr" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="WMER" Authority="RW" Address="0x4000A064" Width="32" Description="WMER.">
|
|
<Bit Name="wrie" Authority="RW" Bits="1" />
|
|
<Bit Name="we" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="WMR" Authority="RW" Address="0x4000A068" Width="32" Description="WMR.">
|
|
<Bit Name="wmr" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="WVR" Authority="RW" Address="0x4000Ax6C" Width="32" Description="WVR.">
|
|
<Bit Name="wvr" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="WSR" Authority="RW" Address="0x4000A070" Width="32" Description="WSR.">
|
|
<Bit Name="wts" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="TICR2" Authority="RW" Address="0x4000A078" Width="32" Description="TICR2.">
|
|
<Bit Name="tclr_2" Authority="RW" Bits="2" />
|
|
<Bit Name="tclr_1" Authority="RW" Bits="1" />
|
|
<Bit Name="tclr_0" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="TICR3" Authority="RW" Address="0x4000A07C" Width="32" Description="TICR3.">
|
|
<Bit Name="tclr_2" Authority="RW" Bits="2" />
|
|
<Bit Name="tclr_1" Authority="RW" Bits="1" />
|
|
<Bit Name="tclr_0" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="WICR" Authority="RW" Address="0x4000A080" Width="32" Description="WICR.">
|
|
<Bit Name="wiclr" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="TCER" Authority="RW" Address="0x4000A084" Width="32" Description="TCER.">
|
|
<Bit Name="timer3_en" Authority="RW" Bits="2" />
|
|
<Bit Name="timer2_en" Authority="RW" Bits="1" />
|
|
</Register>
|
|
<Register Name="TCMR" Authority="RW" Address="0x4000A088" Width="32" Description="TCMR.">
|
|
<Bit Name="timer3_mode" Authority="RW" Bits="2" />
|
|
<Bit Name="timer2_mode" Authority="RW" Bits="1" />
|
|
</Register>
|
|
<Register Name="TILR2" Authority="RW" Address="0x4000A090" Width="32" Description="TILR2.">
|
|
<Bit Name="tilr_2" Authority="RW" Bits="2" />
|
|
<Bit Name="tilr_1" Authority="RW" Bits="1" />
|
|
<Bit Name="tilr_0" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="TILR3" Authority="RW" Address="0x4000A094" Width="32" Description="TILR3.">
|
|
<Bit Name="tilr_2" Authority="RW" Bits="2" />
|
|
<Bit Name="tilr_1" Authority="RW" Bits="1" />
|
|
<Bit Name="tilr_0" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="WCR" Authority="RW" Address="0x4000A098" Width="32" Description="WCR.">
|
|
<Bit Name="wcr" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="WFAR" Authority="RW" Address="0x4000A09C" Width="32" Description="WFAR.">
|
|
<Bit Name="wfar" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="WSAR" Authority="RW" Address="0x4000A0A0" Width="32" Description="WSAR.">
|
|
<Bit Name="wsar" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="TCVWR2" Authority="RW" Address="0x4000A0A8" Width="32" Description="TCVWR2.">
|
|
<Bit Name="tcvwr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TCVWR3" Authority="RW" Address="0x4000A0AC" Width="32" Description="TCVWR3.">
|
|
<Bit Name="tcvwr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TCVSYN2" Authority="RW" Address="0x4000A0B4" Width="32" Description="TCVSYN2.">
|
|
<Bit Name="tcvsyn2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TCVSYN3" Authority="RW" Address="0x4000A0B8" Width="32" Description="TCVSYN3.">
|
|
<Bit Name="tcvsyn3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TCDR" Authority="RW" Address="0x4000A0BC" Width="32" Description="TCDR.">
|
|
<Bit Name="wcdr" Authority="RW" Bits="31-24" />
|
|
<Bit Name="tcdr3" Authority="RW" Bits="23-16" />
|
|
<Bit Name="tcdr2" Authority="RW" Bits="15-8" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="ir">
|
|
<Register Name="irtx_config" Authority="RW" Address="0x4000A000" Width="32" Description="irtx_config.">
|
|
<Bit Name="cr_irtx_data_num" Authority="RW" Bits="17-12" />
|
|
<Bit Name="cr_irtx_tail_hl_inv" Authority="RW" Bits="11" />
|
|
<Bit Name="cr_irtx_tail_en" Authority="RW" Bits="10" />
|
|
<Bit Name="cr_irtx_head_hl_inv" Authority="RW" Bits="9" />
|
|
<Bit Name="cr_irtx_head_en" Authority="RW" Bits="8" />
|
|
<Bit Name="cr_irtx_logic1_hl_inv" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_irtx_logic0_hl_inv" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_irtx_data_en" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_irtx_swm_en" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_irtx_mod_en" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_irtx_out_inv" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_irtx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="irtx_int_sts" Authority="RW" Address="0x4000A004" Width="32" Description="irtx_int_sts.">
|
|
<Bit Name="cr_irtx_end_en" Authority="RW" Bits="24" />
|
|
<Bit Name="cr_irtx_end_clr" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_irtx_end_mask" Authority="RW" Bits="8" />
|
|
<Bit Name="irtx_end_int" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="irtx_data_word0" Authority="RW" Address="0x4000A008" Width="32" Description="irtx_data_word0.">
|
|
<Bit Name="cr_irtx_data_word0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irtx_data_word1" Authority="RW" Address="0x4000A00C" Width="32" Description="irtx_data_word1.">
|
|
<Bit Name="cr_irtx_data_word1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irtx_pulse_width" Authority="RW" Address="0x4000A010" Width="32" Description="irtx_pulse_width.">
|
|
<Bit Name="cr_irtx_mod_ph1_w" Authority="RW" Bits="31-24" />
|
|
<Bit Name="cr_irtx_mod_ph0_w" Authority="RW" Bits="23-16" />
|
|
<Bit Name="cr_irtx_pw_unit" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="irtx_pw" Authority="RW" Address="0x4000A014" Width="32" Description="irtx_pw.">
|
|
<Bit Name="cr_irtx_tail_ph1_w" Authority="RW" Bits="31-28" />
|
|
<Bit Name="cr_irtx_tail_ph0_w" Authority="RW" Bits="27-24" />
|
|
<Bit Name="cr_irtx_head_ph1_w" Authority="RW" Bits="23-20" />
|
|
<Bit Name="cr_irtx_head_ph0_w" Authority="RW" Bits="19-16" />
|
|
<Bit Name="cr_irtx_logic1_ph1_w" Authority="RW" Bits="15-12" />
|
|
<Bit Name="cr_irtx_logic1_ph0_w" Authority="RW" Bits="11-8" />
|
|
<Bit Name="cr_irtx_logic0_ph1_w" Authority="RW" Bits="7-4" />
|
|
<Bit Name="cr_irtx_logic0_ph0_w" Authority="RW" Bits="3-0" />
|
|
</Register>
|
|
<Register Name="irtx_swm_pw_0" Authority="RW" Address="0x4000A040" Width="32" Description="irtx_swm_pw_0.">
|
|
<Bit Name="cr_irtx_swm_pw_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irtx_swm_pw_1" Authority="RW" Address="0x4000A044" Width="32" Description="irtx_swm_pw_1.">
|
|
<Bit Name="cr_irtx_swm_pw_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irtx_swm_pw_2" Authority="RW" Address="0x4000A048" Width="32" Description="irtx_swm_pw_2.">
|
|
<Bit Name="cr_irtx_swm_pw_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irtx_swm_pw_3" Authority="RW" Address="0x4000Ax4C" Width="32" Description="irtx_swm_pw_3.">
|
|
<Bit Name="cr_irtx_swm_pw_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irtx_swm_pw_4" Authority="RW" Address="0x4000A050" Width="32" Description="irtx_swm_pw_4.">
|
|
<Bit Name="cr_irtx_swm_pw_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irtx_swm_pw_5" Authority="RW" Address="0x4000A054" Width="32" Description="irtx_swm_pw_5.">
|
|
<Bit Name="cr_irtx_swm_pw_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irtx_swm_pw_6" Authority="RW" Address="0x4000A058" Width="32" Description="irtx_swm_pw_6.">
|
|
<Bit Name="cr_irtx_swm_pw_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irtx_swm_pw_7" Authority="RW" Address="0x4000Ax5C" Width="32" Description="irtx_swm_pw_7.">
|
|
<Bit Name="cr_irtx_swm_pw_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irrx_config" Authority="RW" Address="0x4000A080" Width="32" Description="irrx_config.">
|
|
<Bit Name="cr_irrx_deg_cnt" Authority="RW" Bits="11-8" />
|
|
<Bit Name="cr_irrx_deg_en" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_irrx_mode" Authority="RW" Bits="3-2" />
|
|
<Bit Name="cr_irrx_in_inv" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_irrx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="irrx_int_sts" Authority="RW" Address="0x4000A084" Width="32" Description="irrx_int_sts.">
|
|
<Bit Name="cr_irrx_end_en" Authority="RW" Bits="24" />
|
|
<Bit Name="cr_irrx_end_clr" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_irrx_end_mask" Authority="RW" Bits="8" />
|
|
<Bit Name="irrx_end_int" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="irrx_pw_config" Authority="RW" Address="0x4000A088" Width="32" Description="irrx_pw_config.">
|
|
<Bit Name="cr_irrx_end_th" Authority="RW" Bits="31-16" />
|
|
<Bit Name="cr_irrx_data_th" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="irrx_data_count" Authority="RW" Address="0x4000A090" Width="32" Description="irrx_data_count.">
|
|
<Bit Name="sts_irrx_data_cnt" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="irrx_data_word0" Authority="RW" Address="0x4000A094" Width="32" Description="irrx_data_word0.">
|
|
<Bit Name="sts_irrx_data_word0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irrx_data_word1" Authority="RW" Address="0x4000A098" Width="32" Description="irrx_data_word1.">
|
|
<Bit Name="sts_irrx_data_word1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="irrx_swm_fifo_config_0" Authority="RW" Address="0x4000A0C0" Width="32" Description="irrx_swm_fifo_config_0.">
|
|
<Bit Name="rx_fifo_cnt" Authority="RW" Bits="10-4" />
|
|
<Bit Name="rx_fifo_underflow" Authority="RW" Bits="3" />
|
|
<Bit Name="rx_fifo_overflow" Authority="RW" Bits="2" />
|
|
<Bit Name="rx_fifo_clr" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="irrx_swm_fifo_rdata" Authority="RW" Address="0x4000A0C4" Width="32" Description="irrx_swm_fifo_rdata.">
|
|
<Bit Name="rx_fifo_rdata" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="cks">
|
|
<Register Name="cks_config" Authority="RW" Address="0x4000A000" Width="32" Description="cks_config.">
|
|
<Bit Name="cr_cks_byte_swap" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_cks_clr" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="data_in" Authority="RW" Address="0x4000A004" Width="32" Description="data_in.">
|
|
<Bit Name="data_in" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="cks_out" Authority="RW" Address="0x4000A008" Width="32" Description="cks_out.">
|
|
<Bit Name="cks_out" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="qdec">
|
|
<Register Name="qdec_ctrl" Authority="RW" Address="0x4000A000" Width="32" Description="qdec_ctrl.">
|
|
<Bit Name="input_swap" Authority="RW" Bits="31" />
|
|
<Bit Name="rpt_mode" Authority="RW" Bits="30" />
|
|
<Bit Name="spl_mode" Authority="RW" Bits="29" />
|
|
<Bit Name="led_period" Authority="RW" Bits="28-20" />
|
|
<Bit Name="rpt_period" Authority="RW" Bits="19-12" />
|
|
<Bit Name="spl_period" Authority="RW" Bits="11-8" />
|
|
<Bit Name="deg_cnt" Authority="RW" Bits="7-4" />
|
|
<Bit Name="deg_en" Authority="RW" Bits="3" />
|
|
<Bit Name="led_pol" Authority="RW" Bits="2" />
|
|
<Bit Name="led_en" Authority="RW" Bits="1" />
|
|
<Bit Name="qdec_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="qdec_value" Authority="RW" Address="0x4000A004" Width="32" Description="qdec_value.">
|
|
<Bit Name="spl_val" Authority="RW" Bits="29-28" />
|
|
<Bit Name="acc2_val" Authority="RW" Bits="19-16" />
|
|
<Bit Name="acc1_val" Authority="RW" Bits="10-0" />
|
|
</Register>
|
|
<Register Name="qdec_int_en" Authority="RW" Address="0x4000A010" Width="32" Description="qdec_int_en.">
|
|
<Bit Name="overflow_en" Authority="RW" Bits="3" />
|
|
<Bit Name="dbl_rdy_en" Authority="RW" Bits="2" />
|
|
<Bit Name="spl_rdy_en" Authority="RW" Bits="1" />
|
|
<Bit Name="rpt_rdy_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="qdec_int_sts" Authority="RW" Address="0x4000A014" Width="32" Description="qdec_int_sts.">
|
|
<Bit Name="overflow_sts" Authority="RW" Bits="3" />
|
|
<Bit Name="dbl_rdy_sts" Authority="RW" Bits="2" />
|
|
<Bit Name="spl_rdy_sts" Authority="RW" Bits="1" />
|
|
<Bit Name="rpt_rdy_sts" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="qdec_int_clr" Authority="RW" Address="0x4000A018" Width="32" Description="qdec_int_clr.">
|
|
<Bit Name="overflow_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="dbl_rdy_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="spl_rdy_clr" Authority="RW" Bits="1" />
|
|
<Bit Name="rpt_rdy_clr" Authority="RW" Bits="0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="kys">
|
|
<Register Name="ks_ctrl" Authority="RW" Address="0x4000A000" Width="32" Description="ks_ctrl.">
|
|
<Bit Name="col_num" Authority="RW" Bits="24-20" />
|
|
<Bit Name="row_num" Authority="RW" Bits="18-16" />
|
|
<Bit Name="rc_ext" Authority="RW" Bits="9-8" />
|
|
<Bit Name="deg_cnt" Authority="RW" Bits="7-4" />
|
|
<Bit Name="deg_en" Authority="RW" Bits="3" />
|
|
<Bit Name="ghost_en" Authority="RW" Bits="2" />
|
|
<Bit Name="ks_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ks_int_en" Authority="RW" Address="0x4000A010" Width="32" Description="ks_int_en.">
|
|
<Bit Name="ks_int_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ks_int_sts" Authority="RW" Address="0x4000A014" Width="32" Description="ks_int_sts.">
|
|
<Bit Name="keycode_valid" Authority="RW" Bits="3-0" />
|
|
</Register>
|
|
<Register Name="keycode_clr" Authority="RW" Address="0x4000A018" Width="32" Description="keycode_clr.">
|
|
<Bit Name="keycode_clr" Authority="RW" Bits="3-0" />
|
|
</Register>
|
|
<Register Name="keycode_value" Authority="RW" Address="0x4000A01C" Width="32" Description="keycode_value.">
|
|
<Bit Name="keycode3" Authority="RW" Bits="31-24" />
|
|
<Bit Name="keycode2" Authority="RW" Bits="23-16" />
|
|
<Bit Name="keycode1" Authority="RW" Bits="15-8" />
|
|
<Bit Name="keycode0" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="i2s">
|
|
<Register Name="i2s_config" Authority="RW" Address="0x4000A000" Width="32" Description="i2s_config.">
|
|
<Bit Name="cr_ofs_en" Authority="RW" Bits="25" />
|
|
<Bit Name="cr_ofs_cnt" Authority="RW" Bits="24-20" />
|
|
<Bit Name="cr_mono_rx_ch" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_endian" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_i2s_mode" Authority="RW" Bits="17-16" />
|
|
<Bit Name="cr_data_size" Authority="RW" Bits="15-14" />
|
|
<Bit Name="cr_frame_size" Authority="RW" Bits="13-12" />
|
|
<Bit Name="cr_fs_3ch_mode" Authority="RW" Bits="8" />
|
|
<Bit Name="cr_fs_4ch_mode" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_fs_1t_mode" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_mute_mode" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_mono_mode" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_i2s_rxd_en" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_i2s_txd_en" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_i2s_s_en" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_i2s_m_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="i2s_int_sts" Authority="RW" Address="0x4000A004" Width="32" Description="i2s_int_sts.">
|
|
<Bit Name="cr_i2s_fer_en" Authority="RW" Bits="26" />
|
|
<Bit Name="cr_i2s_rxf_en" Authority="RW" Bits="25" />
|
|
<Bit Name="cr_i2s_txf_en" Authority="RW" Bits="24" />
|
|
<Bit Name="cr_i2s_fer_mask" Authority="RW" Bits="10" />
|
|
<Bit Name="cr_i2s_rxf_mask" Authority="RW" Bits="9" />
|
|
<Bit Name="cr_i2s_txf_mask" Authority="RW" Bits="8" />
|
|
<Bit Name="i2s_fer_int" Authority="RW" Bits="2" />
|
|
<Bit Name="i2s_rxf_int" Authority="RW" Bits="1" />
|
|
<Bit Name="i2s_txf_int" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="i2s_bclk_config" Authority="RW" Address="0x4000A010" Width="32" Description="i2s_bclk_config.">
|
|
<Bit Name="cr_bclk_div_h" Authority="RW" Bits="27-16" />
|
|
<Bit Name="cr_bclk_div_l" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="i2s_fifo_config_0" Authority="RW" Address="0x4000A080" Width="32" Description="i2s_fifo_config_0.">
|
|
<Bit Name="cr_fifo_24b_lj" Authority="RW" Bits="10" />
|
|
<Bit Name="cr_fifo_lr_exchg" Authority="RW" Bits="9" />
|
|
<Bit Name="cr_fifo_lr_merge" Authority="RW" Bits="8" />
|
|
<Bit Name="rx_fifo_underflow" Authority="RW" Bits="7" />
|
|
<Bit Name="rx_fifo_overflow" Authority="RW" Bits="6" />
|
|
<Bit Name="tx_fifo_underflow" Authority="RW" Bits="5" />
|
|
<Bit Name="tx_fifo_overflow" Authority="RW" Bits="4" />
|
|
<Bit Name="rx_fifo_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="tx_fifo_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="i2s_dma_rx_en" Authority="RW" Bits="1" />
|
|
<Bit Name="i2s_dma_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="i2s_fifo_config_1" Authority="RW" Address="0x4000A084" Width="32" Description="i2s_fifo_config_1.">
|
|
<Bit Name="rx_fifo_th" Authority="RW" Bits="27-24" />
|
|
<Bit Name="tx_fifo_th" Authority="RW" Bits="19-16" />
|
|
<Bit Name="rx_fifo_cnt" Authority="RW" Bits="12-8" />
|
|
<Bit Name="tx_fifo_cnt" Authority="RW" Bits="4-0" />
|
|
</Register>
|
|
<Register Name="i2s_fifo_wdata" Authority="RW" Address="0x4000A088" Width="32" Description="i2s_fifo_wdata.">
|
|
<Bit Name="i2s_fifo_wdata" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="i2s_fifo_rdata" Authority="RW" Address="0x4000A08C" Width="32" Description="i2s_fifo_rdata.">
|
|
<Bit Name="i2s_fifo_rdata" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="i2s_io_config" Authority="RW" Address="0x4000A0FC" Width="32" Description="i2s_io_config.">
|
|
<Bit Name="cr_deg_en" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_deg_cnt" Authority="RW" Bits="6-4" />
|
|
<Bit Name="cr_i2s_bclk_inv" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_i2s_fs_inv" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_i2s_rxd_inv" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_i2s_txd_inv" Authority="RW" Bits="0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="cam">
|
|
<Register Name="dvp2axi_configue" Authority="RW" Address="0x4000A000" Width="32" Description="dvp2axi_configue.">
|
|
<Bit Name="reg_dvp_wait_cycle" Authority="RW" Bits="31-24" />
|
|
<Bit Name="reg_dvp_pix_clk_cg" Authority="RW" Bits="20" />
|
|
<Bit Name="reg_interlv_mode" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_subsample_even" Authority="RW" Bits="15" />
|
|
<Bit Name="reg_subsample_en" Authority="RW" Bits="14" />
|
|
<Bit Name="reg_drop_even" Authority="RW" Bits="13" />
|
|
<Bit Name="reg_drop_en" Authority="RW" Bits="12" />
|
|
<Bit Name="reg_hw_mode_fwrap" Authority="RW" Bits="11" />
|
|
<Bit Name="reg_dvp_mode" Authority="RW" Bits="10-8" />
|
|
<Bit Name="reg_hburst" Authority="RW" Bits="5-4" />
|
|
<Bit Name="reg_line_vld_pol" Authority="RW" Bits="3" />
|
|
<Bit Name="reg_fram_vld_pol" Authority="RW" Bits="2" />
|
|
<Bit Name="reg_sw_mode" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_dvp_enable" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="dvp2ahb_addr_start_0" Authority="RW" Address="0x4000A004" Width="32" Description="dvp2ahb_addr_start_0.">
|
|
<Bit Name="reg_addr_start_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="dvp2ahb_mem_bcnt_0" Authority="RW" Address="0x4000A008" Width="32" Description="dvp2ahb_mem_bcnt_0.">
|
|
<Bit Name="reg_mem_burst_cnt_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="dvp2ahb_frame_bcnt_0" Authority="RW" Address="0x4000A00C" Width="32" Description="dvp2ahb_frame_bcnt_0.">
|
|
<Bit Name="reg_frame_burst_cnt_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="dvp2ahb_addr_start_1" Authority="RW" Address="0x4000A010" Width="32" Description="dvp2ahb_addr_start_1.">
|
|
<Bit Name="reg_addr_start_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="dvp2ahb_mem_bcnt_1" Authority="RW" Address="0x4000A014" Width="32" Description="dvp2ahb_mem_bcnt_1.">
|
|
<Bit Name="reg_mem_burst_cnt_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="dvp2ahb_frame_bcnt_1" Authority="RW" Address="0x4000A018" Width="32" Description="dvp2ahb_frame_bcnt_1.">
|
|
<Bit Name="reg_frame_burst_cnt_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="dvp_status_and_error" Authority="RW" Address="0x4000A01C" Width="32" Description="dvp_status_and_error.">
|
|
<Bit Name="st_bus_flsh" Authority="RW" Bits="31" />
|
|
<Bit Name="st_bus_wait" Authority="RW" Bits="30" />
|
|
<Bit Name="st_bus_func" Authority="RW" Bits="29" />
|
|
<Bit Name="st_bus_idle" Authority="RW" Bits="28" />
|
|
<Bit Name="frame_valid_cnt_1" Authority="RW" Bits="27-24" />
|
|
<Bit Name="frame_valid_cnt_0" Authority="RW" Bits="23-20" />
|
|
<Bit Name="st_dvp_idle" Authority="RW" Bits="19" />
|
|
<Bit Name="ahb_idle_1" Authority="RW" Bits="17" />
|
|
<Bit Name="ahb_idle_0" Authority="RW" Bits="16" />
|
|
<Bit Name="sts_vcnt_int" Authority="RW" Bits="9" />
|
|
<Bit Name="sts_hcnt_int" Authority="RW" Bits="8" />
|
|
<Bit Name="sts_fifo_int_1" Authority="RW" Bits="7" />
|
|
<Bit Name="sts_fifo_int_0" Authority="RW" Bits="6" />
|
|
<Bit Name="sts_frame_int_1" Authority="RW" Bits="5" />
|
|
<Bit Name="sts_frame_int_0" Authority="RW" Bits="4" />
|
|
<Bit Name="sts_mem_int_1" Authority="RW" Bits="3" />
|
|
<Bit Name="sts_mem_int_0" Authority="RW" Bits="2" />
|
|
<Bit Name="sts_normal_int_1" Authority="RW" Bits="1" />
|
|
<Bit Name="sts_normal_int_0" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="dvp_frame_fifo_pop" Authority="RW" Address="0x4000A020" Width="32" Description="dvp_frame_fifo_pop.">
|
|
<Bit Name="reg_int_fifo_clr_1" Authority="RW" Bits="19" />
|
|
<Bit Name="reg_int_frame_clr_1" Authority="RW" Bits="18" />
|
|
<Bit Name="reg_int_mem_clr_1" Authority="RW" Bits="17" />
|
|
<Bit Name="reg_int_normal_clr_1" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_int_vcnt_clr_0" Authority="RW" Bits="9" />
|
|
<Bit Name="reg_int_hcnt_clr_0" Authority="RW" Bits="8" />
|
|
<Bit Name="reg_int_fifo_clr_0" Authority="RW" Bits="7" />
|
|
<Bit Name="reg_int_frame_clr_0" Authority="RW" Bits="6" />
|
|
<Bit Name="reg_int_mem_clr_0" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_int_normal_clr_0" Authority="RW" Bits="4" />
|
|
<Bit Name="rfifo_pop_1" Authority="RW" Bits="1" />
|
|
<Bit Name="rfifo_pop_0" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="snsr_control" Authority="RW" Address="0x4000A024" Width="32" Description="snsr_control.">
|
|
<Bit Name="reg_cam_pwdn" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_cam_rst" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="int_control" Authority="RW" Address="0x4000A028" Width="32" Description="int_control.">
|
|
<Bit Name="reg_frame_cnt_trgr_int" Authority="RW" Bits="31-28" />
|
|
<Bit Name="reg_int_vcnt_en" Authority="RW" Bits="6" />
|
|
<Bit Name="reg_int_hcnt_en" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_int_fifo_en" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_int_frame_en" Authority="RW" Bits="3" />
|
|
<Bit Name="reg_int_mem_en" Authority="RW" Bits="2" />
|
|
<Bit Name="reg_int_normal_1_en" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_int_normal_0_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="hsync_control" Authority="RW" Address="0x4000A030" Width="32" Description="hsync_control.">
|
|
<Bit Name="reg_hsync_act_start" Authority="RW" Bits="31-16" />
|
|
<Bit Name="reg_hsync_act_end" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="vsync_control" Authority="RW" Address="0x4000A034" Width="32" Description="vsync_control.">
|
|
<Bit Name="reg_vsync_act_start" Authority="RW" Bits="31-16" />
|
|
<Bit Name="reg_vsync_act_end" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="frame_size_control" Authority="RW" Address="0x4000A038" Width="32" Description="frame_size_control.">
|
|
<Bit Name="reg_total_vcnt" Authority="RW" Bits="31-16" />
|
|
<Bit Name="reg_total_hcnt" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr0_0" Authority="RW" Address="0x4000A040" Width="32" Description="frame_start_addr0_0.">
|
|
<Bit Name="frame_start_addr_0_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt0_0" Authority="RW" Address="0x4000A044" Width="32" Description="frame_byte_cnt0_0.">
|
|
<Bit Name="frame_byte_cnt_0_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr0_1" Authority="RW" Address="0x4000A048" Width="32" Description="frame_start_addr0_1.">
|
|
<Bit Name="frame_start_addr_0_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt0_1" Authority="RW" Address="0x4000Ax4C" Width="32" Description="frame_byte_cnt0_1.">
|
|
<Bit Name="frame_byte_cnt_0_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr0_2" Authority="RW" Address="0x4000A050" Width="32" Description="frame_start_addr0_2.">
|
|
<Bit Name="frame_start_addr_0_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt0_2" Authority="RW" Address="0x4000A054" Width="32" Description="frame_byte_cnt0_2.">
|
|
<Bit Name="frame_byte_cnt_0_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr0_3" Authority="RW" Address="0x4000A058" Width="32" Description="frame_start_addr0_3.">
|
|
<Bit Name="frame_start_addr_0_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt0_3" Authority="RW" Address="0x4000Ax5C" Width="32" Description="frame_byte_cnt0_3.">
|
|
<Bit Name="frame_byte_cnt_0_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr0_4" Authority="RW" Address="0x4000A060" Width="32" Description="frame_start_addr0_4.">
|
|
<Bit Name="frame_start_addr_0_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt0_4" Authority="RW" Address="0x4000A064" Width="32" Description="frame_byte_cnt0_4.">
|
|
<Bit Name="frame_byte_cnt_0_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr0_5" Authority="RW" Address="0x4000A068" Width="32" Description="frame_start_addr0_5.">
|
|
<Bit Name="frame_start_addr_0_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt0_5" Authority="RW" Address="0x4000Ax6C" Width="32" Description="frame_byte_cnt0_5.">
|
|
<Bit Name="frame_byte_cnt_0_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr0_6" Authority="RW" Address="0x4000A070" Width="32" Description="frame_start_addr0_6.">
|
|
<Bit Name="frame_start_addr_0_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt0_6" Authority="RW" Address="0x4000A074" Width="32" Description="frame_byte_cnt0_6.">
|
|
<Bit Name="frame_byte_cnt_0_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr0_7" Authority="RW" Address="0x4000A078" Width="32" Description="frame_start_addr0_7.">
|
|
<Bit Name="frame_start_addr_0_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt0_7" Authority="RW" Address="0x4000A07C" Width="32" Description="frame_byte_cnt0_7.">
|
|
<Bit Name="frame_byte_cnt_0_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr1_0" Authority="RW" Address="0x4000A080" Width="32" Description="frame_start_addr1_0.">
|
|
<Bit Name="frame_start_addr_1_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt1_0" Authority="RW" Address="0x4000A084" Width="32" Description="frame_byte_cnt1_0.">
|
|
<Bit Name="frame_byte_cnt_1_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr1_1" Authority="RW" Address="0x4000A088" Width="32" Description="frame_start_addr1_1.">
|
|
<Bit Name="frame_start_addr_1_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt1_1" Authority="RW" Address="0x4000A08C" Width="32" Description="frame_byte_cnt1_1.">
|
|
<Bit Name="frame_byte_cnt_1_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr1_2" Authority="RW" Address="0x4000A090" Width="32" Description="frame_start_addr1_2.">
|
|
<Bit Name="frame_start_addr_1_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt1_2" Authority="RW" Address="0x4000A094" Width="32" Description="frame_byte_cnt1_2.">
|
|
<Bit Name="frame_byte_cnt_1_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr1_3" Authority="RW" Address="0x4000A098" Width="32" Description="frame_start_addr1_3.">
|
|
<Bit Name="frame_start_addr_1_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt1_3" Authority="RW" Address="0x4000A09C" Width="32" Description="frame_byte_cnt1_3.">
|
|
<Bit Name="frame_byte_cnt_1_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr1_4" Authority="RW" Address="0x4000A0A0" Width="32" Description="frame_start_addr1_4.">
|
|
<Bit Name="frame_start_addr_1_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt1_4" Authority="RW" Address="0x4000A0A4" Width="32" Description="frame_byte_cnt1_4.">
|
|
<Bit Name="frame_byte_cnt_1_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr1_5" Authority="RW" Address="0x4000A0A8" Width="32" Description="frame_start_addr1_5.">
|
|
<Bit Name="frame_start_addr_1_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt1_5" Authority="RW" Address="0x4000A0AC" Width="32" Description="frame_byte_cnt1_5.">
|
|
<Bit Name="frame_byte_cnt_1_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr1_6" Authority="RW" Address="0x4000A0B0" Width="32" Description="frame_start_addr1_6.">
|
|
<Bit Name="frame_start_addr_1_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt1_6" Authority="RW" Address="0x4000A0B4" Width="32" Description="frame_byte_cnt1_6.">
|
|
<Bit Name="frame_byte_cnt_1_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_start_addr1_7" Authority="RW" Address="0x4000A0B8" Width="32" Description="frame_start_addr1_7.">
|
|
<Bit Name="frame_start_addr_1_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="frame_byte_cnt1_7" Authority="RW" Address="0x4000A0BC" Width="32" Description="frame_byte_cnt1_7.">
|
|
<Bit Name="frame_byte_cnt_1_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="dvp_debug" Authority="RW" Address="0x4000AFF0" Width="32" Description="dvp_debug.">
|
|
<Bit Name="reg_dvp_dbg_sel" Authority="RW" Bits="3-1" />
|
|
<Bit Name="reg_dvp_dbg_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="dvp_dummy_reg" Authority="RW" Address="0x4000AFFC" Width="32" Description="dvp_dummy_reg.">
|
|
<Bit Name="RESERVED_31_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="mjpeg">
|
|
<Register Name="mjpeg_control_1" Authority="RW" Address="0x4000A000" Width="32" Description="mjpeg_control_1.">
|
|
<Bit Name="reg_v0_order" Authority="RW" Bits="31-30" />
|
|
<Bit Name="reg_y1_order" Authority="RW" Bits="29-28" />
|
|
<Bit Name="reg_u0_order" Authority="RW" Bits="27-26" />
|
|
<Bit Name="reg_y0_order" Authority="RW" Bits="25-24" />
|
|
<Bit Name="reg_q_mode" Authority="RW" Bits="22-16" />
|
|
<Bit Name="reg_yuv_mode" Authority="RW" Bits="13-12" />
|
|
<Bit Name="reg_h_bust" Authority="RW" Bits="9-8" />
|
|
<Bit Name="reg_reflect_dmy" Authority="RW" Bits="6" />
|
|
<Bit Name="reg_last_hf_hblk_dmy" Authority="RW" Bits="5" />
|
|
<Bit Name="reg_last_hf_wblk_dmy" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_wr_over_stop" Authority="RW" Bits="3" />
|
|
<Bit Name="reg_order_u_even" Authority="RW" Bits="2" />
|
|
<Bit Name="reg_mjpeg_bit_order" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_mjpeg_enable" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="mjpeg_control_2" Authority="RW" Address="0x4000A004" Width="32" Description="mjpeg_control_2.">
|
|
<Bit Name="reg_mjpeg_wait_cycle" Authority="RW" Bits="31-16" />
|
|
<Bit Name="reg_uv_dvp2ahb_fsel" Authority="RW" Bits="15" />
|
|
<Bit Name="reg_uv_dvp2ahb_lsel" Authority="RW" Bits="14" />
|
|
<Bit Name="reg_yy_dvp2ahb_fsel" Authority="RW" Bits="13" />
|
|
<Bit Name="reg_yy_dvp2ahb_lsel" Authority="RW" Bits="12" />
|
|
<Bit Name="reg_mjpeg_sw_run" Authority="RW" Bits="9" />
|
|
<Bit Name="reg_mjpeg_sw_mode" Authority="RW" Bits="8" />
|
|
<Bit Name="reg_sw_frame" Authority="RW" Bits="4-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_yy_frame_addr" Authority="RW" Address="0x4000Ax08" Width="32" Description="mjpeg_yy_frame_addr.">
|
|
<Bit Name="reg_yy_addr_start" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_uv_frame_addr" Authority="RW" Address="0x4000Ax0C" Width="32" Description="mjpeg_uv_frame_addr.">
|
|
<Bit Name="reg_uv_addr_start" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_yuv_mem" Authority="RW" Address="0x4000A010" Width="32" Description="mjpeg_yuv_mem.">
|
|
<Bit Name="reg_uv_mem_hblk" Authority="RW" Bits="28-16" />
|
|
<Bit Name="reg_yy_mem_hblk" Authority="RW" Bits="12-0" />
|
|
</Register>
|
|
<Register Name="jpeg_frame_addr" Authority="RW" Address="0x4000A014" Width="32" Description="jpeg_frame_addr.">
|
|
<Bit Name="reg_w_addr_start" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="jpeg_store_memory" Authority="RW" Address="0x4000A018" Width="32" Description="jpeg_store_memory.">
|
|
<Bit Name="reg_w_burst_cnt" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_control_3" Authority="RW" Address="0x4000A01C" Width="32" Description="mjpeg_control_3.">
|
|
<Bit Name="sts_swap_int" Authority="RW" Bits="30" />
|
|
<Bit Name="reg_int_swap_en" Authority="RW" Bits="29" />
|
|
<Bit Name="frame_valid_cnt" Authority="RW" Bits="28-24" />
|
|
<Bit Name="sts_idle_int" Authority="RW" Bits="22" />
|
|
<Bit Name="reg_int_idle_en" Authority="RW" Bits="21" />
|
|
<Bit Name="reg_frame_cnt_trgr_int" Authority="RW" Bits="20-16" />
|
|
<Bit Name="ahb_idle" Authority="RW" Bits="14" />
|
|
<Bit Name="mjpeg_manf" Authority="RW" Bits="13" />
|
|
<Bit Name="mjpeg_mans" Authority="RW" Bits="12" />
|
|
<Bit Name="mjpeg_flsh" Authority="RW" Bits="11" />
|
|
<Bit Name="mjpeg_wait" Authority="RW" Bits="10" />
|
|
<Bit Name="mjpeg_func" Authority="RW" Bits="9" />
|
|
<Bit Name="mjpeg_idle" Authority="RW" Bits="8" />
|
|
<Bit Name="sts_frame_int" Authority="RW" Bits="7" />
|
|
<Bit Name="sts_mem_int" Authority="RW" Bits="6" />
|
|
<Bit Name="sts_cam_int" Authority="RW" Bits="5" />
|
|
<Bit Name="sts_normal_int" Authority="RW" Bits="4" />
|
|
<Bit Name="reg_int_frame_en" Authority="RW" Bits="3" />
|
|
<Bit Name="reg_int_mem_en" Authority="RW" Bits="2" />
|
|
<Bit Name="reg_int_cam_en" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_int_normal_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="mjpeg_frame_fifo_pop" Authority="RW" Address="0x4000A020" Width="32" Description="mjpeg_frame_fifo_pop.">
|
|
<Bit Name="reg_int_swap_clr" Authority="RW" Bits="13" />
|
|
<Bit Name="reg_int_idle_clr" Authority="RW" Bits="12" />
|
|
<Bit Name="reg_int_frame_clr" Authority="RW" Bits="11" />
|
|
<Bit Name="reg_int_mem_clr" Authority="RW" Bits="10" />
|
|
<Bit Name="reg_int_cam_clr" Authority="RW" Bits="9" />
|
|
<Bit Name="reg_int_normal_clr" Authority="RW" Bits="8" />
|
|
<Bit Name="reg_w_swap_clr" Authority="RW" Bits="1" />
|
|
<Bit Name="rfifo_pop" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="mjpeg_frame_size" Authority="RW" Address="0x4000A024" Width="32" Description="mjpeg_frame_size.">
|
|
<Bit Name="reg_frame_hblk" Authority="RW" Bits="27-16" />
|
|
<Bit Name="reg_frame_wblk" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_header_byte" Authority="RW" Address="0x4000A028" Width="32" Description="mjpeg_header_byte.">
|
|
<Bit Name="reg_tail_exp" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_head_byte" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_swap_mode" Authority="RW" Address="0x4000A030" Width="32" Description="mjpeg_swap_mode.">
|
|
<Bit Name="sts_swap_fend" Authority="RW" Bits="12" />
|
|
<Bit Name="sts_swap_fstart" Authority="RW" Bits="11" />
|
|
<Bit Name="sts_read_swap_idx" Authority="RW" Bits="10" />
|
|
<Bit Name="sts_swap1_full" Authority="RW" Bits="9" />
|
|
<Bit Name="sts_swap0_full" Authority="RW" Bits="8" />
|
|
<Bit Name="reg_w_swap_mode" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="mjpeg_swap_bit_cnt" Authority="RW" Address="0x4000A034" Width="32" Description="mjpeg_swap_bit_cnt.">
|
|
<Bit Name="frame_swap_end_bit_cnt" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_paket_ctrl" Authority="RW" Address="0x4000A038" Width="32" Description="mjpeg_paket_ctrl.">
|
|
<Bit Name="reg_pket_body_byte" Authority="RW" Bits="31-16" />
|
|
<Bit Name="reg_jend_to_pend" Authority="RW" Bits="1" />
|
|
<Bit Name="reg_pket_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="mjpeg_paket_head_tail" Authority="RW" Address="0x4000Ax3C" Width="32" Description="mjpeg_paket_head_tail.">
|
|
<Bit Name="reg_pket_tail_byte" Authority="RW" Bits="27-16" />
|
|
<Bit Name="reg_pket_head_byte" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_Y_frame_read_status_1" Authority="RW" Address="0x4000A040" Width="32" Description="mjpeg_Y_frame_read_status_1.">
|
|
<Bit Name="yy_frm_hblk_r" Authority="RW" Bits="28-16" />
|
|
<Bit Name="yy_mem_hblk_r" Authority="RW" Bits="12-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_Y_frame_read_status_2" Authority="RW" Address="0x4000A044" Width="32" Description="mjpeg_Y_frame_read_status_2.">
|
|
<Bit Name="yy_frm_cnt_r" Authority="RW" Bits="31-24" />
|
|
<Bit Name="yy_mem_rnd_r" Authority="RW" Bits="23-16" />
|
|
<Bit Name="yy_wblk_r" Authority="RW" Bits="12-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_Y_frame_write_status" Authority="RW" Address="0x4000A048" Width="32" Description="mjpeg_Y_frame_write_status.">
|
|
<Bit Name="yy_frm_cnt_w" Authority="RW" Bits="31-24" />
|
|
<Bit Name="yy_mem_rnd_w" Authority="RW" Bits="23-16" />
|
|
<Bit Name="yy_mem_hblk_w" Authority="RW" Bits="12-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_UV_frame_read_status_1" Authority="RW" Address="0x4000Ax4C" Width="32" Description="mjpeg_UV_frame_read_status_1.">
|
|
<Bit Name="uv_frm_hblk_r" Authority="RW" Bits="28-16" />
|
|
<Bit Name="uv_mem_hblk_r" Authority="RW" Bits="12-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_UV_frame_read_status_2" Authority="RW" Address="0x4000A050" Width="32" Description="mjpeg_UV_frame_read_status_2.">
|
|
<Bit Name="uv_frm_cnt_r" Authority="RW" Bits="31-24" />
|
|
<Bit Name="uv_mem_rnd_r" Authority="RW" Bits="23-16" />
|
|
<Bit Name="uv_wblk_r" Authority="RW" Bits="12-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_UV_frame_write_status" Authority="RW" Address="0x4000A054" Width="32" Description="mjpeg_UV_frame_write_status.">
|
|
<Bit Name="uv_frm_cnt_w" Authority="RW" Bits="31-24" />
|
|
<Bit Name="uv_mem_rnd_w" Authority="RW" Bits="23-16" />
|
|
<Bit Name="uv_mem_hblk_w" Authority="RW" Bits="12-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr0" Authority="RW" Address="0x4000A080" Width="32" Description="mjpeg_start_addr0.">
|
|
<Bit Name="frame_start_addr_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt0" Authority="RW" Address="0x4000A084" Width="32" Description="mjpeg_bit_cnt0.">
|
|
<Bit Name="frame_bit_cnt_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr1" Authority="RW" Address="0x4000A088" Width="32" Description="mjpeg_start_addr1.">
|
|
<Bit Name="frame_start_addr_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt1" Authority="RW" Address="0x4000A08C" Width="32" Description="mjpeg_bit_cnt1.">
|
|
<Bit Name="frame_bit_cnt_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr2" Authority="RW" Address="0x4000A090" Width="32" Description="mjpeg_start_addr2.">
|
|
<Bit Name="frame_start_addr_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt2" Authority="RW" Address="0x4000A094" Width="32" Description="mjpeg_bit_cnt2.">
|
|
<Bit Name="frame_bit_cnt_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr3" Authority="RW" Address="0x4000A098" Width="32" Description="mjpeg_start_addr3.">
|
|
<Bit Name="frame_start_addr_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt3" Authority="RW" Address="0x4000A09C" Width="32" Description="mjpeg_bit_cnt3.">
|
|
<Bit Name="frame_bit_cnt_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr4" Authority="RW" Address="0x4000A0A0" Width="32" Description="mjpeg_start_addr4.">
|
|
<Bit Name="frame_start_addr_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt4" Authority="RW" Address="0x4000A0A4" Width="32" Description="mjpeg_bit_cnt4.">
|
|
<Bit Name="frame_bit_cnt_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr5" Authority="RW" Address="0x4000A0A8" Width="32" Description="mjpeg_start_addr5.">
|
|
<Bit Name="frame_start_addr_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt5" Authority="RW" Address="0x4000A0AC" Width="32" Description="mjpeg_bit_cnt5.">
|
|
<Bit Name="frame_bit_cnt_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr6" Authority="RW" Address="0x4000A0B0" Width="32" Description="mjpeg_start_addr6.">
|
|
<Bit Name="frame_start_addr_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt6" Authority="RW" Address="0x4000A0B4" Width="32" Description="mjpeg_bit_cnt6.">
|
|
<Bit Name="frame_bit_cnt_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr7" Authority="RW" Address="0x4000A0B8" Width="32" Description="mjpeg_start_addr7.">
|
|
<Bit Name="frame_start_addr_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt7" Authority="RW" Address="0x4000A0BC" Width="32" Description="mjpeg_bit_cnt7.">
|
|
<Bit Name="frame_bit_cnt_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr_8" Authority="RW" Address="0x4000A0C0" Width="32" Description="mjpeg_start_addr_8.">
|
|
<Bit Name="frame_start_addr_8" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt_8" Authority="RW" Address="0x4000A0C4" Width="32" Description="mjpeg_bit_cnt_8.">
|
|
<Bit Name="frame_bit_cnt_8" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr_9" Authority="RW" Address="0x4000A0C8" Width="32" Description="mjpeg_start_addr_9.">
|
|
<Bit Name="frame_start_addr_9" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt_9" Authority="RW" Address="0x4000A0CC" Width="32" Description="mjpeg_bit_cnt_9.">
|
|
<Bit Name="frame_bit_cnt_9" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr_a" Authority="RW" Address="0x4000A0D0" Width="32" Description="mjpeg_start_addr_a.">
|
|
<Bit Name="frame_start_addr_a" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt_a" Authority="RW" Address="0x4000A0D4" Width="32" Description="mjpeg_bit_cnt_a.">
|
|
<Bit Name="frame_bit_cnt_a" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr_b" Authority="RW" Address="0x4000A0D8" Width="32" Description="mjpeg_start_addr_b.">
|
|
<Bit Name="frame_start_addr_b" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt_b" Authority="RW" Address="0x4000A0DC" Width="32" Description="mjpeg_bit_cnt_b.">
|
|
<Bit Name="frame_bit_cnt_b" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr_c" Authority="RW" Address="0x4000A0E0" Width="32" Description="mjpeg_start_addr_c.">
|
|
<Bit Name="frame_start_addr_c" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt_c" Authority="RW" Address="0x4000A0E4" Width="32" Description="mjpeg_bit_cnt_c.">
|
|
<Bit Name="frame_bit_cnt_c" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr_d" Authority="RW" Address="0x4000A0E8" Width="32" Description="mjpeg_start_addr_d.">
|
|
<Bit Name="frame_start_addr_d" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt_d" Authority="RW" Address="0x4000A0EC" Width="32" Description="mjpeg_bit_cnt_d.">
|
|
<Bit Name="frame_bit_cnt_d" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr_e" Authority="RW" Address="0x4000A0F0" Width="32" Description="mjpeg_start_addr_e.">
|
|
<Bit Name="frame_start_addr_e" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt_e" Authority="RW" Address="0x4000A0F4" Width="32" Description="mjpeg_bit_cnt_e.">
|
|
<Bit Name="frame_bit_cnt_e" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_start_addr_f" Authority="RW" Address="0x4000A0F8" Width="32" Description="mjpeg_start_addr_f.">
|
|
<Bit Name="frame_start_addr_f" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_bit_cnt_f" Authority="RW" Address="0x4000A0FC" Width="32" Description="mjpeg_bit_cnt_f.">
|
|
<Bit Name="frame_bit_cnt_f" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode0" Authority="RW" Address="0x4000A100" Width="32" Description="mjpeg_q_mode0.">
|
|
<Bit Name="frame_q_mode_0" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode1" Authority="RW" Address="0x4000A104" Width="32" Description="mjpeg_q_mode1.">
|
|
<Bit Name="frame_q_mode_1" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode2" Authority="RW" Address="0x4000A108" Width="32" Description="mjpeg_q_mode2.">
|
|
<Bit Name="frame_q_mode_2" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode3" Authority="RW" Address="0x4000A10C" Width="32" Description="mjpeg_q_mode3.">
|
|
<Bit Name="frame_q_mode_3" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode4" Authority="RW" Address="0x4000A110" Width="32" Description="mjpeg_q_mode4.">
|
|
<Bit Name="frame_q_mode_4" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode5" Authority="RW" Address="0x4000A114" Width="32" Description="mjpeg_q_mode5.">
|
|
<Bit Name="frame_q_mode_5" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode6" Authority="RW" Address="0x4000A118" Width="32" Description="mjpeg_q_mode6.">
|
|
<Bit Name="frame_q_mode_6" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode7" Authority="RW" Address="0x4000A11C" Width="32" Description="mjpeg_q_mode7.">
|
|
<Bit Name="frame_q_mode_7" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode_8" Authority="RW" Address="0x4000A120" Width="32" Description="mjpeg_q_mode_8.">
|
|
<Bit Name="frame_q_mode_8" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode_9" Authority="RW" Address="0x4000A124" Width="32" Description="mjpeg_q_mode_9.">
|
|
<Bit Name="frame_q_mode_9" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode_a" Authority="RW" Address="0x4000A128" Width="32" Description="mjpeg_q_mode_a.">
|
|
<Bit Name="frame_q_mode_a" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode_b" Authority="RW" Address="0x4000A12C" Width="32" Description="mjpeg_q_mode_b.">
|
|
<Bit Name="frame_q_mode_b" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode_c" Authority="RW" Address="0x4000A130" Width="32" Description="mjpeg_q_mode_c.">
|
|
<Bit Name="frame_q_mode_c" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode_d" Authority="RW" Address="0x4000A134" Width="32" Description="mjpeg_q_mode_d.">
|
|
<Bit Name="frame_q_mode_d" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode_e" Authority="RW" Address="0x4000A138" Width="32" Description="mjpeg_q_mode_e.">
|
|
<Bit Name="frame_q_mode_e" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_q_mode_f" Authority="RW" Address="0x4000A13C" Width="32" Description="mjpeg_q_mode_f.">
|
|
<Bit Name="frame_q_mode_f" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="mjpeg_debug" Authority="RW" Address="0x4000A1F0" Width="32" Description="mjpeg_debug.">
|
|
<Bit Name="reg_mjpeg_dbg_sel" Authority="RW" Bits="7-4" />
|
|
<Bit Name="reg_mjpeg_dbg_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="mjpeg_dummy_reg" Authority="RW" Address="0x4000A1FC" Width="32" Description="mjpeg_dummy_reg.">
|
|
<Bit Name="mjpeg_dummy_reg" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="sf_ctrl">
|
|
<Register Name="sf_ctrl_0" Authority="RW" Address="0x4000B000" Width="32" Description="sf_ctrl_0.">
|
|
<Bit Name="sf_id" Authority="RW" Bits="31-24" />
|
|
<Bit Name="sf_aes_iv_endian" Authority="RW" Bits="23" />
|
|
<Bit Name="sf_aes_key_endian" Authority="RW" Bits="22" />
|
|
<Bit Name="sf_aes_ctr_plus_en" Authority="RW" Bits="21" />
|
|
<Bit Name="sf_aes_dout_endian" Authority="RW" Bits="20" />
|
|
<Bit Name="sf_aes_dly_mode" Authority="RW" Bits="19" />
|
|
<Bit Name="sf_if_int_set" Authority="RW" Bits="18" />
|
|
<Bit Name="sf_if_int_clr" Authority="RW" Bits="17" />
|
|
<Bit Name="sf_if_int" Authority="RW" Bits="16" />
|
|
<Bit Name="sf_if_read_dly_en" Authority="RW" Bits="11" />
|
|
<Bit Name="sf_if_read_dly_n" Authority="RW" Bits="10-8" />
|
|
<Bit Name="sf_clk_sahb_sram_sel" Authority="RW" Bits="5" />
|
|
<Bit Name="sf_clk_out_inv_sel" Authority="RW" Bits="4" />
|
|
<Bit Name="sf_clk_out_gate_en" Authority="RW" Bits="3" />
|
|
<Bit Name="sf_clk_sf_rx_inv_sel" Authority="RW" Bits="2" />
|
|
</Register>
|
|
<Register Name="sf_ctrl_1" Authority="RW" Address="0x4000B004" Width="32" Description="sf_ctrl_1.">
|
|
<Bit Name="sf_ahb2sram_en" Authority="RW" Bits="31" />
|
|
<Bit Name="sf_ahb2sif_en" Authority="RW" Bits="30" />
|
|
<Bit Name="sf_if_en" Authority="RW" Bits="29" />
|
|
<Bit Name="sf_if_fn_sel" Authority="RW" Bits="28" />
|
|
<Bit Name="sf_ahb2sif_stop" Authority="RW" Bits="27" />
|
|
<Bit Name="sf_ahb2sif_stopped" Authority="RW" Bits="26" />
|
|
<Bit Name="sf_if_reg_wp" Authority="RW" Bits="25" />
|
|
<Bit Name="sf_if_reg_hold" Authority="RW" Bits="24" />
|
|
<Bit Name="sf_if_0_ack_lat" Authority="RW" Bits="22-20" />
|
|
<Bit Name="sf_if_sr_int_set" Authority="RW" Bits="18" />
|
|
<Bit Name="sf_if_sr_int_en" Authority="RW" Bits="17" />
|
|
<Bit Name="sf_if_sr_int" Authority="RW" Bits="16" />
|
|
<Bit Name="sf_if_sr_pat" Authority="RW" Bits="15-8" />
|
|
<Bit Name="sf_if_sr_pat_mask" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="sf_if_sahb_0" Authority="RW" Address="0x4000B008" Width="32" Description="sf_if_sahb_0.">
|
|
<Bit Name="sf_if_0_qpi_mode_en" Authority="RW" Bits="31" />
|
|
<Bit Name="sf_if_0_spi_mode" Authority="RW" Bits="30-28" />
|
|
<Bit Name="sf_if_0_cmd_en" Authority="RW" Bits="27" />
|
|
<Bit Name="sf_if_0_adr_en" Authority="RW" Bits="26" />
|
|
<Bit Name="sf_if_0_dmy_en" Authority="RW" Bits="25" />
|
|
<Bit Name="sf_if_0_dat_en" Authority="RW" Bits="24" />
|
|
<Bit Name="sf_if_0_dat_rw " Authority="RW" Bits="23" />
|
|
<Bit Name="sf_if_0_cmd_byte" Authority="RW" Bits="22-20" />
|
|
<Bit Name="sf_if_0_adr_byte" Authority="RW" Bits="19-17" />
|
|
<Bit Name="sf_if_0_dmy_byte" Authority="RW" Bits="16-12" />
|
|
<Bit Name="sf_if_0_dat_byte" Authority="RW" Bits="11-2" />
|
|
<Bit Name="sf_if_0_trig" Authority="RW" Bits="1" />
|
|
<Bit Name="sf_if_busy" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="sf_if_sahb_1" Authority="RW" Address="0x4000B00C" Width="32" Description="sf_if_sahb_1.">
|
|
<Bit Name="sf_if_0_cmd_buf_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_if_sahb_2" Authority="RW" Address="0x4000B010" Width="32" Description="sf_if_sahb_2.">
|
|
<Bit Name="sf_if_0_cmd_buf_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_if_iahb_0" Authority="RW" Address="0x4000B014" Width="32" Description="sf_if_iahb_0.">
|
|
<Bit Name="sf_if_1_qpi_mode_en" Authority="RW" Bits="31" />
|
|
<Bit Name="sf_if_1_spi_mode" Authority="RW" Bits="30-28" />
|
|
<Bit Name="sf_if_1_cmd_en" Authority="RW" Bits="27" />
|
|
<Bit Name="sf_if_1_adr_en" Authority="RW" Bits="26" />
|
|
<Bit Name="sf_if_1_dmy_en" Authority="RW" Bits="25" />
|
|
<Bit Name="sf_if_1_dat_en" Authority="RW" Bits="24" />
|
|
<Bit Name="sf_if_1_dat_rw " Authority="RW" Bits="23" />
|
|
<Bit Name="sf_if_1_cmd_byte" Authority="RW" Bits="22-20" />
|
|
<Bit Name="sf_if_1_adr_byte" Authority="RW" Bits="19-17" />
|
|
<Bit Name="sf_if_1_dmy_byte" Authority="RW" Bits="16-12" />
|
|
</Register>
|
|
<Register Name="sf_if_iahb_1" Authority="RW" Address="0x4000B018" Width="32" Description="sf_if_iahb_1.">
|
|
<Bit Name="sf_if_1_cmd_buf_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_if_iahb_2" Authority="RW" Address="0x4000B01C" Width="32" Description="sf_if_iahb_2.">
|
|
<Bit Name="sf_if_1_cmd_buf_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_if_status_0" Authority="RW" Address="0x4000B020" Width="32" Description="sf_if_status_0.">
|
|
<Bit Name="sf_if_status_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_if_status_1" Authority="RW" Address="0x4000B024" Width="32" Description="sf_if_status_1.">
|
|
<Bit Name="sf_if_status_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes" Authority="RW" Address="0x4000B028" Width="32" Description="sf_aes.">
|
|
<Bit Name="sf_aes_status" Authority="RW" Bits="31-5" />
|
|
<Bit Name="sf_aes_pref_busy" Authority="RW" Bits="4" />
|
|
<Bit Name="sf_aes_pref_trig" Authority="RW" Bits="3" />
|
|
<Bit Name="sf_aes_mode" Authority="RW" Bits="2-1" />
|
|
<Bit Name="sf_aes_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="sf_ahb2sif_status" Authority="RW" Address="0x4000Bx2C" Width="32" Description="sf_ahb2sif_status.">
|
|
<Bit Name="sf_ahb2sif_status" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_if_io_dly_0" Authority="RW" Address="0x4000B030" Width="32" Description="sf_if_io_dly_0.">
|
|
<Bit Name="sf_dqs_do_dly_sel" Authority="RW" Bits="31-30" />
|
|
<Bit Name="sf_dqs_di_dly_sel" Authority="RW" Bits="29-28" />
|
|
<Bit Name="sf_dqs_oe_dly_sel" Authority="RW" Bits="27-26" />
|
|
<Bit Name="sf_clk_out_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf_cs2_dly_sel" Authority="RW" Bits="3-2" />
|
|
<Bit Name="sf_cs_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf_if_io_dly_1" Authority="RW" Address="0x4000B034" Width="32" Description="sf_if_io_dly_1.">
|
|
<Bit Name="sf_io_0_do_dly_sel" Authority="RW" Bits="17-16" />
|
|
<Bit Name="sf_io_0_di_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf_io_0_oe_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf_if_io_dly_2" Authority="RW" Address="0x4000B038" Width="32" Description="sf_if_io_dly_2.">
|
|
<Bit Name="sf_io_1_do_dly_sel" Authority="RW" Bits="17-16" />
|
|
<Bit Name="sf_io_1_di_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf_io_1_oe_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf_if_io_dly_3" Authority="RW" Address="0x4000Bx3C" Width="32" Description="sf_if_io_dly_3.">
|
|
<Bit Name="sf_io_2_do_dly_sel" Authority="RW" Bits="17-16" />
|
|
<Bit Name="sf_io_2_di_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf_io_2_oe_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf_if_io_dly_4" Authority="RW" Address="0x4000B040" Width="32" Description="sf_if_io_dly_4.">
|
|
<Bit Name="sf_io_3_do_dly_sel" Authority="RW" Bits="17-16" />
|
|
<Bit Name="sf_io_3_di_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf_io_3_oe_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf_reserved" Authority="RW" Address="0x4000B044" Width="32" Description="sf_reserved.">
|
|
<Bit Name="sf_reserved" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf2_if_io_dly_0" Authority="RW" Address="0x4000B048" Width="32" Description="sf2_if_io_dly_0.">
|
|
<Bit Name="sf2_dqs_do_dly_sel" Authority="RW" Bits="31-30" />
|
|
<Bit Name="sf2_dqs_di_dly_sel" Authority="RW" Bits="29-28" />
|
|
<Bit Name="sf2_dqs_oe_dly_sel" Authority="RW" Bits="27-26" />
|
|
<Bit Name="sf2_clk_out_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf2_cs2_dly_sel" Authority="RW" Bits="3-2" />
|
|
<Bit Name="sf2_cs_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf2_if_io_dly_1" Authority="RW" Address="0x4000Bx4C" Width="32" Description="sf2_if_io_dly_1.">
|
|
<Bit Name="sf2_io_0_do_dly_sel" Authority="RW" Bits="17-16" />
|
|
<Bit Name="sf2_io_0_di_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf2_io_0_oe_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf2_if_io_dly_2" Authority="RW" Address="0x4000B050" Width="32" Description="sf2_if_io_dly_2.">
|
|
<Bit Name="sf2_io_1_do_dly_sel" Authority="RW" Bits="17-16" />
|
|
<Bit Name="sf2_io_1_di_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf2_io_1_oe_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf2_if_io_dly_3" Authority="RW" Address="0x4000B054" Width="32" Description="sf2_if_io_dly_3.">
|
|
<Bit Name="sf2_io_2_do_dly_sel" Authority="RW" Bits="17-16" />
|
|
<Bit Name="sf2_io_2_di_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf2_io_2_oe_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf2_if_io_dly_4" Authority="RW" Address="0x4000B058" Width="32" Description="sf2_if_io_dly_4.">
|
|
<Bit Name="sf2_io_3_do_dly_sel" Authority="RW" Bits="17-16" />
|
|
<Bit Name="sf2_io_3_di_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf2_io_3_oe_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf3_if_io_dly_0" Authority="RW" Address="0x4000Bx5C" Width="32" Description="sf3_if_io_dly_0.">
|
|
<Bit Name="sf3_dqs_do_dly_sel" Authority="RW" Bits="31-30" />
|
|
<Bit Name="sf3_dqs_di_dly_sel" Authority="RW" Bits="29-28" />
|
|
<Bit Name="sf3_dqs_oe_dly_sel" Authority="RW" Bits="27-26" />
|
|
<Bit Name="sf3_clk_out_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf3_cs2_dly_sel" Authority="RW" Bits="3-2" />
|
|
<Bit Name="sf3_cs_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf3_if_io_dly_1" Authority="RW" Address="0x4000B060" Width="32" Description="sf3_if_io_dly_1.">
|
|
<Bit Name="sf3_io_0_do_dly_sel" Authority="RW" Bits="17-16" />
|
|
<Bit Name="sf3_io_0_di_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf3_io_0_oe_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf3_if_io_dly_2" Authority="RW" Address="0x4000B064" Width="32" Description="sf3_if_io_dly_2.">
|
|
<Bit Name="sf3_io_1_do_dly_sel" Authority="RW" Bits="17-16" />
|
|
<Bit Name="sf3_io_1_di_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf3_io_1_oe_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf3_if_io_dly_3" Authority="RW" Address="0x4000B068" Width="32" Description="sf3_if_io_dly_3.">
|
|
<Bit Name="sf3_io_2_do_dly_sel" Authority="RW" Bits="17-16" />
|
|
<Bit Name="sf3_io_2_di_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf3_io_2_oe_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf3_if_io_dly_4" Authority="RW" Address="0x4000Bx6C" Width="32" Description="sf3_if_io_dly_4.">
|
|
<Bit Name="sf3_io_3_do_dly_sel" Authority="RW" Bits="17-16" />
|
|
<Bit Name="sf3_io_3_di_dly_sel" Authority="RW" Bits="9-8" />
|
|
<Bit Name="sf3_io_3_oe_dly_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf_ctrl_2" Authority="RW" Address="0x4000B070" Width="32" Description="sf_ctrl_2.">
|
|
<Bit Name="sf_if_0_bk_sel" Authority="RW" Bits="31" />
|
|
<Bit Name="sf_if_bk2_en" Authority="RW" Bits="30" />
|
|
<Bit Name="sf_if_bk2_mode" Authority="RW" Bits="29" />
|
|
<Bit Name="sf_if_bk_swap" Authority="RW" Bits="28" />
|
|
<Bit Name="sf_if_dqs_en" Authority="RW" Bits="5" />
|
|
<Bit Name="sf_if_dtr_en" Authority="RW" Bits="4" />
|
|
<Bit Name="sf_if_pad_sel_lock" Authority="RW" Bits="3" />
|
|
<Bit Name="sf_if_pad_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="sf_ctrl_3" Authority="RW" Address="0x4000B074" Width="32" Description="sf_ctrl_3.">
|
|
<Bit Name="sf_if_1_ack_lat" Authority="RW" Bits="31-29" />
|
|
<Bit Name="sf_cmds_wrap_q" Authority="RW" Bits="11" />
|
|
<Bit Name="sf_cmds_wrap_mode" Authority="RW" Bits="10" />
|
|
<Bit Name="sf_cmds_wrap_q_ini" Authority="RW" Bits="9" />
|
|
<Bit Name="sf_cmds_bt_en" Authority="RW" Bits="8" />
|
|
<Bit Name="sf_cmds_bt_dly" Authority="RW" Bits="7-5" />
|
|
<Bit Name="sf_cmds_en" Authority="RW" Bits="4" />
|
|
<Bit Name="sf_cmds_wrap_len" Authority="RW" Bits="3-0" />
|
|
</Register>
|
|
<Register Name="sf_if_iahb_3" Authority="RW" Address="0x4000B078" Width="32" Description="sf_if_iahb_3.">
|
|
<Bit Name="sf_if_2_qpi_mode_en" Authority="RW" Bits="31" />
|
|
<Bit Name="sf_if_2_spi_mode" Authority="RW" Bits="30-28" />
|
|
<Bit Name="sf_if_2_cmd_en" Authority="RW" Bits="27" />
|
|
<Bit Name="sf_if_2_adr_en" Authority="RW" Bits="26" />
|
|
<Bit Name="sf_if_2_dmy_en" Authority="RW" Bits="25" />
|
|
<Bit Name="sf_if_2_dat_en" Authority="RW" Bits="24" />
|
|
<Bit Name="sf_if_2_dat_rw " Authority="RW" Bits="23" />
|
|
<Bit Name="sf_if_2_cmd_byte" Authority="RW" Bits="22-20" />
|
|
<Bit Name="sf_if_2_adr_byte" Authority="RW" Bits="19-17" />
|
|
<Bit Name="sf_if_2_dmy_byte" Authority="RW" Bits="16-12" />
|
|
</Register>
|
|
<Register Name="sf_if_iahb_4" Authority="RW" Address="0x4000B07C" Width="32" Description="sf_if_iahb_4.">
|
|
<Bit Name="sf_if_2_cmd_buf_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_if_iahb_5" Authority="RW" Address="0x4000B080" Width="32" Description="sf_if_iahb_5.">
|
|
<Bit Name="sf_if_2_cmd_buf_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_if_iahb_6" Authority="RW" Address="0x4000B084" Width="32" Description="sf_if_iahb_6.">
|
|
<Bit Name="sf_if_3_qpi_mode_en" Authority="RW" Bits="31" />
|
|
<Bit Name="sf_if_3_spi_mode" Authority="RW" Bits="30-28" />
|
|
<Bit Name="sf_if_3_cmd_en" Authority="RW" Bits="27" />
|
|
<Bit Name="sf_if_3_adr_en" Authority="RW" Bits="26" />
|
|
<Bit Name="sf_if_3_cmd_byte" Authority="RW" Bits="22-20" />
|
|
<Bit Name="sf_if_3_adr_byte" Authority="RW" Bits="19-17" />
|
|
</Register>
|
|
<Register Name="sf_if_iahb_7" Authority="RW" Address="0x4000B088" Width="32" Description="sf_if_iahb_7.">
|
|
<Bit Name="sf_if_3_cmd_buf_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_if_iahb_8" Authority="RW" Address="0x4000B08C" Width="32" Description="sf_if_iahb_8.">
|
|
<Bit Name="sf_if_3_cmd_buf_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_if_iahb_9" Authority="RW" Address="0x4000B090" Width="32" Description="sf_if_iahb_9.">
|
|
<Bit Name="sf_if_4_qpi_mode_en" Authority="RW" Bits="31" />
|
|
<Bit Name="sf_if_4_spi_mode" Authority="RW" Bits="30-28" />
|
|
<Bit Name="sf_if_4_cmd_en" Authority="RW" Bits="27" />
|
|
<Bit Name="sf_if_4_adr_en" Authority="RW" Bits="26" />
|
|
<Bit Name="sf_if_4_dmy_en" Authority="RW" Bits="25" />
|
|
<Bit Name="sf_if_4_dat_en" Authority="RW" Bits="24" />
|
|
<Bit Name="sf_if_4_dat_rw " Authority="RW" Bits="23" />
|
|
<Bit Name="sf_if_4_cmd_byte" Authority="RW" Bits="22-20" />
|
|
<Bit Name="sf_if_4_adr_byte" Authority="RW" Bits="19-17" />
|
|
<Bit Name="sf_if_4_dmy_byte" Authority="RW" Bits="16-12" />
|
|
</Register>
|
|
<Register Name="sf_if_iahb_10" Authority="RW" Address="0x4000B094" Width="32" Description="sf_if_iahb_10.">
|
|
<Bit Name="sf_if_4_cmd_buf_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_if_iahb_11" Authority="RW" Address="0x4000B098" Width="32" Description="sf_if_iahb_11.">
|
|
<Bit Name="sf_if_4_cmd_buf_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_if_iahb_12" Authority="RW" Address="0x4000B09C" Width="32" Description="sf_if_iahb_12.">
|
|
<Bit Name="sf2_if_read_dly_src" Authority="RW" Bits="12" />
|
|
<Bit Name="sf2_if_read_dly_en" Authority="RW" Bits="11" />
|
|
<Bit Name="sf2_if_read_dly_n" Authority="RW" Bits="10-8" />
|
|
<Bit Name="sf3_clk_out_inv_sel" Authority="RW" Bits="5" />
|
|
<Bit Name="sf2_clk_out_inv_sel" Authority="RW" Bits="4" />
|
|
<Bit Name="sf2_clk_sf_rx_inv_src" Authority="RW" Bits="3" />
|
|
<Bit Name="sf2_clk_sf_rx_inv_sel" Authority="RW" Bits="2" />
|
|
</Register>
|
|
<Register Name="sf_ctrl_prot_en_rd" Authority="RW" Address="0x4000B100" Width="32" Description="sf_ctrl_prot_en_rd.">
|
|
<Bit Name="sf_dbg_dis" Authority="RW" Bits="31" />
|
|
<Bit Name="sf_if_0_trig_wr_lock" Authority="RW" Bits="30" />
|
|
<Bit Name="sf_ctrl_id1_en_rd" Authority="RW" Bits="2" />
|
|
<Bit Name="sf_ctrl_id0_en_rd" Authority="RW" Bits="1" />
|
|
<Bit Name="sf_ctrl_prot_en_rd" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="sf_ctrl_prot_en" Authority="RW" Address="0x4000B104" Width="32" Description="sf_ctrl_prot_en.">
|
|
<Bit Name="sf_ctrl_id1_en" Authority="RW" Bits="2" />
|
|
<Bit Name="sf_ctrl_id0_en" Authority="RW" Bits="1" />
|
|
<Bit Name="sf_ctrl_prot_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r0_0" Authority="RW" Address="0x4000B200" Width="32" Description="sf_aes_key_r0_0.">
|
|
<Bit Name="sf_aes_key_r0_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r0_1" Authority="RW" Address="0x4000B204" Width="32" Description="sf_aes_key_r0_1.">
|
|
<Bit Name="sf_aes_key_r0_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r0_2" Authority="RW" Address="0x4000B208" Width="32" Description="sf_aes_key_r0_2.">
|
|
<Bit Name="sf_aes_key_r0_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r0_3" Authority="RW" Address="0x4000B20C" Width="32" Description="sf_aes_key_r0_3.">
|
|
<Bit Name="sf_aes_key_r0_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r0_4" Authority="RW" Address="0x4000B210" Width="32" Description="sf_aes_key_r0_4.">
|
|
<Bit Name="sf_aes_key_r0_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r0_5" Authority="RW" Address="0x4000B214" Width="32" Description="sf_aes_key_r0_5.">
|
|
<Bit Name="sf_aes_key_r0_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r0_6" Authority="RW" Address="0x4000B218" Width="32" Description="sf_aes_key_r0_6.">
|
|
<Bit Name="sf_aes_key_r0_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r0_7" Authority="RW" Address="0x4000B21C" Width="32" Description="sf_aes_key_r0_7.">
|
|
<Bit Name="sf_aes_key_r0_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_iv_r0_w0" Authority="RW" Address="0x4000B220" Width="32" Description="sf_aes_iv_r0_w0.">
|
|
<Bit Name="sf_aes_iv_r0_w0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_iv_r0_w1" Authority="RW" Address="0x4000B224" Width="32" Description="sf_aes_iv_r0_w1.">
|
|
<Bit Name="sf_aes_iv_r0_w1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_iv_r0_w2" Authority="RW" Address="0x4000B228" Width="32" Description="sf_aes_iv_r0_w2.">
|
|
<Bit Name="sf_aes_iv_r0_w2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_iv_r0_w3" Authority="RW" Address="0x4000B22C" Width="32" Description="sf_aes_iv_r0_w3.">
|
|
<Bit Name="sf_aes_iv_r0_w3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_cfg_r0" Authority="RW" Address="0x4000B230" Width="32" Description="sf_aes_cfg_r0.">
|
|
<Bit Name="sf_aes_region_r0_lock" Authority="RW" Bits="31" />
|
|
<Bit Name="sf_aes_region_r0_en" Authority="RW" Bits="30" />
|
|
<Bit Name="sf_aes_region_r0_hw_key_en" Authority="RW" Bits="29" />
|
|
<Bit Name="sf_aes_region_r0_start" Authority="RW" Bits="27-14" />
|
|
<Bit Name="sf_aes_region_r0_end" Authority="RW" Bits="13-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r1_0" Authority="RW" Address="0x4000B300" Width="32" Description="sf_aes_key_r1_0.">
|
|
<Bit Name="sf_aes_key_r1_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r1_1" Authority="RW" Address="0x4000B304" Width="32" Description="sf_aes_key_r1_1.">
|
|
<Bit Name="sf_aes_key_r1_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r1_2" Authority="RW" Address="0x4000B308" Width="32" Description="sf_aes_key_r1_2.">
|
|
<Bit Name="sf_aes_key_r1_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r1_3" Authority="RW" Address="0x4000B30C" Width="32" Description="sf_aes_key_r1_3.">
|
|
<Bit Name="sf_aes_key_r1_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r1_4" Authority="RW" Address="0x4000B310" Width="32" Description="sf_aes_key_r1_4.">
|
|
<Bit Name="sf_aes_key_r1_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r1_5" Authority="RW" Address="0x4000B314" Width="32" Description="sf_aes_key_r1_5.">
|
|
<Bit Name="sf_aes_key_r1_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r1_6" Authority="RW" Address="0x4000B318" Width="32" Description="sf_aes_key_r1_6.">
|
|
<Bit Name="sf_aes_key_r1_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r1_7" Authority="RW" Address="0x4000B31C" Width="32" Description="sf_aes_key_r1_7.">
|
|
<Bit Name="sf_aes_key_r1_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_iv_r1_w0" Authority="RW" Address="0x4000B320" Width="32" Description="sf_aes_iv_r1_w0.">
|
|
<Bit Name="sf_aes_iv_r1_w0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_iv_r1_w1" Authority="RW" Address="0x4000B324" Width="32" Description="sf_aes_iv_r1_w1.">
|
|
<Bit Name="sf_aes_iv_r1_w1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_iv_r1_w2" Authority="RW" Address="0x4000B328" Width="32" Description="sf_aes_iv_r1_w2.">
|
|
<Bit Name="sf_aes_iv_r1_w2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_iv_r1_w3" Authority="RW" Address="0x4000B32C" Width="32" Description="sf_aes_iv_r1_w3.">
|
|
<Bit Name="sf_aes_iv_r1_w3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_r1" Authority="RW" Address="0x4000B330" Width="32" Description="sf_aes_r1.">
|
|
<Bit Name="sf_aes_r1_lock" Authority="RW" Bits="31" />
|
|
<Bit Name="sf_aes_r1_en" Authority="RW" Bits="30" />
|
|
<Bit Name="sf_aes_r1_hw_key_en" Authority="RW" Bits="29" />
|
|
<Bit Name="sf_aes_r1_start" Authority="RW" Bits="27-14" />
|
|
<Bit Name="sf_aes_r1_end" Authority="RW" Bits="13-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r2_0" Authority="RW" Address="0x4000B400" Width="32" Description="sf_aes_key_r2_0.">
|
|
<Bit Name="sf_aes_key_r2_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r2_1" Authority="RW" Address="0x4000B404" Width="32" Description="sf_aes_key_r2_1.">
|
|
<Bit Name="sf_aes_key_r2_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r2_2" Authority="RW" Address="0x4000B408" Width="32" Description="sf_aes_key_r2_2.">
|
|
<Bit Name="sf_aes_key_r2_2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r2_3" Authority="RW" Address="0x4000B40C" Width="32" Description="sf_aes_key_r2_3.">
|
|
<Bit Name="sf_aes_key_r2_3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r2_4" Authority="RW" Address="0x4000B410" Width="32" Description="sf_aes_key_r2_4.">
|
|
<Bit Name="sf_aes_key_r2_4" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r2_5" Authority="RW" Address="0x4000B414" Width="32" Description="sf_aes_key_r2_5.">
|
|
<Bit Name="sf_aes_key_r2_5" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r2_6" Authority="RW" Address="0x4000B418" Width="32" Description="sf_aes_key_r2_6.">
|
|
<Bit Name="sf_aes_key_r2_6" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_key_r2_7" Authority="RW" Address="0x4000B41C" Width="32" Description="sf_aes_key_r2_7.">
|
|
<Bit Name="sf_aes_key_r2_7" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_iv_r2_w0" Authority="RW" Address="0x4000B420" Width="32" Description="sf_aes_iv_r2_w0.">
|
|
<Bit Name="sf_aes_iv_r2_w0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_iv_r2_w1" Authority="RW" Address="0x4000B424" Width="32" Description="sf_aes_iv_r2_w1.">
|
|
<Bit Name="sf_aes_iv_r2_w1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_iv_r2_w2" Authority="RW" Address="0x4000B428" Width="32" Description="sf_aes_iv_r2_w2.">
|
|
<Bit Name="sf_aes_iv_r2_w2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_iv_r2_w3" Authority="RW" Address="0x4000B42C" Width="32" Description="sf_aes_iv_r2_w3.">
|
|
<Bit Name="sf_aes_iv_r2_w3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="sf_aes_r2" Authority="RW" Address="0x4000B430" Width="32" Description="sf_aes_r2.">
|
|
<Bit Name="sf_aes_r2_lock" Authority="RW" Bits="31" />
|
|
<Bit Name="sf_aes_r2_en" Authority="RW" Bits="30" />
|
|
<Bit Name="sf_aes_r2_hw_key_en" Authority="RW" Bits="29" />
|
|
<Bit Name="sf_aes_r2_start" Authority="RW" Bits="27-14" />
|
|
<Bit Name="sf_aes_r2_end" Authority="RW" Bits="13-0" />
|
|
</Register>
|
|
<Register Name="sf_id0_offset" Authority="RW" Address="0x4000B434" Width="32" Description="sf_id0_offset.">
|
|
<Bit Name="sf_id0_offset" Authority="RW" Bits="23-0" />
|
|
</Register>
|
|
<Register Name="sf_id1_offset" Authority="RW" Address="0x4000B438" Width="32" Description="sf_id1_offset.">
|
|
<Bit Name="sf_id1_offset" Authority="RW" Bits="23-0" />
|
|
</Register>
|
|
<Register Name="sf_bk2_id0_offset" Authority="RW" Address="0x4000B43C" Width="32" Description="sf_bk2_id0_offset.">
|
|
<Bit Name="sf_bk2_id0_offset" Authority="RW" Bits="23-0" />
|
|
</Register>
|
|
<Register Name="sf_bk2_id1_offset" Authority="RW" Address="0x4000B440" Width="32" Description="sf_bk2_id1_offset.">
|
|
<Bit Name="sf_bk2_id1_offset" Authority="RW" Bits="23-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="dma">
|
|
<Register Name="DMA_IntStatus" Authority="RW" Address="0x40007000" Width="32" Description="DMA_IntStatus.">
|
|
<Bit Name="IntStatus" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="DMA_IntTCStatus" Authority="RW" Address="0x40007004" Width="32" Description="DMA_IntTCStatus.">
|
|
<Bit Name="IntTCStatus" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="DMA_IntTCClear" Authority="RW" Address="0x40007008" Width="32" Description="DMA_IntTCClear.">
|
|
<Bit Name="IntTCClear" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="DMA_IntErrorStatus" Authority="RW" Address="0x4000700C" Width="32" Description="DMA_IntErrorStatus.">
|
|
<Bit Name="IntErrorStatus" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="DMA_IntErrClr" Authority="RW" Address="0x40007010" Width="32" Description="DMA_IntErrClr.">
|
|
<Bit Name="IntErrClr" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="DMA_RawIntTCStatus" Authority="RW" Address="0x40007014" Width="32" Description="DMA_RawIntTCStatus.">
|
|
<Bit Name="RawIntTCStatus" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="DMA_RawIntErrorStatus" Authority="RW" Address="0x40007018" Width="32" Description="DMA_RawIntErrorStatus.">
|
|
<Bit Name="RawIntErrorStatus" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="DMA_EnbldChns" Authority="RW" Address="0x4000701C" Width="32" Description="DMA_EnbldChns.">
|
|
<Bit Name="EnabledChannels" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="DMA_SoftBReq" Authority="RW" Address="0x40007020" Width="32" Description="DMA_SoftBReq.">
|
|
<Bit Name="SoftBReq" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_SoftSReq" Authority="RW" Address="0x40007024" Width="32" Description="DMA_SoftSReq.">
|
|
<Bit Name="SoftSReq" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_SoftLBReq" Authority="RW" Address="0x40007028" Width="32" Description="DMA_SoftLBReq.">
|
|
<Bit Name="SoftLBReq" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_SoftLSReq" Authority="RW" Address="0x40007x2C" Width="32" Description="DMA_SoftLSReq.">
|
|
<Bit Name="SoftLSReq" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_Top_Config" Authority="RW" Address="0x40007030" Width="32" Description="DMA_Top_Config.">
|
|
<Bit Name="M" Authority="RW" Bits="1" />
|
|
<Bit Name="E" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="DMA_Sync" Authority="RW" Address="0x40007034" Width="32" Description="DMA_Sync.">
|
|
<Bit Name="DMA_Sync" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C0SrcAddr" Authority="RW" Address="0x40007100" Width="32" Description="DMA_C0SrcAddr.">
|
|
<Bit Name="SrcAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C0DstAddr" Authority="RW" Address="0x40007104" Width="32" Description="DMA_C0DstAddr.">
|
|
<Bit Name="DstAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C0LLI" Authority="RW" Address="0x40007108" Width="32" Description="DMA_C0LLI.">
|
|
<Bit Name="LLI" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C0Control" Authority="RW" Address="0x4000710C" Width="32" Description="DMA_C0Control.">
|
|
<Bit Name="I" Authority="RW" Bits="31" />
|
|
<Bit Name="Prot" Authority="RW" Bits="30-28" />
|
|
<Bit Name="DI" Authority="RW" Bits="27" />
|
|
<Bit Name="SI" Authority="RW" Bits="26" />
|
|
<Bit Name="SLargerD" Authority="RW" Bits="25" />
|
|
<Bit Name="fix_cnt" Authority="RW" Bits="24-23" />
|
|
<Bit Name="DWidth" Authority="RW" Bits="22-21" />
|
|
<Bit Name="SWidth" Authority="RW" Bits="19-18" />
|
|
<Bit Name="dst_add_mode" Authority="RW" Bits="17" />
|
|
<Bit Name="DBSize" Authority="RW" Bits="16-15" />
|
|
<Bit Name="dst_min_mode" Authority="RW" Bits="14" />
|
|
<Bit Name="SBSize" Authority="RW" Bits="13-12" />
|
|
<Bit Name="TransferSize" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="DMA_C0Config" Authority="RW" Address="0x40007110" Width="32" Description="DMA_C0Config.">
|
|
<Bit Name="LLICounter" Authority="RW" Bits="29-20" />
|
|
<Bit Name="H" Authority="RW" Bits="18" />
|
|
<Bit Name="A" Authority="RW" Bits="17" />
|
|
<Bit Name="L" Authority="RW" Bits="16" />
|
|
<Bit Name="ITC" Authority="RW" Bits="15" />
|
|
<Bit Name="IE" Authority="RW" Bits="14" />
|
|
<Bit Name="FlowCntrl" Authority="RW" Bits="13-11" />
|
|
<Bit Name="DstPeripheral" Authority="RW" Bits="10-6" />
|
|
<Bit Name="SrcPeripheral" Authority="RW" Bits="5-1" />
|
|
<Bit Name="E" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="DMA_C1SrcAddr" Authority="RW" Address="0x40007200" Width="32" Description="DMA_C1SrcAddr.">
|
|
<Bit Name="SrcAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C1DstAddr" Authority="RW" Address="0x40007204" Width="32" Description="DMA_C1DstAddr.">
|
|
<Bit Name="DstAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C1LLI" Authority="RW" Address="0x40007208" Width="32" Description="DMA_C1LLI.">
|
|
<Bit Name="LLI" Authority="RW" Bits="31-2" />
|
|
</Register>
|
|
<Register Name="DMA_C1Control" Authority="RW" Address="0x4000720C" Width="32" Description="DMA_C1Control.">
|
|
<Bit Name="I" Authority="RW" Bits="31" />
|
|
<Bit Name="Prot" Authority="RW" Bits="30-28" />
|
|
<Bit Name="DI" Authority="RW" Bits="27" />
|
|
<Bit Name="SI" Authority="RW" Bits="26" />
|
|
<Bit Name="fix_cnt" Authority="RW" Bits="24-23" />
|
|
<Bit Name="DWidth" Authority="RW" Bits="23-21" />
|
|
<Bit Name="SWidth" Authority="RW" Bits="20-18" />
|
|
<Bit Name="dst_add_mode" Authority="RW" Bits="17" />
|
|
<Bit Name="DBSize" Authority="RW" Bits="16-15" />
|
|
<Bit Name="dst_min_mode" Authority="RW" Bits="14" />
|
|
<Bit Name="SBSize" Authority="RW" Bits="13-12" />
|
|
<Bit Name="TransferSize" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="DMA_C1Config" Authority="RW" Address="0x40007210" Width="32" Description="DMA_C1Config.">
|
|
<Bit Name="H" Authority="RW" Bits="18" />
|
|
<Bit Name="A" Authority="RW" Bits="17" />
|
|
<Bit Name="L" Authority="RW" Bits="16" />
|
|
<Bit Name="ITC" Authority="RW" Bits="15" />
|
|
<Bit Name="IE" Authority="RW" Bits="14" />
|
|
<Bit Name="FlowCntrl" Authority="RW" Bits="13-11" />
|
|
<Bit Name="DstPeripheral" Authority="RW" Bits="10-6" />
|
|
<Bit Name="SrcPeripheral" Authority="RW" Bits="5-1" />
|
|
<Bit Name="E" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="DMA_C2SrcAddr" Authority="RW" Address="0x40007300" Width="32" Description="DMA_C2SrcAddr.">
|
|
<Bit Name="SrcAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C2DstAddr" Authority="RW" Address="0x40007304" Width="32" Description="DMA_C2DstAddr.">
|
|
<Bit Name="DstAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C2LLI" Authority="RW" Address="0x40007308" Width="32" Description="DMA_C2LLI.">
|
|
<Bit Name="LLI" Authority="RW" Bits="31-2" />
|
|
</Register>
|
|
<Register Name="DMA_C2Control" Authority="RW" Address="0x4000730C" Width="32" Description="DMA_C2Control.">
|
|
<Bit Name="I" Authority="RW" Bits="31" />
|
|
<Bit Name="Prot" Authority="RW" Bits="30-28" />
|
|
<Bit Name="DI" Authority="RW" Bits="27" />
|
|
<Bit Name="SI" Authority="RW" Bits="26" />
|
|
<Bit Name="fix_cnt" Authority="RW" Bits="24-23" />
|
|
<Bit Name="DWidth" Authority="RW" Bits="23-21" />
|
|
<Bit Name="SWidth" Authority="RW" Bits="20-18" />
|
|
<Bit Name="dst_add_mode" Authority="RW" Bits="17" />
|
|
<Bit Name="DBSize" Authority="RW" Bits="16-15" />
|
|
<Bit Name="dst_min_mode" Authority="RW" Bits="14" />
|
|
<Bit Name="SBSize" Authority="RW" Bits="13-12" />
|
|
<Bit Name="TransferSize" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="DMA_C2Config" Authority="RW" Address="0x40007310" Width="32" Description="DMA_C2Config.">
|
|
<Bit Name="H" Authority="RW" Bits="18" />
|
|
<Bit Name="A" Authority="RW" Bits="17" />
|
|
<Bit Name="L" Authority="RW" Bits="16" />
|
|
<Bit Name="ITC" Authority="RW" Bits="15" />
|
|
<Bit Name="IE" Authority="RW" Bits="14" />
|
|
<Bit Name="FlowCntrl" Authority="RW" Bits="13-11" />
|
|
<Bit Name="DstPeripheral" Authority="RW" Bits="10-6" />
|
|
<Bit Name="SrcPeripheral" Authority="RW" Bits="5-1" />
|
|
<Bit Name="E" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="DMA_C3SrcAddr" Authority="RW" Address="0x40007400" Width="32" Description="DMA_C3SrcAddr.">
|
|
<Bit Name="SrcAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C3DstAddr" Authority="RW" Address="0x40007404" Width="32" Description="DMA_C3DstAddr.">
|
|
<Bit Name="DstAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C3LLI" Authority="RW" Address="0x40007408" Width="32" Description="DMA_C3LLI.">
|
|
<Bit Name="LLI" Authority="RW" Bits="31-2" />
|
|
</Register>
|
|
<Register Name="DMA_C3Control" Authority="RW" Address="0x4000740C" Width="32" Description="DMA_C3Control.">
|
|
<Bit Name="I" Authority="RW" Bits="31" />
|
|
<Bit Name="Prot" Authority="RW" Bits="30-28" />
|
|
<Bit Name="DI" Authority="RW" Bits="27" />
|
|
<Bit Name="SI" Authority="RW" Bits="26" />
|
|
<Bit Name="fix_cnt" Authority="RW" Bits="24-23" />
|
|
<Bit Name="DWidth" Authority="RW" Bits="23-21" />
|
|
<Bit Name="SWidth" Authority="RW" Bits="20-18" />
|
|
<Bit Name="dst_add_mode" Authority="RW" Bits="17" />
|
|
<Bit Name="DBSize" Authority="RW" Bits="16-15" />
|
|
<Bit Name="dst_min_mode" Authority="RW" Bits="14" />
|
|
<Bit Name="SBSize" Authority="RW" Bits="13-12" />
|
|
<Bit Name="TransferSize" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="DMA_C3Config" Authority="RW" Address="0x40007410" Width="32" Description="DMA_C3Config.">
|
|
<Bit Name="H" Authority="RW" Bits="18" />
|
|
<Bit Name="A" Authority="RW" Bits="17" />
|
|
<Bit Name="L" Authority="RW" Bits="16" />
|
|
<Bit Name="ITC" Authority="RW" Bits="15" />
|
|
<Bit Name="IE" Authority="RW" Bits="14" />
|
|
<Bit Name="FlowCntrl" Authority="RW" Bits="13-11" />
|
|
<Bit Name="DstPeripheral" Authority="RW" Bits="10-6" />
|
|
<Bit Name="SrcPeripheral" Authority="RW" Bits="5-1" />
|
|
<Bit Name="E" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="DMA_C4SrcAddr" Authority="RW" Address="0x40007500" Width="32" Description="DMA_C4SrcAddr.">
|
|
<Bit Name="SrcAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C4DstAddr" Authority="RW" Address="0x40007504" Width="32" Description="DMA_C4DstAddr.">
|
|
<Bit Name="DstAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C4LLI" Authority="RW" Address="0x40007508" Width="32" Description="DMA_C4LLI.">
|
|
<Bit Name="LLI" Authority="RW" Bits="31-2" />
|
|
</Register>
|
|
<Register Name="DMA_C4Control" Authority="RW" Address="0x4000750C" Width="32" Description="DMA_C4Control.">
|
|
<Bit Name="I" Authority="RW" Bits="31" />
|
|
<Bit Name="Prot" Authority="RW" Bits="30-28" />
|
|
<Bit Name="DI" Authority="RW" Bits="27" />
|
|
<Bit Name="SI" Authority="RW" Bits="26" />
|
|
<Bit Name="fix_cnt" Authority="RW" Bits="24-23" />
|
|
<Bit Name="DWidth" Authority="RW" Bits="23-21" />
|
|
<Bit Name="SWidth" Authority="RW" Bits="20-18" />
|
|
<Bit Name="dst_add_mode" Authority="RW" Bits="17" />
|
|
<Bit Name="DBSize" Authority="RW" Bits="16-15" />
|
|
<Bit Name="dst_min_mode" Authority="RW" Bits="14" />
|
|
<Bit Name="SBSize" Authority="RW" Bits="13-12" />
|
|
<Bit Name="TransferSize" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="DMA_C4Config" Authority="RW" Address="0x40007510" Width="32" Description="DMA_C4Config.">
|
|
<Bit Name="H" Authority="RW" Bits="18" />
|
|
<Bit Name="A" Authority="RW" Bits="17" />
|
|
<Bit Name="L" Authority="RW" Bits="16" />
|
|
<Bit Name="ITC" Authority="RW" Bits="15" />
|
|
<Bit Name="IE" Authority="RW" Bits="14" />
|
|
<Bit Name="FlowCntrl" Authority="RW" Bits="13-11" />
|
|
<Bit Name="DstPeripheral" Authority="RW" Bits="10-6" />
|
|
<Bit Name="SrcPeripheral" Authority="RW" Bits="5-1" />
|
|
<Bit Name="E" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="DMA_C5SrcAddr" Authority="RW" Address="0x40007600" Width="32" Description="DMA_C5SrcAddr.">
|
|
<Bit Name="SrcAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C5DstAddr" Authority="RW" Address="0x40007604" Width="32" Description="DMA_C5DstAddr.">
|
|
<Bit Name="DstAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C5LLI" Authority="RW" Address="0x40007608" Width="32" Description="DMA_C5LLI.">
|
|
<Bit Name="LLI" Authority="RW" Bits="31-2" />
|
|
</Register>
|
|
<Register Name="DMA_C5Control" Authority="RW" Address="0x4000760C" Width="32" Description="DMA_C5Control.">
|
|
<Bit Name="I" Authority="RW" Bits="31" />
|
|
<Bit Name="Prot" Authority="RW" Bits="30-28" />
|
|
<Bit Name="DI" Authority="RW" Bits="27" />
|
|
<Bit Name="SI" Authority="RW" Bits="26" />
|
|
<Bit Name="fix_cnt" Authority="RW" Bits="24-23" />
|
|
<Bit Name="DWidth" Authority="RW" Bits="23-21" />
|
|
<Bit Name="SWidth" Authority="RW" Bits="20-18" />
|
|
<Bit Name="dst_add_mode" Authority="RW" Bits="17" />
|
|
<Bit Name="DBSize" Authority="RW" Bits="16-15" />
|
|
<Bit Name="dst_min_mode" Authority="RW" Bits="14" />
|
|
<Bit Name="SBSize" Authority="RW" Bits="13-12" />
|
|
<Bit Name="TransferSize" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="DMA_C5Config" Authority="RW" Address="0x40007610" Width="32" Description="DMA_C5Config.">
|
|
<Bit Name="H" Authority="RW" Bits="18" />
|
|
<Bit Name="A" Authority="RW" Bits="17" />
|
|
<Bit Name="L" Authority="RW" Bits="16" />
|
|
<Bit Name="ITC" Authority="RW" Bits="15" />
|
|
<Bit Name="IE" Authority="RW" Bits="14" />
|
|
<Bit Name="FlowCntrl" Authority="RW" Bits="13-11" />
|
|
<Bit Name="DstPeripheral" Authority="RW" Bits="10-6" />
|
|
<Bit Name="SrcPeripheral" Authority="RW" Bits="5-1" />
|
|
<Bit Name="E" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="DMA_C6SrcAddr" Authority="RW" Address="0x40007700" Width="32" Description="DMA_C6SrcAddr.">
|
|
<Bit Name="SrcAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C6DstAddr" Authority="RW" Address="0x40007704" Width="32" Description="DMA_C6DstAddr.">
|
|
<Bit Name="DstAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C6LLI" Authority="RW" Address="0x40007708" Width="32" Description="DMA_C6LLI.">
|
|
<Bit Name="LLI" Authority="RW" Bits="31-2" />
|
|
</Register>
|
|
<Register Name="DMA_C6Control" Authority="RW" Address="0x4000770C" Width="32" Description="DMA_C6Control.">
|
|
<Bit Name="I" Authority="RW" Bits="31" />
|
|
<Bit Name="Prot" Authority="RW" Bits="30-28" />
|
|
<Bit Name="DI" Authority="RW" Bits="27" />
|
|
<Bit Name="SI" Authority="RW" Bits="26" />
|
|
<Bit Name="fix_cnt" Authority="RW" Bits="24-23" />
|
|
<Bit Name="DWidth" Authority="RW" Bits="23-21" />
|
|
<Bit Name="SWidth" Authority="RW" Bits="20-18" />
|
|
<Bit Name="dst_add_mode" Authority="RW" Bits="17" />
|
|
<Bit Name="DBSize" Authority="RW" Bits="16-15" />
|
|
<Bit Name="dst_min_mode" Authority="RW" Bits="14" />
|
|
<Bit Name="SBSize" Authority="RW" Bits="13-12" />
|
|
<Bit Name="TransferSize" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="DMA_C6Config" Authority="RW" Address="0x40007710" Width="32" Description="DMA_C6Config.">
|
|
<Bit Name="H" Authority="RW" Bits="18" />
|
|
<Bit Name="A" Authority="RW" Bits="17" />
|
|
<Bit Name="L" Authority="RW" Bits="16" />
|
|
<Bit Name="ITC" Authority="RW" Bits="15" />
|
|
<Bit Name="IE" Authority="RW" Bits="14" />
|
|
<Bit Name="FlowCntrl" Authority="RW" Bits="13-11" />
|
|
<Bit Name="DstPeripheral" Authority="RW" Bits="10-6" />
|
|
<Bit Name="SrcPeripheral" Authority="RW" Bits="5-1" />
|
|
<Bit Name="E" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="DMA_C7SrcAddr" Authority="RW" Address="0x40007800" Width="32" Description="DMA_C7SrcAddr.">
|
|
<Bit Name="SrcAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C7DstAddr" Authority="RW" Address="0x40007804" Width="32" Description="DMA_C7DstAddr.">
|
|
<Bit Name="DstAddr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="DMA_C7LLI" Authority="RW" Address="0x40007808" Width="32" Description="DMA_C7LLI.">
|
|
<Bit Name="LLI" Authority="RW" Bits="31-2" />
|
|
</Register>
|
|
<Register Name="DMA_C7Control" Authority="RW" Address="0x4000780C" Width="32" Description="DMA_C7Control.">
|
|
<Bit Name="I" Authority="RW" Bits="31" />
|
|
<Bit Name="Prot" Authority="RW" Bits="30-28" />
|
|
<Bit Name="DI" Authority="RW" Bits="27" />
|
|
<Bit Name="SI" Authority="RW" Bits="26" />
|
|
<Bit Name="fix_cnt" Authority="RW" Bits="24-23" />
|
|
<Bit Name="DWidth" Authority="RW" Bits="23-21" />
|
|
<Bit Name="SWidth" Authority="RW" Bits="20-18" />
|
|
<Bit Name="dst_add_mode" Authority="RW" Bits="17" />
|
|
<Bit Name="DBSize" Authority="RW" Bits="16-15" />
|
|
<Bit Name="dst_min_mode" Authority="RW" Bits="14" />
|
|
<Bit Name="SBSize" Authority="RW" Bits="13-12" />
|
|
<Bit Name="TransferSize" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="DMA_C7Config" Authority="RW" Address="0x40007810" Width="32" Description="DMA_C7Config.">
|
|
<Bit Name="H" Authority="RW" Bits="18" />
|
|
<Bit Name="A" Authority="RW" Bits="17" />
|
|
<Bit Name="L" Authority="RW" Bits="16" />
|
|
<Bit Name="ITC" Authority="RW" Bits="15" />
|
|
<Bit Name="IE" Authority="RW" Bits="14" />
|
|
<Bit Name="FlowCntrl" Authority="RW" Bits="13-11" />
|
|
<Bit Name="DstPeripheral" Authority="RW" Bits="10-6" />
|
|
<Bit Name="SrcPeripheral" Authority="RW" Bits="5-1" />
|
|
<Bit Name="E" Authority="RW" Bits="0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="emac">
|
|
<Register Name="MODE" Authority="RW" Address="0x4000D000" Width="32" Description="MODE.">
|
|
<Bit Name="rsvd_23_18" Authority="RW" Bits="23-18" />
|
|
<Bit Name="RMII_EN" Authority="RW" Bits="17" />
|
|
<Bit Name="RECSMALL" Authority="RW" Bits="16" />
|
|
<Bit Name="PAD" Authority="RW" Bits="15" />
|
|
<Bit Name="HUGEN" Authority="RW" Bits="14" />
|
|
<Bit Name="CRCEN" Authority="RW" Bits="13" />
|
|
<Bit Name="rsvd_12_11" Authority="RW" Bits="12-11" />
|
|
<Bit Name="FULLD" Authority="RW" Bits="10" />
|
|
<Bit Name="rsvd_9_7" Authority="RW" Bits="9-7" />
|
|
<Bit Name="IFG" Authority="RW" Bits="6" />
|
|
<Bit Name="PRO" Authority="RW" Bits="5" />
|
|
<Bit Name="rsvd_4" Authority="RW" Bits="4" />
|
|
<Bit Name="BRO" Authority="RW" Bits="3" />
|
|
<Bit Name="NOPRE" Authority="RW" Bits="2" />
|
|
<Bit Name="TXEN" Authority="RW" Bits="1" />
|
|
<Bit Name="RXEN" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="INT_SOURCE" Authority="RW" Address="0x4000D004" Width="32" Description="INT_SOURCE.">
|
|
<Bit Name="RXC" Authority="RW" Bits="6" />
|
|
<Bit Name="TXC" Authority="RW" Bits="5" />
|
|
<Bit Name="BUSY" Authority="RW" Bits="4" />
|
|
<Bit Name="RXE" Authority="RW" Bits="3" />
|
|
<Bit Name="RXB" Authority="RW" Bits="2" />
|
|
<Bit Name="TXE" Authority="RW" Bits="1" />
|
|
<Bit Name="TXB" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="INT_MASK" Authority="RW" Address="0x4000D008" Width="32" Description="INT_MASK.">
|
|
<Bit Name="RXC_M" Authority="RW" Bits="6" />
|
|
<Bit Name="TXC_M" Authority="RW" Bits="5" />
|
|
<Bit Name="BUSY_M" Authority="RW" Bits="4" />
|
|
<Bit Name="RXE_M" Authority="RW" Bits="3" />
|
|
<Bit Name="RXB_M" Authority="RW" Bits="2" />
|
|
<Bit Name="TXE_M" Authority="RW" Bits="1" />
|
|
<Bit Name="TXB_M" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="IPGT" Authority="RW" Address="0x4000D00C" Width="32" Description="IPGT.">
|
|
<Bit Name="IPGT" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="PACKETLEN" Authority="RW" Address="0x4000D018" Width="32" Description="PACKETLEN.">
|
|
<Bit Name="MINFL" Authority="RW" Bits="31-16" />
|
|
<Bit Name="MAXFL" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="COLLCONFIG" Authority="RW" Address="0x4000D01C" Width="32" Description="COLLCONFIG.">
|
|
<Bit Name="MAXRET" Authority="RW" Bits="19-16" />
|
|
<Bit Name="COLLVALID" Authority="RW" Bits="5-0" />
|
|
</Register>
|
|
<Register Name="TX_BD_NUM" Authority="RW" Address="0x4000D020" Width="32" Description="TX_BD_NUM.">
|
|
<Bit Name="RXBDPTR" Authority="RW" Bits="30-24" />
|
|
<Bit Name="TXBDPTR" Authority="RW" Bits="22-16" />
|
|
<Bit Name="TXBDNUM" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="MIIMODE" Authority="RW" Address="0x4000D028" Width="32" Description="MIIMODE.">
|
|
<Bit Name="MIINOPRE" Authority="RW" Bits="8" />
|
|
<Bit Name="CLKDIV" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="MIICOMMAND" Authority="RW" Address="0x4000Dx2C" Width="32" Description="MIICOMMAND.">
|
|
<Bit Name="WCTRLDATA" Authority="RW" Bits="2" />
|
|
<Bit Name="RSTAT" Authority="RW" Bits="1" />
|
|
<Bit Name="SCANSTAT" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="MIIADDRESS" Authority="RW" Address="0x4000D030" Width="32" Description="MIIADDRESS.">
|
|
<Bit Name="RGAD" Authority="RW" Bits="12-8" />
|
|
<Bit Name="FIAD" Authority="RW" Bits="4-0" />
|
|
</Register>
|
|
<Register Name="MIITX_DATA" Authority="RW" Address="0x4000D034" Width="32" Description="MIITX_DATA.">
|
|
<Bit Name="CTRLDATA" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="MIIRX_DATA" Authority="RW" Address="0x4000D038" Width="32" Description="MIIRX_DATA.">
|
|
<Bit Name="PRSD" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="MIISTATUS" Authority="RW" Address="0x4000Dx3C" Width="32" Description="MIISTATUS.">
|
|
<Bit Name="MIIM_BUSY" Authority="RW" Bits="1" />
|
|
<Bit Name="MIIM_LINKFAIL" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="MAC_ADDR0" Authority="RW" Address="0x4000D040" Width="32" Description="MAC_ADDR0.">
|
|
<Bit Name="MAC_B2" Authority="RW" Bits="31-24" />
|
|
<Bit Name="MAC_B3" Authority="RW" Bits="23-16" />
|
|
<Bit Name="MAC_B4" Authority="RW" Bits="15-8" />
|
|
<Bit Name="MAC_B5" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="MAC_ADDR1" Authority="RW" Address="0x4000D044" Width="32" Description="MAC_ADDR1.">
|
|
<Bit Name="MAC_B0" Authority="RW" Bits="15-8" />
|
|
<Bit Name="MAC_B1" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="HASH0_ADDR" Authority="RW" Address="0x4000D048" Width="32" Description="HASH0_ADDR.">
|
|
<Bit Name="HASH0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="HASH1_ADDR" Authority="RW" Address="0x4000Dx4C" Width="32" Description="HASH1_ADDR.">
|
|
<Bit Name="HASH1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="TXCTRL" Authority="RW" Address="0x4000D050" Width="32" Description="TXCTRL.">
|
|
<Bit Name="TXPAUSERQ" Authority="RW" Bits="16" />
|
|
<Bit Name="TXPAUSETV" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="usb">
|
|
<Register Name="usb_config" Authority="RW" Address="0x4000D000" Width="32" Description="usb_config.">
|
|
<Bit Name="sts_usb_ep0_sw_rdy" Authority="RW" Bits="28" />
|
|
<Bit Name="cr_usb_ep0_sw_rdy" Authority="RW" Bits="27" />
|
|
<Bit Name="cr_usb_ep0_sw_nack_out" Authority="RW" Bits="26" />
|
|
<Bit Name="cr_usb_ep0_sw_nack_in" Authority="RW" Bits="25" />
|
|
<Bit Name="cr_usb_ep0_sw_stall" Authority="RW" Bits="24" />
|
|
<Bit Name="cr_usb_ep0_sw_size" Authority="RW" Bits="23-16" />
|
|
<Bit Name="cr_usb_ep0_sw_addr" Authority="RW" Bits="15-9" />
|
|
<Bit Name="cr_usb_ep0_sw_ctrl" Authority="RW" Bits="8" />
|
|
<Bit Name="cr_usb_rom_dct_en" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_usb_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="usb_lpm_config" Authority="RW" Address="0x4000D004" Width="32" Description="usb_lpm_config.">
|
|
<Bit Name="sts_lpm" Authority="RW" Bits="31" />
|
|
<Bit Name="sts_lpm_attr" Authority="RW" Bits="30-20" />
|
|
<Bit Name="cr_lpm_resp" Authority="RW" Bits="3-2" />
|
|
<Bit Name="cr_lpm_resp_upd" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_lpm_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="usb_resume_config" Authority="RW" Address="0x4000D008" Width="32" Description="usb_resume_config.">
|
|
<Bit Name="cr_res_force" Authority="RW" Bits="31" />
|
|
<Bit Name="cr_res_trig" Authority="RW" Bits="12" />
|
|
<Bit Name="cr_res_width" Authority="RW" Bits="10-0" />
|
|
</Register>
|
|
<Register Name="usb_setup_data_0" Authority="RW" Address="0x4000D010" Width="32" Description="usb_setup_data_0.">
|
|
<Bit Name="sts_setup_data_b3" Authority="RW" Bits="31-24" />
|
|
<Bit Name="sts_setup_data_b2" Authority="RW" Bits="23-16" />
|
|
<Bit Name="sts_setup_data_b1" Authority="RW" Bits="15-8" />
|
|
<Bit Name="sts_setup_data_b0" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="usb_setup_data_1" Authority="RW" Address="0x4000D014" Width="32" Description="usb_setup_data_1.">
|
|
<Bit Name="sts_setup_data_b7" Authority="RW" Bits="31-24" />
|
|
<Bit Name="sts_setup_data_b6" Authority="RW" Bits="23-16" />
|
|
<Bit Name="sts_setup_data_b5" Authority="RW" Bits="15-8" />
|
|
<Bit Name="sts_setup_data_b4" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="usb_frame_no" Authority="RW" Address="0x4000D018" Width="32" Description="usb_frame_no.">
|
|
<Bit Name="sts_ep_no" Authority="RW" Bits="19-16" />
|
|
<Bit Name="sts_pid" Authority="RW" Bits="15-12" />
|
|
<Bit Name="sts_frame_no" Authority="RW" Bits="10-0" />
|
|
</Register>
|
|
<Register Name="usb_error" Authority="RW" Address="0x4000D01C" Width="32" Description="usb_error.">
|
|
<Bit Name="crc16_err" Authority="RW" Bits="6" />
|
|
<Bit Name="crc5_err" Authority="RW" Bits="5" />
|
|
<Bit Name="pid_cks_err" Authority="RW" Bits="4" />
|
|
<Bit Name="pid_seq_err" Authority="RW" Bits="3" />
|
|
<Bit Name="ivld_ep_err" Authority="RW" Bits="2" />
|
|
<Bit Name="xfer_to_err" Authority="RW" Bits="1" />
|
|
<Bit Name="utmi_rx_err" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="usb_int_en" Authority="RW" Address="0x4000D020" Width="32" Description="USB interrupt enable">
|
|
<Bit Name="cr_usb_err_en" Authority="RW" Bits="31" />
|
|
<Bit Name="cr_sof_3ms_en" Authority="RW" Bits="30" />
|
|
<Bit Name="cr_lpm_pkt_en" Authority="RW" Bits="29" />
|
|
<Bit Name="cr_lpm_wkup_en" Authority="RW" Bits="28" />
|
|
<Bit Name="rsvd_27_24" Authority="RW" Bits="27-24" />
|
|
<Bit Name="cr_ep7_done_en" Authority="RW" Bits="23" />
|
|
<Bit Name="cr_ep7_cmd_en" Authority="RW" Bits="22" />
|
|
<Bit Name="cr_ep6_done_en" Authority="RW" Bits="21" />
|
|
<Bit Name="cr_ep6_cmd_en" Authority="RW" Bits="20" />
|
|
<Bit Name="cr_ep5_done_en" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_ep5_cmd_en" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_ep4_done_en" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_ep4_cmd_en" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_ep3_done_en" Authority="RW" Bits="15" />
|
|
<Bit Name="cr_ep3_cmd_en" Authority="RW" Bits="14" />
|
|
<Bit Name="cr_ep2_done_en" Authority="RW" Bits="13" />
|
|
<Bit Name="cr_ep2_cmd_en" Authority="RW" Bits="12" />
|
|
<Bit Name="cr_ep1_done_en" Authority="RW" Bits="11" />
|
|
<Bit Name="cr_ep1_cmd_en" Authority="RW" Bits="10" />
|
|
<Bit Name="cr_ep0_out_done_en" Authority="RW" Bits="9" />
|
|
<Bit Name="cr_ep0_out_cmd_en" Authority="RW" Bits="8" />
|
|
<Bit Name="cr_ep0_in_done_en" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_ep0_in_cmd_en" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_ep0_setup_done_en" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_ep0_setup_cmd_en" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_get_dct_cmd_en" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_vbus_tgl_en" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_usb_reset_en" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_sof_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="usb_int_sts" Authority="RW" Address="0x4000D024" Width="32" Description="USB interrupt status">
|
|
<Bit Name="usb_err_int" Authority="RW" Bits="31" />
|
|
<Bit Name="sof_3ms_int" Authority="RW" Bits="30" />
|
|
<Bit Name="lpm_pkt_int" Authority="RW" Bits="29" />
|
|
<Bit Name="lpm_wkup_int" Authority="RW" Bits="28" />
|
|
<Bit Name="rsvd_27_24" Authority="RW" Bits="27-24" />
|
|
<Bit Name="ep7_done_int" Authority="RW" Bits="23" />
|
|
<Bit Name="ep7_cmd_int" Authority="RW" Bits="22" />
|
|
<Bit Name="ep6_done_int" Authority="RW" Bits="21" />
|
|
<Bit Name="ep6_cmd_int" Authority="RW" Bits="20" />
|
|
<Bit Name="ep5_done_int" Authority="RW" Bits="19" />
|
|
<Bit Name="ep5_cmd_int" Authority="RW" Bits="18" />
|
|
<Bit Name="ep4_done_int" Authority="RW" Bits="17" />
|
|
<Bit Name="ep4_cmd_int" Authority="RW" Bits="16" />
|
|
<Bit Name="ep3_done_int" Authority="RW" Bits="15" />
|
|
<Bit Name="ep3_cmd_int" Authority="RW" Bits="14" />
|
|
<Bit Name="ep2_done_int" Authority="RW" Bits="13" />
|
|
<Bit Name="ep2_cmd_int" Authority="RW" Bits="12" />
|
|
<Bit Name="ep1_done_int" Authority="RW" Bits="11" />
|
|
<Bit Name="ep1_cmd_int" Authority="RW" Bits="10" />
|
|
<Bit Name="ep0_out_done_int" Authority="RW" Bits="9" />
|
|
<Bit Name="ep0_out_cmd_int" Authority="RW" Bits="8" />
|
|
<Bit Name="ep0_in_done_int" Authority="RW" Bits="7" />
|
|
<Bit Name="ep0_in_cmd_int" Authority="RW" Bits="6" />
|
|
<Bit Name="ep0_setup_done_int" Authority="RW" Bits="5" />
|
|
<Bit Name="ep0_setup_cmd_int" Authority="RW" Bits="4" />
|
|
<Bit Name="get_dct_cmd_int" Authority="RW" Bits="3" />
|
|
<Bit Name="vbus_tgl_int" Authority="RW" Bits="2" />
|
|
<Bit Name="usb_reset_int" Authority="RW" Bits="1" />
|
|
<Bit Name="sof_int" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="usb_int_mask" Authority="RW" Address="0x4000D028" Width="32" Description="USB interrupt mask">
|
|
<Bit Name="cr_usb_err_mask" Authority="RW" Bits="31" />
|
|
<Bit Name="cr_sof_3ms_mask" Authority="RW" Bits="30" />
|
|
<Bit Name="cr_lpm_pkt_mask" Authority="RW" Bits="29" />
|
|
<Bit Name="cr_lpm_wkup_mask" Authority="RW" Bits="28" />
|
|
<Bit Name="rsvd_27_24" Authority="RW" Bits="27-24" />
|
|
<Bit Name="cr_ep7_done_mask" Authority="RW" Bits="23" />
|
|
<Bit Name="cr_ep7_cmd_mask" Authority="RW" Bits="22" />
|
|
<Bit Name="cr_ep6_done_mask" Authority="RW" Bits="21" />
|
|
<Bit Name="cr_ep6_cmd_mask" Authority="RW" Bits="20" />
|
|
<Bit Name="cr_ep5_done_mask" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_ep5_cmd_mask" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_ep4_done_mask" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_ep4_cmd_mask" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_ep3_done_mask" Authority="RW" Bits="15" />
|
|
<Bit Name="cr_ep3_cmd_mask" Authority="RW" Bits="14" />
|
|
<Bit Name="cr_ep2_done_mask" Authority="RW" Bits="13" />
|
|
<Bit Name="cr_ep2_cmd_mask" Authority="RW" Bits="12" />
|
|
<Bit Name="cr_ep1_done_mask" Authority="RW" Bits="11" />
|
|
<Bit Name="cr_ep1_cmd_mask" Authority="RW" Bits="10" />
|
|
<Bit Name="cr_ep0_out_done_mask" Authority="RW" Bits="9" />
|
|
<Bit Name="cr_ep0_out_cmd_mask" Authority="RW" Bits="8" />
|
|
<Bit Name="cr_ep0_in_done_mask" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_ep0_in_cmd_mask" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_ep0_setup_done_mask" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_ep0_setup_cmd_mask" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_get_dct_cmd_mask" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_vbus_tgl_mask" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_usb_reset_mask" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_sof_mask" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="usb_int_clear" Authority="RW" Address="0x4000Dx2C" Width="32" Description="USB interrupt clear">
|
|
<Bit Name="cr_usb_err_clr" Authority="RW" Bits="31" />
|
|
<Bit Name="cr_sof_3ms_clr" Authority="RW" Bits="30" />
|
|
<Bit Name="cr_lpm_pkt_clr" Authority="RW" Bits="29" />
|
|
<Bit Name="cr_lpm_wkup_clr" Authority="RW" Bits="28" />
|
|
<Bit Name="rsvd_27_24" Authority="RW" Bits="27-24" />
|
|
<Bit Name="cr_ep7_done_clr" Authority="RW" Bits="23" />
|
|
<Bit Name="cr_ep7_cmd_clr" Authority="RW" Bits="22" />
|
|
<Bit Name="cr_ep6_done_clr" Authority="RW" Bits="21" />
|
|
<Bit Name="cr_ep6_cmd_clr" Authority="RW" Bits="20" />
|
|
<Bit Name="cr_ep5_done_clr" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_ep5_cmd_clr" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_ep4_done_clr" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_ep4_cmd_clr" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_ep3_done_clr" Authority="RW" Bits="15" />
|
|
<Bit Name="cr_ep3_cmd_clr" Authority="RW" Bits="14" />
|
|
<Bit Name="cr_ep2_done_clr" Authority="RW" Bits="13" />
|
|
<Bit Name="cr_ep2_cmd_clr" Authority="RW" Bits="12" />
|
|
<Bit Name="cr_ep1_done_clr" Authority="RW" Bits="11" />
|
|
<Bit Name="cr_ep1_cmd_clr" Authority="RW" Bits="10" />
|
|
<Bit Name="cr_ep0_out_done_clr" Authority="RW" Bits="9" />
|
|
<Bit Name="cr_ep0_out_cmd_clr" Authority="RW" Bits="8" />
|
|
<Bit Name="cr_ep0_in_done_clr" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_ep0_in_cmd_clr" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_ep0_setup_done_clr" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_ep0_setup_cmd_clr" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_get_dct_cmd_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_vbus_tgl_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_usb_reset_clr" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_sof_clr" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ep1_config" Authority="RW" Address="0x4000D040" Width="32" Description="ep1_config.">
|
|
<Bit Name="sts_ep1_rdy" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_ep1_rdy" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_ep1_nack" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_ep1_stall" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_ep1_type" Authority="RW" Bits="15-13" />
|
|
<Bit Name="cr_ep1_dir" Authority="RW" Bits="12-11" />
|
|
<Bit Name="cr_ep1_size" Authority="RW" Bits="10-0" />
|
|
</Register>
|
|
<Register Name="ep2_config" Authority="RW" Address="0x4000D044" Width="32" Description="ep2_config.">
|
|
<Bit Name="sts_ep2_rdy" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_ep2_rdy" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_ep2_nack" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_ep2_stall" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_ep2_type" Authority="RW" Bits="15-13" />
|
|
<Bit Name="cr_ep2_dir" Authority="RW" Bits="12-11" />
|
|
<Bit Name="cr_ep2_size" Authority="RW" Bits="10-0" />
|
|
</Register>
|
|
<Register Name="ep3_config" Authority="RW" Address="0x4000D048" Width="32" Description="ep3_config.">
|
|
<Bit Name="sts_ep3_rdy" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_ep3_rdy" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_ep3_nack" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_ep3_stall" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_ep3_type" Authority="RW" Bits="15-13" />
|
|
<Bit Name="cr_ep3_dir" Authority="RW" Bits="12-11" />
|
|
<Bit Name="cr_ep3_size" Authority="RW" Bits="10-0" />
|
|
</Register>
|
|
<Register Name="ep4_config" Authority="RW" Address="0x4000Dx4C" Width="32" Description="ep4_config.">
|
|
<Bit Name="sts_ep4_rdy" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_ep4_rdy" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_ep4_nack" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_ep4_stall" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_ep4_type" Authority="RW" Bits="15-13" />
|
|
<Bit Name="cr_ep4_dir" Authority="RW" Bits="12-11" />
|
|
<Bit Name="cr_ep4_size" Authority="RW" Bits="10-0" />
|
|
</Register>
|
|
<Register Name="ep5_config" Authority="RW" Address="0x4000D050" Width="32" Description="ep5_config.">
|
|
<Bit Name="sts_ep5_rdy" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_ep5_rdy" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_ep5_nack" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_ep5_stall" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_ep5_type" Authority="RW" Bits="15-13" />
|
|
<Bit Name="cr_ep5_dir" Authority="RW" Bits="12-11" />
|
|
<Bit Name="cr_ep5_size" Authority="RW" Bits="10-0" />
|
|
</Register>
|
|
<Register Name="ep6_config" Authority="RW" Address="0x4000D054" Width="32" Description="ep6_config.">
|
|
<Bit Name="sts_ep6_rdy" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_ep6_rdy" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_ep6_nack" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_ep6_stall" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_ep6_type" Authority="RW" Bits="15-13" />
|
|
<Bit Name="cr_ep6_dir" Authority="RW" Bits="12-11" />
|
|
<Bit Name="cr_ep6_size" Authority="RW" Bits="10-0" />
|
|
</Register>
|
|
<Register Name="ep7_config" Authority="RW" Address="0x4000D058" Width="32" Description="ep7_config.">
|
|
<Bit Name="sts_ep7_rdy" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_ep7_rdy" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_ep7_nack" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_ep7_stall" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_ep7_type" Authority="RW" Bits="15-13" />
|
|
<Bit Name="cr_ep7_dir" Authority="RW" Bits="12-11" />
|
|
<Bit Name="cr_ep7_size" Authority="RW" Bits="10-0" />
|
|
</Register>
|
|
<Register Name="ep0_fifo_config" Authority="RW" Address="0x4000D100" Width="32" Description="ep0_fifo_config.">
|
|
<Bit Name="ep0_rx_fifo_underflow" Authority="RW" Bits="7" />
|
|
<Bit Name="ep0_rx_fifo_overflow" Authority="RW" Bits="6" />
|
|
<Bit Name="ep0_tx_fifo_underflow" Authority="RW" Bits="5" />
|
|
<Bit Name="ep0_tx_fifo_overflow" Authority="RW" Bits="4" />
|
|
<Bit Name="ep0_rx_fifo_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="ep0_tx_fifo_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="ep0_dma_rx_en" Authority="RW" Bits="1" />
|
|
<Bit Name="ep0_dma_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ep0_fifo_status" Authority="RW" Address="0x4000D104" Width="32" Description="ep0_fifo_status.">
|
|
<Bit Name="ep0_rx_fifo_full" Authority="RW" Bits="31" />
|
|
<Bit Name="ep0_rx_fifo_empty" Authority="RW" Bits="30" />
|
|
<Bit Name="ep0_rx_fifo_cnt" Authority="RW" Bits="22-16" />
|
|
<Bit Name="ep0_tx_fifo_full" Authority="RW" Bits="15" />
|
|
<Bit Name="ep0_tx_fifo_empty" Authority="RW" Bits="14" />
|
|
<Bit Name="ep0_tx_fifo_cnt" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="ep0_tx_fifo_wdata" Authority="RW" Address="0x4000D108" Width="32" Description="ep0_tx_fifo_wdata.">
|
|
<Bit Name="ep0_tx_fifo_wdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep0_rx_fifo_rdata" Authority="RW" Address="0x4000D10C" Width="32" Description="ep0_rx_fifo_rdata.">
|
|
<Bit Name="ep0_rx_fifo_rdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep1_fifo_config" Authority="RW" Address="0x4000D110" Width="32" Description="ep1_fifo_config.">
|
|
<Bit Name="ep1_rx_fifo_underflow" Authority="RW" Bits="7" />
|
|
<Bit Name="ep1_rx_fifo_overflow" Authority="RW" Bits="6" />
|
|
<Bit Name="ep1_tx_fifo_underflow" Authority="RW" Bits="5" />
|
|
<Bit Name="ep1_tx_fifo_overflow" Authority="RW" Bits="4" />
|
|
<Bit Name="ep1_rx_fifo_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="ep1_tx_fifo_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="ep1_dma_rx_en" Authority="RW" Bits="1" />
|
|
<Bit Name="ep1_dma_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ep1_fifo_status" Authority="RW" Address="0x4000D114" Width="32" Description="ep1_fifo_status.">
|
|
<Bit Name="ep1_rx_fifo_full" Authority="RW" Bits="31" />
|
|
<Bit Name="ep1_rx_fifo_empty" Authority="RW" Bits="30" />
|
|
<Bit Name="ep1_rx_fifo_cnt" Authority="RW" Bits="22-16" />
|
|
<Bit Name="ep1_tx_fifo_full" Authority="RW" Bits="15" />
|
|
<Bit Name="ep1_tx_fifo_empty" Authority="RW" Bits="14" />
|
|
<Bit Name="ep1_tx_fifo_cnt" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="ep1_tx_fifo_wdata" Authority="RW" Address="0x4000D118" Width="32" Description="ep1_tx_fifo_wdata.">
|
|
<Bit Name="ep1_tx_fifo_wdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep1_rx_fifo_rdata" Authority="RW" Address="0x4000D11C" Width="32" Description="ep1_rx_fifo_rdata.">
|
|
<Bit Name="ep1_rx_fifo_rdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep2_fifo_config" Authority="RW" Address="0x4000D120" Width="32" Description="ep2_fifo_config.">
|
|
<Bit Name="ep2_rx_fifo_underflow" Authority="RW" Bits="7" />
|
|
<Bit Name="ep2_rx_fifo_overflow" Authority="RW" Bits="6" />
|
|
<Bit Name="ep2_tx_fifo_underflow" Authority="RW" Bits="5" />
|
|
<Bit Name="ep2_tx_fifo_overflow" Authority="RW" Bits="4" />
|
|
<Bit Name="ep2_rx_fifo_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="ep2_tx_fifo_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="ep2_dma_rx_en" Authority="RW" Bits="1" />
|
|
<Bit Name="ep2_dma_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ep2_fifo_status" Authority="RW" Address="0x4000D124" Width="32" Description="ep2_fifo_status.">
|
|
<Bit Name="ep2_rx_fifo_full" Authority="RW" Bits="31" />
|
|
<Bit Name="ep2_rx_fifo_empty" Authority="RW" Bits="30" />
|
|
<Bit Name="ep2_rx_fifo_cnt" Authority="RW" Bits="22-16" />
|
|
<Bit Name="ep2_tx_fifo_full" Authority="RW" Bits="15" />
|
|
<Bit Name="ep2_tx_fifo_empty" Authority="RW" Bits="14" />
|
|
<Bit Name="ep2_tx_fifo_cnt" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="ep2_tx_fifo_wdata" Authority="RW" Address="0x4000D128" Width="32" Description="ep2_tx_fifo_wdata.">
|
|
<Bit Name="ep2_tx_fifo_wdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep2_rx_fifo_rdata" Authority="RW" Address="0x4000D12C" Width="32" Description="ep2_rx_fifo_rdata.">
|
|
<Bit Name="ep2_rx_fifo_rdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep3_fifo_config" Authority="RW" Address="0x4000D130" Width="32" Description="ep3_fifo_config.">
|
|
<Bit Name="ep3_rx_fifo_underflow" Authority="RW" Bits="7" />
|
|
<Bit Name="ep3_rx_fifo_overflow" Authority="RW" Bits="6" />
|
|
<Bit Name="ep3_tx_fifo_underflow" Authority="RW" Bits="5" />
|
|
<Bit Name="ep3_tx_fifo_overflow" Authority="RW" Bits="4" />
|
|
<Bit Name="ep3_rx_fifo_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="ep3_tx_fifo_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="ep3_dma_rx_en" Authority="RW" Bits="1" />
|
|
<Bit Name="ep3_dma_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ep3_fifo_status" Authority="RW" Address="0x4000D134" Width="32" Description="ep3_fifo_status.">
|
|
<Bit Name="ep3_rx_fifo_full" Authority="RW" Bits="31" />
|
|
<Bit Name="ep3_rx_fifo_empty" Authority="RW" Bits="30" />
|
|
<Bit Name="ep3_rx_fifo_cnt" Authority="RW" Bits="22-16" />
|
|
<Bit Name="ep3_tx_fifo_full" Authority="RW" Bits="15" />
|
|
<Bit Name="ep3_tx_fifo_empty" Authority="RW" Bits="14" />
|
|
<Bit Name="ep3_tx_fifo_cnt" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="ep3_tx_fifo_wdata" Authority="RW" Address="0x4000D138" Width="32" Description="ep3_tx_fifo_wdata.">
|
|
<Bit Name="ep3_tx_fifo_wdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep3_rx_fifo_rdata" Authority="RW" Address="0x4000D13C" Width="32" Description="ep3_rx_fifo_rdata.">
|
|
<Bit Name="ep3_rx_fifo_rdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep4_fifo_config" Authority="RW" Address="0x4000D140" Width="32" Description="ep4_fifo_config.">
|
|
<Bit Name="ep4_rx_fifo_underflow" Authority="RW" Bits="7" />
|
|
<Bit Name="ep4_rx_fifo_overflow" Authority="RW" Bits="6" />
|
|
<Bit Name="ep4_tx_fifo_underflow" Authority="RW" Bits="5" />
|
|
<Bit Name="ep4_tx_fifo_overflow" Authority="RW" Bits="4" />
|
|
<Bit Name="ep4_rx_fifo_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="ep4_tx_fifo_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="ep4_dma_rx_en" Authority="RW" Bits="1" />
|
|
<Bit Name="ep4_dma_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ep4_fifo_status" Authority="RW" Address="0x4000D144" Width="32" Description="ep4_fifo_status.">
|
|
<Bit Name="ep4_rx_fifo_full" Authority="RW" Bits="31" />
|
|
<Bit Name="ep4_rx_fifo_empty" Authority="RW" Bits="30" />
|
|
<Bit Name="ep4_rx_fifo_cnt" Authority="RW" Bits="22-16" />
|
|
<Bit Name="ep4_tx_fifo_full" Authority="RW" Bits="15" />
|
|
<Bit Name="ep4_tx_fifo_empty" Authority="RW" Bits="14" />
|
|
<Bit Name="ep4_tx_fifo_cnt" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="ep4_tx_fifo_wdata" Authority="RW" Address="0x4000D148" Width="32" Description="ep4_tx_fifo_wdata.">
|
|
<Bit Name="ep4_tx_fifo_wdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep4_rx_fifo_rdata" Authority="RW" Address="0x4000D14C" Width="32" Description="ep4_rx_fifo_rdata.">
|
|
<Bit Name="ep4_rx_fifo_rdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep5_fifo_config" Authority="RW" Address="0x4000D150" Width="32" Description="ep5_fifo_config.">
|
|
<Bit Name="ep5_rx_fifo_underflow" Authority="RW" Bits="7" />
|
|
<Bit Name="ep5_rx_fifo_overflow" Authority="RW" Bits="6" />
|
|
<Bit Name="ep5_tx_fifo_underflow" Authority="RW" Bits="5" />
|
|
<Bit Name="ep5_tx_fifo_overflow" Authority="RW" Bits="4" />
|
|
<Bit Name="ep5_rx_fifo_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="ep5_tx_fifo_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="ep5_dma_rx_en" Authority="RW" Bits="1" />
|
|
<Bit Name="ep5_dma_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ep5_fifo_status" Authority="RW" Address="0x4000D154" Width="32" Description="ep5_fifo_status.">
|
|
<Bit Name="ep5_rx_fifo_full" Authority="RW" Bits="31" />
|
|
<Bit Name="ep5_rx_fifo_empty" Authority="RW" Bits="30" />
|
|
<Bit Name="ep5_rx_fifo_cnt" Authority="RW" Bits="22-16" />
|
|
<Bit Name="ep5_tx_fifo_full" Authority="RW" Bits="15" />
|
|
<Bit Name="ep5_tx_fifo_empty" Authority="RW" Bits="14" />
|
|
<Bit Name="ep5_tx_fifo_cnt" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="ep5_tx_fifo_wdata" Authority="RW" Address="0x4000D158" Width="32" Description="ep5_tx_fifo_wdata.">
|
|
<Bit Name="ep5_tx_fifo_wdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep5_rx_fifo_rdata" Authority="RW" Address="0x4000D15C" Width="32" Description="ep5_rx_fifo_rdata.">
|
|
<Bit Name="ep5_rx_fifo_rdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep6_fifo_config" Authority="RW" Address="0x4000D160" Width="32" Description="ep6_fifo_config.">
|
|
<Bit Name="ep6_rx_fifo_underflow" Authority="RW" Bits="7" />
|
|
<Bit Name="ep6_rx_fifo_overflow" Authority="RW" Bits="6" />
|
|
<Bit Name="ep6_tx_fifo_underflow" Authority="RW" Bits="5" />
|
|
<Bit Name="ep6_tx_fifo_overflow" Authority="RW" Bits="4" />
|
|
<Bit Name="ep6_rx_fifo_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="ep6_tx_fifo_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="ep6_dma_rx_en" Authority="RW" Bits="1" />
|
|
<Bit Name="ep6_dma_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ep6_fifo_status" Authority="RW" Address="0x4000D164" Width="32" Description="ep6_fifo_status.">
|
|
<Bit Name="ep6_rx_fifo_full" Authority="RW" Bits="31" />
|
|
<Bit Name="ep6_rx_fifo_empty" Authority="RW" Bits="30" />
|
|
<Bit Name="ep6_rx_fifo_cnt" Authority="RW" Bits="22-16" />
|
|
<Bit Name="ep6_tx_fifo_full" Authority="RW" Bits="15" />
|
|
<Bit Name="ep6_tx_fifo_empty" Authority="RW" Bits="14" />
|
|
<Bit Name="ep6_tx_fifo_cnt" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="ep6_tx_fifo_wdata" Authority="RW" Address="0x4000D168" Width="32" Description="ep6_tx_fifo_wdata.">
|
|
<Bit Name="ep6_tx_fifo_wdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep6_rx_fifo_rdata" Authority="RW" Address="0x4000D16C" Width="32" Description="ep6_rx_fifo_rdata.">
|
|
<Bit Name="ep6_rx_fifo_rdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep7_fifo_config" Authority="RW" Address="0x4000D170" Width="32" Description="ep7_fifo_config.">
|
|
<Bit Name="ep7_rx_fifo_underflow" Authority="RW" Bits="7" />
|
|
<Bit Name="ep7_rx_fifo_overflow" Authority="RW" Bits="6" />
|
|
<Bit Name="ep7_tx_fifo_underflow" Authority="RW" Bits="5" />
|
|
<Bit Name="ep7_tx_fifo_overflow" Authority="RW" Bits="4" />
|
|
<Bit Name="ep7_rx_fifo_clr" Authority="RW" Bits="3" />
|
|
<Bit Name="ep7_tx_fifo_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="ep7_dma_rx_en" Authority="RW" Bits="1" />
|
|
<Bit Name="ep7_dma_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ep7_fifo_status" Authority="RW" Address="0x4000D174" Width="32" Description="ep7_fifo_status.">
|
|
<Bit Name="ep7_rx_fifo_full" Authority="RW" Bits="31" />
|
|
<Bit Name="ep7_rx_fifo_empty" Authority="RW" Bits="30" />
|
|
<Bit Name="ep7_rx_fifo_cnt" Authority="RW" Bits="22-16" />
|
|
<Bit Name="ep7_tx_fifo_full" Authority="RW" Bits="15" />
|
|
<Bit Name="ep7_tx_fifo_empty" Authority="RW" Bits="14" />
|
|
<Bit Name="ep7_tx_fifo_cnt" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="ep7_tx_fifo_wdata" Authority="RW" Address="0x4000D178" Width="32" Description="ep7_tx_fifo_wdata.">
|
|
<Bit Name="ep7_tx_fifo_wdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="ep7_rx_fifo_rdata" Authority="RW" Address="0x4000D17C" Width="32" Description="ep7_rx_fifo_rdata.">
|
|
<Bit Name="ep7_rx_fifo_rdata" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="rsvd_0" Authority="RW" Address="0x4000D1F0" Width="32" Description="rsvd_0.">
|
|
<Bit Name="rsvd_0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="rsvd_1" Authority="RW" Address="0x4000D1F4" Width="32" Description="rsvd_1.">
|
|
<Bit Name="rsvd_1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="xcvr_if_config" Authority="RW" Address="0x4000D1FC" Width="32" Description="xcvr_if_config.">
|
|
<Bit Name="sts_vbus_det" Authority="RW" Bits="31" />
|
|
<Bit Name="cr_xcvr_om_rx_dn" Authority="RW" Bits="11" />
|
|
<Bit Name="cr_xcvr_om_rx_dp" Authority="RW" Bits="10" />
|
|
<Bit Name="cr_xcvr_om_rx_d" Authority="RW" Bits="9" />
|
|
<Bit Name="cr_xcvr_om_rx_sel" Authority="RW" Bits="8" />
|
|
<Bit Name="cr_xcvr_force_rx_dn" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_xcvr_force_rx_dp" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_xcvr_force_rx_d" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_xcvr_force_rx_en" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_xcvr_force_tx_dn" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_xcvr_force_tx_dp" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_xcvr_force_tx_oe" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_xcvr_force_tx_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="pds">
|
|
<Register Name="PDS_CTL" Authority="RW" Address="0x4000E000" Width="32" Description="PDS_CTL.">
|
|
<Bit Name="cr_pds_ctrl_pll" Authority="RW" Bits="31-30" />
|
|
<Bit Name="cr_pds_ctrl_rf" Authority="RW" Bits="29-28" />
|
|
<Bit Name="cr_pds_ldo_vol" Authority="RW" Bits="27-24" />
|
|
<Bit Name="cr_pds_force_ram_clk_en" Authority="RW" Bits="23" />
|
|
<Bit Name="cr_pds_pd_ldo11" Authority="RW" Bits="22" />
|
|
<Bit Name="cr_np_wfi_mask" Authority="RW" Bits="21" />
|
|
<Bit Name="cr_pds_ram_lp_with_clk_en" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_pds_ldo_vsel_en" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_pds_rc32m_off_dis" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_pds_rst_soc_en" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_pds_soc_enb_force_on" Authority="RW" Bits="15" />
|
|
<Bit Name="cr_pds_pd_xtal" Authority="RW" Bits="14" />
|
|
<Bit Name="cr_pds_pwr_off" Authority="RW" Bits="13" />
|
|
<Bit Name="cr_pds_wait_xtal_rdy" Authority="RW" Bits="12" />
|
|
<Bit Name="cr_pds_iso_en" Authority="RW" Bits="11" />
|
|
<Bit Name="cr_sw_pu_flash" Authority="RW" Bits="10" />
|
|
<Bit Name="cr_pds_mem_stby" Authority="RW" Bits="9" />
|
|
<Bit Name="cr_pds_gate_clk" Authority="RW" Bits="8" />
|
|
<Bit Name="cr_pds_ctrl_pu_flash" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_pds_ctrl_gpio_ie_pu_pd" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_pds_pd_bg_sys" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_pds_pd_dcdc18" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_wifi_pds_save_state" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_xtal_force_off" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_sleep_forever" Authority="RW" Bits="1" />
|
|
<Bit Name="pds_start_ps" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="PDS_TIME1" Authority="RW" Address="0x4000E004" Width="32" Description="PDS_TIME1.">
|
|
<Bit Name="cr_sleep_duration" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="PDS_INT" Authority="RW" Address="0x4000E00C" Width="32" Description="PDS_INT.">
|
|
<Bit Name="ro_pds_wakeup_event" Authority="RW" Bits="31-24" />
|
|
<Bit Name="cr_pds_wakeup_src_en" Authority="RW" Bits="23-16" />
|
|
<Bit Name="cr_pds_int_clr" Authority="RW" Bits="15" />
|
|
<Bit Name="cr_pds_pll_done_int_mask" Authority="RW" Bits="11" />
|
|
<Bit Name="cr_pds_rf_done_int_mask" Authority="RW" Bits="10" />
|
|
<Bit Name="cr_pds_wake_int_mask" Authority="RW" Bits="8" />
|
|
<Bit Name="pds_clr_reset_event" Authority="RW" Bits="7" />
|
|
<Bit Name="pds_reset_event" Authority="RW" Bits="6-4" />
|
|
<Bit Name="ro_pds_pll_done_int" Authority="RW" Bits="3" />
|
|
<Bit Name="ro_pds_rf_done_int" Authority="RW" Bits="2" />
|
|
<Bit Name="ro_pds_wake_int" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="PDS_CTL2" Authority="RW" Address="0x4000E010" Width="32" Description="PDS_CTL2.">
|
|
<Bit Name="cr_pds_force_usb_gate_clk" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_pds_force_bz_gate_clk" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_pds_force_np_gate_clk" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_pds_force_usb_mem_stby" Authority="RW" Bits="15" />
|
|
<Bit Name="cr_pds_force_bz_mem_stby" Authority="RW" Bits="14" />
|
|
<Bit Name="cr_pds_force_np_mem_stby" Authority="RW" Bits="12" />
|
|
<Bit Name="cr_pds_force_usb_pds_rst" Authority="RW" Bits="11" />
|
|
<Bit Name="cr_pds_force_bz_pds_rst" Authority="RW" Bits="10" />
|
|
<Bit Name="cr_pds_force_np_pds_rst" Authority="RW" Bits="8" />
|
|
<Bit Name="cr_pds_force_usb_iso_en" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_pds_force_bz_iso_en" Authority="RW" Bits="6" />
|
|
<Bit Name="cr_pds_force_np_iso_en" Authority="RW" Bits="4" />
|
|
<Bit Name="cr_pds_force_usb_pwr_off" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_pds_force_bz_pwr_off" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_pds_force_np_pwr_off" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="PDS_CTL3" Authority="RW" Address="0x4000E014" Width="32" Description="PDS_CTL3.">
|
|
<Bit Name="cr_pds_misc_iso_en" Authority="RW" Bits="30" />
|
|
<Bit Name="cr_pds_usb_iso_en" Authority="RW" Bits="29" />
|
|
<Bit Name="cr_pds_ble_iso_en" Authority="RW" Bits="28" />
|
|
<Bit Name="cr_pds_bz_iso_en" Authority="RW" Bits="27" />
|
|
<Bit Name="cr_pds_np_iso_en" Authority="RW" Bits="24" />
|
|
<Bit Name="cr_pds_force_ble_gate_clk" Authority="RW" Bits="14" />
|
|
<Bit Name="cr_pds_force_misc_gate_clk" Authority="RW" Bits="13" />
|
|
<Bit Name="cr_pds_force_ble_mem_stby" Authority="RW" Bits="11" />
|
|
<Bit Name="cr_pds_force_misc_mem_stby" Authority="RW" Bits="10" />
|
|
<Bit Name="cr_pds_force_ble_pds_rst" Authority="RW" Bits="8" />
|
|
<Bit Name="cr_pds_force_misc_pds_rst" Authority="RW" Bits="7" />
|
|
<Bit Name="cr_pds_force_ble_iso_en" Authority="RW" Bits="5" />
|
|
<Bit Name="cr_pds_force_ble_pwr_off" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_pds_force_misc_pwr_off" Authority="RW" Bits="1" />
|
|
</Register>
|
|
<Register Name="PDS_CTL4" Authority="RW" Address="0x4000E018" Width="32" Description="PDS_CTL4.">
|
|
<Bit Name="cr_pds_misc_dig_pwr_off" Authority="RW" Bits="31" />
|
|
<Bit Name="cr_pds_misc_ana_pwr_off" Authority="RW" Bits="30" />
|
|
<Bit Name="cr_pds_misc_gate_clk" Authority="RW" Bits="27" />
|
|
<Bit Name="cr_pds_misc_mem_stby" Authority="RW" Bits="26" />
|
|
<Bit Name="cr_pds_misc_reset" Authority="RW" Bits="25" />
|
|
<Bit Name="cr_pds_misc_pwr_off" Authority="RW" Bits="24" />
|
|
<Bit Name="cr_pds_usb_gate_clk" Authority="RW" Bits="23" />
|
|
<Bit Name="cr_pds_usb_mem_stby" Authority="RW" Bits="22" />
|
|
<Bit Name="cr_pds_usb_reset" Authority="RW" Bits="21" />
|
|
<Bit Name="cr_pds_usb_pwr_off" Authority="RW" Bits="20" />
|
|
<Bit Name="cr_pds_ble_gate_clk" Authority="RW" Bits="19" />
|
|
<Bit Name="cr_pds_ble_mem_stby" Authority="RW" Bits="18" />
|
|
<Bit Name="cr_pds_ble_reset" Authority="RW" Bits="17" />
|
|
<Bit Name="cr_pds_ble_pwr_off" Authority="RW" Bits="16" />
|
|
<Bit Name="cr_pds_bz_gate_clk" Authority="RW" Bits="15" />
|
|
<Bit Name="cr_pds_bz_mem_stby" Authority="RW" Bits="14" />
|
|
<Bit Name="cr_pds_bz_reset" Authority="RW" Bits="13" />
|
|
<Bit Name="cr_pds_bz_pwr_off" Authority="RW" Bits="12" />
|
|
<Bit Name="cr_pds_np_gate_clk" Authority="RW" Bits="3" />
|
|
<Bit Name="cr_pds_np_mem_stby" Authority="RW" Bits="2" />
|
|
<Bit Name="cr_pds_np_reset" Authority="RW" Bits="1" />
|
|
<Bit Name="cr_pds_np_pwr_off" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="pds_stat" Authority="RW" Address="0x4000E01C" Width="32" Description="pds_stat.">
|
|
<Bit Name="ro_pds_pll_state" Authority="RW" Bits="17-16" />
|
|
<Bit Name="ro_pds_rf_state" Authority="RW" Bits="11-8" />
|
|
<Bit Name="ro_pds_state" Authority="RW" Bits="3-0" />
|
|
</Register>
|
|
<Register Name="pds_ram1" Authority="RW" Address="0x4000E020" Width="32" Description="pds_ram1.">
|
|
<Bit Name="cr_pds_ram_pgen" Authority="RW" Bits="11-8" />
|
|
<Bit Name="cr_pds_ram_ret2n" Authority="RW" Bits="7-4" />
|
|
<Bit Name="cr_pds_ram_ret1n" Authority="RW" Bits="3-0" />
|
|
</Register>
|
|
<Register Name="pds_gpio_set_pu_pd" Authority="RW" Address="0x4000E030" Width="32" Description="pds_gpio_set_pu_pd.">
|
|
<Bit Name="cr_pds_gpio_28_23_pu" Authority="RW" Bits="29-24" />
|
|
<Bit Name="cr_pds_gpio_28_23_pd" Authority="RW" Bits="21-16" />
|
|
<Bit Name="cr_pds_gpio_22_17_pu" Authority="RW" Bits="13-8" />
|
|
<Bit Name="cr_pds_gpio_22_17_pd" Authority="RW" Bits="5-0" />
|
|
</Register>
|
|
<Register Name="pds_gpio_int" Authority="RW" Address="0x4000E040" Width="32" Description="pds_gpio_int.">
|
|
<Bit Name="pds_gpio_int_select" Authority="RW" Bits="10-8" />
|
|
<Bit Name="pds_gpio_int_mode" Authority="RW" Bits="6-4" />
|
|
<Bit Name="pds_gpio_int_clr" Authority="RW" Bits="2" />
|
|
<Bit Name="pds_gpio_int_stat" Authority="RW" Bits="1" />
|
|
<Bit Name="pds_gpio_int_mask" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="rc32m_ctrl0" Authority="RW" Address="0x4000E300" Width="32" Description="rc32m_ctrl0.">
|
|
<Bit Name="rc32m_code_fr_ext" Authority="RW" Bits="29-22" />
|
|
<Bit Name="rc32m_pd" Authority="RW" Bits="21" />
|
|
<Bit Name="rc32m_cal_en" Authority="RW" Bits="20" />
|
|
<Bit Name="rc32m_ext_code_en" Authority="RW" Bits="19" />
|
|
<Bit Name="rc32m_refclk_half" Authority="RW" Bits="18" />
|
|
<Bit Name="rc32m_allow_cal" Authority="RW" Bits="17" />
|
|
<Bit Name="rc32m_dig_code_fr_cal" Authority="RW" Bits="13-6" />
|
|
<Bit Name="rc32m_cal_precharge" Authority="RW" Bits="5" />
|
|
<Bit Name="rc32m_cal_div" Authority="RW" Bits="4-3" />
|
|
<Bit Name="rc32m_cal_inprogress" Authority="RW" Bits="2" />
|
|
<Bit Name="rc32m_rdy" Authority="RW" Bits="1" />
|
|
<Bit Name="rc32m_cal_done" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="rc32m_ctrl1" Authority="RW" Address="0x4000E304" Width="32" Description="rc32m_ctrl1.">
|
|
<Bit Name="rc32m_reserved" Authority="RW" Bits="31-24" />
|
|
<Bit Name="rc32m_clk_force_on" Authority="RW" Bits="4" />
|
|
<Bit Name="rc32m_clk_inv" Authority="RW" Bits="3" />
|
|
<Bit Name="rc32m_clk_soft_rst" Authority="RW" Bits="2" />
|
|
<Bit Name="rc32m_soft_rst" Authority="RW" Bits="1" />
|
|
<Bit Name="rc32m_test_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="pu_rst_clkpll" Authority="RW" Address="0x4000E400" Width="32" Description="pu_rst_clkpll.">
|
|
<Bit Name="pu_clkpll" Authority="RW" Bits="10" />
|
|
<Bit Name="pu_clkpll_sfreg" Authority="RW" Bits="9" />
|
|
<Bit Name="clkpll_pu_cp" Authority="RW" Bits="8" />
|
|
<Bit Name="clkpll_pu_pfd" Authority="RW" Bits="7" />
|
|
<Bit Name="clkpll_pu_clamp_op" Authority="RW" Bits="6" />
|
|
<Bit Name="clkpll_pu_fbdv" Authority="RW" Bits="5" />
|
|
<Bit Name="clkpll_pu_postdiv" Authority="RW" Bits="4" />
|
|
<Bit Name="clkpll_reset_refdiv" Authority="RW" Bits="3" />
|
|
<Bit Name="clkpll_reset_fbdv" Authority="RW" Bits="2" />
|
|
<Bit Name="clkpll_reset_postdiv" Authority="RW" Bits="1" />
|
|
<Bit Name="clkpll_sdm_reset" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="clkpll_top_ctrl" Authority="RW" Address="0x4000E404" Width="32" Description="clkpll_top_ctrl.">
|
|
<Bit Name="clkpll_resv" Authority="RW" Bits="25-24" />
|
|
<Bit Name="clkpll_vg11_sel" Authority="RW" Bits="21-20" />
|
|
<Bit Name="clkpll_refclk_sel" Authority="RW" Bits="16" />
|
|
<Bit Name="clkpll_xtal_rc32m_sel" Authority="RW" Bits="12" />
|
|
<Bit Name="clkpll_refdiv_ratio" Authority="RW" Bits="11-8" />
|
|
<Bit Name="clkpll_postdiv" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="clkpll_cp" Authority="RW" Address="0x4000E408" Width="32" Description="clkpll_cp.">
|
|
<Bit Name="clkpll_cp_opamp_en" Authority="RW" Bits="10" />
|
|
<Bit Name="clkpll_cp_startup_en" Authority="RW" Bits="9" />
|
|
<Bit Name="clkpll_int_frac_sw" Authority="RW" Bits="8" />
|
|
<Bit Name="clkpll_icp_1u" Authority="RW" Bits="7-6" />
|
|
<Bit Name="clkpll_icp_5u" Authority="RW" Bits="5-4" />
|
|
<Bit Name="clkpll_sel_cp_bias" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="clkpll_rz" Authority="RW" Address="0x4000E40C" Width="32" Description="clkpll_rz.">
|
|
<Bit Name="clkpll_rz" Authority="RW" Bits="18-16" />
|
|
<Bit Name="clkpll_cz" Authority="RW" Bits="15-14" />
|
|
<Bit Name="clkpll_c3" Authority="RW" Bits="13-12" />
|
|
<Bit Name="clkpll_r4_short" Authority="RW" Bits="8" />
|
|
<Bit Name="clkpll_r4" Authority="RW" Bits="5-4" />
|
|
<Bit Name="clkpll_c4_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="clkpll_fbdv" Authority="RW" Address="0x4000E410" Width="32" Description="clkpll_fbdv.">
|
|
<Bit Name="clkpll_sel_fb_clk" Authority="RW" Bits="3-2" />
|
|
<Bit Name="clkpll_sel_sample_clk" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="clkpll_vco" Authority="RW" Address="0x4000E414" Width="32" Description="clkpll_vco.">
|
|
<Bit Name="clkpll_shrtr" Authority="RW" Bits="3" />
|
|
<Bit Name="clkpll_vco_speed" Authority="RW" Bits="2-0" />
|
|
</Register>
|
|
<Register Name="clkpll_sdm" Authority="RW" Address="0x4000E418" Width="32" Description="clkpll_sdm.">
|
|
<Bit Name="clkpll_sdm_bypass" Authority="RW" Bits="29" />
|
|
<Bit Name="clkpll_sdm_flag" Authority="RW" Bits="28" />
|
|
<Bit Name="clkpll_dither_sel" Authority="RW" Bits="25-24" />
|
|
<Bit Name="clkpll_sdmin" Authority="RW" Bits="23-0" />
|
|
</Register>
|
|
<Register Name="clkpll_output_en" Authority="RW" Address="0x4000E41C" Width="32" Description="clkpll_output_en.">
|
|
<Bit Name="clkpll_en_div2_480m" Authority="RW" Bits="9" />
|
|
<Bit Name="clkpll_en_32m" Authority="RW" Bits="8" />
|
|
<Bit Name="clkpll_en_48m" Authority="RW" Bits="7" />
|
|
<Bit Name="clkpll_en_80m" Authority="RW" Bits="6" />
|
|
<Bit Name="clkpll_en_96m" Authority="RW" Bits="5" />
|
|
<Bit Name="clkpll_en_120m" Authority="RW" Bits="4" />
|
|
<Bit Name="clkpll_en_160m" Authority="RW" Bits="3" />
|
|
<Bit Name="clkpll_en_192m" Authority="RW" Bits="2" />
|
|
<Bit Name="clkpll_en_240m" Authority="RW" Bits="1" />
|
|
<Bit Name="clkpll_en_480m" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="clkpll_test_enable" Authority="RW" Address="0x4000E420" Width="32" Description="clkpll_test_enable.">
|
|
<Bit Name="clkpll_dc_tp_out_en" Authority="RW" Bits="8" />
|
|
<Bit Name="ten_clkpll" Authority="RW" Bits="7" />
|
|
<Bit Name="ten_clkpll_sfreg" Authority="RW" Bits="6" />
|
|
<Bit Name="dten_clkpll_fin" Authority="RW" Bits="5" />
|
|
<Bit Name="dten_clkpll_fref" Authority="RW" Bits="4" />
|
|
<Bit Name="dten_clkpll_fsdm" Authority="RW" Bits="3" />
|
|
<Bit Name="dten_clk32M" Authority="RW" Bits="2" />
|
|
<Bit Name="dten_clk96M" Authority="RW" Bits="1" />
|
|
<Bit Name="dten_clkpll_postdiv_clk" Authority="RW" Bits="0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="hbn">
|
|
<Register Name="HBN_CTL" Authority="RW" Address="0x4000F000" Width="32" Description="HBN_CTL.">
|
|
<Bit Name="hbn_state" Authority="RW" Bits="31-28" />
|
|
<Bit Name="sram_slp" Authority="RW" Bits="27" />
|
|
<Bit Name="sram_slp_option" Authority="RW" Bits="26" />
|
|
<Bit Name="pwr_on_option" Authority="RW" Bits="25" />
|
|
<Bit Name="rtc_dly_option" Authority="RW" Bits="24" />
|
|
<Bit Name="pu_dcdc18_aon" Authority="RW" Bits="23" />
|
|
<Bit Name="hbn_ldo11_aon_vout_sel" Authority="RW" Bits="22-19" />
|
|
<Bit Name="hbn_ldo11_rt_vout_sel" Authority="RW" Bits="18-15" />
|
|
<Bit Name="hbn_dis_pwr_off_ldo11_rt" Authority="RW" Bits="14" />
|
|
<Bit Name="hbn_dis_pwr_off_ldo11" Authority="RW" Bits="13" />
|
|
<Bit Name="sw_rst" Authority="RW" Bits="12" />
|
|
<Bit Name="pwrdn_hbn_rtc" Authority="RW" Bits="11" />
|
|
<Bit Name="pwrdn_hbn_core" Authority="RW" Bits="9" />
|
|
<Bit Name="trap_mode" Authority="RW" Bits="8" />
|
|
<Bit Name="hbn_mode" Authority="RW" Bits="7" />
|
|
<Bit Name="rtc_ctl" Authority="RW" Bits="6-0" />
|
|
</Register>
|
|
<Register Name="HBN_TIME_L" Authority="RW" Address="0x4000F004" Width="32" Description="HBN_TIME_L.">
|
|
<Bit Name="hbn_time_l" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="HBN_TIME_H" Authority="RW" Address="0x4000F008" Width="32" Description="HBN_TIME_H.">
|
|
<Bit Name="hbn_time_h" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="RTC_TIME_L" Authority="RW" Address="0x4000F00C" Width="32" Description="RTC_TIME_L.">
|
|
<Bit Name="rtc_time_latch_l" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="RTC_TIME_H" Authority="RW" Address="0x4000F010" Width="32" Description="RTC_TIME_H.">
|
|
<Bit Name="rtc_time_latch" Authority="RW" Bits="31" />
|
|
<Bit Name="rtc_time_latch_h" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="HBN_IRQ_MODE" Authority="RW" Address="0x4000F014" Width="32" Description="HBN_IRQ_MODE.">
|
|
<Bit Name="pin_wakeup_en" Authority="RW" Bits="27" />
|
|
<Bit Name="pin_wakeup_sel" Authority="RW" Bits="26-24" />
|
|
<Bit Name="irq_acomp1_en" Authority="RW" Bits="23-22" />
|
|
<Bit Name="irq_acomp0_en" Authority="RW" Bits="21-20" />
|
|
<Bit Name="irq_bor_en" Authority="RW" Bits="18" />
|
|
<Bit Name="reg_en_hw_pu_pd" Authority="RW" Bits="16" />
|
|
<Bit Name="reg_aon_pad_ie_smt" Authority="RW" Bits="12-8" />
|
|
<Bit Name="hbn_pin_wakeup_mask" Authority="RW" Bits="7-3" />
|
|
<Bit Name="hbn_pin_wakeup_mode" Authority="RW" Bits="2-0" />
|
|
</Register>
|
|
<Register Name="HBN_IRQ_STAT" Authority="RW" Address="0x4000F018" Width="32" Description="HBN_IRQ_STAT.">
|
|
<Bit Name="irq_stat" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="HBN_IRQ_CLR" Authority="RW" Address="0x4000F01C" Width="32" Description="HBN_IRQ_CLR.">
|
|
<Bit Name="irq_clr" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="HBN_PIR_CFG" Authority="RW" Address="0x4000F020" Width="32" Description="HBN_PIR_CFG.">
|
|
<Bit Name="gpadc_nosync" Authority="RW" Bits="9" />
|
|
<Bit Name="gpadc_cgen" Authority="RW" Bits="8" />
|
|
<Bit Name="pir_en" Authority="RW" Bits="7" />
|
|
<Bit Name="pir_dis" Authority="RW" Bits="5-4" />
|
|
<Bit Name="pir_lpf_sel" Authority="RW" Bits="2" />
|
|
<Bit Name="pir_hpf_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="HBN_PIR_VTH" Authority="RW" Address="0x4000F024" Width="32" Description="HBN_PIR_VTH.">
|
|
<Bit Name="pir_vth" Authority="RW" Bits="13-0" />
|
|
</Register>
|
|
<Register Name="HBN_PIR_INTERVAL" Authority="RW" Address="0x4000F028" Width="32" Description="HBN_PIR_INTERVAL.">
|
|
<Bit Name="pir_interval" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="HBN_MISC" Authority="RW" Address="0x4000Fx2C" Width="32" Description="HBN_MISC.">
|
|
<Bit Name="hbn_flash_pulldown_aon" Authority="RW" Bits="29-24" />
|
|
<Bit Name="hbn_flash_pullup_aon" Authority="RW" Bits="21-16" />
|
|
<Bit Name="r_bor_out" Authority="RW" Bits="3" />
|
|
<Bit Name="pu_bor" Authority="RW" Bits="2" />
|
|
<Bit Name="bor_vth" Authority="RW" Bits="1" />
|
|
<Bit Name="bor_sel" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="HBN_GLB" Authority="RW" Address="0x4000F030" Width="32" Description="HBN_GLB.">
|
|
<Bit Name="sw_ldo11_aon_vout_sel" Authority="RW" Bits="31-28" />
|
|
<Bit Name="sw_ldo11_rt_vout_sel" Authority="RW" Bits="27-24" />
|
|
<Bit Name="sw_ldo11soc_vout_sel_aon" Authority="RW" Bits="19-16" />
|
|
<Bit Name="hbn_clear_reset_event" Authority="RW" Bits="13" />
|
|
<Bit Name="hbn_reset_event" Authority="RW" Bits="12-8" />
|
|
<Bit Name="ldo11_rt_iload_sel" Authority="RW" Bits="7-6" />
|
|
<Bit Name="hbn_pu_rc32k" Authority="RW" Bits="5" />
|
|
<Bit Name="hbn_f32k_sel" Authority="RW" Bits="4-3" />
|
|
<Bit Name="hbn_uart_clk_sel" Authority="RW" Bits="2" />
|
|
<Bit Name="hbn_root_clk_sel" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="HBN_SRAM" Authority="RW" Address="0x4000F034" Width="32" Description="HBN_SRAM.">
|
|
<Bit Name="retram_slp" Authority="RW" Bits="7" />
|
|
<Bit Name="retram_ret" Authority="RW" Bits="6" />
|
|
<Bit Name="retram_emaw" Authority="RW" Bits="4-3" />
|
|
<Bit Name="retram_ema" Authority="RW" Bits="2-0" />
|
|
</Register>
|
|
<Register Name="HBN_RSV0" Authority="RW" Address="0x4000F100" Width="32" Description="HBN_RSV0.">
|
|
<Bit Name="HBN_RSV0" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="HBN_RSV1" Authority="RW" Address="0x4000F104" Width="32" Description="HBN_RSV1.">
|
|
<Bit Name="HBN_RSV1" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="HBN_RSV2" Authority="RW" Address="0x4000F108" Width="32" Description="HBN_RSV2.">
|
|
<Bit Name="HBN_RSV2" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="HBN_RSV3" Authority="RW" Address="0x4000F10C" Width="32" Description="HBN_RSV3.">
|
|
<Bit Name="HBN_RSV3" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="rc32k_ctrl0" Authority="RW" Address="0x4000F200" Width="32" Description="rc32k_ctrl0.">
|
|
<Bit Name="rc32k_code_fr_ext" Authority="RW" Bits="31-22" />
|
|
<Bit Name="rc32k_cal_en" Authority="RW" Bits="20" />
|
|
<Bit Name="rc32k_ext_code_en" Authority="RW" Bits="19" />
|
|
<Bit Name="rc32k_allow_cal" Authority="RW" Bits="18" />
|
|
<Bit Name="rc32k_vref_dly" Authority="RW" Bits="17-16" />
|
|
<Bit Name="rc32k_dig_code_fr_cal" Authority="RW" Bits="15-6" />
|
|
<Bit Name="rc32k_cal_precharge" Authority="RW" Bits="5" />
|
|
<Bit Name="rc32k_cal_div" Authority="RW" Bits="4-3" />
|
|
<Bit Name="rc32k_cal_inprogress" Authority="RW" Bits="2" />
|
|
<Bit Name="rc32k_rdy" Authority="RW" Bits="1" />
|
|
<Bit Name="rc32k_cal_done" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="xtal32k" Authority="RW" Address="0x4000F204" Width="32" Description="xtal32k.">
|
|
<Bit Name="pu_xtal32k" Authority="RW" Bits="19" />
|
|
<Bit Name="pu_xtal32k_buf" Authority="RW" Bits="18" />
|
|
<Bit Name="xtal32k_ac_cap_short" Authority="RW" Bits="17" />
|
|
<Bit Name="xtal32k_capbank" Authority="RW" Bits="16-11" />
|
|
<Bit Name="xtal32k_inv_stre" Authority="RW" Bits="10-9" />
|
|
<Bit Name="xtal32k_otf_short" Authority="RW" Bits="8" />
|
|
<Bit Name="xtal32k_outbuf_stre" Authority="RW" Bits="7" />
|
|
<Bit Name="xtal32k_reg" Authority="RW" Bits="6-5" />
|
|
<Bit Name="xtal32k_amp_ctrl" Authority="RW" Bits="4-3" />
|
|
<Bit Name="xtal32k_ext_sel" Authority="RW" Bits="2" />
|
|
<Bit Name="xtal32k_lowv_en" Authority="RW" Bits="1" />
|
|
<Bit Name="xtal32k_hiz_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
</Peripheral>
|
|
<Peripheral Name="aon">
|
|
<Register Name="aon" Authority="RW" Address="0x4000F800" Width="32" Description="aon.">
|
|
<Bit Name="sw_pu_ldo11_rt" Authority="RW" Bits="22" />
|
|
<Bit Name="ldo11_rt_pulldown_sel" Authority="RW" Bits="21" />
|
|
<Bit Name="ldo11_rt_pulldown" Authority="RW" Bits="20" />
|
|
<Bit Name="pu_aon_dc_tbuf" Authority="RW" Bits="12" />
|
|
<Bit Name="aon_resv" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="aon_common" Authority="RW" Address="0x4000F804" Width="32" Description="aon_common.">
|
|
<Bit Name="ten_cip_misc_aon" Authority="RW" Bits="20" />
|
|
<Bit Name="ten_mbg_aon" Authority="RW" Bits="19" />
|
|
<Bit Name="dten_xtal_aon" Authority="RW" Bits="18" />
|
|
<Bit Name="ten_xtal_aon" Authority="RW" Bits="17" />
|
|
<Bit Name="ten_ldo15rf_aon" Authority="RW" Bits="16" />
|
|
<Bit Name="ten_bg_sys_aon" Authority="RW" Bits="12" />
|
|
<Bit Name="ten_dcdc18_1_aon" Authority="RW" Bits="11" />
|
|
<Bit Name="ten_dcdc18_0_aon" Authority="RW" Bits="10" />
|
|
<Bit Name="ten_ldo11soc_aon" Authority="RW" Bits="9" />
|
|
<Bit Name="ten_vddcore_aon" Authority="RW" Bits="8" />
|
|
<Bit Name="ten_xtal32k" Authority="RW" Bits="6" />
|
|
<Bit Name="dten_xtal32k" Authority="RW" Bits="5" />
|
|
<Bit Name="ten_aon" Authority="RW" Bits="4" />
|
|
<Bit Name="tmux_aon" Authority="RW" Bits="2-0" />
|
|
</Register>
|
|
<Register Name="aon_misc" Authority="RW" Address="0x4000F808" Width="32" Description="aon_misc.">
|
|
<Bit Name="sw_bz_en_aon" Authority="RW" Bits="1" />
|
|
<Bit Name="sw_soc_en_aon" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="bg_sys_top" Authority="RW" Address="0x4000F810" Width="32" Description="bg_sys_top.">
|
|
<Bit Name="bg_sys_start_ctrl_aon" Authority="RW" Bits="12" />
|
|
<Bit Name="pu_bg_sys_aon" Authority="RW" Bits="8" />
|
|
<Bit Name="pmip_resv" Authority="RW" Bits="7-0" />
|
|
</Register>
|
|
<Register Name="dcdc18_top_0" Authority="RW" Address="0x4000F814" Width="32" Description="dcdc18_top_0.">
|
|
<Bit Name="dcdc18_rdy_aon" Authority="RW" Bits="31" />
|
|
<Bit Name="dcdc18_sstart_time_aon" Authority="RW" Bits="29-28" />
|
|
<Bit Name="dcdc18_osc_inhibit_t2_aon" Authority="RW" Bits="27" />
|
|
<Bit Name="dcdc18_slow_osc_aon" Authority="RW" Bits="26" />
|
|
<Bit Name="dcdc18_stop_osc_aon" Authority="RW" Bits="25" />
|
|
<Bit Name="dcdc18_slope_curr_sel_aon" Authority="RW" Bits="24-20" />
|
|
<Bit Name="dcdc18_osc_freq_trim_aon" Authority="RW" Bits="19-16" />
|
|
<Bit Name="dcdc18_osc_2m_mode_aon" Authority="RW" Bits="12" />
|
|
<Bit Name="dcdc18_vpfm_aon" Authority="RW" Bits="11-8" />
|
|
<Bit Name="dcdc18_vout_sel_aon" Authority="RW" Bits="5-1" />
|
|
</Register>
|
|
<Register Name="dcdc18_top_1" Authority="RW" Address="0x4000F818" Width="32" Description="dcdc18_top_1.">
|
|
<Bit Name="dcdc18_pulldown_aon" Authority="RW" Bits="29" />
|
|
<Bit Name="dcdc18_en_antiring_aon" Authority="RW" Bits="28" />
|
|
<Bit Name="dcdc18_cfb_sel_aon" Authority="RW" Bits="27-24" />
|
|
<Bit Name="dcdc18_chf_sel_aon" Authority="RW" Bits="23-20" />
|
|
<Bit Name="dcdc18_rc_sel_aon" Authority="RW" Bits="19-16" />
|
|
<Bit Name="dcdc18_nonoverlap_td_aon" Authority="RW" Bits="12-8" />
|
|
<Bit Name="dcdc18_zvs_td_opt_aon" Authority="RW" Bits="6-4" />
|
|
<Bit Name="dcdc18_cs_delay_aon" Authority="RW" Bits="3-1" />
|
|
<Bit Name="dcdc18_force_cs_zvs_aon" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="ldo11soc_and_dctest" Authority="RW" Address="0x4000F81C" Width="32" Description="ldo11soc_and_dctest.">
|
|
<Bit Name="pmip_dc_tp_out_en_aon" Authority="RW" Bits="31" />
|
|
<Bit Name="pu_vddcore_misc_aon" Authority="RW" Bits="30" />
|
|
<Bit Name="ldo11soc_power_good_aon" Authority="RW" Bits="29" />
|
|
<Bit Name="ldo11soc_rdy_aon" Authority="RW" Bits="28" />
|
|
<Bit Name="ldo11soc_cc_aon" Authority="RW" Bits="25-24" />
|
|
<Bit Name="ldo11soc_vth_sel_aon" Authority="RW" Bits="13-12" />
|
|
<Bit Name="ldo11soc_pulldown_sel_aon" Authority="RW" Bits="11" />
|
|
<Bit Name="ldo11soc_pulldown_aon" Authority="RW" Bits="10" />
|
|
<Bit Name="ldo11soc_sstart_delay_aon" Authority="RW" Bits="9-8" />
|
|
<Bit Name="ldo11soc_sstart_sel_aon" Authority="RW" Bits="4" />
|
|
<Bit Name="pu_ldo11soc_aon" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="psw_irrcv" Authority="RW" Address="0x4000F820" Width="32" Description="psw_irrcv.">
|
|
<Bit Name="pu_ir_psw_aon" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="rf_top_aon" Authority="RW" Address="0x4000F880" Width="32" Description="rf_top_aon.">
|
|
<Bit Name="ldo15rf_bypass_aon" Authority="RW" Bits="28" />
|
|
<Bit Name="ldo15rf_cc_aon" Authority="RW" Bits="25-24" />
|
|
<Bit Name="ldo15rf_vout_sel_aon" Authority="RW" Bits="18-16" />
|
|
<Bit Name="ldo15rf_pulldown_sel_aon" Authority="RW" Bits="13" />
|
|
<Bit Name="ldo15rf_pulldown_aon" Authority="RW" Bits="12" />
|
|
<Bit Name="ldo15rf_sstart_delay_aon" Authority="RW" Bits="10-9" />
|
|
<Bit Name="ldo15rf_sstart_sel_aon" Authority="RW" Bits="8" />
|
|
<Bit Name="pu_xtal_aon" Authority="RW" Bits="5" />
|
|
<Bit Name="pu_xtal_buf_aon" Authority="RW" Bits="4" />
|
|
<Bit Name="pu_sfreg_aon" Authority="RW" Bits="2" />
|
|
<Bit Name="pu_ldo15rf_aon" Authority="RW" Bits="1" />
|
|
<Bit Name="pu_mbg_aon" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="xtal_cfg" Authority="RW" Address="0x4000F884" Width="32" Description="xtal_cfg.">
|
|
<Bit Name="xtal_rdy_sel_aon" Authority="RW" Bits="31-30" />
|
|
<Bit Name="xtal_gm_boost_aon" Authority="RW" Bits="29-28" />
|
|
<Bit Name="xtal_capcode_in_aon" Authority="RW" Bits="27-22" />
|
|
<Bit Name="xtal_capcode_out_aon" Authority="RW" Bits="21-16" />
|
|
<Bit Name="xtal_amp_ctrl_aon" Authority="RW" Bits="15-14" />
|
|
<Bit Name="xtal_sleep_aon" Authority="RW" Bits="13" />
|
|
<Bit Name="xtal_fast_startup_aon" Authority="RW" Bits="12" />
|
|
<Bit Name="xtal_buf_hp_aon" Authority="RW" Bits="11-8" />
|
|
<Bit Name="xtal_buf_en_aon" Authority="RW" Bits="7-4" />
|
|
<Bit Name="xtal_ext_sel_aon" Authority="RW" Bits="3" />
|
|
<Bit Name="xtal_capcode_extra_aon" Authority="RW" Bits="2" />
|
|
<Bit Name="xtal_bk_aon" Authority="RW" Bits="1-0" />
|
|
</Register>
|
|
<Register Name="tsen" Authority="RW" Address="0x4000F888" Width="32" Description="tsen.">
|
|
<Bit Name="xtal_rdy_int_sel_aon" Authority="RW" Bits="31-30" />
|
|
<Bit Name="xtal_inn_cfg_en_aon" Authority="RW" Bits="29" />
|
|
<Bit Name="xtal_rdy" Authority="RW" Bits="28" />
|
|
<Bit Name="tsen_refcode_rfcal" Authority="RW" Bits="27-16" />
|
|
<Bit Name="tsen_refcode_corner" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="acomp0_ctrl" Authority="RW" Address="0x4000F900" Width="32" Description="acomp0_ctrl.">
|
|
<Bit Name="acomp0_muxen" Authority="RW" Bits="26" />
|
|
<Bit Name="acomp0_pos_sel" Authority="RW" Bits="25-22" />
|
|
<Bit Name="acomp0_neg_sel" Authority="RW" Bits="21-18" />
|
|
<Bit Name="acomp0_level_sel" Authority="RW" Bits="17-12" />
|
|
<Bit Name="acomp0_bias_prog" Authority="RW" Bits="11-10" />
|
|
<Bit Name="acomp0_hyst_selp" Authority="RW" Bits="9-7" />
|
|
<Bit Name="acomp0_hyst_seln" Authority="RW" Bits="6-4" />
|
|
<Bit Name="acomp0_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="acomp1_ctrl" Authority="RW" Address="0x4000F904" Width="32" Description="acomp1_ctrl.">
|
|
<Bit Name="acomp1_muxen" Authority="RW" Bits="26" />
|
|
<Bit Name="acomp1_pos_sel" Authority="RW" Bits="25-22" />
|
|
<Bit Name="acomp1_neg_sel" Authority="RW" Bits="21-18" />
|
|
<Bit Name="acomp1_level_sel" Authority="RW" Bits="17-12" />
|
|
<Bit Name="acomp1_bias_prog" Authority="RW" Bits="11-10" />
|
|
<Bit Name="acomp1_hyst_selp" Authority="RW" Bits="9-7" />
|
|
<Bit Name="acomp1_hyst_seln" Authority="RW" Bits="6-4" />
|
|
<Bit Name="acomp1_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="acomp_ctrl" Authority="RW" Address="0x4000F908" Width="32" Description="acomp_ctrl.">
|
|
<Bit Name="acomp_reserved" Authority="RW" Bits="31-24" />
|
|
<Bit Name="acomp0_out_raw" Authority="RW" Bits="19" />
|
|
<Bit Name="acomp1_out_raw" Authority="RW" Bits="17" />
|
|
<Bit Name="acomp0_test_sel" Authority="RW" Bits="13-12" />
|
|
<Bit Name="acomp1_test_sel" Authority="RW" Bits="11-10" />
|
|
<Bit Name="acomp0_test_en" Authority="RW" Bits="9" />
|
|
<Bit Name="acomp1_test_en" Authority="RW" Bits="8" />
|
|
<Bit Name="acomp0_rstn_ana" Authority="RW" Bits="1" />
|
|
<Bit Name="acomp1_rstn_ana" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="gpadc_reg_cmd" Authority="RW" Address="0x4000F90C" Width="32" Description="gpadc_reg_cmd.">
|
|
<Bit Name="gpadc_sen_test_en" Authority="RW" Bits="30" />
|
|
<Bit Name="gpadc_sen_sel" Authority="RW" Bits="29-28" />
|
|
<Bit Name="gpadc_chip_sen_pu" Authority="RW" Bits="27" />
|
|
<Bit Name="gpadc_micboost_32db_en" Authority="RW" Bits="23" />
|
|
<Bit Name="gpadc_mic_pga2_gain" Authority="RW" Bits="22-21" />
|
|
<Bit Name="gpadc_mic1_diff" Authority="RW" Bits="20" />
|
|
<Bit Name="gpadc_mic2_diff" Authority="RW" Bits="19" />
|
|
<Bit Name="gpadc_dwa_en" Authority="RW" Bits="18" />
|
|
<Bit Name="gpadc_byp_micboost" Authority="RW" Bits="16" />
|
|
<Bit Name="gpadc_micpga_en" Authority="RW" Bits="15" />
|
|
<Bit Name="gpadc_micbias_en" Authority="RW" Bits="14" />
|
|
<Bit Name="gpadc_neg_gnd" Authority="RW" Bits="13" />
|
|
<Bit Name="gpadc_pos_sel" Authority="RW" Bits="12-8" />
|
|
<Bit Name="gpadc_neg_sel" Authority="RW" Bits="7-3" />
|
|
<Bit Name="gpadc_soft_rst" Authority="RW" Bits="2" />
|
|
<Bit Name="gpadc_conv_start" Authority="RW" Bits="1" />
|
|
<Bit Name="gpadc_global_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="gpadc_reg_config1" Authority="RW" Address="0x4000F910" Width="32" Description="gpadc_reg_config1.">
|
|
<Bit Name="gpadc_v18_sel" Authority="RW" Bits="30-29" />
|
|
<Bit Name="gpadc_v11_sel" Authority="RW" Bits="28-27" />
|
|
<Bit Name="gpadc_dither_en" Authority="RW" Bits="26" />
|
|
<Bit Name="gpadc_scan_en" Authority="RW" Bits="25" />
|
|
<Bit Name="gpadc_scan_length" Authority="RW" Bits="24-21" />
|
|
<Bit Name="gpadc_clk_div_ratio" Authority="RW" Bits="20-18" />
|
|
<Bit Name="gpadc_clk_ana_inv" Authority="RW" Bits="17" />
|
|
<Bit Name="gpadc_lowv_det_en" Authority="RW" Bits="10" />
|
|
<Bit Name="gpadc_vcm_hyst_sel" Authority="RW" Bits="9" />
|
|
<Bit Name="gpadc_vcm_sel_en" Authority="RW" Bits="8" />
|
|
<Bit Name="gpadc_res_sel" Authority="RW" Bits="4-2" />
|
|
<Bit Name="gpadc_cont_conv_en" Authority="RW" Bits="1" />
|
|
<Bit Name="gpadc_cal_os_en" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="gpadc_reg_config2" Authority="RW" Address="0x4000F914" Width="32" Description="gpadc_reg_config2.">
|
|
<Bit Name="gpadc_tsvbe_low" Authority="RW" Bits="31" />
|
|
<Bit Name="gpadc_dly_sel" Authority="RW" Bits="30-28" />
|
|
<Bit Name="gpadc_pga1_gain" Authority="RW" Bits="27-25" />
|
|
<Bit Name="gpadc_pga2_gain" Authority="RW" Bits="24-22" />
|
|
<Bit Name="gpadc_test_sel" Authority="RW" Bits="21-19" />
|
|
<Bit Name="gpadc_test_en" Authority="RW" Bits="18" />
|
|
<Bit Name="gpadc_bias_sel" Authority="RW" Bits="17" />
|
|
<Bit Name="gpadc_chop_mode" Authority="RW" Bits="16-15" />
|
|
<Bit Name="gpadc_pga_vcmi_en" Authority="RW" Bits="14" />
|
|
<Bit Name="gpadc_pga_en" Authority="RW" Bits="13" />
|
|
<Bit Name="gpadc_pga_os_cal" Authority="RW" Bits="12-9" />
|
|
<Bit Name="gpadc_pga_vcm" Authority="RW" Bits="8-7" />
|
|
<Bit Name="gpadc_ts_en" Authority="RW" Bits="6" />
|
|
<Bit Name="gpadc_tsext_sel" Authority="RW" Bits="5" />
|
|
<Bit Name="gpadc_vbat_en" Authority="RW" Bits="4" />
|
|
<Bit Name="gpadc_vref_sel" Authority="RW" Bits="3" />
|
|
<Bit Name="gpadc_diff_mode" Authority="RW" Bits="2" />
|
|
</Register>
|
|
<Register Name="gpadc_reg_scn_pos1" Authority="RW" Address="0x4000F918" Width="32" Description="adc converation sequence 1">
|
|
<Bit Name="gpadc_scan_pos_5" Authority="RW" Bits="29-25" />
|
|
<Bit Name="gpadc_scan_pos_4" Authority="RW" Bits="24-20" />
|
|
<Bit Name="gpadc_scan_pos_3" Authority="RW" Bits="19-15" />
|
|
<Bit Name="gpadc_scan_pos_2" Authority="RW" Bits="14-10" />
|
|
<Bit Name="gpadc_scan_pos_1" Authority="RW" Bits="9-5" />
|
|
<Bit Name="gpadc_scan_pos_0" Authority="RW" Bits="4-0" />
|
|
</Register>
|
|
<Register Name="gpadc_reg_scn_pos2" Authority="RW" Address="0x4000F91C" Width="32" Description="adc converation sequence 2">
|
|
<Bit Name="gpadc_scan_pos_11" Authority="RW" Bits="29-25" />
|
|
<Bit Name="gpadc_scan_pos_10" Authority="RW" Bits="24-20" />
|
|
<Bit Name="gpadc_scan_pos_9" Authority="RW" Bits="19-15" />
|
|
<Bit Name="gpadc_scan_pos_8" Authority="RW" Bits="14-10" />
|
|
<Bit Name="gpadc_scan_pos_7" Authority="RW" Bits="9-5" />
|
|
<Bit Name="gpadc_scan_pos_6" Authority="RW" Bits="4-0" />
|
|
</Register>
|
|
<Register Name="gpadc_reg_scn_neg1" Authority="RW" Address="0x4000F920" Width="32" Description="adc converation sequence 3">
|
|
<Bit Name="gpadc_scan_neg_5" Authority="RW" Bits="29-25" />
|
|
<Bit Name="gpadc_scan_neg_4" Authority="RW" Bits="24-20" />
|
|
<Bit Name="gpadc_scan_neg_3" Authority="RW" Bits="19-15" />
|
|
<Bit Name="gpadc_scan_neg_2" Authority="RW" Bits="14-10" />
|
|
<Bit Name="gpadc_scan_neg_1" Authority="RW" Bits="9-5" />
|
|
<Bit Name="gpadc_scan_neg_0" Authority="RW" Bits="4-0" />
|
|
</Register>
|
|
<Register Name="gpadc_reg_scn_neg2" Authority="RW" Address="0x4000F924" Width="32" Description="adc converation sequence 4">
|
|
<Bit Name="gpadc_scan_neg_11" Authority="RW" Bits="29-25" />
|
|
<Bit Name="gpadc_scan_neg_10" Authority="RW" Bits="24-20" />
|
|
<Bit Name="gpadc_scan_neg_9" Authority="RW" Bits="19-15" />
|
|
<Bit Name="gpadc_scan_neg_8" Authority="RW" Bits="14-10" />
|
|
<Bit Name="gpadc_scan_neg_7" Authority="RW" Bits="9-5" />
|
|
<Bit Name="gpadc_scan_neg_6" Authority="RW" Bits="4-0" />
|
|
</Register>
|
|
<Register Name="gpadc_reg_status" Authority="RW" Address="0x4000F928" Width="32" Description="gpadc_reg_status.">
|
|
<Bit Name="gpadc_reserved" Authority="RW" Bits="31-16" />
|
|
<Bit Name="gpadc_data_rdy" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="gpadc_reg_isr" Authority="RW" Address="0x4000F92C" Width="32" Description="gpadc_reg_isr.">
|
|
<Bit Name="gpadc_pos_satur_mask" Authority="RW" Bits="9" />
|
|
<Bit Name="gpadc_neg_satur_mask" Authority="RW" Bits="8" />
|
|
<Bit Name="gpadc_pos_satur_clr" Authority="RW" Bits="5" />
|
|
<Bit Name="gpadc_neg_satur_clr" Authority="RW" Bits="4" />
|
|
<Bit Name="gpadc_pos_satur" Authority="RW" Bits="1" />
|
|
<Bit Name="gpadc_neg_satur" Authority="RW" Bits="0" />
|
|
</Register>
|
|
<Register Name="gpadc_reg_result" Authority="RW" Address="0x4000F930" Width="32" Description="gpadc_reg_result.">
|
|
<Bit Name="gpadc_data_out" Authority="RW" Bits="25-0" />
|
|
</Register>
|
|
<Register Name="gpadc_reg_raw_result" Authority="RW" Address="0x4000F934" Width="32" Description="gpadc_reg_raw_result.">
|
|
<Bit Name="gpadc_raw_data" Authority="RW" Bits="11-0" />
|
|
</Register>
|
|
<Register Name="gpadc_reg_define" Authority="RW" Address="0x4000F938" Width="32" Description="gpadc_reg_define.">
|
|
<Bit Name="gpadc_os_cal_data" Authority="RW" Bits="15-0" />
|
|
</Register>
|
|
<Register Name="hbncore_resv0" Authority="RW" Address="0x4000F93C" Width="32" Description="hbncore_resv0.">
|
|
<Bit Name="hbncore_resv0_data" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
<Register Name="hbncore_resv1" Authority="RW" Address="0x4000F940" Width="32" Description="hbncore_resv1.">
|
|
<Bit Name="hbncore_resv1_data" Authority="RW" Bits="31-0" />
|
|
</Register>
|
|
</Peripheral>
|
|
</config>
|
|
</com.csky.cds.peripheral> |