308 lines
18 KiB
C
308 lines
18 KiB
C
/**
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******************************************************************************
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* @file gpip_reg.h
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* @version V1.2
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* @date 2020-04-30
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __GPIP_REG_H__
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#define __GPIP_REG_H__
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#include "bl602.h"
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/* 0x0 : gpadc_config */
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#define GPIP_GPADC_CONFIG_OFFSET (0x0)
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#define GPIP_GPADC_DMA_EN GPIP_GPADC_DMA_EN
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#define GPIP_GPADC_DMA_EN_POS (0U)
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#define GPIP_GPADC_DMA_EN_LEN (1U)
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#define GPIP_GPADC_DMA_EN_MSK (((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS)
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#define GPIP_GPADC_DMA_EN_UMSK (~(((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS))
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#define GPIP_GPADC_FIFO_CLR GPIP_GPADC_FIFO_CLR
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#define GPIP_GPADC_FIFO_CLR_POS (1U)
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#define GPIP_GPADC_FIFO_CLR_LEN (1U)
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#define GPIP_GPADC_FIFO_CLR_MSK (((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS)
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#define GPIP_GPADC_FIFO_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS))
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#define GPIP_GPADC_FIFO_NE GPIP_GPADC_FIFO_NE
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#define GPIP_GPADC_FIFO_NE_POS (2U)
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#define GPIP_GPADC_FIFO_NE_LEN (1U)
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#define GPIP_GPADC_FIFO_NE_MSK (((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS)
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#define GPIP_GPADC_FIFO_NE_UMSK (~(((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS))
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#define GPIP_GPADC_FIFO_FULL GPIP_GPADC_FIFO_FULL
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#define GPIP_GPADC_FIFO_FULL_POS (3U)
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#define GPIP_GPADC_FIFO_FULL_LEN (1U)
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#define GPIP_GPADC_FIFO_FULL_MSK (((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS)
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#define GPIP_GPADC_FIFO_FULL_UMSK (~(((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS))
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#define GPIP_GPADC_RDY GPIP_GPADC_RDY
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#define GPIP_GPADC_RDY_POS (4U)
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#define GPIP_GPADC_RDY_LEN (1U)
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#define GPIP_GPADC_RDY_MSK (((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS)
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#define GPIP_GPADC_RDY_UMSK (~(((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS))
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#define GPIP_GPADC_FIFO_OVERRUN GPIP_GPADC_FIFO_OVERRUN
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#define GPIP_GPADC_FIFO_OVERRUN_POS (5U)
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#define GPIP_GPADC_FIFO_OVERRUN_LEN (1U)
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#define GPIP_GPADC_FIFO_OVERRUN_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS)
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#define GPIP_GPADC_FIFO_OVERRUN_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS))
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#define GPIP_GPADC_FIFO_UNDERRUN GPIP_GPADC_FIFO_UNDERRUN
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#define GPIP_GPADC_FIFO_UNDERRUN_POS (6U)
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#define GPIP_GPADC_FIFO_UNDERRUN_LEN (1U)
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#define GPIP_GPADC_FIFO_UNDERRUN_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS)
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#define GPIP_GPADC_FIFO_UNDERRUN_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS))
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#define GPIP_GPADC_RDY_CLR GPIP_GPADC_RDY_CLR
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#define GPIP_GPADC_RDY_CLR_POS (8U)
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#define GPIP_GPADC_RDY_CLR_LEN (1U)
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#define GPIP_GPADC_RDY_CLR_MSK (((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS)
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#define GPIP_GPADC_RDY_CLR_UMSK (~(((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS))
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#define GPIP_GPADC_FIFO_OVERRUN_CLR GPIP_GPADC_FIFO_OVERRUN_CLR
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#define GPIP_GPADC_FIFO_OVERRUN_CLR_POS (9U)
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#define GPIP_GPADC_FIFO_OVERRUN_CLR_LEN (1U)
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#define GPIP_GPADC_FIFO_OVERRUN_CLR_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS)
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#define GPIP_GPADC_FIFO_OVERRUN_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS))
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#define GPIP_GPADC_FIFO_UNDERRUN_CLR GPIP_GPADC_FIFO_UNDERRUN_CLR
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#define GPIP_GPADC_FIFO_UNDERRUN_CLR_POS (10U)
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#define GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN (1U)
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#define GPIP_GPADC_FIFO_UNDERRUN_CLR_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS)
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#define GPIP_GPADC_FIFO_UNDERRUN_CLR_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS))
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#define GPIP_GPADC_RDY_MASK GPIP_GPADC_RDY_MASK
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#define GPIP_GPADC_RDY_MASK_POS (12U)
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#define GPIP_GPADC_RDY_MASK_LEN (1U)
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#define GPIP_GPADC_RDY_MASK_MSK (((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS)
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#define GPIP_GPADC_RDY_MASK_UMSK (~(((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS))
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#define GPIP_GPADC_FIFO_OVERRUN_MASK GPIP_GPADC_FIFO_OVERRUN_MASK
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#define GPIP_GPADC_FIFO_OVERRUN_MASK_POS (13U)
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#define GPIP_GPADC_FIFO_OVERRUN_MASK_LEN (1U)
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#define GPIP_GPADC_FIFO_OVERRUN_MASK_MSK (((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS)
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#define GPIP_GPADC_FIFO_OVERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS))
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#define GPIP_GPADC_FIFO_UNDERRUN_MASK GPIP_GPADC_FIFO_UNDERRUN_MASK
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#define GPIP_GPADC_FIFO_UNDERRUN_MASK_POS (14U)
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#define GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN (1U)
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#define GPIP_GPADC_FIFO_UNDERRUN_MASK_MSK (((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS)
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#define GPIP_GPADC_FIFO_UNDERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS))
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#define GPIP_GPADC_FIFO_DATA_COUNT GPIP_GPADC_FIFO_DATA_COUNT
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#define GPIP_GPADC_FIFO_DATA_COUNT_POS (16U)
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#define GPIP_GPADC_FIFO_DATA_COUNT_LEN (6U)
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#define GPIP_GPADC_FIFO_DATA_COUNT_MSK (((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS)
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#define GPIP_GPADC_FIFO_DATA_COUNT_UMSK (~(((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS))
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#define GPIP_GPADC_FIFO_THL GPIP_GPADC_FIFO_THL
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#define GPIP_GPADC_FIFO_THL_POS (22U)
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#define GPIP_GPADC_FIFO_THL_LEN (2U)
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#define GPIP_GPADC_FIFO_THL_MSK (((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS)
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#define GPIP_GPADC_FIFO_THL_UMSK (~(((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS))
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/* 0x4 : gpadc_dma_rdata */
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#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4)
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#define GPIP_GPADC_DMA_RDATA GPIP_GPADC_DMA_RDATA
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#define GPIP_GPADC_DMA_RDATA_POS (0U)
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#define GPIP_GPADC_DMA_RDATA_LEN (26U)
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#define GPIP_GPADC_DMA_RDATA_MSK (((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS)
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#define GPIP_GPADC_DMA_RDATA_UMSK (~(((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS))
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/* 0x40 : gpdac_config */
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#define GPIP_GPDAC_CONFIG_OFFSET (0x40)
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#define GPIP_GPDAC_EN GPIP_GPDAC_EN
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#define GPIP_GPDAC_EN_POS (0U)
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#define GPIP_GPDAC_EN_LEN (1U)
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#define GPIP_GPDAC_EN_MSK (((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS)
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#define GPIP_GPDAC_EN_UMSK (~(((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS))
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#define GPIP_GPDAC_EN2 GPIP_GPDAC_EN2
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#define GPIP_GPDAC_EN2_POS (1U)
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#define GPIP_GPDAC_EN2_LEN (1U)
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#define GPIP_GPDAC_EN2_MSK (((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS)
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#define GPIP_GPDAC_EN2_UMSK (~(((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS))
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#define GPIP_DSM_MODE GPIP_DSM_MODE
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#define GPIP_DSM_MODE_POS (4U)
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#define GPIP_DSM_MODE_LEN (2U)
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#define GPIP_DSM_MODE_MSK (((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS)
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#define GPIP_DSM_MODE_UMSK (~(((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS))
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#define GPIP_GPDAC_MODE GPIP_GPDAC_MODE
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#define GPIP_GPDAC_MODE_POS (8U)
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#define GPIP_GPDAC_MODE_LEN (3U)
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#define GPIP_GPDAC_MODE_MSK (((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS)
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#define GPIP_GPDAC_MODE_UMSK (~(((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS))
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#define GPIP_GPDAC_CH_A_SEL GPIP_GPDAC_CH_A_SEL
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#define GPIP_GPDAC_CH_A_SEL_POS (16U)
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#define GPIP_GPDAC_CH_A_SEL_LEN (4U)
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#define GPIP_GPDAC_CH_A_SEL_MSK (((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS)
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#define GPIP_GPDAC_CH_A_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS))
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#define GPIP_GPDAC_CH_B_SEL GPIP_GPDAC_CH_B_SEL
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#define GPIP_GPDAC_CH_B_SEL_POS (20U)
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#define GPIP_GPDAC_CH_B_SEL_LEN (4U)
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#define GPIP_GPDAC_CH_B_SEL_MSK (((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS)
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#define GPIP_GPDAC_CH_B_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS))
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/* 0x44 : gpdac_dma_config */
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#define GPIP_GPDAC_DMA_CONFIG_OFFSET (0x44)
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#define GPIP_GPDAC_DMA_TX_EN GPIP_GPDAC_DMA_TX_EN
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#define GPIP_GPDAC_DMA_TX_EN_POS (0U)
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#define GPIP_GPDAC_DMA_TX_EN_LEN (1U)
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#define GPIP_GPDAC_DMA_TX_EN_MSK (((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS)
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#define GPIP_GPDAC_DMA_TX_EN_UMSK (~(((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS))
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#define GPIP_GPDAC_DMA_FORMAT GPIP_GPDAC_DMA_FORMAT
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#define GPIP_GPDAC_DMA_FORMAT_POS (4U)
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#define GPIP_GPDAC_DMA_FORMAT_LEN (2U)
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#define GPIP_GPDAC_DMA_FORMAT_MSK (((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS)
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#define GPIP_GPDAC_DMA_FORMAT_UMSK (~(((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS))
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/* 0x48 : gpdac_dma_wdata */
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#define GPIP_GPDAC_DMA_WDATA_OFFSET (0x48)
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#define GPIP_GPDAC_DMA_WDATA GPIP_GPDAC_DMA_WDATA
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#define GPIP_GPDAC_DMA_WDATA_POS (0U)
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#define GPIP_GPDAC_DMA_WDATA_LEN (32U)
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#define GPIP_GPDAC_DMA_WDATA_MSK (((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS)
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#define GPIP_GPDAC_DMA_WDATA_UMSK (~(((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS))
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/* 0x4C : gpdac_tx_fifo_status */
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#define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C)
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#define GPIP_TX_FIFO_EMPTY GPIP_TX_FIFO_EMPTY
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#define GPIP_TX_FIFO_EMPTY_POS (0U)
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#define GPIP_TX_FIFO_EMPTY_LEN (1U)
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#define GPIP_TX_FIFO_EMPTY_MSK (((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS)
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#define GPIP_TX_FIFO_EMPTY_UMSK (~(((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS))
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#define GPIP_TX_FIFO_FULL GPIP_TX_FIFO_FULL
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#define GPIP_TX_FIFO_FULL_POS (1U)
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#define GPIP_TX_FIFO_FULL_LEN (1U)
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#define GPIP_TX_FIFO_FULL_MSK (((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS)
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#define GPIP_TX_FIFO_FULL_UMSK (~(((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS))
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#define GPIP_TX_CS GPIP_TX_CS
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#define GPIP_TX_CS_POS (2U)
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#define GPIP_TX_CS_LEN (2U)
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#define GPIP_TX_CS_MSK (((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS)
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#define GPIP_TX_CS_UMSK (~(((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS))
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#define GPIP_TXFIFORDPTR GPIP_TXFIFORDPTR
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#define GPIP_TXFIFORDPTR_POS (4U)
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#define GPIP_TXFIFORDPTR_LEN (3U)
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#define GPIP_TXFIFORDPTR_MSK (((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS)
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#define GPIP_TXFIFORDPTR_UMSK (~(((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS))
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#define GPIP_TXFIFOWRPTR GPIP_TXFIFOWRPTR
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#define GPIP_TXFIFOWRPTR_POS (8U)
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#define GPIP_TXFIFOWRPTR_LEN (2U)
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#define GPIP_TXFIFOWRPTR_MSK (((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS)
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#define GPIP_TXFIFOWRPTR_UMSK (~(((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS))
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struct gpip_reg {
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/* 0x0 : gpadc_config */
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union {
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struct
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{
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uint32_t gpadc_dma_en : 1; /* [ 0], r/w, 0x0 */
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uint32_t gpadc_fifo_clr : 1; /* [ 1], w1c, 0x0 */
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uint32_t gpadc_fifo_ne : 1; /* [ 2], r, 0x0 */
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uint32_t gpadc_fifo_full : 1; /* [ 3], r, 0x0 */
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uint32_t gpadc_rdy : 1; /* [ 4], r, 0x0 */
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uint32_t gpadc_fifo_overrun : 1; /* [ 5], r, 0x0 */
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uint32_t gpadc_fifo_underrun : 1; /* [ 6], r, 0x0 */
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uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
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uint32_t gpadc_rdy_clr : 1; /* [ 8], r/w, 0x0 */
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uint32_t gpadc_fifo_overrun_clr : 1; /* [ 9], r/w, 0x0 */
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uint32_t gpadc_fifo_underrun_clr : 1; /* [ 10], r/w, 0x0 */
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uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */
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uint32_t gpadc_rdy_mask : 1; /* [ 12], r/w, 0x0 */
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uint32_t gpadc_fifo_overrun_mask : 1; /* [ 13], r/w, 0x0 */
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uint32_t gpadc_fifo_underrun_mask : 1; /* [ 14], r/w, 0x0 */
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uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */
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uint32_t gpadc_fifo_data_count : 6; /* [21:16], r, 0x0 */
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uint32_t gpadc_fifo_thl : 2; /* [23:22], r/w, 0x0 */
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uint32_t rsvd_31_24 : 8; /* [31:24], rsvd, 0x0 */
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} BF;
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uint32_t WORD;
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} gpadc_config;
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/* 0x4 : gpadc_dma_rdata */
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union {
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struct
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{
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uint32_t gpadc_dma_rdata : 26; /* [25: 0], r, 0x0 */
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uint32_t rsvd_31_26 : 6; /* [31:26], rsvd, 0x0 */
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} BF;
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uint32_t WORD;
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} gpadc_dma_rdata;
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/* 0x8 reserved */
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uint8_t RESERVED0x8[56];
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/* 0x40 : gpdac_config */
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union {
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struct
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{
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uint32_t gpdac_en : 1; /* [ 0], r/w, 0x0 */
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uint32_t gpdac_en2 : 1; /* [ 1], r/w, 0x0 */
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uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */
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uint32_t dsm_mode : 2; /* [ 5: 4], r/w, 0x0 */
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uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
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uint32_t gpdac_mode : 3; /* [10: 8], r/w, 0x0 */
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uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */
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uint32_t gpdac_ch_a_sel : 4; /* [19:16], r/w, 0x0 */
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uint32_t gpdac_ch_b_sel : 4; /* [23:20], r/w, 0x0 */
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uint32_t rsvd_31_24 : 8; /* [31:24], rsvd, 0xd */
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} BF;
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uint32_t WORD;
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} gpdac_config;
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/* 0x44 : gpdac_dma_config */
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union {
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|
struct
|
|
{
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uint32_t gpdac_dma_tx_en : 1; /* [ 0], r/w, 0x0 */
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uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
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uint32_t gpdac_dma_format : 2; /* [ 5: 4], r/w, 0x0 */
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uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */
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} BF;
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uint32_t WORD;
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} gpdac_dma_config;
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|
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/* 0x48 : gpdac_dma_wdata */
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union {
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|
struct
|
|
{
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uint32_t gpdac_dma_wdata : 32; /* [31: 0], w, x */
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} BF;
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|
uint32_t WORD;
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} gpdac_dma_wdata;
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|
|
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/* 0x4C : gpdac_tx_fifo_status */
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union {
|
|
struct
|
|
{
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uint32_t tx_fifo_empty : 1; /* [ 0], r, 0x0 */
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uint32_t tx_fifo_full : 1; /* [ 1], r, 0x0 */
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uint32_t tx_cs : 2; /* [ 3: 2], r, 0x0 */
|
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uint32_t TxFifoRdPtr : 3; /* [ 6: 4], r, 0x4 */
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uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
|
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uint32_t TxFifoWrPtr : 2; /* [ 9: 8], r, 0x0 */
|
|
uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} gpdac_tx_fifo_status;
|
|
};
|
|
|
|
typedef volatile struct gpip_reg gpip_reg_t;
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|
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#endif /* __GPIP_REG_H__ */
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