79 lines
2.4 KiB
C
79 lines
2.4 KiB
C
/**
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* @file system_bl702.c
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* @brief
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*
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* Copyright (c) 2021 Bouffalolab team
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*/
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#include "bl602_glb.h"
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#include <arch/risc-v/e24/clic.h>
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void SystemInit(void)
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{
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uint32_t *p;
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uint8_t i;
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uint32_t tmpVal = 0;
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/* global IRQ disable */
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__disable_irq();
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tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
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tmpVal |= (1 << 8); /*mask pds wakeup*/
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tmpVal |= (1 << 10); /*mask rf done*/
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tmpVal |= (1 << 11); /*mask pll done*/
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tmpVal &= ~(0xff << 16); /*mask all pds wakeup source int*/
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BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
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/* GLB_Set_EM_Sel(GLB_EM_0KB); */
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tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x00); //GLB_EM_0KB
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BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);
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/* Restore default setting*/
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/* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
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tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, 0x00); //UART_SIG_SWAP_NONE
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BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
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/* CLear all interrupt */
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p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIE_OFFSET);
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for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
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p[i] = 0;
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}
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p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIP_OFFSET);
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for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
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p[i] = 0;
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}
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BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, 0xffffffff);
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/* init bor for all platform */
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// HBN_BOR_CFG_Type borCfg = { 0 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 0 /* bor_sel */ };
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// HBN_Set_BOR_Cfg(&borCfg);
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}
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void System_Post_Init(void)
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{
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PDS_Trim_RC32M();
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HBN_Trim_RC32K();
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/* global IRQ enable */
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__enable_irq();
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} |