340 lines
18 KiB
C
340 lines
18 KiB
C
#ifndef __BL702_H__
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#define __BL702_H__
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/* This file had been modified, add USB_IRQn=43 for temp test, the irq value 43 should be checked after all. */
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/** @addtogroup Configuration_section_for_RISCV
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* @{
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*/
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/**
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* @brief Configuration of the Processor and Core Peripherals
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*/
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/* fix 57.6M */
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#define SystemCoreClockSet(val) if(val==57*6000*1000){ \
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BL_WR_WORD(0x4000F108,57.6*1000*1000); \
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}else{ \
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BL_WR_WORD(0x4000F108,val); \
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}
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#define SystemCoreClockGet(val) BL_RD_WORD(0x4000F108)
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/**
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* @}
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*/
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/** @addtogroup Peripheral_interrupt_number_definition
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* @{
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*/
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#ifdef ARCH_ARM
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#define IRQ_NUM_BASE 0
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#endif
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#ifdef ARCH_RISCV
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#define IRQ_NUM_BASE 16
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#endif
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/**
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* @brief BL702 Interrupt Number Definition, according to the selected device
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* in @ref Library_configuration_section
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*/
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typedef enum
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{
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#ifdef ARCH_ARM
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/****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
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NonMaskableInt_IRQn = -14, /*!< 2 Cortex-M4 Non Maskable Interrupt */
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HardFault_IRQn = -13, /*!< 3 Cortex-M4 Hard Fault Interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
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#endif
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#ifdef ARCH_RISCV
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MSOFT_IRQn =3, /*!< 3 RISCV machine software Interrupt */
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MTIME_IRQn =7, /*!< 7 RISCV machine time Interrupt */
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MEXT_IRQn =11, /*!< 11 RISCV external Interrupt */
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CLIC_SOFT_PEND_IRQn =12, /*!< 12 RISCV CLIC software pending Interrupt */
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#endif
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/****** BL702 specific Interrupt Numbers **********************************************************************/
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BMX_ERR_IRQn = IRQ_NUM_BASE+0, /*!< BMX Error Interrupt */
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BMX_TO_IRQn = IRQ_NUM_BASE+1, /*!< BMX Timeout Interrupt */
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L1C_BMX_ERR_IRQn = IRQ_NUM_BASE+2, /*!< L1C BMX Error Interrupt */
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L1C_BMX_TO_IRQn = IRQ_NUM_BASE+3, /*!< L1C BMX Timeout Interrupt */
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SEC_BMX_ERR_IRQn = IRQ_NUM_BASE+4, /*!< SEC BMX Error Interrupt */
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RF_TOP_INT0_IRQn = IRQ_NUM_BASE+5, /*!< RF_TOP_INT0 Interrupt */
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RF_TOP_INT1_IRQn = IRQ_NUM_BASE+6, /*!< RF_TOP_INT1 Interrupt */
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RESERVED0 = IRQ_NUM_BASE+7, /*!< RESERVED Interrupt */
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DMA_BMX_ERR_IRQn = IRQ_NUM_BASE+8, /*!< DMA BMX Error Interrupt */
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SEC_GMAC_IRQn = IRQ_NUM_BASE+9, /*!< SEC_ENG_GMAC_INT Interrupt */
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SEC_CDET_IRQn = IRQ_NUM_BASE+10, /*!< SEC_ENG_CDET_INT Interrupt */
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SEC_PKA_IRQn = IRQ_NUM_BASE+11, /*!< SEC_ENG_PKA_INT Interrupt */
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SEC_TRNG_IRQn = IRQ_NUM_BASE+12, /*!< SEC_ENG_TRNG_INT Interrupt */
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SEC_AES_IRQn = IRQ_NUM_BASE+13, /*!< SEC_ENG_AES_INT Interrupt */
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SEC_SHA_IRQn = IRQ_NUM_BASE+14, /*!< SEC_ENG_SHA_INT Interrupt */
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DMA_ALL_IRQn = IRQ_NUM_BASE+15, /*!< DMA ALL Interrupt */
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MJPEG_IRQn = IRQ_NUM_BASE+16, /*!< MJPEG Interrupt */
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CAM_IRQn = IRQ_NUM_BASE+17, /*!< CAM Interrupt */
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I2S_IRQn = IRQ_NUM_BASE+18, /*!< I2S Interrupt */
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IRTX_IRQn = IRQ_NUM_BASE+19, /*!< IR TX Interrupt */
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IRRX_IRQn = IRQ_NUM_BASE+20, /*!< IR RX Interrupt */
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USB_IRQn = IRQ_NUM_BASE+21, /*!< USB Interrupt */
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EMAC_IRQn = IRQ_NUM_BASE+22, /*!< EMAC Interrupt */
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SF_CTRL_IRQn = IRQ_NUM_BASE+23, /*!< SF_CTRL Interrupt */
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RESERVED1 = IRQ_NUM_BASE+24, /*!< RESERVED Interrupt */
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GPADC_DMA_IRQn = IRQ_NUM_BASE+25, /*!< GPADC_DMA Interrupt */
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EFUSE_IRQn = IRQ_NUM_BASE+26, /*!< Efuse Interrupt */
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SPI_IRQn = IRQ_NUM_BASE+27, /*!< SPI Interrupt */
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RESERVED2 = IRQ_NUM_BASE+28, /*!< RESERVED Interrupt */
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UART0_IRQn = IRQ_NUM_BASE+29, /*!< UART Interrupt */
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UART1_IRQn = IRQ_NUM_BASE+30, /*!< UART1 Interrupt */
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RESERVED3 = IRQ_NUM_BASE+31, /*!< RESERVED Interrupt */
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I2C_IRQn = IRQ_NUM_BASE+32, /*!< I2C Interrupt */
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RESERVED4 = IRQ_NUM_BASE+33, /*!< RESERVED Interrupt */
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PWM_IRQn = IRQ_NUM_BASE+34, /*!< PWM Interrupt */
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RESERVED5 = IRQ_NUM_BASE+35, /*!< RESERVED Interrupt */
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TIMER_CH0_IRQn = IRQ_NUM_BASE+36, /*!< Timer Channel 0 Interrupt */
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TIMER_CH1_IRQn = IRQ_NUM_BASE+37, /*!< Timer Channel 1 Interrupt */
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TIMER_WDT_IRQn = IRQ_NUM_BASE+38, /*!< Timer Watch Dog Interrupt */
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KYS_IRQn = IRQ_NUM_BASE+39, /*!< KYS Interrupt */
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QDEC0_IRQn = IRQ_NUM_BASE+40, /*!< QDEC0 Interrupt */
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QDEC1_IRQn = IRQ_NUM_BASE+41, /*!< QDEC1 Interrupt */
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QDEC2_IRQn = IRQ_NUM_BASE+42, /*!< QDEC2 Interrupt */
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RESERVED6 = IRQ_NUM_BASE+43, /*!< RESERVED Interrupt */
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GPIO_INT0_IRQn = IRQ_NUM_BASE+44, /*!< GPIO_INT0 Interrupt */
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TOUCH_IRQn = IRQ_NUM_BASE+45, /*!< TOUCH Interrupt */
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RESERVED7 = IRQ_NUM_BASE+46, /*!< RESERVED Interrupt */
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M154_REQ_ENH_ACK_IRQn = IRQ_NUM_BASE+47, /*!< M154_REQ Interrupt */
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M154_IRQn = IRQ_NUM_BASE+48, /*!< M154 Interrupt */
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M154_AES_IRQn = IRQ_NUM_BASE+49, /*!< M154_AES Interrupt */
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PDS_WAKEUP_IRQn = IRQ_NUM_BASE+50, /*!< PDS Wakeup Interrupt */
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HBN_OUT0_IRQn = IRQ_NUM_BASE+51, /*!< Hibernate out 0 Interrupt */
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HBN_OUT1_IRQn = IRQ_NUM_BASE+52, /*!< Hibernate out 1 Interrupt */
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BOR_IRQn = IRQ_NUM_BASE+53, /*!< BOR Interrupt */
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WIFI_IRQn = IRQ_NUM_BASE+54, /*!< WIFI To CPU Interrupt */
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BZ_PHY_IRQn = IRQ_NUM_BASE+55, /*!< BZ_PHY Interrupt */
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BLE_IRQn = IRQ_NUM_BASE+56, /*!< BLE Interrupt */
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MAC_TXRX_TIMER_IRQn = IRQ_NUM_BASE+57, /*!< mac_int_tx_rx_timer Interrupt */
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MAC_TXRX_MISC_IRQn = IRQ_NUM_BASE+58, /*!< mac_int_tx_rx_misc Interrupt */
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MAC_RX_TRG_IRQn = IRQ_NUM_BASE+59, /*!< mac_int_rx_trigger Interrupt */
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MAC_TX_TRG_IRQn = IRQ_NUM_BASE+60, /*!< mac_int_tx_trigger Interrupt */
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MAC_GEN_IRQn = IRQ_NUM_BASE+61, /*!< mac_int_gen Interrupt */
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MAC_PORT_TRG_IRQn = IRQ_NUM_BASE+62, /*!< mac_int_port_trigger Interrupt */
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WIFI_IPC_PUBLIC_IRQn = IRQ_NUM_BASE+63, /*!< wifi IPC public Interrupt */
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IRQn_LAST,
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} IRQn_Type;
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/**
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* @brief BL702 Memory Map Definitions
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*/
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#define BL702_FLASH_XIP_BASE 0x23000000
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#define BL702_FLASH_XIP_END (0x23000000+16*1024*1024)
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#define BL702_FLASH_XIP_REMAP0_BASE 0x33000000
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#define BL702_FLASH_XIP_REMAP0_END (0x33000000+16*1024*1024)
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#define BL702_FLASH_XIP_REMAP1_BASE 0x43000000
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#define BL702_FLASH_XIP_REMAP1_END (0x43000000+16*1024*1024)
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#define BL702_FLASH_XIP_REMAP2_BASE 0x53000000
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#define BL702_FLASH_XIP_REMAP2_END (0x53000000+16*1024*1024)
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#define BL702_PSRAM_XIP_BASE 0x24000000
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#define BL702_PSRAM_XIP_END (0x24000000+16*1024*1024)
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#define BL702_PSRAM_XIP_REMAP0_BASE 0x34000000
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#define BL702_PSRAM_XIP_REMAP0_END (0x34000000+16*1024*1024)
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#define BL702_PSRAM_XIP_REMAP1_BASE 0x44000000
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#define BL702_PSRAM_XIP_REMAP1_END (0x44000000+16*1024*1024)
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#define BL702_PSRAM_XIP_REMAP2_BASE 0x54000000
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#define BL702_PSRAM_XIP_REMAP2_END (0x54000000+16*1024*1024)
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#define BL702_WRAM_BASE 0x42020000
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#define BL702_WRAM_END (0x42020000+56*1024)
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#define BL702_WRAM_REMAP0_BASE 0x22020000
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#define BL702_WRAM_REMAP0_END (0x22020000+56*1024)
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#define BL702_WRAM_REMAP1_BASE 0x32020000
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#define BL702_WRAM_REMAP1_END (0x32020000+56*1024)
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#define BL702_WRAM_REMAP2_BASE 0x52020000
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#define BL702_WRAM_REMAP2_END (0x52020000+56*1024)
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#define BL702_TCM_BASE 0x22010000
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#define BL702_TCM_END (0x22010000+(16+48)*1024)
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#define BL702_TCM_REMAP0_BASE 0x32010000
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#define BL702_TCM_REMAP0_END (0x32010000+(16+48)*1024)
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#define BL702_TCM_REMAP1_BASE 0x42010000
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#define BL702_TCM_REMAP1_END (0x42010000+(16+48)*1024)
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#define BL702_TCM_REMAP2_BASE 0x52010000
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#define BL702_TCM_REMAP2_END (0x52010000+(16+48)*1024)
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/*@} end of group Memory_Map_Section */
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/* BL702 peripherals base address */
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#define GLB_BASE ((uint32_t)0x40000000)
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#define RF_BASE ((uint32_t)0x40001000)
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#define BZ_PHY_BASE ((uint32_t)0x40001000)
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#define BZ_PHY_AGC_BASE ((uint32_t)0x40001000)
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#define GPIP_BASE ((uint32_t)0x40002000) /*!< AUX module base address */
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#define SEC_DBG_BASE ((uint32_t)0x40003000) /*!< Security Debug module base address */
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#define SEC_ENG_BASE ((uint32_t)0x40004000) /*!< Security Engine module base address */
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#define TZC_SEC_BASE ((uint32_t)0x40005000) /*!< Trustzone control security base address */
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#define TZC_NSEC_BASE ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */
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#define EF_DATA_BASE ((uint32_t)0x40007000)
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#define EF_CTRL_BASE ((uint32_t)0x40007000)
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#define CCI_BASE ((uint32_t)0x40008000)
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#define L1C_BASE ((uint32_t)0x40009000) /*!< L1 cache config base address */
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#define UART0_BASE ((uint32_t)0x4000A000)
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#define UART1_BASE ((uint32_t)0x4000A100)
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#define SPI_BASE ((uint32_t)0x4000A200)
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#define I2C_BASE ((uint32_t)0x4000A300)
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#define PWM_BASE ((uint32_t)0x4000A400)
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#define TIMER_BASE ((uint32_t)0x4000A500)
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#define IR_BASE ((uint32_t)0x4000A600)
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#define CKS_BASE ((uint32_t)0x4000A700)
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#define QDEC0_BASE ((uint32_t)0x4000A800)
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#define QDEC1_BASE ((uint32_t)0x4000A840)
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#define QDEC2_BASE ((uint32_t)0x4000A880)
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#define KYS_BASE ((uint32_t)0x4000A900)
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#define I2S_BASE ((uint32_t)0x4000AA00)
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#define CAM_BASE ((uint32_t)0x4000AD00)
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#define MJPEG_BASE ((uint32_t)0x4000AE00)
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#define SF_CTRL_BASE ((uint32_t)0x4000B000)
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#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
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#define DMA_BASE ((uint32_t)0x4000C000)
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#define EMAC_BASE ((uint32_t)0x4000D000)
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#define USB_BASE ((uint32_t)0x4000D800)
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#define PDS_BASE ((uint32_t)0x4000E000) /*!< Power down sleep module base address */
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#define HBN_BASE ((uint32_t)0x4000F000) /*!< Hibernate module base address */
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#define AON_BASE ((uint32_t)0x4000F000) /*!< Always on module base address */
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#define MAC154_BASE ((uint32_t)0x4C000000) /*!< MAC154 module base address */
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#define HBN_RAM_BASE ((uint32_t)0x40010000)
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typedef enum
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{
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BL_AHB_SLAVE1_GLB = 0x00,
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BL_AHB_SLAVE1_MIX = 0x01,
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BL_AHB_SLAVE1_GPIP = 0x02,
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BL_AHB_SLAVE1_SEC_DBG = 0x03,
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BL_AHB_SLAVE1_SEC = 0x04,
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BL_AHB_SLAVE1_TZ1 = 0x05,
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BL_AHB_SLAVE1_TZ2 = 0x06,
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BL_AHB_SLAVE1_EFUSE = 0x07,
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BL_AHB_SLAVE1_CCI = 0x08,
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BL_AHB_SLAVE1_L1C = 0x09,
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BL_AHB_SLAVE1_S1A_ALL = 0x0A,
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BL_AHB_SLAVE1_SFC = 0x0B,
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BL_AHB_SLAVE1_DMA = 0x0C,
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BL_AHB_SLAVE1_EMAC = 0x0D,
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BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0E,
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BL_AHB_SLAVE1_RSVD0F = 0x0F,
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BL_AHB_SLAVE1_UART0 = 0x10,
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BL_AHB_SLAVE1_UART1 = 0x11,
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BL_AHB_SLAVE1_SPI = 0x12,
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BL_AHB_SLAVE1_I2C = 0x13,
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BL_AHB_SLAVE1_PWM = 0x14,
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BL_AHB_SLAVE1_TMR = 0x15,
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BL_AHB_SLAVE1_IRR = 0x16,
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BL_AHB_SLAVE1_CKS = 0x17,
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BL_AHB_SLAVE1_QDEC = 0x18,
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BL_AHB_SLAVE1_KYS = 0x19,
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BL_AHB_SLAVE1_I2S = 0x1A,
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BL_AHB_SLAVE1_RSVD1B = 0x1B,
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BL_AHB_SLAVE1_USB = 0x1C,
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BL_AHB_SLAVE1_CAM = 0x1D,
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BL_AHB_SLAVE1_MJPEG = 0x1E,
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BL_AHB_SLAVE1_MAX = 0x1F,
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}BL_AHB_Slave1_Type;
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typedef enum
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{
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BL_AHB_SEC_ENG_AES0 = 0,
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BL_AHB_SEC_ENG_AES1,
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BL_AHB_SEC_ENG_SHA0,
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BL_AHB_SEC_ENG_SHA1,
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}BL_AHB_Sec_Eng_Type;
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typedef enum
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{
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BL_AHB_DMA0_CH0 = 0,
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BL_AHB_DMA0_CH1,
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BL_AHB_DMA0_CH2,
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BL_AHB_DMA0_CH3,
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BL_AHB_DMA0_CH4,
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BL_AHB_DMA0_CH5,
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BL_AHB_DMA0_CH6,
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BL_AHB_DMA0_CH7,
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}BL_AHB_DMA0_CHNL_Type;
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typedef enum
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{
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BL_AHB_SLAVE2_WIFI_CFG = 0,
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BL_AHB_SLAVE2_MAX,
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}BL_AHB_Slave2_Type;
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typedef enum
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{
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BL_AHB_SLAVE3_BLE = 0,
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BL_AHB_SLAVE3_MAX,
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}BL_AHB_Slave3_Type;
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typedef enum
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{
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BL_CORE_MASTER_IBUS_CPU = 0,
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BL_CORE_MASTER_DBUS_CPU,
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BL_CORE_MASTER_BUS_S2F,
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BL_CORE_MASTER_MAX,
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}BL_Core_Master_Type;
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typedef enum
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{
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BL_CORE_SLAVE0_DTCM_CPU = 0,
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BL_CORE_SLAVE0_MAX,
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}BL_Core_Slave0_Type;
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typedef enum
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{
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BL_CORE_SLAVE1_XIP_CPU = 0,
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BL_CORE_SLAVE1_ITCM_CPU,
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BL_CORE_SLAVE1_ROM,
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BL_CORE_SLAVE1_MAX,
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}BL_Core_Slave1_Type;
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typedef enum
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{
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BL_CORE_SLAVE2_F2S = 0,
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BL_CORE_SLAVE2_MAX,
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}BL_Core_Slave2_Type;
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/**
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* @}
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*/
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#include <stdint.h>
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#include <system_bl702.h>
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/* ARM CPU include files */
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#ifdef ARCH_ARM
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#ifdef CPU_AP_CM4
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#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
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#endif
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#ifdef CPU_NP_CM0
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#include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
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#endif
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#endif
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/* RISCV CPU include files */
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#ifdef ARCH_RISCV
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#ifdef __GNUC__
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#include "cmsis_compatible_gcc.h"
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#include "clic.h"
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#include "riscv_encoding.h"
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#endif
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#endif
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/**
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* @}
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*/
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#endif
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