85 lines
2.2 KiB
C
85 lines
2.2 KiB
C
#include "bflb_mtimer.h"
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#include "bflb_dma.h"
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extern void board_init(void);
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static ATTR_NOCACHE_RAM_SECTION uint8_t src_buffer[4100];
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static ATTR_NOCACHE_RAM_SECTION uint8_t src2_buffer[4100];
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static ATTR_NOCACHE_RAM_SECTION uint8_t src3_buffer[4100];
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static ATTR_NOCACHE_RAM_SECTION uint8_t dst_buffer[4100];
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static ATTR_NOCACHE_RAM_SECTION uint8_t dst2_buffer[4100];
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static ATTR_NOCACHE_RAM_SECTION uint8_t dst3_buffer[4100];
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static uint8_t dma_tc_flag0 = 0;
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struct bflb_device_s *dma0_ch0;
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void dma0_ch0_isr(void *arg)
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{
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dma_tc_flag0++;
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printf("tc done\r\n");
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}
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void sram_init()
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{
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memset(src_buffer, 'a', 4100);
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src_buffer[3999] = 'B';
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src_buffer[4095] = 'A';
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src_buffer[4096] = 'B';
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src_buffer[4097] = 'C';
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src_buffer[4098] = 'D';
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src_buffer[4099] = 'E';
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memset(src2_buffer, 'c', 512);
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memset(src3_buffer, 'd', 256);
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}
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int main(void)
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{
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board_init();
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sram_init();
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printf("dma memory test\r\n");
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dma0_ch0 = bflb_device_get_by_name("dma0_ch0");
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struct bflb_dma_channel_config_s config;
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config.direction = DMA_MEMORY_TO_MEMORY;
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config.src_req = 0;
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config.dst_req = 0;
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config.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
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config.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
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config.src_burst_count = DMA_BURST_INCR1;
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config.dst_burst_count = DMA_BURST_INCR1;
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config.src_width = DMA_DATA_WIDTH_32BIT;
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config.dst_width = DMA_DATA_WIDTH_32BIT;
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bflb_dma_channel_init(dma0_ch0, &config);
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bflb_dma_channel_irq_attach(dma0_ch0, dma0_ch0_isr, NULL);
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struct bflb_dma_channel_lli_pool_s lli[20]; /* max trasnfer size 4064 * 20 */
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struct bflb_dma_channel_lli_transfer_s transfers[3];
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transfers[0].src_addr = (uint32_t)src_buffer;
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transfers[0].dst_addr = (uint32_t)dst_buffer;
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transfers[0].nbytes = 4100;
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transfers[1].src_addr = (uint32_t)src2_buffer;
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transfers[1].dst_addr = (uint32_t)dst2_buffer;
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transfers[1].nbytes = 4100;
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transfers[2].src_addr = (uint32_t)src3_buffer;
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transfers[2].dst_addr = (uint32_t)dst3_buffer;
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transfers[2].nbytes = 4100;
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bflb_dma_channel_lli_reload(dma0_ch0, lli, 20, transfers, 3);
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bflb_dma_channel_start(dma0_ch0);
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while (dma_tc_flag0 != 3) {
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bflb_mtimer_delay_ms(1);
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}
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while (1) {
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}
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}
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