2736 lines
146 KiB
C
2736 lines
146 KiB
C
/**
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******************************************************************************
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* @file sf_ctrl_reg.h
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* @version V1.2
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* @date 2020-03-30
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __SF_CTRL_REG_H__
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#define __SF_CTRL_REG_H__
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#include "bl702.h"
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/* 0x0 : sf_ctrl_0 */
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#define SF_CTRL_0_OFFSET (0x0)
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#define SF_CTRL_SF_CLK_SF_RX_INV_SEL SF_CTRL_SF_CLK_SF_RX_INV_SEL
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#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS (2U)
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#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN (1U)
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#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_MSK (((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS)
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#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS))
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#define SF_CTRL_SF_CLK_OUT_GATE_EN SF_CTRL_SF_CLK_OUT_GATE_EN
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#define SF_CTRL_SF_CLK_OUT_GATE_EN_POS (3U)
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#define SF_CTRL_SF_CLK_OUT_GATE_EN_LEN (1U)
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#define SF_CTRL_SF_CLK_OUT_GATE_EN_MSK (((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS)
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#define SF_CTRL_SF_CLK_OUT_GATE_EN_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS))
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#define SF_CTRL_SF_CLK_OUT_INV_SEL SF_CTRL_SF_CLK_OUT_INV_SEL
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#define SF_CTRL_SF_CLK_OUT_INV_SEL_POS (4U)
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#define SF_CTRL_SF_CLK_OUT_INV_SEL_LEN (1U)
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#define SF_CTRL_SF_CLK_OUT_INV_SEL_MSK (((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS)
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#define SF_CTRL_SF_CLK_OUT_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS))
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#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL SF_CTRL_SF_CLK_SAHB_SRAM_SEL
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#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS (5U)
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#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN (1U)
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#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_MSK (((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS)
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#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS))
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#define SF_CTRL_SF_IF_READ_DLY_N SF_CTRL_SF_IF_READ_DLY_N
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#define SF_CTRL_SF_IF_READ_DLY_N_POS (8U)
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#define SF_CTRL_SF_IF_READ_DLY_N_LEN (3U)
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#define SF_CTRL_SF_IF_READ_DLY_N_MSK (((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS)
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#define SF_CTRL_SF_IF_READ_DLY_N_UMSK (~(((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS))
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#define SF_CTRL_SF_IF_READ_DLY_EN SF_CTRL_SF_IF_READ_DLY_EN
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#define SF_CTRL_SF_IF_READ_DLY_EN_POS (11U)
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#define SF_CTRL_SF_IF_READ_DLY_EN_LEN (1U)
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#define SF_CTRL_SF_IF_READ_DLY_EN_MSK (((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS)
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#define SF_CTRL_SF_IF_READ_DLY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS))
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#define SF_CTRL_SF_IF_INT SF_CTRL_SF_IF_INT
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#define SF_CTRL_SF_IF_INT_POS (16U)
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#define SF_CTRL_SF_IF_INT_LEN (1U)
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#define SF_CTRL_SF_IF_INT_MSK (((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS)
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#define SF_CTRL_SF_IF_INT_UMSK (~(((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS))
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#define SF_CTRL_SF_IF_INT_CLR SF_CTRL_SF_IF_INT_CLR
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#define SF_CTRL_SF_IF_INT_CLR_POS (17U)
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#define SF_CTRL_SF_IF_INT_CLR_LEN (1U)
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#define SF_CTRL_SF_IF_INT_CLR_MSK (((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS)
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#define SF_CTRL_SF_IF_INT_CLR_UMSK (~(((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS))
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#define SF_CTRL_SF_IF_INT_SET SF_CTRL_SF_IF_INT_SET
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#define SF_CTRL_SF_IF_INT_SET_POS (18U)
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#define SF_CTRL_SF_IF_INT_SET_LEN (1U)
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#define SF_CTRL_SF_IF_INT_SET_MSK (((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS)
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#define SF_CTRL_SF_IF_INT_SET_UMSK (~(((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS))
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#define SF_CTRL_SF_AES_DLY_MODE SF_CTRL_SF_AES_DLY_MODE
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#define SF_CTRL_SF_AES_DLY_MODE_POS (19U)
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#define SF_CTRL_SF_AES_DLY_MODE_LEN (1U)
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#define SF_CTRL_SF_AES_DLY_MODE_MSK (((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS)
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#define SF_CTRL_SF_AES_DLY_MODE_UMSK (~(((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS))
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#define SF_CTRL_SF_AES_DOUT_ENDIAN SF_CTRL_SF_AES_DOUT_ENDIAN
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#define SF_CTRL_SF_AES_DOUT_ENDIAN_POS (20U)
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#define SF_CTRL_SF_AES_DOUT_ENDIAN_LEN (1U)
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#define SF_CTRL_SF_AES_DOUT_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS)
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#define SF_CTRL_SF_AES_DOUT_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS))
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#define SF_CTRL_SF_AES_CTR_PLUS_EN SF_CTRL_SF_AES_CTR_PLUS_EN
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#define SF_CTRL_SF_AES_CTR_PLUS_EN_POS (21U)
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#define SF_CTRL_SF_AES_CTR_PLUS_EN_LEN (1U)
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#define SF_CTRL_SF_AES_CTR_PLUS_EN_MSK (((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS)
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#define SF_CTRL_SF_AES_CTR_PLUS_EN_UMSK (~(((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS))
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#define SF_CTRL_SF_AES_KEY_ENDIAN SF_CTRL_SF_AES_KEY_ENDIAN
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#define SF_CTRL_SF_AES_KEY_ENDIAN_POS (22U)
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#define SF_CTRL_SF_AES_KEY_ENDIAN_LEN (1U)
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#define SF_CTRL_SF_AES_KEY_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS)
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#define SF_CTRL_SF_AES_KEY_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS))
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#define SF_CTRL_SF_AES_IV_ENDIAN SF_CTRL_SF_AES_IV_ENDIAN
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#define SF_CTRL_SF_AES_IV_ENDIAN_POS (23U)
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#define SF_CTRL_SF_AES_IV_ENDIAN_LEN (1U)
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#define SF_CTRL_SF_AES_IV_ENDIAN_MSK (((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS)
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#define SF_CTRL_SF_AES_IV_ENDIAN_UMSK (~(((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS))
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#define SF_CTRL_SF_ID SF_CTRL_SF_ID
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#define SF_CTRL_SF_ID_POS (24U)
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#define SF_CTRL_SF_ID_LEN (8U)
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#define SF_CTRL_SF_ID_MSK (((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS)
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#define SF_CTRL_SF_ID_UMSK (~(((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS))
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/* 0x4 : sf_ctrl_1 */
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#define SF_CTRL_1_OFFSET (0x4)
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#define SF_CTRL_SF_IF_SR_PAT_MASK SF_CTRL_SF_IF_SR_PAT_MASK
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#define SF_CTRL_SF_IF_SR_PAT_MASK_POS (0U)
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#define SF_CTRL_SF_IF_SR_PAT_MASK_LEN (8U)
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#define SF_CTRL_SF_IF_SR_PAT_MASK_MSK (((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS)
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#define SF_CTRL_SF_IF_SR_PAT_MASK_UMSK (~(((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS))
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#define SF_CTRL_SF_IF_SR_PAT SF_CTRL_SF_IF_SR_PAT
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#define SF_CTRL_SF_IF_SR_PAT_POS (8U)
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#define SF_CTRL_SF_IF_SR_PAT_LEN (8U)
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#define SF_CTRL_SF_IF_SR_PAT_MSK (((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS)
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#define SF_CTRL_SF_IF_SR_PAT_UMSK (~(((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS))
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#define SF_CTRL_SF_IF_SR_INT SF_CTRL_SF_IF_SR_INT
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#define SF_CTRL_SF_IF_SR_INT_POS (16U)
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#define SF_CTRL_SF_IF_SR_INT_LEN (1U)
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#define SF_CTRL_SF_IF_SR_INT_MSK (((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS)
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#define SF_CTRL_SF_IF_SR_INT_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS))
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#define SF_CTRL_SF_IF_SR_INT_EN SF_CTRL_SF_IF_SR_INT_EN
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#define SF_CTRL_SF_IF_SR_INT_EN_POS (17U)
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#define SF_CTRL_SF_IF_SR_INT_EN_LEN (1U)
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#define SF_CTRL_SF_IF_SR_INT_EN_MSK (((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS)
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#define SF_CTRL_SF_IF_SR_INT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS))
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#define SF_CTRL_SF_IF_SR_INT_SET SF_CTRL_SF_IF_SR_INT_SET
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#define SF_CTRL_SF_IF_SR_INT_SET_POS (18U)
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#define SF_CTRL_SF_IF_SR_INT_SET_LEN (1U)
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#define SF_CTRL_SF_IF_SR_INT_SET_MSK (((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS)
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#define SF_CTRL_SF_IF_SR_INT_SET_UMSK (~(((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS))
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#define SF_CTRL_SF_IF_0_ACK_LAT SF_CTRL_SF_IF_0_ACK_LAT
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#define SF_CTRL_SF_IF_0_ACK_LAT_POS (20U)
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#define SF_CTRL_SF_IF_0_ACK_LAT_LEN (3U)
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#define SF_CTRL_SF_IF_0_ACK_LAT_MSK (((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS)
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#define SF_CTRL_SF_IF_0_ACK_LAT_UMSK (~(((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS))
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#define SF_CTRL_SF_IF_REG_HOLD SF_CTRL_SF_IF_REG_HOLD
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#define SF_CTRL_SF_IF_REG_HOLD_POS (24U)
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#define SF_CTRL_SF_IF_REG_HOLD_LEN (1U)
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#define SF_CTRL_SF_IF_REG_HOLD_MSK (((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS)
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#define SF_CTRL_SF_IF_REG_HOLD_UMSK (~(((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS))
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#define SF_CTRL_SF_IF_REG_WP SF_CTRL_SF_IF_REG_WP
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#define SF_CTRL_SF_IF_REG_WP_POS (25U)
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#define SF_CTRL_SF_IF_REG_WP_LEN (1U)
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#define SF_CTRL_SF_IF_REG_WP_MSK (((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS)
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#define SF_CTRL_SF_IF_REG_WP_UMSK (~(((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS))
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#define SF_CTRL_SF_AHB2SIF_STOPPED SF_CTRL_SF_AHB2SIF_STOPPED
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#define SF_CTRL_SF_AHB2SIF_STOPPED_POS (26U)
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#define SF_CTRL_SF_AHB2SIF_STOPPED_LEN (1U)
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#define SF_CTRL_SF_AHB2SIF_STOPPED_MSK (((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS)
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#define SF_CTRL_SF_AHB2SIF_STOPPED_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS))
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#define SF_CTRL_SF_AHB2SIF_STOP SF_CTRL_SF_AHB2SIF_STOP
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#define SF_CTRL_SF_AHB2SIF_STOP_POS (27U)
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#define SF_CTRL_SF_AHB2SIF_STOP_LEN (1U)
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#define SF_CTRL_SF_AHB2SIF_STOP_MSK (((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS)
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#define SF_CTRL_SF_AHB2SIF_STOP_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS))
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#define SF_CTRL_SF_IF_FN_SEL SF_CTRL_SF_IF_FN_SEL
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#define SF_CTRL_SF_IF_FN_SEL_POS (28U)
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#define SF_CTRL_SF_IF_FN_SEL_LEN (1U)
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#define SF_CTRL_SF_IF_FN_SEL_MSK (((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS)
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#define SF_CTRL_SF_IF_FN_SEL_UMSK (~(((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS))
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#define SF_CTRL_SF_IF_EN SF_CTRL_SF_IF_EN
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#define SF_CTRL_SF_IF_EN_POS (29U)
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#define SF_CTRL_SF_IF_EN_LEN (1U)
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#define SF_CTRL_SF_IF_EN_MSK (((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS)
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#define SF_CTRL_SF_IF_EN_UMSK (~(((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS))
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#define SF_CTRL_SF_AHB2SIF_EN SF_CTRL_SF_AHB2SIF_EN
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#define SF_CTRL_SF_AHB2SIF_EN_POS (30U)
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#define SF_CTRL_SF_AHB2SIF_EN_LEN (1U)
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#define SF_CTRL_SF_AHB2SIF_EN_MSK (((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS)
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#define SF_CTRL_SF_AHB2SIF_EN_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS))
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#define SF_CTRL_SF_AHB2SRAM_EN SF_CTRL_SF_AHB2SRAM_EN
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#define SF_CTRL_SF_AHB2SRAM_EN_POS (31U)
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#define SF_CTRL_SF_AHB2SRAM_EN_LEN (1U)
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#define SF_CTRL_SF_AHB2SRAM_EN_MSK (((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS)
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#define SF_CTRL_SF_AHB2SRAM_EN_UMSK (~(((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS))
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/* 0x8 : sf_if_sahb_0 */
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#define SF_CTRL_SF_IF_SAHB_0_OFFSET (0x8)
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#define SF_CTRL_SF_IF_BUSY SF_CTRL_SF_IF_BUSY
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#define SF_CTRL_SF_IF_BUSY_POS (0U)
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#define SF_CTRL_SF_IF_BUSY_LEN (1U)
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#define SF_CTRL_SF_IF_BUSY_MSK (((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS)
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#define SF_CTRL_SF_IF_BUSY_UMSK (~(((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS))
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#define SF_CTRL_SF_IF_0_TRIG SF_CTRL_SF_IF_0_TRIG
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#define SF_CTRL_SF_IF_0_TRIG_POS (1U)
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#define SF_CTRL_SF_IF_0_TRIG_LEN (1U)
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#define SF_CTRL_SF_IF_0_TRIG_MSK (((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS)
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#define SF_CTRL_SF_IF_0_TRIG_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS))
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#define SF_CTRL_SF_IF_0_DAT_BYTE SF_CTRL_SF_IF_0_DAT_BYTE
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#define SF_CTRL_SF_IF_0_DAT_BYTE_POS (2U)
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#define SF_CTRL_SF_IF_0_DAT_BYTE_LEN (10U)
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#define SF_CTRL_SF_IF_0_DAT_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS)
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#define SF_CTRL_SF_IF_0_DAT_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS))
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#define SF_CTRL_SF_IF_0_DMY_BYTE SF_CTRL_SF_IF_0_DMY_BYTE
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#define SF_CTRL_SF_IF_0_DMY_BYTE_POS (12U)
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#define SF_CTRL_SF_IF_0_DMY_BYTE_LEN (5U)
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#define SF_CTRL_SF_IF_0_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS)
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#define SF_CTRL_SF_IF_0_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS))
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#define SF_CTRL_SF_IF_0_ADR_BYTE SF_CTRL_SF_IF_0_ADR_BYTE
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#define SF_CTRL_SF_IF_0_ADR_BYTE_POS (17U)
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#define SF_CTRL_SF_IF_0_ADR_BYTE_LEN (3U)
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#define SF_CTRL_SF_IF_0_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS)
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#define SF_CTRL_SF_IF_0_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS))
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#define SF_CTRL_SF_IF_0_CMD_BYTE SF_CTRL_SF_IF_0_CMD_BYTE
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#define SF_CTRL_SF_IF_0_CMD_BYTE_POS (20U)
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#define SF_CTRL_SF_IF_0_CMD_BYTE_LEN (3U)
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#define SF_CTRL_SF_IF_0_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS)
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#define SF_CTRL_SF_IF_0_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS))
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#define SF_CTRL_SF_IF_0_DAT_RW SF_CTRL_SF_IF_0_DAT_RW
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#define SF_CTRL_SF_IF_0_DAT_RW_POS (23U)
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#define SF_CTRL_SF_IF_0_DAT_RW_LEN (1U)
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#define SF_CTRL_SF_IF_0_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS)
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#define SF_CTRL_SF_IF_0_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS))
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#define SF_CTRL_SF_IF_0_DAT_EN SF_CTRL_SF_IF_0_DAT_EN
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#define SF_CTRL_SF_IF_0_DAT_EN_POS (24U)
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#define SF_CTRL_SF_IF_0_DAT_EN_LEN (1U)
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#define SF_CTRL_SF_IF_0_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS)
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#define SF_CTRL_SF_IF_0_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS))
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#define SF_CTRL_SF_IF_0_DMY_EN SF_CTRL_SF_IF_0_DMY_EN
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#define SF_CTRL_SF_IF_0_DMY_EN_POS (25U)
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#define SF_CTRL_SF_IF_0_DMY_EN_LEN (1U)
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#define SF_CTRL_SF_IF_0_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS)
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#define SF_CTRL_SF_IF_0_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS))
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#define SF_CTRL_SF_IF_0_ADR_EN SF_CTRL_SF_IF_0_ADR_EN
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#define SF_CTRL_SF_IF_0_ADR_EN_POS (26U)
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#define SF_CTRL_SF_IF_0_ADR_EN_LEN (1U)
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#define SF_CTRL_SF_IF_0_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS)
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#define SF_CTRL_SF_IF_0_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS))
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#define SF_CTRL_SF_IF_0_CMD_EN SF_CTRL_SF_IF_0_CMD_EN
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#define SF_CTRL_SF_IF_0_CMD_EN_POS (27U)
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#define SF_CTRL_SF_IF_0_CMD_EN_LEN (1U)
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#define SF_CTRL_SF_IF_0_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS)
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#define SF_CTRL_SF_IF_0_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS))
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#define SF_CTRL_SF_IF_0_SPI_MODE SF_CTRL_SF_IF_0_SPI_MODE
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#define SF_CTRL_SF_IF_0_SPI_MODE_POS (28U)
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#define SF_CTRL_SF_IF_0_SPI_MODE_LEN (3U)
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#define SF_CTRL_SF_IF_0_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS)
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#define SF_CTRL_SF_IF_0_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS))
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#define SF_CTRL_SF_IF_0_QPI_MODE_EN SF_CTRL_SF_IF_0_QPI_MODE_EN
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#define SF_CTRL_SF_IF_0_QPI_MODE_EN_POS (31U)
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#define SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN (1U)
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#define SF_CTRL_SF_IF_0_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS)
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#define SF_CTRL_SF_IF_0_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS))
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/* 0xC : sf_if_sahb_1 */
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#define SF_CTRL_SF_IF_SAHB_1_OFFSET (0xC)
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#define SF_CTRL_SF_IF_0_CMD_BUF_0 SF_CTRL_SF_IF_0_CMD_BUF_0
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#define SF_CTRL_SF_IF_0_CMD_BUF_0_POS (0U)
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#define SF_CTRL_SF_IF_0_CMD_BUF_0_LEN (32U)
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#define SF_CTRL_SF_IF_0_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS)
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#define SF_CTRL_SF_IF_0_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS))
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/* 0x10 : sf_if_sahb_2 */
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#define SF_CTRL_SF_IF_SAHB_2_OFFSET (0x10)
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#define SF_CTRL_SF_IF_0_CMD_BUF_1 SF_CTRL_SF_IF_0_CMD_BUF_1
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#define SF_CTRL_SF_IF_0_CMD_BUF_1_POS (0U)
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#define SF_CTRL_SF_IF_0_CMD_BUF_1_LEN (32U)
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#define SF_CTRL_SF_IF_0_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS)
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#define SF_CTRL_SF_IF_0_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS))
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/* 0x14 : sf_if_iahb_0 */
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#define SF_CTRL_SF_IF_IAHB_0_OFFSET (0x14)
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#define SF_CTRL_SF_IF_1_DMY_BYTE SF_CTRL_SF_IF_1_DMY_BYTE
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#define SF_CTRL_SF_IF_1_DMY_BYTE_POS (12U)
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#define SF_CTRL_SF_IF_1_DMY_BYTE_LEN (5U)
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#define SF_CTRL_SF_IF_1_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS)
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#define SF_CTRL_SF_IF_1_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS))
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#define SF_CTRL_SF_IF_1_ADR_BYTE SF_CTRL_SF_IF_1_ADR_BYTE
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#define SF_CTRL_SF_IF_1_ADR_BYTE_POS (17U)
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#define SF_CTRL_SF_IF_1_ADR_BYTE_LEN (3U)
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#define SF_CTRL_SF_IF_1_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS)
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#define SF_CTRL_SF_IF_1_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS))
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#define SF_CTRL_SF_IF_1_CMD_BYTE SF_CTRL_SF_IF_1_CMD_BYTE
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#define SF_CTRL_SF_IF_1_CMD_BYTE_POS (20U)
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#define SF_CTRL_SF_IF_1_CMD_BYTE_LEN (3U)
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#define SF_CTRL_SF_IF_1_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS)
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#define SF_CTRL_SF_IF_1_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS))
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#define SF_CTRL_SF_IF_1_DAT_RW SF_CTRL_SF_IF_1_DAT_RW
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#define SF_CTRL_SF_IF_1_DAT_RW_POS (23U)
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#define SF_CTRL_SF_IF_1_DAT_RW_LEN (1U)
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#define SF_CTRL_SF_IF_1_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS)
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#define SF_CTRL_SF_IF_1_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS))
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#define SF_CTRL_SF_IF_1_DAT_EN SF_CTRL_SF_IF_1_DAT_EN
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#define SF_CTRL_SF_IF_1_DAT_EN_POS (24U)
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#define SF_CTRL_SF_IF_1_DAT_EN_LEN (1U)
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#define SF_CTRL_SF_IF_1_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS)
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#define SF_CTRL_SF_IF_1_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS))
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#define SF_CTRL_SF_IF_1_DMY_EN SF_CTRL_SF_IF_1_DMY_EN
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#define SF_CTRL_SF_IF_1_DMY_EN_POS (25U)
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#define SF_CTRL_SF_IF_1_DMY_EN_LEN (1U)
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#define SF_CTRL_SF_IF_1_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS)
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#define SF_CTRL_SF_IF_1_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS))
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#define SF_CTRL_SF_IF_1_ADR_EN SF_CTRL_SF_IF_1_ADR_EN
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#define SF_CTRL_SF_IF_1_ADR_EN_POS (26U)
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#define SF_CTRL_SF_IF_1_ADR_EN_LEN (1U)
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#define SF_CTRL_SF_IF_1_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS)
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#define SF_CTRL_SF_IF_1_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS))
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#define SF_CTRL_SF_IF_1_CMD_EN SF_CTRL_SF_IF_1_CMD_EN
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#define SF_CTRL_SF_IF_1_CMD_EN_POS (27U)
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#define SF_CTRL_SF_IF_1_CMD_EN_LEN (1U)
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#define SF_CTRL_SF_IF_1_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS)
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#define SF_CTRL_SF_IF_1_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS))
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#define SF_CTRL_SF_IF_1_SPI_MODE SF_CTRL_SF_IF_1_SPI_MODE
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#define SF_CTRL_SF_IF_1_SPI_MODE_POS (28U)
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#define SF_CTRL_SF_IF_1_SPI_MODE_LEN (3U)
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#define SF_CTRL_SF_IF_1_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS)
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#define SF_CTRL_SF_IF_1_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS))
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#define SF_CTRL_SF_IF_1_QPI_MODE_EN SF_CTRL_SF_IF_1_QPI_MODE_EN
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#define SF_CTRL_SF_IF_1_QPI_MODE_EN_POS (31U)
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#define SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN (1U)
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#define SF_CTRL_SF_IF_1_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS)
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#define SF_CTRL_SF_IF_1_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS))
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/* 0x18 : sf_if_iahb_1 */
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#define SF_CTRL_SF_IF_IAHB_1_OFFSET (0x18)
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#define SF_CTRL_SF_IF_1_CMD_BUF_0 SF_CTRL_SF_IF_1_CMD_BUF_0
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#define SF_CTRL_SF_IF_1_CMD_BUF_0_POS (0U)
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#define SF_CTRL_SF_IF_1_CMD_BUF_0_LEN (32U)
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#define SF_CTRL_SF_IF_1_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS)
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#define SF_CTRL_SF_IF_1_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS))
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/* 0x1C : sf_if_iahb_2 */
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#define SF_CTRL_SF_IF_IAHB_2_OFFSET (0x1C)
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#define SF_CTRL_SF_IF_1_CMD_BUF_1 SF_CTRL_SF_IF_1_CMD_BUF_1
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#define SF_CTRL_SF_IF_1_CMD_BUF_1_POS (0U)
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#define SF_CTRL_SF_IF_1_CMD_BUF_1_LEN (32U)
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#define SF_CTRL_SF_IF_1_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS)
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#define SF_CTRL_SF_IF_1_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS))
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/* 0x20 : sf_if_status_0 */
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#define SF_CTRL_SF_IF_STATUS_0_OFFSET (0x20)
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#define SF_CTRL_SF_IF_STATUS_0 SF_CTRL_SF_IF_STATUS_0
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#define SF_CTRL_SF_IF_STATUS_0_POS (0U)
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#define SF_CTRL_SF_IF_STATUS_0_LEN (32U)
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#define SF_CTRL_SF_IF_STATUS_0_MSK (((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS)
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#define SF_CTRL_SF_IF_STATUS_0_UMSK (~(((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS))
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/* 0x24 : sf_if_status_1 */
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#define SF_CTRL_SF_IF_STATUS_1_OFFSET (0x24)
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#define SF_CTRL_SF_IF_STATUS_1 SF_CTRL_SF_IF_STATUS_1
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#define SF_CTRL_SF_IF_STATUS_1_POS (0U)
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#define SF_CTRL_SF_IF_STATUS_1_LEN (32U)
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#define SF_CTRL_SF_IF_STATUS_1_MSK (((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS)
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#define SF_CTRL_SF_IF_STATUS_1_UMSK (~(((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS))
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/* 0x28 : sf_aes */
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#define SF_CTRL_SF_AES_OFFSET (0x28)
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#define SF_CTRL_SF_AES_EN SF_CTRL_SF_AES_EN
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#define SF_CTRL_SF_AES_EN_POS (0U)
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#define SF_CTRL_SF_AES_EN_LEN (1U)
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#define SF_CTRL_SF_AES_EN_MSK (((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS)
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#define SF_CTRL_SF_AES_EN_UMSK (~(((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS))
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#define SF_CTRL_SF_AES_MODE SF_CTRL_SF_AES_MODE
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#define SF_CTRL_SF_AES_MODE_POS (1U)
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#define SF_CTRL_SF_AES_MODE_LEN (2U)
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#define SF_CTRL_SF_AES_MODE_MSK (((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS)
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#define SF_CTRL_SF_AES_MODE_UMSK (~(((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS))
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#define SF_CTRL_SF_AES_PREF_TRIG SF_CTRL_SF_AES_PREF_TRIG
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#define SF_CTRL_SF_AES_PREF_TRIG_POS (3U)
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#define SF_CTRL_SF_AES_PREF_TRIG_LEN (1U)
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#define SF_CTRL_SF_AES_PREF_TRIG_MSK (((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS)
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#define SF_CTRL_SF_AES_PREF_TRIG_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS))
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#define SF_CTRL_SF_AES_PREF_BUSY SF_CTRL_SF_AES_PREF_BUSY
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#define SF_CTRL_SF_AES_PREF_BUSY_POS (4U)
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#define SF_CTRL_SF_AES_PREF_BUSY_LEN (1U)
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#define SF_CTRL_SF_AES_PREF_BUSY_MSK (((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS)
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#define SF_CTRL_SF_AES_PREF_BUSY_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS))
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#define SF_CTRL_SF_AES_STATUS SF_CTRL_SF_AES_STATUS
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#define SF_CTRL_SF_AES_STATUS_POS (5U)
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#define SF_CTRL_SF_AES_STATUS_LEN (27U)
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#define SF_CTRL_SF_AES_STATUS_MSK (((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS)
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#define SF_CTRL_SF_AES_STATUS_UMSK (~(((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS))
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/* 0x2C : sf_ahb2sif_status */
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#define SF_CTRL_SF_AHB2SIF_STATUS_OFFSET (0x2C)
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#define SF_CTRL_SF_AHB2SIF_STATUS SF_CTRL_SF_AHB2SIF_STATUS
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#define SF_CTRL_SF_AHB2SIF_STATUS_POS (0U)
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#define SF_CTRL_SF_AHB2SIF_STATUS_LEN (32U)
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#define SF_CTRL_SF_AHB2SIF_STATUS_MSK (((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS)
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#define SF_CTRL_SF_AHB2SIF_STATUS_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS))
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/* 0x30 : sf_if_io_dly_0 */
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#define SF_CTRL_SF_IF_IO_DLY_0_OFFSET (0x30)
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#define SF_CTRL_SF_CS_DLY_SEL SF_CTRL_SF_CS_DLY_SEL
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#define SF_CTRL_SF_CS_DLY_SEL_POS (0U)
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#define SF_CTRL_SF_CS_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS)
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#define SF_CTRL_SF_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS))
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#define SF_CTRL_SF_CS2_DLY_SEL SF_CTRL_SF_CS2_DLY_SEL
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#define SF_CTRL_SF_CS2_DLY_SEL_POS (2U)
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#define SF_CTRL_SF_CS2_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_CS2_DLY_SEL_MSK (((1U << SF_CTRL_SF_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS2_DLY_SEL_POS)
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#define SF_CTRL_SF_CS2_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS2_DLY_SEL_POS))
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#define SF_CTRL_SF_CLK_OUT_DLY_SEL SF_CTRL_SF_CLK_OUT_DLY_SEL
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#define SF_CTRL_SF_CLK_OUT_DLY_SEL_POS (8U)
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#define SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS)
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#define SF_CTRL_SF_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS))
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#define SF_CTRL_SF_DQS_OE_DLY_SEL SF_CTRL_SF_DQS_OE_DLY_SEL
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#define SF_CTRL_SF_DQS_OE_DLY_SEL_POS (26U)
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#define SF_CTRL_SF_DQS_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS)
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#define SF_CTRL_SF_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS))
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#define SF_CTRL_SF_DQS_DI_DLY_SEL SF_CTRL_SF_DQS_DI_DLY_SEL
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#define SF_CTRL_SF_DQS_DI_DLY_SEL_POS (28U)
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#define SF_CTRL_SF_DQS_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS)
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#define SF_CTRL_SF_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS))
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#define SF_CTRL_SF_DQS_DO_DLY_SEL SF_CTRL_SF_DQS_DO_DLY_SEL
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#define SF_CTRL_SF_DQS_DO_DLY_SEL_POS (30U)
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#define SF_CTRL_SF_DQS_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS)
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#define SF_CTRL_SF_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS))
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/* 0x34 : sf_if_io_dly_1 */
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#define SF_CTRL_SF_IF_IO_DLY_1_OFFSET (0x34)
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#define SF_CTRL_SF_IO_0_OE_DLY_SEL SF_CTRL_SF_IO_0_OE_DLY_SEL
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#define SF_CTRL_SF_IO_0_OE_DLY_SEL_POS (0U)
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#define SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS)
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#define SF_CTRL_SF_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS))
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#define SF_CTRL_SF_IO_0_DI_DLY_SEL SF_CTRL_SF_IO_0_DI_DLY_SEL
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#define SF_CTRL_SF_IO_0_DI_DLY_SEL_POS (8U)
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#define SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS)
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#define SF_CTRL_SF_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS))
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#define SF_CTRL_SF_IO_0_DO_DLY_SEL SF_CTRL_SF_IO_0_DO_DLY_SEL
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#define SF_CTRL_SF_IO_0_DO_DLY_SEL_POS (16U)
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#define SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS)
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#define SF_CTRL_SF_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS))
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/* 0x38 : sf_if_io_dly_2 */
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#define SF_CTRL_SF_IF_IO_DLY_2_OFFSET (0x38)
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#define SF_CTRL_SF_IO_1_OE_DLY_SEL SF_CTRL_SF_IO_1_OE_DLY_SEL
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#define SF_CTRL_SF_IO_1_OE_DLY_SEL_POS (0U)
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#define SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS)
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#define SF_CTRL_SF_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS))
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#define SF_CTRL_SF_IO_1_DI_DLY_SEL SF_CTRL_SF_IO_1_DI_DLY_SEL
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#define SF_CTRL_SF_IO_1_DI_DLY_SEL_POS (8U)
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#define SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS)
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#define SF_CTRL_SF_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS))
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#define SF_CTRL_SF_IO_1_DO_DLY_SEL SF_CTRL_SF_IO_1_DO_DLY_SEL
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#define SF_CTRL_SF_IO_1_DO_DLY_SEL_POS (16U)
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#define SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS)
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#define SF_CTRL_SF_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS))
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/* 0x3C : sf_if_io_dly_3 */
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#define SF_CTRL_SF_IF_IO_DLY_3_OFFSET (0x3C)
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#define SF_CTRL_SF_IO_2_OE_DLY_SEL SF_CTRL_SF_IO_2_OE_DLY_SEL
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#define SF_CTRL_SF_IO_2_OE_DLY_SEL_POS (0U)
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#define SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS)
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#define SF_CTRL_SF_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS))
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#define SF_CTRL_SF_IO_2_DI_DLY_SEL SF_CTRL_SF_IO_2_DI_DLY_SEL
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#define SF_CTRL_SF_IO_2_DI_DLY_SEL_POS (8U)
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#define SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS)
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#define SF_CTRL_SF_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS))
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#define SF_CTRL_SF_IO_2_DO_DLY_SEL SF_CTRL_SF_IO_2_DO_DLY_SEL
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#define SF_CTRL_SF_IO_2_DO_DLY_SEL_POS (16U)
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#define SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS)
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#define SF_CTRL_SF_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS))
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/* 0x40 : sf_if_io_dly_4 */
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#define SF_CTRL_SF_IF_IO_DLY_4_OFFSET (0x40)
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#define SF_CTRL_SF_IO_3_OE_DLY_SEL SF_CTRL_SF_IO_3_OE_DLY_SEL
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#define SF_CTRL_SF_IO_3_OE_DLY_SEL_POS (0U)
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#define SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS)
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#define SF_CTRL_SF_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS))
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#define SF_CTRL_SF_IO_3_DI_DLY_SEL SF_CTRL_SF_IO_3_DI_DLY_SEL
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#define SF_CTRL_SF_IO_3_DI_DLY_SEL_POS (8U)
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#define SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS)
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#define SF_CTRL_SF_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS))
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#define SF_CTRL_SF_IO_3_DO_DLY_SEL SF_CTRL_SF_IO_3_DO_DLY_SEL
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#define SF_CTRL_SF_IO_3_DO_DLY_SEL_POS (16U)
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#define SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS)
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#define SF_CTRL_SF_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS))
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/* 0x44 : sf_reserved */
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#define SF_CTRL_SF_RESERVED_OFFSET (0x44)
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#define SF_CTRL_SF_RESERVED SF_CTRL_SF_RESERVED
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#define SF_CTRL_SF_RESERVED_POS (0U)
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#define SF_CTRL_SF_RESERVED_LEN (32U)
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#define SF_CTRL_SF_RESERVED_MSK (((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS)
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#define SF_CTRL_SF_RESERVED_UMSK (~(((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS))
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/* 0x48 : sf2_if_io_dly_0 */
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#define SF_CTRL_SF2_IF_IO_DLY_0_OFFSET (0x48)
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#define SF_CTRL_SF2_CS_DLY_SEL SF_CTRL_SF2_CS_DLY_SEL
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#define SF_CTRL_SF2_CS_DLY_SEL_POS (0U)
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#define SF_CTRL_SF2_CS_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS)
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#define SF_CTRL_SF2_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS))
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#define SF_CTRL_SF2_CS2_DLY_SEL SF_CTRL_SF2_CS2_DLY_SEL
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#define SF_CTRL_SF2_CS2_DLY_SEL_POS (2U)
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#define SF_CTRL_SF2_CS2_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_CS2_DLY_SEL_MSK (((1U << SF_CTRL_SF2_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS2_DLY_SEL_POS)
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#define SF_CTRL_SF2_CS2_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS2_DLY_SEL_POS))
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#define SF_CTRL_SF2_CLK_OUT_DLY_SEL SF_CTRL_SF2_CLK_OUT_DLY_SEL
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#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS (8U)
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#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS)
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#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS))
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#define SF_CTRL_SF2_DQS_OE_DLY_SEL SF_CTRL_SF2_DQS_OE_DLY_SEL
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#define SF_CTRL_SF2_DQS_OE_DLY_SEL_POS (26U)
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#define SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS)
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#define SF_CTRL_SF2_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS))
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#define SF_CTRL_SF2_DQS_DI_DLY_SEL SF_CTRL_SF2_DQS_DI_DLY_SEL
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#define SF_CTRL_SF2_DQS_DI_DLY_SEL_POS (28U)
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#define SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS)
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#define SF_CTRL_SF2_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS))
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#define SF_CTRL_SF2_DQS_DO_DLY_SEL SF_CTRL_SF2_DQS_DO_DLY_SEL
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#define SF_CTRL_SF2_DQS_DO_DLY_SEL_POS (30U)
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#define SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS)
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#define SF_CTRL_SF2_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS))
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/* 0x4C : sf2_if_io_dly_1 */
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#define SF_CTRL_SF2_IF_IO_DLY_1_OFFSET (0x4C)
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#define SF_CTRL_SF2_IO_0_OE_DLY_SEL SF_CTRL_SF2_IO_0_OE_DLY_SEL
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#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS (0U)
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#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS)
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#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS))
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#define SF_CTRL_SF2_IO_0_DI_DLY_SEL SF_CTRL_SF2_IO_0_DI_DLY_SEL
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#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS (8U)
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#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS)
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#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS))
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#define SF_CTRL_SF2_IO_0_DO_DLY_SEL SF_CTRL_SF2_IO_0_DO_DLY_SEL
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#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS (16U)
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#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS)
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#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS))
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/* 0x50 : sf2_if_io_dly_2 */
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#define SF_CTRL_SF2_IF_IO_DLY_2_OFFSET (0x50)
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#define SF_CTRL_SF2_IO_1_OE_DLY_SEL SF_CTRL_SF2_IO_1_OE_DLY_SEL
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#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS (0U)
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#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS)
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#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS))
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#define SF_CTRL_SF2_IO_1_DI_DLY_SEL SF_CTRL_SF2_IO_1_DI_DLY_SEL
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#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS (8U)
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#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS)
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#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS))
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#define SF_CTRL_SF2_IO_1_DO_DLY_SEL SF_CTRL_SF2_IO_1_DO_DLY_SEL
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#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS (16U)
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#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS)
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#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS))
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/* 0x54 : sf2_if_io_dly_3 */
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#define SF_CTRL_SF2_IF_IO_DLY_3_OFFSET (0x54)
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#define SF_CTRL_SF2_IO_2_OE_DLY_SEL SF_CTRL_SF2_IO_2_OE_DLY_SEL
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#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS (0U)
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#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS)
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#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS))
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#define SF_CTRL_SF2_IO_2_DI_DLY_SEL SF_CTRL_SF2_IO_2_DI_DLY_SEL
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#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS (8U)
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#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS)
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#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS))
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#define SF_CTRL_SF2_IO_2_DO_DLY_SEL SF_CTRL_SF2_IO_2_DO_DLY_SEL
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#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS (16U)
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#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS)
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#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS))
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/* 0x58 : sf2_if_io_dly_4 */
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#define SF_CTRL_SF2_IF_IO_DLY_4_OFFSET (0x58)
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#define SF_CTRL_SF2_IO_3_OE_DLY_SEL SF_CTRL_SF2_IO_3_OE_DLY_SEL
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#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS (0U)
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#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS)
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#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS))
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#define SF_CTRL_SF2_IO_3_DI_DLY_SEL SF_CTRL_SF2_IO_3_DI_DLY_SEL
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#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS (8U)
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#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS)
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#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS))
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#define SF_CTRL_SF2_IO_3_DO_DLY_SEL SF_CTRL_SF2_IO_3_DO_DLY_SEL
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#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS (16U)
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#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS)
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#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS))
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/* 0x5C : sf3_if_io_dly_0 */
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#define SF_CTRL_SF3_IF_IO_DLY_0_OFFSET (0x5C)
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#define SF_CTRL_SF3_CS_DLY_SEL SF_CTRL_SF3_CS_DLY_SEL
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#define SF_CTRL_SF3_CS_DLY_SEL_POS (0U)
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#define SF_CTRL_SF3_CS_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_CS_DLY_SEL_MSK (((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS)
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#define SF_CTRL_SF3_CS_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS))
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#define SF_CTRL_SF3_CS2_DLY_SEL SF_CTRL_SF3_CS2_DLY_SEL
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#define SF_CTRL_SF3_CS2_DLY_SEL_POS (2U)
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#define SF_CTRL_SF3_CS2_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_CS2_DLY_SEL_MSK (((1U << SF_CTRL_SF3_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS2_DLY_SEL_POS)
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#define SF_CTRL_SF3_CS2_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS2_DLY_SEL_POS))
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#define SF_CTRL_SF3_CLK_OUT_DLY_SEL SF_CTRL_SF3_CLK_OUT_DLY_SEL
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#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS (8U)
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#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_MSK (((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS)
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#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS))
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#define SF_CTRL_SF3_DQS_OE_DLY_SEL SF_CTRL_SF3_DQS_OE_DLY_SEL
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#define SF_CTRL_SF3_DQS_OE_DLY_SEL_POS (26U)
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#define SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_DQS_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS)
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#define SF_CTRL_SF3_DQS_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS))
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#define SF_CTRL_SF3_DQS_DI_DLY_SEL SF_CTRL_SF3_DQS_DI_DLY_SEL
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#define SF_CTRL_SF3_DQS_DI_DLY_SEL_POS (28U)
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#define SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_DQS_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS)
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#define SF_CTRL_SF3_DQS_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS))
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#define SF_CTRL_SF3_DQS_DO_DLY_SEL SF_CTRL_SF3_DQS_DO_DLY_SEL
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#define SF_CTRL_SF3_DQS_DO_DLY_SEL_POS (30U)
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#define SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_DQS_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS)
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#define SF_CTRL_SF3_DQS_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS))
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/* 0x60 : sf3_if_io_dly_1 */
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#define SF_CTRL_SF3_IF_IO_DLY_1_OFFSET (0x60)
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#define SF_CTRL_SF3_IO_0_OE_DLY_SEL SF_CTRL_SF3_IO_0_OE_DLY_SEL
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#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS (0U)
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#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS)
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#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS))
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#define SF_CTRL_SF3_IO_0_DI_DLY_SEL SF_CTRL_SF3_IO_0_DI_DLY_SEL
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#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS (8U)
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#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS)
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#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS))
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#define SF_CTRL_SF3_IO_0_DO_DLY_SEL SF_CTRL_SF3_IO_0_DO_DLY_SEL
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#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS (16U)
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#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS)
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#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS))
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/* 0x64 : sf3_if_io_dly_2 */
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#define SF_CTRL_SF3_IF_IO_DLY_2_OFFSET (0x64)
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#define SF_CTRL_SF3_IO_1_OE_DLY_SEL SF_CTRL_SF3_IO_1_OE_DLY_SEL
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#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS (0U)
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#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS)
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#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS))
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#define SF_CTRL_SF3_IO_1_DI_DLY_SEL SF_CTRL_SF3_IO_1_DI_DLY_SEL
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#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS (8U)
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#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS)
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#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS))
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#define SF_CTRL_SF3_IO_1_DO_DLY_SEL SF_CTRL_SF3_IO_1_DO_DLY_SEL
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#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS (16U)
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#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS)
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#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS))
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/* 0x68 : sf3_if_io_dly_3 */
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#define SF_CTRL_SF3_IF_IO_DLY_3_OFFSET (0x68)
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#define SF_CTRL_SF3_IO_2_OE_DLY_SEL SF_CTRL_SF3_IO_2_OE_DLY_SEL
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#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS (0U)
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#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS)
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#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS))
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#define SF_CTRL_SF3_IO_2_DI_DLY_SEL SF_CTRL_SF3_IO_2_DI_DLY_SEL
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#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS (8U)
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#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS)
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#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS))
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#define SF_CTRL_SF3_IO_2_DO_DLY_SEL SF_CTRL_SF3_IO_2_DO_DLY_SEL
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#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS (16U)
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#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS)
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#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS))
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/* 0x6C : sf3_if_io_dly_4 */
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#define SF_CTRL_SF3_IF_IO_DLY_4_OFFSET (0x6C)
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#define SF_CTRL_SF3_IO_3_OE_DLY_SEL SF_CTRL_SF3_IO_3_OE_DLY_SEL
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#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS (0U)
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#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS)
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#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS))
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#define SF_CTRL_SF3_IO_3_DI_DLY_SEL SF_CTRL_SF3_IO_3_DI_DLY_SEL
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#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS (8U)
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#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS)
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#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS))
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#define SF_CTRL_SF3_IO_3_DO_DLY_SEL SF_CTRL_SF3_IO_3_DO_DLY_SEL
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#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS (16U)
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#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN (2U)
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#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_MSK (((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS)
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#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS))
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/* 0x70 : sf_ctrl_2 */
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#define SF_CTRL_2_OFFSET (0x70)
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#define SF_CTRL_SF_IF_PAD_SEL SF_CTRL_SF_IF_PAD_SEL
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#define SF_CTRL_SF_IF_PAD_SEL_POS (0U)
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#define SF_CTRL_SF_IF_PAD_SEL_LEN (2U)
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#define SF_CTRL_SF_IF_PAD_SEL_MSK (((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS)
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#define SF_CTRL_SF_IF_PAD_SEL_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS))
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#define SF_CTRL_SF_IF_PAD_SEL_LOCK SF_CTRL_SF_IF_PAD_SEL_LOCK
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#define SF_CTRL_SF_IF_PAD_SEL_LOCK_POS (3U)
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#define SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN (1U)
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#define SF_CTRL_SF_IF_PAD_SEL_LOCK_MSK (((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS)
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#define SF_CTRL_SF_IF_PAD_SEL_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS))
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#define SF_CTRL_SF_IF_DTR_EN SF_CTRL_SF_IF_DTR_EN
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#define SF_CTRL_SF_IF_DTR_EN_POS (4U)
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#define SF_CTRL_SF_IF_DTR_EN_LEN (1U)
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#define SF_CTRL_SF_IF_DTR_EN_MSK (((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS)
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#define SF_CTRL_SF_IF_DTR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS))
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#define SF_CTRL_SF_IF_DQS_EN SF_CTRL_SF_IF_DQS_EN
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#define SF_CTRL_SF_IF_DQS_EN_POS (5U)
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#define SF_CTRL_SF_IF_DQS_EN_LEN (1U)
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#define SF_CTRL_SF_IF_DQS_EN_MSK (((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS)
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#define SF_CTRL_SF_IF_DQS_EN_UMSK (~(((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS))
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#define SF_CTRL_SF_IF_BK_SWAP SF_CTRL_SF_IF_BK_SWAP
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#define SF_CTRL_SF_IF_BK_SWAP_POS (28U)
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#define SF_CTRL_SF_IF_BK_SWAP_LEN (1U)
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#define SF_CTRL_SF_IF_BK_SWAP_MSK (((1U << SF_CTRL_SF_IF_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF_BK_SWAP_POS)
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#define SF_CTRL_SF_IF_BK_SWAP_UMSK (~(((1U << SF_CTRL_SF_IF_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF_BK_SWAP_POS))
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#define SF_CTRL_SF_IF_BK2_MODE SF_CTRL_SF_IF_BK2_MODE
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#define SF_CTRL_SF_IF_BK2_MODE_POS (29U)
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#define SF_CTRL_SF_IF_BK2_MODE_LEN (1U)
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#define SF_CTRL_SF_IF_BK2_MODE_MSK (((1U << SF_CTRL_SF_IF_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF_BK2_MODE_POS)
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#define SF_CTRL_SF_IF_BK2_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF_BK2_MODE_POS))
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#define SF_CTRL_SF_IF_BK2_EN SF_CTRL_SF_IF_BK2_EN
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#define SF_CTRL_SF_IF_BK2_EN_POS (30U)
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#define SF_CTRL_SF_IF_BK2_EN_LEN (1U)
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#define SF_CTRL_SF_IF_BK2_EN_MSK (((1U << SF_CTRL_SF_IF_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF_BK2_EN_POS)
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#define SF_CTRL_SF_IF_BK2_EN_UMSK (~(((1U << SF_CTRL_SF_IF_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF_BK2_EN_POS))
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#define SF_CTRL_SF_IF_0_BK_SEL SF_CTRL_SF_IF_0_BK_SEL
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#define SF_CTRL_SF_IF_0_BK_SEL_POS (31U)
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#define SF_CTRL_SF_IF_0_BK_SEL_LEN (1U)
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#define SF_CTRL_SF_IF_0_BK_SEL_MSK (((1U << SF_CTRL_SF_IF_0_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF_0_BK_SEL_POS)
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#define SF_CTRL_SF_IF_0_BK_SEL_UMSK (~(((1U << SF_CTRL_SF_IF_0_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF_0_BK_SEL_POS))
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/* 0x74 : sf_ctrl_3 */
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#define SF_CTRL_3_OFFSET (0x74)
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#define SF_CTRL_SF_CMDS_WRAP_LEN SF_CTRL_SF_CMDS_WRAP_LEN
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#define SF_CTRL_SF_CMDS_WRAP_LEN_POS (0U)
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#define SF_CTRL_SF_CMDS_WRAP_LEN_LEN (4U)
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#define SF_CTRL_SF_CMDS_WRAP_LEN_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS)
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#define SF_CTRL_SF_CMDS_WRAP_LEN_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS))
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#define SF_CTRL_SF_CMDS_EN SF_CTRL_SF_CMDS_EN
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#define SF_CTRL_SF_CMDS_EN_POS (4U)
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#define SF_CTRL_SF_CMDS_EN_LEN (1U)
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#define SF_CTRL_SF_CMDS_EN_MSK (((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS)
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#define SF_CTRL_SF_CMDS_EN_UMSK (~(((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS))
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#define SF_CTRL_SF_CMDS_BT_DLY SF_CTRL_SF_CMDS_BT_DLY
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#define SF_CTRL_SF_CMDS_BT_DLY_POS (5U)
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#define SF_CTRL_SF_CMDS_BT_DLY_LEN (3U)
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#define SF_CTRL_SF_CMDS_BT_DLY_MSK (((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS)
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#define SF_CTRL_SF_CMDS_BT_DLY_UMSK (~(((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS))
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#define SF_CTRL_SF_CMDS_BT_EN SF_CTRL_SF_CMDS_BT_EN
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#define SF_CTRL_SF_CMDS_BT_EN_POS (8U)
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#define SF_CTRL_SF_CMDS_BT_EN_LEN (1U)
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#define SF_CTRL_SF_CMDS_BT_EN_MSK (((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS)
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#define SF_CTRL_SF_CMDS_BT_EN_UMSK (~(((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS))
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#define SF_CTRL_SF_CMDS_WRAP_Q_INI SF_CTRL_SF_CMDS_WRAP_Q_INI
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#define SF_CTRL_SF_CMDS_WRAP_Q_INI_POS (9U)
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#define SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN (1U)
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#define SF_CTRL_SF_CMDS_WRAP_Q_INI_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS)
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#define SF_CTRL_SF_CMDS_WRAP_Q_INI_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS))
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#define SF_CTRL_SF_CMDS_WRAP_MODE SF_CTRL_SF_CMDS_WRAP_MODE
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#define SF_CTRL_SF_CMDS_WRAP_MODE_POS (10U)
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#define SF_CTRL_SF_CMDS_WRAP_MODE_LEN (1U)
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#define SF_CTRL_SF_CMDS_WRAP_MODE_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS)
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#define SF_CTRL_SF_CMDS_WRAP_MODE_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS))
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#define SF_CTRL_SF_CMDS_WRAP_Q SF_CTRL_SF_CMDS_WRAP_Q
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#define SF_CTRL_SF_CMDS_WRAP_Q_POS (11U)
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#define SF_CTRL_SF_CMDS_WRAP_Q_LEN (1U)
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#define SF_CTRL_SF_CMDS_WRAP_Q_MSK (((1U << SF_CTRL_SF_CMDS_WRAP_Q_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_POS)
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#define SF_CTRL_SF_CMDS_WRAP_Q_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_Q_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_POS))
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#define SF_CTRL_SF_IF_1_ACK_LAT SF_CTRL_SF_IF_1_ACK_LAT
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#define SF_CTRL_SF_IF_1_ACK_LAT_POS (29U)
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#define SF_CTRL_SF_IF_1_ACK_LAT_LEN (3U)
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#define SF_CTRL_SF_IF_1_ACK_LAT_MSK (((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS)
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#define SF_CTRL_SF_IF_1_ACK_LAT_UMSK (~(((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS))
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/* 0x78 : sf_if_iahb_3 */
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#define SF_CTRL_SF_IF_IAHB_3_OFFSET (0x78)
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#define SF_CTRL_SF_IF_2_DMY_BYTE SF_CTRL_SF_IF_2_DMY_BYTE
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#define SF_CTRL_SF_IF_2_DMY_BYTE_POS (12U)
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#define SF_CTRL_SF_IF_2_DMY_BYTE_LEN (5U)
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#define SF_CTRL_SF_IF_2_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS)
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#define SF_CTRL_SF_IF_2_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS))
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#define SF_CTRL_SF_IF_2_ADR_BYTE SF_CTRL_SF_IF_2_ADR_BYTE
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#define SF_CTRL_SF_IF_2_ADR_BYTE_POS (17U)
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#define SF_CTRL_SF_IF_2_ADR_BYTE_LEN (3U)
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#define SF_CTRL_SF_IF_2_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS)
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#define SF_CTRL_SF_IF_2_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS))
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#define SF_CTRL_SF_IF_2_CMD_BYTE SF_CTRL_SF_IF_2_CMD_BYTE
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#define SF_CTRL_SF_IF_2_CMD_BYTE_POS (20U)
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#define SF_CTRL_SF_IF_2_CMD_BYTE_LEN (3U)
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#define SF_CTRL_SF_IF_2_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS)
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#define SF_CTRL_SF_IF_2_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS))
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#define SF_CTRL_SF_IF_2_DAT_RW SF_CTRL_SF_IF_2_DAT_RW
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#define SF_CTRL_SF_IF_2_DAT_RW_POS (23U)
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#define SF_CTRL_SF_IF_2_DAT_RW_LEN (1U)
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#define SF_CTRL_SF_IF_2_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS)
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#define SF_CTRL_SF_IF_2_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS))
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#define SF_CTRL_SF_IF_2_DAT_EN SF_CTRL_SF_IF_2_DAT_EN
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#define SF_CTRL_SF_IF_2_DAT_EN_POS (24U)
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#define SF_CTRL_SF_IF_2_DAT_EN_LEN (1U)
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#define SF_CTRL_SF_IF_2_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS)
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#define SF_CTRL_SF_IF_2_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS))
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#define SF_CTRL_SF_IF_2_DMY_EN SF_CTRL_SF_IF_2_DMY_EN
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#define SF_CTRL_SF_IF_2_DMY_EN_POS (25U)
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#define SF_CTRL_SF_IF_2_DMY_EN_LEN (1U)
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#define SF_CTRL_SF_IF_2_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS)
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#define SF_CTRL_SF_IF_2_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS))
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#define SF_CTRL_SF_IF_2_ADR_EN SF_CTRL_SF_IF_2_ADR_EN
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#define SF_CTRL_SF_IF_2_ADR_EN_POS (26U)
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#define SF_CTRL_SF_IF_2_ADR_EN_LEN (1U)
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#define SF_CTRL_SF_IF_2_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS)
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#define SF_CTRL_SF_IF_2_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS))
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#define SF_CTRL_SF_IF_2_CMD_EN SF_CTRL_SF_IF_2_CMD_EN
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#define SF_CTRL_SF_IF_2_CMD_EN_POS (27U)
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#define SF_CTRL_SF_IF_2_CMD_EN_LEN (1U)
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#define SF_CTRL_SF_IF_2_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS)
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#define SF_CTRL_SF_IF_2_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS))
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#define SF_CTRL_SF_IF_2_SPI_MODE SF_CTRL_SF_IF_2_SPI_MODE
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#define SF_CTRL_SF_IF_2_SPI_MODE_POS (28U)
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#define SF_CTRL_SF_IF_2_SPI_MODE_LEN (3U)
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#define SF_CTRL_SF_IF_2_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS)
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#define SF_CTRL_SF_IF_2_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS))
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#define SF_CTRL_SF_IF_2_QPI_MODE_EN SF_CTRL_SF_IF_2_QPI_MODE_EN
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#define SF_CTRL_SF_IF_2_QPI_MODE_EN_POS (31U)
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#define SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN (1U)
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#define SF_CTRL_SF_IF_2_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS)
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#define SF_CTRL_SF_IF_2_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS))
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/* 0x7C : sf_if_iahb_4 */
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#define SF_CTRL_SF_IF_IAHB_4_OFFSET (0x7C)
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#define SF_CTRL_SF_IF_2_CMD_BUF_0 SF_CTRL_SF_IF_2_CMD_BUF_0
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#define SF_CTRL_SF_IF_2_CMD_BUF_0_POS (0U)
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#define SF_CTRL_SF_IF_2_CMD_BUF_0_LEN (32U)
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#define SF_CTRL_SF_IF_2_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS)
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#define SF_CTRL_SF_IF_2_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS))
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/* 0x80 : sf_if_iahb_5 */
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#define SF_CTRL_SF_IF_IAHB_5_OFFSET (0x80)
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#define SF_CTRL_SF_IF_2_CMD_BUF_1 SF_CTRL_SF_IF_2_CMD_BUF_1
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#define SF_CTRL_SF_IF_2_CMD_BUF_1_POS (0U)
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#define SF_CTRL_SF_IF_2_CMD_BUF_1_LEN (32U)
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#define SF_CTRL_SF_IF_2_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS)
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#define SF_CTRL_SF_IF_2_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS))
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/* 0x84 : sf_if_iahb_6 */
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#define SF_CTRL_SF_IF_IAHB_6_OFFSET (0x84)
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#define SF_CTRL_SF_IF_3_ADR_BYTE SF_CTRL_SF_IF_3_ADR_BYTE
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#define SF_CTRL_SF_IF_3_ADR_BYTE_POS (17U)
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#define SF_CTRL_SF_IF_3_ADR_BYTE_LEN (3U)
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#define SF_CTRL_SF_IF_3_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_3_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_BYTE_POS)
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#define SF_CTRL_SF_IF_3_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_3_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_BYTE_POS))
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#define SF_CTRL_SF_IF_3_CMD_BYTE SF_CTRL_SF_IF_3_CMD_BYTE
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#define SF_CTRL_SF_IF_3_CMD_BYTE_POS (20U)
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#define SF_CTRL_SF_IF_3_CMD_BYTE_LEN (3U)
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#define SF_CTRL_SF_IF_3_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS)
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#define SF_CTRL_SF_IF_3_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS))
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#define SF_CTRL_SF_IF_3_ADR_EN SF_CTRL_SF_IF_3_ADR_EN
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#define SF_CTRL_SF_IF_3_ADR_EN_POS (26U)
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#define SF_CTRL_SF_IF_3_ADR_EN_LEN (1U)
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#define SF_CTRL_SF_IF_3_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_3_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_EN_POS)
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#define SF_CTRL_SF_IF_3_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_EN_POS))
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#define SF_CTRL_SF_IF_3_CMD_EN SF_CTRL_SF_IF_3_CMD_EN
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#define SF_CTRL_SF_IF_3_CMD_EN_POS (27U)
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#define SF_CTRL_SF_IF_3_CMD_EN_LEN (1U)
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#define SF_CTRL_SF_IF_3_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_3_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_EN_POS)
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#define SF_CTRL_SF_IF_3_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_EN_POS))
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#define SF_CTRL_SF_IF_3_SPI_MODE SF_CTRL_SF_IF_3_SPI_MODE
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#define SF_CTRL_SF_IF_3_SPI_MODE_POS (28U)
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#define SF_CTRL_SF_IF_3_SPI_MODE_LEN (3U)
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#define SF_CTRL_SF_IF_3_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS)
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#define SF_CTRL_SF_IF_3_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS))
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#define SF_CTRL_SF_IF_3_QPI_MODE_EN SF_CTRL_SF_IF_3_QPI_MODE_EN
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#define SF_CTRL_SF_IF_3_QPI_MODE_EN_POS (31U)
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#define SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN (1U)
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#define SF_CTRL_SF_IF_3_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS)
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#define SF_CTRL_SF_IF_3_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS))
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/* 0x88 : sf_if_iahb_7 */
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#define SF_CTRL_SF_IF_IAHB_7_OFFSET (0x88)
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#define SF_CTRL_SF_IF_3_CMD_BUF_0 SF_CTRL_SF_IF_3_CMD_BUF_0
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#define SF_CTRL_SF_IF_3_CMD_BUF_0_POS (0U)
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#define SF_CTRL_SF_IF_3_CMD_BUF_0_LEN (32U)
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#define SF_CTRL_SF_IF_3_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS)
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#define SF_CTRL_SF_IF_3_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS))
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/* 0x8C : sf_if_iahb_8 */
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#define SF_CTRL_SF_IF_IAHB_8_OFFSET (0x8C)
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#define SF_CTRL_SF_IF_3_CMD_BUF_1 SF_CTRL_SF_IF_3_CMD_BUF_1
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#define SF_CTRL_SF_IF_3_CMD_BUF_1_POS (0U)
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#define SF_CTRL_SF_IF_3_CMD_BUF_1_LEN (32U)
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#define SF_CTRL_SF_IF_3_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_3_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_1_POS)
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#define SF_CTRL_SF_IF_3_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_1_POS))
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/* 0x90 : sf_if_iahb_9 */
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#define SF_CTRL_SF_IF_IAHB_9_OFFSET (0x90)
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#define SF_CTRL_SF_IF_4_DMY_BYTE SF_CTRL_SF_IF_4_DMY_BYTE
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#define SF_CTRL_SF_IF_4_DMY_BYTE_POS (12U)
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#define SF_CTRL_SF_IF_4_DMY_BYTE_LEN (5U)
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#define SF_CTRL_SF_IF_4_DMY_BYTE_MSK (((1U << SF_CTRL_SF_IF_4_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_BYTE_POS)
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#define SF_CTRL_SF_IF_4_DMY_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_4_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_BYTE_POS))
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#define SF_CTRL_SF_IF_4_ADR_BYTE SF_CTRL_SF_IF_4_ADR_BYTE
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#define SF_CTRL_SF_IF_4_ADR_BYTE_POS (17U)
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#define SF_CTRL_SF_IF_4_ADR_BYTE_LEN (3U)
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#define SF_CTRL_SF_IF_4_ADR_BYTE_MSK (((1U << SF_CTRL_SF_IF_4_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_BYTE_POS)
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#define SF_CTRL_SF_IF_4_ADR_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_4_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_BYTE_POS))
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#define SF_CTRL_SF_IF_4_CMD_BYTE SF_CTRL_SF_IF_4_CMD_BYTE
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#define SF_CTRL_SF_IF_4_CMD_BYTE_POS (20U)
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#define SF_CTRL_SF_IF_4_CMD_BYTE_LEN (3U)
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#define SF_CTRL_SF_IF_4_CMD_BYTE_MSK (((1U << SF_CTRL_SF_IF_4_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BYTE_POS)
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#define SF_CTRL_SF_IF_4_CMD_BYTE_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BYTE_POS))
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#define SF_CTRL_SF_IF_4_DAT_RW SF_CTRL_SF_IF_4_DAT_RW
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#define SF_CTRL_SF_IF_4_DAT_RW_POS (23U)
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#define SF_CTRL_SF_IF_4_DAT_RW_LEN (1U)
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#define SF_CTRL_SF_IF_4_DAT_RW_MSK (((1U << SF_CTRL_SF_IF_4_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_RW_POS)
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#define SF_CTRL_SF_IF_4_DAT_RW_UMSK (~(((1U << SF_CTRL_SF_IF_4_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_RW_POS))
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#define SF_CTRL_SF_IF_4_DAT_EN SF_CTRL_SF_IF_4_DAT_EN
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#define SF_CTRL_SF_IF_4_DAT_EN_POS (24U)
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#define SF_CTRL_SF_IF_4_DAT_EN_LEN (1U)
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#define SF_CTRL_SF_IF_4_DAT_EN_MSK (((1U << SF_CTRL_SF_IF_4_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_EN_POS)
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#define SF_CTRL_SF_IF_4_DAT_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_EN_POS))
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#define SF_CTRL_SF_IF_4_DMY_EN SF_CTRL_SF_IF_4_DMY_EN
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#define SF_CTRL_SF_IF_4_DMY_EN_POS (25U)
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#define SF_CTRL_SF_IF_4_DMY_EN_LEN (1U)
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#define SF_CTRL_SF_IF_4_DMY_EN_MSK (((1U << SF_CTRL_SF_IF_4_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_EN_POS)
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#define SF_CTRL_SF_IF_4_DMY_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_EN_POS))
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#define SF_CTRL_SF_IF_4_ADR_EN SF_CTRL_SF_IF_4_ADR_EN
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#define SF_CTRL_SF_IF_4_ADR_EN_POS (26U)
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#define SF_CTRL_SF_IF_4_ADR_EN_LEN (1U)
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#define SF_CTRL_SF_IF_4_ADR_EN_MSK (((1U << SF_CTRL_SF_IF_4_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_EN_POS)
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#define SF_CTRL_SF_IF_4_ADR_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_EN_POS))
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#define SF_CTRL_SF_IF_4_CMD_EN SF_CTRL_SF_IF_4_CMD_EN
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#define SF_CTRL_SF_IF_4_CMD_EN_POS (27U)
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#define SF_CTRL_SF_IF_4_CMD_EN_LEN (1U)
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#define SF_CTRL_SF_IF_4_CMD_EN_MSK (((1U << SF_CTRL_SF_IF_4_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_EN_POS)
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#define SF_CTRL_SF_IF_4_CMD_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_EN_POS))
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#define SF_CTRL_SF_IF_4_SPI_MODE SF_CTRL_SF_IF_4_SPI_MODE
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#define SF_CTRL_SF_IF_4_SPI_MODE_POS (28U)
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#define SF_CTRL_SF_IF_4_SPI_MODE_LEN (3U)
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#define SF_CTRL_SF_IF_4_SPI_MODE_MSK (((1U << SF_CTRL_SF_IF_4_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_4_SPI_MODE_POS)
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#define SF_CTRL_SF_IF_4_SPI_MODE_UMSK (~(((1U << SF_CTRL_SF_IF_4_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_4_SPI_MODE_POS))
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#define SF_CTRL_SF_IF_4_QPI_MODE_EN SF_CTRL_SF_IF_4_QPI_MODE_EN
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#define SF_CTRL_SF_IF_4_QPI_MODE_EN_POS (31U)
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#define SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN (1U)
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#define SF_CTRL_SF_IF_4_QPI_MODE_EN_MSK (((1U << SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_4_QPI_MODE_EN_POS)
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#define SF_CTRL_SF_IF_4_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_4_QPI_MODE_EN_POS))
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/* 0x94 : sf_if_iahb_10 */
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#define SF_CTRL_SF_IF_IAHB_10_OFFSET (0x94)
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#define SF_CTRL_SF_IF_4_CMD_BUF_0 SF_CTRL_SF_IF_4_CMD_BUF_0
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#define SF_CTRL_SF_IF_4_CMD_BUF_0_POS (0U)
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#define SF_CTRL_SF_IF_4_CMD_BUF_0_LEN (32U)
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#define SF_CTRL_SF_IF_4_CMD_BUF_0_MSK (((1U << SF_CTRL_SF_IF_4_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_0_POS)
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#define SF_CTRL_SF_IF_4_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_0_POS))
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/* 0x98 : sf_if_iahb_11 */
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#define SF_CTRL_SF_IF_IAHB_11_OFFSET (0x98)
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#define SF_CTRL_SF_IF_4_CMD_BUF_1 SF_CTRL_SF_IF_4_CMD_BUF_1
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#define SF_CTRL_SF_IF_4_CMD_BUF_1_POS (0U)
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#define SF_CTRL_SF_IF_4_CMD_BUF_1_LEN (32U)
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#define SF_CTRL_SF_IF_4_CMD_BUF_1_MSK (((1U << SF_CTRL_SF_IF_4_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_1_POS)
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#define SF_CTRL_SF_IF_4_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_1_POS))
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/* 0x9C : sf_if_iahb_12 */
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#define SF_CTRL_SF_IF_IAHB_12_OFFSET (0x9C)
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#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL SF_CTRL_SF2_CLK_SF_RX_INV_SEL
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#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS (2U)
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#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN (1U)
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#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_MSK (((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS)
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#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS))
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#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC SF_CTRL_SF2_CLK_SF_RX_INV_SRC
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#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS (3U)
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#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN (1U)
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#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_MSK (((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS)
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#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_UMSK (~(((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS))
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#define SF_CTRL_SF2_CLK_OUT_INV_SEL SF_CTRL_SF2_CLK_OUT_INV_SEL
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#define SF_CTRL_SF2_CLK_OUT_INV_SEL_POS (4U)
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#define SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN (1U)
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#define SF_CTRL_SF2_CLK_OUT_INV_SEL_MSK (((1U << SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_INV_SEL_POS)
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#define SF_CTRL_SF2_CLK_OUT_INV_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_INV_SEL_POS))
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#define SF_CTRL_SF3_CLK_OUT_INV_SEL SF_CTRL_SF3_CLK_OUT_INV_SEL
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#define SF_CTRL_SF3_CLK_OUT_INV_SEL_POS (5U)
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#define SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN (1U)
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#define SF_CTRL_SF3_CLK_OUT_INV_SEL_MSK (((1U << SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_INV_SEL_POS)
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#define SF_CTRL_SF3_CLK_OUT_INV_SEL_UMSK (~(((1U << SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_INV_SEL_POS))
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#define SF_CTRL_SF2_IF_READ_DLY_N SF_CTRL_SF2_IF_READ_DLY_N
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#define SF_CTRL_SF2_IF_READ_DLY_N_POS (8U)
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#define SF_CTRL_SF2_IF_READ_DLY_N_LEN (3U)
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#define SF_CTRL_SF2_IF_READ_DLY_N_MSK (((1U << SF_CTRL_SF2_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_N_POS)
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#define SF_CTRL_SF2_IF_READ_DLY_N_UMSK (~(((1U << SF_CTRL_SF2_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_N_POS))
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#define SF_CTRL_SF2_IF_READ_DLY_EN SF_CTRL_SF2_IF_READ_DLY_EN
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#define SF_CTRL_SF2_IF_READ_DLY_EN_POS (11U)
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#define SF_CTRL_SF2_IF_READ_DLY_EN_LEN (1U)
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#define SF_CTRL_SF2_IF_READ_DLY_EN_MSK (((1U << SF_CTRL_SF2_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_EN_POS)
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#define SF_CTRL_SF2_IF_READ_DLY_EN_UMSK (~(((1U << SF_CTRL_SF2_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_EN_POS))
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#define SF_CTRL_SF2_IF_READ_DLY_SRC SF_CTRL_SF2_IF_READ_DLY_SRC
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#define SF_CTRL_SF2_IF_READ_DLY_SRC_POS (12U)
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#define SF_CTRL_SF2_IF_READ_DLY_SRC_LEN (1U)
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#define SF_CTRL_SF2_IF_READ_DLY_SRC_MSK (((1U << SF_CTRL_SF2_IF_READ_DLY_SRC_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_SRC_POS)
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#define SF_CTRL_SF2_IF_READ_DLY_SRC_UMSK (~(((1U << SF_CTRL_SF2_IF_READ_DLY_SRC_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_SRC_POS))
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/* 0x100 : sf_ctrl_prot_en_rd */
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#define SF_CTRL_PROT_EN_RD_OFFSET (0x100)
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#define SF_CTRL_PROT_EN_RD SF_CTRL_PROT_EN_RD
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#define SF_CTRL_PROT_EN_RD_POS (0U)
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#define SF_CTRL_PROT_EN_RD_LEN (1U)
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#define SF_CTRL_PROT_EN_RD_MSK (((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS)
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#define SF_CTRL_PROT_EN_RD_UMSK (~(((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS))
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#define SF_CTRL_ID0_EN_RD SF_CTRL_ID0_EN_RD
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#define SF_CTRL_ID0_EN_RD_POS (1U)
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#define SF_CTRL_ID0_EN_RD_LEN (1U)
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#define SF_CTRL_ID0_EN_RD_MSK (((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS)
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#define SF_CTRL_ID0_EN_RD_UMSK (~(((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS))
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#define SF_CTRL_ID1_EN_RD SF_CTRL_ID1_EN_RD
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#define SF_CTRL_ID1_EN_RD_POS (2U)
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#define SF_CTRL_ID1_EN_RD_LEN (1U)
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#define SF_CTRL_ID1_EN_RD_MSK (((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS)
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#define SF_CTRL_ID1_EN_RD_UMSK (~(((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS))
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#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK SF_CTRL_SF_IF_0_TRIG_WR_LOCK
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#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS (30U)
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#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN (1U)
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#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_MSK (((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS)
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#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS))
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#define SF_CTRL_SF_DBG_DIS SF_CTRL_SF_DBG_DIS
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#define SF_CTRL_SF_DBG_DIS_POS (31U)
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#define SF_CTRL_SF_DBG_DIS_LEN (1U)
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#define SF_CTRL_SF_DBG_DIS_MSK (((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS)
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#define SF_CTRL_SF_DBG_DIS_UMSK (~(((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS))
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/* 0x104 : sf_ctrl_prot_en */
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#define SF_CTRL_PROT_EN_OFFSET (0x104)
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#define SF_CTRL_PROT_EN SF_CTRL_PROT_EN
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#define SF_CTRL_PROT_EN_POS (0U)
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#define SF_CTRL_PROT_EN_LEN (1U)
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#define SF_CTRL_PROT_EN_MSK (((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS)
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#define SF_CTRL_PROT_EN_UMSK (~(((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS))
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#define SF_CTRL_ID0_EN SF_CTRL_ID0_EN
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#define SF_CTRL_ID0_EN_POS (1U)
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#define SF_CTRL_ID0_EN_LEN (1U)
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#define SF_CTRL_ID0_EN_MSK (((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS)
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#define SF_CTRL_ID0_EN_UMSK (~(((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS))
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#define SF_CTRL_ID1_EN SF_CTRL_ID1_EN
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#define SF_CTRL_ID1_EN_POS (2U)
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#define SF_CTRL_ID1_EN_LEN (1U)
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#define SF_CTRL_ID1_EN_MSK (((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS)
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#define SF_CTRL_ID1_EN_UMSK (~(((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS))
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/* 0x200 : sf_aes_key_r0_0 */
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#define SF_CTRL_SF_AES_KEY_R0_0_OFFSET (0x200)
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#define SF_CTRL_SF_AES_KEY_R0_0 SF_CTRL_SF_AES_KEY_R0_0
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#define SF_CTRL_SF_AES_KEY_R0_0_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R0_0_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R0_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS)
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#define SF_CTRL_SF_AES_KEY_R0_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS))
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/* 0x204 : sf_aes_key_r0_1 */
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#define SF_CTRL_SF_AES_KEY_R0_1_OFFSET (0x204)
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#define SF_CTRL_SF_AES_KEY_R0_1 SF_CTRL_SF_AES_KEY_R0_1
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#define SF_CTRL_SF_AES_KEY_R0_1_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R0_1_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R0_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS)
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#define SF_CTRL_SF_AES_KEY_R0_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS))
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/* 0x208 : sf_aes_key_r0_2 */
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#define SF_CTRL_SF_AES_KEY_R0_2_OFFSET (0x208)
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#define SF_CTRL_SF_AES_KEY_R0_2 SF_CTRL_SF_AES_KEY_R0_2
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#define SF_CTRL_SF_AES_KEY_R0_2_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R0_2_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R0_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS)
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#define SF_CTRL_SF_AES_KEY_R0_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS))
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/* 0x20C : sf_aes_key_r0_3 */
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#define SF_CTRL_SF_AES_KEY_R0_3_OFFSET (0x20C)
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#define SF_CTRL_SF_AES_KEY_R0_3 SF_CTRL_SF_AES_KEY_R0_3
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#define SF_CTRL_SF_AES_KEY_R0_3_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R0_3_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R0_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS)
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#define SF_CTRL_SF_AES_KEY_R0_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS))
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/* 0x210 : sf_aes_key_r0_4 */
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#define SF_CTRL_SF_AES_KEY_R0_4_OFFSET (0x210)
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#define SF_CTRL_SF_AES_KEY_R0_4 SF_CTRL_SF_AES_KEY_R0_4
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#define SF_CTRL_SF_AES_KEY_R0_4_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R0_4_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R0_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS)
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#define SF_CTRL_SF_AES_KEY_R0_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS))
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/* 0x214 : sf_aes_key_r0_5 */
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#define SF_CTRL_SF_AES_KEY_R0_5_OFFSET (0x214)
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#define SF_CTRL_SF_AES_KEY_R0_5 SF_CTRL_SF_AES_KEY_R0_5
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#define SF_CTRL_SF_AES_KEY_R0_5_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R0_5_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R0_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS)
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#define SF_CTRL_SF_AES_KEY_R0_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS))
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/* 0x218 : sf_aes_key_r0_6 */
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#define SF_CTRL_SF_AES_KEY_R0_6_OFFSET (0x218)
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#define SF_CTRL_SF_AES_KEY_R0_6 SF_CTRL_SF_AES_KEY_R0_6
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#define SF_CTRL_SF_AES_KEY_R0_6_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R0_6_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R0_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS)
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#define SF_CTRL_SF_AES_KEY_R0_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS))
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/* 0x21C : sf_aes_key_r0_7 */
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#define SF_CTRL_SF_AES_KEY_R0_7_OFFSET (0x21C)
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#define SF_CTRL_SF_AES_KEY_R0_7 SF_CTRL_SF_AES_KEY_R0_7
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#define SF_CTRL_SF_AES_KEY_R0_7_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R0_7_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R0_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS)
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#define SF_CTRL_SF_AES_KEY_R0_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS))
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/* 0x220 : sf_aes_iv_r0_w0 */
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#define SF_CTRL_SF_AES_IV_R0_W0_OFFSET (0x220)
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#define SF_CTRL_SF_AES_IV_R0_W0 SF_CTRL_SF_AES_IV_R0_W0
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#define SF_CTRL_SF_AES_IV_R0_W0_POS (0U)
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#define SF_CTRL_SF_AES_IV_R0_W0_LEN (32U)
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#define SF_CTRL_SF_AES_IV_R0_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS)
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#define SF_CTRL_SF_AES_IV_R0_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS))
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/* 0x224 : sf_aes_iv_r0_w1 */
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#define SF_CTRL_SF_AES_IV_R0_W1_OFFSET (0x224)
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#define SF_CTRL_SF_AES_IV_R0_W1 SF_CTRL_SF_AES_IV_R0_W1
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#define SF_CTRL_SF_AES_IV_R0_W1_POS (0U)
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#define SF_CTRL_SF_AES_IV_R0_W1_LEN (32U)
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#define SF_CTRL_SF_AES_IV_R0_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS)
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#define SF_CTRL_SF_AES_IV_R0_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS))
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/* 0x228 : sf_aes_iv_r0_w2 */
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#define SF_CTRL_SF_AES_IV_R0_W2_OFFSET (0x228)
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#define SF_CTRL_SF_AES_IV_R0_W2 SF_CTRL_SF_AES_IV_R0_W2
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#define SF_CTRL_SF_AES_IV_R0_W2_POS (0U)
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#define SF_CTRL_SF_AES_IV_R0_W2_LEN (32U)
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#define SF_CTRL_SF_AES_IV_R0_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS)
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#define SF_CTRL_SF_AES_IV_R0_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS))
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/* 0x22C : sf_aes_iv_r0_w3 */
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#define SF_CTRL_SF_AES_IV_R0_W3_OFFSET (0x22C)
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#define SF_CTRL_SF_AES_IV_R0_W3 SF_CTRL_SF_AES_IV_R0_W3
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#define SF_CTRL_SF_AES_IV_R0_W3_POS (0U)
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#define SF_CTRL_SF_AES_IV_R0_W3_LEN (32U)
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#define SF_CTRL_SF_AES_IV_R0_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS)
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#define SF_CTRL_SF_AES_IV_R0_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS))
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/* 0x230 : sf_aes_cfg_r0 */
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#define SF_CTRL_SF_AES_CFG_R0_OFFSET (0x230)
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#define SF_CTRL_SF_AES_REGION_R0_END SF_CTRL_SF_AES_REGION_R0_END
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#define SF_CTRL_SF_AES_REGION_R0_END_POS (0U)
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#define SF_CTRL_SF_AES_REGION_R0_END_LEN (14U)
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#define SF_CTRL_SF_AES_REGION_R0_END_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS)
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#define SF_CTRL_SF_AES_REGION_R0_END_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS))
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#define SF_CTRL_SF_AES_REGION_R0_START SF_CTRL_SF_AES_REGION_R0_START
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#define SF_CTRL_SF_AES_REGION_R0_START_POS (14U)
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#define SF_CTRL_SF_AES_REGION_R0_START_LEN (14U)
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#define SF_CTRL_SF_AES_REGION_R0_START_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS)
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#define SF_CTRL_SF_AES_REGION_R0_START_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS))
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#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN
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#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS (29U)
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#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN (1U)
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#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS)
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#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS))
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#define SF_CTRL_SF_AES_REGION_R0_EN SF_CTRL_SF_AES_REGION_R0_EN
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#define SF_CTRL_SF_AES_REGION_R0_EN_POS (30U)
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#define SF_CTRL_SF_AES_REGION_R0_EN_LEN (1U)
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#define SF_CTRL_SF_AES_REGION_R0_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS)
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#define SF_CTRL_SF_AES_REGION_R0_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS))
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#define SF_CTRL_SF_AES_REGION_R0_LOCK SF_CTRL_SF_AES_REGION_R0_LOCK
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#define SF_CTRL_SF_AES_REGION_R0_LOCK_POS (31U)
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#define SF_CTRL_SF_AES_REGION_R0_LOCK_LEN (1U)
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#define SF_CTRL_SF_AES_REGION_R0_LOCK_MSK (((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS)
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#define SF_CTRL_SF_AES_REGION_R0_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS))
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/* 0x300 : sf_aes_key_r1_0 */
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#define SF_CTRL_SF_AES_KEY_R1_0_OFFSET (0x300)
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#define SF_CTRL_SF_AES_KEY_R1_0 SF_CTRL_SF_AES_KEY_R1_0
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#define SF_CTRL_SF_AES_KEY_R1_0_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R1_0_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R1_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS)
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#define SF_CTRL_SF_AES_KEY_R1_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS))
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/* 0x304 : sf_aes_key_r1_1 */
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#define SF_CTRL_SF_AES_KEY_R1_1_OFFSET (0x304)
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#define SF_CTRL_SF_AES_KEY_R1_1 SF_CTRL_SF_AES_KEY_R1_1
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#define SF_CTRL_SF_AES_KEY_R1_1_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R1_1_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R1_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS)
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#define SF_CTRL_SF_AES_KEY_R1_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS))
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/* 0x308 : sf_aes_key_r1_2 */
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#define SF_CTRL_SF_AES_KEY_R1_2_OFFSET (0x308)
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#define SF_CTRL_SF_AES_KEY_R1_2 SF_CTRL_SF_AES_KEY_R1_2
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#define SF_CTRL_SF_AES_KEY_R1_2_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R1_2_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R1_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS)
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#define SF_CTRL_SF_AES_KEY_R1_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS))
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/* 0x30C : sf_aes_key_r1_3 */
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#define SF_CTRL_SF_AES_KEY_R1_3_OFFSET (0x30C)
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#define SF_CTRL_SF_AES_KEY_R1_3 SF_CTRL_SF_AES_KEY_R1_3
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#define SF_CTRL_SF_AES_KEY_R1_3_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R1_3_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R1_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS)
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#define SF_CTRL_SF_AES_KEY_R1_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS))
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/* 0x310 : sf_aes_key_r1_4 */
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#define SF_CTRL_SF_AES_KEY_R1_4_OFFSET (0x310)
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#define SF_CTRL_SF_AES_KEY_R1_4 SF_CTRL_SF_AES_KEY_R1_4
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#define SF_CTRL_SF_AES_KEY_R1_4_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R1_4_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R1_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS)
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#define SF_CTRL_SF_AES_KEY_R1_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS))
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/* 0x314 : sf_aes_key_r1_5 */
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#define SF_CTRL_SF_AES_KEY_R1_5_OFFSET (0x314)
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#define SF_CTRL_SF_AES_KEY_R1_5 SF_CTRL_SF_AES_KEY_R1_5
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#define SF_CTRL_SF_AES_KEY_R1_5_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R1_5_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R1_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS)
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#define SF_CTRL_SF_AES_KEY_R1_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS))
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/* 0x318 : sf_aes_key_r1_6 */
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#define SF_CTRL_SF_AES_KEY_R1_6_OFFSET (0x318)
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#define SF_CTRL_SF_AES_KEY_R1_6 SF_CTRL_SF_AES_KEY_R1_6
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#define SF_CTRL_SF_AES_KEY_R1_6_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R1_6_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R1_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS)
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#define SF_CTRL_SF_AES_KEY_R1_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS))
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/* 0x31C : sf_aes_key_r1_7 */
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#define SF_CTRL_SF_AES_KEY_R1_7_OFFSET (0x31C)
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#define SF_CTRL_SF_AES_KEY_R1_7 SF_CTRL_SF_AES_KEY_R1_7
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#define SF_CTRL_SF_AES_KEY_R1_7_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R1_7_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R1_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS)
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#define SF_CTRL_SF_AES_KEY_R1_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS))
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/* 0x320 : sf_aes_iv_r1_w0 */
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#define SF_CTRL_SF_AES_IV_R1_W0_OFFSET (0x320)
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#define SF_CTRL_SF_AES_IV_R1_W0 SF_CTRL_SF_AES_IV_R1_W0
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#define SF_CTRL_SF_AES_IV_R1_W0_POS (0U)
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#define SF_CTRL_SF_AES_IV_R1_W0_LEN (32U)
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#define SF_CTRL_SF_AES_IV_R1_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS)
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#define SF_CTRL_SF_AES_IV_R1_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS))
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/* 0x324 : sf_aes_iv_r1_w1 */
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#define SF_CTRL_SF_AES_IV_R1_W1_OFFSET (0x324)
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#define SF_CTRL_SF_AES_IV_R1_W1 SF_CTRL_SF_AES_IV_R1_W1
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#define SF_CTRL_SF_AES_IV_R1_W1_POS (0U)
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#define SF_CTRL_SF_AES_IV_R1_W1_LEN (32U)
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#define SF_CTRL_SF_AES_IV_R1_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS)
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#define SF_CTRL_SF_AES_IV_R1_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS))
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/* 0x328 : sf_aes_iv_r1_w2 */
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#define SF_CTRL_SF_AES_IV_R1_W2_OFFSET (0x328)
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#define SF_CTRL_SF_AES_IV_R1_W2 SF_CTRL_SF_AES_IV_R1_W2
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#define SF_CTRL_SF_AES_IV_R1_W2_POS (0U)
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#define SF_CTRL_SF_AES_IV_R1_W2_LEN (32U)
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#define SF_CTRL_SF_AES_IV_R1_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS)
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#define SF_CTRL_SF_AES_IV_R1_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS))
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/* 0x32C : sf_aes_iv_r1_w3 */
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#define SF_CTRL_SF_AES_IV_R1_W3_OFFSET (0x32C)
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#define SF_CTRL_SF_AES_IV_R1_W3 SF_CTRL_SF_AES_IV_R1_W3
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#define SF_CTRL_SF_AES_IV_R1_W3_POS (0U)
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#define SF_CTRL_SF_AES_IV_R1_W3_LEN (32U)
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#define SF_CTRL_SF_AES_IV_R1_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS)
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#define SF_CTRL_SF_AES_IV_R1_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS))
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/* 0x330 : sf_aes_r1 */
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#define SF_CTRL_SF_AES_R1_OFFSET (0x330)
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#define SF_CTRL_SF_AES_R1_END SF_CTRL_SF_AES_R1_END
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#define SF_CTRL_SF_AES_R1_END_POS (0U)
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#define SF_CTRL_SF_AES_R1_END_LEN (14U)
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#define SF_CTRL_SF_AES_R1_END_MSK (((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS)
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#define SF_CTRL_SF_AES_R1_END_UMSK (~(((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS))
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#define SF_CTRL_SF_AES_R1_START SF_CTRL_SF_AES_R1_START
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#define SF_CTRL_SF_AES_R1_START_POS (14U)
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#define SF_CTRL_SF_AES_R1_START_LEN (14U)
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#define SF_CTRL_SF_AES_R1_START_MSK (((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS)
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#define SF_CTRL_SF_AES_R1_START_UMSK (~(((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS))
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#define SF_CTRL_SF_AES_R1_HW_KEY_EN SF_CTRL_SF_AES_R1_HW_KEY_EN
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#define SF_CTRL_SF_AES_R1_HW_KEY_EN_POS (29U)
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#define SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN (1U)
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#define SF_CTRL_SF_AES_R1_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS)
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#define SF_CTRL_SF_AES_R1_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS))
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#define SF_CTRL_SF_AES_R1_EN SF_CTRL_SF_AES_R1_EN
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#define SF_CTRL_SF_AES_R1_EN_POS (30U)
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#define SF_CTRL_SF_AES_R1_EN_LEN (1U)
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#define SF_CTRL_SF_AES_R1_EN_MSK (((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS)
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#define SF_CTRL_SF_AES_R1_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS))
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#define SF_CTRL_SF_AES_R1_LOCK SF_CTRL_SF_AES_R1_LOCK
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#define SF_CTRL_SF_AES_R1_LOCK_POS (31U)
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#define SF_CTRL_SF_AES_R1_LOCK_LEN (1U)
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#define SF_CTRL_SF_AES_R1_LOCK_MSK (((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS)
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#define SF_CTRL_SF_AES_R1_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS))
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/* 0x400 : sf_aes_key_r2_0 */
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#define SF_CTRL_SF_AES_KEY_R2_0_OFFSET (0x400)
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#define SF_CTRL_SF_AES_KEY_R2_0 SF_CTRL_SF_AES_KEY_R2_0
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#define SF_CTRL_SF_AES_KEY_R2_0_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R2_0_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R2_0_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS)
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#define SF_CTRL_SF_AES_KEY_R2_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS))
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/* 0x404 : sf_aes_key_r2_1 */
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#define SF_CTRL_SF_AES_KEY_R2_1_OFFSET (0x404)
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#define SF_CTRL_SF_AES_KEY_R2_1 SF_CTRL_SF_AES_KEY_R2_1
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#define SF_CTRL_SF_AES_KEY_R2_1_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R2_1_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R2_1_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS)
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#define SF_CTRL_SF_AES_KEY_R2_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS))
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/* 0x408 : sf_aes_key_r2_2 */
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#define SF_CTRL_SF_AES_KEY_R2_2_OFFSET (0x408)
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#define SF_CTRL_SF_AES_KEY_R2_2 SF_CTRL_SF_AES_KEY_R2_2
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#define SF_CTRL_SF_AES_KEY_R2_2_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R2_2_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R2_2_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS)
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#define SF_CTRL_SF_AES_KEY_R2_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS))
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/* 0x40C : sf_aes_key_r2_3 */
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#define SF_CTRL_SF_AES_KEY_R2_3_OFFSET (0x40C)
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#define SF_CTRL_SF_AES_KEY_R2_3 SF_CTRL_SF_AES_KEY_R2_3
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#define SF_CTRL_SF_AES_KEY_R2_3_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R2_3_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R2_3_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS)
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#define SF_CTRL_SF_AES_KEY_R2_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS))
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/* 0x410 : sf_aes_key_r2_4 */
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#define SF_CTRL_SF_AES_KEY_R2_4_OFFSET (0x410)
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#define SF_CTRL_SF_AES_KEY_R2_4 SF_CTRL_SF_AES_KEY_R2_4
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#define SF_CTRL_SF_AES_KEY_R2_4_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R2_4_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R2_4_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS)
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#define SF_CTRL_SF_AES_KEY_R2_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS))
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/* 0x414 : sf_aes_key_r2_5 */
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#define SF_CTRL_SF_AES_KEY_R2_5_OFFSET (0x414)
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#define SF_CTRL_SF_AES_KEY_R2_5 SF_CTRL_SF_AES_KEY_R2_5
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#define SF_CTRL_SF_AES_KEY_R2_5_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R2_5_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R2_5_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS)
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#define SF_CTRL_SF_AES_KEY_R2_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS))
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/* 0x418 : sf_aes_key_r2_6 */
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#define SF_CTRL_SF_AES_KEY_R2_6_OFFSET (0x418)
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#define SF_CTRL_SF_AES_KEY_R2_6 SF_CTRL_SF_AES_KEY_R2_6
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#define SF_CTRL_SF_AES_KEY_R2_6_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R2_6_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R2_6_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS)
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#define SF_CTRL_SF_AES_KEY_R2_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS))
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/* 0x41C : sf_aes_key_r2_7 */
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#define SF_CTRL_SF_AES_KEY_R2_7_OFFSET (0x41C)
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#define SF_CTRL_SF_AES_KEY_R2_7 SF_CTRL_SF_AES_KEY_R2_7
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#define SF_CTRL_SF_AES_KEY_R2_7_POS (0U)
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#define SF_CTRL_SF_AES_KEY_R2_7_LEN (32U)
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#define SF_CTRL_SF_AES_KEY_R2_7_MSK (((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS)
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#define SF_CTRL_SF_AES_KEY_R2_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS))
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/* 0x420 : sf_aes_iv_r2_w0 */
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#define SF_CTRL_SF_AES_IV_R2_W0_OFFSET (0x420)
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#define SF_CTRL_SF_AES_IV_R2_W0 SF_CTRL_SF_AES_IV_R2_W0
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#define SF_CTRL_SF_AES_IV_R2_W0_POS (0U)
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#define SF_CTRL_SF_AES_IV_R2_W0_LEN (32U)
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#define SF_CTRL_SF_AES_IV_R2_W0_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS)
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#define SF_CTRL_SF_AES_IV_R2_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS))
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/* 0x424 : sf_aes_iv_r2_w1 */
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#define SF_CTRL_SF_AES_IV_R2_W1_OFFSET (0x424)
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#define SF_CTRL_SF_AES_IV_R2_W1 SF_CTRL_SF_AES_IV_R2_W1
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#define SF_CTRL_SF_AES_IV_R2_W1_POS (0U)
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#define SF_CTRL_SF_AES_IV_R2_W1_LEN (32U)
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#define SF_CTRL_SF_AES_IV_R2_W1_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS)
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#define SF_CTRL_SF_AES_IV_R2_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS))
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/* 0x428 : sf_aes_iv_r2_w2 */
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#define SF_CTRL_SF_AES_IV_R2_W2_OFFSET (0x428)
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#define SF_CTRL_SF_AES_IV_R2_W2 SF_CTRL_SF_AES_IV_R2_W2
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#define SF_CTRL_SF_AES_IV_R2_W2_POS (0U)
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#define SF_CTRL_SF_AES_IV_R2_W2_LEN (32U)
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#define SF_CTRL_SF_AES_IV_R2_W2_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS)
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#define SF_CTRL_SF_AES_IV_R2_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS))
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/* 0x42C : sf_aes_iv_r2_w3 */
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#define SF_CTRL_SF_AES_IV_R2_W3_OFFSET (0x42C)
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#define SF_CTRL_SF_AES_IV_R2_W3 SF_CTRL_SF_AES_IV_R2_W3
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#define SF_CTRL_SF_AES_IV_R2_W3_POS (0U)
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#define SF_CTRL_SF_AES_IV_R2_W3_LEN (32U)
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#define SF_CTRL_SF_AES_IV_R2_W3_MSK (((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS)
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#define SF_CTRL_SF_AES_IV_R2_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS))
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/* 0x430 : sf_aes_r2 */
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#define SF_CTRL_SF_AES_R2_OFFSET (0x430)
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#define SF_CTRL_SF_AES_R2_END SF_CTRL_SF_AES_R2_END
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#define SF_CTRL_SF_AES_R2_END_POS (0U)
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#define SF_CTRL_SF_AES_R2_END_LEN (14U)
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#define SF_CTRL_SF_AES_R2_END_MSK (((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS)
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#define SF_CTRL_SF_AES_R2_END_UMSK (~(((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS))
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#define SF_CTRL_SF_AES_R2_START SF_CTRL_SF_AES_R2_START
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#define SF_CTRL_SF_AES_R2_START_POS (14U)
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#define SF_CTRL_SF_AES_R2_START_LEN (14U)
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#define SF_CTRL_SF_AES_R2_START_MSK (((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS)
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#define SF_CTRL_SF_AES_R2_START_UMSK (~(((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS))
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#define SF_CTRL_SF_AES_R2_HW_KEY_EN SF_CTRL_SF_AES_R2_HW_KEY_EN
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#define SF_CTRL_SF_AES_R2_HW_KEY_EN_POS (29U)
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#define SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN (1U)
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#define SF_CTRL_SF_AES_R2_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS)
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#define SF_CTRL_SF_AES_R2_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS))
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#define SF_CTRL_SF_AES_R2_EN SF_CTRL_SF_AES_R2_EN
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#define SF_CTRL_SF_AES_R2_EN_POS (30U)
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#define SF_CTRL_SF_AES_R2_EN_LEN (1U)
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#define SF_CTRL_SF_AES_R2_EN_MSK (((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS)
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#define SF_CTRL_SF_AES_R2_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS))
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#define SF_CTRL_SF_AES_R2_LOCK SF_CTRL_SF_AES_R2_LOCK
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#define SF_CTRL_SF_AES_R2_LOCK_POS (31U)
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#define SF_CTRL_SF_AES_R2_LOCK_LEN (1U)
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#define SF_CTRL_SF_AES_R2_LOCK_MSK (((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS)
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#define SF_CTRL_SF_AES_R2_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS))
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/* 0x434 : sf_id0_offset */
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#define SF_CTRL_SF_ID0_OFFSET_OFFSET (0x434)
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#define SF_CTRL_SF_ID0_OFFSET SF_CTRL_SF_ID0_OFFSET
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#define SF_CTRL_SF_ID0_OFFSET_POS (0U)
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#define SF_CTRL_SF_ID0_OFFSET_LEN (24U)
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#define SF_CTRL_SF_ID0_OFFSET_MSK (((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS)
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#define SF_CTRL_SF_ID0_OFFSET_UMSK (~(((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS))
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/* 0x438 : sf_id1_offset */
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#define SF_CTRL_SF_ID1_OFFSET_OFFSET (0x438)
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#define SF_CTRL_SF_ID1_OFFSET SF_CTRL_SF_ID1_OFFSET
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#define SF_CTRL_SF_ID1_OFFSET_POS (0U)
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#define SF_CTRL_SF_ID1_OFFSET_LEN (24U)
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#define SF_CTRL_SF_ID1_OFFSET_MSK (((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS)
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#define SF_CTRL_SF_ID1_OFFSET_UMSK (~(((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS))
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/* 0x43C : sf_bk2_id0_offset */
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#define SF_CTRL_SF_BK2_ID0_OFFSET_OFFSET (0x43C)
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#define SF_CTRL_SF_BK2_ID0_OFFSET SF_CTRL_SF_BK2_ID0_OFFSET
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#define SF_CTRL_SF_BK2_ID0_OFFSET_POS (0U)
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#define SF_CTRL_SF_BK2_ID0_OFFSET_LEN (24U)
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#define SF_CTRL_SF_BK2_ID0_OFFSET_MSK (((1U << SF_CTRL_SF_BK2_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID0_OFFSET_POS)
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#define SF_CTRL_SF_BK2_ID0_OFFSET_UMSK (~(((1U << SF_CTRL_SF_BK2_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID0_OFFSET_POS))
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|
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/* 0x440 : sf_bk2_id1_offset */
|
|
#define SF_CTRL_SF_BK2_ID1_OFFSET_OFFSET (0x440)
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|
#define SF_CTRL_SF_BK2_ID1_OFFSET SF_CTRL_SF_BK2_ID1_OFFSET
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|
#define SF_CTRL_SF_BK2_ID1_OFFSET_POS (0U)
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#define SF_CTRL_SF_BK2_ID1_OFFSET_LEN (24U)
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|
#define SF_CTRL_SF_BK2_ID1_OFFSET_MSK (((1U << SF_CTRL_SF_BK2_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID1_OFFSET_POS)
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|
#define SF_CTRL_SF_BK2_ID1_OFFSET_UMSK (~(((1U << SF_CTRL_SF_BK2_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID1_OFFSET_POS))
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|
|
|
struct sf_ctrl_reg {
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|
/* 0x0 : sf_ctrl_0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
|
|
uint32_t sf_clk_sf_rx_inv_sel : 1; /* [ 2], r/w, 0x1 */
|
|
uint32_t sf_clk_out_gate_en : 1; /* [ 3], r/w, 0x1 */
|
|
uint32_t sf_clk_out_inv_sel : 1; /* [ 4], r/w, 0x1 */
|
|
uint32_t sf_clk_sahb_sram_sel : 1; /* [ 5], r/w, 0x0 */
|
|
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
|
|
uint32_t sf_if_read_dly_n : 3; /* [10: 8], r/w, 0x0 */
|
|
uint32_t sf_if_read_dly_en : 1; /* [ 11], r/w, 0x0 */
|
|
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
|
|
uint32_t sf_if_int : 1; /* [ 16], r, 0x0 */
|
|
uint32_t sf_if_int_clr : 1; /* [ 17], r/w, 0x1 */
|
|
uint32_t sf_if_int_set : 1; /* [ 18], r/w, 0x0 */
|
|
uint32_t sf_aes_dly_mode : 1; /* [ 19], r/w, 0x0 */
|
|
uint32_t sf_aes_dout_endian : 1; /* [ 20], r/w, 0x1 */
|
|
uint32_t sf_aes_ctr_plus_en : 1; /* [ 21], r/w, 0x0 */
|
|
uint32_t sf_aes_key_endian : 1; /* [ 22], r/w, 0x1 */
|
|
uint32_t sf_aes_iv_endian : 1; /* [ 23], r/w, 0x1 */
|
|
uint32_t sf_id : 8; /* [31:24], r/w, 0x1a */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_ctrl_0;
|
|
|
|
/* 0x4 : sf_ctrl_1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_sr_pat_mask : 8; /* [ 7: 0], r/w, 0x0 */
|
|
uint32_t sf_if_sr_pat : 8; /* [15: 8], r/w, 0x0 */
|
|
uint32_t sf_if_sr_int : 1; /* [ 16], r, 0x0 */
|
|
uint32_t sf_if_sr_int_en : 1; /* [ 17], r/w, 0x0 */
|
|
uint32_t sf_if_sr_int_set : 1; /* [ 18], r/w, 0x0 */
|
|
uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */
|
|
uint32_t sf_if_0_ack_lat : 3; /* [22:20], r/w, 0x6 */
|
|
uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */
|
|
uint32_t sf_if_reg_hold : 1; /* [ 24], r/w, 0x1 */
|
|
uint32_t sf_if_reg_wp : 1; /* [ 25], r/w, 0x1 */
|
|
uint32_t sf_ahb2sif_stopped : 1; /* [ 26], r, 0x0 */
|
|
uint32_t sf_ahb2sif_stop : 1; /* [ 27], r/w, 0x0 */
|
|
uint32_t sf_if_fn_sel : 1; /* [ 28], r/w, 0x1 */
|
|
uint32_t sf_if_en : 1; /* [ 29], r/w, 0x1 */
|
|
uint32_t sf_ahb2sif_en : 1; /* [ 30], r/w, 0x1 */
|
|
uint32_t sf_ahb2sram_en : 1; /* [ 31], r/w, 0x1 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_ctrl_1;
|
|
|
|
/* 0x8 : sf_if_sahb_0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_busy : 1; /* [ 0], r, 0x0 */
|
|
uint32_t sf_if_0_trig : 1; /* [ 1], r/w, 0x0 */
|
|
uint32_t sf_if_0_dat_byte : 10; /* [11: 2], r/w, 0x0 */
|
|
uint32_t sf_if_0_dmy_byte : 5; /* [16:12], r/w, 0x0 */
|
|
uint32_t sf_if_0_adr_byte : 3; /* [19:17], r/w, 0x0 */
|
|
uint32_t sf_if_0_cmd_byte : 3; /* [22:20], r/w, 0x0 */
|
|
uint32_t sf_if_0_dat_rw : 1; /* [ 23], r/w, 0x0 */
|
|
uint32_t sf_if_0_dat_en : 1; /* [ 24], r/w, 0x0 */
|
|
uint32_t sf_if_0_dmy_en : 1; /* [ 25], r/w, 0x0 */
|
|
uint32_t sf_if_0_adr_en : 1; /* [ 26], r/w, 0x0 */
|
|
uint32_t sf_if_0_cmd_en : 1; /* [ 27], r/w, 0x0 */
|
|
uint32_t sf_if_0_spi_mode : 3; /* [30:28], r/w, 0x0 */
|
|
uint32_t sf_if_0_qpi_mode_en : 1; /* [ 31], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_sahb_0;
|
|
|
|
/* 0xC : sf_if_sahb_1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_0_cmd_buf_0 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_sahb_1;
|
|
|
|
/* 0x10 : sf_if_sahb_2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_0_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_sahb_2;
|
|
|
|
/* 0x14 : sf_if_iahb_0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */
|
|
uint32_t sf_if_1_dmy_byte : 5; /* [16:12], r/w, 0x0 */
|
|
uint32_t sf_if_1_adr_byte : 3; /* [19:17], r/w, 0x2 */
|
|
uint32_t sf_if_1_cmd_byte : 3; /* [22:20], r/w, 0x0 */
|
|
uint32_t sf_if_1_dat_rw : 1; /* [ 23], r/w, 0x0 */
|
|
uint32_t sf_if_1_dat_en : 1; /* [ 24], r/w, 0x1 */
|
|
uint32_t sf_if_1_dmy_en : 1; /* [ 25], r/w, 0x0 */
|
|
uint32_t sf_if_1_adr_en : 1; /* [ 26], r/w, 0x1 */
|
|
uint32_t sf_if_1_cmd_en : 1; /* [ 27], r/w, 0x1 */
|
|
uint32_t sf_if_1_spi_mode : 3; /* [30:28], r/w, 0x0 */
|
|
uint32_t sf_if_1_qpi_mode_en : 1; /* [ 31], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_iahb_0;
|
|
|
|
/* 0x18 : sf_if_iahb_1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_1_cmd_buf_0 : 32; /* [31: 0], r/w, 0x3000000 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_iahb_1;
|
|
|
|
/* 0x1C : sf_if_iahb_2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_1_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_iahb_2;
|
|
|
|
/* 0x20 : sf_if_status_0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_status_0 : 32; /* [31: 0], r, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_status_0;
|
|
|
|
/* 0x24 : sf_if_status_1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_status_1 : 32; /* [31: 0], r, 0x20000000 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_status_1;
|
|
|
|
/* 0x28 : sf_aes */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_en : 1; /* [ 0], r/w, 0x0 */
|
|
uint32_t sf_aes_mode : 2; /* [ 2: 1], r/w, 0x0 */
|
|
uint32_t sf_aes_pref_trig : 1; /* [ 3], r/w, 0x0 */
|
|
uint32_t sf_aes_pref_busy : 1; /* [ 4], r, 0x0 */
|
|
uint32_t sf_aes_status : 27; /* [31: 5], r, 0x2 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes;
|
|
|
|
/* 0x2C : sf_ahb2sif_status */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_ahb2sif_status : 32; /* [31: 0], r, 0x10000003 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_ahb2sif_status;
|
|
|
|
/* 0x30 : sf_if_io_dly_0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t sf_cs2_dly_sel : 2; /* [ 3: 2], r/w, 0x0 */
|
|
uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
|
|
uint32_t sf_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */
|
|
uint32_t sf_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */
|
|
uint32_t sf_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */
|
|
uint32_t sf_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_io_dly_0;
|
|
|
|
/* 0x34 : sf_if_io_dly_1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
|
|
uint32_t sf_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
|
|
uint32_t sf_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
|
|
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_io_dly_1;
|
|
|
|
/* 0x38 : sf_if_io_dly_2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
|
|
uint32_t sf_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
|
|
uint32_t sf_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
|
|
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_io_dly_2;
|
|
|
|
/* 0x3C : sf_if_io_dly_3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
|
|
uint32_t sf_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
|
|
uint32_t sf_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
|
|
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_io_dly_3;
|
|
|
|
/* 0x40 : sf_if_io_dly_4 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
|
|
uint32_t sf_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
|
|
uint32_t sf_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
|
|
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_io_dly_4;
|
|
|
|
/* 0x44 : sf_reserved */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_reserved : 32; /* [31: 0], r/w, 0xffff */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_reserved;
|
|
|
|
/* 0x48 : sf2_if_io_dly_0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf2_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t sf2_cs2_dly_sel : 2; /* [ 3: 2], r/w, 0x0 */
|
|
uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
|
|
uint32_t sf2_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */
|
|
uint32_t sf2_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */
|
|
uint32_t sf2_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */
|
|
uint32_t sf2_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf2_if_io_dly_0;
|
|
|
|
/* 0x4C : sf2_if_io_dly_1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf2_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
|
|
uint32_t sf2_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
|
|
uint32_t sf2_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
|
|
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf2_if_io_dly_1;
|
|
|
|
/* 0x50 : sf2_if_io_dly_2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf2_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
|
|
uint32_t sf2_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
|
|
uint32_t sf2_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
|
|
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf2_if_io_dly_2;
|
|
|
|
/* 0x54 : sf2_if_io_dly_3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf2_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
|
|
uint32_t sf2_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
|
|
uint32_t sf2_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
|
|
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf2_if_io_dly_3;
|
|
|
|
/* 0x58 : sf2_if_io_dly_4 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf2_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
|
|
uint32_t sf2_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
|
|
uint32_t sf2_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
|
|
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf2_if_io_dly_4;
|
|
|
|
/* 0x5C : sf3_if_io_dly_0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf3_cs_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t sf3_cs2_dly_sel : 2; /* [ 3: 2], r/w, 0x0 */
|
|
uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
|
|
uint32_t sf3_clk_out_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_25 : 16; /* [25:10], rsvd, 0x0 */
|
|
uint32_t sf3_dqs_oe_dly_sel : 2; /* [27:26], r/w, 0x0 */
|
|
uint32_t sf3_dqs_di_dly_sel : 2; /* [29:28], r/w, 0x0 */
|
|
uint32_t sf3_dqs_do_dly_sel : 2; /* [31:30], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf3_if_io_dly_0;
|
|
|
|
/* 0x60 : sf3_if_io_dly_1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf3_io_0_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
|
|
uint32_t sf3_io_0_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
|
|
uint32_t sf3_io_0_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
|
|
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf3_if_io_dly_1;
|
|
|
|
/* 0x64 : sf3_if_io_dly_2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf3_io_1_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
|
|
uint32_t sf3_io_1_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
|
|
uint32_t sf3_io_1_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
|
|
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf3_if_io_dly_2;
|
|
|
|
/* 0x68 : sf3_if_io_dly_3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf3_io_2_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
|
|
uint32_t sf3_io_2_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
|
|
uint32_t sf3_io_2_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
|
|
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf3_if_io_dly_3;
|
|
|
|
/* 0x6C : sf3_if_io_dly_4 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf3_io_3_oe_dly_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */
|
|
uint32_t sf3_io_3_di_dly_sel : 2; /* [ 9: 8], r/w, 0x0 */
|
|
uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */
|
|
uint32_t sf3_io_3_do_dly_sel : 2; /* [17:16], r/w, 0x0 */
|
|
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf3_if_io_dly_4;
|
|
|
|
/* 0x70 : sf_ctrl_2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_pad_sel : 2; /* [ 1: 0], r/w, 0x0 */
|
|
uint32_t reserved_2 : 1; /* [ 2], rsvd, 0x0 */
|
|
uint32_t sf_if_pad_sel_lock : 1; /* [ 3], r/w, 0x0 */
|
|
uint32_t sf_if_dtr_en : 1; /* [ 4], r/w, 0x0 */
|
|
uint32_t sf_if_dqs_en : 1; /* [ 5], r/w, 0x0 */
|
|
uint32_t reserved_6_27 : 22; /* [27: 6], rsvd, 0x0 */
|
|
uint32_t sf_if_bk_swap : 1; /* [ 28], r/w, 0x0 */
|
|
uint32_t sf_if_bk2_mode : 1; /* [ 29], r/w, 0x0 */
|
|
uint32_t sf_if_bk2_en : 1; /* [ 30], r/w, 0x0 */
|
|
uint32_t sf_if_0_bk_sel : 1; /* [ 31], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_ctrl_2;
|
|
|
|
/* 0x74 : sf_ctrl_3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_cmds_wrap_len : 4; /* [ 3: 0], r/w, 0x6 */
|
|
uint32_t sf_cmds_en : 1; /* [ 4], r/w, 0x0 */
|
|
uint32_t sf_cmds_bt_dly : 3; /* [ 7: 5], r/w, 0x2 */
|
|
uint32_t sf_cmds_bt_en : 1; /* [ 8], r/w, 0x0 */
|
|
uint32_t sf_cmds_wrap_q_ini : 1; /* [ 9], r/w, 0x0 */
|
|
uint32_t sf_cmds_wrap_mode : 1; /* [ 10], r/w, 0x0 */
|
|
uint32_t sf_cmds_wrap_q : 1; /* [ 11], r, 0x0 */
|
|
uint32_t reserved_12_28 : 17; /* [28:12], rsvd, 0x0 */
|
|
uint32_t sf_if_1_ack_lat : 3; /* [31:29], r/w, 0x1 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_ctrl_3;
|
|
|
|
/* 0x78 : sf_if_iahb_3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */
|
|
uint32_t sf_if_2_dmy_byte : 5; /* [16:12], r/w, 0x0 */
|
|
uint32_t sf_if_2_adr_byte : 3; /* [19:17], r/w, 0x2 */
|
|
uint32_t sf_if_2_cmd_byte : 3; /* [22:20], r/w, 0x0 */
|
|
uint32_t sf_if_2_dat_rw : 1; /* [ 23], r/w, 0x1 */
|
|
uint32_t sf_if_2_dat_en : 1; /* [ 24], r/w, 0x1 */
|
|
uint32_t sf_if_2_dmy_en : 1; /* [ 25], r/w, 0x0 */
|
|
uint32_t sf_if_2_adr_en : 1; /* [ 26], r/w, 0x1 */
|
|
uint32_t sf_if_2_cmd_en : 1; /* [ 27], r/w, 0x1 */
|
|
uint32_t sf_if_2_spi_mode : 3; /* [30:28], r/w, 0x0 */
|
|
uint32_t sf_if_2_qpi_mode_en : 1; /* [ 31], r/w, 0x1 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_iahb_3;
|
|
|
|
/* 0x7C : sf_if_iahb_4 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_2_cmd_buf_0 : 32; /* [31: 0], r/w, 0x38000000 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_iahb_4;
|
|
|
|
/* 0x80 : sf_if_iahb_5 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_2_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_iahb_5;
|
|
|
|
/* 0x84 : sf_if_iahb_6 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t reserved_0_16 : 17; /* [16: 0], rsvd, 0x0 */
|
|
uint32_t sf_if_3_adr_byte : 3; /* [19:17], r/w, 0x0 */
|
|
uint32_t sf_if_3_cmd_byte : 3; /* [22:20], r/w, 0x0 */
|
|
uint32_t reserved_23_25 : 3; /* [25:23], rsvd, 0x0 */
|
|
uint32_t sf_if_3_adr_en : 1; /* [ 26], r/w, 0x0 */
|
|
uint32_t sf_if_3_cmd_en : 1; /* [ 27], r/w, 0x1 */
|
|
uint32_t sf_if_3_spi_mode : 3; /* [30:28], r/w, 0x0 */
|
|
uint32_t sf_if_3_qpi_mode_en : 1; /* [ 31], r/w, 0x1 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_iahb_6;
|
|
|
|
/* 0x88 : sf_if_iahb_7 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_3_cmd_buf_0 : 32; /* [31: 0], r/w, 0xc0000000L */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_iahb_7;
|
|
|
|
/* 0x8C : sf_if_iahb_8 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_3_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_iahb_8;
|
|
|
|
/* 0x90 : sf_if_iahb_9 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */
|
|
uint32_t sf_if_4_dmy_byte : 5; /* [16:12], r/w, 0x2 */
|
|
uint32_t sf_if_4_adr_byte : 3; /* [19:17], r/w, 0x2 */
|
|
uint32_t sf_if_4_cmd_byte : 3; /* [22:20], r/w, 0x0 */
|
|
uint32_t sf_if_4_dat_rw : 1; /* [ 23], r/w, 0x0 */
|
|
uint32_t sf_if_4_dat_en : 1; /* [ 24], r/w, 0x1 */
|
|
uint32_t sf_if_4_dmy_en : 1; /* [ 25], r/w, 0x1 */
|
|
uint32_t sf_if_4_adr_en : 1; /* [ 26], r/w, 0x1 */
|
|
uint32_t sf_if_4_cmd_en : 1; /* [ 27], r/w, 0x1 */
|
|
uint32_t sf_if_4_spi_mode : 3; /* [30:28], r/w, 0x0 */
|
|
uint32_t sf_if_4_qpi_mode_en : 1; /* [ 31], r/w, 0x1 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_iahb_9;
|
|
|
|
/* 0x94 : sf_if_iahb_10 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_4_cmd_buf_0 : 32; /* [31: 0], r/w, 0xeb000000L */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_iahb_10;
|
|
|
|
/* 0x98 : sf_if_iahb_11 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_if_4_cmd_buf_1 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_iahb_11;
|
|
|
|
/* 0x9C : sf_if_iahb_12 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */
|
|
uint32_t sf2_clk_sf_rx_inv_sel : 1; /* [ 2], r/w, 0x0 */
|
|
uint32_t sf2_clk_sf_rx_inv_src : 1; /* [ 3], r/w, 0x0 */
|
|
uint32_t sf2_clk_out_inv_sel : 1; /* [ 4], r/w, 0x1 */
|
|
uint32_t sf3_clk_out_inv_sel : 1; /* [ 5], r/w, 0x1 */
|
|
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
|
|
uint32_t sf2_if_read_dly_n : 3; /* [10: 8], r/w, 0x0 */
|
|
uint32_t sf2_if_read_dly_en : 1; /* [ 11], r/w, 0x0 */
|
|
uint32_t sf2_if_read_dly_src : 1; /* [ 12], r/w, 0x0 */
|
|
uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_if_iahb_12;
|
|
|
|
/* 0xa0 reserved */
|
|
uint8_t RESERVED0xa0[96];
|
|
|
|
/* 0x100 : sf_ctrl_prot_en_rd */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_ctrl_prot_en_rd : 1; /* [ 0], r, 0x1 */
|
|
uint32_t sf_ctrl_id0_en_rd : 1; /* [ 1], r, 0x1 */
|
|
uint32_t sf_ctrl_id1_en_rd : 1; /* [ 2], r, 0x1 */
|
|
uint32_t reserved_3_29 : 27; /* [29: 3], rsvd, 0x0 */
|
|
uint32_t sf_if_0_trig_wr_lock : 1; /* [ 30], r, 0x0 */
|
|
uint32_t sf_dbg_dis : 1; /* [ 31], r, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_ctrl_prot_en_rd;
|
|
|
|
/* 0x104 : sf_ctrl_prot_en */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_ctrl_prot_en : 1; /* [ 0], r/w, 0x1 */
|
|
uint32_t sf_ctrl_id0_en : 1; /* [ 1], r/w, 0x1 */
|
|
uint32_t sf_ctrl_id1_en : 1; /* [ 2], r/w, 0x1 */
|
|
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_ctrl_prot_en;
|
|
|
|
/* 0x108 reserved */
|
|
uint8_t RESERVED0x108[248];
|
|
|
|
/* 0x200 : sf_aes_key_r0_0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r0_0 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r0_0;
|
|
|
|
/* 0x204 : sf_aes_key_r0_1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r0_1 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r0_1;
|
|
|
|
/* 0x208 : sf_aes_key_r0_2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r0_2 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r0_2;
|
|
|
|
/* 0x20C : sf_aes_key_r0_3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r0_3 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r0_3;
|
|
|
|
/* 0x210 : sf_aes_key_r0_4 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r0_4 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r0_4;
|
|
|
|
/* 0x214 : sf_aes_key_r0_5 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r0_5 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r0_5;
|
|
|
|
/* 0x218 : sf_aes_key_r0_6 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r0_6 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r0_6;
|
|
|
|
/* 0x21C : sf_aes_key_r0_7 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r0_7 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r0_7;
|
|
|
|
/* 0x220 : sf_aes_iv_r0_w0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_r0_w0 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_r0_w0;
|
|
|
|
/* 0x224 : sf_aes_iv_r0_w1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_r0_w1 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_r0_w1;
|
|
|
|
/* 0x228 : sf_aes_iv_r0_w2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_r0_w2 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_r0_w2;
|
|
|
|
/* 0x22C : sf_aes_iv_r0_w3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_r0_w3 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_r0_w3;
|
|
|
|
/* 0x230 : sf_aes_cfg_r0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_region_r0_end : 14; /* [13: 0], r/w, 0x3fff */
|
|
uint32_t sf_aes_region_r0_start : 14; /* [27:14], r/w, 0x0 */
|
|
uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */
|
|
uint32_t sf_aes_region_r0_hw_key_en : 1; /* [ 29], r/w, 0x0 */
|
|
uint32_t sf_aes_region_r0_en : 1; /* [ 30], r/w, 0x0 */
|
|
uint32_t sf_aes_region_r0_lock : 1; /* [ 31], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_cfg_r0;
|
|
|
|
/* 0x234 reserved */
|
|
uint8_t RESERVED0x234[204];
|
|
|
|
/* 0x300 : sf_aes_key_r1_0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r1_0 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r1_0;
|
|
|
|
/* 0x304 : sf_aes_key_r1_1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r1_1 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r1_1;
|
|
|
|
/* 0x308 : sf_aes_key_r1_2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r1_2 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r1_2;
|
|
|
|
/* 0x30C : sf_aes_key_r1_3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r1_3 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r1_3;
|
|
|
|
/* 0x310 : sf_aes_key_r1_4 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r1_4 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r1_4;
|
|
|
|
/* 0x314 : sf_aes_key_r1_5 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r1_5 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r1_5;
|
|
|
|
/* 0x318 : sf_aes_key_r1_6 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r1_6 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r1_6;
|
|
|
|
/* 0x31C : sf_aes_key_r1_7 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r1_7 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r1_7;
|
|
|
|
/* 0x320 : sf_aes_iv_r1_w0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_r1_w0 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_r1_w0;
|
|
|
|
/* 0x324 : sf_aes_iv_r1_w1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_r1_w1 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_r1_w1;
|
|
|
|
/* 0x328 : sf_aes_iv_r1_w2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_r1_w2 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_r1_w2;
|
|
|
|
/* 0x32C : sf_aes_iv_r1_w3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_r1_w3 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_r1_w3;
|
|
|
|
/* 0x330 : sf_aes_r1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_r1_end : 14; /* [13: 0], r/w, 0x3fff */
|
|
uint32_t sf_aes_r1_start : 14; /* [27:14], r/w, 0x0 */
|
|
uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */
|
|
uint32_t sf_aes_r1_hw_key_en : 1; /* [ 29], r/w, 0x0 */
|
|
uint32_t sf_aes_r1_en : 1; /* [ 30], r/w, 0x0 */
|
|
uint32_t sf_aes_r1_lock : 1; /* [ 31], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_r1;
|
|
|
|
/* 0x334 reserved */
|
|
uint8_t RESERVED0x334[204];
|
|
|
|
/* 0x400 : sf_aes_key_r2_0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r2_0 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r2_0;
|
|
|
|
/* 0x404 : sf_aes_key_r2_1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r2_1 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r2_1;
|
|
|
|
/* 0x408 : sf_aes_key_r2_2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r2_2 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r2_2;
|
|
|
|
/* 0x40C : sf_aes_key_r2_3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r2_3 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r2_3;
|
|
|
|
/* 0x410 : sf_aes_key_r2_4 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r2_4 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r2_4;
|
|
|
|
/* 0x414 : sf_aes_key_r2_5 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r2_5 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r2_5;
|
|
|
|
/* 0x418 : sf_aes_key_r2_6 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r2_6 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r2_6;
|
|
|
|
/* 0x41C : sf_aes_key_r2_7 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_r2_7 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_r2_7;
|
|
|
|
/* 0x420 : sf_aes_iv_r2_w0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_r2_w0 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_r2_w0;
|
|
|
|
/* 0x424 : sf_aes_iv_r2_w1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_r2_w1 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_r2_w1;
|
|
|
|
/* 0x428 : sf_aes_iv_r2_w2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_r2_w2 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_r2_w2;
|
|
|
|
/* 0x42C : sf_aes_iv_r2_w3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_r2_w3 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_r2_w3;
|
|
|
|
/* 0x430 : sf_aes_r2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_r2_end : 14; /* [13: 0], r/w, 0x3fff */
|
|
uint32_t sf_aes_r2_start : 14; /* [27:14], r/w, 0x0 */
|
|
uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */
|
|
uint32_t sf_aes_r2_hw_key_en : 1; /* [ 29], r/w, 0x0 */
|
|
uint32_t sf_aes_r2_en : 1; /* [ 30], r/w, 0x0 */
|
|
uint32_t sf_aes_r2_lock : 1; /* [ 31], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_r2;
|
|
|
|
/* 0x434 : sf_id0_offset */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_id0_offset : 24; /* [23: 0], r/w, 0x0 */
|
|
uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_id0_offset;
|
|
|
|
/* 0x438 : sf_id1_offset */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_id1_offset : 24; /* [23: 0], r/w, 0x0 */
|
|
uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_id1_offset;
|
|
|
|
/* 0x43C : sf_bk2_id0_offset */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_bk2_id0_offset : 24; /* [23: 0], r/w, 0x0 */
|
|
uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_bk2_id0_offset;
|
|
|
|
/* 0x440 : sf_bk2_id1_offset */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_bk2_id1_offset : 24; /* [23: 0], r/w, 0x0 */
|
|
uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_bk2_id1_offset;
|
|
};
|
|
|
|
typedef volatile struct sf_ctrl_reg sf_ctrl_reg_t;
|
|
|
|
/*Following is reg patch*/
|
|
|
|
/* 0x0 : sf_aes_key_0 */
|
|
#define SF_CTRL_SF_AES_KEY_0_OFFSET (0x0)
|
|
#define SF_CTRL_SF_AES_KEY_0 SF_CTRL_SF_AES_KEY_0
|
|
#define SF_CTRL_SF_AES_KEY_0_POS (0U)
|
|
#define SF_CTRL_SF_AES_KEY_0_LEN (32U)
|
|
#define SF_CTRL_SF_AES_KEY_0_MSK (((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS)
|
|
#define SF_CTRL_SF_AES_KEY_0_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS))
|
|
|
|
/* 0x4 : sf_aes_key_1 */
|
|
#define SF_CTRL_SF_AES_KEY_1_OFFSET (0x4)
|
|
#define SF_CTRL_SF_AES_KEY_1 SF_CTRL_SF_AES_KEY_1
|
|
#define SF_CTRL_SF_AES_KEY_1_POS (0U)
|
|
#define SF_CTRL_SF_AES_KEY_1_LEN (32U)
|
|
#define SF_CTRL_SF_AES_KEY_1_MSK (((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS)
|
|
#define SF_CTRL_SF_AES_KEY_1_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS))
|
|
|
|
/* 0x8 : sf_aes_key_2 */
|
|
#define SF_CTRL_SF_AES_KEY_2_OFFSET (0x8)
|
|
#define SF_CTRL_SF_AES_KEY_2 SF_CTRL_SF_AES_KEY_2
|
|
#define SF_CTRL_SF_AES_KEY_2_POS (0U)
|
|
#define SF_CTRL_SF_AES_KEY_2_LEN (32U)
|
|
#define SF_CTRL_SF_AES_KEY_2_MSK (((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS)
|
|
#define SF_CTRL_SF_AES_KEY_2_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS))
|
|
|
|
/* 0xc : sf_aes_key_3 */
|
|
#define SF_CTRL_SF_AES_KEY_3_OFFSET (0xc)
|
|
#define SF_CTRL_SF_AES_KEY_3 SF_CTRL_SF_AES_KEY_3
|
|
#define SF_CTRL_SF_AES_KEY_3_POS (0U)
|
|
#define SF_CTRL_SF_AES_KEY_3_LEN (32U)
|
|
#define SF_CTRL_SF_AES_KEY_3_MSK (((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS)
|
|
#define SF_CTRL_SF_AES_KEY_3_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS))
|
|
|
|
/* 0x10 : sf_aes_key_4 */
|
|
#define SF_CTRL_SF_AES_KEY_4_OFFSET (0x10)
|
|
#define SF_CTRL_SF_AES_KEY_4 SF_CTRL_SF_AES_KEY_4
|
|
#define SF_CTRL_SF_AES_KEY_4_POS (0U)
|
|
#define SF_CTRL_SF_AES_KEY_4_LEN (32U)
|
|
#define SF_CTRL_SF_AES_KEY_4_MSK (((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS)
|
|
#define SF_CTRL_SF_AES_KEY_4_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS))
|
|
|
|
/* 0x14 : sf_aes_key_5 */
|
|
#define SF_CTRL_SF_AES_KEY_5_OFFSET (0x14)
|
|
#define SF_CTRL_SF_AES_KEY_5 SF_CTRL_SF_AES_KEY_5
|
|
#define SF_CTRL_SF_AES_KEY_5_POS (0U)
|
|
#define SF_CTRL_SF_AES_KEY_5_LEN (32U)
|
|
#define SF_CTRL_SF_AES_KEY_5_MSK (((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS)
|
|
#define SF_CTRL_SF_AES_KEY_5_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS))
|
|
|
|
/* 0x18 : sf_aes_key_6 */
|
|
#define SF_CTRL_SF_AES_KEY_6_OFFSET (0x18)
|
|
#define SF_CTRL_SF_AES_KEY_6 SF_CTRL_SF_AES_KEY_6
|
|
#define SF_CTRL_SF_AES_KEY_6_POS (0U)
|
|
#define SF_CTRL_SF_AES_KEY_6_LEN (32U)
|
|
#define SF_CTRL_SF_AES_KEY_6_MSK (((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS)
|
|
#define SF_CTRL_SF_AES_KEY_6_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS))
|
|
|
|
/* 0x1c : sf_aes_key_7 */
|
|
#define SF_CTRL_SF_AES_KEY_7_OFFSET (0x1c)
|
|
#define SF_CTRL_SF_AES_KEY_7 SF_CTRL_SF_AES_KEY_7
|
|
#define SF_CTRL_SF_AES_KEY_7_POS (0U)
|
|
#define SF_CTRL_SF_AES_KEY_7_LEN (32U)
|
|
#define SF_CTRL_SF_AES_KEY_7_MSK (((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS)
|
|
#define SF_CTRL_SF_AES_KEY_7_UMSK (~(((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS))
|
|
|
|
/* 0x20 : sf_aes_iv_w0 */
|
|
#define SF_CTRL_SF_AES_IV_W0_OFFSET (0x20)
|
|
#define SF_CTRL_SF_AES_IV_W0 SF_CTRL_SF_AES_IV_W0
|
|
#define SF_CTRL_SF_AES_IV_W0_POS (0U)
|
|
#define SF_CTRL_SF_AES_IV_W0_LEN (32U)
|
|
#define SF_CTRL_SF_AES_IV_W0_MSK (((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS)
|
|
#define SF_CTRL_SF_AES_IV_W0_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS))
|
|
|
|
/* 0x24 : sf_aes_iv_w1 */
|
|
#define SF_CTRL_SF_AES_IV_W1_OFFSET (0x24)
|
|
#define SF_CTRL_SF_AES_IV_W1 SF_CTRL_SF_AES_IV_W1
|
|
#define SF_CTRL_SF_AES_IV_W1_POS (0U)
|
|
#define SF_CTRL_SF_AES_IV_W1_LEN (32U)
|
|
#define SF_CTRL_SF_AES_IV_W1_MSK (((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS)
|
|
#define SF_CTRL_SF_AES_IV_W1_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS))
|
|
|
|
/* 0x28 : sf_aes_iv_w2 */
|
|
#define SF_CTRL_SF_AES_IV_W2_OFFSET (0x28)
|
|
#define SF_CTRL_SF_AES_IV_W2 SF_CTRL_SF_AES_IV_W2
|
|
#define SF_CTRL_SF_AES_IV_W2_POS (0U)
|
|
#define SF_CTRL_SF_AES_IV_W2_LEN (32U)
|
|
#define SF_CTRL_SF_AES_IV_W2_MSK (((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS)
|
|
#define SF_CTRL_SF_AES_IV_W2_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS))
|
|
|
|
/* 0x2c : sf_aes_iv_w3 */
|
|
#define SF_CTRL_SF_AES_IV_W3_OFFSET (0x2c)
|
|
#define SF_CTRL_SF_AES_IV_W3 SF_CTRL_SF_AES_IV_W3
|
|
#define SF_CTRL_SF_AES_IV_W3_POS (0U)
|
|
#define SF_CTRL_SF_AES_IV_W3_LEN (32U)
|
|
#define SF_CTRL_SF_AES_IV_W3_MSK (((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS)
|
|
#define SF_CTRL_SF_AES_IV_W3_UMSK (~(((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS))
|
|
|
|
/* 0x30 : sf_aes_cfg */
|
|
#define SF_CTRL_SF_AES_CFG_OFFSET (0x30)
|
|
#define SF_CTRL_SF_AES_REGION_END SF_CTRL_SF_AES_REGION_END
|
|
#define SF_CTRL_SF_AES_REGION_END_POS (0U)
|
|
#define SF_CTRL_SF_AES_REGION_END_LEN (14U)
|
|
#define SF_CTRL_SF_AES_REGION_END_MSK (((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS)
|
|
#define SF_CTRL_SF_AES_REGION_END_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS))
|
|
#define SF_CTRL_SF_AES_REGION_START SF_CTRL_SF_AES_REGION_START
|
|
#define SF_CTRL_SF_AES_REGION_START_POS (14U)
|
|
#define SF_CTRL_SF_AES_REGION_START_LEN (14U)
|
|
#define SF_CTRL_SF_AES_REGION_START_MSK (((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS)
|
|
#define SF_CTRL_SF_AES_REGION_START_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS))
|
|
#define SF_CTRL_SF_AES_REGION_HW_KEY_EN SF_CTRL_SF_AES_REGION_HW_KEY_EN
|
|
#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS (29U)
|
|
#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN (1U)
|
|
#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS)
|
|
#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS))
|
|
#define SF_CTRL_SF_AES_REGION_EN SF_CTRL_SF_AES_REGION_EN
|
|
#define SF_CTRL_SF_AES_REGION_EN_POS (30U)
|
|
#define SF_CTRL_SF_AES_REGION_EN_LEN (1U)
|
|
#define SF_CTRL_SF_AES_REGION_EN_MSK (((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS)
|
|
#define SF_CTRL_SF_AES_REGION_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS))
|
|
#define SF_CTRL_SF_AES_REGION_LOCK SF_CTRL_SF_AES_REGION_LOCK
|
|
#define SF_CTRL_SF_AES_REGION_LOCK_POS (31U)
|
|
#define SF_CTRL_SF_AES_REGION_LOCK_LEN (1U)
|
|
#define SF_CTRL_SF_AES_REGION_LOCK_MSK (((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS)
|
|
#define SF_CTRL_SF_AES_REGION_LOCK_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS))
|
|
|
|
struct sf_ctrl_aes_region_reg {
|
|
/* 0x0 : sf_aes_key_0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_0 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_0;
|
|
|
|
/* 0x4 : sf_aes_key_1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_1 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_1;
|
|
|
|
/* 0x8 : sf_aes_key_2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_2 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_2;
|
|
|
|
/* 0xc : sf_aes_key_3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_3 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_3;
|
|
|
|
/* 0x10 : sf_aes_key_4 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_4 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_4;
|
|
|
|
/* 0x14 : sf_aes_key_5 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_5 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_5;
|
|
|
|
/* 0x18 : sf_aes_key_6 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_6 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_6;
|
|
|
|
/* 0x1c : sf_aes_key_7 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_key_7 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_key_7;
|
|
|
|
/* 0x20 : sf_aes_iv_w0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_w0 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_w0;
|
|
|
|
/* 0x24 : sf_aes_iv_w1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_w1 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_w1;
|
|
|
|
/* 0x28 : sf_aes_iv_w2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_w2 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_w2;
|
|
|
|
/* 0x2c : sf_aes_iv_w3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_iv_w3 : 32; /* [31: 0], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_iv_w3;
|
|
|
|
/* 0x30 : sf_aes_cfg */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t sf_aes_region_end : 14; /* [13: 0], r/w, 0x3fff */
|
|
uint32_t sf_aes_region_start : 14; /* [27:14], r/w, 0x0 */
|
|
uint32_t reserved_28 : 1; /* [ 28], rsvd, 0x0 */
|
|
uint32_t sf_aes_region_hw_key_en : 1; /* [ 29], r/w, 0x0 */
|
|
uint32_t sf_aes_region_en : 1; /* [ 30], r/w, 0x0 */
|
|
uint32_t sf_aes_region_lock : 1; /* [ 31], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} sf_aes_cfg;
|
|
};
|
|
|
|
typedef volatile struct sf_ctrl_aes_region_reg sf_ctrl_aes_region_reg_t;
|
|
|
|
#define SF_CTRL_AES_REGION_OFFSET 0x200
|
|
|
|
#endif /* __SF_CTRL_REG_H__ */
|