1412 lines
92 KiB
C
1412 lines
92 KiB
C
/**
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******************************************************************************
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* @file pds_reg.h
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* @version V1.2
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* @date 2020-03-30
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __PDS_REG_H__
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#define __PDS_REG_H__
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#include "bl702.h"
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/* 0x0 : PDS_CTL */
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#define PDS_CTL_OFFSET (0x0)
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#define PDS_START_PS PDS_START_PS
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#define PDS_START_PS_POS (0U)
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#define PDS_START_PS_LEN (1U)
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#define PDS_START_PS_MSK (((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS)
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#define PDS_START_PS_UMSK (~(((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS))
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#define PDS_CR_SLEEP_FOREVER PDS_CR_SLEEP_FOREVER
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#define PDS_CR_SLEEP_FOREVER_POS (1U)
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#define PDS_CR_SLEEP_FOREVER_LEN (1U)
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#define PDS_CR_SLEEP_FOREVER_MSK (((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS)
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#define PDS_CR_SLEEP_FOREVER_UMSK (~(((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS))
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#define PDS_CR_XTAL_FORCE_OFF PDS_CR_XTAL_FORCE_OFF
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#define PDS_CR_XTAL_FORCE_OFF_POS (2U)
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#define PDS_CR_XTAL_FORCE_OFF_LEN (1U)
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#define PDS_CR_XTAL_FORCE_OFF_MSK (((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS)
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#define PDS_CR_XTAL_FORCE_OFF_UMSK (~(((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS))
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#define PDS_CR_WIFI_PDS_SAVE_STATE PDS_CR_WIFI_PDS_SAVE_STATE
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#define PDS_CR_WIFI_PDS_SAVE_STATE_POS (3U)
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#define PDS_CR_WIFI_PDS_SAVE_STATE_LEN (1U)
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#define PDS_CR_WIFI_PDS_SAVE_STATE_MSK (((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS)
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#define PDS_CR_WIFI_PDS_SAVE_STATE_UMSK (~(((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS))
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#define PDS_CR_PDS_PD_DCDC18 PDS_CR_PDS_PD_DCDC18
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#define PDS_CR_PDS_PD_DCDC18_POS (4U)
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#define PDS_CR_PDS_PD_DCDC18_LEN (1U)
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#define PDS_CR_PDS_PD_DCDC18_MSK (((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS)
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#define PDS_CR_PDS_PD_DCDC18_UMSK (~(((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS))
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#define PDS_CR_PDS_PD_BG_SYS PDS_CR_PDS_PD_BG_SYS
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#define PDS_CR_PDS_PD_BG_SYS_POS (5U)
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#define PDS_CR_PDS_PD_BG_SYS_LEN (1U)
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#define PDS_CR_PDS_PD_BG_SYS_MSK (((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS)
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#define PDS_CR_PDS_PD_BG_SYS_UMSK (~(((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS))
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#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD PDS_CR_PDS_CTRL_GPIO_IE_PU_PD
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#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS (6U)
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#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN (1U)
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#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_MSK (((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS)
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#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_UMSK (~(((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS))
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#define PDS_CR_PDS_CTRL_PU_FLASH PDS_CR_PDS_CTRL_PU_FLASH
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#define PDS_CR_PDS_CTRL_PU_FLASH_POS (7U)
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#define PDS_CR_PDS_CTRL_PU_FLASH_LEN (1U)
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#define PDS_CR_PDS_CTRL_PU_FLASH_MSK (((1U << PDS_CR_PDS_CTRL_PU_FLASH_LEN) - 1) << PDS_CR_PDS_CTRL_PU_FLASH_POS)
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#define PDS_CR_PDS_CTRL_PU_FLASH_UMSK (~(((1U << PDS_CR_PDS_CTRL_PU_FLASH_LEN) - 1) << PDS_CR_PDS_CTRL_PU_FLASH_POS))
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#define PDS_CR_PDS_GATE_CLK PDS_CR_PDS_GATE_CLK
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#define PDS_CR_PDS_GATE_CLK_POS (8U)
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#define PDS_CR_PDS_GATE_CLK_LEN (1U)
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#define PDS_CR_PDS_GATE_CLK_MSK (((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS)
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#define PDS_CR_PDS_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS))
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#define PDS_CR_PDS_MEM_STBY PDS_CR_PDS_MEM_STBY
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#define PDS_CR_PDS_MEM_STBY_POS (9U)
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#define PDS_CR_PDS_MEM_STBY_LEN (1U)
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#define PDS_CR_PDS_MEM_STBY_MSK (((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS)
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#define PDS_CR_PDS_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS))
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#define PDS_CR_SW_PU_FLASH PDS_CR_SW_PU_FLASH
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#define PDS_CR_SW_PU_FLASH_POS (10U)
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#define PDS_CR_SW_PU_FLASH_LEN (1U)
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#define PDS_CR_SW_PU_FLASH_MSK (((1U << PDS_CR_SW_PU_FLASH_LEN) - 1) << PDS_CR_SW_PU_FLASH_POS)
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#define PDS_CR_SW_PU_FLASH_UMSK (~(((1U << PDS_CR_SW_PU_FLASH_LEN) - 1) << PDS_CR_SW_PU_FLASH_POS))
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#define PDS_CR_PDS_ISO_EN PDS_CR_PDS_ISO_EN
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#define PDS_CR_PDS_ISO_EN_POS (11U)
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#define PDS_CR_PDS_ISO_EN_LEN (1U)
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#define PDS_CR_PDS_ISO_EN_MSK (((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS)
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#define PDS_CR_PDS_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS))
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#define PDS_CR_PDS_WAIT_XTAL_RDY PDS_CR_PDS_WAIT_XTAL_RDY
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#define PDS_CR_PDS_WAIT_XTAL_RDY_POS (12U)
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#define PDS_CR_PDS_WAIT_XTAL_RDY_LEN (1U)
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#define PDS_CR_PDS_WAIT_XTAL_RDY_MSK (((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS)
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#define PDS_CR_PDS_WAIT_XTAL_RDY_UMSK (~(((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS))
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#define PDS_CR_PDS_PWR_OFF PDS_CR_PDS_PWR_OFF
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#define PDS_CR_PDS_PWR_OFF_POS (13U)
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#define PDS_CR_PDS_PWR_OFF_LEN (1U)
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#define PDS_CR_PDS_PWR_OFF_MSK (((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS)
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#define PDS_CR_PDS_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS))
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#define PDS_CR_PDS_PD_XTAL PDS_CR_PDS_PD_XTAL
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#define PDS_CR_PDS_PD_XTAL_POS (14U)
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#define PDS_CR_PDS_PD_XTAL_LEN (1U)
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#define PDS_CR_PDS_PD_XTAL_MSK (((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS)
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#define PDS_CR_PDS_PD_XTAL_UMSK (~(((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS))
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#define PDS_CR_PDS_SOC_ENB_FORCE_ON PDS_CR_PDS_SOC_ENB_FORCE_ON
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#define PDS_CR_PDS_SOC_ENB_FORCE_ON_POS (15U)
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#define PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN (1U)
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#define PDS_CR_PDS_SOC_ENB_FORCE_ON_MSK (((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS)
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#define PDS_CR_PDS_SOC_ENB_FORCE_ON_UMSK (~(((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS))
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#define PDS_CR_PDS_RST_SOC_EN PDS_CR_PDS_RST_SOC_EN
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#define PDS_CR_PDS_RST_SOC_EN_POS (16U)
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#define PDS_CR_PDS_RST_SOC_EN_LEN (1U)
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#define PDS_CR_PDS_RST_SOC_EN_MSK (((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS)
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#define PDS_CR_PDS_RST_SOC_EN_UMSK (~(((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS))
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#define PDS_CR_PDS_RC32M_OFF_DIS PDS_CR_PDS_RC32M_OFF_DIS
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#define PDS_CR_PDS_RC32M_OFF_DIS_POS (17U)
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#define PDS_CR_PDS_RC32M_OFF_DIS_LEN (1U)
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#define PDS_CR_PDS_RC32M_OFF_DIS_MSK (((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS)
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#define PDS_CR_PDS_RC32M_OFF_DIS_UMSK (~(((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS))
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#define PDS_CR_PDS_LDO_VSEL_EN PDS_CR_PDS_LDO_VSEL_EN
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#define PDS_CR_PDS_LDO_VSEL_EN_POS (18U)
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#define PDS_CR_PDS_LDO_VSEL_EN_LEN (1U)
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#define PDS_CR_PDS_LDO_VSEL_EN_MSK (((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS)
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#define PDS_CR_PDS_LDO_VSEL_EN_UMSK (~(((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS))
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#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN PDS_CR_PDS_RAM_LP_WITH_CLK_EN
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#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS (19U)
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#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN (1U)
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#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_MSK (((1U << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN) - 1) << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS)
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#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_UMSK (~(((1U << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN) - 1) << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS))
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#define PDS_CR_NP_WFI_MASK PDS_CR_NP_WFI_MASK
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#define PDS_CR_NP_WFI_MASK_POS (21U)
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#define PDS_CR_NP_WFI_MASK_LEN (1U)
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#define PDS_CR_NP_WFI_MASK_MSK (((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS)
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#define PDS_CR_NP_WFI_MASK_UMSK (~(((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS))
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#define PDS_CR_PDS_PD_LDO11 PDS_CR_PDS_PD_LDO11
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#define PDS_CR_PDS_PD_LDO11_POS (22U)
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#define PDS_CR_PDS_PD_LDO11_LEN (1U)
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#define PDS_CR_PDS_PD_LDO11_MSK (((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS)
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#define PDS_CR_PDS_PD_LDO11_UMSK (~(((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS))
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#define PDS_CR_PDS_FORCE_RAM_CLK_EN PDS_CR_PDS_FORCE_RAM_CLK_EN
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#define PDS_CR_PDS_FORCE_RAM_CLK_EN_POS (23U)
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#define PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN (1U)
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#define PDS_CR_PDS_FORCE_RAM_CLK_EN_MSK (((1U << PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN) - 1) << PDS_CR_PDS_FORCE_RAM_CLK_EN_POS)
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#define PDS_CR_PDS_FORCE_RAM_CLK_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN) - 1) << PDS_CR_PDS_FORCE_RAM_CLK_EN_POS))
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#define PDS_CR_PDS_LDO_VOL PDS_CR_PDS_LDO_VOL
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#define PDS_CR_PDS_LDO_VOL_POS (24U)
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#define PDS_CR_PDS_LDO_VOL_LEN (4U)
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#define PDS_CR_PDS_LDO_VOL_MSK (((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS)
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#define PDS_CR_PDS_LDO_VOL_UMSK (~(((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS))
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#define PDS_CR_PDS_CTRL_RF PDS_CR_PDS_CTRL_RF
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#define PDS_CR_PDS_CTRL_RF_POS (28U)
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#define PDS_CR_PDS_CTRL_RF_LEN (2U)
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#define PDS_CR_PDS_CTRL_RF_MSK (((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS)
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#define PDS_CR_PDS_CTRL_RF_UMSK (~(((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS))
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#define PDS_CR_PDS_CTRL_PLL PDS_CR_PDS_CTRL_PLL
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#define PDS_CR_PDS_CTRL_PLL_POS (30U)
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#define PDS_CR_PDS_CTRL_PLL_LEN (2U)
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#define PDS_CR_PDS_CTRL_PLL_MSK (((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS)
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#define PDS_CR_PDS_CTRL_PLL_UMSK (~(((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS))
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/* 0x4 : PDS_TIME1 */
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#define PDS_TIME1_OFFSET (0x4)
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#define PDS_CR_SLEEP_DURATION PDS_CR_SLEEP_DURATION
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#define PDS_CR_SLEEP_DURATION_POS (0U)
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#define PDS_CR_SLEEP_DURATION_LEN (32U)
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#define PDS_CR_SLEEP_DURATION_MSK (((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS)
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#define PDS_CR_SLEEP_DURATION_UMSK (~(((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS))
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/* 0xC : PDS_INT */
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#define PDS_INT_OFFSET (0xC)
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#define PDS_RO_PDS_WAKE_INT PDS_RO_PDS_WAKE_INT
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#define PDS_RO_PDS_WAKE_INT_POS (0U)
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#define PDS_RO_PDS_WAKE_INT_LEN (1U)
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#define PDS_RO_PDS_WAKE_INT_MSK (((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS)
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#define PDS_RO_PDS_WAKE_INT_UMSK (~(((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS))
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#define PDS_RO_PDS_RF_DONE_INT PDS_RO_PDS_RF_DONE_INT
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#define PDS_RO_PDS_RF_DONE_INT_POS (2U)
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#define PDS_RO_PDS_RF_DONE_INT_LEN (1U)
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#define PDS_RO_PDS_RF_DONE_INT_MSK (((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS)
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#define PDS_RO_PDS_RF_DONE_INT_UMSK (~(((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS))
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#define PDS_RO_PDS_PLL_DONE_INT PDS_RO_PDS_PLL_DONE_INT
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#define PDS_RO_PDS_PLL_DONE_INT_POS (3U)
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#define PDS_RO_PDS_PLL_DONE_INT_LEN (1U)
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#define PDS_RO_PDS_PLL_DONE_INT_MSK (((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS)
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#define PDS_RO_PDS_PLL_DONE_INT_UMSK (~(((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS))
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#define PDS_RESET_EVENT PDS_RESET_EVENT
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#define PDS_RESET_EVENT_POS (4U)
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#define PDS_RESET_EVENT_LEN (3U)
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#define PDS_RESET_EVENT_MSK (((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS)
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#define PDS_RESET_EVENT_UMSK (~(((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS))
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#define PDS_CLR_RESET_EVENT PDS_CLR_RESET_EVENT
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#define PDS_CLR_RESET_EVENT_POS (7U)
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#define PDS_CLR_RESET_EVENT_LEN (1U)
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#define PDS_CLR_RESET_EVENT_MSK (((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS)
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#define PDS_CLR_RESET_EVENT_UMSK (~(((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS))
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#define PDS_CR_PDS_WAKE_INT_MASK PDS_CR_PDS_WAKE_INT_MASK
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#define PDS_CR_PDS_WAKE_INT_MASK_POS (8U)
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#define PDS_CR_PDS_WAKE_INT_MASK_LEN (1U)
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#define PDS_CR_PDS_WAKE_INT_MASK_MSK (((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS)
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#define PDS_CR_PDS_WAKE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS))
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#define PDS_CR_PDS_RF_DONE_INT_MASK PDS_CR_PDS_RF_DONE_INT_MASK
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#define PDS_CR_PDS_RF_DONE_INT_MASK_POS (10U)
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#define PDS_CR_PDS_RF_DONE_INT_MASK_LEN (1U)
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#define PDS_CR_PDS_RF_DONE_INT_MASK_MSK (((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS)
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#define PDS_CR_PDS_RF_DONE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS))
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#define PDS_CR_PDS_PLL_DONE_INT_MASK PDS_CR_PDS_PLL_DONE_INT_MASK
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#define PDS_CR_PDS_PLL_DONE_INT_MASK_POS (11U)
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#define PDS_CR_PDS_PLL_DONE_INT_MASK_LEN (1U)
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#define PDS_CR_PDS_PLL_DONE_INT_MASK_MSK (((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS)
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#define PDS_CR_PDS_PLL_DONE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS))
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#define PDS_CR_PDS_INT_CLR PDS_CR_PDS_INT_CLR
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#define PDS_CR_PDS_INT_CLR_POS (15U)
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#define PDS_CR_PDS_INT_CLR_LEN (1U)
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#define PDS_CR_PDS_INT_CLR_MSK (((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS)
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#define PDS_CR_PDS_INT_CLR_UMSK (~(((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS))
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#define PDS_CR_PDS_WAKEUP_SRC_EN PDS_CR_PDS_WAKEUP_SRC_EN
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#define PDS_CR_PDS_WAKEUP_SRC_EN_POS (16U)
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#define PDS_CR_PDS_WAKEUP_SRC_EN_LEN (8U)
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#define PDS_CR_PDS_WAKEUP_SRC_EN_MSK (((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS)
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#define PDS_CR_PDS_WAKEUP_SRC_EN_UMSK (~(((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS))
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#define PDS_RO_PDS_WAKEUP_EVENT PDS_RO_PDS_WAKEUP_EVENT
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#define PDS_RO_PDS_WAKEUP_EVENT_POS (24U)
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#define PDS_RO_PDS_WAKEUP_EVENT_LEN (8U)
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#define PDS_RO_PDS_WAKEUP_EVENT_MSK (((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS)
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#define PDS_RO_PDS_WAKEUP_EVENT_UMSK (~(((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS))
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/* 0x10 : PDS_CTL2 */
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#define PDS_CTL2_OFFSET (0x10)
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#define PDS_CR_PDS_FORCE_NP_PWR_OFF PDS_CR_PDS_FORCE_NP_PWR_OFF
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#define PDS_CR_PDS_FORCE_NP_PWR_OFF_POS (0U)
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#define PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN (1U)
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#define PDS_CR_PDS_FORCE_NP_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS)
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#define PDS_CR_PDS_FORCE_NP_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS))
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#define PDS_CR_PDS_FORCE_BZ_PWR_OFF PDS_CR_PDS_FORCE_BZ_PWR_OFF
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#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS (2U)
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#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN (1U)
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#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS)
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#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS))
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#define PDS_CR_PDS_FORCE_USB_PWR_OFF PDS_CR_PDS_FORCE_USB_PWR_OFF
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#define PDS_CR_PDS_FORCE_USB_PWR_OFF_POS (3U)
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#define PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN (1U)
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#define PDS_CR_PDS_FORCE_USB_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS)
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#define PDS_CR_PDS_FORCE_USB_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS))
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#define PDS_CR_PDS_FORCE_NP_ISO_EN PDS_CR_PDS_FORCE_NP_ISO_EN
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#define PDS_CR_PDS_FORCE_NP_ISO_EN_POS (4U)
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#define PDS_CR_PDS_FORCE_NP_ISO_EN_LEN (1U)
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#define PDS_CR_PDS_FORCE_NP_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS)
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#define PDS_CR_PDS_FORCE_NP_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS))
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#define PDS_CR_PDS_FORCE_BZ_ISO_EN PDS_CR_PDS_FORCE_BZ_ISO_EN
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#define PDS_CR_PDS_FORCE_BZ_ISO_EN_POS (6U)
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#define PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN (1U)
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#define PDS_CR_PDS_FORCE_BZ_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_ISO_EN_POS)
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#define PDS_CR_PDS_FORCE_BZ_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_ISO_EN_POS))
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#define PDS_CR_PDS_FORCE_USB_ISO_EN PDS_CR_PDS_FORCE_USB_ISO_EN
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#define PDS_CR_PDS_FORCE_USB_ISO_EN_POS (7U)
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#define PDS_CR_PDS_FORCE_USB_ISO_EN_LEN (1U)
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#define PDS_CR_PDS_FORCE_USB_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS)
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#define PDS_CR_PDS_FORCE_USB_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS))
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#define PDS_CR_PDS_FORCE_NP_PDS_RST PDS_CR_PDS_FORCE_NP_PDS_RST
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#define PDS_CR_PDS_FORCE_NP_PDS_RST_POS (8U)
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#define PDS_CR_PDS_FORCE_NP_PDS_RST_LEN (1U)
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#define PDS_CR_PDS_FORCE_NP_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS)
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#define PDS_CR_PDS_FORCE_NP_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS))
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#define PDS_CR_PDS_FORCE_BZ_PDS_RST PDS_CR_PDS_FORCE_BZ_PDS_RST
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#define PDS_CR_PDS_FORCE_BZ_PDS_RST_POS (10U)
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#define PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN (1U)
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#define PDS_CR_PDS_FORCE_BZ_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PDS_RST_POS)
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#define PDS_CR_PDS_FORCE_BZ_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PDS_RST_POS))
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#define PDS_CR_PDS_FORCE_USB_PDS_RST PDS_CR_PDS_FORCE_USB_PDS_RST
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#define PDS_CR_PDS_FORCE_USB_PDS_RST_POS (11U)
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#define PDS_CR_PDS_FORCE_USB_PDS_RST_LEN (1U)
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#define PDS_CR_PDS_FORCE_USB_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS)
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#define PDS_CR_PDS_FORCE_USB_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS))
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#define PDS_CR_PDS_FORCE_NP_MEM_STBY PDS_CR_PDS_FORCE_NP_MEM_STBY
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#define PDS_CR_PDS_FORCE_NP_MEM_STBY_POS (12U)
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#define PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN (1U)
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#define PDS_CR_PDS_FORCE_NP_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS)
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#define PDS_CR_PDS_FORCE_NP_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS))
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#define PDS_CR_PDS_FORCE_BZ_MEM_STBY PDS_CR_PDS_FORCE_BZ_MEM_STBY
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#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS (14U)
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#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN (1U)
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#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS)
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#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS))
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#define PDS_CR_PDS_FORCE_USB_MEM_STBY PDS_CR_PDS_FORCE_USB_MEM_STBY
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#define PDS_CR_PDS_FORCE_USB_MEM_STBY_POS (15U)
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#define PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN (1U)
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#define PDS_CR_PDS_FORCE_USB_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS)
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#define PDS_CR_PDS_FORCE_USB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS))
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#define PDS_CR_PDS_FORCE_NP_GATE_CLK PDS_CR_PDS_FORCE_NP_GATE_CLK
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#define PDS_CR_PDS_FORCE_NP_GATE_CLK_POS (16U)
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#define PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN (1U)
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#define PDS_CR_PDS_FORCE_NP_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS)
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#define PDS_CR_PDS_FORCE_NP_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS))
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#define PDS_CR_PDS_FORCE_BZ_GATE_CLK PDS_CR_PDS_FORCE_BZ_GATE_CLK
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#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS (18U)
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#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN (1U)
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#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS)
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#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS))
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#define PDS_CR_PDS_FORCE_USB_GATE_CLK PDS_CR_PDS_FORCE_USB_GATE_CLK
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#define PDS_CR_PDS_FORCE_USB_GATE_CLK_POS (19U)
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#define PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN (1U)
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#define PDS_CR_PDS_FORCE_USB_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS)
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#define PDS_CR_PDS_FORCE_USB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS))
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/* 0x14 : PDS_CTL3 */
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#define PDS_CTL3_OFFSET (0x14)
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#define PDS_CR_PDS_FORCE_MISC_PWR_OFF PDS_CR_PDS_FORCE_MISC_PWR_OFF
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#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS (1U)
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#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN (1U)
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#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS)
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#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS))
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#define PDS_CR_PDS_FORCE_BLE_PWR_OFF PDS_CR_PDS_FORCE_BLE_PWR_OFF
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#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS (2U)
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#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN (1U)
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#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_MSK (((1U << PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS)
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#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS))
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#define PDS_CR_PDS_FORCE_BLE_ISO_EN PDS_CR_PDS_FORCE_BLE_ISO_EN
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#define PDS_CR_PDS_FORCE_BLE_ISO_EN_POS (5U)
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#define PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN (1U)
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#define PDS_CR_PDS_FORCE_BLE_ISO_EN_MSK (((1U << PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_ISO_EN_POS)
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#define PDS_CR_PDS_FORCE_BLE_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_ISO_EN_POS))
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#define PDS_CR_PDS_FORCE_MISC_PDS_RST PDS_CR_PDS_FORCE_MISC_PDS_RST
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#define PDS_CR_PDS_FORCE_MISC_PDS_RST_POS (7U)
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#define PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN (1U)
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#define PDS_CR_PDS_FORCE_MISC_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS)
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#define PDS_CR_PDS_FORCE_MISC_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS))
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#define PDS_CR_PDS_FORCE_BLE_PDS_RST PDS_CR_PDS_FORCE_BLE_PDS_RST
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#define PDS_CR_PDS_FORCE_BLE_PDS_RST_POS (8U)
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#define PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN (1U)
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#define PDS_CR_PDS_FORCE_BLE_PDS_RST_MSK (((1U << PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PDS_RST_POS)
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#define PDS_CR_PDS_FORCE_BLE_PDS_RST_UMSK (~(((1U << PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PDS_RST_POS))
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#define PDS_CR_PDS_FORCE_MISC_MEM_STBY PDS_CR_PDS_FORCE_MISC_MEM_STBY
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#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS (10U)
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#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN (1U)
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#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS)
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#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS))
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#define PDS_CR_PDS_FORCE_BLE_MEM_STBY PDS_CR_PDS_FORCE_BLE_MEM_STBY
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#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS (11U)
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#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN (1U)
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#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_MSK (((1U << PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS)
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#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS))
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#define PDS_CR_PDS_FORCE_MISC_GATE_CLK PDS_CR_PDS_FORCE_MISC_GATE_CLK
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#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS (13U)
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#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN (1U)
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#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS)
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#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS))
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#define PDS_CR_PDS_FORCE_BLE_GATE_CLK PDS_CR_PDS_FORCE_BLE_GATE_CLK
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#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS (14U)
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#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN (1U)
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#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_MSK (((1U << PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS)
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#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS))
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#define PDS_CR_PDS_NP_ISO_EN PDS_CR_PDS_NP_ISO_EN
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#define PDS_CR_PDS_NP_ISO_EN_POS (24U)
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#define PDS_CR_PDS_NP_ISO_EN_LEN (1U)
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#define PDS_CR_PDS_NP_ISO_EN_MSK (((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS)
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#define PDS_CR_PDS_NP_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS))
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#define PDS_CR_PDS_BZ_ISO_EN PDS_CR_PDS_BZ_ISO_EN
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#define PDS_CR_PDS_BZ_ISO_EN_POS (27U)
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#define PDS_CR_PDS_BZ_ISO_EN_LEN (1U)
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#define PDS_CR_PDS_BZ_ISO_EN_MSK (((1U << PDS_CR_PDS_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_BZ_ISO_EN_POS)
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#define PDS_CR_PDS_BZ_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_BZ_ISO_EN_POS))
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#define PDS_CR_PDS_BLE_ISO_EN PDS_CR_PDS_BLE_ISO_EN
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#define PDS_CR_PDS_BLE_ISO_EN_POS (28U)
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#define PDS_CR_PDS_BLE_ISO_EN_LEN (1U)
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#define PDS_CR_PDS_BLE_ISO_EN_MSK (((1U << PDS_CR_PDS_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_BLE_ISO_EN_POS)
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#define PDS_CR_PDS_BLE_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_BLE_ISO_EN_POS))
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#define PDS_CR_PDS_USB_ISO_EN PDS_CR_PDS_USB_ISO_EN
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#define PDS_CR_PDS_USB_ISO_EN_POS (29U)
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#define PDS_CR_PDS_USB_ISO_EN_LEN (1U)
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#define PDS_CR_PDS_USB_ISO_EN_MSK (((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS)
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#define PDS_CR_PDS_USB_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS))
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#define PDS_CR_PDS_MISC_ISO_EN PDS_CR_PDS_MISC_ISO_EN
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#define PDS_CR_PDS_MISC_ISO_EN_POS (30U)
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#define PDS_CR_PDS_MISC_ISO_EN_LEN (1U)
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#define PDS_CR_PDS_MISC_ISO_EN_MSK (((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS)
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#define PDS_CR_PDS_MISC_ISO_EN_UMSK (~(((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS))
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/* 0x18 : PDS_CTL4 */
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#define PDS_CTL4_OFFSET (0x18)
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#define PDS_CR_PDS_NP_PWR_OFF PDS_CR_PDS_NP_PWR_OFF
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#define PDS_CR_PDS_NP_PWR_OFF_POS (0U)
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#define PDS_CR_PDS_NP_PWR_OFF_LEN (1U)
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#define PDS_CR_PDS_NP_PWR_OFF_MSK (((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS)
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#define PDS_CR_PDS_NP_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS))
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#define PDS_CR_PDS_NP_RESET PDS_CR_PDS_NP_RESET
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#define PDS_CR_PDS_NP_RESET_POS (1U)
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#define PDS_CR_PDS_NP_RESET_LEN (1U)
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#define PDS_CR_PDS_NP_RESET_MSK (((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS)
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#define PDS_CR_PDS_NP_RESET_UMSK (~(((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS))
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#define PDS_CR_PDS_NP_MEM_STBY PDS_CR_PDS_NP_MEM_STBY
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#define PDS_CR_PDS_NP_MEM_STBY_POS (2U)
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#define PDS_CR_PDS_NP_MEM_STBY_LEN (1U)
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#define PDS_CR_PDS_NP_MEM_STBY_MSK (((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS)
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#define PDS_CR_PDS_NP_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS))
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#define PDS_CR_PDS_NP_GATE_CLK PDS_CR_PDS_NP_GATE_CLK
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#define PDS_CR_PDS_NP_GATE_CLK_POS (3U)
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#define PDS_CR_PDS_NP_GATE_CLK_LEN (1U)
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#define PDS_CR_PDS_NP_GATE_CLK_MSK (((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS)
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#define PDS_CR_PDS_NP_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS))
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#define PDS_CR_PDS_BZ_PWR_OFF PDS_CR_PDS_BZ_PWR_OFF
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#define PDS_CR_PDS_BZ_PWR_OFF_POS (12U)
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#define PDS_CR_PDS_BZ_PWR_OFF_LEN (1U)
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#define PDS_CR_PDS_BZ_PWR_OFF_MSK (((1U << PDS_CR_PDS_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BZ_PWR_OFF_POS)
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#define PDS_CR_PDS_BZ_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BZ_PWR_OFF_POS))
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#define PDS_CR_PDS_BZ_RESET PDS_CR_PDS_BZ_RESET
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#define PDS_CR_PDS_BZ_RESET_POS (13U)
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#define PDS_CR_PDS_BZ_RESET_LEN (1U)
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#define PDS_CR_PDS_BZ_RESET_MSK (((1U << PDS_CR_PDS_BZ_RESET_LEN) - 1) << PDS_CR_PDS_BZ_RESET_POS)
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#define PDS_CR_PDS_BZ_RESET_UMSK (~(((1U << PDS_CR_PDS_BZ_RESET_LEN) - 1) << PDS_CR_PDS_BZ_RESET_POS))
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#define PDS_CR_PDS_BZ_MEM_STBY PDS_CR_PDS_BZ_MEM_STBY
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#define PDS_CR_PDS_BZ_MEM_STBY_POS (14U)
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#define PDS_CR_PDS_BZ_MEM_STBY_LEN (1U)
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#define PDS_CR_PDS_BZ_MEM_STBY_MSK (((1U << PDS_CR_PDS_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BZ_MEM_STBY_POS)
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#define PDS_CR_PDS_BZ_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BZ_MEM_STBY_POS))
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#define PDS_CR_PDS_BZ_GATE_CLK PDS_CR_PDS_BZ_GATE_CLK
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#define PDS_CR_PDS_BZ_GATE_CLK_POS (15U)
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#define PDS_CR_PDS_BZ_GATE_CLK_LEN (1U)
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#define PDS_CR_PDS_BZ_GATE_CLK_MSK (((1U << PDS_CR_PDS_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BZ_GATE_CLK_POS)
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#define PDS_CR_PDS_BZ_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BZ_GATE_CLK_POS))
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#define PDS_CR_PDS_BLE_PWR_OFF PDS_CR_PDS_BLE_PWR_OFF
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#define PDS_CR_PDS_BLE_PWR_OFF_POS (16U)
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#define PDS_CR_PDS_BLE_PWR_OFF_LEN (1U)
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#define PDS_CR_PDS_BLE_PWR_OFF_MSK (((1U << PDS_CR_PDS_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BLE_PWR_OFF_POS)
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#define PDS_CR_PDS_BLE_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BLE_PWR_OFF_POS))
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#define PDS_CR_PDS_BLE_RESET PDS_CR_PDS_BLE_RESET
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#define PDS_CR_PDS_BLE_RESET_POS (17U)
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#define PDS_CR_PDS_BLE_RESET_LEN (1U)
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#define PDS_CR_PDS_BLE_RESET_MSK (((1U << PDS_CR_PDS_BLE_RESET_LEN) - 1) << PDS_CR_PDS_BLE_RESET_POS)
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#define PDS_CR_PDS_BLE_RESET_UMSK (~(((1U << PDS_CR_PDS_BLE_RESET_LEN) - 1) << PDS_CR_PDS_BLE_RESET_POS))
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#define PDS_CR_PDS_BLE_MEM_STBY PDS_CR_PDS_BLE_MEM_STBY
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#define PDS_CR_PDS_BLE_MEM_STBY_POS (18U)
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#define PDS_CR_PDS_BLE_MEM_STBY_LEN (1U)
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#define PDS_CR_PDS_BLE_MEM_STBY_MSK (((1U << PDS_CR_PDS_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BLE_MEM_STBY_POS)
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#define PDS_CR_PDS_BLE_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BLE_MEM_STBY_POS))
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#define PDS_CR_PDS_BLE_GATE_CLK PDS_CR_PDS_BLE_GATE_CLK
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#define PDS_CR_PDS_BLE_GATE_CLK_POS (19U)
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#define PDS_CR_PDS_BLE_GATE_CLK_LEN (1U)
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#define PDS_CR_PDS_BLE_GATE_CLK_MSK (((1U << PDS_CR_PDS_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BLE_GATE_CLK_POS)
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#define PDS_CR_PDS_BLE_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BLE_GATE_CLK_POS))
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#define PDS_CR_PDS_USB_PWR_OFF PDS_CR_PDS_USB_PWR_OFF
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#define PDS_CR_PDS_USB_PWR_OFF_POS (20U)
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#define PDS_CR_PDS_USB_PWR_OFF_LEN (1U)
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#define PDS_CR_PDS_USB_PWR_OFF_MSK (((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS)
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#define PDS_CR_PDS_USB_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS))
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#define PDS_CR_PDS_USB_RESET PDS_CR_PDS_USB_RESET
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#define PDS_CR_PDS_USB_RESET_POS (21U)
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#define PDS_CR_PDS_USB_RESET_LEN (1U)
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#define PDS_CR_PDS_USB_RESET_MSK (((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS)
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#define PDS_CR_PDS_USB_RESET_UMSK (~(((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS))
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#define PDS_CR_PDS_USB_MEM_STBY PDS_CR_PDS_USB_MEM_STBY
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#define PDS_CR_PDS_USB_MEM_STBY_POS (22U)
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#define PDS_CR_PDS_USB_MEM_STBY_LEN (1U)
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#define PDS_CR_PDS_USB_MEM_STBY_MSK (((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS)
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#define PDS_CR_PDS_USB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS))
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#define PDS_CR_PDS_USB_GATE_CLK PDS_CR_PDS_USB_GATE_CLK
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#define PDS_CR_PDS_USB_GATE_CLK_POS (23U)
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#define PDS_CR_PDS_USB_GATE_CLK_LEN (1U)
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#define PDS_CR_PDS_USB_GATE_CLK_MSK (((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS)
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#define PDS_CR_PDS_USB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS))
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#define PDS_CR_PDS_MISC_PWR_OFF PDS_CR_PDS_MISC_PWR_OFF
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#define PDS_CR_PDS_MISC_PWR_OFF_POS (24U)
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#define PDS_CR_PDS_MISC_PWR_OFF_LEN (1U)
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#define PDS_CR_PDS_MISC_PWR_OFF_MSK (((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS)
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#define PDS_CR_PDS_MISC_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS))
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#define PDS_CR_PDS_MISC_RESET PDS_CR_PDS_MISC_RESET
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#define PDS_CR_PDS_MISC_RESET_POS (25U)
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#define PDS_CR_PDS_MISC_RESET_LEN (1U)
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#define PDS_CR_PDS_MISC_RESET_MSK (((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS)
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#define PDS_CR_PDS_MISC_RESET_UMSK (~(((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS))
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#define PDS_CR_PDS_MISC_MEM_STBY PDS_CR_PDS_MISC_MEM_STBY
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#define PDS_CR_PDS_MISC_MEM_STBY_POS (26U)
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#define PDS_CR_PDS_MISC_MEM_STBY_LEN (1U)
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#define PDS_CR_PDS_MISC_MEM_STBY_MSK (((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS)
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#define PDS_CR_PDS_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS))
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#define PDS_CR_PDS_MISC_GATE_CLK PDS_CR_PDS_MISC_GATE_CLK
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#define PDS_CR_PDS_MISC_GATE_CLK_POS (27U)
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#define PDS_CR_PDS_MISC_GATE_CLK_LEN (1U)
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#define PDS_CR_PDS_MISC_GATE_CLK_MSK (((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS)
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#define PDS_CR_PDS_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS))
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#define PDS_CR_PDS_MISC_ANA_PWR_OFF PDS_CR_PDS_MISC_ANA_PWR_OFF
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#define PDS_CR_PDS_MISC_ANA_PWR_OFF_POS (30U)
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#define PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN (1U)
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#define PDS_CR_PDS_MISC_ANA_PWR_OFF_MSK (((1U << PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_ANA_PWR_OFF_POS)
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#define PDS_CR_PDS_MISC_ANA_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_ANA_PWR_OFF_POS))
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#define PDS_CR_PDS_MISC_DIG_PWR_OFF PDS_CR_PDS_MISC_DIG_PWR_OFF
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#define PDS_CR_PDS_MISC_DIG_PWR_OFF_POS (31U)
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#define PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN (1U)
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#define PDS_CR_PDS_MISC_DIG_PWR_OFF_MSK (((1U << PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_DIG_PWR_OFF_POS)
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#define PDS_CR_PDS_MISC_DIG_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_DIG_PWR_OFF_POS))
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/* 0x1C : pds_stat */
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#define PDS_STAT_OFFSET (0x1C)
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#define PDS_RO_PDS_STATE PDS_RO_PDS_STATE
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#define PDS_RO_PDS_STATE_POS (0U)
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#define PDS_RO_PDS_STATE_LEN (4U)
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#define PDS_RO_PDS_STATE_MSK (((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS)
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#define PDS_RO_PDS_STATE_UMSK (~(((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS))
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#define PDS_RO_PDS_RF_STATE PDS_RO_PDS_RF_STATE
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#define PDS_RO_PDS_RF_STATE_POS (8U)
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#define PDS_RO_PDS_RF_STATE_LEN (4U)
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#define PDS_RO_PDS_RF_STATE_MSK (((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS)
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#define PDS_RO_PDS_RF_STATE_UMSK (~(((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS))
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#define PDS_RO_PDS_PLL_STATE PDS_RO_PDS_PLL_STATE
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#define PDS_RO_PDS_PLL_STATE_POS (16U)
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#define PDS_RO_PDS_PLL_STATE_LEN (2U)
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#define PDS_RO_PDS_PLL_STATE_MSK (((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS)
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#define PDS_RO_PDS_PLL_STATE_UMSK (~(((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS))
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/* 0x20 : pds_ram1 */
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#define PDS_RAM1_OFFSET (0x20)
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#define PDS_CR_PDS_RAM_RET1N PDS_CR_PDS_RAM_RET1N
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#define PDS_CR_PDS_RAM_RET1N_POS (0U)
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#define PDS_CR_PDS_RAM_RET1N_LEN (4U)
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#define PDS_CR_PDS_RAM_RET1N_MSK (((1U << PDS_CR_PDS_RAM_RET1N_LEN) - 1) << PDS_CR_PDS_RAM_RET1N_POS)
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#define PDS_CR_PDS_RAM_RET1N_UMSK (~(((1U << PDS_CR_PDS_RAM_RET1N_LEN) - 1) << PDS_CR_PDS_RAM_RET1N_POS))
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#define PDS_CR_PDS_RAM_RET2N PDS_CR_PDS_RAM_RET2N
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#define PDS_CR_PDS_RAM_RET2N_POS (4U)
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#define PDS_CR_PDS_RAM_RET2N_LEN (4U)
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#define PDS_CR_PDS_RAM_RET2N_MSK (((1U << PDS_CR_PDS_RAM_RET2N_LEN) - 1) << PDS_CR_PDS_RAM_RET2N_POS)
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#define PDS_CR_PDS_RAM_RET2N_UMSK (~(((1U << PDS_CR_PDS_RAM_RET2N_LEN) - 1) << PDS_CR_PDS_RAM_RET2N_POS))
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#define PDS_CR_PDS_RAM_PGEN PDS_CR_PDS_RAM_PGEN
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#define PDS_CR_PDS_RAM_PGEN_POS (8U)
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#define PDS_CR_PDS_RAM_PGEN_LEN (4U)
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#define PDS_CR_PDS_RAM_PGEN_MSK (((1U << PDS_CR_PDS_RAM_PGEN_LEN) - 1) << PDS_CR_PDS_RAM_PGEN_POS)
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#define PDS_CR_PDS_RAM_PGEN_UMSK (~(((1U << PDS_CR_PDS_RAM_PGEN_LEN) - 1) << PDS_CR_PDS_RAM_PGEN_POS))
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/* 0x30 : pds_gpio_set_pu_pd */
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#define PDS_GPIO_SET_PU_PD_OFFSET (0x30)
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#define PDS_CR_PDS_GPIO_22_17_PD PDS_CR_PDS_GPIO_22_17_PD
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#define PDS_CR_PDS_GPIO_22_17_PD_POS (0U)
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#define PDS_CR_PDS_GPIO_22_17_PD_LEN (6U)
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#define PDS_CR_PDS_GPIO_22_17_PD_MSK (((1U << PDS_CR_PDS_GPIO_22_17_PD_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PD_POS)
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#define PDS_CR_PDS_GPIO_22_17_PD_UMSK (~(((1U << PDS_CR_PDS_GPIO_22_17_PD_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PD_POS))
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#define PDS_CR_PDS_GPIO_22_17_PU PDS_CR_PDS_GPIO_22_17_PU
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#define PDS_CR_PDS_GPIO_22_17_PU_POS (8U)
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#define PDS_CR_PDS_GPIO_22_17_PU_LEN (6U)
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#define PDS_CR_PDS_GPIO_22_17_PU_MSK (((1U << PDS_CR_PDS_GPIO_22_17_PU_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PU_POS)
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#define PDS_CR_PDS_GPIO_22_17_PU_UMSK (~(((1U << PDS_CR_PDS_GPIO_22_17_PU_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PU_POS))
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#define PDS_CR_PDS_GPIO_28_23_PD PDS_CR_PDS_GPIO_28_23_PD
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#define PDS_CR_PDS_GPIO_28_23_PD_POS (16U)
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#define PDS_CR_PDS_GPIO_28_23_PD_LEN (6U)
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#define PDS_CR_PDS_GPIO_28_23_PD_MSK (((1U << PDS_CR_PDS_GPIO_28_23_PD_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PD_POS)
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#define PDS_CR_PDS_GPIO_28_23_PD_UMSK (~(((1U << PDS_CR_PDS_GPIO_28_23_PD_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PD_POS))
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#define PDS_CR_PDS_GPIO_28_23_PU PDS_CR_PDS_GPIO_28_23_PU
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#define PDS_CR_PDS_GPIO_28_23_PU_POS (24U)
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#define PDS_CR_PDS_GPIO_28_23_PU_LEN (6U)
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#define PDS_CR_PDS_GPIO_28_23_PU_MSK (((1U << PDS_CR_PDS_GPIO_28_23_PU_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PU_POS)
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#define PDS_CR_PDS_GPIO_28_23_PU_UMSK (~(((1U << PDS_CR_PDS_GPIO_28_23_PU_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PU_POS))
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/* 0x40 : pds_gpio_int */
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#define PDS_GPIO_INT_OFFSET (0x40)
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#define PDS_GPIO_INT_MASK PDS_GPIO_INT_MASK
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#define PDS_GPIO_INT_MASK_POS (0U)
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#define PDS_GPIO_INT_MASK_LEN (1U)
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#define PDS_GPIO_INT_MASK_MSK (((1U << PDS_GPIO_INT_MASK_LEN) - 1) << PDS_GPIO_INT_MASK_POS)
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#define PDS_GPIO_INT_MASK_UMSK (~(((1U << PDS_GPIO_INT_MASK_LEN) - 1) << PDS_GPIO_INT_MASK_POS))
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#define PDS_GPIO_INT_STAT PDS_GPIO_INT_STAT
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#define PDS_GPIO_INT_STAT_POS (1U)
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#define PDS_GPIO_INT_STAT_LEN (1U)
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#define PDS_GPIO_INT_STAT_MSK (((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS)
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#define PDS_GPIO_INT_STAT_UMSK (~(((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS))
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#define PDS_GPIO_INT_CLR PDS_GPIO_INT_CLR
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#define PDS_GPIO_INT_CLR_POS (2U)
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#define PDS_GPIO_INT_CLR_LEN (1U)
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#define PDS_GPIO_INT_CLR_MSK (((1U << PDS_GPIO_INT_CLR_LEN) - 1) << PDS_GPIO_INT_CLR_POS)
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#define PDS_GPIO_INT_CLR_UMSK (~(((1U << PDS_GPIO_INT_CLR_LEN) - 1) << PDS_GPIO_INT_CLR_POS))
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#define PDS_GPIO_INT_MODE PDS_GPIO_INT_MODE
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#define PDS_GPIO_INT_MODE_POS (4U)
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#define PDS_GPIO_INT_MODE_LEN (3U)
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#define PDS_GPIO_INT_MODE_MSK (((1U << PDS_GPIO_INT_MODE_LEN) - 1) << PDS_GPIO_INT_MODE_POS)
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#define PDS_GPIO_INT_MODE_UMSK (~(((1U << PDS_GPIO_INT_MODE_LEN) - 1) << PDS_GPIO_INT_MODE_POS))
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#define PDS_GPIO_INT_SELECT PDS_GPIO_INT_SELECT
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#define PDS_GPIO_INT_SELECT_POS (8U)
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#define PDS_GPIO_INT_SELECT_LEN (3U)
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#define PDS_GPIO_INT_SELECT_MSK (((1U << PDS_GPIO_INT_SELECT_LEN) - 1) << PDS_GPIO_INT_SELECT_POS)
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#define PDS_GPIO_INT_SELECT_UMSK (~(((1U << PDS_GPIO_INT_SELECT_LEN) - 1) << PDS_GPIO_INT_SELECT_POS))
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/* 0x300 : rc32m_ctrl0 */
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#define PDS_RC32M_CTRL0_OFFSET (0x300)
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#define PDS_RC32M_CAL_DONE PDS_RC32M_CAL_DONE
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#define PDS_RC32M_CAL_DONE_POS (0U)
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#define PDS_RC32M_CAL_DONE_LEN (1U)
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#define PDS_RC32M_CAL_DONE_MSK (((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS)
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#define PDS_RC32M_CAL_DONE_UMSK (~(((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS))
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#define PDS_RC32M_RDY PDS_RC32M_RDY
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#define PDS_RC32M_RDY_POS (1U)
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#define PDS_RC32M_RDY_LEN (1U)
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#define PDS_RC32M_RDY_MSK (((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS)
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#define PDS_RC32M_RDY_UMSK (~(((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS))
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#define PDS_RC32M_CAL_INPROGRESS PDS_RC32M_CAL_INPROGRESS
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#define PDS_RC32M_CAL_INPROGRESS_POS (2U)
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#define PDS_RC32M_CAL_INPROGRESS_LEN (1U)
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#define PDS_RC32M_CAL_INPROGRESS_MSK (((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS)
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#define PDS_RC32M_CAL_INPROGRESS_UMSK (~(((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS))
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#define PDS_RC32M_CAL_DIV PDS_RC32M_CAL_DIV
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#define PDS_RC32M_CAL_DIV_POS (3U)
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#define PDS_RC32M_CAL_DIV_LEN (2U)
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#define PDS_RC32M_CAL_DIV_MSK (((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS)
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#define PDS_RC32M_CAL_DIV_UMSK (~(((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS))
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#define PDS_RC32M_CAL_PRECHARGE PDS_RC32M_CAL_PRECHARGE
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#define PDS_RC32M_CAL_PRECHARGE_POS (5U)
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#define PDS_RC32M_CAL_PRECHARGE_LEN (1U)
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#define PDS_RC32M_CAL_PRECHARGE_MSK (((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS)
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#define PDS_RC32M_CAL_PRECHARGE_UMSK (~(((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS))
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#define PDS_RC32M_DIG_CODE_FR_CAL PDS_RC32M_DIG_CODE_FR_CAL
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#define PDS_RC32M_DIG_CODE_FR_CAL_POS (6U)
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#define PDS_RC32M_DIG_CODE_FR_CAL_LEN (8U)
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#define PDS_RC32M_DIG_CODE_FR_CAL_MSK (((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS)
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#define PDS_RC32M_DIG_CODE_FR_CAL_UMSK (~(((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS))
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#define PDS_RC32M_ALLOW_CAL PDS_RC32M_ALLOW_CAL
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#define PDS_RC32M_ALLOW_CAL_POS (17U)
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#define PDS_RC32M_ALLOW_CAL_LEN (1U)
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#define PDS_RC32M_ALLOW_CAL_MSK (((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS)
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#define PDS_RC32M_ALLOW_CAL_UMSK (~(((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS))
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#define PDS_RC32M_REFCLK_HALF PDS_RC32M_REFCLK_HALF
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#define PDS_RC32M_REFCLK_HALF_POS (18U)
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#define PDS_RC32M_REFCLK_HALF_LEN (1U)
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#define PDS_RC32M_REFCLK_HALF_MSK (((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS)
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#define PDS_RC32M_REFCLK_HALF_UMSK (~(((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS))
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#define PDS_RC32M_EXT_CODE_EN PDS_RC32M_EXT_CODE_EN
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#define PDS_RC32M_EXT_CODE_EN_POS (19U)
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#define PDS_RC32M_EXT_CODE_EN_LEN (1U)
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#define PDS_RC32M_EXT_CODE_EN_MSK (((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS)
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#define PDS_RC32M_EXT_CODE_EN_UMSK (~(((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS))
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#define PDS_RC32M_CAL_EN PDS_RC32M_CAL_EN
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#define PDS_RC32M_CAL_EN_POS (20U)
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#define PDS_RC32M_CAL_EN_LEN (1U)
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#define PDS_RC32M_CAL_EN_MSK (((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS)
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#define PDS_RC32M_CAL_EN_UMSK (~(((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS))
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#define PDS_RC32M_PD PDS_RC32M_PD
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#define PDS_RC32M_PD_POS (21U)
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#define PDS_RC32M_PD_LEN (1U)
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#define PDS_RC32M_PD_MSK (((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS)
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#define PDS_RC32M_PD_UMSK (~(((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS))
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#define PDS_RC32M_CODE_FR_EXT PDS_RC32M_CODE_FR_EXT
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#define PDS_RC32M_CODE_FR_EXT_POS (22U)
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#define PDS_RC32M_CODE_FR_EXT_LEN (8U)
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#define PDS_RC32M_CODE_FR_EXT_MSK (((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS)
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#define PDS_RC32M_CODE_FR_EXT_UMSK (~(((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS))
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/* 0x304 : rc32m_ctrl1 */
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#define PDS_RC32M_CTRL1_OFFSET (0x304)
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#define PDS_RC32M_TEST_EN PDS_RC32M_TEST_EN
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#define PDS_RC32M_TEST_EN_POS (0U)
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#define PDS_RC32M_TEST_EN_LEN (1U)
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#define PDS_RC32M_TEST_EN_MSK (((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS)
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#define PDS_RC32M_TEST_EN_UMSK (~(((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS))
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#define PDS_RC32M_SOFT_RST PDS_RC32M_SOFT_RST
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#define PDS_RC32M_SOFT_RST_POS (1U)
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#define PDS_RC32M_SOFT_RST_LEN (1U)
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#define PDS_RC32M_SOFT_RST_MSK (((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS)
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#define PDS_RC32M_SOFT_RST_UMSK (~(((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS))
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#define PDS_RC32M_CLK_SOFT_RST PDS_RC32M_CLK_SOFT_RST
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#define PDS_RC32M_CLK_SOFT_RST_POS (2U)
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#define PDS_RC32M_CLK_SOFT_RST_LEN (1U)
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#define PDS_RC32M_CLK_SOFT_RST_MSK (((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS)
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#define PDS_RC32M_CLK_SOFT_RST_UMSK (~(((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS))
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#define PDS_RC32M_CLK_INV PDS_RC32M_CLK_INV
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#define PDS_RC32M_CLK_INV_POS (3U)
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#define PDS_RC32M_CLK_INV_LEN (1U)
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#define PDS_RC32M_CLK_INV_MSK (((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS)
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#define PDS_RC32M_CLK_INV_UMSK (~(((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS))
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#define PDS_RC32M_CLK_FORCE_ON PDS_RC32M_CLK_FORCE_ON
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#define PDS_RC32M_CLK_FORCE_ON_POS (4U)
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#define PDS_RC32M_CLK_FORCE_ON_LEN (1U)
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#define PDS_RC32M_CLK_FORCE_ON_MSK (((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS)
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#define PDS_RC32M_CLK_FORCE_ON_UMSK (~(((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS))
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#define PDS_RC32M_RESERVED PDS_RC32M_RESERVED
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#define PDS_RC32M_RESERVED_POS (24U)
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#define PDS_RC32M_RESERVED_LEN (8U)
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#define PDS_RC32M_RESERVED_MSK (((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS)
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#define PDS_RC32M_RESERVED_UMSK (~(((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS))
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/* 0x400 : pu_rst_clkpll */
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#define PDS_PU_RST_CLKPLL_OFFSET (0x400)
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#define PDS_CLKPLL_SDM_RESET PDS_CLKPLL_SDM_RESET
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#define PDS_CLKPLL_SDM_RESET_POS (0U)
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#define PDS_CLKPLL_SDM_RESET_LEN (1U)
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#define PDS_CLKPLL_SDM_RESET_MSK (((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS)
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#define PDS_CLKPLL_SDM_RESET_UMSK (~(((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS))
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#define PDS_CLKPLL_RESET_POSTDIV PDS_CLKPLL_RESET_POSTDIV
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#define PDS_CLKPLL_RESET_POSTDIV_POS (1U)
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#define PDS_CLKPLL_RESET_POSTDIV_LEN (1U)
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#define PDS_CLKPLL_RESET_POSTDIV_MSK (((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS)
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#define PDS_CLKPLL_RESET_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS))
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#define PDS_CLKPLL_RESET_FBDV PDS_CLKPLL_RESET_FBDV
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#define PDS_CLKPLL_RESET_FBDV_POS (2U)
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#define PDS_CLKPLL_RESET_FBDV_LEN (1U)
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#define PDS_CLKPLL_RESET_FBDV_MSK (((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS)
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#define PDS_CLKPLL_RESET_FBDV_UMSK (~(((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS))
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#define PDS_CLKPLL_RESET_REFDIV PDS_CLKPLL_RESET_REFDIV
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#define PDS_CLKPLL_RESET_REFDIV_POS (3U)
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#define PDS_CLKPLL_RESET_REFDIV_LEN (1U)
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#define PDS_CLKPLL_RESET_REFDIV_MSK (((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS)
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#define PDS_CLKPLL_RESET_REFDIV_UMSK (~(((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS))
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#define PDS_CLKPLL_PU_POSTDIV PDS_CLKPLL_PU_POSTDIV
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#define PDS_CLKPLL_PU_POSTDIV_POS (4U)
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#define PDS_CLKPLL_PU_POSTDIV_LEN (1U)
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#define PDS_CLKPLL_PU_POSTDIV_MSK (((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS)
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#define PDS_CLKPLL_PU_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS))
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#define PDS_CLKPLL_PU_FBDV PDS_CLKPLL_PU_FBDV
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#define PDS_CLKPLL_PU_FBDV_POS (5U)
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#define PDS_CLKPLL_PU_FBDV_LEN (1U)
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#define PDS_CLKPLL_PU_FBDV_MSK (((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS)
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#define PDS_CLKPLL_PU_FBDV_UMSK (~(((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS))
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#define PDS_CLKPLL_PU_CLAMP_OP PDS_CLKPLL_PU_CLAMP_OP
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#define PDS_CLKPLL_PU_CLAMP_OP_POS (6U)
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#define PDS_CLKPLL_PU_CLAMP_OP_LEN (1U)
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#define PDS_CLKPLL_PU_CLAMP_OP_MSK (((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS)
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#define PDS_CLKPLL_PU_CLAMP_OP_UMSK (~(((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS))
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#define PDS_CLKPLL_PU_PFD PDS_CLKPLL_PU_PFD
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#define PDS_CLKPLL_PU_PFD_POS (7U)
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#define PDS_CLKPLL_PU_PFD_LEN (1U)
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#define PDS_CLKPLL_PU_PFD_MSK (((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS)
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#define PDS_CLKPLL_PU_PFD_UMSK (~(((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS))
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#define PDS_CLKPLL_PU_CP PDS_CLKPLL_PU_CP
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#define PDS_CLKPLL_PU_CP_POS (8U)
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#define PDS_CLKPLL_PU_CP_LEN (1U)
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#define PDS_CLKPLL_PU_CP_MSK (((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS)
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#define PDS_CLKPLL_PU_CP_UMSK (~(((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS))
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#define PDS_PU_CLKPLL_SFREG PDS_PU_CLKPLL_SFREG
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#define PDS_PU_CLKPLL_SFREG_POS (9U)
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#define PDS_PU_CLKPLL_SFREG_LEN (1U)
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#define PDS_PU_CLKPLL_SFREG_MSK (((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS)
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#define PDS_PU_CLKPLL_SFREG_UMSK (~(((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS))
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#define PDS_PU_CLKPLL PDS_PU_CLKPLL
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#define PDS_PU_CLKPLL_POS (10U)
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#define PDS_PU_CLKPLL_LEN (1U)
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#define PDS_PU_CLKPLL_MSK (((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS)
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#define PDS_PU_CLKPLL_UMSK (~(((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS))
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/* 0x404 : clkpll_top_ctrl */
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#define PDS_CLKPLL_TOP_CTRL_OFFSET (0x404)
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#define PDS_CLKPLL_POSTDIV PDS_CLKPLL_POSTDIV
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#define PDS_CLKPLL_POSTDIV_POS (0U)
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#define PDS_CLKPLL_POSTDIV_LEN (7U)
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#define PDS_CLKPLL_POSTDIV_MSK (((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS)
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#define PDS_CLKPLL_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS))
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#define PDS_CLKPLL_REFDIV_RATIO PDS_CLKPLL_REFDIV_RATIO
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#define PDS_CLKPLL_REFDIV_RATIO_POS (8U)
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#define PDS_CLKPLL_REFDIV_RATIO_LEN (4U)
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#define PDS_CLKPLL_REFDIV_RATIO_MSK (((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS)
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#define PDS_CLKPLL_REFDIV_RATIO_UMSK (~(((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS))
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#define PDS_CLKPLL_XTAL_RC32M_SEL PDS_CLKPLL_XTAL_RC32M_SEL
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#define PDS_CLKPLL_XTAL_RC32M_SEL_POS (12U)
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#define PDS_CLKPLL_XTAL_RC32M_SEL_LEN (1U)
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#define PDS_CLKPLL_XTAL_RC32M_SEL_MSK (((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS)
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#define PDS_CLKPLL_XTAL_RC32M_SEL_UMSK (~(((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS))
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#define PDS_CLKPLL_REFCLK_SEL PDS_CLKPLL_REFCLK_SEL
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#define PDS_CLKPLL_REFCLK_SEL_POS (16U)
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#define PDS_CLKPLL_REFCLK_SEL_LEN (1U)
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#define PDS_CLKPLL_REFCLK_SEL_MSK (((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS)
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#define PDS_CLKPLL_REFCLK_SEL_UMSK (~(((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS))
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#define PDS_CLKPLL_VG11_SEL PDS_CLKPLL_VG11_SEL
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#define PDS_CLKPLL_VG11_SEL_POS (20U)
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#define PDS_CLKPLL_VG11_SEL_LEN (2U)
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#define PDS_CLKPLL_VG11_SEL_MSK (((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS)
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#define PDS_CLKPLL_VG11_SEL_UMSK (~(((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS))
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#define PDS_CLKPLL_RESV PDS_CLKPLL_RESV
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#define PDS_CLKPLL_RESV_POS (24U)
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#define PDS_CLKPLL_RESV_LEN (2U)
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#define PDS_CLKPLL_RESV_MSK (((1U << PDS_CLKPLL_RESV_LEN) - 1) << PDS_CLKPLL_RESV_POS)
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#define PDS_CLKPLL_RESV_UMSK (~(((1U << PDS_CLKPLL_RESV_LEN) - 1) << PDS_CLKPLL_RESV_POS))
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/* 0x408 : clkpll_cp */
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#define PDS_CLKPLL_CP_OFFSET (0x408)
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#define PDS_CLKPLL_SEL_CP_BIAS PDS_CLKPLL_SEL_CP_BIAS
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#define PDS_CLKPLL_SEL_CP_BIAS_POS (0U)
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#define PDS_CLKPLL_SEL_CP_BIAS_LEN (1U)
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#define PDS_CLKPLL_SEL_CP_BIAS_MSK (((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS)
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#define PDS_CLKPLL_SEL_CP_BIAS_UMSK (~(((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS))
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#define PDS_CLKPLL_ICP_5U PDS_CLKPLL_ICP_5U
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#define PDS_CLKPLL_ICP_5U_POS (4U)
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#define PDS_CLKPLL_ICP_5U_LEN (2U)
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#define PDS_CLKPLL_ICP_5U_MSK (((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS)
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#define PDS_CLKPLL_ICP_5U_UMSK (~(((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS))
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#define PDS_CLKPLL_ICP_1U PDS_CLKPLL_ICP_1U
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#define PDS_CLKPLL_ICP_1U_POS (6U)
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#define PDS_CLKPLL_ICP_1U_LEN (2U)
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#define PDS_CLKPLL_ICP_1U_MSK (((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS)
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#define PDS_CLKPLL_ICP_1U_UMSK (~(((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS))
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#define PDS_CLKPLL_INT_FRAC_SW PDS_CLKPLL_INT_FRAC_SW
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#define PDS_CLKPLL_INT_FRAC_SW_POS (8U)
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#define PDS_CLKPLL_INT_FRAC_SW_LEN (1U)
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#define PDS_CLKPLL_INT_FRAC_SW_MSK (((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS)
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#define PDS_CLKPLL_INT_FRAC_SW_UMSK (~(((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS))
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#define PDS_CLKPLL_CP_STARTUP_EN PDS_CLKPLL_CP_STARTUP_EN
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#define PDS_CLKPLL_CP_STARTUP_EN_POS (9U)
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#define PDS_CLKPLL_CP_STARTUP_EN_LEN (1U)
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#define PDS_CLKPLL_CP_STARTUP_EN_MSK (((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS)
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#define PDS_CLKPLL_CP_STARTUP_EN_UMSK (~(((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS))
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#define PDS_CLKPLL_CP_OPAMP_EN PDS_CLKPLL_CP_OPAMP_EN
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#define PDS_CLKPLL_CP_OPAMP_EN_POS (10U)
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#define PDS_CLKPLL_CP_OPAMP_EN_LEN (1U)
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#define PDS_CLKPLL_CP_OPAMP_EN_MSK (((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS)
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#define PDS_CLKPLL_CP_OPAMP_EN_UMSK (~(((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS))
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/* 0x40C : clkpll_rz */
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#define PDS_CLKPLL_RZ_OFFSET (0x40C)
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#define PDS_CLKPLL_C4_EN PDS_CLKPLL_C4_EN
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#define PDS_CLKPLL_C4_EN_POS (0U)
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#define PDS_CLKPLL_C4_EN_LEN (1U)
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#define PDS_CLKPLL_C4_EN_MSK (((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS)
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#define PDS_CLKPLL_C4_EN_UMSK (~(((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS))
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#define PDS_CLKPLL_R4 PDS_CLKPLL_R4
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#define PDS_CLKPLL_R4_POS (4U)
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#define PDS_CLKPLL_R4_LEN (2U)
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#define PDS_CLKPLL_R4_MSK (((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS)
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#define PDS_CLKPLL_R4_UMSK (~(((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS))
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#define PDS_CLKPLL_R4_SHORT PDS_CLKPLL_R4_SHORT
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#define PDS_CLKPLL_R4_SHORT_POS (8U)
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#define PDS_CLKPLL_R4_SHORT_LEN (1U)
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#define PDS_CLKPLL_R4_SHORT_MSK (((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS)
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#define PDS_CLKPLL_R4_SHORT_UMSK (~(((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS))
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#define PDS_CLKPLL_C3 PDS_CLKPLL_C3
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#define PDS_CLKPLL_C3_POS (12U)
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#define PDS_CLKPLL_C3_LEN (2U)
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#define PDS_CLKPLL_C3_MSK (((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS)
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#define PDS_CLKPLL_C3_UMSK (~(((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS))
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#define PDS_CLKPLL_CZ PDS_CLKPLL_CZ
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#define PDS_CLKPLL_CZ_POS (14U)
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#define PDS_CLKPLL_CZ_LEN (2U)
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#define PDS_CLKPLL_CZ_MSK (((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS)
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#define PDS_CLKPLL_CZ_UMSK (~(((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS))
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#define PDS_CLKPLL_RZ PDS_CLKPLL_RZ
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#define PDS_CLKPLL_RZ_POS (16U)
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#define PDS_CLKPLL_RZ_LEN (3U)
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#define PDS_CLKPLL_RZ_MSK (((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS)
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#define PDS_CLKPLL_RZ_UMSK (~(((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS))
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/* 0x410 : clkpll_fbdv */
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#define PDS_CLKPLL_FBDV_OFFSET (0x410)
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#define PDS_CLKPLL_SEL_SAMPLE_CLK PDS_CLKPLL_SEL_SAMPLE_CLK
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#define PDS_CLKPLL_SEL_SAMPLE_CLK_POS (0U)
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#define PDS_CLKPLL_SEL_SAMPLE_CLK_LEN (2U)
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#define PDS_CLKPLL_SEL_SAMPLE_CLK_MSK (((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS)
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#define PDS_CLKPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS))
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#define PDS_CLKPLL_SEL_FB_CLK PDS_CLKPLL_SEL_FB_CLK
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#define PDS_CLKPLL_SEL_FB_CLK_POS (2U)
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#define PDS_CLKPLL_SEL_FB_CLK_LEN (2U)
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#define PDS_CLKPLL_SEL_FB_CLK_MSK (((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS)
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#define PDS_CLKPLL_SEL_FB_CLK_UMSK (~(((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS))
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/* 0x414 : clkpll_vco */
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#define PDS_CLKPLL_VCO_OFFSET (0x414)
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#define PDS_CLKPLL_VCO_SPEED PDS_CLKPLL_VCO_SPEED
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#define PDS_CLKPLL_VCO_SPEED_POS (0U)
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#define PDS_CLKPLL_VCO_SPEED_LEN (3U)
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#define PDS_CLKPLL_VCO_SPEED_MSK (((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS)
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#define PDS_CLKPLL_VCO_SPEED_UMSK (~(((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS))
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#define PDS_CLKPLL_SHRTR PDS_CLKPLL_SHRTR
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#define PDS_CLKPLL_SHRTR_POS (3U)
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#define PDS_CLKPLL_SHRTR_LEN (1U)
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#define PDS_CLKPLL_SHRTR_MSK (((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS)
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#define PDS_CLKPLL_SHRTR_UMSK (~(((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS))
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/* 0x418 : clkpll_sdm */
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#define PDS_CLKPLL_SDM_OFFSET (0x418)
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#define PDS_CLKPLL_SDMIN PDS_CLKPLL_SDMIN
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#define PDS_CLKPLL_SDMIN_POS (0U)
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#define PDS_CLKPLL_SDMIN_LEN (24U)
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#define PDS_CLKPLL_SDMIN_MSK (((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS)
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#define PDS_CLKPLL_SDMIN_UMSK (~(((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS))
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#define PDS_CLKPLL_DITHER_SEL PDS_CLKPLL_DITHER_SEL
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#define PDS_CLKPLL_DITHER_SEL_POS (24U)
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#define PDS_CLKPLL_DITHER_SEL_LEN (2U)
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#define PDS_CLKPLL_DITHER_SEL_MSK (((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS)
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#define PDS_CLKPLL_DITHER_SEL_UMSK (~(((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS))
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#define PDS_CLKPLL_SDM_FLAG PDS_CLKPLL_SDM_FLAG
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#define PDS_CLKPLL_SDM_FLAG_POS (28U)
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#define PDS_CLKPLL_SDM_FLAG_LEN (1U)
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#define PDS_CLKPLL_SDM_FLAG_MSK (((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS)
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#define PDS_CLKPLL_SDM_FLAG_UMSK (~(((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS))
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#define PDS_CLKPLL_SDM_BYPASS PDS_CLKPLL_SDM_BYPASS
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#define PDS_CLKPLL_SDM_BYPASS_POS (29U)
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#define PDS_CLKPLL_SDM_BYPASS_LEN (1U)
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#define PDS_CLKPLL_SDM_BYPASS_MSK (((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS)
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#define PDS_CLKPLL_SDM_BYPASS_UMSK (~(((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS))
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/* 0x41C : clkpll_output_en */
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#define PDS_CLKPLL_OUTPUT_EN_OFFSET (0x41C)
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#define PDS_CLKPLL_EN_480M PDS_CLKPLL_EN_480M
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#define PDS_CLKPLL_EN_480M_POS (0U)
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#define PDS_CLKPLL_EN_480M_LEN (1U)
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#define PDS_CLKPLL_EN_480M_MSK (((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS)
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#define PDS_CLKPLL_EN_480M_UMSK (~(((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS))
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#define PDS_CLKPLL_EN_240M PDS_CLKPLL_EN_240M
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#define PDS_CLKPLL_EN_240M_POS (1U)
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#define PDS_CLKPLL_EN_240M_LEN (1U)
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#define PDS_CLKPLL_EN_240M_MSK (((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS)
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#define PDS_CLKPLL_EN_240M_UMSK (~(((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS))
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#define PDS_CLKPLL_EN_192M PDS_CLKPLL_EN_192M
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#define PDS_CLKPLL_EN_192M_POS (2U)
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#define PDS_CLKPLL_EN_192M_LEN (1U)
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#define PDS_CLKPLL_EN_192M_MSK (((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS)
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#define PDS_CLKPLL_EN_192M_UMSK (~(((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS))
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#define PDS_CLKPLL_EN_160M PDS_CLKPLL_EN_160M
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#define PDS_CLKPLL_EN_160M_POS (3U)
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#define PDS_CLKPLL_EN_160M_LEN (1U)
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#define PDS_CLKPLL_EN_160M_MSK (((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS)
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#define PDS_CLKPLL_EN_160M_UMSK (~(((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS))
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#define PDS_CLKPLL_EN_120M PDS_CLKPLL_EN_120M
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#define PDS_CLKPLL_EN_120M_POS (4U)
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#define PDS_CLKPLL_EN_120M_LEN (1U)
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#define PDS_CLKPLL_EN_120M_MSK (((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS)
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#define PDS_CLKPLL_EN_120M_UMSK (~(((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS))
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#define PDS_CLKPLL_EN_96M PDS_CLKPLL_EN_96M
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#define PDS_CLKPLL_EN_96M_POS (5U)
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#define PDS_CLKPLL_EN_96M_LEN (1U)
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#define PDS_CLKPLL_EN_96M_MSK (((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS)
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#define PDS_CLKPLL_EN_96M_UMSK (~(((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS))
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#define PDS_CLKPLL_EN_80M PDS_CLKPLL_EN_80M
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#define PDS_CLKPLL_EN_80M_POS (6U)
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#define PDS_CLKPLL_EN_80M_LEN (1U)
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#define PDS_CLKPLL_EN_80M_MSK (((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS)
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#define PDS_CLKPLL_EN_80M_UMSK (~(((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS))
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#define PDS_CLKPLL_EN_48M PDS_CLKPLL_EN_48M
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#define PDS_CLKPLL_EN_48M_POS (7U)
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#define PDS_CLKPLL_EN_48M_LEN (1U)
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#define PDS_CLKPLL_EN_48M_MSK (((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS)
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#define PDS_CLKPLL_EN_48M_UMSK (~(((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS))
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#define PDS_CLKPLL_EN_32M PDS_CLKPLL_EN_32M
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#define PDS_CLKPLL_EN_32M_POS (8U)
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#define PDS_CLKPLL_EN_32M_LEN (1U)
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#define PDS_CLKPLL_EN_32M_MSK (((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS)
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#define PDS_CLKPLL_EN_32M_UMSK (~(((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS))
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#define PDS_CLKPLL_EN_DIV2_480M PDS_CLKPLL_EN_DIV2_480M
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#define PDS_CLKPLL_EN_DIV2_480M_POS (9U)
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#define PDS_CLKPLL_EN_DIV2_480M_LEN (1U)
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#define PDS_CLKPLL_EN_DIV2_480M_MSK (((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS)
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#define PDS_CLKPLL_EN_DIV2_480M_UMSK (~(((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS))
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/* 0x420 : clkpll_test_enable */
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#define PDS_CLKPLL_TEST_ENABLE_OFFSET (0x420)
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#define PDS_DTEN_CLKPLL_POSTDIV_CLK PDS_DTEN_CLKPLL_POSTDIV_CLK
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#define PDS_DTEN_CLKPLL_POSTDIV_CLK_POS (0U)
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#define PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN (1U)
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#define PDS_DTEN_CLKPLL_POSTDIV_CLK_MSK (((1U << PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN) - 1) << PDS_DTEN_CLKPLL_POSTDIV_CLK_POS)
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#define PDS_DTEN_CLKPLL_POSTDIV_CLK_UMSK (~(((1U << PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN) - 1) << PDS_DTEN_CLKPLL_POSTDIV_CLK_POS))
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#define PDS_DTEN_CLK96M PDS_DTEN_CLK96M
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#define PDS_DTEN_CLK96M_POS (1U)
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#define PDS_DTEN_CLK96M_LEN (1U)
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#define PDS_DTEN_CLK96M_MSK (((1U << PDS_DTEN_CLK96M_LEN) - 1) << PDS_DTEN_CLK96M_POS)
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#define PDS_DTEN_CLK96M_UMSK (~(((1U << PDS_DTEN_CLK96M_LEN) - 1) << PDS_DTEN_CLK96M_POS))
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#define PDS_DTEN_CLK32M PDS_DTEN_CLK32M
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#define PDS_DTEN_CLK32M_POS (2U)
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#define PDS_DTEN_CLK32M_LEN (1U)
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#define PDS_DTEN_CLK32M_MSK (((1U << PDS_DTEN_CLK32M_LEN) - 1) << PDS_DTEN_CLK32M_POS)
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#define PDS_DTEN_CLK32M_UMSK (~(((1U << PDS_DTEN_CLK32M_LEN) - 1) << PDS_DTEN_CLK32M_POS))
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#define PDS_DTEN_CLKPLL_FSDM PDS_DTEN_CLKPLL_FSDM
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#define PDS_DTEN_CLKPLL_FSDM_POS (3U)
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#define PDS_DTEN_CLKPLL_FSDM_LEN (1U)
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#define PDS_DTEN_CLKPLL_FSDM_MSK (((1U << PDS_DTEN_CLKPLL_FSDM_LEN) - 1) << PDS_DTEN_CLKPLL_FSDM_POS)
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#define PDS_DTEN_CLKPLL_FSDM_UMSK (~(((1U << PDS_DTEN_CLKPLL_FSDM_LEN) - 1) << PDS_DTEN_CLKPLL_FSDM_POS))
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#define PDS_DTEN_CLKPLL_FREF PDS_DTEN_CLKPLL_FREF
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#define PDS_DTEN_CLKPLL_FREF_POS (4U)
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#define PDS_DTEN_CLKPLL_FREF_LEN (1U)
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#define PDS_DTEN_CLKPLL_FREF_MSK (((1U << PDS_DTEN_CLKPLL_FREF_LEN) - 1) << PDS_DTEN_CLKPLL_FREF_POS)
|
|
#define PDS_DTEN_CLKPLL_FREF_UMSK (~(((1U << PDS_DTEN_CLKPLL_FREF_LEN) - 1) << PDS_DTEN_CLKPLL_FREF_POS))
|
|
#define PDS_DTEN_CLKPLL_FIN PDS_DTEN_CLKPLL_FIN
|
|
#define PDS_DTEN_CLKPLL_FIN_POS (5U)
|
|
#define PDS_DTEN_CLKPLL_FIN_LEN (1U)
|
|
#define PDS_DTEN_CLKPLL_FIN_MSK (((1U << PDS_DTEN_CLKPLL_FIN_LEN) - 1) << PDS_DTEN_CLKPLL_FIN_POS)
|
|
#define PDS_DTEN_CLKPLL_FIN_UMSK (~(((1U << PDS_DTEN_CLKPLL_FIN_LEN) - 1) << PDS_DTEN_CLKPLL_FIN_POS))
|
|
#define PDS_TEN_CLKPLL_SFREG PDS_TEN_CLKPLL_SFREG
|
|
#define PDS_TEN_CLKPLL_SFREG_POS (6U)
|
|
#define PDS_TEN_CLKPLL_SFREG_LEN (1U)
|
|
#define PDS_TEN_CLKPLL_SFREG_MSK (((1U << PDS_TEN_CLKPLL_SFREG_LEN) - 1) << PDS_TEN_CLKPLL_SFREG_POS)
|
|
#define PDS_TEN_CLKPLL_SFREG_UMSK (~(((1U << PDS_TEN_CLKPLL_SFREG_LEN) - 1) << PDS_TEN_CLKPLL_SFREG_POS))
|
|
#define PDS_TEN_CLKPLL PDS_TEN_CLKPLL
|
|
#define PDS_TEN_CLKPLL_POS (7U)
|
|
#define PDS_TEN_CLKPLL_LEN (1U)
|
|
#define PDS_TEN_CLKPLL_MSK (((1U << PDS_TEN_CLKPLL_LEN) - 1) << PDS_TEN_CLKPLL_POS)
|
|
#define PDS_TEN_CLKPLL_UMSK (~(((1U << PDS_TEN_CLKPLL_LEN) - 1) << PDS_TEN_CLKPLL_POS))
|
|
#define PDS_CLKPLL_DC_TP_OUT_EN PDS_CLKPLL_DC_TP_OUT_EN
|
|
#define PDS_CLKPLL_DC_TP_OUT_EN_POS (8U)
|
|
#define PDS_CLKPLL_DC_TP_OUT_EN_LEN (1U)
|
|
#define PDS_CLKPLL_DC_TP_OUT_EN_MSK (((1U << PDS_CLKPLL_DC_TP_OUT_EN_LEN) - 1) << PDS_CLKPLL_DC_TP_OUT_EN_POS)
|
|
#define PDS_CLKPLL_DC_TP_OUT_EN_UMSK (~(((1U << PDS_CLKPLL_DC_TP_OUT_EN_LEN) - 1) << PDS_CLKPLL_DC_TP_OUT_EN_POS))
|
|
|
|
struct pds_reg {
|
|
/* 0x0 : PDS_CTL */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t pds_start_ps : 1; /* [ 0], w1p, 0x0 */
|
|
uint32_t cr_sleep_forever : 1; /* [ 1], r/w, 0x0 */
|
|
uint32_t cr_xtal_force_off : 1; /* [ 2], r/w, 0x0 */
|
|
uint32_t cr_wifi_pds_save_state : 1; /* [ 3], r/w, 0x0 */
|
|
uint32_t cr_pds_pd_dcdc18 : 1; /* [ 4], r/w, 0x0 */
|
|
uint32_t cr_pds_pd_bg_sys : 1; /* [ 5], r/w, 0x0 */
|
|
uint32_t cr_pds_ctrl_gpio_ie_pu_pd : 1; /* [ 6], r/w, 0x0 */
|
|
uint32_t cr_pds_ctrl_pu_flash : 1; /* [ 7], r/w, 0x0 */
|
|
uint32_t cr_pds_gate_clk : 1; /* [ 8], r/w, 0x1 */
|
|
uint32_t cr_pds_mem_stby : 1; /* [ 9], r/w, 0x1 */
|
|
uint32_t cr_sw_pu_flash : 1; /* [ 10], r/w, 0x1 */
|
|
uint32_t cr_pds_iso_en : 1; /* [ 11], r/w, 0x1 */
|
|
uint32_t cr_pds_wait_xtal_rdy : 1; /* [ 12], r/w, 0x0 */
|
|
uint32_t cr_pds_pwr_off : 1; /* [ 13], r/w, 0x1 */
|
|
uint32_t cr_pds_pd_xtal : 1; /* [ 14], r/w, 0x1 */
|
|
uint32_t cr_pds_soc_enb_force_on : 1; /* [ 15], r/w, 0x0 */
|
|
uint32_t cr_pds_rst_soc_en : 1; /* [ 16], r/w, 0x0 */
|
|
uint32_t cr_pds_rc32m_off_dis : 1; /* [ 17], r/w, 0x0 */
|
|
uint32_t cr_pds_ldo_vsel_en : 1; /* [ 18], r/w, 0x0 */
|
|
uint32_t cr_pds_ram_lp_with_clk_en : 1; /* [ 19], r/w, 0x0 */
|
|
uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */
|
|
uint32_t cr_np_wfi_mask : 1; /* [ 21], r/w, 0x0 */
|
|
uint32_t cr_pds_pd_ldo11 : 1; /* [ 22], r/w, 0x0 */
|
|
uint32_t cr_pds_force_ram_clk_en : 1; /* [ 23], r/w, 0x0 */
|
|
uint32_t cr_pds_ldo_vol : 4; /* [27:24], r/w, 0xa */
|
|
uint32_t cr_pds_ctrl_rf : 2; /* [29:28], r/w, 0x1 */
|
|
uint32_t cr_pds_ctrl_pll : 2; /* [31:30], r/w, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} PDS_CTL;
|
|
|
|
/* 0x4 : PDS_TIME1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t cr_sleep_duration : 32; /* [31: 0], r/w, 0xca8 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} PDS_TIME1;
|
|
|
|
/* 0x8 reserved */
|
|
uint8_t RESERVED0x8[4];
|
|
|
|
/* 0xC : PDS_INT */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t ro_pds_wake_int : 1; /* [ 0], r, 0x0 */
|
|
uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
|
|
uint32_t ro_pds_rf_done_int : 1; /* [ 2], r, 0x0 */
|
|
uint32_t ro_pds_pll_done_int : 1; /* [ 3], r, 0x0 */
|
|
uint32_t pds_reset_event : 3; /* [ 6: 4], r, 0x0 */
|
|
uint32_t pds_clr_reset_event : 1; /* [ 7], w, 0x0 */
|
|
uint32_t cr_pds_wake_int_mask : 1; /* [ 8], r/w, 0x0 */
|
|
uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */
|
|
uint32_t cr_pds_rf_done_int_mask : 1; /* [ 10], r/w, 0x0 */
|
|
uint32_t cr_pds_pll_done_int_mask : 1; /* [ 11], r/w, 0x0 */
|
|
uint32_t reserved_12_14 : 3; /* [14:12], rsvd, 0x0 */
|
|
uint32_t cr_pds_int_clr : 1; /* [ 15], r/w, 0x0 */
|
|
uint32_t cr_pds_wakeup_src_en : 8; /* [23:16], r/w, 0xff */
|
|
uint32_t ro_pds_wakeup_event : 8; /* [31:24], r, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} PDS_INT;
|
|
|
|
/* 0x10 : PDS_CTL2 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t cr_pds_force_np_pwr_off : 1; /* [ 0], r/w, 0x0 */
|
|
uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */
|
|
uint32_t cr_pds_force_bz_pwr_off : 1; /* [ 2], r/w, 0x0 */
|
|
uint32_t cr_pds_force_usb_pwr_off : 1; /* [ 3], r/w, 0x0 */
|
|
uint32_t cr_pds_force_np_iso_en : 1; /* [ 4], r/w, 0x0 */
|
|
uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */
|
|
uint32_t cr_pds_force_bz_iso_en : 1; /* [ 6], r/w, 0x0 */
|
|
uint32_t cr_pds_force_usb_iso_en : 1; /* [ 7], r/w, 0x0 */
|
|
uint32_t cr_pds_force_np_pds_rst : 1; /* [ 8], r/w, 0x0 */
|
|
uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */
|
|
uint32_t cr_pds_force_bz_pds_rst : 1; /* [ 10], r/w, 0x0 */
|
|
uint32_t cr_pds_force_usb_pds_rst : 1; /* [ 11], r/w, 0x0 */
|
|
uint32_t cr_pds_force_np_mem_stby : 1; /* [ 12], r/w, 0x0 */
|
|
uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */
|
|
uint32_t cr_pds_force_bz_mem_stby : 1; /* [ 14], r/w, 0x0 */
|
|
uint32_t cr_pds_force_usb_mem_stby : 1; /* [ 15], r/w, 0x0 */
|
|
uint32_t cr_pds_force_np_gate_clk : 1; /* [ 16], r/w, 0x0 */
|
|
uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */
|
|
uint32_t cr_pds_force_bz_gate_clk : 1; /* [ 18], r/w, 0x0 */
|
|
uint32_t cr_pds_force_usb_gate_clk : 1; /* [ 19], r/w, 0x0 */
|
|
uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} PDS_CTL2;
|
|
|
|
/* 0x14 : PDS_CTL3 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */
|
|
uint32_t cr_pds_force_misc_pwr_off : 1; /* [ 1], r/w, 0x0 */
|
|
uint32_t cr_pds_force_ble_pwr_off : 1; /* [ 2], r/w, 0x0 */
|
|
uint32_t reserved_3_4 : 2; /* [ 4: 3], rsvd, 0x0 */
|
|
uint32_t cr_pds_force_ble_iso_en : 1; /* [ 5], r/w, 0x0 */
|
|
uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */
|
|
uint32_t cr_pds_force_misc_pds_rst : 1; /* [ 7], r/w, 0x0 */
|
|
uint32_t cr_pds_force_ble_pds_rst : 1; /* [ 8], r/w, 0x0 */
|
|
uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */
|
|
uint32_t cr_pds_force_misc_mem_stby : 1; /* [ 10], r/w, 0x0 */
|
|
uint32_t cr_pds_force_ble_mem_stby : 1; /* [ 11], r/w, 0x0 */
|
|
uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */
|
|
uint32_t cr_pds_force_misc_gate_clk : 1; /* [ 13], r/w, 0x0 */
|
|
uint32_t cr_pds_force_ble_gate_clk : 1; /* [ 14], r/w, 0x0 */
|
|
uint32_t reserved_15_23 : 9; /* [23:15], rsvd, 0x0 */
|
|
uint32_t cr_pds_np_iso_en : 1; /* [ 24], r/w, 0x1 */
|
|
uint32_t reserved_25_26 : 2; /* [26:25], rsvd, 0x0 */
|
|
uint32_t cr_pds_bz_iso_en : 1; /* [ 27], r/w, 0x1 */
|
|
uint32_t cr_pds_ble_iso_en : 1; /* [ 28], r/w, 0x1 */
|
|
uint32_t cr_pds_usb_iso_en : 1; /* [ 29], r/w, 0x1 */
|
|
uint32_t cr_pds_misc_iso_en : 1; /* [ 30], r/w, 0x1 */
|
|
uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} PDS_CTL3;
|
|
|
|
/* 0x18 : PDS_CTL4 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t cr_pds_np_pwr_off : 1; /* [ 0], r/w, 0x1 */
|
|
uint32_t cr_pds_np_reset : 1; /* [ 1], r/w, 0x1 */
|
|
uint32_t cr_pds_np_mem_stby : 1; /* [ 2], r/w, 0x1 */
|
|
uint32_t cr_pds_np_gate_clk : 1; /* [ 3], r/w, 0x1 */
|
|
uint32_t reserved_4_11 : 8; /* [11: 4], rsvd, 0x0 */
|
|
uint32_t cr_pds_bz_pwr_off : 1; /* [ 12], r/w, 0x1 */
|
|
uint32_t cr_pds_bz_reset : 1; /* [ 13], r/w, 0x1 */
|
|
uint32_t cr_pds_bz_mem_stby : 1; /* [ 14], r/w, 0x1 */
|
|
uint32_t cr_pds_bz_gate_clk : 1; /* [ 15], r/w, 0x1 */
|
|
uint32_t cr_pds_ble_pwr_off : 1; /* [ 16], r/w, 0x1 */
|
|
uint32_t cr_pds_ble_reset : 1; /* [ 17], r/w, 0x1 */
|
|
uint32_t cr_pds_ble_mem_stby : 1; /* [ 18], r/w, 0x1 */
|
|
uint32_t cr_pds_ble_gate_clk : 1; /* [ 19], r/w, 0x1 */
|
|
uint32_t cr_pds_usb_pwr_off : 1; /* [ 20], r/w, 0x1 */
|
|
uint32_t cr_pds_usb_reset : 1; /* [ 21], r/w, 0x1 */
|
|
uint32_t cr_pds_usb_mem_stby : 1; /* [ 22], r/w, 0x1 */
|
|
uint32_t cr_pds_usb_gate_clk : 1; /* [ 23], r/w, 0x1 */
|
|
uint32_t cr_pds_misc_pwr_off : 1; /* [ 24], r/w, 0x1 */
|
|
uint32_t cr_pds_misc_reset : 1; /* [ 25], r/w, 0x1 */
|
|
uint32_t cr_pds_misc_mem_stby : 1; /* [ 26], r/w, 0x1 */
|
|
uint32_t cr_pds_misc_gate_clk : 1; /* [ 27], r/w, 0x1 */
|
|
uint32_t reserved_28_29 : 2; /* [29:28], rsvd, 0x0 */
|
|
uint32_t cr_pds_misc_ana_pwr_off : 1; /* [ 30], r/w, 0x1 */
|
|
uint32_t cr_pds_misc_dig_pwr_off : 1; /* [ 31], r/w, 0x1 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} PDS_CTL4;
|
|
|
|
/* 0x1C : pds_stat */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t ro_pds_state : 4; /* [ 3: 0], r, 0x0 */
|
|
uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
|
|
uint32_t ro_pds_rf_state : 4; /* [11: 8], r, 0x0 */
|
|
uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */
|
|
uint32_t ro_pds_pll_state : 2; /* [17:16], r, 0x0 */
|
|
uint32_t reserved_18_31 : 14; /* [31:18], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} pds_stat;
|
|
|
|
/* 0x20 : pds_ram1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t cr_pds_ram_ret1n : 4; /* [ 3: 0], r/w, 0xf */
|
|
uint32_t cr_pds_ram_ret2n : 4; /* [ 7: 4], r/w, 0x0 */
|
|
uint32_t cr_pds_ram_pgen : 4; /* [11: 8], r/w, 0x0 */
|
|
uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} pds_ram1;
|
|
|
|
/* 0x24 reserved */
|
|
uint8_t RESERVED0x24[12];
|
|
|
|
/* 0x30 : pds_gpio_set_pu_pd */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t cr_pds_gpio_22_17_pd : 6; /* [ 5: 0], r/w, 0x0 */
|
|
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
|
|
uint32_t cr_pds_gpio_22_17_pu : 6; /* [13: 8], r/w, 0x0 */
|
|
uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
|
|
uint32_t cr_pds_gpio_28_23_pd : 6; /* [21:16], r/w, 0x0 */
|
|
uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
|
|
uint32_t cr_pds_gpio_28_23_pu : 6; /* [29:24], r/w, 0x0 */
|
|
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} pds_gpio_set_pu_pd;
|
|
|
|
/* 0x34 reserved */
|
|
uint8_t RESERVED0x34[12];
|
|
|
|
/* 0x40 : pds_gpio_int */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t pds_gpio_int_mask : 1; /* [ 0], r/w, 0x1 */
|
|
uint32_t pds_gpio_int_stat : 1; /* [ 1], r, 0x0 */
|
|
uint32_t pds_gpio_int_clr : 1; /* [ 2], r/w, 0x0 */
|
|
uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */
|
|
uint32_t pds_gpio_int_mode : 3; /* [ 6: 4], r/w, 0x0 */
|
|
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
|
|
uint32_t pds_gpio_int_select : 3; /* [10: 8], r/w, 0x0 */
|
|
uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} pds_gpio_int;
|
|
|
|
/* 0x44 reserved */
|
|
uint8_t RESERVED0x44[700];
|
|
|
|
/* 0x300 : rc32m_ctrl0 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t rc32m_cal_done : 1; /* [ 0], r, 0x0 */
|
|
uint32_t rc32m_rdy : 1; /* [ 1], r, 0x0 */
|
|
uint32_t rc32m_cal_inprogress : 1; /* [ 2], r, 0x0 */
|
|
uint32_t rc32m_cal_div : 2; /* [ 4: 3], r/w, 0x3 */
|
|
uint32_t rc32m_cal_precharge : 1; /* [ 5], r, 0x0 */
|
|
uint32_t rc32m_dig_code_fr_cal : 8; /* [13: 6], r, 0x0 */
|
|
uint32_t reserved_14_16 : 3; /* [16:14], rsvd, 0x0 */
|
|
uint32_t rc32m_allow_cal : 1; /* [ 17], r/w, 0x0 */
|
|
uint32_t rc32m_refclk_half : 1; /* [ 18], r/w, 0x0 */
|
|
uint32_t rc32m_ext_code_en : 1; /* [ 19], r/w, 0x1 */
|
|
uint32_t rc32m_cal_en : 1; /* [ 20], r/w, 0x0 */
|
|
uint32_t rc32m_pd : 1; /* [ 21], r/w, 0x0 */
|
|
uint32_t rc32m_code_fr_ext : 8; /* [29:22], r/w, 0x60 */
|
|
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} rc32m_ctrl0;
|
|
|
|
/* 0x304 : rc32m_ctrl1 */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t rc32m_test_en : 1; /* [ 0], r/w, 0x0 */
|
|
uint32_t rc32m_soft_rst : 1; /* [ 1], r/w, 0x0 */
|
|
uint32_t rc32m_clk_soft_rst : 1; /* [ 2], r/w, 0x0 */
|
|
uint32_t rc32m_clk_inv : 1; /* [ 3], r/w, 0x0 */
|
|
uint32_t rc32m_clk_force_on : 1; /* [ 4], r/w, 0x0 */
|
|
uint32_t reserved_5_23 : 19; /* [23: 5], rsvd, 0x0 */
|
|
uint32_t rc32m_reserved : 8; /* [31:24], r/w, 0xf */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} rc32m_ctrl1;
|
|
|
|
/* 0x308 reserved */
|
|
uint8_t RESERVED0x308[248];
|
|
|
|
/* 0x400 : pu_rst_clkpll */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t clkpll_sdm_reset : 1; /* [ 0], r/w, 0x0 */
|
|
uint32_t clkpll_reset_postdiv : 1; /* [ 1], r/w, 0x0 */
|
|
uint32_t clkpll_reset_fbdv : 1; /* [ 2], r/w, 0x0 */
|
|
uint32_t clkpll_reset_refdiv : 1; /* [ 3], r/w, 0x0 */
|
|
uint32_t clkpll_pu_postdiv : 1; /* [ 4], r/w, 0x1 */
|
|
uint32_t clkpll_pu_fbdv : 1; /* [ 5], r/w, 0x1 */
|
|
uint32_t clkpll_pu_clamp_op : 1; /* [ 6], r/w, 0x1 */
|
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uint32_t clkpll_pu_pfd : 1; /* [ 7], r/w, 0x1 */
|
|
uint32_t clkpll_pu_cp : 1; /* [ 8], r/w, 0x1 */
|
|
uint32_t pu_clkpll_sfreg : 1; /* [ 9], r/w, 0x0 */
|
|
uint32_t pu_clkpll : 1; /* [ 10], r/w, 0x0 */
|
|
uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} pu_rst_clkpll;
|
|
|
|
/* 0x404 : clkpll_top_ctrl */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t clkpll_postdiv : 7; /* [ 6: 0], r/w, 0x14 */
|
|
uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */
|
|
uint32_t clkpll_refdiv_ratio : 4; /* [11: 8], r/w, 0x4 */
|
|
uint32_t clkpll_xtal_rc32m_sel : 1; /* [ 12], r/w, 0x0 */
|
|
uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */
|
|
uint32_t clkpll_refclk_sel : 1; /* [ 16], r/w, 0x0 */
|
|
uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */
|
|
uint32_t clkpll_vg11_sel : 2; /* [21:20], r/w, 0x1 */
|
|
uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
|
|
uint32_t clkpll_resv : 2; /* [25:24], r/w, 0x1 */
|
|
uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} clkpll_top_ctrl;
|
|
|
|
/* 0x408 : clkpll_cp */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t clkpll_sel_cp_bias : 1; /* [ 0], r/w, 0x1 */
|
|
uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
|
|
uint32_t clkpll_icp_5u : 2; /* [ 5: 4], r/w, 0x0 */
|
|
uint32_t clkpll_icp_1u : 2; /* [ 7: 6], r/w, 0x1 */
|
|
uint32_t clkpll_int_frac_sw : 1; /* [ 8], r/w, 0x1 */
|
|
uint32_t clkpll_cp_startup_en : 1; /* [ 9], r/w, 0x1 */
|
|
uint32_t clkpll_cp_opamp_en : 1; /* [ 10], r/w, 0x1 */
|
|
uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} clkpll_cp;
|
|
|
|
/* 0x40C : clkpll_rz */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t clkpll_c4_en : 1; /* [ 0], r/w, 0x0 */
|
|
uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
|
|
uint32_t clkpll_r4 : 2; /* [ 5: 4], r/w, 0x2 */
|
|
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
|
|
uint32_t clkpll_r4_short : 1; /* [ 8], r/w, 0x0 */
|
|
uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */
|
|
uint32_t clkpll_c3 : 2; /* [13:12], r/w, 0x2 */
|
|
uint32_t clkpll_cz : 2; /* [15:14], r/w, 0x2 */
|
|
uint32_t clkpll_rz : 3; /* [18:16], r/w, 0x5 */
|
|
uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} clkpll_rz;
|
|
|
|
/* 0x410 : clkpll_fbdv */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t clkpll_sel_sample_clk : 2; /* [ 1: 0], r/w, 0x1 */
|
|
uint32_t clkpll_sel_fb_clk : 2; /* [ 3: 2], r/w, 0x1 */
|
|
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} clkpll_fbdv;
|
|
|
|
/* 0x414 : clkpll_vco */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t clkpll_vco_speed : 3; /* [ 2: 0], r/w, 0x6 */
|
|
uint32_t clkpll_shrtr : 1; /* [ 3], r/w, 0x0 */
|
|
uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} clkpll_vco;
|
|
|
|
/* 0x418 : clkpll_sdm */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t clkpll_sdmin : 24; /* [23: 0], r/w, 0x600000 */
|
|
uint32_t clkpll_dither_sel : 2; /* [25:24], r/w, 0x0 */
|
|
uint32_t reserved_26_27 : 2; /* [27:26], rsvd, 0x0 */
|
|
uint32_t clkpll_sdm_flag : 1; /* [ 28], r/w, 0x1 */
|
|
uint32_t clkpll_sdm_bypass : 1; /* [ 29], r/w, 0x0 */
|
|
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} clkpll_sdm;
|
|
|
|
/* 0x41C : clkpll_output_en */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t clkpll_en_480m : 1; /* [ 0], r/w, 0x0 */
|
|
uint32_t clkpll_en_240m : 1; /* [ 1], r/w, 0x0 */
|
|
uint32_t clkpll_en_192m : 1; /* [ 2], r/w, 0x0 */
|
|
uint32_t clkpll_en_160m : 1; /* [ 3], r/w, 0x0 */
|
|
uint32_t clkpll_en_120m : 1; /* [ 4], r/w, 0x0 */
|
|
uint32_t clkpll_en_96m : 1; /* [ 5], r/w, 0x0 */
|
|
uint32_t clkpll_en_80m : 1; /* [ 6], r/w, 0x0 */
|
|
uint32_t clkpll_en_48m : 1; /* [ 7], r/w, 0x0 */
|
|
uint32_t clkpll_en_32m : 1; /* [ 8], r/w, 0x1 */
|
|
uint32_t clkpll_en_div2_480m : 1; /* [ 9], r/w, 0x0 */
|
|
uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} clkpll_output_en;
|
|
|
|
/* 0x420 : clkpll_test_enable */
|
|
union {
|
|
struct
|
|
{
|
|
uint32_t dten_clkpll_postdiv_clk : 1; /* [ 0], r/w, 0x0 */
|
|
uint32_t dten_clk96M : 1; /* [ 1], r/w, 0x0 */
|
|
uint32_t dten_clk32M : 1; /* [ 2], r/w, 0x0 */
|
|
uint32_t dten_clkpll_fsdm : 1; /* [ 3], r/w, 0x0 */
|
|
uint32_t dten_clkpll_fref : 1; /* [ 4], r/w, 0x0 */
|
|
uint32_t dten_clkpll_fin : 1; /* [ 5], r/w, 0x0 */
|
|
uint32_t ten_clkpll_sfreg : 1; /* [ 6], r/w, 0x0 */
|
|
uint32_t ten_clkpll : 1; /* [ 7], r/w, 0x0 */
|
|
uint32_t clkpll_dc_tp_out_en : 1; /* [ 8], r/w, 0x0 */
|
|
uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */
|
|
} BF;
|
|
uint32_t WORD;
|
|
} clkpll_test_enable;
|
|
};
|
|
|
|
typedef volatile struct pds_reg pds_reg_t;
|
|
|
|
#endif /* __PDS_REG_H__ */
|