178 lines
5.5 KiB
C
178 lines
5.5 KiB
C
/**
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* @file system_bl702.c
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* @brief
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*
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* Copyright (c) 2021 Bouffalolab team
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*/
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#include "bl702.h"
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#include "bl702_glb.h"
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#include "bl702_hbn.h"
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#include "system_bl702.h"
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#ifdef BOOTROM
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#include "bflb_bootrom.h"
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#endif
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#ifdef BFLB_EFLASH_LOADER
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#include "bl702_usb.h"
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void USB_DoNothing_IRQHandler(void)
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{
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/* clear all USB int sts */
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USB_Clr_IntStatus(32);
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}
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#endif
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/*----------------------------------------------------------------------------
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Define clocks
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*----------------------------------------------------------------------------*/
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#define SYSTEM_CLOCK ( 32000000UL )
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/*----------------------------------------------------------------------------
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Vector Table
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*----------------------------------------------------------------------------*/
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#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/*----------------------------------------------------------------------------
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System initialization function
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*----------------------------------------------------------------------------*/
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void system_bor_init(void)
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{
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HBN_BOR_CFG_Type borCfg = {1/* pu_bor */, 0/* irq_bor_en */, 1/* bor_vth */, 1/* bor_sel */};
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HBN_Set_BOR_Cfg(&borCfg);
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}
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void SystemInit (void)
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{
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uint32_t *p;
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uint32_t i=0;
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uint32_t tmpVal=0;
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#ifdef BOOTROM
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extern void GLB_Power_On_LDO18_IO(void);
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extern void WDT_Disable(void);
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extern void HBN_Clear_RTC_INT(void);
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BMX_Cfg_Type bmxCfg={
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.timeoutEn=0,
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.errEn=DISABLE,
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.arbMod=BMX_ARB_FIX
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};
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L1C_BMX_Cfg_Type l1cBmxCfg={
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.timeoutEn=0,
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.errEn=DISABLE,
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.arbMod=L1C_BMX_ARB_FIX,
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};
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/* NP boot log Flag */
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p= (uint32_t *)(BFLB_BOOTROM_NP_BOOT_LOG_ADDR);
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*p=0x5A5AA5A5;
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/*diable BMX error incase Sbooten=0xf,while user send vector(core) reset and CPU read deadbeef,
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if not disable this bit, CPU will also get hardfault at the same time*/
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//GLB->bmx_cfg1.BF.bmx_err_en=0;
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//GLB->bmx_cfg1.BF.bmx_timeout_en=0;
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//GLB->bmx_cfg2.BF.bmx_err_addr_dis=1;
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GLB_BMX_Init(&bmxCfg);
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GLB_BMX_Addr_Monitor_Disable();
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//L1C->l1c_config.BF.l1c_bmx_err_en=0;
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//L1C->l1c_config.BF.l1c_bmx_timeout_en=0;
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//L1C->l1c_bmx_err_addr_en.BF.l1c_bmx_err_addr_dis=1;
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L1C_BMX_Init(&l1cBmxCfg);
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L1C_BMX_Addr_Monitor_Disable();
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//L1C->l1c_config.BF.l1c_way_dis=0xf;
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L1C_Set_Way_Disable(0x0f);
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/* Disable Watchdog */
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WDT_Disable();
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/* Clear RTC */
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HBN_Clear_RTC_INT();
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/* Make OCRAM Idle from retention or sleep */
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GLB_Set_OCRAM_Idle();
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/* Disable embedded flash power up*/
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HBN_Set_Embedded_Flash_Pullup(DISABLE);
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#endif
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/* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
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tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE);
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tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_REG_EN_HW_PU_PD);
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BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmpVal);
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/* disable aon_pad_ie_smt (reg_aon_pad_ie_smt = 0) */
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tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE);
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tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_REG_AON_PAD_IE_SMT);
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BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmpVal);
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/* GLB_Set_EM_Sel(GLB_EM_0KB); */
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tmpVal=BL_RD_REG(GLB_BASE,GLB_SEAM_MISC);
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tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_EM_SEL,GLB_EM_0KB);
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BL_WR_REG(GLB_BASE,GLB_SEAM_MISC,tmpVal);
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/* Restore default setting*/
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/* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
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tmpVal=BL_RD_REG(GLB_BASE,GLB_PARM);
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tmpVal=BL_SET_REG_BITS_VAL(tmpVal,GLB_UART_SWAP_SET,UART_SIG_SWAP_NONE);
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BL_WR_REG(GLB_BASE,GLB_PARM,tmpVal);
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// GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE);
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// /* update SystemCoreClock value */
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// SystemCoreClockSet(SYSTEM_CLOCK);
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/* fix 57.6M */
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if(SystemCoreClockGet()==57*6000*1000){
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SystemCoreClockSet(57.6*1000*1000)
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}
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/* CLear all interrupt */
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p=(uint32_t *)(CLIC_HART0_ADDR+CLIC_INTIE);
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for(i=0;i<(IRQn_LAST+3)/4;i++){
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p[i]=0;
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}
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p=(uint32_t *)(CLIC_HART0_ADDR+CLIC_INTIP);
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for(i=0;i<(IRQn_LAST+3)/4;i++){
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p[i]=0;
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}
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#ifdef BFLB_EFLASH_LOADER
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Interrupt_Handler_Register(USB_IRQn,USB_DoNothing_IRQHandler);
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#endif
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/* global IRQ enable */
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__enable_irq();
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/* init bor for all platform */
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system_bor_init();
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#ifdef BOOTROM
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/*Power up soc 11 power domain,TODO: This should be optional */
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//AON_Power_On_SOC_11();
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/* Record LDO18 pu flag before power up. This maybe not neccessary but copy from 606*/
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//BL_WR_WORD(BFLB_BOOTROM_AP_BOOT_LOG_ADDR,GLB->ldo18io.BF.pu_ldo18io);
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/* Power up flash power*/
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//GLB_Power_On_LDO18_IO();
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#endif
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/* release 64K OCARAM for appliction */
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GLB_Set_EM_Sel(GLB_EM_0KB);
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}
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void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
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{
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}
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