150 lines
4.2 KiB
C
Executable File
150 lines
4.2 KiB
C
Executable File
#include "bflb_mtimer.h"
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#include "bflb_i2s.h"
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#include "bflb_dma.h"
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#include "bflb_gpio.h"
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#include "board.h"
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#include "bflb_clock.h"
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#define I2S_CHANMEL_MERGE_ENABLE 1
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struct bflb_device_s *i2s0;
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struct bflb_device_s *dma0_ch0;
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struct bflb_device_s *dma0_ch1;
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static ATTR_NOCACHE_NOINIT_RAM_SECTION uint16_t tx_buffer[256] __ALIGNED(4);
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static ATTR_NOCACHE_NOINIT_RAM_SECTION uint16_t rx_buffer[256] __ALIGNED(4);
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static volatile uint8_t dma_tc_flag0 = 0;
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static volatile uint8_t dma_tc_flag1 = 0;
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void dma0_ch0_isr(void *arg)
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{
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dma_tc_flag0++;
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printf("tc done\r\n");
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}
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void dma0_ch1_isr(void *arg)
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{
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dma_tc_flag1++;
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printf("rx done\r\n");
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}
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void sram_init()
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{
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uint32_t i;
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for (i = 0; i < 256; i++) {
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tx_buffer[i] = i;
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rx_buffer[i] = 0;
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}
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}
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int main(void)
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{
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struct bflb_dma_channel_lli_pool_s tx_llipool[1];
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struct bflb_dma_channel_lli_transfer_s tx_transfers[1];
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struct bflb_dma_channel_lli_pool_s rx_llipool[1];
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struct bflb_dma_channel_lli_transfer_s rx_transfers[1];
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uint32_t num;
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struct bflb_i2s_config_s i2s_cfg = {
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.bclk_freq_hz = 32000 * 16 * 2, /* bclk = Sampling_rate * frame_width * channel_num */
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.role = I2S_ROLE_MASTER,
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.format_mode = I2S_MODE_LEFT_JUSTIFIED,
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.channel_mode = I2S_CHANNEL_MODE_NUM_2,
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.frame_width = I2S_SLOT_WIDTH_16,
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.data_width = I2S_SLOT_WIDTH_16,
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.fs_offset_cycle = 0,
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.tx_fifo_threshold = 0,
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.rx_fifo_threshold = 0,
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};
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struct bflb_dma_channel_config_s tx_config = {
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.direction = DMA_MEMORY_TO_PERIPH,
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.src_req = DMA_REQUEST_NONE,
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.dst_req = DMA_REQUEST_I2S_TX,
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.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE,
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.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE,
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.src_burst_count = DMA_BURST_INCR1,
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.dst_burst_count = DMA_BURST_INCR1,
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#if I2S_CHANMEL_MERGE_ENABLE
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.src_width = DMA_DATA_WIDTH_32BIT,
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.dst_width = DMA_DATA_WIDTH_32BIT,
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#else
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.src_width = DMA_DATA_WIDTH_16BIT,
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.dst_width = DMA_DATA_WIDTH_16BIT,
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#endif
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};
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struct bflb_dma_channel_config_s rx_config = {
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.direction = DMA_PERIPH_TO_MEMORY,
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.src_req = DMA_REQUEST_I2S_RX,
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.dst_req = DMA_REQUEST_NONE,
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.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE,
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.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE,
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.src_burst_count = DMA_BURST_INCR1,
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.dst_burst_count = DMA_BURST_INCR1,
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#if I2S_CHANMEL_MERGE_ENABLE
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.src_width = DMA_DATA_WIDTH_32BIT,
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.dst_width = DMA_DATA_WIDTH_32BIT,
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#else
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.src_width = DMA_DATA_WIDTH_16BIT,
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.dst_width = DMA_DATA_WIDTH_16BIT,
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#endif
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};
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board_init();
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sram_init();
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/* gpio init */
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board_i2s_gpio_init();
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i2s0 = bflb_device_get_by_name("i2s0");
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/* i2s init */
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bflb_i2s_init(i2s0, &i2s_cfg);
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/* enable dma */
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bflb_i2s_link_txdma(i2s0, true);
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bflb_i2s_link_rxdma(i2s0, true);
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printf("\n\ri2s dma test\n\r");
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dma0_ch0 = bflb_device_get_by_name("dma0_ch0");
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dma0_ch1 = bflb_device_get_by_name("dma0_ch1");
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bflb_dma_channel_init(dma0_ch0, &tx_config);
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bflb_dma_channel_init(dma0_ch1, &rx_config);
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bflb_dma_channel_irq_attach(dma0_ch0, dma0_ch0_isr, NULL);
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bflb_dma_channel_irq_attach(dma0_ch1, dma0_ch1_isr, NULL);
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tx_transfers[0].src_addr = (uint32_t)tx_buffer;
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tx_transfers[0].dst_addr = (uint32_t)DMA_ADDR_I2S_TDR;
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tx_transfers[0].nbytes = sizeof(tx_buffer);
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rx_transfers[0].src_addr = (uint32_t)DMA_ADDR_I2S_RDR;
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rx_transfers[0].dst_addr = (uint32_t)rx_buffer;
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rx_transfers[0].nbytes = sizeof(rx_buffer);
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num = bflb_dma_channel_lli_reload(dma0_ch0, tx_llipool, 1, tx_transfers, 1);
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bflb_dma_channel_lli_link_head(dma0_ch0, tx_llipool, num);
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num = bflb_dma_channel_lli_reload(dma0_ch1, rx_llipool, 1, rx_transfers, 1);
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bflb_dma_channel_lli_link_head(dma0_ch1, tx_llipool, num);
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bflb_dma_channel_start(dma0_ch0);
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bflb_dma_channel_start(dma0_ch1);
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#if I2S_CHANMEL_MERGE_ENABLE
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/* enable channel merge */
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bflb_i2s_feature_control(i2s0, I2S_CMD_CHANNEL_LR_MERGE, true);
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#endif
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/* enable i2s tx and rx */
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bflb_i2s_feature_control(i2s0, I2S_CMD_DATA_ENABLE, I2S_CMD_DATA_ENABLE_TX | I2S_CMD_DATA_ENABLE_RX);
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printf("\n\rtest end\n\r");
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while (1) {
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}
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}
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