# SiPEED USB-JTAG/TTL based on FT2232D
interface ftdi
ftdi_vid_pid 0x0403 0x6010
# http://blog.sipeed.com/p/727.html
ftdi_channel 0
transport select jtag
adapter_khz     10000

ftdi_layout_init 0x0508 0x0f1b
ftdi_layout_signal nTRST -data 0x0200 -noe 0x0100
ftdi_layout_signal nSRST -data 0x0800 -noe 0x0400

set _CHIPNAME riscv
#jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x0

set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
#$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
#$_TARGETNAME.0 configure -work-area-phys 0x50000000 -work-area-size 32768 -work-area-backup 0

echo "SiPEED USB-JTAG/TTL Ready for Remote Connections"

proc install_bootrom {} {
#    sleep 1000
    init
    reset init
    load_image chiptest_bootrom.bin 0x21000000 bin
    sleep 500
    reg pc 0x21000000
#    sleep 500
#    bp 0x21002f0c 4 hw
#    resume
}

echo "Start loading BOOTROM under project folder"
install_bootrom
echo "flash the XIP code before debugging"
echo "ONLY load symbol in GDB"
echo "use [gdb_breakpoint_override hard] for XIP debugging"