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[update][drivers] update drivers

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This commit is contained in:
jzlv 2022-02-23 17:03:42 +08:00
parent c9a587c430
commit ffdd9d7053
14 changed files with 107 additions and 70 deletions
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2
drivers/bl602_driver/std_drv/inc/bl602_uart.h
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@ -287,7 +287,7 @@ BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length);
BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length);
BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time);
BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt);
BL_Err_Type UART_SetBaudrate(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet);
BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet);
BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId);
BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId);
BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun);

2
drivers/bl602_driver/std_drv/src/bl602_uart.c
View File

@ -591,7 +591,7 @@ BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt)
* @return SUCCESS
*
*******************************************************************************/
BL_Err_Type UART_SetBaudrate(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet)
BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet)
{
uint32_t UARTx = uartAddr[uartId];
uint16_t tmpVal;

3
drivers/bl702_driver/hal_drv/inc/hal_adc.h
View File

@ -99,7 +99,7 @@ typedef enum {
typedef enum {
ADC_DATA_WIDTH_12B, /*!< ADC 12 bits */
ADC_DATA_WIDTH_14B_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */
ADC_DATA_WIDTH_16B_WITH_64_AVERAGE, /*!< ADC 16 bits,and the value is average of 64 converts */
ADC_DATA_WIDTH_14B_WITH_64_AVERAGE, /*!< ADC 14 bits,and the value is average of 64 converts */
ADC_DATA_WIDTH_16B_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */
ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */
} adc_data_width_t;
@ -162,6 +162,7 @@ typedef struct adc_device {
adc_data_width_t data_width;
adc_fifo_threshold_t fifo_threshold;
adc_pga_gain_t gain;
void* rx_dma;
} adc_device_t;
#define ADC_DEV(dev) ((adc_device_t *)dev)

9
drivers/bl702_driver/hal_drv/inc/hal_spi.h
View File

@ -31,8 +31,17 @@ extern "C" {
#include "drv_device.h"
#include "bl702_config.h"
#define SPI_FIFO_LEN 4
#define DEVICE_CTRL_SPI_CONFIG_CLOCK 0x10
#define DEVICE_CTRL_SPI_GET_TX_FIFO 0x11
#define DEVICE_CTRL_SPI_GET_RX_FIFO 0x12
#define DEVICE_CTRL_SPI_CLEAR_TX_FIFO 0x13
#define DEVICE_CTRL_SPI_CLEAR_RX_FIFO 0x14
#define DEVICE_CTRL_SPI_GET_BUS_BUSY_STATUS 0x15
enum spi_index_type {
#ifdef BSP_USING_SPI0
SPI0_INDEX,

19
drivers/bl702_driver/hal_drv/src/hal_adc.c
View File

@ -22,6 +22,7 @@
*/
#include "hal_adc.h"
#include "hal_clock.h"
#include "hal_dma.h"
#include "bl702_glb.h"
#include "bl702_dma.h"
#include "bl702_adc.h"
@ -278,7 +279,9 @@ int adc_control(struct device *dev, int cmd, void *args)
case DEVICE_CTRL_ADC_TSEN_OFF:
break;
case DEVICE_CTRL_ATTACH_RX_DMA :
adc_device->rx_dma = (struct device *)args;
break;
default:
break;
}
@ -302,6 +305,8 @@ int adc_control(struct device *dev, int cmd, void *args)
int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
uint32_t adc_fifo_val[32];
int ret = -1;
adc_device_t *adc_device = (adc_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_STREAM_RX) {
if (size > 32)
@ -315,9 +320,17 @@ int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
adc_channel_val_t *adc_parse_val = (adc_channel_val_t *)buffer;
ADC_Parse_Result(adc_fifo_val, size, (ADC_Result_Type *)adc_parse_val);
return size;
}
} else if (dev->oflag & DEVICE_OFLAG_DMA_RX) {
struct device *dma_ch = (struct device *)adc_device->rx_dma;
if (!dma_ch)
return -1;
return 0;
ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_ADC_RDR, (uint32_t)buffer, size);
dma_channel_start(dma_ch);
return ret;
}
return ret;
}
int adc_trim_tsen(uint16_t *tsen_offset)

6
drivers/bl702_driver/hal_drv/src/hal_dma.c
View File

@ -280,6 +280,9 @@ int dma_allocate_register(const char *name)
*/
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size)
{
#if defined(BSP_USING_DMA0_CH0) || defined(BSP_USING_DMA0_CH1) || defined(BSP_USING_DMA0_CH2) || defined(BSP_USING_DMA0_CH3) || \
defined(BSP_USING_DMA0_CH4) || defined(BSP_USING_DMA0_CH5) || defined(BSP_USING_DMA0_CH6) || defined(BSP_USING_DMA0_CH7)
uint32_t malloc_count;
uint32_t remain_len;
uint32_t actual_transfer_len = 0;
@ -365,7 +368,6 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
}
dma_device->lli_cfg[i].cfg = dma_ctrl_cfg;
}
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_SRCADDR, dma_device->lli_cfg[0].src_addr);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_DSTADDR, dma_device->lli_cfg[0].dst_addr);
@ -374,7 +376,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
} else {
return -2;
}
#endif
return 0;
}

13
drivers/bl702_driver/hal_drv/src/hal_pm.c
View File

@ -26,6 +26,7 @@
#include "hal_clock.h"
#include "hal_rtc.h"
#include "hal_flash.h"
#include "risc-v/Core/Include/clic.h"
/* Cache Way Disable, will get from l1c register */
uint8_t cacheWayDisable = 0;
@ -1163,12 +1164,6 @@ ATTR_TCM_SECTION void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8
/* To make it simple and safe*/
cpu_global_irq_disable();
CPU_Interrupt_Pending_Clear(HBN_OUT0_IRQn);
CPU_Interrupt_Pending_Clear(HBN_OUT1_IRQn);
BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);
if (sleep_time && (hbn_level < PM_HBN_LEVEL_2))
rtc_init(sleep_time); //sleep time,unit is second
@ -1226,6 +1221,12 @@ ATTR_TCM_SECTION void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8
tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + HBN_OUT0_IRQn) = 0;
*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + HBN_OUT1_IRQn) = 0;
BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);
/* Enable HBN mode */
tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);

15
drivers/bl702_driver/hal_drv/src/hal_spi.c
View File

@ -234,6 +234,21 @@ int spi_control(struct device *dev, int cmd, void *args)
break;
}
case DEVICE_CTRL_SPI_GET_TX_FIFO :
return SPI_GetTxFifoCount(spi_device->id);
case DEVICE_CTRL_SPI_GET_RX_FIFO :
return SPI_GetRxFifoCount(spi_device->id);
case DEVICE_CTRL_SPI_CLEAR_TX_FIFO :
return SPI_ClrTxFifo(spi_device->id);
case DEVICE_CTRL_SPI_CLEAR_RX_FIFO :
return SPI_ClrRxFifo(spi_device->id);
case DEVICE_CTRL_SPI_GET_BUS_BUSY_STATUS :
return SPI_GetBusyStatus(spi_device->id);
default:
break;
}

60
drivers/bl702_driver/hal_drv/src/hal_usb.c
View File

@ -237,7 +237,7 @@ int usb_open(struct device *dev, uint16_t oflag)
usb_fs_device.in_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL;
/* USB interrupt enable config */
USB_IntEn(USB_INT_ALL, DISABLE); //all
BL_WR_REG(USB_BASE, USB_INT_EN, 0);
USB_IntEn(USB_INT_RESET, ENABLE); //1
USB_IntEn(USB_INT_EP0_SETUP_DONE, ENABLE); //5
USB_IntEn(USB_INT_EP0_IN_DONE, ENABLE); //7
@ -245,7 +245,7 @@ int usb_open(struct device *dev, uint16_t oflag)
USB_IntEn(USB_INT_RESET_END, ENABLE); //27
/* USB interrupt mask config */
USB_IntMask(USB_INT_ALL, MASK); //all
BL_WR_REG(USB_BASE, USB_INT_MASK, 0xffffffff);
USB_IntMask(USB_INT_RESET, UNMASK); //1
USB_IntMask(USB_INT_EP0_SETUP_DONE, UNMASK); //5
USB_IntMask(USB_INT_EP0_IN_DONE, UNMASK); //7
@ -527,45 +527,37 @@ int usb_dc_ep_open(struct device *dev, const struct usb_dc_ep_cfg *ep_cfg)
usb_fs_device.in_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type;
}
if (ep_idx) {
switch (ep_cfg->ep_type) {
case USBD_EP_TYPE_CTRL:
epCfg.type = USB_DC_EP_TYPE_CTRL;
break;
switch (ep_cfg->ep_type) {
case USBD_EP_TYPE_CTRL:
epCfg.type = USB_DC_EP_TYPE_CTRL;
break;
case USBD_EP_TYPE_ISOC:
epCfg.type = USB_DC_EP_TYPE_ISOC;
break;
case USBD_EP_TYPE_ISOC:
epCfg.type = USB_DC_EP_TYPE_ISOC;
break;
case USBD_EP_TYPE_BULK:
epCfg.type = USB_DC_EP_TYPE_BULK;
break;
case USBD_EP_TYPE_BULK:
epCfg.type = USB_DC_EP_TYPE_BULK;
break;
case USBD_EP_TYPE_INTR:
epCfg.type = USB_DC_EP_TYPE_INTR;
break;
case USBD_EP_TYPE_INTR:
epCfg.type = USB_DC_EP_TYPE_INTR;
break;
default:
return -1;
}
default:
return -1;
}
USB_Set_EPx_Config(ep_idx, &epCfg);
USB_Set_EPx_Config(ep_idx, &epCfg);
if (USB_EP_DIR_IS_OUT(ep)) {
/* Clear NAK and enable ep */
USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK);
usb_fs_device.out_ep[ep_idx].ep_ena = 1U;
} else {
//USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK);
USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_NACK);
usb_fs_device.in_ep[ep_idx].ep_ena = 1U;
}
if (USB_EP_DIR_IS_OUT(ep)) {
/* Clear NAK and enable ep */
USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK);
usb_fs_device.out_ep[ep_idx].ep_ena = 1U;
} else {
if (USB_EP_DIR_IS_OUT(ep)) {
usb_fs_device.out_ep[ep_idx].ep_ena = 1U;
} else {
usb_fs_device.in_ep[ep_idx].ep_ena = 1U;
}
//USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK);
USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_NACK);
usb_fs_device.in_ep[ep_idx].ep_ena = 1U;
}
return 0;

4
drivers/bl702_driver/std_drv/inc/bl702_adc.h
View File

@ -201,7 +201,7 @@ typedef enum {
typedef enum {
ADC_DATA_WIDTH_12, /*!< ADC 12 bits */
ADC_DATA_WIDTH_14_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */
ADC_DATA_WIDTH_16_WITH_64_AVERAGE, /*!< ADC 16 bits,and the value is average of 64 converts */
ADC_DATA_WIDTH_14_WITH_64_AVERAGE, /*!< ADC 14 bits,and the value is average of 64 converts */
ADC_DATA_WIDTH_16_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */
ADC_DATA_WIDTH_16_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */
} ADC_Data_Width_Type;
@ -450,7 +450,7 @@ typedef struct
*/
#define IS_ADC_DATA_WIDTH_TYPE(type) (((type) == ADC_DATA_WIDTH_12) || \
((type) == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || \
((type) == ADC_DATA_WIDTH_16_WITH_64_AVERAGE) || \
((type) == ADC_DATA_WIDTH_14_WITH_64_AVERAGE) || \
((type) == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || \
((type) == ADC_DATA_WIDTH_16_WITH_256_AVERAGE))

28
drivers/bl702_driver/std_drv/inc/bl702_clock.h
View File

@ -1,6 +1,6 @@
/**
******************************************************************************
* @file bl702_glb.h
* @file bl702_clock.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
@ -33,8 +33,8 @@
*
******************************************************************************
*/
#ifndef __BL702_GLB_H__
#define __BL702_GLB_H__
#ifndef __BL702_CLOCK_H__
#define __BL702_CLOCK_H__
#include "glb_reg.h"
#include "bl702_hbn.h"
@ -44,11 +44,11 @@
* @{
*/
/** @addtogroup GLB
/** @addtogroup CLOCK
* @{
*/
/** @defgroup GLB_Public_Types
/** @defgroup CLOCK_Public_Types
* @{
*/
@ -74,9 +74,9 @@ typedef struct
uint32_t i2sClock; /*!< I2S clock */
} Clock_Cfg_Type;
/*@} end of group GLB_Public_Types */
/*@} end of group CLOCK_Public_Types */
/** @defgroup GLB_Public_Constants
/** @defgroup CLOCK_Public_Constants
* @{
*/
@ -90,15 +90,15 @@ typedef struct
((type) == BL_SYSTEM_CLOCK_XTAL) || \
((type) == BL_SYSTEM_CLOCK_MAX))
/*@} end of group GLB_Public_Constants */
/*@} end of group CLOCK_Public_Constants */
/** @defgroup GLB_Public_Macros
/** @defgroup CLOCK_Public_Macros
* @{
*/
/*@} end of group GLB_Public_Macros */
/*@} end of group CLOCK_Public_Macros */
/** @defgroup GLB_Public_Functions
/** @defgroup CLOCK_Public_Functions
* @{
*/
void Clock_System_Clock_Set(BL_System_Clock_Type type, uint32_t clock);
@ -106,10 +106,10 @@ void Clock_Peripheral_Clock_Set(BL_AHB_Slave1_Type type, uint32_t clock);
uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type);
uint32_t Clock_Peripheral_Clock_Get(BL_AHB_Slave1_Type type);
/*@} end of group GLB_Public_Functions */
/*@} end of group CLOCK_Public_Functions */
/*@} end of group GLB */
/*@} end of group CLOCK */
/*@} end of group BL702_Peripheral_Driver */
#endif /* __BL702_GLB_H__ */
#endif /* __BL702_CLOCK_H__ */

2
drivers/bl702_driver/std_drv/inc/bl702_uart.h
View File

@ -294,7 +294,7 @@ BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length);
BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length);
BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time);
BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt);
BL_Err_Type UART_SetBaudrate(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet);
BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet);
BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId);
BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId);
BL_Err_Type UART_SetTxValue(UART_ID_Type uartId);

12
drivers/bl702_driver/std_drv/src/bl702_adc.c
View File

@ -534,10 +534,12 @@ void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result)
if (dataType == ADC_DATA_WIDTH_12) {
result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe);
result[i].volt = result[i].value / 4096.0 * ref;
} else if (dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) {
} else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) ||
(dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) {
result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe);
result[i].volt = result[i].value / 16384.0 * ref;
} else if (dataType == ADC_DATA_WIDTH_16_WITH_64_AVERAGE || dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE) {
} else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) ||
(dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) {
result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe);
result[i].volt = result[i].value / 65536.0 * ref;
}
@ -557,10 +559,12 @@ void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result)
if (dataType == ADC_DATA_WIDTH_12) {
result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe);
result[i].volt = result[i].value / 2048.0 * ref;
} else if (dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) {
} else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) ||
(dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) {
result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe);
result[i].volt = result[i].value / 8192.0 * ref;
} else if (dataType == ADC_DATA_WIDTH_16_WITH_64_AVERAGE || dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE) {
} else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) ||
(dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) {
result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe);
result[i].volt = result[i].value / 32768.0 * ref;
}

2
drivers/bl702_driver/std_drv/src/bl702_uart.c
View File

@ -601,7 +601,7 @@ BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt)
* @return SUCCESS
*
*******************************************************************************/
BL_Err_Type UART_SetBaudrate(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet)
BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet)
{
uint32_t UARTx = uartAddr[uartId];
uint16_t tmpVal;