[update] update lhal, soc and demos
* Add flash driver and init in boards. * Add timeout for all poll wait apis * Add 808 d0 startup to bringup * Update lhal device tables * Update demos
This commit is contained in:
jzlv
parent
9f241971e3
commit
d6fab307bf
@ -164,6 +164,7 @@ SECTIONS
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__system_ram_data_start__ = .;
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*(.system_ram)
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*(.nocache_ram)
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. = ALIGN(4);
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__system_ram_data_end__ = .;
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@ -2,9 +2,11 @@
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#include "bflb_gpio.h"
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#include "bflb_clock.h"
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#include "bflb_rtc.h"
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#include "bflb_flash.h"
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#include "mmheap.h"
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#include "board.h"
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#include "bl602_glb.h"
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#include "bl602_sflash.h"
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extern uint32_t __HeapBase;
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extern uint32_t __HeapLimit;
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@ -40,7 +42,7 @@ static void peripheral_clock_init(void)
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GLB_Set_SPI_CLK(ENABLE, 0);
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GLB_Set_I2C_CLK(ENABLE, 0);
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GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 0);
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GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
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GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, 0x3E);
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}
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@ -58,6 +60,33 @@ void bl_show_log(void)
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printf("Copyright (c) 2022 Bouffalolab team\r\n");
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}
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void bl_show_flashinfo(void)
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{
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SPI_Flash_Cfg_Type flashCfg;
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uint8_t *pFlashCfg = NULL;
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uint32_t flashCfgLen = 0;
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uint32_t flashJedecId = 0;
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flashJedecId = bflb_flash_get_jedec_id();
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bflb_flash_get_cfg(&pFlashCfg, &flashCfgLen);
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arch_memcpy((void *)&flashCfg, pFlashCfg, flashCfgLen);
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printf("=========== flash cfg ==============\r\n");
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printf("jedec id 0x%06X\r\n", flashJedecId);
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printf("mid 0x%02X\r\n", flashCfg.mid);
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printf("iomode 0x%02X\r\n", flashCfg.ioMode);
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printf("clk delay 0x%02X\r\n", flashCfg.clkDelay);
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printf("clk invert 0x%02X\r\n", flashCfg.clkInvert);
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printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]);
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printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]);
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printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]);
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printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]);
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printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen);
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printf("cread support 0x%02X\r\n", flashCfg.cReadSupport);
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printf("cread code 0x%02X\r\n", flashCfg.cReadMode);
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printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd);
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printf("=====================================\r\n");
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}
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extern void bflb_uart_set_console(struct bflb_device_s *dev);
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static void console_init()
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@ -85,9 +114,17 @@ static void console_init()
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void board_init(void)
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{
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bflb_irq_initialize();
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uintptr_t flag;
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flag = bflb_irq_save();
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bflb_flash_init();
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system_clock_init();
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peripheral_clock_init();
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bflb_irq_initialize();
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bflb_irq_restore(flag);
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system_mmheap[0].addr = (uint8_t *)&__HeapBase;
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system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
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@ -103,20 +140,20 @@ void board_init(void)
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printf("dynamic memory init success,heap size = %d Kbyte \r\n", system_mmheap[0].mem_size / 1024);
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}
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void board_uart1_gpio_init()
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void board_uartx_gpio_init()
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{
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struct bflb_device_s *gpio;
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// struct bflb_device_s *gpio;
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gpio = bflb_device_get_by_name("gpio");
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// gpio = bflb_device_get_by_name("gpio");
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// bflb_gpio_uart_init(gpio, GPIO_PIN_18, GPIO_UART_FUNC_UART1_TX);
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// bflb_gpio_uart_init(gpio, GPIO_PIN_19, GPIO_UART_FUNC_UART1_RX);
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}
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void board_i2c0_gpio_init()
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{
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struct bflb_device_s *gpio;
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// struct bflb_device_s *gpio;
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gpio = bflb_device_get_by_name("gpio");
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// gpio = bflb_device_get_by_name("gpio");
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// /* I2C0_SDA */
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// bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_FUNC_I2C0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
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// /* I2C0_SCL */
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@ -125,9 +162,9 @@ void board_i2c0_gpio_init()
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void board_spi0_gpio_init()
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{
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struct bflb_device_s *gpio;
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// struct bflb_device_s *gpio;
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gpio = bflb_device_get_by_name("gpio");
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// gpio = bflb_device_get_by_name("gpio");
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// bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
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// bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
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// bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
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@ -135,9 +172,9 @@ void board_spi0_gpio_init()
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void board_pwm_gpio_init()
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{
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struct bflb_device_s *gpio;
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// struct bflb_device_s *gpio;
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gpio = bflb_device_get_by_name("gpio");
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// gpio = bflb_device_get_by_name("gpio");
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// bflb_gpio_init(gpio, GPIO_PIN_0, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
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// bflb_gpio_init(gpio, GPIO_PIN_1, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
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// bflb_gpio_init(gpio, GPIO_PIN_2, GPIO_FUNC_PWM0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
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@ -147,9 +184,9 @@ void board_pwm_gpio_init()
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void board_adc_gpio_init()
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{
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struct bflb_device_s *gpio;
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// struct bflb_device_s *gpio;
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gpio = bflb_device_get_by_name("gpio");
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// gpio = bflb_device_get_by_name("gpio");
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// bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
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// bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
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// bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
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@ -157,9 +194,9 @@ void board_adc_gpio_init()
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void board_dac_gpio_init()
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{
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struct bflb_device_s *gpio;
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// struct bflb_device_s *gpio;
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gpio = bflb_device_get_by_name("gpio");
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// gpio = bflb_device_get_by_name("gpio");
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/* DAC_CHA */
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// bflb_gpio_init(gpio, GPIO_PIN_11, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
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// /* DAC_CHB */
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@ -3,11 +3,18 @@
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void board_init(void);
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void board_uart1_gpio_init();
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void board_uartx_gpio_init();
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void board_i2c0_gpio_init();
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void board_spi0_gpio_init();
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void board_adc_gpio_init();
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void board_dac_gpio_init();
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void board_emac_gpio_init();
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void board_pwm_gpio_init();
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#define DEFAULT_TEST_UART "uart1"
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#define DEFAULT_TEST_UART_DMA_TX_REQUEST DMA_REQUEST_UART1_TX
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#define DEFAULT_TEST_UART_DMA_RX_REQUEST DMA_REQUEST_UART1_RX
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#define DEFAULT_TEST_UART_DMA_TDR DMA_ADDR_UART1_TDR
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#define DEFAULT_TEST_UART_DMA_RDR DMA_ADDR_UART1_RDR
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#endif
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@ -23,10 +23,10 @@ HeapMinSize = 0x1000; /* 4KB */
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MEMORY
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{
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xip_memory (rx) : ORIGIN = 0xA0000000, LENGTH = 4M
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itcm_memory (rx) : ORIGIN = 0x62FC0000, LENGTH = 16K
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dtcm_memory (rx) : ORIGIN = 0x62FC4000, LENGTH = 4K
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nocache_ram_memory (!rx) : ORIGIN = 0x22FC5000, LENGTH = 44K+64K
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ram_memory (!rx) : ORIGIN = 0x62FE0000 , LENGTH = 320K+160K-16K-4K-44K-64K
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itcm_memory (rx) : ORIGIN = 0x62FC0000, LENGTH = 20K
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dtcm_memory (rx) : ORIGIN = 0x62FC5000, LENGTH = 4K
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nocache_ram_memory (!rx) : ORIGIN = 0x22FC6000, LENGTH = 44K+60K
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ram_memory (!rx) : ORIGIN = 0x62FE0000 , LENGTH = 320K+160K-20K-4K-44K-60K
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}
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SECTIONS
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@ -2,11 +2,13 @@
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#include "bflb_gpio.h"
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#include "bflb_clock.h"
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#include "bflb_rtc.h"
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#include "bflb_flash.h"
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#include "mmheap.h"
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#include "board.h"
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#include "bl616_tzc_sec.h"
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#include "bl616_psram.h"
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#include "bl616_glb.h"
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#include "bl616_sflash.h"
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#define WB_4MB_PSRAM (1)
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@ -26,7 +28,7 @@ static struct heap_region system_mmheap[] = {
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static struct bflb_device_s *uart0;
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#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG))
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#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
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static struct bflb_device_s *rtc;
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#endif
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@ -56,10 +58,11 @@ static void peripheral_clock_init(void)
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GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0);
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GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0);
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GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0);
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GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 0);
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GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
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GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK);
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GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E);
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GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END);
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GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19);
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GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M);
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#ifdef CONFIG_BSP_SDH_SDCARD
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@ -70,21 +73,16 @@ static void peripheral_clock_init(void)
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#endif
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GLB_Set_USB_CLK_From_WIFIPLL(1);
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GLB_Swap_MCU_SPI_0_MOSI_With_MISO(0);
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}
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static void bflb_init_psram_gpio(void)
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{
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GLB_GPIO_Cfg_Type cfg;
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cfg.pullType = GPIO_PULL_NONE;
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cfg.drive = 0;
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cfg.smtCtrl = 1;
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struct bflb_device_s *gpio;
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gpio = bflb_device_get_by_name("gpio");
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for (uint8_t i = 0; i < 12; i++) {
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cfg.gpioPin = 41 + i;
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cfg.gpioMode = GPIO_MODE_INPUT;
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GLB_GPIO_Init(&cfg);
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bflb_gpio_init(gpio, (41 + i), GPIO_INPUT | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_0);
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}
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}
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@ -146,6 +144,33 @@ void bl_show_log(void)
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printf("Copyright (c) 2022 Bouffalolab team\r\n");
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}
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void bl_show_flashinfo(void)
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{
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SPI_Flash_Cfg_Type flashCfg;
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uint8_t *pFlashCfg = NULL;
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uint32_t flashCfgLen = 0;
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uint32_t flashJedecId = 0;
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flashJedecId = bflb_flash_get_jedec_id();
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bflb_flash_get_cfg(&pFlashCfg, &flashCfgLen);
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arch_memcpy((void *)&flashCfg, pFlashCfg, flashCfgLen);
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printf("=========== flash cfg ==============\r\n");
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printf("jedec id 0x%06X\r\n", flashJedecId);
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printf("mid 0x%02X\r\n", flashCfg.mid);
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printf("iomode 0x%02X\r\n", flashCfg.ioMode);
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printf("clk delay 0x%02X\r\n", flashCfg.clkDelay);
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printf("clk invert 0x%02X\r\n", flashCfg.clkInvert);
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printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]);
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printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]);
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printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]);
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printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]);
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printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen);
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printf("cread support 0x%02X\r\n", flashCfg.cReadSupport);
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printf("cread code 0x%02X\r\n", flashCfg.cReadMode);
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printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd);
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printf("=====================================\r\n");
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}
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extern void bflb_uart_set_console(struct bflb_device_s *dev);
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static void console_init()
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@ -173,9 +198,17 @@ static void console_init()
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void board_init(void)
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{
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bflb_irq_initialize();
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uintptr_t flag;
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flag = bflb_irq_save();
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bflb_flash_init();
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system_clock_init();
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peripheral_clock_init();
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bflb_irq_initialize();
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bflb_irq_restore(flag);
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system_mmheap[0].addr = (uint8_t *)&__HeapBase;
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system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
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@ -187,23 +220,24 @@ void board_init(void)
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console_init();
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bl_show_log();
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bl_show_flashinfo();
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printf("dynamic memory init success,heap size = %d Kbyte \r\n", system_mmheap[0].mem_size / 1024);
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printf("sig1:%08lx\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1));
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printf("sig2:%08lx\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2));
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#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG))
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#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
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rtc = bflb_device_get_by_name("rtc");
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bflb_rtc_set_time(rtc, BFLB_RTC_SEC2TIME(0));
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#endif
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#ifdef CONFIG_PSRAM
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board_psram_x8_init();
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Tzc_Sec_PSRAMB_Access_Release();
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#endif
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}
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void board_uart1_gpio_init()
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void board_uartx_gpio_init()
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{
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struct bflb_device_s *gpio;
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@ -231,13 +265,17 @@ void board_spi0_gpio_init()
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struct bflb_device_s *gpio;
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gpio = bflb_device_get_by_name("gpio");
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bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
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bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
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/* spi cs */
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bflb_gpio_init(gpio, GPIO_PIN_12, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
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/* spi clk */
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bflb_gpio_init(gpio, GPIO_PIN_13, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
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/* spi miso */
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bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
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/* spi mosi */
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bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
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}
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void board_pwm0_gpio_init()
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void board_pwm_gpio_init()
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{
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struct bflb_device_s *gpio;
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@ -314,6 +352,15 @@ void board_sdh_gpio_init()
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bflb_gpio_init(gpio, GPIO_PIN_15, GPIO_FUNC_SDH | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
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}
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void board_ir_gpio_init(void)
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{
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struct bflb_device_s *gpio;
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gpio = bflb_device_get_by_name("gpio");
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bflb_gpio_init(gpio, GPIO_PIN_10, GPIO_INPUT | GPIO_SMT_EN | GPIO_DRV_0);
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GLB_IR_RX_GPIO_Sel(GLB_GPIO_PIN_10);
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}
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#ifdef CONFIG_BFLOG
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__attribute__((weak)) uint64_t bflog_clock(void)
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{
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@ -322,7 +369,7 @@ __attribute__((weak)) uint64_t bflog_clock(void)
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__attribute__((weak)) uint32_t bflog_time(void)
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{
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return BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc));
|
||||
return BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)) + 1640995200;
|
||||
}
|
||||
|
||||
__attribute__((weak)) char *bflog_thread(void)
|
||||
@ -332,18 +379,35 @@ __attribute__((weak)) char *bflog_thread(void)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LUA
|
||||
clock_t luaport_clock(void)
|
||||
__attribute__((weak)) clock_t luaport_clock(void)
|
||||
{
|
||||
return (clock_t)CPU_Get_MTimer_Counter();
|
||||
}
|
||||
|
||||
time_t luaport_time(time_t *seconds)
|
||||
__attribute__((weak)) time_t luaport_time(time_t *seconds)
|
||||
{
|
||||
time_t t = (time_t)BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc));
|
||||
time_t t = (time_t)BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)) + 1640995200;
|
||||
if (seconds != NULL) {
|
||||
*seconds = t;
|
||||
}
|
||||
|
||||
return t;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FATFS
|
||||
#include "bflb_timestamp.h"
|
||||
__attribute__((weak)) uint32_t get_fattime(void)
|
||||
{
|
||||
bflb_timestamp_t tm;
|
||||
|
||||
bflb_timestamp_utc2time(BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)) + 1640995200, &tm);
|
||||
|
||||
return ((uint32_t)(tm.year - 1980) << 25) /* Year 2015 */
|
||||
| ((uint32_t)tm.mon << 21) /* Month 1 */
|
||||
| ((uint32_t)tm.mday << 16) /* Mday 1 */
|
||||
| ((uint32_t)tm.hour << 11) /* Hour 0 */
|
||||
| ((uint32_t)tm.min << 5) /* Min 0 */
|
||||
| ((uint32_t)tm.sec >> 1); /* Sec 0 */
|
||||
}
|
||||
#endif
|
||||
@ -3,13 +3,20 @@
|
||||
|
||||
void board_init(void);
|
||||
|
||||
void board_uart1_gpio_init();
|
||||
void board_uartx_gpio_init();
|
||||
void board_i2c0_gpio_init();
|
||||
void board_spi0_gpio_init();
|
||||
void board_pwm0_gpio_init();
|
||||
void board_pwm_gpio_init();
|
||||
void board_adc_gpio_init();
|
||||
void board_dac_gpio_init();
|
||||
void board_emac_gpio_init();
|
||||
void board_sdh_gpio_init();
|
||||
void board_ir_gpio_init();
|
||||
|
||||
#define DEFAULT_TEST_UART "uart1"
|
||||
#define DEFAULT_TEST_UART_DMA_TX_REQUEST DMA_REQUEST_UART1_TX
|
||||
#define DEFAULT_TEST_UART_DMA_RX_REQUEST DMA_REQUEST_UART1_RX
|
||||
#define DEFAULT_TEST_UART_DMA_TDR DMA_ADDR_UART1_TDR
|
||||
#define DEFAULT_TEST_UART_DMA_RDR DMA_ADDR_UART1_RDR
|
||||
|
||||
#endif
|
||||
@ -22,9 +22,9 @@ StackSize = 0x1000; /* 4KB */
|
||||
MEMORY
|
||||
{
|
||||
xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 1024K
|
||||
itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 8K
|
||||
dtcm_memory (rx) : ORIGIN = 0x42016000, LENGTH = 4K
|
||||
ram_memory (!rx) : ORIGIN = 0x42017000, LENGTH = 100K
|
||||
itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 12K
|
||||
dtcm_memory (rx) : ORIGIN = 0x42017000, LENGTH = 4K
|
||||
ram_memory (!rx) : ORIGIN = 0x42018000, LENGTH = 96K
|
||||
hbn_memory (rx) : ORIGIN = 0x40010000, LENGTH = 0xE00 /* hbn ram 4K used 3.5K*/
|
||||
}
|
||||
|
||||
@ -158,6 +158,7 @@ SECTIONS
|
||||
__system_ram_data_start__ = .;
|
||||
|
||||
*(.system_ram)
|
||||
*(.nocache_ram)
|
||||
|
||||
. = ALIGN(4);
|
||||
__system_ram_data_end__ = .;
|
||||
|
||||
@ -2,9 +2,11 @@
|
||||
#include "bflb_gpio.h"
|
||||
#include "bflb_clock.h"
|
||||
#include "bflb_rtc.h"
|
||||
#include "bflb_flash.h"
|
||||
#include "mmheap.h"
|
||||
#include "board.h"
|
||||
#include "bl702_glb.h"
|
||||
#include "bl702_sflash.h"
|
||||
|
||||
extern uint32_t __HeapBase;
|
||||
extern uint32_t __HeapLimit;
|
||||
@ -43,7 +45,7 @@ static void peripheral_clock_init(void)
|
||||
GLB_Set_SPI_CLK(ENABLE, 0);
|
||||
GLB_Set_I2C_CLK(ENABLE, 0);
|
||||
|
||||
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 0);
|
||||
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
|
||||
GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, 0x3E);
|
||||
|
||||
GLB_Set_USB_CLK(ENABLE);
|
||||
@ -63,6 +65,33 @@ void bl_show_log(void)
|
||||
printf("Copyright (c) 2022 Bouffalolab team\r\n");
|
||||
}
|
||||
|
||||
void bl_show_flashinfo(void)
|
||||
{
|
||||
SPI_Flash_Cfg_Type flashCfg;
|
||||
uint8_t *pFlashCfg = NULL;
|
||||
uint32_t flashCfgLen = 0;
|
||||
uint32_t flashJedecId = 0;
|
||||
|
||||
flashJedecId = bflb_flash_get_jedec_id();
|
||||
bflb_flash_get_cfg(&pFlashCfg, &flashCfgLen);
|
||||
arch_memcpy((void *)&flashCfg, pFlashCfg, flashCfgLen);
|
||||
printf("=========== flash cfg ==============\r\n");
|
||||
printf("jedec id 0x%06X\r\n", flashJedecId);
|
||||
printf("mid 0x%02X\r\n", flashCfg.mid);
|
||||
printf("iomode 0x%02X\r\n", flashCfg.ioMode);
|
||||
printf("clk delay 0x%02X\r\n", flashCfg.clkDelay);
|
||||
printf("clk invert 0x%02X\r\n", flashCfg.clkInvert);
|
||||
printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]);
|
||||
printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]);
|
||||
printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]);
|
||||
printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]);
|
||||
printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen);
|
||||
printf("cread support 0x%02X\r\n", flashCfg.cReadSupport);
|
||||
printf("cread code 0x%02X\r\n", flashCfg.cReadMode);
|
||||
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd);
|
||||
printf("=====================================\r\n");
|
||||
}
|
||||
|
||||
extern void bflb_uart_set_console(struct bflb_device_s *dev);
|
||||
|
||||
static void console_init()
|
||||
@ -90,9 +119,17 @@ static void console_init()
|
||||
|
||||
void board_init(void)
|
||||
{
|
||||
bflb_irq_initialize();
|
||||
uintptr_t flag;
|
||||
|
||||
flag = bflb_irq_save();
|
||||
|
||||
bflb_flash_init();
|
||||
|
||||
system_clock_init();
|
||||
peripheral_clock_init();
|
||||
bflb_irq_initialize();
|
||||
|
||||
bflb_irq_restore(flag);
|
||||
|
||||
system_mmheap[0].addr = (uint8_t *)&__HeapBase;
|
||||
system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
|
||||
@ -105,10 +142,12 @@ void board_init(void)
|
||||
|
||||
bl_show_log();
|
||||
|
||||
bl_show_flashinfo();
|
||||
|
||||
printf("dynamic memory init success,heap size = %d Kbyte \r\n", system_mmheap[0].mem_size / 1024);
|
||||
}
|
||||
|
||||
void board_uart1_gpio_init()
|
||||
void board_uartx_gpio_init()
|
||||
{
|
||||
struct bflb_device_s *gpio;
|
||||
|
||||
@ -133,8 +172,11 @@ void board_spi0_gpio_init()
|
||||
struct bflb_device_s *gpio;
|
||||
|
||||
gpio = bflb_device_get_by_name("gpio");
|
||||
/* spi clk */
|
||||
bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
|
||||
/* spi miso */
|
||||
bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
|
||||
/* spi mosi */
|
||||
bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
|
||||
}
|
||||
|
||||
|
||||
@ -3,11 +3,18 @@
|
||||
|
||||
void board_init(void);
|
||||
|
||||
void board_uart1_gpio_init();
|
||||
void board_uartx_gpio_init();
|
||||
void board_i2c0_gpio_init();
|
||||
void board_spi0_gpio_init();
|
||||
void board_adc_gpio_init();
|
||||
void board_dac_gpio_init();
|
||||
void board_emac_gpio_init();
|
||||
void board_pwm_gpio_init();
|
||||
|
||||
#define DEFAULT_TEST_UART "uart1"
|
||||
#define DEFAULT_TEST_UART_DMA_TX_REQUEST DMA_REQUEST_UART1_TX
|
||||
#define DEFAULT_TEST_UART_DMA_RX_REQUEST DMA_REQUEST_UART1_RX
|
||||
#define DEFAULT_TEST_UART_DMA_TDR DMA_ADDR_UART1_TDR
|
||||
#define DEFAULT_TEST_UART_DMA_RDR DMA_ADDR_UART1_RDR
|
||||
|
||||
#endif
|
||||
@ -1,6 +1,6 @@
|
||||
sdk_add_include_directories(.)
|
||||
|
||||
sdk_set_linker_script(bl808_flash.ld)
|
||||
sdk_set_linker_script(bl808_flash_${CPU_ID}.ld)
|
||||
|
||||
if(CONFIG_PSRAM)
|
||||
sdk_add_compile_definitions(-DCONFIG_PSRAM)
|
||||
|
||||
256
bsp/board/bl808dk/bl808_flash_d0.ld
Normal file
256
bsp/board/bl808dk/bl808_flash_d0.ld
Normal file
@ -0,0 +1,256 @@
|
||||
/****************************************************************************************
|
||||
* @file flash.ld
|
||||
*
|
||||
* @brief This file is the link script file (gnuarm or armgcc).
|
||||
*
|
||||
* Copyright (C) BouffaloLab 2021
|
||||
*
|
||||
****************************************************************************************
|
||||
*/
|
||||
|
||||
/* configure the CPU type */
|
||||
OUTPUT_ARCH( "riscv" )
|
||||
/* link with the standard c library */
|
||||
INPUT(-lc)
|
||||
/* link with the standard GCC library */
|
||||
INPUT(-lgcc)
|
||||
/* configure the entry point */
|
||||
ENTRY(__start)
|
||||
|
||||
StackSize = 0x0400; /* 1KB */
|
||||
HeapMinSize = 0x1000; /* 4KB */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
|
||||
itcm_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 28K
|
||||
dtcm_memory (rx) : ORIGIN = 0x3eff7000, LENGTH = 4K
|
||||
nocache_ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 0K
|
||||
ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 64K
|
||||
xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__text_code_start__ = .;
|
||||
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
|
||||
/* section information for shell */
|
||||
. = ALIGN(8);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
|
||||
/*put .rodata**/
|
||||
*(EXCLUDE_FILE( *bl808_glb*.o* \
|
||||
*bl808_glb_gpio*.o* \
|
||||
*bl808_pds*.o* \
|
||||
*bl808_aon*.o* \
|
||||
*bl808_hbn*.o* \
|
||||
*bl808_l1c*.o* \
|
||||
*bl808_common*.o* \
|
||||
*bl808_clock*.o* \
|
||||
*bl808_ef_ctrl*.o* \
|
||||
*bl808_sf_cfg*.o* \
|
||||
*bl808_sf_ctrl*.o* \
|
||||
*bl808_sflash*.o* \
|
||||
*bl808_xip_sflash*.o* \
|
||||
*bl808_romapi_patch*.o* ) .rodata*)
|
||||
|
||||
*(.srodata)
|
||||
*(.srodata.*)
|
||||
|
||||
. = ALIGN(4);
|
||||
__text_code_end__ = .;
|
||||
} > xip_memory
|
||||
|
||||
. = ALIGN(4);
|
||||
__itcm_load_addr = .;
|
||||
|
||||
.itcm_region : AT (__itcm_load_addr)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__tcm_code_start__ = .;
|
||||
|
||||
*(.tcm_code.*)
|
||||
*(.tcm_const.*)
|
||||
*(.sclock_rlt_code.*)
|
||||
*(.sclock_rlt_const.*)
|
||||
|
||||
*bl808_glb*.o*(.rodata*)
|
||||
*bl808_glb_gpio*.o*(.rodata*)
|
||||
*bl808_pds*.o*(.rodata*)
|
||||
*bl808_aon*.o*(.rodata*)
|
||||
*bl808_hbn*.o*(.rodata*)
|
||||
*bl808_l1c*.o*(.rodata*)
|
||||
*bl808_common*.o*(.rodata*)
|
||||
*bl808_clock*.o*(.rodata*)
|
||||
*bl808_ef_ctrl*.o*(.rodata*)
|
||||
*bl808_sf_cfg*.o*(.rodata*)
|
||||
*bl808_sf_ctrl*.o*(.rodata*)
|
||||
*bl808_sflash*.o*(.rodata*)
|
||||
*bl808_xip_sflash*.o*(.rodata*)
|
||||
*bl808_romapi_patch*.o*(.rodata*)
|
||||
|
||||
. = ALIGN(4);
|
||||
__tcm_code_end__ = .;
|
||||
} > itcm_memory
|
||||
|
||||
__dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
|
||||
|
||||
.dtcm_region : AT (__dtcm_load_addr)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__tcm_data_start__ = .;
|
||||
|
||||
*(.tcm_data)
|
||||
/* *finger_print.o(.data*) */
|
||||
|
||||
. = ALIGN(4);
|
||||
__tcm_data_end__ = .;
|
||||
} > dtcm_memory
|
||||
|
||||
/*************************************************************************/
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (NOLOAD):
|
||||
{
|
||||
. = ALIGN(0x4);
|
||||
. = . + StackSize;
|
||||
. = ALIGN(0x4);
|
||||
} > dtcm_memory
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
|
||||
PROVIDE( __freertos_irq_stack_top = __StackTop);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
|
||||
/*************************************************************************/
|
||||
__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
|
||||
|
||||
.nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__nocache_ram_data_start__ = .;
|
||||
|
||||
*(.nocache_ram)
|
||||
|
||||
. = ALIGN(4);
|
||||
__nocache_ram_data_end__ = .;
|
||||
} > nocache_ram_memory
|
||||
|
||||
__system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
|
||||
|
||||
.system_ram_data_region : AT (__system_ram_load_addr)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__system_ram_data_start__ = .;
|
||||
|
||||
*(.system_ram)
|
||||
|
||||
. = ALIGN(4);
|
||||
__system_ram_data_end__ = .;
|
||||
} > ram_memory
|
||||
|
||||
.system_ram_noinit_data_region (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.system_ram_noinit)
|
||||
|
||||
. = ALIGN(4);
|
||||
} > ram_memory
|
||||
|
||||
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
|
||||
|
||||
/* Data section */
|
||||
RAM_DATA : AT (__ram_load_addr)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__ram_data_start__ = .;
|
||||
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
|
||||
. = ALIGN(4);
|
||||
__ram_data_end__ = .;
|
||||
} > ram_memory
|
||||
|
||||
__etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
|
||||
ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow")
|
||||
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > ram_memory
|
||||
|
||||
.noinit_data (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__noinit_data_start__ = .;
|
||||
|
||||
*(.noinit_data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
__noinit_data_end__ = .;
|
||||
} > ram_memory
|
||||
|
||||
.nocache_noinit_ram_region (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__nocache_ram_data_start__ = .;
|
||||
|
||||
*(.nocache_noinit_ram)
|
||||
|
||||
. = ALIGN(4);
|
||||
__nocache_ram_data_end__ = .;
|
||||
} > nocache_ram_memory
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__HeapBase = .;
|
||||
|
||||
/*__end__ = .;*/
|
||||
/*end = __end__;*/
|
||||
KEEP(*(.heap*))
|
||||
|
||||
. = ALIGN(4);
|
||||
__HeapLimit = .;
|
||||
} > ram_memory
|
||||
|
||||
__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
|
||||
ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
|
||||
|
||||
}
|
||||
|
||||
263
bsp/board/bl808dk/bl808_flash_m0.ld
Normal file
263
bsp/board/bl808dk/bl808_flash_m0.ld
Normal file
@ -0,0 +1,263 @@
|
||||
/****************************************************************************************
|
||||
* @file flash.ld
|
||||
*
|
||||
* @brief This file is the link script file (gnuarm or armgcc).
|
||||
*
|
||||
* Copyright (C) BouffaloLab 2021
|
||||
*
|
||||
****************************************************************************************
|
||||
*/
|
||||
|
||||
/* configure the CPU type */
|
||||
OUTPUT_ARCH( "riscv" )
|
||||
/* link with the standard c library */
|
||||
INPUT(-lc)
|
||||
/* link with the standard GCC library */
|
||||
INPUT(-lgcc)
|
||||
/* configure the entry point */
|
||||
ENTRY(__start)
|
||||
|
||||
StackSize = 0x0400; /* 1KB */
|
||||
HeapMinSize = 0x1000; /* 4KB */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 32M
|
||||
itcm_memory (rx) : ORIGIN = 0x62028000, LENGTH = 20K
|
||||
dtcm_memory (rx) : ORIGIN = 0x6202D000, LENGTH = 4K
|
||||
nocache_ram_memory (!rx) : ORIGIN = 0x2202E000, LENGTH = 16K + 56K
|
||||
ram_memory (!rx) : ORIGIN = 0x62040000, LENGTH = 160K - 56K
|
||||
xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
|
||||
.text :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__text_code_start__ = .;
|
||||
|
||||
KEEP (*(SORT_NONE(.init)))
|
||||
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
|
||||
/* section information for shell */
|
||||
. = ALIGN(4);
|
||||
__fsymtab_start = .;
|
||||
KEEP(*(FSymTab))
|
||||
__fsymtab_end = .;
|
||||
|
||||
. = ALIGN(4);
|
||||
__vsymtab_start = .;
|
||||
KEEP(*(VSymTab))
|
||||
__vsymtab_end = .;
|
||||
|
||||
/* section information for usb usbh_class_info */
|
||||
. = ALIGN(4);
|
||||
__usbh_class_info_start__ = .;
|
||||
KEEP(*(.usbh_class_info))
|
||||
. = ALIGN(4);
|
||||
__usbh_class_info_end__ = .;
|
||||
|
||||
/*put .rodata**/
|
||||
*(EXCLUDE_FILE( *bl808_glb*.o* \
|
||||
*bl808_glb_gpio*.o* \
|
||||
*bl808_pds*.o* \
|
||||
*bl808_aon*.o* \
|
||||
*bl808_hbn*.o* \
|
||||
*bl808_l1c*.o* \
|
||||
*bl808_common*.o* \
|
||||
*bl808_clock*.o* \
|
||||
*bl808_ef_ctrl*.o* \
|
||||
*bl808_sf_cfg*.o* \
|
||||
*bl808_sf_ctrl*.o* \
|
||||
*bl808_sflash*.o* \
|
||||
*bl808_xip_sflash*.o* \
|
||||
*bl808_romapi_patch*.o* ) .rodata*)
|
||||
*(.srodata)
|
||||
*(.srodata.*)
|
||||
|
||||
. = ALIGN(4);
|
||||
__text_code_end__ = .;
|
||||
} > xip_memory
|
||||
|
||||
. = ALIGN(4);
|
||||
__itcm_load_addr = .;
|
||||
|
||||
.itcm_region : AT (__itcm_load_addr)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__tcm_code_start__ = .;
|
||||
|
||||
*(.tcm_code.*)
|
||||
*(.tcm_const.*)
|
||||
*(.sclock_rlt_code.*)
|
||||
*(.sclock_rlt_const.*)
|
||||
|
||||
*bl808_glb*.o*(.rodata*)
|
||||
*bl808_glb_gpio*.o*(.rodata*)
|
||||
*bl808_pds*.o*(.rodata*)
|
||||
*bl808_aon*.o*(.rodata*)
|
||||
*bl808_hbn*.o*(.rodata*)
|
||||
*bl808_l1c*.o*(.rodata*)
|
||||
*bl808_common*.o*(.rodata*)
|
||||
*bl808_clock*.o*(.rodata*)
|
||||
*bl808_ef_ctrl*.o*(.rodata*)
|
||||
*bl808_sf_cfg*.o*(.rodata*)
|
||||
*bl808_sf_ctrl*.o*(.rodata*)
|
||||
*bl808_sflash*.o*(.rodata*)
|
||||
*bl808_xip_sflash*.o*(.rodata*)
|
||||
*bl808_romapi_patch*.o*(.rodata*)
|
||||
|
||||
. = ALIGN(4);
|
||||
__tcm_code_end__ = .;
|
||||
} > itcm_memory
|
||||
|
||||
__dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
|
||||
|
||||
.dtcm_region : AT (__dtcm_load_addr)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__tcm_data_start__ = .;
|
||||
|
||||
*(.tcm_data)
|
||||
/* *finger_print.o(.data*) */
|
||||
|
||||
. = ALIGN(4);
|
||||
__tcm_data_end__ = .;
|
||||
} > dtcm_memory
|
||||
|
||||
/*************************************************************************/
|
||||
/* .stack_dummy section doesn't contains any symbols. It is only
|
||||
* used for linker to calculate size of stack sections, and assign
|
||||
* values to stack symbols later */
|
||||
.stack_dummy (NOLOAD):
|
||||
{
|
||||
. = ALIGN(0x4);
|
||||
. = . + StackSize;
|
||||
. = ALIGN(0x4);
|
||||
} > dtcm_memory
|
||||
|
||||
/* Set stack top to end of RAM, and stack limit move down by
|
||||
* size of stack_dummy section */
|
||||
__StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
|
||||
PROVIDE( __freertos_irq_stack_top = __StackTop);
|
||||
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
|
||||
|
||||
/* Check if data + heap + stack exceeds RAM limit */
|
||||
ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
|
||||
/*************************************************************************/
|
||||
__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
|
||||
|
||||
.nocache_ram_region : AT (__nocache_ram_load_addr)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__nocache_ram_data_start__ = .;
|
||||
|
||||
*(.nocache_ram)
|
||||
|
||||
. = ALIGN(4);
|
||||
__nocache_ram_data_end__ = .;
|
||||
} > nocache_ram_memory
|
||||
|
||||
__system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
|
||||
|
||||
.system_ram_data_region : AT (__system_ram_load_addr)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__system_ram_data_start__ = .;
|
||||
|
||||
*(.system_ram)
|
||||
|
||||
. = ALIGN(4);
|
||||
__system_ram_data_end__ = .;
|
||||
} > ram_memory
|
||||
|
||||
.system_ram_noinit_data_region (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
*(.system_ram_noinit)
|
||||
|
||||
. = ALIGN(4);
|
||||
} > ram_memory
|
||||
|
||||
__ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
|
||||
|
||||
/* Data section */
|
||||
RAM_DATA : AT (__ram_load_addr)
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__ram_data_start__ = .;
|
||||
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
|
||||
*(.data)
|
||||
*(.data.*)
|
||||
*(.sdata)
|
||||
*(.sdata.*)
|
||||
*(.sdata2)
|
||||
*(.sdata2.*)
|
||||
|
||||
. = ALIGN(4);
|
||||
__ram_data_end__ = .;
|
||||
} > ram_memory
|
||||
|
||||
__etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
|
||||
ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow")
|
||||
|
||||
.bss (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__bss_start__ = .;
|
||||
|
||||
*(.bss*)
|
||||
*(.sbss*)
|
||||
*(COMMON)
|
||||
|
||||
. = ALIGN(4);
|
||||
__bss_end__ = .;
|
||||
} > ram_memory
|
||||
|
||||
.noinit_data (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__noinit_data_start__ = .;
|
||||
|
||||
*(.noinit_data*)
|
||||
|
||||
. = ALIGN(4);
|
||||
__noinit_data_end__ = .;
|
||||
} > ram_memory
|
||||
|
||||
.nocache_noinit_ram_region (NOLOAD) :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__nocache_noinit_ram_data_start__ = .;
|
||||
|
||||
*(.nocache_noinit_ram)
|
||||
*(.noncacheable)
|
||||
|
||||
. = ALIGN(4);
|
||||
__nocache_noinit_ram_data_end__ = .;
|
||||
} > nocache_ram_memory
|
||||
|
||||
.heap (NOLOAD):
|
||||
{
|
||||
. = ALIGN(4);
|
||||
__HeapBase = .;
|
||||
|
||||
/*__end__ = .;*/
|
||||
/*end = __end__;*/
|
||||
KEEP(*(.heap*))
|
||||
|
||||
. = ALIGN(4);
|
||||
__HeapLimit = .;
|
||||
} > ram_memory
|
||||
|
||||
__HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
|
||||
ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
|
||||
|
||||
}
|
||||
|
||||
@ -2,8 +2,10 @@
|
||||
#include "bflb_gpio.h"
|
||||
#include "bflb_clock.h"
|
||||
#include "bflb_rtc.h"
|
||||
#include "bflb_flash.h"
|
||||
#include "mmheap.h"
|
||||
#include "bl808_glb.h"
|
||||
#include "bl808_sflash.h"
|
||||
#include "bl808_psram_uhs.h"
|
||||
#include "bl808_tzc_sec.h"
|
||||
#include "bl808_ef_cfg.h"
|
||||
@ -26,14 +28,12 @@ static struct heap_region system_mmheap[] = {
|
||||
|
||||
static struct bflb_device_s *uart0;
|
||||
|
||||
#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG))
|
||||
#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
|
||||
static struct bflb_device_s *rtc;
|
||||
#endif
|
||||
|
||||
#if defined(CPU_M0)
|
||||
static void system_clock_init(void)
|
||||
{
|
||||
GLB_Halt_CPU(GLB_CORE_ID_D0);
|
||||
GLB_Halt_CPU(GLB_CORE_ID_LP);
|
||||
/* wifipll/audiopll */
|
||||
GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL |
|
||||
GLB_PLL_CPUPLL |
|
||||
@ -44,8 +44,6 @@ static void system_clock_init(void)
|
||||
GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_CPUPLL_400M);
|
||||
|
||||
CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1);
|
||||
GLB_Release_CPU(GLB_CORE_ID_D0);
|
||||
GLB_Release_CPU(GLB_CORE_ID_LP);
|
||||
}
|
||||
|
||||
static void peripheral_clock_init(void)
|
||||
@ -64,10 +62,11 @@ static void peripheral_clock_init(void)
|
||||
|
||||
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 4);
|
||||
GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0);
|
||||
GLB_Set_DSP_UART0_CLK(ENABLE, GLB_DSP_UART_CLK_DSP_XCLK, 0);
|
||||
GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0);
|
||||
GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0);
|
||||
GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19);
|
||||
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 0);
|
||||
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
|
||||
GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK);
|
||||
GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E);
|
||||
GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END);
|
||||
@ -143,6 +142,7 @@ int uhs_psram_init(void)
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
void bl_show_log(void)
|
||||
{
|
||||
@ -158,6 +158,33 @@ void bl_show_log(void)
|
||||
printf("Copyright (c) 2022 Bouffalolab team\r\n");
|
||||
}
|
||||
|
||||
void bl_show_flashinfo(void)
|
||||
{
|
||||
SPI_Flash_Cfg_Type flashCfg;
|
||||
uint8_t *pFlashCfg = NULL;
|
||||
uint32_t flashCfgLen = 0;
|
||||
uint32_t flashJedecId = 0;
|
||||
|
||||
flashJedecId = bflb_flash_get_jedec_id();
|
||||
bflb_flash_get_cfg(&pFlashCfg, &flashCfgLen);
|
||||
arch_memcpy((void *)&flashCfg, pFlashCfg, flashCfgLen);
|
||||
printf("=========== flash cfg ==============\r\n");
|
||||
printf("jedec id 0x%06X\r\n", flashJedecId);
|
||||
printf("mid 0x%02X\r\n", flashCfg.mid);
|
||||
printf("iomode 0x%02X\r\n", flashCfg.ioMode);
|
||||
printf("clk delay 0x%02X\r\n", flashCfg.clkDelay);
|
||||
printf("clk invert 0x%02X\r\n", flashCfg.clkInvert);
|
||||
printf("read reg cmd0 0x%02X\r\n", flashCfg.readRegCmd[0]);
|
||||
printf("read reg cmd1 0x%02X\r\n", flashCfg.readRegCmd[1]);
|
||||
printf("write reg cmd0 0x%02X\r\n", flashCfg.writeRegCmd[0]);
|
||||
printf("write reg cmd1 0x%02X\r\n", flashCfg.writeRegCmd[1]);
|
||||
printf("qe write len 0x%02X\r\n", flashCfg.qeWriteRegLen);
|
||||
printf("cread support 0x%02X\r\n", flashCfg.cReadSupport);
|
||||
printf("cread code 0x%02X\r\n", flashCfg.cReadMode);
|
||||
printf("burst wrap cmd 0x%02X\r\n", flashCfg.burstWrapCmd);
|
||||
printf("=====================================\r\n");
|
||||
}
|
||||
|
||||
extern void bflb_uart_set_console(struct bflb_device_s *dev);
|
||||
|
||||
static void console_init()
|
||||
@ -165,9 +192,13 @@ static void console_init()
|
||||
struct bflb_device_s *gpio;
|
||||
|
||||
gpio = bflb_device_get_by_name("gpio");
|
||||
#if defined(CPU_M0)
|
||||
bflb_gpio_uart_init(gpio, GPIO_PIN_14, GPIO_UART_FUNC_UART0_TX);
|
||||
bflb_gpio_uart_init(gpio, GPIO_PIN_15, GPIO_UART_FUNC_UART0_RX);
|
||||
|
||||
#elif defined(CPU_D0)
|
||||
bflb_gpio_init(gpio, GPIO_PIN_8, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
|
||||
//bflb_gpio_init(gpio, GPIO_PIN_9, 21 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
|
||||
#endif
|
||||
struct bflb_uart_config_s cfg;
|
||||
cfg.baudrate = 2000000;
|
||||
cfg.data_bits = UART_DATA_BITS_8;
|
||||
@ -176,18 +207,74 @@ static void console_init()
|
||||
cfg.flow_ctrl = 0;
|
||||
cfg.tx_fifo_threshold = 7;
|
||||
cfg.rx_fifo_threshold = 7;
|
||||
|
||||
#if defined(CPU_M0)
|
||||
uart0 = bflb_device_get_by_name("uart0");
|
||||
|
||||
#elif defined(CPU_D0)
|
||||
uart0 = bflb_device_get_by_name("uart3");
|
||||
#endif
|
||||
bflb_uart_init(uart0, &cfg);
|
||||
bflb_uart_set_console(uart0);
|
||||
}
|
||||
|
||||
#if defined(CPU_M0)
|
||||
void board_init(void)
|
||||
{
|
||||
bflb_irq_initialize();
|
||||
uintptr_t flag;
|
||||
|
||||
flag = bflb_irq_save();
|
||||
|
||||
bflb_flash_init();
|
||||
|
||||
GLB_Halt_CPU(GLB_CORE_ID_D0);
|
||||
GLB_Halt_CPU(GLB_CORE_ID_LP);
|
||||
|
||||
system_clock_init();
|
||||
peripheral_clock_init();
|
||||
bflb_irq_initialize();
|
||||
|
||||
GLB_Release_CPU(GLB_CORE_ID_D0);
|
||||
GLB_Release_CPU(GLB_CORE_ID_LP);
|
||||
|
||||
bflb_irq_restore(flag);
|
||||
|
||||
system_mmheap[0].addr = (uint8_t *)&__HeapBase;
|
||||
system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
|
||||
|
||||
if (system_mmheap[0].mem_size > 0) {
|
||||
mmheap_init(&mmheap_root, system_mmheap);
|
||||
}
|
||||
|
||||
console_init();
|
||||
|
||||
bl_show_log();
|
||||
bl_show_flashinfo();
|
||||
|
||||
printf("dynamic memory init success,heap size = %d Kbyte \r\n", system_mmheap[0].mem_size / 1024);
|
||||
|
||||
printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1));
|
||||
printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2));
|
||||
|
||||
#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG) || defined(CONFIG_FATFS))
|
||||
rtc = bflb_device_get_by_name("rtc");
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PSRAM
|
||||
if (uhs_psram_init() < 0) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
#endif
|
||||
/* release d0 and then do can run */
|
||||
BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG);
|
||||
BL_WR_WORD(IPC_SYNC_ADDR2, IPC_SYNC_FLAG);
|
||||
L1C_DCache_Clean_By_Addr(IPC_SYNC_ADDR1, 8);
|
||||
}
|
||||
#elif defined(CPU_D0)
|
||||
void board_init(void)
|
||||
{
|
||||
CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1);
|
||||
|
||||
bflb_irq_initialize();
|
||||
|
||||
system_mmheap[0].addr = (uint8_t *)&__HeapBase;
|
||||
system_mmheap[0].mem_size = ((size_t)&__HeapLimit - (size_t)&__HeapBase);
|
||||
@ -204,20 +291,10 @@ void board_init(void)
|
||||
|
||||
printf("sig1:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG1));
|
||||
printf("sig2:%08x\r\n", BL_RD_REG(GLB_BASE, GLB_UART_CFG2));
|
||||
|
||||
#if (defined(CONFIG_LUA) || defined(CONFIG_BFLOG))
|
||||
rtc = bflb_device_get_by_name("rtc");
|
||||
bflb_rtc_set_time(rtc, BFLB_RTC_SEC2TIME(0));
|
||||
#endif
|
||||
#ifdef CONFIG_PSRAM
|
||||
if (uhs_psram_init() < 0) {
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
void board_uart1_gpio_init(void)
|
||||
void board_uartx_gpio_init(void)
|
||||
{
|
||||
struct bflb_device_s *gpio;
|
||||
|
||||
@ -245,13 +322,17 @@ void board_spi0_gpio_init(void)
|
||||
struct bflb_device_s *gpio;
|
||||
|
||||
gpio = bflb_device_get_by_name("gpio");
|
||||
/* spi cs */
|
||||
bflb_gpio_init(gpio, GPIO_PIN_16, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
|
||||
/* spi miso */
|
||||
bflb_gpio_init(gpio, GPIO_PIN_17, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
|
||||
/* spi mosi */
|
||||
bflb_gpio_init(gpio, GPIO_PIN_18, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
|
||||
/* spi clk */
|
||||
bflb_gpio_init(gpio, GPIO_PIN_19, GPIO_FUNC_SPI0 | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
|
||||
}
|
||||
|
||||
void board_pwm0_gpio_init(void)
|
||||
void board_pwm_gpio_init(void)
|
||||
{
|
||||
struct bflb_device_s *gpio;
|
||||
|
||||
@ -371,7 +452,7 @@ __attribute__((weak)) uint64_t bflog_clock(void)
|
||||
|
||||
__attribute__((weak)) uint32_t bflog_time(void)
|
||||
{
|
||||
return BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc));
|
||||
return BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)) + 1640995200;
|
||||
}
|
||||
|
||||
__attribute__((weak)) char *bflog_thread(void)
|
||||
@ -381,18 +462,35 @@ __attribute__((weak)) char *bflog_thread(void)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_LUA
|
||||
clock_t luaport_clock(void)
|
||||
__attribute__((weak)) clock_t luaport_clock(void)
|
||||
{
|
||||
return (clock_t)CPU_Get_MTimer_Counter();
|
||||
}
|
||||
|
||||
time_t luaport_time(time_t *seconds)
|
||||
__attribute__((weak)) time_t luaport_time(time_t *seconds)
|
||||
{
|
||||
time_t t = (time_t)BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc));
|
||||
time_t t = (time_t)BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)) + 1640995200;
|
||||
if (seconds != NULL) {
|
||||
*seconds = t;
|
||||
}
|
||||
|
||||
return t;
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_FATFS
|
||||
#include "bflb_timestamp.h"
|
||||
__attribute__((weak)) uint32_t get_fattime(void)
|
||||
{
|
||||
bflb_timestamp_t tm;
|
||||
|
||||
bflb_timestamp_utc2time(BFLB_RTC_TIME2SEC(bflb_rtc_get_time(rtc)) + 1640995200, &tm);
|
||||
|
||||
return ((uint32_t)(tm.year - 1980) << 25) /* Year 2015 */
|
||||
| ((uint32_t)tm.mon << 21) /* Month 1 */
|
||||
| ((uint32_t)tm.mday << 16) /* Mday 1 */
|
||||
| ((uint32_t)tm.hour << 11) /* Hour 0 */
|
||||
| ((uint32_t)tm.min << 5) /* Min 0 */
|
||||
| ((uint32_t)tm.sec >> 1); /* Sec 0 */
|
||||
}
|
||||
#endif
|
||||
@ -4,10 +4,10 @@
|
||||
void board_init(void);
|
||||
|
||||
void board_jtag_gpio_init(void);
|
||||
void board_uart1_gpio_init(void);
|
||||
void board_uartx_gpio_init(void);
|
||||
void board_i2c0_gpio_init(void);
|
||||
void board_spi0_gpio_init(void);
|
||||
void board_pwm0_gpio_init(void);
|
||||
void board_pwm_gpio_init(void);
|
||||
void board_adc_gpio_init(void);
|
||||
void board_dac_gpio_init(void);
|
||||
void board_ir_gpio_init(void);
|
||||
@ -17,4 +17,10 @@ void board_emac_gpio_init(void);
|
||||
void board_sdh_gpio_init(void);
|
||||
#endif
|
||||
|
||||
#define DEFAULT_TEST_UART "uart1"
|
||||
#define DEFAULT_TEST_UART_DMA_TX_REQUEST DMA_REQUEST_UART1_TX
|
||||
#define DEFAULT_TEST_UART_DMA_RX_REQUEST DMA_REQUEST_UART1_RX
|
||||
#define DEFAULT_TEST_UART_DMA_TDR DMA_ADDR_UART1_TDR
|
||||
#define DEFAULT_TEST_UART_DMA_RDR DMA_ADDR_UART1_RDR
|
||||
|
||||
#endif
|
||||
@ -104,15 +104,6 @@ int MMC_disk_ioctl(BYTE cmd, void *buff)
|
||||
return 0;
|
||||
}
|
||||
|
||||
DWORD get_fattime(void)
|
||||
{
|
||||
return ((DWORD)(2015 - 1980) << 25) /* Year 2015 */
|
||||
| ((DWORD)1 << 21) /* Month 1 */
|
||||
| ((DWORD)1 << 16) /* Mday 1 */
|
||||
| ((DWORD)0 << 11) /* Hour 0 */
|
||||
| ((DWORD)0 << 5) /* Min 0 */
|
||||
| ((DWORD)0 >> 1); /* Sec 0 */
|
||||
}
|
||||
|
||||
DSTATUS Translate_Result_Code(int result)
|
||||
{
|
||||
|
||||
@ -12,13 +12,16 @@ sdk_library_add_sources(src/bflb_emac.c)
|
||||
endif()
|
||||
sdk_library_add_sources(src/bflb_gpio.c)
|
||||
sdk_library_add_sources(src/bflb_i2c.c)
|
||||
if((NOT ("${CHIP}" STREQUAL "bl602")) AND (NOT ("${CHIP}" STREQUAL "bl702")))
|
||||
sdk_library_add_sources(src/bflb_ir.c)
|
||||
endif()
|
||||
sdk_library_add_sources(src/bflb_uart.c)
|
||||
sdk_library_add_sources(src/bflb_spi.c)
|
||||
sdk_library_add_sources(src/bflb_rtc.c)
|
||||
sdk_library_add_sources(src/bflb_sec_aes.c)
|
||||
sdk_library_add_sources(src/bflb_sec_sha.c)
|
||||
sdk_library_add_sources(src/bflb_sec_trng.c)
|
||||
# sdk_library_add_sources(src/bflb_sec_irq.c)
|
||||
sdk_library_add_sources(src/bflb_timer.c)
|
||||
sdk_library_add_sources(src/bflb_wdg.c)
|
||||
sdk_library_add_sources(src/bflb_cks.c)
|
||||
@ -46,6 +49,7 @@ endif()
|
||||
|
||||
# optional
|
||||
sdk_library_add_sources(src/bflb_irq.c)
|
||||
sdk_library_add_sources(src/bflb_l1c.c)
|
||||
sdk_library_add_sources(src/bflb_mtimer.c)
|
||||
|
||||
sdk_add_include_directories(include)
|
||||
|
||||
@ -162,6 +162,13 @@ struct bflb_device_s bl602_device_table[] = {
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_PKA,
|
||||
.user_data = NULL },
|
||||
{ .name = "watchdog",
|
||||
.reg_base = TIMER_BASE,
|
||||
.irq_num = BL602_IRQ_WDT,
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_TIMER,
|
||||
.user_data = NULL },
|
||||
};
|
||||
|
||||
struct bflb_device_s *bflb_device_get_by_name(const char *name)
|
||||
|
||||
@ -44,7 +44,7 @@ struct bflb_device_s bl616_device_table[] = {
|
||||
.idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_SPI,
|
||||
.user_data = NULL },
|
||||
{ .name = "pwm0",
|
||||
{ .name = "pwm_v2_0",
|
||||
.reg_base = PWM_BASE,
|
||||
.irq_num = BL616_IRQ_PWM,
|
||||
.idx = 0,
|
||||
@ -191,6 +191,13 @@ struct bflb_device_s bl616_device_table[] = {
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_MJPEG,
|
||||
.user_data = NULL },
|
||||
{ .name = "irrx",
|
||||
.reg_base = IR_BASE,
|
||||
.irq_num = BL616_IRQ_IRRX,
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_IR,
|
||||
.user_data = NULL },
|
||||
};
|
||||
|
||||
struct bflb_device_s *bflb_device_get_by_name(const char *name)
|
||||
|
||||
@ -44,7 +44,7 @@ struct bflb_device_s bl702_device_table[] = {
|
||||
.idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_SPI,
|
||||
.user_data = NULL },
|
||||
{ .name = "pwm0",
|
||||
{ .name = "pwm_v1",
|
||||
.reg_base = PWM_BASE,
|
||||
.irq_num = BL702_IRQ_PWM,
|
||||
.idx = 0,
|
||||
@ -169,6 +169,13 @@ struct bflb_device_s bl702_device_table[] = {
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_ETH,
|
||||
.user_data = NULL },
|
||||
{ .name = "watchdog",
|
||||
.reg_base = TIMER_BASE,
|
||||
.irq_num = BL702_IRQ_WDT,
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_TIMER,
|
||||
.user_data = NULL },
|
||||
};
|
||||
|
||||
struct bflb_device_s *bflb_device_get_by_name(const char *name)
|
||||
|
||||
@ -7,7 +7,11 @@
|
||||
struct bflb_device_s bl808_device_table[] = {
|
||||
{ .name = "adc",
|
||||
.reg_base = AON_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_GPADC_DMA,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_ADC,
|
||||
@ -21,116 +25,204 @@ struct bflb_device_s bl808_device_table[] = {
|
||||
.user_data = NULL },
|
||||
{ .name = "gpio",
|
||||
.reg_base = GLB_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_GPIO_INT0,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_GPIO,
|
||||
.user_data = NULL },
|
||||
{ .name = "uart0",
|
||||
.reg_base = UART0_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_UART0,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_UART,
|
||||
.user_data = NULL },
|
||||
{ .name = "uart1",
|
||||
.reg_base = UART1_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_UART1,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 1,
|
||||
.dev_type = BFLB_DEVICE_TYPE_UART,
|
||||
.user_data = NULL },
|
||||
{ .name = "uart2",
|
||||
.reg_base = UART2_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_UART2,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 2,
|
||||
.dev_type = BFLB_DEVICE_TYPE_UART,
|
||||
.user_data = NULL },
|
||||
{ .name = "uart3",
|
||||
.reg_base = UART3_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = 0xff,
|
||||
#else
|
||||
.irq_num = BL808_IRQ_UART3,
|
||||
#endif
|
||||
.idx = 3,
|
||||
.dev_type = BFLB_DEVICE_TYPE_UART,
|
||||
.user_data = NULL },
|
||||
{ .name = "spi0",
|
||||
.reg_base = SPI0_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_SPI0,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_SPI,
|
||||
.user_data = NULL },
|
||||
{ .name = "pwm0",
|
||||
{ .name = "pwm_v2_0",
|
||||
.reg_base = PWM_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_PWM,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_PWM,
|
||||
.user_data = NULL },
|
||||
{ .name = "dma0_ch0",
|
||||
.reg_base = DMA0_BASE + 1 * DMA_CHANNEL_OFFSET,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_DMA0_ALL,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_DMA,
|
||||
.user_data = NULL },
|
||||
{ .name = "dma0_ch1",
|
||||
.reg_base = DMA0_BASE + 2 * DMA_CHANNEL_OFFSET,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_DMA0_ALL,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 1,
|
||||
.dev_type = BFLB_DEVICE_TYPE_DMA,
|
||||
.user_data = NULL },
|
||||
{ .name = "dma0_ch2",
|
||||
.reg_base = DMA0_BASE + 3 * DMA_CHANNEL_OFFSET,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_DMA0_ALL,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 2,
|
||||
.dev_type = BFLB_DEVICE_TYPE_DMA,
|
||||
.user_data = NULL },
|
||||
{ .name = "dma0_ch3",
|
||||
.reg_base = DMA0_BASE + 4 * DMA_CHANNEL_OFFSET,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_DMA0_ALL,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 3,
|
||||
.dev_type = BFLB_DEVICE_TYPE_DMA,
|
||||
.user_data = NULL },
|
||||
{ .name = "dma0_ch4",
|
||||
.reg_base = DMA0_BASE + 5 * DMA_CHANNEL_OFFSET,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_DMA0_ALL,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 4,
|
||||
.dev_type = BFLB_DEVICE_TYPE_DMA,
|
||||
.user_data = NULL },
|
||||
{ .name = "dma0_ch5",
|
||||
.reg_base = DMA0_BASE + 6 * DMA_CHANNEL_OFFSET,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_DMA0_ALL,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 5,
|
||||
.dev_type = BFLB_DEVICE_TYPE_DMA,
|
||||
.user_data = NULL },
|
||||
{ .name = "dma0_ch6",
|
||||
.reg_base = DMA0_BASE + 7 * DMA_CHANNEL_OFFSET,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_DMA0_ALL,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 6,
|
||||
.dev_type = BFLB_DEVICE_TYPE_DMA,
|
||||
.user_data = NULL },
|
||||
{ .name = "dma0_ch7",
|
||||
.reg_base = DMA0_BASE + 8 * DMA_CHANNEL_OFFSET,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_DMA0_ALL,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 7,
|
||||
.dev_type = BFLB_DEVICE_TYPE_DMA,
|
||||
.user_data = NULL },
|
||||
{ .name = "i2c0",
|
||||
.reg_base = I2C0_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_I2C0,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_I2C,
|
||||
.user_data = NULL },
|
||||
{ .name = "timer0",
|
||||
.reg_base = TIMER0_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_TIMER0,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_TIMER,
|
||||
.user_data = NULL },
|
||||
{ .name = "timer1",
|
||||
.reg_base = TIMER1_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_TIMER1,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 1,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_TIMER,
|
||||
.user_data = NULL },
|
||||
{ .name = "rtc",
|
||||
.reg_base = HBN_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_HBN_OUT0,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_RTC,
|
||||
@ -165,21 +257,33 @@ struct bflb_device_s bl808_device_table[] = {
|
||||
.user_data = NULL },
|
||||
{ .name = "emac0",
|
||||
.reg_base = EMAC_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_EMAC,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_ETH,
|
||||
.user_data = NULL },
|
||||
{ .name = "irtx",
|
||||
.reg_base = IR_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_IRTX,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_IR,
|
||||
.user_data = NULL },
|
||||
{ .name = "irrx",
|
||||
.reg_base = IR_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_IRRX,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_IR,
|
||||
@ -191,15 +295,28 @@ struct bflb_device_s bl808_device_table[] = {
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_CKS,
|
||||
.user_data = NULL },
|
||||
#if defined(CPU_D0)
|
||||
{ .name = "mjpeg",
|
||||
.reg_base = MJPEG_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = 0xff,
|
||||
#else
|
||||
.irq_num = BL808_IRQ_MJPEG,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_MJPEG,
|
||||
.user_data = NULL },
|
||||
{ .name = "watchdog",
|
||||
.reg_base = TIMER0_BASE,
|
||||
#if defined(CPU_M0)
|
||||
.irq_num = BL808_IRQ_WDT,
|
||||
#else
|
||||
.irq_num = 0xff,
|
||||
#endif
|
||||
.idx = 0,
|
||||
.sub_idx = 0,
|
||||
.dev_type = BFLB_DEVICE_TYPE_TIMER,
|
||||
.user_data = NULL },
|
||||
};
|
||||
|
||||
struct bflb_device_s *bflb_device_get_by_name(const char *name)
|
||||
|
||||
@ -298,7 +298,7 @@
|
||||
#define CSR_DSCRATCH 0x7B2
|
||||
|
||||
/* In mstatus register */
|
||||
|
||||
#define MSTATUS_SIE (0x1 << 1) /* Superior Interrupt Enable */
|
||||
#define MSTATUS_MIE (0x1 << 3) /* Machine Interrupt Enable */
|
||||
#define MSTATUS_MPIE (0x1 << 7) /* Machine Previous Interrupt Enable */
|
||||
#define MSTATUS_MPPM (0x3 << 11) /* Machine Previous Privilege (m-mode) */
|
||||
|
||||
@ -1,12 +1,12 @@
|
||||
#ifndef _RISCV_ARCH_H
|
||||
#define _RISCV_ARCH_H
|
||||
|
||||
#define getreg8(a) (*(volatile uint8_t *)(a))
|
||||
#define putreg8(v, a) (*(volatile uint8_t *)(a) = (v))
|
||||
#define getreg16(a) (*(volatile uint16_t *)(a))
|
||||
#define putreg16(v, a) (*(volatile uint16_t *)(a) = (v))
|
||||
#define getreg32(a) (*(volatile uint32_t *)(a))
|
||||
#define putreg32(v, a) (*(volatile uint32_t *)(a) = (v))
|
||||
#define getreg8(a) (*(volatile uint8_t *)(uintptr_t)(a))
|
||||
#define putreg8(v, a) (*(volatile uint8_t *)(uintptr_t)(a) = (v))
|
||||
#define getreg16(a) (*(volatile uint16_t *)(uintptr_t)(a))
|
||||
#define putreg16(v, a) (*(volatile uint16_t *)(uintptr_t)(a) = (v))
|
||||
#define getreg32(a) (*(volatile uint32_t *)(uintptr_t)(a))
|
||||
#define putreg32(v, a) (*(volatile uint32_t *)(uintptr_t)(a) = (v))
|
||||
// #define getreg64(a) (*(volatile uint64_t *)(a))
|
||||
// #define putreg64(v, a) (*(volatile uint64_t *)(a) = (v))
|
||||
// #define modifyreg32(a, clearbits, setbits) putreg32((getreg32(a) & (~clearbits)) | setbits, a)
|
||||
|
||||
@ -6,15 +6,14 @@
|
||||
/** @defgroup ADC_CHANNEL adc channel definition
|
||||
* @{
|
||||
*/
|
||||
#define ADC_CHANNEL_0 0
|
||||
#define ADC_CHANNEL_1 1
|
||||
#define ADC_CHANNEL_2 2
|
||||
#define ADC_CHANNEL_3 3
|
||||
#define ADC_CHANNEL_4 4
|
||||
#define ADC_CHANNEL_5 5
|
||||
#define ADC_CHANNEL_6 6
|
||||
#define ADC_CHANNEL_7 7
|
||||
#if !defined(BL702L)
|
||||
#define ADC_CHANNEL_0 0
|
||||
#define ADC_CHANNEL_1 1
|
||||
#define ADC_CHANNEL_2 2
|
||||
#define ADC_CHANNEL_3 3
|
||||
#define ADC_CHANNEL_4 4
|
||||
#define ADC_CHANNEL_5 5
|
||||
#define ADC_CHANNEL_6 6
|
||||
#define ADC_CHANNEL_7 7
|
||||
#define ADC_CHANNEL_8 8
|
||||
#define ADC_CHANNEL_9 9
|
||||
#define ADC_CHANNEL_10 10
|
||||
@ -23,16 +22,9 @@
|
||||
#define ADC_CHANNEL_DACB 13
|
||||
#define ADC_CHANNEL_TSEN_P 14
|
||||
#define ADC_CHANNEL_TSEN_N 15
|
||||
#define ADC_CHANNEL_VREF 16
|
||||
#define ADC_CHANNEL_VABT_HALF 18
|
||||
#define ADC_CHANNEL_GND 23
|
||||
#else
|
||||
#define ADC_CHANNEL_DACA 8
|
||||
#define ADC_CHANNEL_DACB 9
|
||||
#define ADC_CHANNEL_VBAT 10
|
||||
#define ADC_CHANNEL_TSEN 11
|
||||
#define ADC_CHANNEL_VREF 12
|
||||
#define ADC_CHANNEL_GND 13
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -166,8 +158,9 @@ uint32_t bflb_adc_get_intstatus(struct bflb_device_s *dev);
|
||||
void bflb_adc_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
|
||||
|
||||
void bflb_adc_parse_result(struct bflb_device_s *dev, uint32_t *buffer, struct bflb_adc_result_s *result, uint16_t count);
|
||||
|
||||
void bflb_adc_tsen_init(struct bflb_device_s *dev, uint8_t tsen_mod);
|
||||
float bflb_adc_tsen_get_temp(struct bflb_device_s *dev, uint32_t tsen_offset);
|
||||
float bflb_adc_tsen_get_temp(struct bflb_device_s *dev);
|
||||
void bflb_adc_vbat_enable(struct bflb_device_s *dev);
|
||||
void bflb_adc_vbat_disable(struct bflb_device_s *dev);
|
||||
|
||||
|
||||
@ -66,6 +66,9 @@
|
||||
#if !defined(BL702L)
|
||||
#define DMA_ADDR_DAC_TDR (0x40002000 + 0x48)
|
||||
#endif
|
||||
#if defined(BL702L)
|
||||
#define DMA_ADDR_IR_TDR (0x4000A600 + 0x88)
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -82,6 +85,9 @@
|
||||
#endif
|
||||
#define DMA_REQUEST_I2C0_RX 0x00000006
|
||||
#define DMA_REQUEST_I2C0_TX 0x00000007
|
||||
#if defined(BL702L)
|
||||
#define DMA_REQUEST_IR_TX 0x00000008
|
||||
#endif
|
||||
#define DMA_REQUEST_SPI0_RX 0x0000000A
|
||||
#define DMA_REQUEST_SPI0_TX 0x0000000B
|
||||
#if !defined(BL702L)
|
||||
@ -165,6 +171,7 @@
|
||||
#define DMA_ADDR_I2S_RDR (0x2000AB00 + 0x8C)
|
||||
#define DMA_ADDR_ADC_RDR (0x20002000 + 0x04)
|
||||
#define DMA_ADDR_DAC_TDR (0x20002000 + 0x48)
|
||||
#define DMA_ADDR_IR_TDR (0x2000A600 + 0x88)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -360,7 +367,6 @@ int bflb_dma_channel_lli_reload(struct bflb_device_s *dev,
|
||||
|
||||
int bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
|
||||
|
||||
/* Not use */
|
||||
void bflb_dma_channel_tcint_mask(struct bflb_device_s *dev, bool mask);
|
||||
bool bflb_dma_channel_get_tcint_status(struct bflb_device_s *dev);
|
||||
void bflb_dma_channel_tcint_clear(struct bflb_device_s *dev);
|
||||
|
||||
20
drivers/lhal/include/bflb_efuse.h
Normal file
20
drivers/lhal/include/bflb_efuse.h
Normal file
@ -0,0 +1,20 @@
|
||||
#ifndef _BFLB_EFUSE_H
|
||||
#define _BFLB_EFUSE_H
|
||||
|
||||
#include "bflb_core.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
float bflb_efuse_get_adc_trim(void);
|
||||
uint32_t bflb_efuse_get_adc_tsen_trim(void);
|
||||
void bflb_efuse_write_secure_boot();
|
||||
void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len);
|
||||
void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
56
drivers/lhal/include/bflb_flash.h
Normal file
56
drivers/lhal/include/bflb_flash.h
Normal file
@ -0,0 +1,56 @@
|
||||
#ifndef _BFLB_FLASH_H
|
||||
#define _BFLB_FLASH_H
|
||||
|
||||
#include "bflb_core.h"
|
||||
|
||||
#define FLASH_IOMODE_NIO 0 /*!< Normal IO mode define */
|
||||
#define FLASH_IOMODE_DO 1 /*!< Dual Output mode define */
|
||||
#define FLASH_IOMODE_QO 2 /*!< Quad Output mode define */
|
||||
#define FLASH_IOMODE_DIO 3 /*!< Dual IO mode define */
|
||||
#define FLASH_IOMODE_QIO 4 /*!< Quad IO mode define */
|
||||
|
||||
#define FLASH_AES_KEY_128BITS 0
|
||||
#define FLASH_AES_KEY_192BITS 2
|
||||
#define FLASH_AES_KEY_256BITS 1
|
||||
#define FLASH_AES_KEY_DOUBLE_128BITS 3
|
||||
|
||||
#if defined(BL602) || defined(BL702) || defined(BL702L)
|
||||
#define FLASH_XIP_BASE (0x23000000)
|
||||
#elif defined(BL616) || defined(BL628)
|
||||
#define FLASH_XIP_BASE (0xA0000000)
|
||||
#elif defined(BL808) || defined(BL606P)
|
||||
#define FLASH_XIP_BASE (0x58000000)
|
||||
#endif
|
||||
|
||||
struct bflb_flash_aes_config_s {
|
||||
uint8_t region;
|
||||
uint8_t region_enable;
|
||||
uint8_t lock_enable;
|
||||
const uint8_t *key;
|
||||
uint8_t keybits;
|
||||
uint8_t *iv;
|
||||
uint32_t start_addr;
|
||||
uint32_t end_addr;
|
||||
};
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
int bflb_flash_init(void);
|
||||
uint32_t bflb_flash_get_jedec_id(void);
|
||||
void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len);
|
||||
void bflb_flash_set_iomode(uint8_t iomode);
|
||||
int bflb_flash_erase(uint32_t addr, uint32_t len);
|
||||
int bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len);
|
||||
int bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len);
|
||||
|
||||
void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config);
|
||||
void bflb_flash_aes_enable(void);
|
||||
void bflb_flash_aes_disable(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -169,7 +169,7 @@
|
||||
#define GPIO_INT_TRIG_MODE_SYNC_RISING_EDGE 1
|
||||
#define GPIO_INT_TRIG_MODE_SYNC_LOW_LEVEL 2
|
||||
#define GPIO_INT_TRIG_MODE_SYNC_HIGH_LEVEL 3
|
||||
#if defined(BL702)
|
||||
#if defined(BL602) || defined(BL702)
|
||||
#define GPIO_INT_TRIG_MODE_ASYNC_FALLING_EDGE 4
|
||||
#define GPIO_INT_TRIG_MODE_ASYNC_RISING_EDGE 5
|
||||
#define GPIO_INT_TRIG_MODE_ASYNC_LOW_LEVEL 6
|
||||
|
||||
@ -64,11 +64,8 @@
|
||||
* @{
|
||||
*/
|
||||
#define I2C_INTCLR_END (1 << 0) /* Transfer end interrupt */
|
||||
#define I2C_INTCLR_TX_FIFO (1 << 1) /* TX FIFO ready interrupt */
|
||||
#define I2C_INTCLR_RX_FIFO (1 << 2) /* RX FIFO ready interrupt */
|
||||
#define I2C_INTCLR_NACK (1 << 3) /* NACK interrupt */
|
||||
#define I2C_INTCLR_ARB (1 << 4) /* Arbitration lost interrupt */
|
||||
#define I2C_INTCLR_FER (1 << 5) /* TX/RX FIFO error interrupt */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -3,6 +3,7 @@
|
||||
|
||||
#include "bflb_core.h"
|
||||
|
||||
#if !defined(BL616)
|
||||
/** @defgroup IR TX mode definition
|
||||
* @{
|
||||
*/
|
||||
@ -34,7 +35,9 @@
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
#if !defined(BL702L)
|
||||
/** @defgroup IR RX mode definition
|
||||
* @{
|
||||
*/
|
||||
@ -54,6 +57,7 @@
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif
|
||||
|
||||
/** @defgroup IR word definition
|
||||
* @{
|
||||
@ -64,6 +68,7 @@
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if !defined(BL616)
|
||||
/**
|
||||
* @brief IR TX configuration structure
|
||||
*
|
||||
@ -124,7 +129,9 @@ struct bflb_ir_tx_config_s {
|
||||
uint8_t modu_width_0;
|
||||
uint16_t pulse_width_unit;
|
||||
};
|
||||
#endif
|
||||
|
||||
#if !defined(BL702L)
|
||||
/**
|
||||
* @brief IR RX configuration structure
|
||||
*
|
||||
@ -145,11 +152,13 @@ struct bflb_ir_rx_config_s {
|
||||
uint16_t end_threshold;
|
||||
uint16_t fifo_threshold;
|
||||
};
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if !defined(BL616)
|
||||
void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s *config);
|
||||
void bflb_ir_send(struct bflb_device_s *dev, uint32_t *data, uint32_t length);
|
||||
void bflb_ir_swm_send(struct bflb_device_s *dev, uint16_t *data, uint8_t length);
|
||||
@ -160,7 +169,9 @@ uint32_t bflb_ir_txint_status(struct bflb_device_s *dev);
|
||||
void bflb_ir_link_txdma(struct bflb_device_s *dev, bool enable);
|
||||
uint8_t bflb_ir_txfifo_cnt(struct bflb_device_s *dev);
|
||||
void bflb_ir_txfifo_clear(struct bflb_device_s *dev);
|
||||
#endif
|
||||
|
||||
#if !defined(BL702L)
|
||||
void bflb_ir_rx_init(struct bflb_device_s *dev, const struct bflb_ir_rx_config_s *config);
|
||||
uint8_t bflb_ir_receive(struct bflb_device_s *dev, uint64_t *data);
|
||||
uint8_t bflb_ir_swm_receive(struct bflb_device_s *dev, uint16_t *data, uint8_t length);
|
||||
@ -170,6 +181,7 @@ void bflb_ir_rxint_clear(struct bflb_device_s *dev);
|
||||
uint32_t bflb_ir_rxint_status(struct bflb_device_s *dev);
|
||||
uint8_t bflb_ir_rxfifo_cnt(struct bflb_device_s *dev);
|
||||
void bflb_ir_rxfifo_clear(struct bflb_device_s *dev);
|
||||
#endif
|
||||
|
||||
void bflb_ir_feature_control();
|
||||
|
||||
|
||||
@ -21,14 +21,15 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
void bflb_irq_initialize(void);
|
||||
uint32_t bflb_irq_save(void);
|
||||
void bflb_irq_restore(uint32_t flags);
|
||||
uintptr_t bflb_irq_save(void);
|
||||
void bflb_irq_restore(uintptr_t flags);
|
||||
int bflb_irq_attach(int irq, irq_callback isr, void *arg);
|
||||
int bflb_irq_detach(int irq);
|
||||
void bflb_irq_enable(int irq);
|
||||
void bflb_irq_disable(int irq);
|
||||
void bflb_irq_set_pending(int irq);
|
||||
void bflb_irq_clear_pending(int irq);
|
||||
void bflb_irq_set_nlbits(uint8_t nlbits);
|
||||
void bflb_irq_set_priority(int irq, uint8_t preemptprio, uint8_t subprio);
|
||||
|
||||
#ifdef __cplusplus
|
||||
|
||||
@ -3,31 +3,16 @@
|
||||
|
||||
#include "bflb_core.h"
|
||||
|
||||
#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
|
||||
#include "csi_core.h"
|
||||
#define bflb_l1c_icache_enable() csi_icache_enable()
|
||||
#define bflb_l1c_icache_disable() csi_icache_disable()
|
||||
#define bflb_l1c_icache_invalid_all() csi_icache_invalid()
|
||||
#define bflb_l1c_dcache_enable() csi_dcache_enable()
|
||||
#define bflb_l1c_dcache_disable() csi_dcache_disable()
|
||||
#define bflb_l1c_dcache_clean_all() csi_dcache_clean()
|
||||
#define bflb_l1c_dcache_invalidate_all() csi_icache_invalid()
|
||||
#define bflb_l1c_dcache_clean_invalidate_all() csi_dcache_clean_invalid()
|
||||
#define bflb_l1c_dcache_clean_range(addr, len) csi_dcache_clean_range(addr, len)
|
||||
#define bflb_l1c_dcache_invalidate_range(addr, len) csi_dcache_invalid_range(addr, len)
|
||||
#define bflb_l1c_dcache_clean_invalidate_range(addr, len) csi_dcache_clean_invalid_range(addr, len)
|
||||
#else
|
||||
#define bflb_l1c_icache_enable()
|
||||
#define bflb_l1c_icache_disable()
|
||||
#define bflb_l1c_icache_invalid_all()
|
||||
#define bflb_l1c_dcache_enable()
|
||||
#define bflb_l1c_dcache_disable()
|
||||
#define bflb_l1c_dcache_clean_all()
|
||||
#define bflb_l1c_dcache_invalidate_all()
|
||||
#define bflb_l1c_dcache_clean_invalidate_all()
|
||||
#define bflb_l1c_dcache_clean_range(addr, len)
|
||||
#define bflb_l1c_dcache_invalidate_range(addr, len)
|
||||
#define bflb_l1c_dcache_clean_invalidate_range(addr, len)
|
||||
#endif
|
||||
void bflb_l1c_icache_enable(void);
|
||||
void bflb_l1c_icache_disable(void);
|
||||
void bflb_l1c_icache_invalid_all(void);
|
||||
void bflb_l1c_dcache_enable(void);
|
||||
void bflb_l1c_dcache_disable(void);
|
||||
void bflb_l1c_dcache_clean_all(void);
|
||||
void bflb_l1c_dcache_invalidate_all(void);
|
||||
void bflb_l1c_dcache_clean_invalidate_all(void);
|
||||
void bflb_l1c_dcache_clean_range(void *addr, uint32_t size);
|
||||
void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size);
|
||||
void bflb_l1c_dcache_clean_invalidate_range(void *addr, uint32_t size);
|
||||
|
||||
#endif
|
||||
@ -80,11 +80,11 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
void bflb_pwm_v1_channel_init(struct bflb_device_s *dev, uint8_t ch, const struct bflb_pwm_v1_channel_config_s *config);
|
||||
void bflb_pwm_v1_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold);
|
||||
void bflb_pwm_v1_deinit(struct bflb_device_s *dev, uint8_t ch);
|
||||
void bflb_pwm_v1_channel_deinit(struct bflb_device_s *dev, uint8_t ch);
|
||||
void bflb_pwm_v1_start(struct bflb_device_s *dev, uint8_t ch);
|
||||
void bflb_pwm_v1_stop(struct bflb_device_s *dev, uint8_t ch);
|
||||
void bflb_pwm_v1_set_period(struct bflb_device_s *dev, uint8_t ch, uint16_t period);
|
||||
void bflb_pwm_v1_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold);
|
||||
|
||||
void bflb_pwm_v1_int_enable(struct bflb_device_s *dev, uint8_t ch, bool enable);
|
||||
uint32_t bflb_pwm_v1_get_intstatus(struct bflb_device_s *dev);
|
||||
|
||||
24
drivers/lhal/include/bflb_sec_irq.h
Normal file
24
drivers/lhal/include/bflb_sec_irq.h
Normal file
@ -0,0 +1,24 @@
|
||||
#ifndef _BFLB_SEC_IRQ_H
|
||||
#define _BFLB_SEC_IRQ_H
|
||||
|
||||
#include "bflb_core.h"
|
||||
|
||||
#define BFLB_SEC_ENG_IRQ_TYPE_AES 0
|
||||
#define BFLB_SEC_ENG_IRQ_TYPE_SHA 1
|
||||
#define BFLB_SEC_ENG_IRQ_TYPE_PKA 2
|
||||
#define BFLB_SEC_ENG_IRQ_TYPE_TRNG 3
|
||||
#define BFLB_SEC_ENG_IRQ_TYPE_GMAC 4
|
||||
#define BFLB_SEC_ENG_IRQ_TYPE_CDET 5
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
void bflb_sec_irq_attach(uint8_t sec_type, void (*callback)(void *arg), void *arg);
|
||||
void bflb_sec_irq_detach(uint8_t sec_type);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@ -70,6 +70,29 @@
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_INTSTS spi interrupt status definition
|
||||
* @{
|
||||
*/
|
||||
#define SPI_INTSTS_TC (1 << 0)
|
||||
#define SPI_INTSTS_TX_FIFO (1 << 1)
|
||||
#define SPI_INTSTS_RX_FIFO (1 << 2)
|
||||
#define SPI_INTSTS_SLAVE_TIMEOUT (1 << 3)
|
||||
#define SPI_INTSTS_SLAVE_TX_UNDERRUN (1 << 4)
|
||||
#define SPI_INTSTS_FIFO_ERR (1 << 5)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_INTCLR spi interrupt clear definition
|
||||
* @{
|
||||
*/
|
||||
#define SPI_INTCLR_TC (1 << 16)
|
||||
#define SPI_INTCLR_SLAVE_TIMEOUT (1 << 19)
|
||||
#define SPI_INTCLR_SLAVE_TX_UNDERRUN (1 << 20)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup SPI_CMD spi feature control cmd definition
|
||||
* @{
|
||||
*/
|
||||
@ -118,6 +141,7 @@ int bflb_spi_poll_exchange(struct bflb_device_s *dev, const void *txbuffer, void
|
||||
bool bflb_spi_isbusy(struct bflb_device_s *dev);
|
||||
void bflb_spi_txint_mask(struct bflb_device_s *dev, bool mask);
|
||||
void bflb_spi_rxint_mask(struct bflb_device_s *dev, bool mask);
|
||||
void bflb_spi_tcint_mask(struct bflb_device_s *dev, bool mask);
|
||||
void bflb_spi_errint_mask(struct bflb_device_s *dev, bool mask);
|
||||
uint32_t bflb_spi_get_intstatus(struct bflb_device_s *dev);
|
||||
void bflb_spi_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
|
||||
|
||||
@ -7,11 +7,15 @@
|
||||
/** @defgroup TIMER_CLK_SOURCE timer clock source definition
|
||||
* @{
|
||||
*/
|
||||
#if !defined(BL702L)
|
||||
#define TIMER_CLKSRC_BCLK 0
|
||||
#endif
|
||||
#define TIMER_CLKSRC_32K 1
|
||||
#define TIMER_CLKSRC_1K 2
|
||||
#define TIMER_CLKSRC_XTAL 3
|
||||
#if !defined(BL702) && !defined(BL602)
|
||||
#define TIMER_CLKSRC_GPIO 4
|
||||
#endif
|
||||
#define TIMER_CLKSRC_NO 5
|
||||
/**
|
||||
* @}
|
||||
@ -37,15 +41,6 @@
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup TIMER_CAPTURE_POLARITY timer capture polarity definition
|
||||
* @{
|
||||
*/
|
||||
#define TIMER_CAPTURE_POLARITY_RISING 0
|
||||
#define TIMER_CAPTURE_POLARITY_FALLING 1
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief TIMER configuration structure
|
||||
*
|
||||
@ -96,8 +91,6 @@ void bflb_timer_compint_mask(struct bflb_device_s *dev, uint8_t cmp_no, bool mas
|
||||
bool bflb_timer_get_compint_status(struct bflb_device_s *dev, uint8_t cmp_no);
|
||||
void bflb_timer_compint_clear(struct bflb_device_s *dev, uint8_t cmp_no);
|
||||
|
||||
void bflb_timer_capture_init(struct bflb_device_s *dev, const struct bflb_timer_capture_config_s *config);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -134,6 +134,14 @@
|
||||
#define UART_CMD_SET_ABR_ALLOWABLE_ERROR (0x13)
|
||||
#define UART_CMD_SET_SW_RTS_CONTROL (0x14)
|
||||
#define UART_CMD_IR_CONFIG (0x15)
|
||||
#define UART_CMD_SET_TX_FREERUN (0x16)
|
||||
#define UART_CMD_SET_TX_END_INTERRUPT (0x17)
|
||||
#define UART_CMD_SET_RX_END_INTERRUPT (0x18)
|
||||
#define UART_CMD_SET_TX_TRANSFER_LEN (0x19)
|
||||
#define UART_CMD_SET_RX_TRANSFER_LEN (0x20)
|
||||
#define UART_CMD_SET_TX_EN (0x21)
|
||||
#define UART_CMD_SET_BCR_END_INTERRUPT (0x22)
|
||||
#define UART_CMD_GET_BCR_COUNT (0x23)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -186,9 +194,9 @@ void bflb_uart_enable(struct bflb_device_s *dev);
|
||||
void bflb_uart_disable(struct bflb_device_s *dev);
|
||||
void bflb_uart_link_txdma(struct bflb_device_s *dev, bool enable);
|
||||
void bflb_uart_link_rxdma(struct bflb_device_s *dev, bool enable);
|
||||
void bflb_uart_putchar(struct bflb_device_s *dev, int ch);
|
||||
int bflb_uart_putchar(struct bflb_device_s *dev, int ch);
|
||||
int bflb_uart_getchar(struct bflb_device_s *dev);
|
||||
void bflb_uart_put(struct bflb_device_s *dev, uint8_t *data, uint32_t len);
|
||||
int bflb_uart_put(struct bflb_device_s *dev, uint8_t *data, uint32_t len);
|
||||
int bflb_uart_get(struct bflb_device_s *dev, uint8_t *data, uint32_t len);
|
||||
bool bflb_uart_txready(struct bflb_device_s *dev);
|
||||
bool bflb_uart_txempty(struct bflb_device_s *dev);
|
||||
|
||||
@ -4,11 +4,15 @@
|
||||
#include "bflb_core.h"
|
||||
#include "bflb_clock.h"
|
||||
|
||||
#if !defined(BL702L)
|
||||
#define WDG_CLKSRC_BCLK 0
|
||||
#endif
|
||||
#define WDG_CLKSRC_32K 1
|
||||
#define WDG_CLKSRC_1K 2
|
||||
#define WDG_CLKSRC_XTAL 3
|
||||
#if !defined(BL702) && !defined(BL602)
|
||||
#define WDG_CLKSRC_GPIO 4
|
||||
#endif
|
||||
#define WDG_CLKSRC_NO 5
|
||||
|
||||
/** @defgroup WDG_MODE Watch-dog reset/interrupt mode definition
|
||||
|
||||
@ -1522,6 +1522,7 @@
|
||||
#define GLB_GPIO_CFGCTL33_OFFSET (0x18C)/* GPIO_CFGCTL33 */
|
||||
#define GLB_GPIO_CFGCTL34_OFFSET (0x190)/* GPIO_CFGCTL34 */
|
||||
#define GLB_GPIO_CFGCTL35_OFFSET (0x194)/* GPIO_CFGCTL35 */
|
||||
#define GLB_GPIO_CFGCTL36_OFFSET (0x198)/* GPIO_CFGCTL36 */
|
||||
#define GLB_GPIO_INT_MASK1_OFFSET (0x1A0)/* GPIO_INT_MASK1 */
|
||||
#define GLB_GPIO_INT_STAT1_OFFSET (0x1A8)/* GPIO_INT_STAT1 */
|
||||
#define GLB_GPIO_INT_CLR1_OFFSET (0x1B0)/* GPIO_INT_CLR1 */
|
||||
|
||||
@ -42,24 +42,61 @@
|
||||
|
||||
/* Register offsets *********************************************************/
|
||||
|
||||
#if !defined(BL616)
|
||||
#define IRTX_CONFIG_OFFSET (0x0) /* irtx_config */
|
||||
#define IRTX_INT_STS_OFFSET (0x4) /* irtx_int_sts */
|
||||
#if defined(BL602) || defined(BL702)
|
||||
#define IRTX_DATA_WORD0_OFFSET (0x8) /* irtx_data_word0 */
|
||||
#define IRTX_DATA_WORD1_OFFSET (0xC) /* irtx_data_word1 */
|
||||
#endif
|
||||
#define IRTX_PULSE_WIDTH_OFFSET (0x10) /* irtx_pulse_width */
|
||||
#if defined(BL602) || defined(BL702)
|
||||
#define IRTX_PW_OFFSET (0x14) /* irtx_pw */
|
||||
#define IRTX_SWM_PW_0_OFFSET (0x40) /* irtx_swm_pw_0 */
|
||||
#define IRTX_SWM_PW_1_OFFSET (0x44) /* irtx_swm_pw_1 */
|
||||
#define IRTX_SWM_PW_2_OFFSET (0x48) /* irtx_swm_pw_2 */
|
||||
#define IRTX_SWM_PW_3_OFFSET (0x4C) /* irtx_swm_pw_3 */
|
||||
#define IRTX_SWM_PW_4_OFFSET (0x50) /* irtx_swm_pw_4 */
|
||||
#define IRTX_SWM_PW_5_OFFSET (0x54) /* irtx_swm_pw_5 */
|
||||
#define IRTX_SWM_PW_6_OFFSET (0x58) /* irtx_swm_pw_6 */
|
||||
#define IRTX_SWM_PW_7_OFFSET (0x5C) /* irtx_swm_pw_7 */
|
||||
#else
|
||||
#define IRTX_PW_0_OFFSET (0x14) /* irtx_pw_0 */
|
||||
#define IRTX_PW_1_OFFSET (0x18) /* irtx_pw_1 */
|
||||
#endif
|
||||
#endif
|
||||
#if !defined(BL702L)
|
||||
#if defined(BL602) || defined(BL702)
|
||||
#define IRRX_CONFIG_OFFSET (0x80) /* irrx_config */
|
||||
#define IRRX_INT_STS_OFFSET (0x84) /* irrx_int_sts */
|
||||
#define IRRX_PW_CONFIG_OFFSET (0x88) /* irrx_pw_config */
|
||||
#define IRRX_DATA_COUNT_OFFSET (0x90) /* irrx_data_count */
|
||||
#define IRRX_DATA_WORD0_OFFSET (0x94) /* irrx_data_word0 */
|
||||
#define IRRX_DATA_WORD1_OFFSET (0x98) /* irrx_data_word1 */
|
||||
#else
|
||||
#define IRRX_CONFIG_OFFSET (0x40) /* irrx_config */
|
||||
#define IRRX_INT_STS_OFFSET (0x44) /* irrx_int_sts */
|
||||
#define IRRX_PW_CONFIG_OFFSET (0x48) /* irrx_pw_config */
|
||||
#define IRRX_DATA_COUNT_OFFSET (0x50) /* irrx_data_count */
|
||||
#define IRRX_DATA_WORD0_OFFSET (0x54) /* irrx_data_word0 */
|
||||
#define IRRX_DATA_WORD1_OFFSET (0x58) /* irrx_data_word1 */
|
||||
#endif
|
||||
#endif
|
||||
#if defined(BL602) || defined(BL702)
|
||||
#define IRRX_SWM_FIFO_CONFIG_0_OFFSET (0xC0) /* irrx_swm_fifo_config_0 */
|
||||
#define IRRX_SWM_FIFO_RDATA_OFFSET (0xC4) /* irrx_swm_fifo_rdata */
|
||||
#else
|
||||
#define IR_FIFO_CONFIG_0_OFFSET (0x80) /* ir_fifo_config_0 */
|
||||
#define IR_FIFO_CONFIG_1_OFFSET (0x84) /* ir_fifo_config_1 */
|
||||
#define IR_FIFO_WDATA_OFFSET (0x88) /* ir_fifo_wdata */
|
||||
#if !defined(BL702L)
|
||||
#define IR_FIFO_RDATA_OFFSET (0x8C) /* ir_fifo_rdata */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Register Bitfield definitions *****************************************************/
|
||||
|
||||
#if !defined(BL616)
|
||||
/* 0x0 : irtx_config */
|
||||
#define IR_CR_IRTX_EN (1 << 0U)
|
||||
#define IR_CR_IRTX_OUT_INV (1 << 1U)
|
||||
@ -72,24 +109,43 @@
|
||||
#define IR_CR_IRTX_HEAD_HL_INV (1 << 9U)
|
||||
#define IR_CR_IRTX_TAIL_EN (1 << 10U)
|
||||
#define IR_CR_IRTX_TAIL_HL_INV (1 << 11U)
|
||||
#if defined(BL602) || defined(BL702)
|
||||
#define IR_CR_IRTX_DATA_NUM_SHIFT (12U)
|
||||
#define IR_CR_IRTX_DATA_NUM_MASK (0x3f << IR_CR_IRTX_DATA_NUM_SHIFT)
|
||||
#else
|
||||
#define IR_CR_IRTX_FRM_EN (1 << 12U)
|
||||
#define IR_CR_IRTX_FRM_CONT_EN (1 << 13U)
|
||||
#define IR_CR_IRTX_FRM_FRAME_SIZE_SHIFT (14U)
|
||||
#define IR_CR_IRTX_FRM_FRAME_SIZE_MASK (0x3 << IR_CR_IRTX_FRM_FRAME_SIZE_SHIFT)
|
||||
#define IR_CR_IRTX_DATA_NUM_SHIFT (16U)
|
||||
#define IR_CR_IRTX_DATA_NUM_MASK (0x7f << IR_CR_IRTX_DATA_NUM_SHIFT)
|
||||
#endif
|
||||
|
||||
/* 0x4 : irtx_int_sts */
|
||||
#define IRTX_END_INT (1 << 0U)
|
||||
#if !defined(BL602) && !defined(BL702)
|
||||
#define IRTX_FRDY_INT (1 << 1U)
|
||||
#define IRTX_FER_INT (1 << 2U)
|
||||
#endif
|
||||
#define IR_CR_IRTX_END_MASK (1 << 8U)
|
||||
#if !defined(BL602) && !defined(BL702)
|
||||
#define IR_CR_IRTX_FRDY_MASK (1 << 9U)
|
||||
#define IR_CR_IRTX_FER_MASK (1 << 10U)
|
||||
#endif
|
||||
#define IR_CR_IRTX_END_CLR (1 << 16U)
|
||||
#define IR_CR_IRTX_END_EN (1 << 24U)
|
||||
#if !defined(BL602) && !defined(BL702)
|
||||
#define IR_CR_IRTX_FRDY_EN (1 << 25U)
|
||||
#define IR_CR_IRTX_FER_EN (1 << 26U)
|
||||
#else
|
||||
/* 0x8 : irtx_data_word0 */
|
||||
#define IR_CR_IRTX_DATA_WORD0_SHIFT (0U)
|
||||
#define IR_CR_IRTX_DATA_WORD0_MASK (0xffffffff<<IR_CR_IRTX_DATA_WORD0_SHIFT)
|
||||
|
||||
/* 0xC : irtx_data_word1 */
|
||||
#define IR_CR_IRTX_DATA_WORD1_SHIFT (0U)
|
||||
#define IR_CR_IRTX_DATA_WORD1_MASK (0xffffffff<<IR_CR_IRTX_DATA_WORD1_SHIFT)
|
||||
#endif
|
||||
|
||||
/* 0x10 : irtx_pulse_width */
|
||||
#define IR_CR_IRTX_PW_UNIT_SHIFT (0U)
|
||||
@ -99,6 +155,57 @@
|
||||
#define IR_CR_IRTX_MOD_PH1_W_SHIFT (24U)
|
||||
#define IR_CR_IRTX_MOD_PH1_W_MASK (0xff << IR_CR_IRTX_MOD_PH1_W_SHIFT)
|
||||
|
||||
#if defined(BL602) || defined(BL702)
|
||||
/* 0x14 : irtx_pw */
|
||||
#define IR_CR_IRTX_LOGIC0_PH0_W_SHIFT (0U)
|
||||
#define IR_CR_IRTX_LOGIC0_PH0_W_MASK (0xf<<IR_CR_IRTX_LOGIC0_PH0_W_SHIFT)
|
||||
#define IR_CR_IRTX_LOGIC0_PH1_W_SHIFT (4U)
|
||||
#define IR_CR_IRTX_LOGIC0_PH1_W_MASK (0xf<<IR_CR_IRTX_LOGIC0_PH1_W_SHIFT)
|
||||
#define IR_CR_IRTX_LOGIC1_PH0_W_SHIFT (8U)
|
||||
#define IR_CR_IRTX_LOGIC1_PH0_W_MASK (0xf<<IR_CR_IRTX_LOGIC1_PH0_W_SHIFT)
|
||||
#define IR_CR_IRTX_LOGIC1_PH1_W_SHIFT (12U)
|
||||
#define IR_CR_IRTX_LOGIC1_PH1_W_MASK (0xf<<IR_CR_IRTX_LOGIC1_PH1_W_SHIFT)
|
||||
#define IR_CR_IRTX_HEAD_PH0_W_SHIFT (16U)
|
||||
#define IR_CR_IRTX_HEAD_PH0_W_MASK (0xf<<IR_CR_IRTX_HEAD_PH0_W_SHIFT)
|
||||
#define IR_CR_IRTX_HEAD_PH1_W_SHIFT (20U)
|
||||
#define IR_CR_IRTX_HEAD_PH1_W_MASK (0xf<<IR_CR_IRTX_HEAD_PH1_W_SHIFT)
|
||||
#define IR_CR_IRTX_TAIL_PH0_W_SHIFT (24U)
|
||||
#define IR_CR_IRTX_TAIL_PH0_W_MASK (0xf<<IR_CR_IRTX_TAIL_PH0_W_SHIFT)
|
||||
#define IR_CR_IRTX_TAIL_PH1_W_SHIFT (28U)
|
||||
#define IR_CR_IRTX_TAIL_PH1_W_MASK (0xf<<IR_CR_IRTX_TAIL_PH1_W_SHIFT)
|
||||
|
||||
/* 0x40 : irtx_swm_pw_0 */
|
||||
#define IR_CR_IRTX_SWM_PW_0_SHIFT (0U)
|
||||
#define IR_CR_IRTX_SWM_PW_0_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_0_SHIFT)
|
||||
|
||||
/* 0x44 : irtx_swm_pw_1 */
|
||||
#define IR_CR_IRTX_SWM_PW_1_SHIFT (0U)
|
||||
#define IR_CR_IRTX_SWM_PW_1_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_1_SHIFT)
|
||||
|
||||
/* 0x48 : irtx_swm_pw_2 */
|
||||
#define IR_CR_IRTX_SWM_PW_2_SHIFT (0U)
|
||||
#define IR_CR_IRTX_SWM_PW_2_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_2_SHIFT)
|
||||
|
||||
/* 0x4C : irtx_swm_pw_3 */
|
||||
#define IR_CR_IRTX_SWM_PW_3_SHIFT (0U)
|
||||
#define IR_CR_IRTX_SWM_PW_3_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_3_SHIFT)
|
||||
|
||||
/* 0x50 : irtx_swm_pw_4 */
|
||||
#define IR_CR_IRTX_SWM_PW_4_SHIFT (0U)
|
||||
#define IR_CR_IRTX_SWM_PW_4_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_4_SHIFT)
|
||||
|
||||
/* 0x54 : irtx_swm_pw_5 */
|
||||
#define IR_CR_IRTX_SWM_PW_5_SHIFT (0U)
|
||||
#define IR_CR_IRTX_SWM_PW_5_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_5_SHIFT)
|
||||
|
||||
/* 0x58 : irtx_swm_pw_6 */
|
||||
#define IR_CR_IRTX_SWM_PW_6_SHIFT (0U)
|
||||
#define IR_CR_IRTX_SWM_PW_6_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_6_SHIFT)
|
||||
|
||||
/* 0x5C : irtx_swm_pw_7 */
|
||||
#define IR_CR_IRTX_SWM_PW_7_SHIFT (0U)
|
||||
#define IR_CR_IRTX_SWM_PW_7_MASK (0xffffffff<<IR_CR_IRTX_SWM_PW_7_SHIFT)
|
||||
#else
|
||||
/* 0x14 : irtx_pw_0 */
|
||||
#define IR_CR_IRTX_LOGIC0_PH0_W_SHIFT (0U)
|
||||
#define IR_CR_IRTX_LOGIC0_PH0_W_MASK (0xff << IR_CR_IRTX_LOGIC0_PH0_W_SHIFT)
|
||||
@ -118,7 +225,10 @@
|
||||
#define IR_CR_IRTX_TAIL_PH0_W_MASK (0xff << IR_CR_IRTX_TAIL_PH0_W_SHIFT)
|
||||
#define IR_CR_IRTX_TAIL_PH1_W_SHIFT (24U)
|
||||
#define IR_CR_IRTX_TAIL_PH1_W_MASK (0xff << IR_CR_IRTX_TAIL_PH1_W_SHIFT)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if !defined(BL702L)
|
||||
/* 0x40 : irrx_config */
|
||||
#define IR_CR_IRRX_EN (1 << 0U)
|
||||
#define IR_CR_IRRX_IN_INV (1 << 1U)
|
||||
@ -130,15 +240,21 @@
|
||||
|
||||
/* 0x44 : irrx_int_sts */
|
||||
#define IRRX_END_INT (1 << 0U)
|
||||
#if !defined(BL602) && !defined(BL702)
|
||||
#define IRRX_FRDY_INT (1 << 1U)
|
||||
#define IRRX_FER_INT (1 << 2U)
|
||||
#endif
|
||||
#define IR_CR_IRRX_END_MASK (1 << 8U)
|
||||
#if !defined(BL602) && !defined(BL702)
|
||||
#define IR_CR_IRRX_FRDY_MASK (1 << 9U)
|
||||
#define IR_CR_IRRX_FER_MASK (1 << 10U)
|
||||
#endif
|
||||
#define IR_CR_IRRX_END_CLR (1 << 16U)
|
||||
#define IR_CR_IRRX_END_EN (1 << 24U)
|
||||
#if !defined(BL602) && !defined(BL702)
|
||||
#define IR_CR_IRRX_FRDY_EN (1 << 25U)
|
||||
#define IR_CR_IRRX_FER_EN (1 << 26U)
|
||||
#endif
|
||||
|
||||
/* 0x48 : irrx_pw_config */
|
||||
#define IR_CR_IRRX_DATA_TH_SHIFT (0U)
|
||||
@ -157,32 +273,66 @@
|
||||
/* 0x58 : irrx_data_word1 */
|
||||
#define IR_STS_IRRX_DATA_WORD1_SHIFT (0U)
|
||||
#define IR_STS_IRRX_DATA_WORD1_MASK (0xffffffff << IR_STS_IRRX_DATA_WORD1_SHIFT)
|
||||
#endif
|
||||
|
||||
/* 0x80 : ir_fifo_config_0 */
|
||||
#if !defined(BL616) && !defined(BL602) && !defined(BL702)
|
||||
#define IRTX_DMA_EN (1 << 0U)
|
||||
#define IR_TX_FIFO_CLR (1 << 2U)
|
||||
#endif
|
||||
#if !defined(BL702L)
|
||||
#if defined(BL602) || defined(BL702)
|
||||
#define IR_RX_FIFO_CLR (1 << 0U)
|
||||
#else
|
||||
#define IR_RX_FIFO_CLR (1 << 3U)
|
||||
#endif
|
||||
#endif
|
||||
#if !defined(BL616) && !defined(BL602) && !defined(BL702)
|
||||
#define IR_TX_FIFO_OVERFLOW (1 << 4U)
|
||||
#define IR_TX_FIFO_UNDERFLOW (1 << 5U)
|
||||
#endif
|
||||
#if !defined(BL702L)
|
||||
#if defined(BL602) || defined(BL702)
|
||||
#define IR_RX_FIFO_OVERFLOW (1<<2U)
|
||||
#define IR_RX_FIFO_UNDERFLOW (1<<3U)
|
||||
#else
|
||||
#define IR_RX_FIFO_OVERFLOW (1 << 6U)
|
||||
#define IR_RX_FIFO_UNDERFLOW (1 << 7U)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* 0x84 : ir_fifo_config_1 */
|
||||
#if !defined(BL616) && !defined(BL602) && !defined(BL702)
|
||||
#define IR_TX_FIFO_CNT_SHIFT (0U)
|
||||
#define IR_TX_FIFO_CNT_MASK (0x7 << IR_TX_FIFO_CNT_SHIFT)
|
||||
#endif
|
||||
#if !defined(BL702L)
|
||||
#if defined(BL602) || defined(BL702)
|
||||
#define IR_RX_FIFO_CNT_SHIFT (4U)
|
||||
#else
|
||||
#define IR_RX_FIFO_CNT_SHIFT (8U)
|
||||
#endif
|
||||
#define IR_RX_FIFO_CNT_MASK (0x7f << IR_RX_FIFO_CNT_SHIFT)
|
||||
#endif
|
||||
#if !defined(BL616) && !defined(BL602) && !defined(BL702)
|
||||
#define IR_TX_FIFO_TH_SHIFT (16U)
|
||||
#define IR_TX_FIFO_TH_MASK (0x3 << IR_TX_FIFO_TH_SHIFT)
|
||||
#endif
|
||||
#if !defined(BL702L) && !defined(BL602) && !defined(BL702)
|
||||
#define IR_RX_FIFO_TH_SHIFT (24U)
|
||||
#define IR_RX_FIFO_TH_MASK (0x3f << IR_RX_FIFO_TH_SHIFT)
|
||||
#endif
|
||||
|
||||
#if !defined(BL616) && !defined(BL602) && !defined(BL702)
|
||||
/* 0x88 : ir_fifo_wdata */
|
||||
#define IR_TX_FIFO_WDATA_SHIFT (0U)
|
||||
#define IR_TX_FIFO_WDATA_MASK (0xffffffff << IR_TX_FIFO_WDATA_SHIFT)
|
||||
#endif
|
||||
|
||||
#if !defined(BL702L)
|
||||
/* 0x8C : ir_fifo_rdata */
|
||||
#define IR_RX_FIFO_RDATA_SHIFT (0U)
|
||||
#define IR_RX_FIFO_RDATA_MASK (0xffff << IR_RX_FIFO_RDATA_SHIFT)
|
||||
#endif
|
||||
|
||||
#endif /* __HARDWARE_IR_H__ */
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
#include "bflb_adc.h"
|
||||
#include "bflb_efuse.h"
|
||||
#include "hardware/adc_reg.h"
|
||||
|
||||
#if defined(BL702) || defined(BL602) || defined(BL702L)
|
||||
@ -7,6 +8,9 @@
|
||||
#define ADC_GPIP_BASE ((uint32_t)0x20002000)
|
||||
#endif
|
||||
|
||||
volatile float coe = 1.0;
|
||||
volatile uint32_t tsen_offset;
|
||||
|
||||
void bflb_adc_init(struct bflb_device_s *dev, const struct bflb_adc_config_s *config)
|
||||
{
|
||||
uint32_t regval;
|
||||
@ -114,6 +118,9 @@ void bflb_adc_init(struct bflb_device_s *dev, const struct bflb_adc_config_s *co
|
||||
regval |= AON_GPADC_NEG_SATUR_MASK;
|
||||
regval |= AON_GPADC_POS_SATUR_MASK;
|
||||
putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
|
||||
|
||||
coe = bflb_efuse_get_adc_trim(); /* read from efuse */
|
||||
tsen_offset = bflb_efuse_get_adc_tsen_trim(); /* read from efuse */
|
||||
}
|
||||
|
||||
void bflb_adc_deinit(struct bflb_device_s *dev)
|
||||
@ -205,7 +212,7 @@ int bflb_adc_channel_config(struct bflb_device_s *dev, struct bflb_adc_channel_s
|
||||
regval2 = 0;
|
||||
for (uint8_t i = 0; i < (channels - 6); i++) {
|
||||
regval |= (chan[i + 6].pos_chan << (i * 5));
|
||||
regval |= (chan[i + 6].neg_chan << (i * 5));
|
||||
regval2 |= (chan[i + 6].neg_chan << (i * 5));
|
||||
}
|
||||
putreg32(regval, reg_base + AON_GPADC_REG_SCN_POS2_OFFSET);
|
||||
putreg32(regval2, reg_base + AON_GPADC_REG_SCN_NEG2_OFFSET);
|
||||
@ -226,6 +233,12 @@ void bflb_adc_start_conversion(struct bflb_device_s *dev)
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
|
||||
regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
|
||||
regval &= ~AON_GPADC_CONV_START;
|
||||
putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
|
||||
|
||||
bflb_mtimer_delay_us(100);
|
||||
|
||||
regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
|
||||
regval |= AON_GPADC_CONV_START;
|
||||
putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
|
||||
@ -398,7 +411,6 @@ void bflb_adc_parse_result(struct bflb_device_s *dev, uint32_t *buffer, struct b
|
||||
uint8_t vref;
|
||||
uint32_t conv_result = 0;
|
||||
uint16_t ref = 3200;
|
||||
float coe = 1.0;
|
||||
uint8_t neg = 0;
|
||||
uint32_t tmp;
|
||||
|
||||
@ -525,7 +537,7 @@ void bflb_adc_tsen_init(struct bflb_device_s *dev, uint8_t tsen_mod)
|
||||
putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
|
||||
}
|
||||
|
||||
float bflb_adc_tsen_get_temp(struct bflb_device_s *dev, uint32_t tsen_offset)
|
||||
float bflb_adc_tsen_get_temp(struct bflb_device_s *dev)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t reg_base;
|
||||
@ -533,6 +545,7 @@ float bflb_adc_tsen_get_temp(struct bflb_device_s *dev, uint32_t tsen_offset)
|
||||
uint32_t v0 = 0, v1 = 0;
|
||||
float temp = 0;
|
||||
uint32_t raw_data;
|
||||
uint64_t start_time;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
|
||||
@ -544,30 +557,35 @@ float bflb_adc_tsen_get_temp(struct bflb_device_s *dev, uint32_t tsen_offset)
|
||||
regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
|
||||
regval &= ~AON_GPADC_TSVBE_LOW;
|
||||
putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
|
||||
|
||||
bflb_adc_start_conversion(dev);
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (bflb_adc_get_count(dev) == 0) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
raw_data = bflb_adc_read_raw(dev);
|
||||
bflb_adc_parse_result(dev, &raw_data, &result, 1);
|
||||
bflb_adc_stop_conversion(dev);
|
||||
v0 = result.value;
|
||||
|
||||
regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
|
||||
regval |= (0 << 22);
|
||||
regval |= GPIP_GPADC_FIFO_CLR;
|
||||
putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
|
||||
|
||||
regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
|
||||
regval |= AON_GPADC_TSVBE_LOW;
|
||||
putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
|
||||
|
||||
bflb_adc_start_conversion(dev);
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (bflb_adc_get_count(dev) == 0) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
raw_data = bflb_adc_read_raw(dev);
|
||||
bflb_adc_parse_result(dev, &raw_data, &result, 1);
|
||||
bflb_adc_stop_conversion(dev);
|
||||
v1 = result.value;
|
||||
|
||||
if (v0 > v1) {
|
||||
temp = (((float)v0 - (float)v1) - (float)tsen_offset) / 7.753;
|
||||
} else {
|
||||
|
||||
@ -38,11 +38,21 @@ void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset)
|
||||
} else if (mode == GPIO_OUTPUT) {
|
||||
regval |= (1 << (pin & 0x1f));
|
||||
function = 11;
|
||||
#if defined(BL702L)
|
||||
if (function == 22) {
|
||||
regval &= ~(1 << (pin & 0x1f));
|
||||
}
|
||||
#endif
|
||||
} else if (mode == GPIO_ANALOG) {
|
||||
regval &= ~(1 << (pin & 0x1f));
|
||||
function = 10;
|
||||
} else if (mode == GPIO_ALTERNATE) {
|
||||
cfg |= (1 << (is_odd * 16 + 0));
|
||||
#if defined(BL702L)
|
||||
if (function == 22) {
|
||||
cfg &= ~(1 << (is_odd * 16 + 0));
|
||||
}
|
||||
#endif
|
||||
regval &= ~(1 << (pin & 0x1f));
|
||||
} else {
|
||||
}
|
||||
@ -63,7 +73,9 @@ void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset)
|
||||
cfg |= (function << (is_odd * 16 + 8));
|
||||
#if defined(BL702L)
|
||||
/* configure output mode:set and clr mode */
|
||||
cfg |= (1 << (is_odd * 16 + 15));
|
||||
if ((function != 22) || (function != 21)) {
|
||||
cfg |= (1 << (is_odd * 16 + 15));
|
||||
}
|
||||
#endif
|
||||
#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
|
||||
cfg_address = reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2);
|
||||
@ -109,8 +121,10 @@ void bflb_gpio_deinit(struct bflb_device_s *dev, uint8_t pin)
|
||||
|
||||
void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin)
|
||||
{
|
||||
#if defined(BL702) || defined(BL602) || defined(BL702L)
|
||||
#if defined(BL702) || defined(BL602)
|
||||
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
|
||||
#elif defined(BL702L)
|
||||
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL35_OFFSET);
|
||||
#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
|
||||
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG138_OFFSET + ((pin >> 5) << 2));
|
||||
#endif
|
||||
@ -118,8 +132,10 @@ void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin)
|
||||
|
||||
void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin)
|
||||
{
|
||||
#if defined(BL702) || defined(BL602) || defined(BL702L)
|
||||
#if defined(BL702) || defined(BL602)
|
||||
putreg32(0 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
|
||||
#elif defined(BL702L)
|
||||
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL36_OFFSET);
|
||||
#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
|
||||
putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG140_OFFSET + ((pin >> 5) << 2));
|
||||
#endif
|
||||
@ -147,11 +163,16 @@ void bflb_gpio_int_init(struct bflb_device_s *dev, uint8_t pin, uint8_t trig_mod
|
||||
bflb_gpio_int_mask(dev, pin, true);
|
||||
bflb_gpio_int_clear(dev, pin);
|
||||
|
||||
#if defined(BL702) || defined(BL602) || defined(BL702L)
|
||||
#if defined(BL702) || defined(BL602)
|
||||
cfg_address = reg_base + GLB_GPIO_INT_MODE_SET1_OFFSET + ((pin / 10) << 2);
|
||||
regval = getreg32(cfg_address);
|
||||
regval &= ~(0x07 << ((pin % 10) * 3));
|
||||
regval |= (trig_mode << ((pin % 10) * 3));
|
||||
#elif defined(BL702L)
|
||||
cfg_address = reg_base + GLB_GPIO_INT_MODE_SET1_OFFSET + ((pin / 8) << 2);
|
||||
regval = getreg32(cfg_address);
|
||||
regval &= ~(0x0f << ((pin % 8) * 4));
|
||||
regval |= (trig_mode << ((pin % 8) * 4));
|
||||
#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
|
||||
cfg_address = reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2);
|
||||
regval = getreg32(cfg_address);
|
||||
|
||||
@ -178,6 +178,7 @@ static int bflb_i2c_write_bytes(struct bflb_device_s *dev, uint8_t *data, uint32
|
||||
uint32_t reg_base;
|
||||
uint32_t temp = 0;
|
||||
uint8_t *tmp_buf;
|
||||
uint64_t start_time;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
tmp_buf = data;
|
||||
@ -187,7 +188,11 @@ static int bflb_i2c_write_bytes(struct bflb_device_s *dev, uint8_t *data, uint32
|
||||
}
|
||||
tmp_buf += 4;
|
||||
len -= 4;
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while ((getreg32(reg_base + I2C_FIFO_CONFIG_1_OFFSET) & I2C_TX_FIFO_CNT_MASK) == 0) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
putreg32(temp, reg_base + I2C_FIFO_WDATA_OFFSET);
|
||||
if (!bflb_i2c_isenable(dev)) {
|
||||
@ -200,7 +205,11 @@ static int bflb_i2c_write_bytes(struct bflb_device_s *dev, uint8_t *data, uint32
|
||||
for (uint8_t i = 0; i < len; i++) {
|
||||
temp += (tmp_buf[i] << ((i % 4) * 8));
|
||||
}
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while ((getreg32(reg_base + I2C_FIFO_CONFIG_1_OFFSET) & I2C_TX_FIFO_CNT_MASK) == 0) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
putreg32(temp, reg_base + I2C_FIFO_WDATA_OFFSET);
|
||||
if (!bflb_i2c_isenable(dev)) {
|
||||
@ -208,7 +217,11 @@ static int bflb_i2c_write_bytes(struct bflb_device_s *dev, uint8_t *data, uint32
|
||||
}
|
||||
}
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (bflb_i2c_isbusy(dev) || !bflb_i2c_isend(dev)) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
bflb_i2c_disable(dev);
|
||||
|
||||
@ -220,6 +233,7 @@ static int bflb_i2c_read_bytes(struct bflb_device_s *dev, uint8_t *data, uint32_
|
||||
uint32_t reg_base;
|
||||
uint32_t temp = 0;
|
||||
uint8_t *tmp_buf;
|
||||
uint64_t start_time;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
tmp_buf = data;
|
||||
@ -227,7 +241,11 @@ static int bflb_i2c_read_bytes(struct bflb_device_s *dev, uint8_t *data, uint32_
|
||||
bflb_i2c_enable(dev);
|
||||
|
||||
while (len >= 4) {
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while ((getreg32(reg_base + I2C_FIFO_CONFIG_1_OFFSET) & I2C_RX_FIFO_CNT_MASK) == 0) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
temp = getreg32(reg_base + I2C_FIFO_RDATA_OFFSET);
|
||||
PUT_UINT32_LE(tmp_buf, temp);
|
||||
@ -236,7 +254,11 @@ static int bflb_i2c_read_bytes(struct bflb_device_s *dev, uint8_t *data, uint32_
|
||||
}
|
||||
|
||||
if (len > 0) {
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while ((getreg32(reg_base + I2C_FIFO_CONFIG_1_OFFSET) & I2C_RX_FIFO_CNT_MASK) == 0) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
temp = getreg32(reg_base + I2C_FIFO_RDATA_OFFSET);
|
||||
|
||||
@ -245,7 +267,11 @@ static int bflb_i2c_read_bytes(struct bflb_device_s *dev, uint8_t *data, uint32_
|
||||
}
|
||||
}
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (bflb_i2c_isbusy(dev) || !bflb_i2c_isend(dev)) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
bflb_i2c_disable(dev);
|
||||
|
||||
@ -331,6 +357,7 @@ int bflb_i2c_transfer(struct bflb_device_s *dev, struct bflb_i2c_msg_s *msgs, in
|
||||
uint16_t subaddr = 0;
|
||||
uint16_t subaddr_size = 0;
|
||||
bool is_addr_10bit = false;
|
||||
int ret = 0;
|
||||
|
||||
bflb_i2c_disable(dev);
|
||||
|
||||
@ -361,14 +388,20 @@ int bflb_i2c_transfer(struct bflb_device_s *dev, struct bflb_i2c_msg_s *msgs, in
|
||||
if (msgs[i].flags & I2C_M_READ) {
|
||||
bflb_i2c_set_dir(dev, 1);
|
||||
if ((msgs[i].flags & I2C_M_DMA) == 0) {
|
||||
bflb_i2c_read_bytes(dev, msgs[i].buffer, msgs[i].length);
|
||||
ret = bflb_i2c_read_bytes(dev, msgs[i].buffer, msgs[i].length);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
bflb_i2c_enable(dev);
|
||||
}
|
||||
} else {
|
||||
bflb_i2c_set_dir(dev, 0);
|
||||
if ((msgs[i].flags & I2C_M_DMA) == 0) {
|
||||
bflb_i2c_write_bytes(dev, msgs[i].buffer, msgs[i].length);
|
||||
ret = bflb_i2c_write_bytes(dev, msgs[i].buffer, msgs[i].length);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
} else {
|
||||
bflb_i2c_enable(dev);
|
||||
}
|
||||
@ -408,7 +441,7 @@ uint32_t bflb_i2c_get_intstatus(struct bflb_device_s *dev)
|
||||
uint32_t reg_base;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
return(getreg32(reg_base + I2C_INT_STS_OFFSET) & 0xff);
|
||||
return (getreg32(reg_base + I2C_INT_STS_OFFSET) & 0xff);
|
||||
}
|
||||
|
||||
int bflb_i2c_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
|
||||
@ -416,7 +449,7 @@ int bflb_i2c_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
|
||||
int ret = 0;
|
||||
switch (cmd) {
|
||||
default:
|
||||
ret = -EPERM;
|
||||
ret = -EPERM;
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
|
||||
@ -4,6 +4,7 @@
|
||||
|
||||
#define DIVIDE_ROUND(a, b) ((2 * a + b) / (2 * b))
|
||||
|
||||
#if !defined(BL616)
|
||||
void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s *config)
|
||||
{
|
||||
uint32_t reg_base;
|
||||
@ -80,6 +81,16 @@ void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s
|
||||
if (tx_config->tx_mode != IR_TX_CUSTOMIZE) {
|
||||
tx_config->modu_width_1 = ((ir_clock / 11310 + 5) / 10 - 1) & 0xff;
|
||||
tx_config->modu_width_0 = ((ir_clock / 5655 + 5) / 10 - 1) & 0xff;
|
||||
} else {
|
||||
if (tx_config->output_modulation != 0 && tx_config->freerun_enable != 0) {
|
||||
tx_config->continue_enable = 0;
|
||||
if (tx_config->tail_pulse_width_1 < 5) {
|
||||
tx_config->tail_pulse_width_1 = 5;
|
||||
}
|
||||
if (tx_config->tail_pulse_width_0 < 5) {
|
||||
tx_config->tail_pulse_width_0 = 5;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
@ -172,10 +183,16 @@ void bflb_ir_send(struct bflb_device_s *dev, uint32_t *data, uint32_t length)
|
||||
}
|
||||
}
|
||||
|
||||
while((bflb_ir_txint_status(dev) & IR_TX_INT_END) == 0){
|
||||
/* Waiting for sending */
|
||||
if ((getreg32(reg_base + IRTX_CONFIG_OFFSET) & IR_CR_IRTX_FRM_EN) == 0) {
|
||||
while((bflb_ir_txint_status(dev) & IR_TX_INT_END) == 0){
|
||||
/* Waiting for sending */
|
||||
}
|
||||
} else {
|
||||
while(bflb_ir_txfifo_cnt(dev) < 4){
|
||||
/* Waiting for sending */
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
regval &= ~IR_CR_IRTX_EN;
|
||||
putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
|
||||
|
||||
@ -334,7 +351,9 @@ void bflb_ir_txfifo_clear(struct bflb_device_s *dev)
|
||||
regval |= IR_TX_FIFO_CLR;
|
||||
putreg32(regval, reg_base + IR_FIFO_CONFIG_0_OFFSET);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(BL702L)
|
||||
void bflb_ir_rx_init(struct bflb_device_s *dev, const struct bflb_ir_rx_config_s *config)
|
||||
{
|
||||
uint32_t reg_base;
|
||||
@ -513,3 +532,4 @@ void bflb_ir_rxfifo_clear(struct bflb_device_s *dev)
|
||||
regval |= IR_RX_FIFO_CLR;
|
||||
putreg32(regval, reg_base + IR_FIFO_CONFIG_0_OFFSET);
|
||||
}
|
||||
#endif
|
||||
|
||||
@ -10,6 +10,7 @@ extern struct bflb_irq_info_s g_irqvector[];
|
||||
|
||||
void irq_unexpected_isr(int irq, void *arg)
|
||||
{
|
||||
printf("irq :%d unregistered\r\n", irq);
|
||||
}
|
||||
|
||||
void bflb_irq_initialize(void)
|
||||
@ -23,9 +24,9 @@ void bflb_irq_initialize(void)
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t bflb_irq_save(void)
|
||||
ATTR_TCM_SECTION uintptr_t bflb_irq_save(void)
|
||||
{
|
||||
uint32_t oldstat;
|
||||
uintptr_t oldstat;
|
||||
|
||||
/* Read mstatus & clear machine interrupt enable (MIE) in mstatus */
|
||||
|
||||
@ -35,7 +36,7 @@ uint32_t bflb_irq_save(void)
|
||||
return oldstat;
|
||||
}
|
||||
|
||||
void bflb_irq_restore(uint32_t flags)
|
||||
ATTR_TCM_SECTION void bflb_irq_restore(uintptr_t flags)
|
||||
{
|
||||
/* Write flags to mstatus */
|
||||
|
||||
@ -59,6 +60,8 @@ int bflb_irq_detach(int irq)
|
||||
if (irq > CONFIG_IRQ_NUM) {
|
||||
return -EINVAL;
|
||||
}
|
||||
g_irqvector[irq].handler = irq_unexpected_isr;
|
||||
g_irqvector[irq].arg = NULL;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -67,6 +70,11 @@ void bflb_irq_enable(int irq)
|
||||
#if defined(BL702) || defined(BL602) || defined(BL702L)
|
||||
putreg8(1, CLIC_HART0_BASE + CLIC_INTIE_OFFSET + irq);
|
||||
#else
|
||||
#if (defined(BL808) || defined(BL606P)) && defined(CPU_D0)
|
||||
if (csi_vic_get_prio(irq) == 0) {
|
||||
csi_vic_set_prio(irq, 1);
|
||||
}
|
||||
#endif
|
||||
csi_vic_enable_irq(irq);
|
||||
#endif
|
||||
}
|
||||
@ -98,12 +106,25 @@ void bflb_irq_clear_pending(int irq)
|
||||
#endif
|
||||
}
|
||||
|
||||
void bflb_irq_set_nlbits(uint8_t nlbits)
|
||||
{
|
||||
#if defined(BL702) || defined(BL602) || defined(BL702L)
|
||||
uint8_t clicCfg = getreg8(CLIC_HART0_BASE + CLIC_CFG_OFFSET);
|
||||
putreg8((clicCfg & 0xe1) | ((nlbits & 0xf) << 1), CLIC_HART0_BASE + CLIC_CFG_OFFSET);
|
||||
#else
|
||||
#if !defined(CPU_D0)
|
||||
CLIC->CLICCFG = ((nlbits & 0xf) << 1) | 1;
|
||||
#endif
|
||||
#endif
|
||||
}
|
||||
|
||||
void bflb_irq_set_priority(int irq, uint8_t preemptprio, uint8_t subprio)
|
||||
{
|
||||
#if defined(BL702) || defined(BL602)
|
||||
#elif defined(BL702L)
|
||||
#if defined(BL702) || defined(BL602) || defined(BL702L)
|
||||
uint8_t nlbits = getreg8(CLIC_HART0_BASE + CLIC_CFG_OFFSET) >> 1 & 0xf;
|
||||
uint8_t clicIntCfg = getreg8(CLIC_HART0_BASE + CLIC_INTCFG_OFFSET + irq);
|
||||
putreg8((clicIntCfg & 0xf) | (preemptprio << (8 - nlbits)) | ((subprio & (0xf >> nlbits)) << 4), CLIC_HART0_BASE + CLIC_INTCFG_OFFSET + irq);
|
||||
#else
|
||||
csi_vic_set_prio(irq, preemptprio);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
109
drivers/lhal/src/bflb_l1c.c
Normal file
109
drivers/lhal/src/bflb_l1c.c
Normal file
@ -0,0 +1,109 @@
|
||||
#include "bflb_l1c.h"
|
||||
|
||||
#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
|
||||
#include "csi_core.h"
|
||||
void bflb_l1c_icache_enable(void)
|
||||
{
|
||||
csi_icache_enable();
|
||||
}
|
||||
|
||||
void bflb_l1c_icache_disable(void)
|
||||
{
|
||||
csi_icache_disable();
|
||||
}
|
||||
|
||||
ATTR_TCM_SECTION void bflb_l1c_icache_invalid_all(void)
|
||||
{
|
||||
csi_icache_invalid();
|
||||
}
|
||||
|
||||
void bflb_l1c_dcache_enable(void)
|
||||
{
|
||||
csi_dcache_enable();
|
||||
}
|
||||
|
||||
void bflb_l1c_dcache_disable(void)
|
||||
{
|
||||
csi_dcache_disable();
|
||||
}
|
||||
|
||||
ATTR_TCM_SECTION void bflb_l1c_dcache_clean_all(void)
|
||||
{
|
||||
csi_dcache_clean();
|
||||
}
|
||||
|
||||
ATTR_TCM_SECTION void bflb_l1c_dcache_invalidate_all(void)
|
||||
{
|
||||
csi_dcache_invalid();
|
||||
}
|
||||
|
||||
ATTR_TCM_SECTION void bflb_l1c_dcache_clean_invalidate_all(void)
|
||||
{
|
||||
csi_dcache_clean_invalid();
|
||||
}
|
||||
|
||||
ATTR_TCM_SECTION void bflb_l1c_dcache_clean_range(void *addr, uint32_t size)
|
||||
{
|
||||
csi_dcache_clean_range(addr, size);
|
||||
}
|
||||
|
||||
ATTR_TCM_SECTION void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size)
|
||||
{
|
||||
csi_dcache_invalid_range(addr, size);
|
||||
}
|
||||
|
||||
ATTR_TCM_SECTION void bflb_l1c_dcache_clean_invalidate_range(void *addr, uint32_t size)
|
||||
{
|
||||
csi_dcache_clean_invalid_range(addr, size);
|
||||
}
|
||||
#else
|
||||
|
||||
extern void L1C_Cache_Enable_Set(uint8_t wayDisable);
|
||||
extern void L1C_Cache_Flush(void);
|
||||
|
||||
void bflb_l1c_icache_enable(void)
|
||||
{
|
||||
}
|
||||
|
||||
void bflb_l1c_icache_disable(void)
|
||||
{
|
||||
L1C_Cache_Enable_Set(0x0f);
|
||||
}
|
||||
|
||||
ATTR_TCM_SECTION void bflb_l1c_icache_invalid_all(void)
|
||||
{
|
||||
L1C_Cache_Flush();
|
||||
}
|
||||
|
||||
void bflb_l1c_dcache_enable(void)
|
||||
{
|
||||
}
|
||||
|
||||
void bflb_l1c_dcache_disable(void)
|
||||
{
|
||||
}
|
||||
|
||||
void bflb_l1c_dcache_clean_all(void)
|
||||
{
|
||||
}
|
||||
|
||||
void bflb_l1c_dcache_invalidate_all(void)
|
||||
{
|
||||
}
|
||||
|
||||
void bflb_l1c_dcache_clean_invalidate_all(void)
|
||||
{
|
||||
}
|
||||
|
||||
void bflb_l1c_dcache_clean_range(void *addr, uint32_t size)
|
||||
{
|
||||
}
|
||||
|
||||
void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size)
|
||||
{
|
||||
}
|
||||
|
||||
void bflb_l1c_dcache_clean_invalidate_range(void *addr, uint32_t size)
|
||||
{
|
||||
}
|
||||
#endif
|
||||
@ -166,8 +166,6 @@ void bflb_mjpeg_init(struct bflb_device_s *dev, const struct bflb_mjpeg_config_s
|
||||
|
||||
if (min_framesize > config->output_bufsize) {
|
||||
printf("mjpeg output size is too small\r\n");
|
||||
while (1) {
|
||||
}
|
||||
}
|
||||
|
||||
putreg32(config->output_bufaddr, reg_base + MJPEG_JPEG_FRAME_ADDR_OFFSET);
|
||||
|
||||
@ -5,15 +5,21 @@ void bflb_pwm_v1_channel_init(struct bflb_device_s *dev, uint8_t ch, const struc
|
||||
{
|
||||
uint32_t reg_base;
|
||||
uint32_t regval;
|
||||
uint64_t start_time;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
/* stop pwm */
|
||||
regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
regval |= PWM_STOP_EN;
|
||||
putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
do {
|
||||
regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
regval &= PWM_STS_TOP;
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return;
|
||||
}
|
||||
} while (regval == 0);
|
||||
|
||||
/* config clock source and dividor */
|
||||
@ -41,37 +47,25 @@ void bflb_pwm_v1_channel_init(struct bflb_device_s *dev, uint8_t ch, const struc
|
||||
putreg32(regval, reg_base + PWM0_PERIOD_OFFSET + ch * 0x20);
|
||||
}
|
||||
|
||||
void bflb_pwm_v1_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold)
|
||||
{
|
||||
uint32_t reg_base;
|
||||
uint32_t regval;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
|
||||
regval = getreg32(reg_base + PWM0_THRE1_OFFSET + ch * 0x20);
|
||||
regval &= ~PWM_THRE1_MASK;
|
||||
regval |= low_threhold;
|
||||
putreg32(regval, reg_base + PWM0_THRE1_OFFSET + ch * 0x20);
|
||||
|
||||
regval = getreg32(reg_base + PWM0_THRE2_OFFSET + ch * 0x20);
|
||||
regval &= ~PWM_THRE2_MASK;
|
||||
regval |= high_threhold;
|
||||
putreg32(regval, reg_base + PWM0_THRE2_OFFSET + ch * 0x20);
|
||||
}
|
||||
|
||||
void bflb_pwm_v1_deinit(struct bflb_device_s *dev, uint8_t ch)
|
||||
void bflb_pwm_v1_channel_deinit(struct bflb_device_s *dev, uint8_t ch)
|
||||
{
|
||||
uint32_t reg_base;
|
||||
uint32_t regval;
|
||||
uint64_t start_time;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
/* stop pwmx */
|
||||
regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
regval |= PWM_STOP_EN;
|
||||
putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
do {
|
||||
regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
regval &= PWM_STS_TOP;
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return;
|
||||
}
|
||||
} while (regval == 0);
|
||||
|
||||
/* restore pwmx_clkdiv register with default value */
|
||||
@ -97,6 +91,50 @@ void bflb_pwm_v1_deinit(struct bflb_device_s *dev, uint8_t ch)
|
||||
putreg32(0xFFFFFFFF, reg_base + PWM_INT_CONFIG_OFFSET);
|
||||
}
|
||||
|
||||
void bflb_pwm_v1_start(struct bflb_device_s *dev, uint8_t ch)
|
||||
{
|
||||
uint32_t reg_base;
|
||||
uint32_t regval;
|
||||
uint32_t start_time;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
|
||||
regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
regval &= ~PWM_STOP_EN;
|
||||
putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
do {
|
||||
regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
regval &= PWM_STS_TOP;
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return;
|
||||
}
|
||||
} while (regval != 0);
|
||||
}
|
||||
|
||||
void bflb_pwm_v1_stop(struct bflb_device_s *dev, uint8_t ch)
|
||||
{
|
||||
uint32_t reg_base;
|
||||
uint32_t regval;
|
||||
uint32_t start_time;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
|
||||
regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
regval |= PWM_STOP_EN;
|
||||
putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
do {
|
||||
regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
regval &= PWM_STS_TOP;
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return;
|
||||
}
|
||||
} while (regval == 0);
|
||||
}
|
||||
|
||||
void bflb_pwm_v1_set_period(struct bflb_device_s *dev, uint8_t ch, uint16_t period)
|
||||
{
|
||||
uint32_t reg_base;
|
||||
@ -110,36 +148,22 @@ void bflb_pwm_v1_set_period(struct bflb_device_s *dev, uint8_t ch, uint16_t peri
|
||||
putreg32(regval, reg_base + PWM0_PERIOD_OFFSET + ch * 0x20);
|
||||
}
|
||||
|
||||
void bflb_pwm_v1_start(struct bflb_device_s *dev, uint8_t ch)
|
||||
void bflb_pwm_v1_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold)
|
||||
{
|
||||
uint32_t reg_base;
|
||||
uint32_t regval;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
|
||||
regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
regval &= ~PWM_STOP_EN;
|
||||
putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
do {
|
||||
regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
regval &= PWM_STS_TOP;
|
||||
} while (regval != 0);
|
||||
}
|
||||
regval = getreg32(reg_base + PWM0_THRE1_OFFSET + ch * 0x20);
|
||||
regval &= ~PWM_THRE1_MASK;
|
||||
regval |= low_threhold;
|
||||
putreg32(regval, reg_base + PWM0_THRE1_OFFSET + ch * 0x20);
|
||||
|
||||
void bflb_pwm_v1_stop(struct bflb_device_s *dev, uint8_t ch)
|
||||
{
|
||||
uint32_t reg_base;
|
||||
uint32_t regval;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
|
||||
regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
regval |= PWM_STOP_EN;
|
||||
putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
do {
|
||||
regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
|
||||
regval &= PWM_STS_TOP;
|
||||
} while (regval == 0);
|
||||
regval = getreg32(reg_base + PWM0_THRE2_OFFSET + ch * 0x20);
|
||||
regval &= ~PWM_THRE2_MASK;
|
||||
regval |= high_threhold;
|
||||
putreg32(regval, reg_base + PWM0_THRE2_OFFSET + ch * 0x20);
|
||||
}
|
||||
|
||||
void bflb_pwm_v1_int_enable(struct bflb_device_s *dev, uint8_t ch, bool enable)
|
||||
|
||||
@ -5,15 +5,21 @@ void bflb_pwm_v2_init(struct bflb_device_s *dev, const struct bflb_pwm_v2_config
|
||||
{
|
||||
uint32_t reg_base;
|
||||
uint32_t regval;
|
||||
uint64_t start_time;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
/* stop pwm */
|
||||
regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
|
||||
regval |= PWM_STOP_EN;
|
||||
putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
do {
|
||||
regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
|
||||
regval &= PWM_STS_STOP;
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return;
|
||||
}
|
||||
} while (regval == 0);
|
||||
|
||||
/* config clock source and dividor */
|
||||
@ -42,15 +48,21 @@ void bflb_pwm_v2_deinit(struct bflb_device_s *dev)
|
||||
{
|
||||
uint32_t reg_base;
|
||||
uint32_t regval;
|
||||
uint64_t start_time;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
/* stop pwm */
|
||||
regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
|
||||
regval |= PWM_STOP_EN;
|
||||
putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
do {
|
||||
regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
|
||||
regval &= PWM_STS_STOP;
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return;
|
||||
}
|
||||
} while (regval == 0);
|
||||
|
||||
/* restore pwm_mc0_config0 register with default value */
|
||||
@ -99,14 +111,20 @@ void bflb_pwm_v2_start(struct bflb_device_s *dev)
|
||||
{
|
||||
uint32_t reg_base;
|
||||
uint32_t regval;
|
||||
uint64_t start_time;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
|
||||
regval &= ~PWM_STOP_EN;
|
||||
putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
do {
|
||||
regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
|
||||
regval &= PWM_STS_STOP;
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return;
|
||||
}
|
||||
} while (regval != 0);
|
||||
}
|
||||
|
||||
@ -114,14 +132,20 @@ void bflb_pwm_v2_stop(struct bflb_device_s *dev)
|
||||
{
|
||||
uint32_t reg_base;
|
||||
uint32_t regval;
|
||||
uint64_t start_time;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
|
||||
regval |= PWM_STOP_EN;
|
||||
putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
do {
|
||||
regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
|
||||
regval &= PWM_STS_STOP;
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return;
|
||||
}
|
||||
} while (regval == 0);
|
||||
}
|
||||
|
||||
@ -356,7 +380,7 @@ int bflb_pwm_v2_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
|
||||
break;
|
||||
|
||||
default:
|
||||
ret = -EPERM;
|
||||
ret = -EPERM;
|
||||
break;
|
||||
}
|
||||
return ret;
|
||||
|
||||
@ -138,6 +138,7 @@ int bflb_aes_encrypt(struct bflb_device_s *dev,
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t reg_base;
|
||||
uint64_t start_time;
|
||||
uint8_t mode;
|
||||
uint8_t *temp_iv = (uint8_t *)iv;
|
||||
|
||||
@ -186,7 +187,11 @@ int bflb_aes_encrypt(struct bflb_device_s *dev,
|
||||
regval |= SEC_ENG_SE_AES_0_TRIG_1T;
|
||||
putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET) & SEC_ENG_SE_AES_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -199,6 +204,7 @@ int bflb_aes_decrypt(struct bflb_device_s *dev,
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t reg_base;
|
||||
uint64_t start_time;
|
||||
uint8_t mode;
|
||||
uint8_t *temp_iv = (uint8_t *)iv;
|
||||
|
||||
@ -247,7 +253,11 @@ int bflb_aes_decrypt(struct bflb_device_s *dev,
|
||||
regval |= SEC_ENG_SE_AES_0_TRIG_1T;
|
||||
putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET) & SEC_ENG_SE_AES_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -292,6 +302,7 @@ int bflb_aes_link_update(struct bflb_device_s *dev,
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t reg_base;
|
||||
uint64_t start_time;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
|
||||
@ -320,7 +331,11 @@ int bflb_aes_link_update(struct bflb_device_s *dev,
|
||||
__asm volatile("nop");
|
||||
__asm volatile("nop");
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET) & SEC_ENG_SE_AES_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
176
drivers/lhal/src/bflb_sec_irq.c
Normal file
176
drivers/lhal/src/bflb_sec_irq.c
Normal file
@ -0,0 +1,176 @@
|
||||
#include "bflb_sec_irq.h"
|
||||
#include "hardware/sec_eng_reg.h"
|
||||
|
||||
struct bflb_sec_irq_callback {
|
||||
void (*handler)(void *arg);
|
||||
void *arg;
|
||||
};
|
||||
|
||||
#if defined(BL702) || defined(BL602) || defined(BL702L)
|
||||
#define BFLB_SEC_ENG_BASE ((uint32_t)0x40004000)
|
||||
#elif defined(BL616) || defined(BL606P) || defined(BL808)
|
||||
#define BFLB_SEC_ENG_BASE ((uint32_t)0x20004000)
|
||||
#elif defined(BL628)
|
||||
#define BFLB_SEC_ENG_BASE ((uint32_t)0x20080000)
|
||||
#endif
|
||||
|
||||
struct bflb_sec_irq_callback sec_eng_callback[6];
|
||||
|
||||
void sec_eng_isr(int irq, void *arg)
|
||||
{
|
||||
uint32_t regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_AES_0_CTRL_OFFSET);
|
||||
if (regval & SEC_ENG_SE_AES_0_INT) {
|
||||
regval |= SEC_ENG_SE_AES_0_INT_CLR_1T;
|
||||
putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_AES_0_CTRL_OFFSET);
|
||||
if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_AES].handler) {
|
||||
sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_AES].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_AES].arg);
|
||||
}
|
||||
}
|
||||
|
||||
regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
|
||||
if (regval & SEC_ENG_SE_SHA_0_INT) {
|
||||
regval |= SEC_ENG_SE_SHA_0_INT_CLR_1T;
|
||||
putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
|
||||
if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_SHA].handler) {
|
||||
sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_SHA].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_SHA].arg);
|
||||
}
|
||||
}
|
||||
|
||||
regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_PKA_0_CTRL_0_OFFSET);
|
||||
if (regval & SEC_ENG_SE_PKA_0_INT) {
|
||||
regval |= SEC_ENG_SE_PKA_0_INT_CLR_1T;
|
||||
putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_PKA_0_CTRL_0_OFFSET);
|
||||
if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_PKA].handler) {
|
||||
sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_PKA].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_PKA].arg);
|
||||
}
|
||||
}
|
||||
|
||||
regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
|
||||
if (regval & SEC_ENG_SE_TRNG_0_INT) {
|
||||
regval |= SEC_ENG_SE_TRNG_0_INT_CLR_1T;
|
||||
putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
|
||||
if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_TRNG].handler) {
|
||||
sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_TRNG].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_TRNG].arg);
|
||||
}
|
||||
}
|
||||
|
||||
regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET);
|
||||
if (regval & SEC_ENG_SE_GMAC_0_INT) {
|
||||
regval |= SEC_ENG_SE_GMAC_0_INT_CLR_1T;
|
||||
putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET);
|
||||
if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_GMAC].handler) {
|
||||
sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_GMAC].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_GMAC].arg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void bflb_sec_int_mask(uint8_t sec_type, bool mask)
|
||||
{
|
||||
uint32_t regval;
|
||||
|
||||
switch (sec_type) {
|
||||
case BFLB_SEC_ENG_IRQ_TYPE_AES:
|
||||
regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_AES_0_CTRL_OFFSET);
|
||||
if (mask) {
|
||||
regval |= SEC_ENG_SE_AES_0_INT_MASK;
|
||||
} else {
|
||||
regval &= ~SEC_ENG_SE_AES_0_INT_MASK;
|
||||
}
|
||||
putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_AES_0_CTRL_OFFSET);
|
||||
break;
|
||||
case BFLB_SEC_ENG_IRQ_TYPE_SHA:
|
||||
regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
|
||||
if (mask) {
|
||||
regval |= SEC_ENG_SE_SHA_0_INT_MASK;
|
||||
} else {
|
||||
regval &= ~SEC_ENG_SE_SHA_0_INT_MASK;
|
||||
}
|
||||
putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
|
||||
break;
|
||||
case BFLB_SEC_ENG_IRQ_TYPE_PKA:
|
||||
regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_PKA_0_CTRL_0_OFFSET);
|
||||
if (mask) {
|
||||
regval |= SEC_ENG_SE_PKA_0_INT_MASK;
|
||||
} else {
|
||||
regval &= ~SEC_ENG_SE_PKA_0_INT_MASK;
|
||||
}
|
||||
putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_PKA_0_CTRL_0_OFFSET);
|
||||
break;
|
||||
case BFLB_SEC_ENG_IRQ_TYPE_TRNG:
|
||||
regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
|
||||
if (mask) {
|
||||
regval |= SEC_ENG_SE_TRNG_0_INT_MASK;
|
||||
} else {
|
||||
regval &= ~SEC_ENG_SE_TRNG_0_INT_MASK;
|
||||
}
|
||||
putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
|
||||
break;
|
||||
case BFLB_SEC_ENG_IRQ_TYPE_GMAC:
|
||||
regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET);
|
||||
if (mask) {
|
||||
regval |= SEC_ENG_SE_GMAC_0_INT_MASK;
|
||||
} else {
|
||||
regval &= ~SEC_ENG_SE_GMAC_0_INT_MASK;
|
||||
}
|
||||
putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET);
|
||||
break;
|
||||
case BFLB_SEC_ENG_IRQ_TYPE_CDET:
|
||||
regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_CDET_0_CTRL_0_OFFSET);
|
||||
if (mask) {
|
||||
regval |= SEC_ENG_SE_CDET_0_INT_MASK;
|
||||
} else {
|
||||
regval &= ~SEC_ENG_SE_CDET_0_INT_MASK;
|
||||
}
|
||||
putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_CDET_0_CTRL_0_OFFSET);
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
void bflb_sec_irq_attach(uint8_t sec_type, void (*callback)(void *arg), void *arg)
|
||||
{
|
||||
sec_eng_callback[sec_type].handler = callback;
|
||||
sec_eng_callback[sec_type].arg = arg;
|
||||
#if defined(BL702) || defined(BL602) || defined(BL702L)
|
||||
bflb_irq_attach(25, sec_eng_isr, NULL);
|
||||
bflb_irq_attach(26, sec_eng_isr, NULL);
|
||||
bflb_irq_attach(27, sec_eng_isr, NULL);
|
||||
bflb_irq_attach(28, sec_eng_isr, NULL);
|
||||
bflb_irq_attach(29, sec_eng_isr, NULL);
|
||||
bflb_irq_attach(30, sec_eng_isr, NULL);
|
||||
bflb_irq_enable(25);
|
||||
bflb_irq_enable(26);
|
||||
bflb_irq_enable(27);
|
||||
bflb_irq_enable(28);
|
||||
bflb_irq_enable(29);
|
||||
bflb_irq_enable(30);
|
||||
#elif (defined(BL606P) || defined(BL808)) && (defined(CPU_M0) || defined(CPU_LP))
|
||||
bflb_irq_attach(25, sec_eng_isr, NULL);
|
||||
bflb_irq_attach(26, sec_eng_isr, NULL);
|
||||
bflb_irq_attach(27, sec_eng_isr, NULL);
|
||||
bflb_irq_attach(28, sec_eng_isr, NULL);
|
||||
bflb_irq_enable(25);
|
||||
bflb_irq_enable(26);
|
||||
bflb_irq_enable(27);
|
||||
bflb_irq_enable(28);
|
||||
#elif defined(BL616) || defined(BL628)
|
||||
bflb_irq_attach(25, sec_eng_isr, NULL);
|
||||
bflb_irq_attach(26, sec_eng_isr, NULL);
|
||||
bflb_irq_attach(27, sec_eng_isr, NULL);
|
||||
bflb_irq_attach(28, sec_eng_isr, NULL);
|
||||
bflb_irq_enable(25);
|
||||
bflb_irq_enable(26);
|
||||
bflb_irq_enable(27);
|
||||
bflb_irq_enable(28);
|
||||
#endif
|
||||
bflb_sec_int_mask(sec_type, false);
|
||||
}
|
||||
|
||||
void bflb_sec_irq_detach(uint8_t sec_type)
|
||||
{
|
||||
sec_eng_callback[sec_type].handler = NULL;
|
||||
sec_eng_callback[sec_type].arg = NULL;
|
||||
bflb_sec_int_mask(sec_type, true);
|
||||
}
|
||||
@ -84,6 +84,7 @@ int bflb_sha1_update(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, con
|
||||
uint32_t reg_base;
|
||||
uint32_t fill;
|
||||
uint32_t left;
|
||||
uint64_t start_time;
|
||||
|
||||
if (len == 0) {
|
||||
return 0;
|
||||
@ -130,7 +131,11 @@ int bflb_sha1_update(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, con
|
||||
len = len % 64;
|
||||
|
||||
if (fill > 0) {
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* SHA need set se_sha_sel to 1 to keep the last sha state */
|
||||
@ -155,14 +160,22 @@ int bflb_sha1_update(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, con
|
||||
}
|
||||
|
||||
if (len > 0) {
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Copy left data into temp buffer */
|
||||
arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len);
|
||||
}
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -178,6 +191,7 @@ int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx,
|
||||
uint32_t reg_base;
|
||||
uint32_t fill;
|
||||
uint32_t left;
|
||||
uint64_t start_time;
|
||||
|
||||
if (len == 0) {
|
||||
return 0;
|
||||
@ -223,7 +237,11 @@ int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx,
|
||||
len = len % 128;
|
||||
|
||||
if (fill > 0) {
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* SHA need set se_sha_sel to 1 to keep the last sha state */
|
||||
@ -248,14 +266,22 @@ int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx,
|
||||
}
|
||||
|
||||
if (len > 0) {
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Copy left data into temp buffer */
|
||||
arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len);
|
||||
}
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -526,6 +552,7 @@ int bflb_sha1_link_update(struct bflb_device_s *dev,
|
||||
uint32_t reg_base;
|
||||
uint32_t fill;
|
||||
uint32_t left;
|
||||
uint64_t start_time;
|
||||
|
||||
if (len == 0) {
|
||||
return 0;
|
||||
@ -569,7 +596,11 @@ int bflb_sha1_link_update(struct bflb_device_s *dev,
|
||||
len = len % 64;
|
||||
|
||||
if (fill > 0) {
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Fill data */
|
||||
@ -586,14 +617,22 @@ int bflb_sha1_link_update(struct bflb_device_s *dev,
|
||||
}
|
||||
|
||||
if (len > 0) {
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Copy left data into temp buffer */
|
||||
arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len);
|
||||
}
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
@ -615,6 +654,7 @@ int bflb_sha512_link_update(struct bflb_device_s *dev,
|
||||
uint32_t reg_base;
|
||||
uint32_t fill;
|
||||
uint32_t left;
|
||||
uint64_t start_time;
|
||||
|
||||
if (len == 0) {
|
||||
return 0;
|
||||
@ -657,7 +697,11 @@ int bflb_sha512_link_update(struct bflb_device_s *dev,
|
||||
len = len % 128;
|
||||
|
||||
if (fill > 0) {
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Fill data */
|
||||
@ -674,14 +718,22 @@ int bflb_sha512_link_update(struct bflb_device_s *dev,
|
||||
}
|
||||
|
||||
if (len > 0) {
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* Copy left data into temp buffer */
|
||||
arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len);
|
||||
}
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -13,6 +13,7 @@ int bflb_trng_read(struct bflb_device_s *dev, uint8_t data[32])
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t reg_base;
|
||||
uint64_t start_time;
|
||||
uint8_t *p = (uint8_t *)data;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
@ -32,7 +33,11 @@ int bflb_trng_read(struct bflb_device_s *dev, uint8_t data[32])
|
||||
__ASM volatile("nop");
|
||||
__ASM volatile("nop");
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET) & SEC_ENG_SE_TRNG_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
|
||||
@ -49,7 +54,11 @@ int bflb_trng_read(struct bflb_device_s *dev, uint8_t data[32])
|
||||
__ASM volatile("nop");
|
||||
__ASM volatile("nop");
|
||||
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while (getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET) & SEC_ENG_SE_TRNG_0_BUSY) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
|
||||
/* copy trng value */
|
||||
|
||||
@ -215,7 +215,6 @@ ATTR_TCM_SECTION uint32_t bflb_spi_poll_send(struct bflb_device_s *dev, uint32_t
|
||||
regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
|
||||
fifo_cnt = (regval & SPI_RX_FIFO_CNT_MASK) >> SPI_RX_FIFO_CNT_SHIFT;
|
||||
} while (fifo_cnt < frame_size);
|
||||
|
||||
#else
|
||||
|
||||
/* Wait for rx data */
|
||||
@ -223,7 +222,6 @@ ATTR_TCM_SECTION uint32_t bflb_spi_poll_send(struct bflb_device_s *dev, uint32_t
|
||||
regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
|
||||
fifo_cnt = (regval & SPI_RX_FIFO_CNT_MASK) >> SPI_RX_FIFO_CNT_SHIFT;
|
||||
} while (fifo_cnt == 0);
|
||||
|
||||
#endif
|
||||
|
||||
regval = getreg32(reg_base + SPI_FIFO_RDATA_OFFSET);
|
||||
@ -338,7 +336,6 @@ ATTR_TCM_SECTION int bflb_spi_poll_exchange(struct bflb_device_s *dev, const voi
|
||||
fifo_cnt = fifo_cnt > nbytes ? nbytes : fifo_cnt;
|
||||
nbytes -= fifo_cnt;
|
||||
} else {
|
||||
continue;
|
||||
}
|
||||
|
||||
/* read and write data */
|
||||
@ -431,6 +428,20 @@ void bflb_spi_rxint_mask(struct bflb_device_s *dev, bool mask)
|
||||
putreg32(regval, reg_base + SPI_INT_STS_OFFSET);
|
||||
}
|
||||
|
||||
void bflb_spi_tcint_mask(struct bflb_device_s *dev, bool mask)
|
||||
{
|
||||
uint32_t regval;
|
||||
uint32_t reg_base = dev->reg_base;
|
||||
|
||||
regval = getreg32(reg_base + SPI_INT_STS_OFFSET);
|
||||
if (mask) {
|
||||
regval |= SPI_CR_SPI_END_MASK;
|
||||
} else {
|
||||
regval &= ~SPI_CR_SPI_END_MASK;
|
||||
}
|
||||
putreg32(regval, reg_base + SPI_INT_STS_OFFSET);
|
||||
}
|
||||
|
||||
void bflb_spi_errint_mask(struct bflb_device_s *dev, bool mask)
|
||||
{
|
||||
uint32_t regval;
|
||||
@ -456,8 +467,8 @@ uint32_t bflb_spi_get_intstatus(struct bflb_device_s *dev)
|
||||
uint32_t int_mask;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
int_status = getreg32(reg_base + SPI_INT_STS_OFFSET) & 0xff;
|
||||
int_mask = getreg32(reg_base + SPI_INT_STS_OFFSET) >> 8 & 0xff;
|
||||
int_status = getreg32(reg_base + SPI_INT_STS_OFFSET) & 0x1f;
|
||||
int_mask = getreg32(reg_base + SPI_INT_STS_OFFSET) >> 8 & 0x1f;
|
||||
return (int_status & ~int_mask);
|
||||
}
|
||||
|
||||
@ -468,7 +479,7 @@ void bflb_spi_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
regval = getreg32(reg_base + SPI_INT_STS_OFFSET);
|
||||
regval |= int_clear << 16;
|
||||
regval |= int_clear;
|
||||
putreg32(regval, reg_base + SPI_INT_STS_OFFSET);
|
||||
}
|
||||
|
||||
|
||||
@ -192,17 +192,23 @@ void bflb_uart_link_rxdma(struct bflb_device_s *dev, bool enable)
|
||||
putreg32(regval, reg_base + UART_FIFO_CONFIG_0_OFFSET);
|
||||
}
|
||||
|
||||
void bflb_uart_putchar(struct bflb_device_s *dev, int ch)
|
||||
ATTR_TCM_SECTION int bflb_uart_putchar(struct bflb_device_s *dev, int ch)
|
||||
{
|
||||
uint64_t start_time;
|
||||
uint32_t reg_base;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
start_time = bflb_mtimer_get_time_ms();
|
||||
while ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) == 0) {
|
||||
if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
}
|
||||
putreg8(ch, reg_base + UART_FIFO_WDATA_OFFSET);
|
||||
return 0;
|
||||
}
|
||||
|
||||
int bflb_uart_getchar(struct bflb_device_s *dev)
|
||||
ATTR_TCM_SECTION int bflb_uart_getchar(struct bflb_device_s *dev)
|
||||
{
|
||||
int ch = -1;
|
||||
uint32_t reg_base;
|
||||
@ -215,14 +221,19 @@ int bflb_uart_getchar(struct bflb_device_s *dev)
|
||||
return ch;
|
||||
}
|
||||
|
||||
void bflb_uart_put(struct bflb_device_s *dev, uint8_t *data, uint32_t len)
|
||||
ATTR_TCM_SECTION int bflb_uart_put(struct bflb_device_s *dev, uint8_t *data, uint32_t len)
|
||||
{
|
||||
int ret;
|
||||
for (uint32_t i = 0; i < len; i++) {
|
||||
bflb_uart_putchar(dev, data[i]);
|
||||
ret = bflb_uart_putchar(dev, data[i]);
|
||||
if (ret < 0) {
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
int bflb_uart_get(struct bflb_device_s *dev, uint8_t *data, uint32_t len)
|
||||
ATTR_TCM_SECTION int bflb_uart_get(struct bflb_device_s *dev, uint8_t *data, uint32_t len)
|
||||
{
|
||||
int ch = -1;
|
||||
uint32_t count = 0;
|
||||
@ -353,6 +364,7 @@ int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
|
||||
uint32_t tmp;
|
||||
uint32_t tx_tmp;
|
||||
uint32_t rx_tmp;
|
||||
uint32_t int_mask;
|
||||
|
||||
reg_base = dev->reg_base;
|
||||
|
||||
@ -458,14 +470,15 @@ int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
|
||||
tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
|
||||
rx_tmp = getreg32(reg_base + UART_INT_MASK_OFFSET);
|
||||
tmp &= ~UART_CR_URX_ABR_EN;
|
||||
if (arg) {
|
||||
if (arg == UART_AUTO_BAUD_0X55) {
|
||||
tmp |= UART_CR_URX_ABR_EN;
|
||||
#if !defined(BL602) && !defined(BL702)
|
||||
rx_tmp &= ~UART_CR_URX_AD5_MASK;
|
||||
#endif
|
||||
} else {
|
||||
tmp |= UART_CR_URX_ABR_EN;
|
||||
#if !defined(BL602) && !defined(BL702)
|
||||
rx_tmp &= ~UART_CR_URX_ADS_MASK;
|
||||
rx_tmp &= ~UART_CR_URX_AD5_MASK;
|
||||
} else {
|
||||
rx_tmp |= UART_CR_URX_ADS_MASK;
|
||||
rx_tmp |= UART_CR_URX_AD5_MASK;
|
||||
#endif
|
||||
}
|
||||
|
||||
@ -619,6 +632,84 @@ int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
|
||||
/* Configure rx ir pulse start position */
|
||||
putreg32(ir_config->rx_pluse_start, reg_base + UART_URX_IR_POSITION_OFFSET);
|
||||
} break;
|
||||
#endif
|
||||
case UART_CMD_SET_TX_FREERUN:
|
||||
/* Set tx freerun */
|
||||
tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
|
||||
|
||||
if (arg) {
|
||||
tx_tmp |= UART_CR_UTX_FRM_EN;
|
||||
} else {
|
||||
tx_tmp &= ~UART_CR_UTX_FRM_EN;
|
||||
}
|
||||
|
||||
putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
|
||||
break;
|
||||
case UART_CMD_SET_TX_END_INTERRUPT:
|
||||
/* Set tx end interrupt */
|
||||
int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
|
||||
if (arg) {
|
||||
int_mask &= ~UART_CR_UTX_END_MASK;
|
||||
} else {
|
||||
int_mask |= UART_CR_UTX_END_MASK;
|
||||
}
|
||||
putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
|
||||
break;
|
||||
case UART_CMD_SET_RX_END_INTERRUPT:
|
||||
/* Set rx end interrupt */
|
||||
int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
|
||||
if (arg) {
|
||||
int_mask &= ~UART_CR_URX_END_MASK;
|
||||
} else {
|
||||
int_mask |= UART_CR_URX_END_MASK;
|
||||
}
|
||||
putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
|
||||
break;
|
||||
case UART_CMD_SET_TX_TRANSFER_LEN:
|
||||
/* Set tx transfer length */
|
||||
tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
|
||||
|
||||
tx_tmp |= ((arg - 1) << UART_CR_UTX_LEN_SHIFT);
|
||||
|
||||
putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
|
||||
break;
|
||||
case UART_CMD_SET_RX_TRANSFER_LEN:
|
||||
/* Set rx transfer length */
|
||||
rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
|
||||
|
||||
rx_tmp |= ((arg - 1) << UART_CR_URX_LEN_SHIFT);
|
||||
|
||||
putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
|
||||
break;
|
||||
case UART_CMD_SET_TX_EN:
|
||||
/* Set tx enable */
|
||||
tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
|
||||
|
||||
if (arg) {
|
||||
tx_tmp |= UART_CR_UTX_EN;
|
||||
} else {
|
||||
tx_tmp &= ~UART_CR_UTX_EN;
|
||||
}
|
||||
|
||||
putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
|
||||
break;
|
||||
#if !defined(BL602) && !defined(BL702)
|
||||
case UART_CMD_SET_BCR_END_INTERRUPT:
|
||||
/* Set bcr value */
|
||||
int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
|
||||
int_mask &= ~UART_CR_URX_BCR_MASK;
|
||||
putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
|
||||
|
||||
rx_tmp = getreg32(reg_base + UART_URX_BCR_INT_CFG_OFFSET);
|
||||
rx_tmp &= ~UART_CR_URX_BCR_VALUE_MASK;
|
||||
rx_tmp |= (arg << UART_CR_URX_BCR_VALUE_SHIFT);
|
||||
putreg32(rx_tmp, reg_base + UART_URX_BCR_INT_CFG_OFFSET);
|
||||
break;
|
||||
case UART_CMD_GET_BCR_COUNT:
|
||||
/* Get bcr value */
|
||||
rx_tmp = getreg32(reg_base + UART_URX_BCR_INT_CFG_OFFSET);
|
||||
return ((rx_tmp & UART_STS_URX_BCR_COUNT_MASK) >> UART_STS_URX_BCR_COUNT_SHIFT);
|
||||
break;
|
||||
#endif
|
||||
default:
|
||||
ret = -EPERM;
|
||||
|
||||
@ -5,15 +5,31 @@ sdk_library_add_sources(startup/start_load.c)
|
||||
sdk_library_add_sources(startup/system_bl602.c)
|
||||
sdk_library_add_sources(startup/interrupt.c)
|
||||
|
||||
if(CONFIG_ROMAPI)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_romapi.c)
|
||||
sdk_add_compile_definitions(-DBFLB_USE_ROM_DRIVER)
|
||||
endif()
|
||||
|
||||
sdk_library_add_sources(bl602_std/src/bl602_aon.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_common.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_clock.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_ef_ctrl.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_glb.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_hbn.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_romapi.c)
|
||||
# sdk_library_add_sources(bl602_std/src/bl602_pds.c)
|
||||
# sdk_library_add_sources(bl602_std/src/bl602_common.c)
|
||||
# sdk_library_add_sources(bl602_std/src/bl602_l1c.c)
|
||||
# sdk_library_add_sources(bl602_std/src/bl602_aon.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_l1c.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_pds.c)
|
||||
|
||||
sdk_library_add_sources(bl602_std/src/bl602_sf_cfg.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_sf_cfg_ext.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_sf_ctrl.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_sflash.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_sflash_ext.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_xip_sflash.c)
|
||||
sdk_library_add_sources(bl602_std/src/bl602_xip_sflash_ext.c)
|
||||
|
||||
sdk_library_add_sources(port/bl602_clock.c)
|
||||
sdk_library_add_sources(port/bl602_flash.c)
|
||||
sdk_library_add_sources(port/bl602_efuse.c)
|
||||
|
||||
sdk_add_include_directories(
|
||||
bl602_std/include
|
||||
@ -24,7 +40,7 @@ SET(MCPU "riscv-e24")
|
||||
SET(MARCH "rv32imafc")
|
||||
SET(MABI "ilp32f")
|
||||
|
||||
sdk_add_compile_definitions(-DARCH_RISCV)
|
||||
sdk_add_compile_definitions(-DARCH_RISCV -DBFLB_USE_HAL_DRIVER)
|
||||
sdk_add_compile_options(-march=${MARCH} -mabi=${MABI})
|
||||
sdk_add_link_options(-march=${MARCH} -mabi=${MABI})
|
||||
|
||||
|
||||
@ -205,6 +205,11 @@ __ALWAYS_STATIC_INLINE void __disable_irq(void)
|
||||
#define arch_delay_us BL602_Delay_US
|
||||
#define arch_delay_ms BL602_Delay_MS
|
||||
|
||||
#define BFLB_Soft_CRC32 bflb_soft_crc32
|
||||
#define CPU_Interrupt_Enable(irq)
|
||||
#define CPU_Interrupt_Disable(irq)
|
||||
#define Interrupt_Handler_Register(irq, callback)
|
||||
|
||||
void BL602_Delay_US(uint32_t cnt);
|
||||
void BL602_Delay_MS(uint32_t cnt);
|
||||
#endif
|
||||
|
||||
@ -39,7 +39,7 @@
|
||||
#include "glb_reg.h"
|
||||
#include "pds_reg.h"
|
||||
#include "bl602_gpio.h"
|
||||
// #include "bl602_l1c.h"
|
||||
#include "bl602_l1c.h"
|
||||
#include "bl602_hbn.h"
|
||||
#include "bl602_sf_ctrl.h"
|
||||
#include "bl602_sf_cfg.h"
|
||||
|
||||
189
drivers/soc/bl602/bl602_std/include/bl602_l1c.h
Normal file
189
drivers/soc/bl602/bl602_std/include/bl602_l1c.h
Normal file
@ -0,0 +1,189 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file bl602_l1c.h
|
||||
* @version V1.0
|
||||
* @date
|
||||
* @brief This file is the standard driver header file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __BL602_L1C_H__
|
||||
#define __BL602_L1C_H__
|
||||
|
||||
#include "l1c_reg.h"
|
||||
#include "bl602_common.h"
|
||||
|
||||
/** @addtogroup BL602_Peripheral_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup L1C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup L1C_Public_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief L1C configuration structure type definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
BL_Fun_Type wrapDis; /*!< wrap disable */
|
||||
BL_Fun_Type bypassEn; /*!< bypass cache enable */
|
||||
uint8_t wayDis; /*!< Disable part of cache ways & used as ITCM */
|
||||
BL_Fun_Type cntEn; /*!< l1c count enable */
|
||||
} L1C_CACHE_Cfg_Type;
|
||||
|
||||
/**
|
||||
* @brief L1C BMX arb mode type definition
|
||||
*/
|
||||
typedef enum {
|
||||
L1C_BMX_ARB_FIX, /*!< 0->fix */
|
||||
L1C_BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */
|
||||
L1C_BMX_ARB_RANDOM, /*!< 3->random */
|
||||
} L1C_BMX_ARB_Type;
|
||||
|
||||
/**
|
||||
* @brief L1C BMX configuration structure type definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t timeoutEn; /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */
|
||||
BL_Fun_Type errEn; /*!< Bus error response enable */
|
||||
L1C_BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */
|
||||
} L1C_BMX_Cfg_Type;
|
||||
|
||||
/**
|
||||
* @brief L1C BMX bus err type definition
|
||||
*/
|
||||
typedef enum {
|
||||
L1C_BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */
|
||||
L1C_BMX_BUS_ERR_ADDR_DECODE, /*!< Bus addr decode error */
|
||||
} L1C_BMX_BUS_ERR_Type;
|
||||
|
||||
/**
|
||||
* @brief L1C BMX bus err interrupt type definition
|
||||
*/
|
||||
typedef enum {
|
||||
L1C_BMX_ERR_INT_ERR, /*!< L1C BMX bus err interrupt */
|
||||
L1C_BMX_ERR_INT_ALL, /*!< L1C BMX bus err interrupt max num */
|
||||
} L1C_BMX_ERR_INT_Type;
|
||||
|
||||
/**
|
||||
* @brief L1C BMX time out interrupt type definition
|
||||
*/
|
||||
typedef enum {
|
||||
L1C_BMX_TO_INT_TIMEOUT, /*!< L1C_BMX timeout interrupt */
|
||||
L1C_BMX_TO_INT_ALL, /*!< L1C_BMX timeout interrupt max num */
|
||||
} L1C_BMX_TO_INT_Type;
|
||||
|
||||
/*@} end of group L1C_Public_Types */
|
||||
|
||||
/** @defgroup L1C_Public_Constants
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup L1C_BMX_ARB_TYPE
|
||||
* @{
|
||||
*/
|
||||
#define IS_L1C_BMX_ARB_TYPE(type) (((type) == L1C_BMX_ARB_FIX) || \
|
||||
((type) == L1C_BMX_ARB_ROUND_ROBIN) || \
|
||||
((type) == L1C_BMX_ARB_RANDOM))
|
||||
|
||||
/** @defgroup L1C_BMX_BUS_ERR_TYPE
|
||||
* @{
|
||||
*/
|
||||
#define IS_L1C_BMX_BUS_ERR_TYPE(type) (((type) == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) || \
|
||||
((type) == L1C_BMX_BUS_ERR_ADDR_DECODE))
|
||||
|
||||
/** @defgroup L1C_BMX_ERR_INT_TYPE
|
||||
* @{
|
||||
*/
|
||||
#define IS_L1C_BMX_ERR_INT_TYPE(type) (((type) == L1C_BMX_ERR_INT_ERR) || \
|
||||
((type) == L1C_BMX_ERR_INT_ALL))
|
||||
|
||||
/** @defgroup L1C_BMX_TO_INT_TYPE
|
||||
* @{
|
||||
*/
|
||||
#define IS_L1C_BMX_TO_INT_TYPE(type) (((type) == L1C_BMX_TO_INT_TIMEOUT) || \
|
||||
((type) == L1C_BMX_TO_INT_ALL))
|
||||
|
||||
/*@} end of group L1C_Public_Constants */
|
||||
|
||||
/** @defgroup L1C_Public_Macros
|
||||
* @{
|
||||
*/
|
||||
#if 1
|
||||
/*NP config address */
|
||||
#define L1C_CONF_REG_NP (L1C_BASE + 0x00)
|
||||
#define L1C_HIT_CNT_LSB_REG_NP (L1C_BASE + 0x04)
|
||||
#define L1C_HIT_CNT_MSB_REG_NP (L1C_BASE + 0x08)
|
||||
#define L1C_MISS_CNT_REG_NP (L1C_BASE + 0x0C)
|
||||
/* Get miss and hit count */
|
||||
#define L1C_Get_Miss_Cnt_NP() BL602_REG_RD(L1C_MISS_CNT_REG_NP)
|
||||
#define L1C_Get_Hit_Cnt_LSB_NP() BL602_REG_RD(L1C_HIT_CNT_LSB_REG_NP)
|
||||
#define L1C_Get_Hit_Cnt_MSB_NP() BL602_REG_RD(L1C_HIT_CNT_MSB_REG_NP)
|
||||
#endif
|
||||
|
||||
/*@} end of group L1C_Public_Macros */
|
||||
|
||||
/** @defgroup L1C_Public_Functions
|
||||
* @{
|
||||
*/
|
||||
/*----------*/
|
||||
#ifndef BFLB_USE_HAL_DRIVER
|
||||
void L1C_BMX_ERR_IRQHandler(void);
|
||||
void L1C_BMX_TO_IRQHandler(void);
|
||||
#endif
|
||||
/*----------*/
|
||||
BL_Err_Type L1C_Set_Wrap(BL_Fun_Type wrap);
|
||||
BL_Err_Type L1C_Set_Way_Disable(uint8_t disableVal);
|
||||
BL_Err_Type L1C_IROM_2T_Access_Set(uint8_t enable);
|
||||
/*----------*/
|
||||
BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg);
|
||||
BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void);
|
||||
BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void);
|
||||
BL_Err_Type L1C_BMX_BusErrResponse_Enable(void);
|
||||
BL_Err_Type L1C_BMX_BusErrResponse_Disable(void);
|
||||
BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType);
|
||||
uint32_t L1C_BMX_Get_Err_Addr(void);
|
||||
BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun);
|
||||
BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType,
|
||||
intCallback_Type *cbFun);
|
||||
/*----------*/;
|
||||
|
||||
/*@} end of group L1C_Public_Functions */
|
||||
|
||||
/*@} end of group L1C */
|
||||
|
||||
/*@} end of group BL602_Peripheral_Driver */
|
||||
|
||||
#endif /* __BL602_L1C_H__ */
|
||||
318
drivers/soc/bl602/bl602_std/include/hardware/l1c_reg.h
Normal file
318
drivers/soc/bl602/bl602_std/include/hardware/l1c_reg.h
Normal file
@ -0,0 +1,318 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file l1c_reg.h
|
||||
* @version V1.2
|
||||
* @date 2019-11-22
|
||||
* @brief This file is the description of.IP register
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
#ifndef __L1C_REG_H__
|
||||
#define __L1C_REG_H__
|
||||
|
||||
#include "bl602.h"
|
||||
|
||||
/* 0x0 : l1c_config */
|
||||
#define L1C_CONFIG_OFFSET (0x0)
|
||||
#define L1C_CACHEABLE L1C_CACHEABLE
|
||||
#define L1C_CACHEABLE_POS (0U)
|
||||
#define L1C_CACHEABLE_LEN (1U)
|
||||
#define L1C_CACHEABLE_MSK (((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS)
|
||||
#define L1C_CACHEABLE_UMSK (~(((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS))
|
||||
#define L1C_CNT_EN L1C_CNT_EN
|
||||
#define L1C_CNT_EN_POS (1U)
|
||||
#define L1C_CNT_EN_LEN (1U)
|
||||
#define L1C_CNT_EN_MSK (((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS)
|
||||
#define L1C_CNT_EN_UMSK (~(((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS))
|
||||
#define L1C_INVALID_EN L1C_INVALID_EN
|
||||
#define L1C_INVALID_EN_POS (2U)
|
||||
#define L1C_INVALID_EN_LEN (1U)
|
||||
#define L1C_INVALID_EN_MSK (((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS)
|
||||
#define L1C_INVALID_EN_UMSK (~(((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS))
|
||||
#define L1C_INVALID_DONE L1C_INVALID_DONE
|
||||
#define L1C_INVALID_DONE_POS (3U)
|
||||
#define L1C_INVALID_DONE_LEN (1U)
|
||||
#define L1C_INVALID_DONE_MSK (((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS)
|
||||
#define L1C_INVALID_DONE_UMSK (~(((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS))
|
||||
#define L1C_WAY_DIS L1C_WAY_DIS
|
||||
#define L1C_WAY_DIS_POS (8U)
|
||||
#define L1C_WAY_DIS_LEN (4U)
|
||||
#define L1C_WAY_DIS_MSK (((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS)
|
||||
#define L1C_WAY_DIS_UMSK (~(((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS))
|
||||
#define L1C_IROM_2T_ACCESS L1C_IROM_2T_ACCESS
|
||||
#define L1C_IROM_2T_ACCESS_POS (12U)
|
||||
#define L1C_IROM_2T_ACCESS_LEN (1U)
|
||||
#define L1C_IROM_2T_ACCESS_MSK (((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS)
|
||||
#define L1C_IROM_2T_ACCESS_UMSK (~(((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS))
|
||||
#define L1C_BYPASS L1C_BYPASS
|
||||
#define L1C_BYPASS_POS (14U)
|
||||
#define L1C_BYPASS_LEN (1U)
|
||||
#define L1C_BYPASS_MSK (((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS)
|
||||
#define L1C_BYPASS_UMSK (~(((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS))
|
||||
#define L1C_BMX_ERR_EN L1C_BMX_ERR_EN
|
||||
#define L1C_BMX_ERR_EN_POS (15U)
|
||||
#define L1C_BMX_ERR_EN_LEN (1U)
|
||||
#define L1C_BMX_ERR_EN_MSK (((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS)
|
||||
#define L1C_BMX_ERR_EN_UMSK (~(((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS))
|
||||
#define L1C_BMX_ARB_MODE L1C_BMX_ARB_MODE
|
||||
#define L1C_BMX_ARB_MODE_POS (16U)
|
||||
#define L1C_BMX_ARB_MODE_LEN (2U)
|
||||
#define L1C_BMX_ARB_MODE_MSK (((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS)
|
||||
#define L1C_BMX_ARB_MODE_UMSK (~(((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS))
|
||||
#define L1C_BMX_TIMEOUT_EN L1C_BMX_TIMEOUT_EN
|
||||
#define L1C_BMX_TIMEOUT_EN_POS (20U)
|
||||
#define L1C_BMX_TIMEOUT_EN_LEN (4U)
|
||||
#define L1C_BMX_TIMEOUT_EN_MSK (((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS)
|
||||
#define L1C_BMX_TIMEOUT_EN_UMSK (~(((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS))
|
||||
#define L1C_BMX_BUSY_OPTION_DIS L1C_BMX_BUSY_OPTION_DIS
|
||||
#define L1C_BMX_BUSY_OPTION_DIS_POS (24U)
|
||||
#define L1C_BMX_BUSY_OPTION_DIS_LEN (1U)
|
||||
#define L1C_BMX_BUSY_OPTION_DIS_MSK (((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS)
|
||||
#define L1C_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS))
|
||||
#define L1C_EARLY_RESP_DIS L1C_EARLY_RESP_DIS
|
||||
#define L1C_EARLY_RESP_DIS_POS (25U)
|
||||
#define L1C_EARLY_RESP_DIS_LEN (1U)
|
||||
#define L1C_EARLY_RESP_DIS_MSK (((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS)
|
||||
#define L1C_EARLY_RESP_DIS_UMSK (~(((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS))
|
||||
#define L1C_WRAP_DIS L1C_WRAP_DIS
|
||||
#define L1C_WRAP_DIS_POS (26U)
|
||||
#define L1C_WRAP_DIS_LEN (1U)
|
||||
#define L1C_WRAP_DIS_MSK (((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS)
|
||||
#define L1C_WRAP_DIS_UMSK (~(((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS))
|
||||
|
||||
/* 0x4 : hit_cnt_lsb */
|
||||
#define L1C_HIT_CNT_LSB_OFFSET (0x4)
|
||||
#define L1C_HIT_CNT_LSB L1C_HIT_CNT_LSB
|
||||
#define L1C_HIT_CNT_LSB_POS (0U)
|
||||
#define L1C_HIT_CNT_LSB_LEN (32U)
|
||||
#define L1C_HIT_CNT_LSB_MSK (((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS)
|
||||
#define L1C_HIT_CNT_LSB_UMSK (~(((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS))
|
||||
|
||||
/* 0x8 : hit_cnt_msb */
|
||||
#define L1C_HIT_CNT_MSB_OFFSET (0x8)
|
||||
#define L1C_HIT_CNT_MSB L1C_HIT_CNT_MSB
|
||||
#define L1C_HIT_CNT_MSB_POS (0U)
|
||||
#define L1C_HIT_CNT_MSB_LEN (32U)
|
||||
#define L1C_HIT_CNT_MSB_MSK (((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS)
|
||||
#define L1C_HIT_CNT_MSB_UMSK (~(((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS))
|
||||
|
||||
/* 0xC : miss_cnt */
|
||||
#define L1C_MISS_CNT_OFFSET (0xC)
|
||||
#define L1C_MISS_CNT L1C_MISS_CNT
|
||||
#define L1C_MISS_CNT_POS (0U)
|
||||
#define L1C_MISS_CNT_LEN (32U)
|
||||
#define L1C_MISS_CNT_MSK (((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS)
|
||||
#define L1C_MISS_CNT_UMSK (~(((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS))
|
||||
|
||||
/* 0x10 : l1c_range */
|
||||
#define L1C_RANGE_OFFSET (0x10)
|
||||
|
||||
/* 0x200 : l1c_bmx_err_addr_en */
|
||||
#define L1C_BMX_ERR_ADDR_EN_OFFSET (0x200)
|
||||
#define L1C_BMX_ERR_ADDR_DIS L1C_BMX_ERR_ADDR_DIS
|
||||
#define L1C_BMX_ERR_ADDR_DIS_POS (0U)
|
||||
#define L1C_BMX_ERR_ADDR_DIS_LEN (1U)
|
||||
#define L1C_BMX_ERR_ADDR_DIS_MSK (((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS)
|
||||
#define L1C_BMX_ERR_ADDR_DIS_UMSK (~(((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS))
|
||||
#define L1C_BMX_ERR_DEC L1C_BMX_ERR_DEC
|
||||
#define L1C_BMX_ERR_DEC_POS (4U)
|
||||
#define L1C_BMX_ERR_DEC_LEN (1U)
|
||||
#define L1C_BMX_ERR_DEC_MSK (((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS)
|
||||
#define L1C_BMX_ERR_DEC_UMSK (~(((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS))
|
||||
#define L1C_BMX_ERR_TZ L1C_BMX_ERR_TZ
|
||||
#define L1C_BMX_ERR_TZ_POS (5U)
|
||||
#define L1C_BMX_ERR_TZ_LEN (1U)
|
||||
#define L1C_BMX_ERR_TZ_MSK (((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS)
|
||||
#define L1C_BMX_ERR_TZ_UMSK (~(((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS))
|
||||
#define L1C_HSEL_OPTION L1C_HSEL_OPTION
|
||||
#define L1C_HSEL_OPTION_POS (16U)
|
||||
#define L1C_HSEL_OPTION_LEN (4U)
|
||||
#define L1C_HSEL_OPTION_MSK (((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS)
|
||||
#define L1C_HSEL_OPTION_UMSK (~(((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS))
|
||||
|
||||
/* 0x204 : l1c_bmx_err_addr */
|
||||
#define L1C_BMX_ERR_ADDR_OFFSET (0x204)
|
||||
#define L1C_BMX_ERR_ADDR L1C_BMX_ERR_ADDR
|
||||
#define L1C_BMX_ERR_ADDR_POS (0U)
|
||||
#define L1C_BMX_ERR_ADDR_LEN (32U)
|
||||
#define L1C_BMX_ERR_ADDR_MSK (((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS)
|
||||
#define L1C_BMX_ERR_ADDR_UMSK (~(((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS))
|
||||
|
||||
/* 0x208 : irom1_misr_dataout_0 */
|
||||
#define L1C_IROM1_MISR_DATAOUT_0_OFFSET (0x208)
|
||||
#define L1C_IROM1_MISR_DATAOUT_0 L1C_IROM1_MISR_DATAOUT_0
|
||||
#define L1C_IROM1_MISR_DATAOUT_0_POS (0U)
|
||||
#define L1C_IROM1_MISR_DATAOUT_0_LEN (32U)
|
||||
#define L1C_IROM1_MISR_DATAOUT_0_MSK (((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS)
|
||||
#define L1C_IROM1_MISR_DATAOUT_0_UMSK (~(((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS))
|
||||
|
||||
/* 0x20C : irom1_misr_dataout_1 */
|
||||
#define L1C_IROM1_MISR_DATAOUT_1_OFFSET (0x20C)
|
||||
|
||||
/* 0x210 : cpu_clk_gate */
|
||||
#define L1C_CPU_CLK_GATE_OFFSET (0x210)
|
||||
#define L1C_FORCE_E21_CLOCK_ON_0 L1C_FORCE_E21_CLOCK_ON_0
|
||||
#define L1C_FORCE_E21_CLOCK_ON_0_POS (0U)
|
||||
#define L1C_FORCE_E21_CLOCK_ON_0_LEN (1U)
|
||||
#define L1C_FORCE_E21_CLOCK_ON_0_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS)
|
||||
#define L1C_FORCE_E21_CLOCK_ON_0_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS))
|
||||
#define L1C_FORCE_E21_CLOCK_ON_1 L1C_FORCE_E21_CLOCK_ON_1
|
||||
#define L1C_FORCE_E21_CLOCK_ON_1_POS (1U)
|
||||
#define L1C_FORCE_E21_CLOCK_ON_1_LEN (1U)
|
||||
#define L1C_FORCE_E21_CLOCK_ON_1_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS)
|
||||
#define L1C_FORCE_E21_CLOCK_ON_1_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS))
|
||||
#define L1C_FORCE_E21_CLOCK_ON_2 L1C_FORCE_E21_CLOCK_ON_2
|
||||
#define L1C_FORCE_E21_CLOCK_ON_2_POS (2U)
|
||||
#define L1C_FORCE_E21_CLOCK_ON_2_LEN (1U)
|
||||
#define L1C_FORCE_E21_CLOCK_ON_2_MSK (((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS)
|
||||
#define L1C_FORCE_E21_CLOCK_ON_2_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS))
|
||||
|
||||
struct l1c_reg {
|
||||
/* 0x0 : l1c_config */
|
||||
union {
|
||||
struct
|
||||
{
|
||||
uint32_t l1c_cacheable : 1; /* [ 0], r/w, 0x0 */
|
||||
uint32_t l1c_cnt_en : 1; /* [ 1], r/w, 0x0 */
|
||||
uint32_t l1c_invalid_en : 1; /* [ 2], r/w, 0x0 */
|
||||
uint32_t l1c_invalid_done : 1; /* [ 3], r, 0x0 */
|
||||
uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */
|
||||
uint32_t l1c_way_dis : 4; /* [11: 8], r/w, 0xf */
|
||||
uint32_t irom_2t_access : 1; /* [ 12], r/w, 0x0 */
|
||||
uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */
|
||||
uint32_t l1c_bypass : 1; /* [ 14], r/w, 0x0 */
|
||||
uint32_t l1c_bmx_err_en : 1; /* [ 15], r/w, 0x0 */
|
||||
uint32_t l1c_bmx_arb_mode : 2; /* [17:16], r/w, 0x0 */
|
||||
uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */
|
||||
uint32_t l1c_bmx_timeout_en : 4; /* [23:20], r/w, 0x0 */
|
||||
uint32_t l1c_bmx_busy_option_dis : 1; /* [ 24], r/w, 0x0 */
|
||||
uint32_t early_resp_dis : 1; /* [ 25], r/w, 0x1 */
|
||||
uint32_t wrap_dis : 1; /* [ 26], r/w, 0x1 */
|
||||
uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */
|
||||
} BF;
|
||||
uint32_t WORD;
|
||||
} l1c_config;
|
||||
|
||||
/* 0x4 : hit_cnt_lsb */
|
||||
union {
|
||||
struct
|
||||
{
|
||||
uint32_t hit_cnt_lsb : 32; /* [31: 0], r, 0x0 */
|
||||
} BF;
|
||||
uint32_t WORD;
|
||||
} hit_cnt_lsb;
|
||||
|
||||
/* 0x8 : hit_cnt_msb */
|
||||
union {
|
||||
struct
|
||||
{
|
||||
uint32_t hit_cnt_msb : 32; /* [31: 0], r, 0x0 */
|
||||
} BF;
|
||||
uint32_t WORD;
|
||||
} hit_cnt_msb;
|
||||
|
||||
/* 0xC : miss_cnt */
|
||||
union {
|
||||
struct
|
||||
{
|
||||
uint32_t miss_cnt : 32; /* [31: 0], r, 0x0 */
|
||||
} BF;
|
||||
uint32_t WORD;
|
||||
} miss_cnt;
|
||||
|
||||
/* 0x10 : l1c_range */
|
||||
union {
|
||||
struct
|
||||
{
|
||||
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
|
||||
} BF;
|
||||
uint32_t WORD;
|
||||
} l1c_range;
|
||||
|
||||
/* 0x14 reserved */
|
||||
uint8_t RESERVED0x14[492];
|
||||
|
||||
/* 0x200 : l1c_bmx_err_addr_en */
|
||||
union {
|
||||
struct
|
||||
{
|
||||
uint32_t l1c_bmx_err_addr_dis : 1; /* [ 0], r/w, 0x0 */
|
||||
uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */
|
||||
uint32_t l1c_bmx_err_dec : 1; /* [ 4], r, 0x0 */
|
||||
uint32_t l1c_bmx_err_tz : 1; /* [ 5], r, 0x0 */
|
||||
uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */
|
||||
uint32_t l1c_hsel_option : 4; /* [19:16], r/w, 0x0 */
|
||||
uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */
|
||||
} BF;
|
||||
uint32_t WORD;
|
||||
} l1c_bmx_err_addr_en;
|
||||
|
||||
/* 0x204 : l1c_bmx_err_addr */
|
||||
union {
|
||||
struct
|
||||
{
|
||||
uint32_t l1c_bmx_err_addr : 32; /* [31: 0], r, 0x0 */
|
||||
} BF;
|
||||
uint32_t WORD;
|
||||
} l1c_bmx_err_addr;
|
||||
|
||||
/* 0x208 : irom1_misr_dataout_0 */
|
||||
union {
|
||||
struct
|
||||
{
|
||||
uint32_t irom1_misr_dataout_0 : 32; /* [31: 0], r, 0x0 */
|
||||
} BF;
|
||||
uint32_t WORD;
|
||||
} irom1_misr_dataout_0;
|
||||
|
||||
/* 0x20C : irom1_misr_dataout_1 */
|
||||
union {
|
||||
struct
|
||||
{
|
||||
uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */
|
||||
} BF;
|
||||
uint32_t WORD;
|
||||
} irom1_misr_dataout_1;
|
||||
|
||||
/* 0x210 : cpu_clk_gate */
|
||||
union {
|
||||
struct
|
||||
{
|
||||
uint32_t force_e21_clock_on_0 : 1; /* [ 0], r/w, 0x0 */
|
||||
uint32_t force_e21_clock_on_1 : 1; /* [ 1], r/w, 0x0 */
|
||||
uint32_t force_e21_clock_on_2 : 1; /* [ 2], r/w, 0x0 */
|
||||
uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */
|
||||
} BF;
|
||||
uint32_t WORD;
|
||||
} cpu_clk_gate;
|
||||
};
|
||||
|
||||
typedef volatile struct l1c_reg l1c_reg_t;
|
||||
|
||||
#endif /* __L1C_REG_H__ */
|
||||
551
drivers/soc/bl602/bl602_std/src/bl602_aon.c
Normal file
551
drivers/soc/bl602/bl602_std/src/bl602_aon.c
Normal file
@ -0,0 +1,551 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file bl602_aon.c
|
||||
* @version V1.0
|
||||
* @date
|
||||
* @brief This file is the standard driver c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "bl602_aon.h"
|
||||
|
||||
/** @addtogroup BL602_Peripheral_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup AON
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup AON_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define AON_CLK_SET_DUMMY_WAIT \
|
||||
{ \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
}
|
||||
|
||||
/*@} end of group AON_Private_Macros */
|
||||
|
||||
/** @defgroup AON_Private_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group AON_Private_Types */
|
||||
|
||||
/** @defgroup AON_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group AON_Private_Variables */
|
||||
|
||||
/** @defgroup AON_Global_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group AON_Global_Variables */
|
||||
|
||||
/** @defgroup AON_Private_Fun_Declaration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group AON_Private_Fun_Declaration */
|
||||
|
||||
/** @defgroup AON_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group AON_Private_Functions */
|
||||
|
||||
/** @defgroup AON_Public_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power on MXX band gap
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* Power up RF for PLL to work */
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
|
||||
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
|
||||
|
||||
BL602_Delay_US(55);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power off MXX band gap
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* Power OFF */
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
|
||||
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power on XTAL
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
uint32_t timeOut = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
|
||||
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
|
||||
|
||||
/* Polling for ready */
|
||||
do {
|
||||
BL602_Delay_US(10);
|
||||
timeOut++;
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
|
||||
} while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120);
|
||||
|
||||
if (timeOut >= 120) {
|
||||
return TIMEOUT;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Set XTAL cap code
|
||||
*
|
||||
* @param capIn: Cap code in
|
||||
* @param capOut: Cap code out
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut);
|
||||
BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
|
||||
|
||||
BL602_Delay_US(100);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Get XTAL cap code
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return Cap code
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
|
||||
|
||||
return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power off XTAL
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
|
||||
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power on bandgap system
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* power up RF for PLL to work */
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
|
||||
BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
|
||||
|
||||
BL602_Delay_US(55);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power off bandgap system
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* power up RF for PLL to work */
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
|
||||
BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
|
||||
|
||||
BL602_Delay_US(55);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power on LDO11
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
|
||||
BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
|
||||
|
||||
BL602_Delay_US(55);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power off LDO11
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
|
||||
BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
|
||||
|
||||
BL602_Delay_US(55);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power on LDO15_RF
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* ldo15rf power on */
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
|
||||
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
|
||||
|
||||
BL602_Delay_US(90);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power off LDO15_RF
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* ldo15rf power off */
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
|
||||
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief power on source follow regular
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* power on sfreg */
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
|
||||
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
|
||||
|
||||
BL602_Delay_US(10);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief power off source follow regular
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* power off sfreg */
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
|
||||
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power off the power can be shut down in PDS0
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* power off sfreg */
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
|
||||
BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
|
||||
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
|
||||
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
|
||||
|
||||
/* gating Clock */
|
||||
tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
|
||||
tmpVal = tmpVal & (~(1 << 6));
|
||||
tmpVal = tmpVal & (~(1 << 7));
|
||||
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power on the power powered down in PDS0
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
|
||||
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
|
||||
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
|
||||
|
||||
BL602_Delay_US(20);
|
||||
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
|
||||
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
|
||||
|
||||
BL602_Delay_US(60);
|
||||
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
|
||||
BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
|
||||
|
||||
BL602_Delay_US(20);
|
||||
|
||||
/* power on wb */
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
|
||||
BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
|
||||
|
||||
/* ungating Clock */
|
||||
tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
|
||||
tmpVal = tmpVal | ((1 << 6));
|
||||
tmpVal = tmpVal | ((1 << 7));
|
||||
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power on the power powered down in PDS0
|
||||
*
|
||||
* @param delay: None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
CHECK_PARAM((delay <= 0x3));
|
||||
|
||||
/* config ldo11soc_sstart_delay_aon */
|
||||
tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO11SOC_SSTART_DELAY_AON, delay);
|
||||
BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*@} end of group AON_Public_Functions */
|
||||
|
||||
/*@} end of group AON */
|
||||
|
||||
/*@} end of group BL602_Peripheral_Driver */
|
||||
162
drivers/soc/bl602/bl602_std/src/bl602_common.c
Normal file
162
drivers/soc/bl602/bl602_std/src/bl602_common.c
Normal file
@ -0,0 +1,162 @@
|
||||
#include "l1c_reg.h"
|
||||
#include "bl602_common.h"
|
||||
|
||||
/** @addtogroup BL602_Periph_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief delay us
|
||||
*
|
||||
* @param[in] core: systemcoreclock
|
||||
*
|
||||
* @param[in] cnt: delay cnt us
|
||||
*
|
||||
* @return none
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
#ifdef ARCH_ARM
|
||||
#ifndef __GNUC__
|
||||
__WEAK
|
||||
__ASM void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt)
|
||||
{
|
||||
lsrs r0, #0x10 muls r0, r1, r0 mov r2, r0 lsrs r2, #0x04 lsrs r2, #0x03 cmp r2, #0x01 beq end cmp r2, #0x00 beq end loop mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 subs r2, r2, #0x01 cmp r2, #0x00 bne loop end bx lr
|
||||
}
|
||||
#else
|
||||
__WEAK
|
||||
void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt)
|
||||
{
|
||||
__asm__ __volatile__(
|
||||
"lsr r0,#0x10\n\t"
|
||||
"mul r0,r1,r0\n\t"
|
||||
"mov r2,r0\n\t"
|
||||
"lsr r2,#0x04\n\t"
|
||||
"lsr r2,#0x03\n\t"
|
||||
"cmp r2,#0x01\n\t"
|
||||
"beq end\n\t"
|
||||
"cmp r2,#0x00\n\t"
|
||||
"beq end\n"
|
||||
"loop :"
|
||||
"mov r0,r0\n\t"
|
||||
"mov r0,r0\n\t"
|
||||
"mov r0,r0\n\t"
|
||||
"mov r0,r0\n\t"
|
||||
"mov r0,r0\n\t"
|
||||
"sub r2,r2,#0x01\n\t"
|
||||
"cmp r2,#0x00\n\t"
|
||||
"bne loop\n"
|
||||
"end :"
|
||||
"mov r0,r0\n\t");
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
#ifdef ARCH_RISCV
|
||||
__WEAK
|
||||
void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt)
|
||||
{
|
||||
uint32_t codeAddress = 0;
|
||||
uint32_t divVal = 40;
|
||||
|
||||
codeAddress = (uint32_t)&ASM_Delay_Us;
|
||||
|
||||
/* 1M=100K*10, so multiple is 10 */
|
||||
/* loop function take 4 instructions, so instructionNum is 4 */
|
||||
/* if codeAddress locate at IROM space and irom_2t_access is 1, then irom2TAccess=2, else irom2TAccess=1 */
|
||||
/* divVal = multiple*instructionNum*irom2TAccess */
|
||||
if (((codeAddress & (0xF << 24)) >> 24) == 0x01) {
|
||||
/* IROM space */
|
||||
if (BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE, L1C_CONFIG), L1C_IROM_2T_ACCESS)) {
|
||||
/* instruction 2T */
|
||||
divVal = 80;
|
||||
}
|
||||
}
|
||||
|
||||
__asm__ __volatile__(
|
||||
".align 4\n\t"
|
||||
"lw a4,%1\n\t"
|
||||
"lui a5,0x18\n\t"
|
||||
"addi a5,a5,1696\n\t"
|
||||
"divu a5,a4,a5\n\t"
|
||||
"sw a5,%1\n\t"
|
||||
"lw a4,%1\n\t"
|
||||
"lw a5,%0\n\t"
|
||||
"mul a5,a4,a5\n\t"
|
||||
"sw a5,%1\n\t"
|
||||
"lw a4,%1\n\t"
|
||||
"lw a5,%2\n\t"
|
||||
"divu a5,a4,a5\n\t"
|
||||
"sw a5,%1\n\t"
|
||||
"lw a5,%1\n\t"
|
||||
"li a4,0x1\n\t"
|
||||
"beq a5,zero,end\n\t"
|
||||
"beq a5,a4,end\n\t"
|
||||
"nop\n\t"
|
||||
"nop\n\t"
|
||||
".align 4\n\t"
|
||||
"loop :\n"
|
||||
"addi a4,a5,-1\n\t"
|
||||
"mv a5,a4\n\t"
|
||||
"bnez a5,loop\n\t"
|
||||
"nop\n\t"
|
||||
"end :\n\t"
|
||||
"nop\n"
|
||||
: /* output */
|
||||
: "m"(cnt), "m"(core), "m"(divVal) /* input */
|
||||
: "t1", "a4", "a5" /* destruct description */
|
||||
);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief delay us
|
||||
*
|
||||
* @param[in] cnt: delay cnt us
|
||||
*
|
||||
* @return none
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
void ATTR_TCM_SECTION BL602_Delay_US(uint32_t cnt)
|
||||
{
|
||||
ASM_Delay_Us(SystemCoreClockGet(), cnt);
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief delay ms
|
||||
*
|
||||
* @param[in] cnt: delay cnt ms
|
||||
*
|
||||
* @return none
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
void ATTR_TCM_SECTION BL602_Delay_MS(uint32_t cnt)
|
||||
{
|
||||
uint32_t i = 0;
|
||||
uint32_t count = 0;
|
||||
|
||||
if (cnt >= 1024) {
|
||||
/* delay (n*1024) ms */
|
||||
count = 1024;
|
||||
|
||||
for (i = 0; i < (cnt / 1024); i++) {
|
||||
BL602_Delay_US(1024 * 1000);
|
||||
}
|
||||
}
|
||||
|
||||
if (cnt & 0x3FF) {
|
||||
/* delay (1-1023)ms */
|
||||
count = cnt & 0x3FF;
|
||||
BL602_Delay_US(count * 1000);
|
||||
}
|
||||
|
||||
//BL602_Delay_US((count<<10)-(count<<4)-(count<<3));
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@} end of group DRIVER_Public_Functions */
|
||||
|
||||
/*@} end of group DRIVER_COMMON */
|
||||
|
||||
/*@} end of group BL602_Periph_Driver */
|
||||
1872
drivers/soc/bl602/bl602_std/src/bl602_ef_ctrl.c
Normal file
1872
drivers/soc/bl602/bl602_std/src/bl602_ef_ctrl.c
Normal file
File diff suppressed because it is too large
Load Diff
428
drivers/soc/bl602/bl602_std/src/bl602_l1c.c
Normal file
428
drivers/soc/bl602/bl602_std/src/bl602_l1c.c
Normal file
@ -0,0 +1,428 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file bl602_l1c.c
|
||||
* @version V1.0
|
||||
* @date
|
||||
* @brief This file is the standard driver c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "bl602_l1c.h"
|
||||
#include "bl602_common.h"
|
||||
|
||||
/** @addtogroup BL602_Peripheral_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup L1C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup L1C_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group L1C_Private_Macros */
|
||||
|
||||
/** @defgroup L1C_Private_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group L1C_Private_Types */
|
||||
|
||||
/** @defgroup L1C_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
static intCallback_Type *l1cBmxErrIntCbfArra[L1C_BMX_ERR_INT_ALL] = { NULL };
|
||||
static intCallback_Type *l1cBmxToIntCbfArra[L1C_BMX_TO_INT_ALL] = { NULL };
|
||||
|
||||
/*@} end of group L1C_Private_Variables */
|
||||
|
||||
/** @defgroup L1C_Global_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group L1C_Global_Variables */
|
||||
|
||||
/** @defgroup L1C_Private_Fun_Declaration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group L1C_Private_Fun_Declaration */
|
||||
|
||||
/** @defgroup L1C_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group L1C_Private_Functions */
|
||||
|
||||
/** @defgroup L1C_Public_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief wrap set
|
||||
*
|
||||
* @param wrap: ENABLE or DISABLE
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
uint8_t cacheEn = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
|
||||
cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE);
|
||||
|
||||
if (cacheEn != 0) {
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
|
||||
BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
|
||||
}
|
||||
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
|
||||
|
||||
if (wrap == ENABLE) {
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WRAP_DIS);
|
||||
} else {
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WRAP_DIS);
|
||||
}
|
||||
|
||||
BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
|
||||
|
||||
if (cacheEn != 0) {
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
|
||||
BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief cache way disable set
|
||||
*
|
||||
* @param disableVal: cache way disable value
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
uint8_t cacheEn = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
|
||||
cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE);
|
||||
|
||||
if (cacheEn != 0) {
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
|
||||
BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
|
||||
}
|
||||
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS, disableVal);
|
||||
BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
|
||||
|
||||
if (cacheEn != 0) {
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
|
||||
BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Set for ROM 2T access if CPU freq >120MHz
|
||||
*
|
||||
* @param enable: ENABLE or DISABLE
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
|
||||
|
||||
if (enable) {
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS);
|
||||
} else {
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS);
|
||||
}
|
||||
|
||||
BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief L1C BMX init
|
||||
*
|
||||
* @param l1cBmxCfg: L1C BMX config
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
CHECK_PARAM((l1cBmxCfg->timeoutEn) <= 0xF);
|
||||
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_TIMEOUT_EN, l1cBmxCfg->timeoutEn);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_EN, l1cBmxCfg->errEn);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ARB_MODE, l1cBmxCfg->arbMod);
|
||||
BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
|
||||
|
||||
#ifndef BFLB_USE_HAL_DRIVER
|
||||
Interrupt_Handler_Register(L1C_BMX_ERR_IRQn, L1C_BMX_ERR_IRQHandler);
|
||||
Interrupt_Handler_Register(L1C_BMX_TO_IRQn, L1C_BMX_TO_IRQHandler);
|
||||
#endif
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief L1C BMX address monitor enable
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS);
|
||||
BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief L1C BMX address monitor disable
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS);
|
||||
BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief L1C BMX bus error response enable
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type L1C_BMX_BusErrResponse_Enable(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_EN);
|
||||
BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief L1C BMX bus error response disable
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type L1C_BMX_BusErrResponse_Disable(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_EN);
|
||||
BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Get L1C BMX error status
|
||||
*
|
||||
* @param errType: L1C BMX error status type
|
||||
*
|
||||
* @return SET or RESET
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
CHECK_PARAM(IS_L1C_BMX_BUS_ERR_TYPE(errType));
|
||||
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
|
||||
|
||||
if (errType == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) {
|
||||
return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_TZ) ? SET : RESET;
|
||||
} else {
|
||||
return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_DEC) ? SET : RESET;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Get L1C BMX error address
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return NP L1C BMX error address
|
||||
*
|
||||
*******************************************************************************/
|
||||
uint32_t L1C_BMX_Get_Err_Addr(void)
|
||||
{
|
||||
return BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR);
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief L1C BMX error interrupt callback install
|
||||
*
|
||||
* @param intType: L1C BMX error interrupt type
|
||||
* @param cbFun: callback
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun)
|
||||
{
|
||||
CHECK_PARAM(IS_L1C_BMX_ERR_INT_TYPE(intType));
|
||||
|
||||
l1cBmxErrIntCbfArra[intType] = cbFun;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief L1C BMX ERR interrupt IRQ handler
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_HAL_DRIVER
|
||||
void L1C_BMX_ERR_IRQHandler(void)
|
||||
{
|
||||
L1C_BMX_ERR_INT_Type intType;
|
||||
|
||||
for (intType = L1C_BMX_ERR_INT_ERR; intType < L1C_BMX_ERR_INT_ALL; intType++) {
|
||||
if (l1cBmxErrIntCbfArra[intType] != NULL) {
|
||||
l1cBmxErrIntCbfArra[intType]();
|
||||
}
|
||||
}
|
||||
|
||||
while (1) {
|
||||
MSG("L1C_BMX_ERR_IRQHandler\r\n");
|
||||
BL602_Delay_MS(1000);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief L1C BMX timeout interrupt callback install
|
||||
*
|
||||
* @param intType: L1C BMX timeout interrupt type
|
||||
* @param cbFun: callback
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType, intCallback_Type *cbFun)
|
||||
{
|
||||
CHECK_PARAM(IS_L1C_BMX_TO_INT_TYPE(intType));
|
||||
|
||||
l1cBmxToIntCbfArra[intType] = cbFun;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief L1C BMX Time Out interrupt IRQ handler
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_HAL_DRIVER
|
||||
void L1C_BMX_TO_IRQHandler(void)
|
||||
{
|
||||
L1C_BMX_TO_INT_Type intType;
|
||||
|
||||
for (intType = L1C_BMX_TO_INT_TIMEOUT; intType < L1C_BMX_TO_INT_ALL; intType++) {
|
||||
if (l1cBmxToIntCbfArra[intType] != NULL) {
|
||||
l1cBmxToIntCbfArra[intType]();
|
||||
}
|
||||
}
|
||||
|
||||
while (1) {
|
||||
MSG("L1C_BMX_TO_IRQHandler\r\n");
|
||||
BL602_Delay_MS(1000);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@} end of group L1C_Public_Functions */
|
||||
|
||||
/*@} end of group L1C */
|
||||
|
||||
/*@} end of group BL602_Peripheral_Driver */
|
||||
841
drivers/soc/bl602/bl602_std/src/bl602_pds.c
Normal file
841
drivers/soc/bl602/bl602_std/src/bl602_pds.c
Normal file
@ -0,0 +1,841 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file bl602_pds.c
|
||||
* @version V1.0
|
||||
* @date
|
||||
* @brief This file is the standard driver c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "bl602.h"
|
||||
#include "bl602_pds.h"
|
||||
|
||||
/** @addtogroup BL602_Peripheral_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup PDS
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup PDS_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group PDS_Private_Macros */
|
||||
|
||||
/** @defgroup PDS_Private_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group PDS_Private_Types */
|
||||
|
||||
/** @defgroup PDS_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
static intCallback_Type *pdsIntCbfArra[4][1] = { { NULL }, { NULL }, { NULL }, { NULL } };
|
||||
|
||||
/*@} end of group PDS_Private_Variables */
|
||||
|
||||
/** @defgroup PDS_Global_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group PDS_Global_Variables */
|
||||
|
||||
/** @defgroup PDS_Private_Fun_Declaration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group PDS_Private_Fun_Declaration */
|
||||
|
||||
/** @defgroup PDS_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group PDS_Private_Functions */
|
||||
|
||||
/** @defgroup PDS_Public_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief PDS software reset
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION PDS_Reset(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = *(uint32_t *)0x40000014;
|
||||
tmpVal = tmpVal | (1 << 14);
|
||||
*(uint32_t *)0x40000014 = tmpVal;
|
||||
|
||||
tmpVal = *(uint32_t *)0x40000014;
|
||||
tmpVal = tmpVal & ~(1 << 14);
|
||||
*(uint32_t *)0x40000014 = tmpVal;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Enable power down sleep
|
||||
*
|
||||
* @param cfg: power down sleep configuration 1
|
||||
* @param cfg4: power down sleep configuration 2
|
||||
* @param pdsSleepCnt: power down sleep count cycle
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
// #ifndef BFLB_USE_ROM_DRIVER
|
||||
// __WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* PDS sleep time 0 <=> sleep forever */
|
||||
/* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */
|
||||
/* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */
|
||||
if (!pdsSleepCnt) {
|
||||
cfg->sleepForever = 1;
|
||||
} else if ((pdsSleepCnt) && (pdsSleepCnt <= PDS_WARMUP_LATENCY_CNT)) {
|
||||
return ERROR;
|
||||
} else {
|
||||
BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_LATENCY_CNT);
|
||||
}
|
||||
|
||||
/* PDS_CTL4 config */
|
||||
BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4);
|
||||
|
||||
/* PDS_CTL config */
|
||||
if (cfg->pdsStart) {
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
|
||||
BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
|
||||
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
|
||||
BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
|
||||
|
||||
BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg & ~(1 << 0)));
|
||||
BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0)));
|
||||
} else {
|
||||
BL_WR_REG(PDS_BASE, PDS_CTL, *(uint32_t *)cfg);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
// #endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief power down sleep force configure
|
||||
*
|
||||
* @param cfg2: power down sleep force configuration 1
|
||||
* @param cfg3: power down sleep force configuration 2
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3)
|
||||
{
|
||||
/* PDS_CTL2 config */
|
||||
BL_WR_REG(PDS_BASE, PDS_CTL2, *(uint32_t *)cfg2);
|
||||
|
||||
/* PDS_CTL3 config */
|
||||
BL_WR_REG(PDS_BASE, PDS_CTL3, *(uint32_t *)cfg3);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief power down sleep ram configure
|
||||
*
|
||||
* @param ramCfg: power down sleep force ram configuration
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
if (NULL == ramCfg) {
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
tmpVal = BL_RD_REG(GLB_BASE, GLB_MBIST_CTL);
|
||||
/* enter bist mode (make ram idle/slp) */
|
||||
//tmpVal = tmpVal&~0x1F;
|
||||
//tmpVal = tmpVal|0x18;
|
||||
/* enter bist mode (make ram ret) */
|
||||
tmpVal = tmpVal | (0x1 << 3);
|
||||
BL_WR_REG(GLB_BASE, GLB_MBIST_CTL, tmpVal);
|
||||
|
||||
/* PDS_RAM1 config */
|
||||
BL_WR_REG(PDS_BASE, PDS_RAM1, *(uint32_t *)ramCfg);
|
||||
|
||||
tmpVal = BL_RD_REG(GLB_BASE, GLB_MBIST_CTL);
|
||||
/* exit bist mode (make ram idle/slp) */
|
||||
//tmpVal = tmpVal&~0x1F;
|
||||
/* exit bist mode (make ram ret) */
|
||||
tmpVal = tmpVal & ~(0x1 << 3);
|
||||
BL_WR_REG(GLB_BASE, GLB_MBIST_CTL, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief power down sleep force configure
|
||||
*
|
||||
* @param defaultLvCfg: power down sleep default level configuration
|
||||
* @param ramCfg: ram configuration
|
||||
* @param pdsSleepCnt: power down sleep time count
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
// #ifndef BFLB_USE_ROM_DRIVER
|
||||
// __WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, PDS_RAM_CFG_Type *ramCfg, uint32_t pdsSleepCnt)
|
||||
{
|
||||
/* RAM config need fix after ECO */
|
||||
PDS_RAM_Config(ramCfg);
|
||||
PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2), (PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3));
|
||||
PDS_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl), (PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4), pdsSleepCnt);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
// #endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief power down sleep int mask
|
||||
*
|
||||
* @param intType: PDS int type
|
||||
* @param intMask: MASK or UNMASK
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
|
||||
|
||||
if (intMask != UNMASK) {
|
||||
tmpVal = tmpVal | (1 << (intType + PDS_INT_MASK_BIT_OFFSET));
|
||||
} else {
|
||||
tmpVal = tmpVal & ~(1 << (intType + PDS_INT_MASK_BIT_OFFSET));
|
||||
}
|
||||
|
||||
BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief get power down sleep int status
|
||||
*
|
||||
* @param intType: PDS int type
|
||||
*
|
||||
* @return SET or RESET
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType)
|
||||
{
|
||||
return (BL_RD_REG(PDS_BASE, PDS_INT) & (1 << intType)) ? SET : RESET;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief clear power down sleep int status
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type PDS_IntClear(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
|
||||
BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
|
||||
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
|
||||
BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
|
||||
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
|
||||
BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief get power down sleep PLL status
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return PDS PLL status
|
||||
*
|
||||
*******************************************************************************/
|
||||
PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void)
|
||||
{
|
||||
return (PDS_PLL_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_PLL_STATE);
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief get power down sleep RF status
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return PDS RF status
|
||||
*
|
||||
*******************************************************************************/
|
||||
PDS_RF_STS_Type PDS_Get_PdsRfStstus(void)
|
||||
{
|
||||
return (PDS_RF_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_RF_STATE);
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief get power down sleep status
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return PDS status
|
||||
*
|
||||
*******************************************************************************/
|
||||
PDS_STS_Type PDS_Get_PdsStstus(void)
|
||||
{
|
||||
return (PDS_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_STATE);
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief PDS wakeup IRQHandler install
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void)
|
||||
{
|
||||
#ifndef BFLB_USE_HAL_DRIVER
|
||||
Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQHandler);
|
||||
#endif
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Install PDS interrupt callback function
|
||||
*
|
||||
* @param intType: PDS int type
|
||||
* @param cbFun: cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun)
|
||||
{
|
||||
pdsIntCbfArra[intType][0] = cbFun;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Trim RC32M
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void)
|
||||
{
|
||||
Efuse_Ana_RC32M_Trim_Type trim;
|
||||
int32_t tmpVal = 0;
|
||||
|
||||
EF_Ctrl_Read_RC32M_Trim(&trim);
|
||||
|
||||
if (trim.trimRc32mExtCodeEn) {
|
||||
if (trim.trimRc32mCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32mCodeFrExt, 8)) {
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_RC32M_CTRL0);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_RC32M_CODE_FR_EXT, trim.trimRc32mCodeFrExt);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, PDS_RC32M_EXT_CODE_EN);
|
||||
BL_WR_REG(PDS_BASE, PDS_RC32M_CTRL0, tmpVal);
|
||||
BL602_Delay_US(2);
|
||||
return SUCCESS;
|
||||
}
|
||||
}
|
||||
|
||||
return ERROR;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Select RC32M as PLL ref source
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_RC32M_As_PLL_Ref(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_REFCLK_SEL);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL);
|
||||
BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Select XTAL as PLL ref source
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_XTAL_As_PLL_Ref(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_REFCLK_SEL);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL);
|
||||
BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power on PLL
|
||||
*
|
||||
* @param xtalType: xtal type
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* Check parameter*/
|
||||
CHECK_PARAM(IS_PDS_PLL_XTAL_TYPE(xtalType));
|
||||
|
||||
/**************************/
|
||||
/* select PLL XTAL source */
|
||||
/**************************/
|
||||
|
||||
if ((xtalType == PDS_PLL_XTAL_RC32M) || (xtalType == PDS_PLL_XTAL_NONE)) {
|
||||
PDS_Trim_RC32M();
|
||||
PDS_Select_RC32M_As_PLL_Ref();
|
||||
} else {
|
||||
PDS_Select_XTAL_As_PLL_Ref();
|
||||
}
|
||||
|
||||
/*******************************************/
|
||||
/* PLL power down first, not indispensable */
|
||||
/*******************************************/
|
||||
/* power off PLL first, this step is not indispensable */
|
||||
PDS_Power_Off_PLL();
|
||||
|
||||
/********************/
|
||||
/* PLL param config */
|
||||
/********************/
|
||||
|
||||
/* clkpll_icp_1u */
|
||||
/* clkpll_icp_5u */
|
||||
/* clkpll_int_frac_sw */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_CP);
|
||||
|
||||
if (xtalType == PDS_PLL_XTAL_26M) {
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_1U, 1);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_5U, 0);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_INT_FRAC_SW, 1);
|
||||
} else {
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_1U, 0);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_5U, 2);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_INT_FRAC_SW, 0);
|
||||
}
|
||||
|
||||
BL_WR_REG(PDS_BASE, PDS_CLKPLL_CP, tmpVal);
|
||||
|
||||
/* clkpll_c3 */
|
||||
/* clkpll_cz */
|
||||
/* clkpll_rz */
|
||||
/* clkpll_r4 */
|
||||
/* clkpll_r4_short */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_RZ);
|
||||
|
||||
if (xtalType == PDS_PLL_XTAL_26M) {
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_C3, 2);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_CZ, 2);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RZ, 5);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4_SHORT, 0);
|
||||
} else {
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_C3, 3);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_CZ, 1);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RZ, 1);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4_SHORT, 1);
|
||||
}
|
||||
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4, 2);
|
||||
BL_WR_REG(PDS_BASE, PDS_CLKPLL_RZ, tmpVal);
|
||||
|
||||
/* clkpll_refdiv_ratio */
|
||||
/* clkpll_postdiv */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 0x14);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_REFDIV_RATIO, 2);
|
||||
BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
|
||||
|
||||
/* clkpll_sdmin */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
|
||||
|
||||
switch (xtalType) {
|
||||
case PDS_PLL_XTAL_NONE:
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000);
|
||||
break;
|
||||
|
||||
case PDS_PLL_XTAL_24M:
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x500000);
|
||||
break;
|
||||
|
||||
case PDS_PLL_XTAL_32M:
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000);
|
||||
break;
|
||||
|
||||
case PDS_PLL_XTAL_38P4M:
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x320000);
|
||||
break;
|
||||
|
||||
case PDS_PLL_XTAL_40M:
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x300000);
|
||||
break;
|
||||
|
||||
case PDS_PLL_XTAL_26M:
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x49D39D);
|
||||
break;
|
||||
|
||||
case PDS_PLL_XTAL_RC32M:
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000);
|
||||
break;
|
||||
|
||||
default:
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000);
|
||||
break;
|
||||
}
|
||||
|
||||
BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal);
|
||||
|
||||
/* clkpll_sel_fb_clk */
|
||||
/* clkpll_sel_sample_clk can be 0/1, default is 1 */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_FBDV);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_FB_CLK, 1);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_SAMPLE_CLK, 1);
|
||||
BL_WR_REG(PDS_BASE, PDS_CLKPLL_FBDV, tmpVal);
|
||||
|
||||
/*************************/
|
||||
/* PLL power up sequence */
|
||||
/*************************/
|
||||
|
||||
/* pu_clkpll_sfreg=1 */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG);
|
||||
BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
|
||||
|
||||
BL602_Delay_US(5);
|
||||
|
||||
/* pu_clkpll=1 */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL);
|
||||
BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
|
||||
|
||||
/* clkpll_pu_cp=1 */
|
||||
/* clkpll_pu_pfd=1 */
|
||||
/* clkpll_pu_fbdv=1 */
|
||||
/* clkpll_pu_postdiv=1 */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV);
|
||||
BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
|
||||
|
||||
BL602_Delay_US(5);
|
||||
|
||||
/* clkpll_sdm_reset=1 */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET);
|
||||
BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
|
||||
BL602_Delay_US(1);
|
||||
/* clkpll_reset_fbdv=1 */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV);
|
||||
BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
|
||||
BL602_Delay_US(2);
|
||||
/* clkpll_reset_fbdv=0 */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV);
|
||||
BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
|
||||
BL602_Delay_US(1);
|
||||
/* clkpll_sdm_reset=0 */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET);
|
||||
BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Fix XTAL26M Setting
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_CLOCK_SECTION PDS_Fix_Xtal_Settig(void)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
|
||||
/* Fix 26M xtal clkpll_sdmin */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
|
||||
|
||||
if (0x49D39D == BL_GET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN)) {
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x49D89E);
|
||||
BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/** PLL output config **/
|
||||
/*
|
||||
[8] 1'h0 r/w clkpll_en_32m
|
||||
[7] 1'h0 r/w clkpll_en_48m
|
||||
[6] 1'h0 r/w clkpll_en_80m
|
||||
[5] 1'h0 r/w clkpll_en_96m
|
||||
[4] 1'h0 r/w clkpll_en_120m
|
||||
[3] 1'h0 r/w clkpll_en_160m
|
||||
[2] 1'h0 r/w clkpll_en_192m
|
||||
[1] 1'h0 r/w clkpll_en_240m
|
||||
[0] 1'h0 r/w clkpll_en_480m
|
||||
*/
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Enable all PLL clock
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_All_Clks(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
|
||||
tmpVal |= 0x1FF;
|
||||
BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Disable all PLL clock
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_All_Clks(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
|
||||
tmpVal &= (~0x1FF);
|
||||
BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Enable PLL clock
|
||||
*
|
||||
* @param pllClk: PLL clock type
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* Check parameter*/
|
||||
CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));
|
||||
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
|
||||
tmpVal |= (1 << pllClk);
|
||||
BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Disable PLL clock
|
||||
*
|
||||
* @param pllClk: PLL clock type
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* Check parameter*/
|
||||
CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));
|
||||
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
|
||||
tmpVal &= (~(1 << pllClk));
|
||||
BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power off PLL
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
/* pu_clkpll_sfreg=0 */
|
||||
/* pu_clkpll=0 */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL);
|
||||
BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
|
||||
|
||||
/* clkpll_pu_cp=0 */
|
||||
/* clkpll_pu_pfd=0 */
|
||||
/* clkpll_pu_fbdv=0 */
|
||||
/* clkpll_pu_postdiv=0 */
|
||||
tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV);
|
||||
BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Power down sleep wake up interrupt handler
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_HAL_DRIVER
|
||||
void PDS_WAKEUP_IRQHandler(void)
|
||||
{
|
||||
for (PDS_INT_Type intType = PDS_INT_WAKEUP; intType < PDS_INT_MAX; intType++) {
|
||||
if (PDS_Get_IntStatus(intType) && (pdsIntCbfArra[intType][0] != NULL)) {
|
||||
pdsIntCbfArra[intType][0]();
|
||||
}
|
||||
}
|
||||
|
||||
PDS_IntClear();
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@} end of group PDS_Public_Functions */
|
||||
|
||||
/*@} end of group PDS */
|
||||
|
||||
/*@} end of group BL602_Peripheral_Driver */
|
||||
2193
drivers/soc/bl602/bl602_std/src/bl602_sf_cfg.c
Normal file
2193
drivers/soc/bl602/bl602_std/src/bl602_sf_cfg.c
Normal file
File diff suppressed because it is too large
Load Diff
790
drivers/soc/bl602/bl602_std/src/bl602_sf_cfg_ext.c
Normal file
790
drivers/soc/bl602/bl602_std/src/bl602_sf_cfg_ext.c
Normal file
@ -0,0 +1,790 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file bl602_sf_cfg_ext.c
|
||||
* @version V1.0
|
||||
* @date
|
||||
* @brief This file is the standard driver c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "bl602_glb.h"
|
||||
#include "bl602_sf_cfg.h"
|
||||
#include "bl602_sf_cfg_ext.h"
|
||||
#include "bl602_xip_sflash.h"
|
||||
#include "bl602_romdriver.h"
|
||||
#include "soft_crc.h"
|
||||
|
||||
/** @addtogroup BL602_Peripheral_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SF_CFG_EXT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SF_CFG_EXT_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
#define BFLB_FLASH_CFG_MAGIC "FCFG"
|
||||
|
||||
/*@} end of group SF_CFG_EXT_Private_Macros */
|
||||
|
||||
/** @defgroup SF_CFG_EXT_Private_Types
|
||||
* @{
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t jedecID;
|
||||
char *name;
|
||||
const SPI_Flash_Cfg_Type *cfg;
|
||||
}Flash_Info_t;
|
||||
|
||||
/*@} end of group SF_CFG_EXT_Private_Types */
|
||||
|
||||
/** @defgroup SF_CFG_EXT_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_FM_25Q08={
|
||||
.resetCreadCmd=0xff,
|
||||
.resetCreadCmdSize=3,
|
||||
.mid=0xc8,
|
||||
|
||||
.deBurstWrapCmd=0x77,
|
||||
.deBurstWrapCmdDmyClk=0x3,
|
||||
.deBurstWrapDataMode=SF_CTRL_DATA_4_LINES,
|
||||
.deBurstWrapData=0xF0,
|
||||
|
||||
/*reg*/
|
||||
.writeEnableCmd=0x06,
|
||||
.wrEnableIndex=0x00,
|
||||
.wrEnableBit=0x01,
|
||||
.wrEnableReadRegLen=0x01,
|
||||
|
||||
.qeIndex=1,
|
||||
.qeBit=0x01,
|
||||
.qeWriteRegLen=0x02,
|
||||
.qeReadRegLen=0x1,
|
||||
|
||||
.busyIndex=0,
|
||||
.busyBit=0x00,
|
||||
.busyReadRegLen=0x1,
|
||||
.releasePowerDown=0xab,
|
||||
|
||||
.readRegCmd[0]=0x05,
|
||||
.readRegCmd[1]=0x35,
|
||||
.writeRegCmd[0]=0x01,
|
||||
.writeRegCmd[1]=0x01,
|
||||
|
||||
.fastReadQioCmd=0xeb,
|
||||
.frQioDmyClk=16/8,
|
||||
.cReadSupport=1,
|
||||
.cReadMode=0xa0,
|
||||
|
||||
.burstWrapCmd=0x77,
|
||||
.burstWrapCmdDmyClk=0x3,
|
||||
.burstWrapDataMode=SF_CTRL_DATA_4_LINES,
|
||||
.burstWrapData=0x40,
|
||||
/*erase*/
|
||||
.chipEraseCmd=0xc7,
|
||||
.sectorEraseCmd=0x20,
|
||||
.blk32EraseCmd=0x52,
|
||||
.blk64EraseCmd=0xd8,
|
||||
/*write*/
|
||||
.pageProgramCmd=0x02,
|
||||
.qpageProgramCmd=0x32,
|
||||
.qppAddrMode=SF_CTRL_ADDR_1_LINE,
|
||||
|
||||
.ioMode=SF_CTRL_QIO_MODE,
|
||||
.clkDelay=1,
|
||||
.clkInvert=0x01,
|
||||
|
||||
.resetEnCmd=0x66,
|
||||
.resetCmd=0x99,
|
||||
.cRExit=0xff,
|
||||
.wrEnableWriteRegLen=0x00,
|
||||
|
||||
/*id*/
|
||||
.jedecIdCmd=0x9f,
|
||||
.jedecIdCmdDmyClk=0,
|
||||
.qpiJedecIdCmd=0x9f,
|
||||
.qpiJedecIdCmdDmyClk=0x00,
|
||||
.sectorSize=4,
|
||||
.pageSize=256,
|
||||
|
||||
/*read*/
|
||||
.fastReadCmd=0x0b,
|
||||
.frDmyClk=8/8,
|
||||
.qpiFastReadCmd =0x0b,
|
||||
.qpiFrDmyClk=8/8,
|
||||
.fastReadDoCmd=0x3b,
|
||||
.frDoDmyClk=8/8,
|
||||
.fastReadDioCmd=0xbb,
|
||||
.frDioDmyClk=0,
|
||||
.fastReadQoCmd=0x6b,
|
||||
.frQoDmyClk=8/8,
|
||||
|
||||
.qpiFastReadQioCmd=0xeb,
|
||||
.qpiFrQioDmyClk=16/8,
|
||||
.qpiPageProgramCmd=0x02,
|
||||
.writeVregEnableCmd=0x50,
|
||||
|
||||
/* qpi mode */
|
||||
.enterQpi=0x38,
|
||||
.exitQpi=0xff,
|
||||
|
||||
/*AC*/
|
||||
.timeEsector=300,
|
||||
.timeE32k=1200,
|
||||
.timeE64k=1200,
|
||||
.timePagePgm=5,
|
||||
.timeCe=33000,
|
||||
.pdDelay=20,
|
||||
.qeData=0,
|
||||
};
|
||||
|
||||
static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Md_40D={
|
||||
.resetCreadCmd=0xff,
|
||||
.resetCreadCmdSize=3,
|
||||
.mid=0x51,
|
||||
|
||||
.deBurstWrapCmd=0x77,
|
||||
.deBurstWrapCmdDmyClk=0x3,
|
||||
.deBurstWrapDataMode=SF_CTRL_DATA_4_LINES,
|
||||
.deBurstWrapData=0xF0,
|
||||
|
||||
/*reg*/
|
||||
.writeEnableCmd=0x06,
|
||||
.wrEnableIndex=0x00,
|
||||
.wrEnableBit=0x01,
|
||||
.wrEnableReadRegLen=0x01,
|
||||
|
||||
.qeIndex=1,
|
||||
.qeBit=0x01,
|
||||
.qeWriteRegLen=0x02,
|
||||
.qeReadRegLen=0x1,
|
||||
|
||||
.busyIndex=0,
|
||||
.busyBit=0x00,
|
||||
.busyReadRegLen=0x1,
|
||||
.releasePowerDown=0xab,
|
||||
|
||||
.readRegCmd[0]=0x05,
|
||||
.readRegCmd[1]=0x35,
|
||||
.writeRegCmd[0]=0x01,
|
||||
.writeRegCmd[1]=0x01,
|
||||
|
||||
.fastReadQioCmd=0xeb,
|
||||
.frQioDmyClk=16/8,
|
||||
.cReadSupport=0,
|
||||
.cReadMode=0xA0,
|
||||
|
||||
.burstWrapCmd=0x77,
|
||||
.burstWrapCmdDmyClk=0x3,
|
||||
.burstWrapDataMode=SF_CTRL_DATA_4_LINES,
|
||||
.burstWrapData=0x40,
|
||||
/*erase*/
|
||||
.chipEraseCmd=0xc7,
|
||||
.sectorEraseCmd=0x20,
|
||||
.blk32EraseCmd=0x52,
|
||||
.blk64EraseCmd=0xd8,
|
||||
/*write*/
|
||||
.pageProgramCmd=0x02,
|
||||
.qpageProgramCmd=0x32,
|
||||
.qppAddrMode=SF_CTRL_ADDR_1_LINE,
|
||||
|
||||
.ioMode=0x11,
|
||||
.clkDelay=1,
|
||||
.clkInvert=0x01,
|
||||
|
||||
.resetEnCmd=0x66,
|
||||
.resetCmd=0x99,
|
||||
.cRExit=0xff,
|
||||
.wrEnableWriteRegLen=0x00,
|
||||
|
||||
/*id*/
|
||||
.jedecIdCmd=0x9f,
|
||||
.jedecIdCmdDmyClk=0,
|
||||
.qpiJedecIdCmd=0x9f,
|
||||
.qpiJedecIdCmdDmyClk=0x00,
|
||||
.sectorSize=4,
|
||||
.pageSize=256,
|
||||
|
||||
/*read*/
|
||||
.fastReadCmd=0x0b,
|
||||
.frDmyClk=8/8,
|
||||
.qpiFastReadCmd =0x0b,
|
||||
.qpiFrDmyClk=8/8,
|
||||
.fastReadDoCmd=0x3b,
|
||||
.frDoDmyClk=8/8,
|
||||
.fastReadDioCmd=0xbb,
|
||||
.frDioDmyClk=0,
|
||||
.fastReadQoCmd=0x6b,
|
||||
.frQoDmyClk=8/8,
|
||||
|
||||
.qpiFastReadQioCmd=0xeb,
|
||||
.qpiFrQioDmyClk=16/8,
|
||||
.qpiPageProgramCmd=0x02,
|
||||
.writeVregEnableCmd=0x50,
|
||||
|
||||
/* qpi mode */
|
||||
.enterQpi=0x38,
|
||||
.exitQpi=0xff,
|
||||
|
||||
/*AC*/
|
||||
.timeEsector=300,
|
||||
.timeE32k=1200,
|
||||
.timeE64k=1200,
|
||||
.timePagePgm=5,
|
||||
.timeCe=33000,
|
||||
.pdDelay=20,
|
||||
.qeData=0,
|
||||
};
|
||||
|
||||
static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_XM25QH16={
|
||||
.resetCreadCmd=0xff,
|
||||
.resetCreadCmdSize=3,
|
||||
.mid=0x20,
|
||||
|
||||
.deBurstWrapCmd=0x77,
|
||||
.deBurstWrapCmdDmyClk=0x3,
|
||||
.deBurstWrapDataMode=SF_CTRL_DATA_4_LINES,
|
||||
.deBurstWrapData=0xF0,
|
||||
|
||||
/*reg*/
|
||||
.writeEnableCmd=0x06,
|
||||
.wrEnableIndex=0x00,
|
||||
.wrEnableBit=0x01,
|
||||
.wrEnableReadRegLen=0x01,
|
||||
|
||||
.qeIndex=1,
|
||||
.qeBit=0x01,
|
||||
.qeWriteRegLen=0x01,
|
||||
.qeReadRegLen=0x1,
|
||||
|
||||
.busyIndex=0,
|
||||
.busyBit=0x00,
|
||||
.busyReadRegLen=0x1,
|
||||
.releasePowerDown=0xab,
|
||||
|
||||
.readRegCmd[0]=0x05,
|
||||
.readRegCmd[1]=0x35,
|
||||
.writeRegCmd[0]=0x01,
|
||||
.writeRegCmd[1]=0x31,
|
||||
|
||||
.fastReadQioCmd=0xeb,
|
||||
.frQioDmyClk=16/8,
|
||||
.cReadSupport=1,
|
||||
.cReadMode=0x20,
|
||||
|
||||
.burstWrapCmd=0x77,
|
||||
.burstWrapCmdDmyClk=0x3,
|
||||
.burstWrapDataMode=SF_CTRL_DATA_4_LINES,
|
||||
.burstWrapData=0x40,
|
||||
/*erase*/
|
||||
.chipEraseCmd=0xc7,
|
||||
.sectorEraseCmd=0x20,
|
||||
.blk32EraseCmd=0x52,
|
||||
.blk64EraseCmd=0xd8,
|
||||
/*write*/
|
||||
.pageProgramCmd=0x02,
|
||||
.qpageProgramCmd=0x32,
|
||||
.qppAddrMode=SF_CTRL_ADDR_1_LINE,
|
||||
|
||||
.ioMode=SF_CTRL_QIO_MODE,
|
||||
.clkDelay=1,
|
||||
.clkInvert=0x01,
|
||||
|
||||
.resetEnCmd=0x66,
|
||||
.resetCmd=0x99,
|
||||
.cRExit=0xff,
|
||||
.wrEnableWriteRegLen=0x00,
|
||||
|
||||
/*id*/
|
||||
.jedecIdCmd=0x9f,
|
||||
.jedecIdCmdDmyClk=0,
|
||||
.qpiJedecIdCmd=0x9f,
|
||||
.qpiJedecIdCmdDmyClk=0x00,
|
||||
.sectorSize=4,
|
||||
.pageSize=256,
|
||||
|
||||
/*read*/
|
||||
.fastReadCmd=0x0b,
|
||||
.frDmyClk=8/8,
|
||||
.qpiFastReadCmd =0x0b,
|
||||
.qpiFrDmyClk=8/8,
|
||||
.fastReadDoCmd=0x3b,
|
||||
.frDoDmyClk=8/8,
|
||||
.fastReadDioCmd=0xbb,
|
||||
.frDioDmyClk=0,
|
||||
.fastReadQoCmd=0x6b,
|
||||
.frQoDmyClk=8/8,
|
||||
|
||||
.qpiFastReadQioCmd=0xeb,
|
||||
.qpiFrQioDmyClk=16/8,
|
||||
.qpiPageProgramCmd=0x02,
|
||||
.writeVregEnableCmd=0x50,
|
||||
|
||||
/* qpi mode */
|
||||
.enterQpi=0x38,
|
||||
.exitQpi=0xff,
|
||||
|
||||
/*AC*/
|
||||
.timeEsector=400,
|
||||
.timeE32k=1600,
|
||||
.timeE64k=2000,
|
||||
.timePagePgm=5,
|
||||
.timeCe=33000,
|
||||
.pdDelay=3,
|
||||
.qeData=0,
|
||||
};
|
||||
|
||||
static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_MX_KH25={
|
||||
.resetCreadCmd=0xff,
|
||||
.resetCreadCmdSize=3,
|
||||
.mid=0xc2,
|
||||
|
||||
.deBurstWrapCmd=0x77,
|
||||
.deBurstWrapCmdDmyClk=0x3,
|
||||
.deBurstWrapDataMode=SF_CTRL_DATA_4_LINES,
|
||||
.deBurstWrapData=0xF0,
|
||||
|
||||
/*reg*/
|
||||
.writeEnableCmd=0x06,
|
||||
.wrEnableIndex=0x00,
|
||||
.wrEnableBit=0x01,
|
||||
.wrEnableReadRegLen=0x01,
|
||||
|
||||
.qeIndex=1,
|
||||
.qeBit=0x01,
|
||||
.qeWriteRegLen=0x01,
|
||||
.qeReadRegLen=0x1,
|
||||
|
||||
.busyIndex=0,
|
||||
.busyBit=0x00,
|
||||
.busyReadRegLen=0x1,
|
||||
.releasePowerDown=0xab,
|
||||
|
||||
.readRegCmd[0]=0x05,
|
||||
.readRegCmd[1]=0x00,
|
||||
.writeRegCmd[0]=0x01,
|
||||
.writeRegCmd[1]=0x00,
|
||||
|
||||
.fastReadQioCmd=0xeb,
|
||||
.frQioDmyClk=16/8,
|
||||
.cReadSupport=0,
|
||||
.cReadMode=0x20,
|
||||
|
||||
.burstWrapCmd=0x77,
|
||||
.burstWrapCmdDmyClk=0x3,
|
||||
.burstWrapDataMode=SF_CTRL_DATA_4_LINES,
|
||||
.burstWrapData=0x40,
|
||||
/*erase*/
|
||||
.chipEraseCmd=0xc7,
|
||||
.sectorEraseCmd=0x20,
|
||||
.blk32EraseCmd=0x52,
|
||||
.blk64EraseCmd=0xd8,
|
||||
/*write*/
|
||||
.pageProgramCmd=0x02,
|
||||
.qpageProgramCmd=0x32,
|
||||
.qppAddrMode=SF_CTRL_ADDR_1_LINE,
|
||||
|
||||
.ioMode=0x11,
|
||||
.clkDelay=1,
|
||||
.clkInvert=0x01,
|
||||
|
||||
.resetEnCmd=0x66,
|
||||
.resetCmd=0x99,
|
||||
.cRExit=0xff,
|
||||
.wrEnableWriteRegLen=0x00,
|
||||
|
||||
/*id*/
|
||||
.jedecIdCmd=0x9f,
|
||||
.jedecIdCmdDmyClk=0,
|
||||
.qpiJedecIdCmd=0x9f,
|
||||
.qpiJedecIdCmdDmyClk=0x00,
|
||||
.sectorSize=4,
|
||||
.pageSize=256,
|
||||
|
||||
/*read*/
|
||||
.fastReadCmd=0x0b,
|
||||
.frDmyClk=8/8,
|
||||
.qpiFastReadCmd =0x0b,
|
||||
.qpiFrDmyClk=8/8,
|
||||
.fastReadDoCmd=0x3b,
|
||||
.frDoDmyClk=8/8,
|
||||
.fastReadDioCmd=0xbb,
|
||||
.frDioDmyClk=0,
|
||||
.fastReadQoCmd=0x6b,
|
||||
.frQoDmyClk=8/8,
|
||||
|
||||
.qpiFastReadQioCmd=0xeb,
|
||||
.qpiFrQioDmyClk=16/8,
|
||||
.qpiPageProgramCmd=0x02,
|
||||
.writeVregEnableCmd=0x50,
|
||||
|
||||
/* qpi mode */
|
||||
.enterQpi=0x38,
|
||||
.exitQpi=0xff,
|
||||
|
||||
/*AC*/
|
||||
.timeEsector=300,
|
||||
.timeE32k=1200,
|
||||
.timeE64k=1200,
|
||||
.timePagePgm=5,
|
||||
.timeCe=33000,
|
||||
.pdDelay=20,
|
||||
.qeData=0,
|
||||
};
|
||||
|
||||
static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_ZD_25Q16B={
|
||||
.resetCreadCmd=0xff,
|
||||
.resetCreadCmdSize=3,
|
||||
.mid=0xba,
|
||||
|
||||
.deBurstWrapCmd=0x77,
|
||||
.deBurstWrapCmdDmyClk=0x3,
|
||||
.deBurstWrapDataMode=SF_CTRL_DATA_4_LINES,
|
||||
.deBurstWrapData=0xF0,
|
||||
|
||||
/*reg*/
|
||||
.writeEnableCmd=0x06,
|
||||
.wrEnableIndex=0x00,
|
||||
.wrEnableBit=0x01,
|
||||
.wrEnableReadRegLen=0x01,
|
||||
|
||||
.qeIndex=1,
|
||||
.qeBit=0x01,
|
||||
.qeWriteRegLen=0x02,
|
||||
.qeReadRegLen=0x1,
|
||||
|
||||
.busyIndex=0,
|
||||
.busyBit=0x00,
|
||||
.busyReadRegLen=0x1,
|
||||
.releasePowerDown=0xab,
|
||||
|
||||
.readRegCmd[0]=0x05,
|
||||
.readRegCmd[1]=0x35,
|
||||
.writeRegCmd[0]=0x01,
|
||||
.writeRegCmd[1]=0x01,
|
||||
|
||||
.fastReadQioCmd=0xeb,
|
||||
.frQioDmyClk=16/8,
|
||||
.cReadSupport=1,
|
||||
.cReadMode=0xa0,
|
||||
|
||||
.burstWrapCmd=0x77,
|
||||
.burstWrapCmdDmyClk=0x3,
|
||||
.burstWrapDataMode=SF_CTRL_DATA_4_LINES,
|
||||
.burstWrapData=0x40,
|
||||
/*erase*/
|
||||
.chipEraseCmd=0xc7,
|
||||
.sectorEraseCmd=0x20,
|
||||
.blk32EraseCmd=0x52,
|
||||
.blk64EraseCmd=0xd8,
|
||||
/*write*/
|
||||
.pageProgramCmd=0x02,
|
||||
.qpageProgramCmd=0x32,
|
||||
.qppAddrMode=SF_CTRL_ADDR_1_LINE,
|
||||
|
||||
.ioMode=0x14,
|
||||
.clkDelay=1,
|
||||
.clkInvert=0x01,
|
||||
|
||||
.resetEnCmd=0x66,
|
||||
.resetCmd=0x99,
|
||||
.cRExit=0xff,
|
||||
.wrEnableWriteRegLen=0x00,
|
||||
|
||||
/*id*/
|
||||
.jedecIdCmd=0x9f,
|
||||
.jedecIdCmdDmyClk=0,
|
||||
.qpiJedecIdCmd=0x9f,
|
||||
.qpiJedecIdCmdDmyClk=0x00,
|
||||
.sectorSize=4,
|
||||
.pageSize=256,
|
||||
|
||||
/*read*/
|
||||
.fastReadCmd=0x0b,
|
||||
.frDmyClk=8/8,
|
||||
.qpiFastReadCmd =0x0b,
|
||||
.qpiFrDmyClk=8/8,
|
||||
.fastReadDoCmd=0x3b,
|
||||
.frDoDmyClk=8/8,
|
||||
.fastReadDioCmd=0xbb,
|
||||
.frDioDmyClk=0,
|
||||
.fastReadQoCmd=0x6b,
|
||||
.frQoDmyClk=8/8,
|
||||
|
||||
.qpiFastReadQioCmd=0xeb,
|
||||
.qpiFrQioDmyClk=16/8,
|
||||
.qpiPageProgramCmd=0x02,
|
||||
.writeVregEnableCmd=0x50,
|
||||
|
||||
/* qpi mode */
|
||||
.enterQpi=0x38,
|
||||
.exitQpi=0xff,
|
||||
|
||||
/*AC*/
|
||||
.timeEsector=300,
|
||||
.timeE32k=1200,
|
||||
.timeE64k=1200,
|
||||
.timePagePgm=5,
|
||||
.timeCe=33000,
|
||||
.pdDelay=20,
|
||||
.qeData=0,
|
||||
};
|
||||
|
||||
static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[]={
|
||||
{
|
||||
.jedecID=0x1440A1,
|
||||
//.name="FM_25Q08",
|
||||
.cfg=&flashCfg_FM_25Q08,
|
||||
},
|
||||
{
|
||||
.jedecID=0x134051,
|
||||
//.name="GD_MD04D_04_33",
|
||||
.cfg=&flashCfg_Gd_Md_40D,
|
||||
},
|
||||
{
|
||||
.jedecID=0x144020,
|
||||
//.name="XM_25QH80_80_33",
|
||||
.cfg=&flashCfg_XM25QH16,
|
||||
},
|
||||
{
|
||||
.jedecID=0x154020,
|
||||
//.name="XM_25QH16_16_33",
|
||||
.cfg=&flashCfg_XM25QH16,
|
||||
},
|
||||
{
|
||||
.jedecID=0x164020,
|
||||
//.name="XM_25QH32_32_33",
|
||||
.cfg=&flashCfg_XM25QH16,
|
||||
},
|
||||
{
|
||||
.jedecID=0x174020,
|
||||
//.name="XM_25QH64_64_33",
|
||||
.cfg=&flashCfg_XM25QH16,
|
||||
},
|
||||
{
|
||||
.jedecID=0x1320C2,
|
||||
//.name="MX_KH40_04_33",
|
||||
.cfg=&flashCfg_MX_KH25,
|
||||
},
|
||||
{
|
||||
.jedecID=0x1420C2,
|
||||
//.name="MX_KH80_08_33",
|
||||
.cfg=&flashCfg_MX_KH25,
|
||||
},
|
||||
{
|
||||
.jedecID=0x1520C2,
|
||||
//.name="MX_KH16_16_33",
|
||||
.cfg=&flashCfg_MX_KH25,
|
||||
},
|
||||
{
|
||||
.jedecID=0x13325E,
|
||||
//.name="ZB_D40B_80_33",
|
||||
.cfg=&flashCfg_MX_KH25,
|
||||
},
|
||||
{
|
||||
.jedecID=0x14325E,
|
||||
//.name="ZB_D80B_80_33",
|
||||
.cfg=&flashCfg_MX_KH25,
|
||||
},
|
||||
{
|
||||
.jedecID=0x15405E,
|
||||
//.name="ZB_25Q16B_15_33",
|
||||
.cfg=&flashCfg_XM25QH16,
|
||||
},
|
||||
{
|
||||
.jedecID=0x16405E,
|
||||
//.name="ZB_25Q32B_16_33",
|
||||
.cfg=&flashCfg_XM25QH16,
|
||||
},
|
||||
{
|
||||
.jedecID=0x17405E,
|
||||
//.name="ZB_25VQ64_64_33",
|
||||
.cfg=&flashCfg_XM25QH16,
|
||||
},
|
||||
{
|
||||
.jedecID=0x15605E,
|
||||
//.name="ZB_25VQ16_16_33",
|
||||
.cfg=&flashCfg_XM25QH16,
|
||||
},
|
||||
{
|
||||
.jedecID=0x15345E,
|
||||
//.name="ZB_25WQ16_16_33",
|
||||
.cfg=&flashCfg_XM25QH16,
|
||||
},
|
||||
{
|
||||
.jedecID=0x1560EB,
|
||||
//.name="TH_25Q16",
|
||||
.cfg=&flashCfg_FM_25Q08,
|
||||
},
|
||||
{
|
||||
.jedecID=0x1740C8,
|
||||
//.name="GD_25Q64E_64_33",
|
||||
.cfg=&flashCfg_XM25QH16,
|
||||
},
|
||||
{
|
||||
.jedecID=0x1840C8,
|
||||
//.name="GD_25Q127C_128_33",
|
||||
.cfg=&flashCfg_XM25QH16,
|
||||
},
|
||||
{
|
||||
.jedecID=0x176085,
|
||||
//.name="Puya_P25Q64H_64_33",
|
||||
.cfg=&flashCfg_XM25QH16,
|
||||
},
|
||||
{
|
||||
.jedecID=0x17400B,
|
||||
//.name="XT_25F64B",
|
||||
.cfg=&flashCfg_FM_25Q08,
|
||||
},
|
||||
{
|
||||
.jedecID=0x1560BA,
|
||||
//.name="ZD_25Q16B",
|
||||
.cfg=&flashCfg_ZD_25Q16B,
|
||||
},
|
||||
{
|
||||
.jedecID=0x1460CD,
|
||||
//.name="TH_25Q80HB",
|
||||
.cfg=&flashCfg_FM_25Q08,
|
||||
},
|
||||
{
|
||||
.jedecID=0x1870EF,
|
||||
//.name="W25Q128JV_128_33",
|
||||
.cfg=&flashCfg_XM25QH16,
|
||||
},
|
||||
};
|
||||
|
||||
/*@} end of group SF_CFG_EXT_Private_Variables */
|
||||
|
||||
/** @defgroup SF_CFG_EXT_Global_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group SF_CFG_EXT_Global_Variables */
|
||||
|
||||
/** @defgroup SF_CFG_EXT_Private_Fun_Declaration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group SF_CFG_EXT_Private_Fun_Declaration */
|
||||
|
||||
/** @defgroup SF_CFG_EXT_Public_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Get flash config according to flash ID
|
||||
*
|
||||
* @param flashID: Flash ID
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID,SPI_Flash_Cfg_Type * pFlashCfg)
|
||||
{
|
||||
uint32_t i;
|
||||
uint8_t buf[sizeof(SPI_Flash_Cfg_Type)+8];
|
||||
uint32_t crc,*pCrc;
|
||||
char flashCfgMagic[] = "FCFG";
|
||||
|
||||
if(flashID==0){
|
||||
XIP_SFlash_Read_Via_Cache_Need_Lock(8+BL602_FLASH_XIP_BASE,buf,sizeof(SPI_Flash_Cfg_Type)+8);
|
||||
if(BL602_MemCmp(buf,flashCfgMagic,4)==0){
|
||||
crc=BFLB_Soft_CRC32((uint8_t *)buf+4,sizeof(SPI_Flash_Cfg_Type));
|
||||
pCrc=(uint32_t *)(buf+4+sizeof(SPI_Flash_Cfg_Type));
|
||||
if(*pCrc==crc){
|
||||
BL602_MemCpy_Fast(pFlashCfg,(uint8_t *)buf+4,sizeof(SPI_Flash_Cfg_Type));
|
||||
return SUCCESS ;
|
||||
}
|
||||
}
|
||||
}else{
|
||||
if(SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg) == SUCCESS){
|
||||
return SUCCESS;
|
||||
}
|
||||
for(i=0;i<sizeof(flashInfos)/sizeof(flashInfos[0]);i++){
|
||||
if(flashInfos[i].jedecID==flashID){
|
||||
BL602_MemCpy_Fast(pFlashCfg,flashInfos[i].cfg,sizeof(SPI_Flash_Cfg_Type));
|
||||
return SUCCESS;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Identify one flash
|
||||
*
|
||||
* @param callFromFlash: code run at flash or ram
|
||||
* @param autoScan: Auto scan all GPIO pin
|
||||
* @param flashPinCfg: Specify flash GPIO config, not auto scan
|
||||
* @param restoreDefault: Wether restore default flash GPIO config
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
*
|
||||
* @return Flash ID
|
||||
*
|
||||
*******************************************************************************/
|
||||
uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash,
|
||||
uint32_t autoScan,uint32_t flashPinCfg,uint8_t restoreDefault,SPI_Flash_Cfg_Type * pFlashCfg)
|
||||
{
|
||||
uint32_t jdecId=0;
|
||||
uint32_t i=0;
|
||||
uint32_t ret=0;
|
||||
|
||||
ret=SF_Cfg_Flash_Identify(callFromFlash,autoScan,flashPinCfg,restoreDefault,pFlashCfg);
|
||||
if(callFromFlash){
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg,pFlashCfg->ioMode&0xf,1,0,32);
|
||||
}
|
||||
if((ret&BFLB_FLASH_ID_VALID_FLAG)!=0){
|
||||
return ret;
|
||||
}
|
||||
|
||||
jdecId=(ret&0xffffff);
|
||||
for(i=0;i<sizeof(flashInfos)/sizeof(flashInfos[0]);i++){
|
||||
if(flashInfos[i].jedecID==jdecId){
|
||||
BL602_MemCpy_Fast(pFlashCfg,flashInfos[i].cfg,sizeof(SPI_Flash_Cfg_Type));
|
||||
break;
|
||||
}
|
||||
}
|
||||
if(i==sizeof(flashInfos)/sizeof(flashInfos[0])){
|
||||
return jdecId;
|
||||
}else{
|
||||
return (jdecId|BFLB_FLASH_ID_VALID_FLAG);
|
||||
}
|
||||
}
|
||||
|
||||
/*@} end of group SF_CFG_EXT_Public_Functions */
|
||||
|
||||
/*@} end of group SF_CFG_EXT */
|
||||
|
||||
/*@} end of group BL602_Peripheral_Driver */
|
||||
1149
drivers/soc/bl602/bl602_std/src/bl602_sf_ctrl.c
Normal file
1149
drivers/soc/bl602/bl602_std/src/bl602_sf_ctrl.c
Normal file
File diff suppressed because it is too large
Load Diff
1549
drivers/soc/bl602/bl602_std/src/bl602_sflash.c
Normal file
1549
drivers/soc/bl602/bl602_std/src/bl602_sflash.c
Normal file
File diff suppressed because it is too large
Load Diff
608
drivers/soc/bl602/bl602_std/src/bl602_sflash_ext.c
Normal file
608
drivers/soc/bl602/bl602_std/src/bl602_sflash_ext.c
Normal file
@ -0,0 +1,608 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file bl602_sflash_ext.c
|
||||
* @version V1.0
|
||||
* @date
|
||||
* @brief This file is the standard driver c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "bl602_l1c.h"
|
||||
#include "bl602_sflash_ext.h"
|
||||
#include "bl602_sf_ctrl.h"
|
||||
#include "l1c_reg.h"
|
||||
|
||||
/** @addtogroup BL602_Peripheral_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup SFLASH_EXT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup SFLASH_EXT_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group SFLASH_EXT_Private_Macros */
|
||||
|
||||
/** @defgroup SFLASH_EXT_Private_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group SFLASH_EXT_Private_Types */
|
||||
|
||||
/** @defgroup SFLASH_EXT_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000)
|
||||
|
||||
/*@} end of group SFLASH_EXT_Private_Variables */
|
||||
|
||||
/** @defgroup SFLASH_EXT_Global_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group SFLASH_EXT_Global_Variables */
|
||||
|
||||
/** @defgroup SFLASH_EXT_Private_Fun_Declaration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group SFLASH_EXT_Private_Fun_Declaration */
|
||||
|
||||
/** @defgroup SFLASH_EXT_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group SFLASH_EXT_Private_Functions */
|
||||
|
||||
/** @defgroup SFLASH_EXT_Public_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Sflash restore from power down
|
||||
*
|
||||
* @param pFlashCfg: Flash configuration pointer
|
||||
* @param flashContRead: Whether enable continuous read
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead)
|
||||
{
|
||||
BL_Err_Type stat = SUCCESS;
|
||||
uint32_t jdecId = 0;
|
||||
uint8_t tmp[8];
|
||||
uint8_t ioMode = pFlashCfg->ioMode & 0xf;
|
||||
|
||||
/* Wake flash up from power down */
|
||||
SFlash_Releae_Powerdown(pFlashCfg);
|
||||
BL602_Delay_US(120);
|
||||
|
||||
SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId);
|
||||
|
||||
if (SF_CTRL_QO_MODE == ioMode || SF_CTRL_QIO_MODE == ioMode) {
|
||||
SFlash_Qspi_Enable(pFlashCfg);
|
||||
}
|
||||
|
||||
if (((pFlashCfg->ioMode >> 4) & 0x01) == 1) {
|
||||
/* unwrap */
|
||||
L1C_Set_Wrap(DISABLE);
|
||||
} else {
|
||||
/* burst wrap */
|
||||
L1C_Set_Wrap(ENABLE);
|
||||
/* For command that is setting register instead of send command, we need write enable */
|
||||
SFlash_Write_Enable(pFlashCfg);
|
||||
SFlash_SetBurstWrap(pFlashCfg);
|
||||
}
|
||||
|
||||
if (flashContRead) {
|
||||
stat = SFlash_Read(pFlashCfg, ioMode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
|
||||
stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
|
||||
} else {
|
||||
stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 0, 0, 32);
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Sflash enable RCV mode to recovery for erase while power drop
|
||||
*
|
||||
* @param pFlashCfg: Flash configuration pointer
|
||||
* @param rCmd: Read RCV register cmd
|
||||
* @param wCmd: Write RCV register cmd
|
||||
* @param bitPos: RCV register bit pos
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_TCM_SECTION SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t cnt = 0;
|
||||
uint32_t tempVal = 0;
|
||||
|
||||
while (SET == SFlash_Busy(pFlashCfg)) {
|
||||
BL602_Delay_US(500);
|
||||
cnt++;
|
||||
|
||||
if (cnt > 20000 * 3) {
|
||||
return ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1);
|
||||
|
||||
if (SUCCESS != stat) {
|
||||
stat = ERROR;
|
||||
}
|
||||
|
||||
if (((tempVal >> bitPos) & 0x01) > 0) {
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
tempVal |= (uint32_t)(1 << bitPos);
|
||||
stat = SFlash_Write_Enable(pFlashCfg);
|
||||
|
||||
if (SUCCESS != stat) {
|
||||
stat = ERROR;
|
||||
}
|
||||
|
||||
stat = SFlash_Write_Reg_With_Cmd(pFlashCfg, wCmd, (uint8_t *)&tempVal, 1);
|
||||
|
||||
if (SUCCESS != stat) {
|
||||
return stat;
|
||||
}
|
||||
|
||||
while (SET == SFlash_Busy(pFlashCfg)) {
|
||||
BL602_Delay_US(500);
|
||||
cnt++;
|
||||
|
||||
if (cnt > 20000 * 3) {
|
||||
return ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1);
|
||||
|
||||
if (SUCCESS != stat) {
|
||||
stat = ERROR;
|
||||
}
|
||||
|
||||
if (((tempVal >> bitPos) & 0x01) <= 0) {
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Erase flash security register one block
|
||||
*
|
||||
* @param pFlashCfg: Flash configuration pointer
|
||||
* @param pSecRegCfg: Security register configuration pointer
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_TCM_SECTION SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg)
|
||||
{
|
||||
uint32_t cnt = 0;
|
||||
uint8_t cmd = 0;
|
||||
uint8_t secOptMode = 0;
|
||||
uint32_t timeOut = 0;
|
||||
SF_Ctrl_Cmd_Cfg_Type flashCmd;
|
||||
|
||||
if (pSecRegCfg->enterSecOptCmd != 0x00) {
|
||||
secOptMode = 1;
|
||||
|
||||
if (((uint32_t)&flashCmd) % 4 == 0) {
|
||||
BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
|
||||
} else {
|
||||
BL602_MemSet(&flashCmd, 0, sizeof(flashCmd));
|
||||
}
|
||||
|
||||
flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24);
|
||||
flashCmd.rwFlag = SF_CTRL_WRITE;
|
||||
SF_Ctrl_SendCmd(&flashCmd);
|
||||
|
||||
timeOut = SFCTRL_BUSY_STATE_TIMEOUT;
|
||||
|
||||
while (SET == SF_Ctrl_GetBusyState()) {
|
||||
timeOut--;
|
||||
|
||||
if (timeOut == 0) {
|
||||
return TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
BL_Err_Type stat = SFlash_Write_Enable(pFlashCfg);
|
||||
|
||||
if (stat != SUCCESS) {
|
||||
return stat;
|
||||
}
|
||||
|
||||
if (((uint32_t)&flashCmd) % 4 == 0) {
|
||||
BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
|
||||
} else {
|
||||
BL602_MemSet(&flashCmd, 0, sizeof(flashCmd));
|
||||
}
|
||||
|
||||
cmd = pSecRegCfg->eraseCmd;
|
||||
flashCmd.cmdBuf[0] = (cmd << 24) | (pSecRegCfg->blockNum << 12);
|
||||
/* rwFlag don't care */
|
||||
flashCmd.rwFlag = SF_CTRL_READ;
|
||||
flashCmd.addrSize = 3;
|
||||
|
||||
SF_Ctrl_SendCmd(&flashCmd);
|
||||
|
||||
while (SET == SFlash_Busy(pFlashCfg)) {
|
||||
BL602_Delay_US(500);
|
||||
cnt++;
|
||||
|
||||
if (cnt > pFlashCfg->timeEsector * 3) {
|
||||
return ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
if (secOptMode > 0) {
|
||||
if (((uint32_t)&flashCmd) % 4 == 0) {
|
||||
BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
|
||||
} else {
|
||||
BL602_MemSet(&flashCmd, 0, sizeof(flashCmd));
|
||||
}
|
||||
|
||||
flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24);
|
||||
flashCmd.rwFlag = SF_CTRL_WRITE;
|
||||
SF_Ctrl_SendCmd(&flashCmd);
|
||||
|
||||
timeOut = SFCTRL_BUSY_STATE_TIMEOUT;
|
||||
|
||||
while (SET == SF_Ctrl_GetBusyState()) {
|
||||
timeOut--;
|
||||
|
||||
if (timeOut == 0) {
|
||||
return TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Program flash security register one block
|
||||
*
|
||||
* @param pFlashCfg: Flash configuration pointer
|
||||
* @param pSecRegCfg: Security register configuration pointer
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_TCM_SECTION SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg)
|
||||
{
|
||||
uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
|
||||
uint32_t i = 0, curLen = 0;
|
||||
uint32_t cnt = 0;
|
||||
BL_Err_Type stat;
|
||||
uint8_t cmd;
|
||||
uint8_t secOptMode = 0;
|
||||
uint8_t *data = pSecRegCfg->data;
|
||||
uint32_t addr = pSecRegCfg->addr;
|
||||
uint32_t len = pSecRegCfg->len;
|
||||
uint32_t currentAddr = 0;
|
||||
uint32_t timeOut = 0;
|
||||
SF_Ctrl_Cmd_Cfg_Type flashCmd;
|
||||
|
||||
if (pSecRegCfg->enterSecOptCmd != 0x00) {
|
||||
secOptMode = 1;
|
||||
|
||||
if (((uint32_t)&flashCmd) % 4 == 0) {
|
||||
BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
|
||||
} else {
|
||||
BL602_MemSet(&flashCmd, 0, sizeof(flashCmd));
|
||||
}
|
||||
|
||||
flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24);
|
||||
flashCmd.rwFlag = SF_CTRL_WRITE;
|
||||
SF_Ctrl_SendCmd(&flashCmd);
|
||||
|
||||
timeOut = SFCTRL_BUSY_STATE_TIMEOUT;
|
||||
|
||||
while (SET == SF_Ctrl_GetBusyState()) {
|
||||
timeOut--;
|
||||
|
||||
if (timeOut == 0) {
|
||||
return TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (((uint32_t)&flashCmd) % 4 == 0) {
|
||||
BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
|
||||
} else {
|
||||
BL602_MemSet(&flashCmd, 0, sizeof(flashCmd));
|
||||
}
|
||||
|
||||
/* Prepare command */
|
||||
flashCmd.rwFlag = SF_CTRL_WRITE;
|
||||
flashCmd.addrSize = 3;
|
||||
cmd = pSecRegCfg->programCmd;
|
||||
|
||||
for (i = 0; i < len;) {
|
||||
/* Write enable is needed for every program */
|
||||
stat = SFlash_Write_Enable(pFlashCfg);
|
||||
|
||||
if (stat != SUCCESS) {
|
||||
return stat;
|
||||
}
|
||||
|
||||
/* Get current programmed length within page size */
|
||||
curLen = 256 - addr % 256;
|
||||
|
||||
if (curLen > len - i) {
|
||||
curLen = len - i;
|
||||
}
|
||||
|
||||
currentAddr = (pSecRegCfg->blockNum << 12) | addr;
|
||||
|
||||
/* Prepare command */
|
||||
BL602_MemCpy_Fast(flashCtrlBuf, data, curLen);
|
||||
flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr);
|
||||
flashCmd.nbData = curLen;
|
||||
|
||||
SF_Ctrl_SendCmd(&flashCmd);
|
||||
|
||||
/* Adjust address and programmed length */
|
||||
addr += curLen;
|
||||
i += curLen;
|
||||
data += curLen;
|
||||
|
||||
/* Wait for write done */
|
||||
cnt = 0;
|
||||
|
||||
while (SET == SFlash_Busy(pFlashCfg)) {
|
||||
BL602_Delay_US(100);
|
||||
cnt++;
|
||||
|
||||
if (cnt > pFlashCfg->timePagePgm * 20) {
|
||||
return ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (secOptMode > 0) {
|
||||
if (((uint32_t)&flashCmd) % 4 == 0) {
|
||||
BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
|
||||
} else {
|
||||
BL602_MemSet(&flashCmd, 0, sizeof(flashCmd));
|
||||
}
|
||||
|
||||
flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24);
|
||||
flashCmd.rwFlag = SF_CTRL_WRITE;
|
||||
SF_Ctrl_SendCmd(&flashCmd);
|
||||
|
||||
timeOut = SFCTRL_BUSY_STATE_TIMEOUT;
|
||||
|
||||
while (SET == SF_Ctrl_GetBusyState()) {
|
||||
timeOut--;
|
||||
|
||||
if (timeOut == 0) {
|
||||
return TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Read data from flash security register one block
|
||||
*
|
||||
* @param pSecRegCfg: Security register configuration pointer
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg)
|
||||
{
|
||||
uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE;
|
||||
uint32_t curLen, i;
|
||||
uint8_t cmd;
|
||||
uint8_t secOptMode = 0;
|
||||
uint8_t *data = pSecRegCfg->data;
|
||||
uint32_t addr = pSecRegCfg->addr;
|
||||
uint32_t len = pSecRegCfg->len;
|
||||
uint32_t currentAddr = 0;
|
||||
uint32_t timeOut = 0;
|
||||
SF_Ctrl_Cmd_Cfg_Type flashCmd;
|
||||
|
||||
if (pSecRegCfg->enterSecOptCmd != 0x00) {
|
||||
secOptMode = 1;
|
||||
|
||||
if (((uint32_t)&flashCmd) % 4 == 0) {
|
||||
BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
|
||||
} else {
|
||||
BL602_MemSet(&flashCmd, 0, sizeof(flashCmd));
|
||||
}
|
||||
|
||||
flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24);
|
||||
flashCmd.rwFlag = SF_CTRL_WRITE;
|
||||
SF_Ctrl_SendCmd(&flashCmd);
|
||||
|
||||
timeOut = SFCTRL_BUSY_STATE_TIMEOUT;
|
||||
|
||||
while (SET == SF_Ctrl_GetBusyState()) {
|
||||
timeOut--;
|
||||
|
||||
if (timeOut == 0) {
|
||||
return TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (((uint32_t)&flashCmd) % 4 == 0) {
|
||||
BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
|
||||
} else {
|
||||
BL602_MemSet(&flashCmd, 0, sizeof(flashCmd));
|
||||
}
|
||||
|
||||
/* Prepare command */
|
||||
flashCmd.rwFlag = SF_CTRL_READ;
|
||||
flashCmd.addrSize = 3;
|
||||
flashCmd.dummyClks = 1;
|
||||
cmd = pSecRegCfg->readCmd;
|
||||
|
||||
/* Read data */
|
||||
for (i = 0; i < len;) {
|
||||
currentAddr = (pSecRegCfg->blockNum << 12) | addr;
|
||||
/* Prepare command */
|
||||
flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr);
|
||||
curLen = len - i;
|
||||
|
||||
if (curLen >= FLASH_CTRL_BUF_SIZE) {
|
||||
curLen = FLASH_CTRL_BUF_SIZE;
|
||||
flashCmd.nbData = curLen;
|
||||
} else {
|
||||
/* Make sf_ctrl word read */
|
||||
flashCmd.nbData = ((curLen + 3) >> 2) << 2;
|
||||
}
|
||||
|
||||
SF_Ctrl_SendCmd(&flashCmd);
|
||||
|
||||
timeOut = SFCTRL_BUSY_STATE_TIMEOUT;
|
||||
|
||||
while (SET == SF_Ctrl_GetBusyState()) {
|
||||
timeOut--;
|
||||
|
||||
if (timeOut == 0) {
|
||||
return TIMEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
BL602_MemCpy_Fast(data, flashCtrlBuf, curLen);
|
||||
|
||||
addr += curLen;
|
||||
i += curLen;
|
||||
data += curLen;
|
||||
}
|
||||
|
||||
if (secOptMode > 0) {
|
||||
if (((uint32_t)&flashCmd) % 4 == 0) {
|
||||
BL602_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4);
|
||||
} else {
|
||||
BL602_MemSet(&flashCmd, 0, sizeof(flashCmd));
|
||||
}
|
||||
|
||||
flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24);
|
||||
flashCmd.rwFlag = SF_CTRL_WRITE;
|
||||
SF_Ctrl_SendCmd(&flashCmd);
|
||||
|
||||
timeOut = SFCTRL_BUSY_STATE_TIMEOUT;
|
||||
|
||||
while (SET == SF_Ctrl_GetBusyState()) {
|
||||
timeOut--;
|
||||
|
||||
if (timeOut == 0) {
|
||||
return TIMEOUT;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Clear flash status register
|
||||
*
|
||||
* @param pFlashCfg: Flash configuration pointer
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_TCM_SECTION SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *pFlashCfg)
|
||||
{
|
||||
uint32_t ret = 0;
|
||||
uint32_t qeValue = 0;
|
||||
uint32_t regValue = 0;
|
||||
uint32_t readValue = 0;
|
||||
uint8_t readRegValue0 = 0;
|
||||
uint8_t readRegValue1 = 0;
|
||||
|
||||
if((pFlashCfg->ioMode&0xf)==SF_CTRL_QO_MODE || (pFlashCfg->ioMode&0xf)==SF_CTRL_QIO_MODE){
|
||||
qeValue = 1;
|
||||
}
|
||||
|
||||
SFlash_Read_Reg(pFlashCfg, 0, (uint8_t *)&readRegValue0, 1);
|
||||
SFlash_Read_Reg(pFlashCfg, 1, (uint8_t *)&readRegValue1, 1);
|
||||
readValue = (readRegValue0|(readRegValue1<<8));
|
||||
if ((readValue & (~((1<<(pFlashCfg->qeIndex*8+pFlashCfg->qeBit)) |
|
||||
(1<<(pFlashCfg->busyIndex*8+pFlashCfg->busyBit)) |
|
||||
(1<<(pFlashCfg->wrEnableIndex*8+pFlashCfg->wrEnableBit))))) == 0){
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
ret = SFlash_Write_Enable(pFlashCfg);
|
||||
if (SUCCESS != ret) {
|
||||
return ERROR;
|
||||
}
|
||||
if (pFlashCfg->qeWriteRegLen == 2) {
|
||||
regValue = (qeValue<<(pFlashCfg->qeIndex*8+pFlashCfg->qeBit));
|
||||
SFlash_Write_Reg(pFlashCfg, 0, (uint8_t *)®Value, 2);
|
||||
} else {
|
||||
if (pFlashCfg->qeIndex == 0) {
|
||||
regValue = (qeValue<<pFlashCfg->qeBit);
|
||||
} else {
|
||||
regValue = 0;
|
||||
}
|
||||
SFlash_Write_Reg(pFlashCfg, 0, (uint8_t *)®Value, 1);
|
||||
ret = SFlash_Write_Enable(pFlashCfg);
|
||||
if (SUCCESS != ret) {
|
||||
return ERROR;
|
||||
}
|
||||
if (pFlashCfg->qeIndex == 1) {
|
||||
regValue = (qeValue<<pFlashCfg->qeBit);
|
||||
} else {
|
||||
regValue = 0;
|
||||
}
|
||||
SFlash_Write_Reg(pFlashCfg, 1, (uint8_t *)®Value, 1);
|
||||
}
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*@} end of group SFLASH_EXT_Public_Functions */
|
||||
|
||||
/*@} end of group SFLASH_EXT */
|
||||
|
||||
/*@} end of group BL602_Peripheral_Driver */
|
||||
434
drivers/soc/bl602/bl602_std/src/bl602_xip_sflash.c
Normal file
434
drivers/soc/bl602/bl602_std/src/bl602_xip_sflash.c
Normal file
@ -0,0 +1,434 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file bl602_xip_sflash.c
|
||||
* @version V1.0
|
||||
* @date
|
||||
* @brief This file is the standard driver c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "string.h"
|
||||
#include "bl602_xip_sflash.h"
|
||||
|
||||
/** @addtogroup BL602_Peripheral_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup XIP_SFLASH
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup XIP_SFLASH_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group XIP_SFLASH_Private_Macros */
|
||||
|
||||
/** @defgroup XIP_SFLASH_Private_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group XIP_SFLASH_Private_Types */
|
||||
|
||||
/** @defgroup XIP_SFLASH_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group XIP_SFLASH_Private_Variables */
|
||||
|
||||
/** @defgroup XIP_SFLASH_Global_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group XIP_SFLASH_Global_Variables */
|
||||
|
||||
/** @defgroup XIP_SFLASH_Private_Fun_Declaration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group XIP_SFLASH_Private_Fun_Declaration */
|
||||
|
||||
/** @defgroup XIP_SFLASH_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Save flash controller state
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param offset: CPU XIP flash offset pointer
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset)
|
||||
{
|
||||
/* XIP_SFlash_Delay */
|
||||
volatile uint32_t i = 32 * 2;
|
||||
|
||||
while (i--)
|
||||
;
|
||||
|
||||
SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
|
||||
/* Exit form continous read for accepting command */
|
||||
SFlash_Reset_Continue_Read(pFlashCfg);
|
||||
/* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */
|
||||
SFlash_Software_Reset(pFlashCfg);
|
||||
/* For disable command that is setting register instaed of send command, we need write enable */
|
||||
SFlash_DisableBurstWrap(pFlashCfg);
|
||||
/* Enable QE again in case reset command make it reset */
|
||||
SFlash_Qspi_Enable(pFlashCfg);
|
||||
/* Deburst again to make sure */
|
||||
SFlash_DisableBurstWrap(pFlashCfg);
|
||||
|
||||
/* Clear offset setting*/
|
||||
*offset = SF_Ctrl_Get_Flash_Image_Offset();
|
||||
SF_Ctrl_Set_Flash_Image_Offset(0);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Restore flash controller state
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param offset: CPU XIP flash offset
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset)
|
||||
{
|
||||
uint32_t tmp[1];
|
||||
|
||||
SF_Ctrl_Set_Flash_Image_Offset(offset);
|
||||
|
||||
SFlash_SetBurstWrap(pFlashCfg);
|
||||
SFlash_Read(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0x0, (uint8_t *)tmp, sizeof(tmp));
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*@} end of group XIP_SFLASH_Private_Functions */
|
||||
|
||||
/** @defgroup XIP_SFLASH_Public_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Erase flash one region
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param startaddr: start address to erase
|
||||
* @param endaddr: end address(include this address) to erase
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, uint32_t endaddr)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
|
||||
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
|
||||
|
||||
if (stat != SUCCESS) {
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32);
|
||||
} else {
|
||||
stat = SFlash_Erase(pFlashCfg, startaddr, endaddr);
|
||||
XIP_SFlash_State_Restore(pFlashCfg, offset);
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Program flash one region
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param addr: start address to be programed
|
||||
* @param data: data pointer to be programed
|
||||
* @param len: data length to be programed
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
|
||||
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
|
||||
|
||||
if (stat != SUCCESS) {
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32);
|
||||
} else {
|
||||
stat = SFlash_Program(pFlashCfg, SF_CTRL_QIO_MODE, addr, data, len);
|
||||
XIP_SFlash_State_Restore(pFlashCfg, offset);
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Read data from flash
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param addr: flash read start address
|
||||
* @param data: data pointer to store data read from flash
|
||||
* @param len: data length to read
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
|
||||
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
|
||||
|
||||
if (stat != SUCCESS) {
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32);
|
||||
} else {
|
||||
stat = SFlash_Read(pFlashCfg, SF_CTRL_QIO_MODE, 0, addr, data, len);
|
||||
XIP_SFlash_State_Restore(pFlashCfg, offset);
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Get Flash Jedec ID
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param data: data pointer to store Jedec ID Read from flash
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
|
||||
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
|
||||
|
||||
if (stat != SUCCESS) {
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32);
|
||||
} else {
|
||||
SFlash_GetJedecId(pFlashCfg, data);
|
||||
XIP_SFlash_State_Restore(pFlashCfg, offset);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Get Flash Device ID
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param data: data pointer to store Device ID Read from flash
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
|
||||
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
|
||||
|
||||
if (stat != SUCCESS) {
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32);
|
||||
} else {
|
||||
SFlash_GetDeviceId(data);
|
||||
XIP_SFlash_State_Restore(pFlashCfg, offset);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Get Flash Unique ID
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param data: data pointer to store Device ID Read from flash
|
||||
* @param idLen: Unique id len
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
|
||||
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
|
||||
|
||||
if (stat != SUCCESS) {
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, SF_CTRL_QIO_MODE, 1, 0, 32);
|
||||
} else {
|
||||
SFlash_GetUniqueId(data, idLen);
|
||||
XIP_SFlash_State_Restore(pFlashCfg, offset);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Read data from flash via XIP
|
||||
*
|
||||
* @param addr: flash read start address
|
||||
* @param data: data pointer to store data read from flash
|
||||
* @param len: data length to read
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len)
|
||||
{
|
||||
uint32_t offset;
|
||||
|
||||
if (addr >= BL602_FLASH_XIP_BASE && addr < BL602_FLASH_XIP_END) {
|
||||
offset = SF_Ctrl_Get_Flash_Image_Offset();
|
||||
SF_Ctrl_Set_Flash_Image_Offset(0);
|
||||
/* Flash read */
|
||||
BL602_MemCpy_Fast(data, (void *)(addr), len);
|
||||
SF_Ctrl_Set_Flash_Image_Offset(offset);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @return 0
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *dst, int len)
|
||||
{
|
||||
__disable_irq();
|
||||
XIP_SFlash_Read_Need_Lock(pFlashCfg, addr, dst, len);
|
||||
__enable_irq();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Program flash one region with lock
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param addr: Start address to be programed
|
||||
* @param src: Data pointer to be programed
|
||||
* @param len: Data length to be programed
|
||||
*
|
||||
* @return 0
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *src, int len)
|
||||
{
|
||||
__disable_irq();
|
||||
XIP_SFlash_Write_Need_Lock(pFlashCfg, addr, src, len);
|
||||
__enable_irq();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Erase flash one region with lock
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param addr: Start address to be erased
|
||||
* @param len: Data length to be erased
|
||||
*
|
||||
* @return 0
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
int ATTR_TCM_SECTION XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, int len)
|
||||
{
|
||||
__disable_irq();
|
||||
XIP_SFlash_Erase_Need_Lock(pFlashCfg, addr, addr + len - 1);
|
||||
__enable_irq();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief XIP SFlash option save
|
||||
*
|
||||
* @param aesEnable: AES enable status pointer
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(uint8_t *aesEnable)
|
||||
{
|
||||
*aesEnable = SF_Ctrl_Is_AES_Enable();
|
||||
|
||||
if (*aesEnable) {
|
||||
SF_Ctrl_AES_Disable();
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief XIP SFlash option restore
|
||||
*
|
||||
* @param aesEnable: AES enable status
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable)
|
||||
{
|
||||
if (aesEnable) {
|
||||
SF_Ctrl_AES_Enable();
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@} end of group XIP_SFLASH_Public_Functions */
|
||||
|
||||
/*@} end of group XIP_SFLASH */
|
||||
|
||||
/*@} end of group BL602_Peripheral_Driver */
|
||||
583
drivers/soc/bl602/bl602_std/src/bl602_xip_sflash_ext.c
Normal file
583
drivers/soc/bl602/bl602_std/src/bl602_xip_sflash_ext.c
Normal file
@ -0,0 +1,583 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file bl602_xip_sflash_ext.c
|
||||
* @version V1.0
|
||||
* @date
|
||||
* @brief This file is the standard driver c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "string.h"
|
||||
#include "bl602_sf_cfg.h"
|
||||
#include "bl602_sf_cfg_ext.h"
|
||||
#include "bl602_xip_sflash.h"
|
||||
#include "bl602_xip_sflash_ext.h"
|
||||
|
||||
/** @addtogroup BL602_Peripheral_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup XIP_SFLASH_EXT
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup XIP_SFLASH_EXT_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group XIP_SFLASH_EXT_Private_Macros */
|
||||
|
||||
/** @defgroup XIP_SFLASH_EXT_Private_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group XIP_SFLASH_EXT_Private_Types */
|
||||
|
||||
/** @defgroup XIP_SFLASH_EXT_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
static SPI_Flash_Cfg_Type flashCfg;
|
||||
static uint8_t aesEnable;
|
||||
|
||||
/*@} end of group XIP_SFLASH_EXT_Private_Variables */
|
||||
|
||||
/** @defgroup XIP_SFLASH_EXT_Global_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group XIP_SFLASH_EXT_Global_Variables */
|
||||
|
||||
/** @defgroup XIP_SFLASH_EXT_Private_Fun_Declaration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group XIP_SFLASH_EXT_Private_Fun_Declaration */
|
||||
|
||||
/** @defgroup XIP_SFLASH_EXT_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group XIP_SFLASH_EXT_Private_Functions */
|
||||
|
||||
/** @defgroup XIP_SFLASH_EXT_Public_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Save flash controller state
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param offset: CPU XIP flash offset pointer
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t *offset)
|
||||
{
|
||||
/* XIP_SFlash_Delay */
|
||||
volatile uint32_t i=32*2;
|
||||
while(i--);
|
||||
|
||||
SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
|
||||
/* Exit form continous read for accepting command */
|
||||
SFlash_Reset_Continue_Read(pFlashCfg);
|
||||
/* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */
|
||||
SFlash_Software_Reset(pFlashCfg);
|
||||
/* For disable command that is setting register instaed of send command, we need write enable */
|
||||
SFlash_DisableBurstWrap(pFlashCfg);
|
||||
if ((pFlashCfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (pFlashCfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
|
||||
/* Enable QE again in case reset command make it reset */
|
||||
SFlash_Qspi_Enable(pFlashCfg);
|
||||
}
|
||||
/* Deburst again to make sure */
|
||||
SFlash_DisableBurstWrap(pFlashCfg);
|
||||
|
||||
/* Clear offset setting*/
|
||||
*offset=SF_Ctrl_Get_Flash_Image_Offset();
|
||||
SF_Ctrl_Set_Flash_Image_Offset(0);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Restore flash controller state
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param offset: CPU XIP flash offset
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset)
|
||||
{
|
||||
uint32_t tmp[1];
|
||||
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;
|
||||
|
||||
SF_Ctrl_Set_Flash_Image_Offset(offset);
|
||||
|
||||
if (((pFlashCfg->ioMode >> 4) & 0x01) == 0) {
|
||||
if ((pFlashCfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (pFlashCfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
|
||||
SFlash_SetBurstWrap(pFlashCfg);
|
||||
}
|
||||
}
|
||||
SFlash_Read(pFlashCfg, ioMode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp));
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*@} end of group XIP_SFLASH_EXT_Public_Functions */
|
||||
|
||||
/** @defgroup XIP_SFLASH_EXT_Public_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Erase flash one region
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param startaddr: start address to erase
|
||||
* @param endaddr: end address(include this address) to erase
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, uint32_t endaddr)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf;
|
||||
|
||||
XIP_SFlash_Opt_Enter(&aesEnable);
|
||||
stat=XIP_SFlash_State_Save(pFlashCfg,&offset);
|
||||
if(stat!=SUCCESS){
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32);
|
||||
}else{
|
||||
stat=SFlash_Erase(pFlashCfg,startaddr,endaddr);
|
||||
XIP_SFlash_State_Restore_Ext(pFlashCfg,offset);
|
||||
}
|
||||
XIP_SFlash_Opt_Exit(aesEnable);
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Program flash one region
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param addr: start address to be programed
|
||||
* @param data: data pointer to be programed
|
||||
* @param len: data length to be programed
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf;
|
||||
|
||||
XIP_SFlash_Opt_Enter(&aesEnable);
|
||||
stat=XIP_SFlash_State_Save(pFlashCfg,&offset);
|
||||
if(stat!=SUCCESS){
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32);
|
||||
}else{
|
||||
stat= SFlash_Program(pFlashCfg,ioMode,addr,data,len);
|
||||
XIP_SFlash_State_Restore_Ext(pFlashCfg,offset);
|
||||
}
|
||||
XIP_SFlash_Opt_Exit(aesEnable);
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Read data from flash
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param addr: flash read start address
|
||||
* @param data: data pointer to store data read from flash
|
||||
* @param len: data length to read
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf;
|
||||
|
||||
XIP_SFlash_Opt_Enter(&aesEnable);
|
||||
stat=XIP_SFlash_State_Save(pFlashCfg,&offset);
|
||||
if(stat!=SUCCESS){
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg,ioMode,1,0,32);
|
||||
}else{
|
||||
stat=SFlash_Read(pFlashCfg,ioMode,0,addr, data,len);
|
||||
XIP_SFlash_State_Restore_Ext(pFlashCfg,offset);
|
||||
}
|
||||
XIP_SFlash_Opt_Exit(aesEnable);
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Clear flash status register need lock
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf;
|
||||
|
||||
stat=XIP_SFlash_State_Save(pFlashCfg, &offset);
|
||||
if (stat != SUCCESS) {
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
|
||||
} else {
|
||||
stat=SFlash_Clear_Status_Register(pFlashCfg);
|
||||
XIP_SFlash_State_Restore_Ext(pFlashCfg, offset);
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Get Flash Jedec ID
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param data: data pointer to store Jedec ID Read from flash
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;
|
||||
|
||||
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
|
||||
if (stat != SUCCESS) {
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
|
||||
} else {
|
||||
SFlash_GetJedecId(pFlashCfg, data);
|
||||
XIP_SFlash_State_Restore_Ext(pFlashCfg, offset);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Get Flash Device ID
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param data: data pointer to store Device ID Read from flash
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;
|
||||
|
||||
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
|
||||
if (stat != SUCCESS) {
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
|
||||
} else {
|
||||
SFlash_GetDeviceId(data);
|
||||
XIP_SFlash_State_Restore_Ext(pFlashCfg, offset);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Get Flash Unique ID
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param data: data pointer to store Device ID Read from flash
|
||||
* @param idLen: Unique id len
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;
|
||||
|
||||
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
|
||||
if (stat != SUCCESS) {
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
|
||||
} else {
|
||||
SFlash_GetUniqueId(data, idLen);
|
||||
XIP_SFlash_State_Restore_Ext(pFlashCfg, offset);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Sflash enable RCV mode to recovery for erase while power drop need lock
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param rCmd: Read RCV register cmd
|
||||
* @param wCmd: Write RCV register cmd
|
||||
* @param bitPos: RCV register bit pos
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_RCV_Enable_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf;
|
||||
|
||||
stat = XIP_SFlash_State_Save(pFlashCfg, &offset);
|
||||
if (stat != SUCCESS) {
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
|
||||
} else {
|
||||
stat = SFlash_RCV_Enable(pFlashCfg, rCmd, wCmd, bitPos);
|
||||
XIP_SFlash_State_Restore_Ext(pFlashCfg, offset);
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Read data from flash with lock
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param addr: flash read start address
|
||||
* @param dst: data pointer to store data read from flash
|
||||
* @param len: data length to read
|
||||
*
|
||||
* @return 0
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *dst, int len)
|
||||
{
|
||||
__disable_irq();
|
||||
XIP_SFlash_Read_Need_Lock_Ext(pFlashCfg, addr, dst, len);
|
||||
__enable_irq();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Program flash one region with lock
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param addr: Start address to be programed
|
||||
* @param src: Data pointer to be programed
|
||||
* @param len: Data length to be programed
|
||||
*
|
||||
* @return 0
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, uint8_t *src, int len)
|
||||
{
|
||||
__disable_irq();
|
||||
XIP_SFlash_Write_Need_Lock_Ext(pFlashCfg, addr, src, len);
|
||||
__enable_irq();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Erase flash one region with lock
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param addr: Start address to be erased
|
||||
* @param len: Data length to be erased
|
||||
*
|
||||
* @return 0
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
int ATTR_TCM_SECTION XIP_SFlash_Erase_With_Lock_Ext(SPI_Flash_Cfg_Type *pFlashCfg,uint32_t addr, int len)
|
||||
{
|
||||
__disable_irq();
|
||||
XIP_SFlash_Erase_Need_Lock_Ext(pFlashCfg, addr, addr + len - 1);
|
||||
__enable_irq();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Clear flash status register with lock
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
*
|
||||
* @return 0
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
int ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg)
|
||||
{
|
||||
__disable_irq();
|
||||
XIP_SFlash_Clear_Status_Register_Need_Lock(pFlashCfg);
|
||||
__enable_irq();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Sflash enable RCV mode to recovery for erase while power drop with lock
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param rCmd: Read RCV register cmd
|
||||
* @param wCmd: Write RCV register cmd
|
||||
* @param bitPos: RCV register bit pos
|
||||
*
|
||||
* @return 0
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
int ATTR_TCM_SECTION XIP_SFlash_RCV_Enable_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos)
|
||||
{
|
||||
__disable_irq();
|
||||
XIP_SFlash_RCV_Enable_Need_Lock(pFlashCfg, rCmd, wCmd, bitPos);
|
||||
__enable_irq();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Read data from flash with lock
|
||||
*
|
||||
* @param pFlashCfg:Flash config pointer
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg)
|
||||
{
|
||||
uint32_t ret;
|
||||
|
||||
if(pFlashCfg==NULL){
|
||||
/* Get flash config identify */
|
||||
XIP_SFlash_Opt_Enter(&aesEnable);
|
||||
ret=SF_Cfg_Flash_Identify_Ext(1,1,0,0,&flashCfg);
|
||||
XIP_SFlash_Opt_Exit(aesEnable);
|
||||
if((ret&BFLB_FLASH_ID_VALID_FLAG)==0){
|
||||
return ERROR;
|
||||
}
|
||||
}else{
|
||||
memcpy(&flashCfg,pFlashCfg,sizeof(flashCfg));
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Read data from flash with lock
|
||||
*
|
||||
* @param addr: flash read start address
|
||||
* @param dst: data pointer to store data read from flash
|
||||
* @param len: data length to read
|
||||
*
|
||||
* @return 0
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
int ATTR_TCM_SECTION XIP_SFlash_Read(uint32_t addr, uint8_t *dst, int len)
|
||||
{
|
||||
__disable_irq();
|
||||
XIP_SFlash_Opt_Enter(&aesEnable);
|
||||
XIP_SFlash_Read_Need_Lock_Ext(&flashCfg, addr, dst, len);
|
||||
XIP_SFlash_Opt_Exit(aesEnable);
|
||||
__enable_irq();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Program flash one region with lock
|
||||
*
|
||||
* @param addr: Start address to be programed
|
||||
* @param src: Data pointer to be programed
|
||||
* @param len: Data length to be programed
|
||||
*
|
||||
* @return 0
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
int ATTR_TCM_SECTION XIP_SFlash_Write(uint32_t addr, uint8_t *src, int len)
|
||||
{
|
||||
__disable_irq();
|
||||
XIP_SFlash_Opt_Enter(&aesEnable);
|
||||
XIP_SFlash_Write_Need_Lock_Ext(&flashCfg, addr, src, len);
|
||||
XIP_SFlash_Opt_Exit(aesEnable);
|
||||
__enable_irq();
|
||||
return 0;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Erase flash one region with lock
|
||||
*
|
||||
* @param addr: Start address to be erased
|
||||
* @param len: Data length to be erased
|
||||
*
|
||||
* @return 0
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
int ATTR_TCM_SECTION XIP_SFlash_Erase(uint32_t addr, int len)
|
||||
{
|
||||
__disable_irq();
|
||||
XIP_SFlash_Opt_Enter(&aesEnable);
|
||||
XIP_SFlash_Erase_Need_Lock_Ext(&flashCfg, addr, addr + len - 1);
|
||||
XIP_SFlash_Opt_Exit(aesEnable);
|
||||
__enable_irq();
|
||||
return 0;
|
||||
}
|
||||
/*@} end of group XIP_SFLASH_EXT_Public_Functions */
|
||||
|
||||
/*@} end of group XIP_SFLASH_EXT */
|
||||
|
||||
/*@} end of group BL602_Peripheral_Driver */
|
||||
53
drivers/soc/bl602/port/bl602_efuse.c
Normal file
53
drivers/soc/bl602/port/bl602_efuse.c
Normal file
@ -0,0 +1,53 @@
|
||||
#include "bflb_efuse.h"
|
||||
#include "bl602_ef_ctrl.h"
|
||||
|
||||
float bflb_efuse_get_adc_trim(void)
|
||||
{
|
||||
Efuse_ADC_Gain_Coeff_Type trim;
|
||||
uint32_t tmp;
|
||||
|
||||
float coe = 1.0;
|
||||
|
||||
EF_Ctrl_Read_ADC_Gain_Trim(&trim);
|
||||
|
||||
if (trim.adcGainCoeffEn) {
|
||||
if (trim.adcGainCoeffParity == EF_Ctrl_Get_Trim_Parity(trim.adcGainCoeff, 12)) {
|
||||
tmp = trim.adcGainCoeff;
|
||||
|
||||
if (tmp & 0x800) {
|
||||
tmp = ~tmp;
|
||||
tmp += 1;
|
||||
tmp = tmp & 0xfff;
|
||||
coe = (1.0 + ((float)tmp / 2048.0));
|
||||
} else {
|
||||
coe = (1.0 - ((float)tmp / 2048.0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return coe;
|
||||
}
|
||||
|
||||
uint32_t bflb_efuse_get_adc_tsen_trim(void)
|
||||
{
|
||||
Efuse_TSEN_Refcode_Corner_Type trim;
|
||||
|
||||
EF_Ctrl_Read_TSEN_Trim(&trim);
|
||||
if (trim.tsenRefcodeCornerEn) {
|
||||
if (trim.tsenRefcodeCornerParity == EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner, 12)) {
|
||||
return trim.tsenRefcodeCorner;
|
||||
}
|
||||
}
|
||||
|
||||
return 2042;
|
||||
}
|
||||
|
||||
void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
|
||||
{
|
||||
EF_Ctrl_Write_AES_Key(index, (uint32_t *)data, len, 1);
|
||||
}
|
||||
|
||||
void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
|
||||
{
|
||||
EF_Ctrl_Read_AES_Key(index, (uint32_t *)data, len);
|
||||
}
|
||||
201
drivers/soc/bl602/port/bl602_flash.c
Normal file
201
drivers/soc/bl602/port/bl602_flash.c
Normal file
@ -0,0 +1,201 @@
|
||||
#include "bl602_glb.h"
|
||||
#include "bl602_xip_sflash.h"
|
||||
#include "bl602_xip_sflash_ext.h"
|
||||
#include "bl602_sf_cfg.h"
|
||||
#include "bl602_sf_cfg_ext.h"
|
||||
#include "bflb_flash.h"
|
||||
|
||||
static uint32_t g_jedec_id = 0;
|
||||
static SPI_Flash_Cfg_Type g_flash_cfg;
|
||||
|
||||
void ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg)
|
||||
{
|
||||
if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
|
||||
SFlash_Qspi_Enable(p_flash_cfg);
|
||||
}
|
||||
}
|
||||
|
||||
void ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg)
|
||||
{
|
||||
if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) {
|
||||
L1C_Set_Wrap(DISABLE);
|
||||
} else {
|
||||
L1C_Set_Wrap(ENABLE);
|
||||
if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
|
||||
SFlash_SetBurstWrap(p_flash_cfg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief flash_config_init
|
||||
*
|
||||
* @return int
|
||||
*/
|
||||
static int ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id)
|
||||
{
|
||||
int ret = -1;
|
||||
uint8_t isAesEnable = 0;
|
||||
uint32_t jid = 0;
|
||||
uint32_t offset = 0;
|
||||
uintptr_t flag;
|
||||
|
||||
flag = bflb_irq_save();
|
||||
XIP_SFlash_Opt_Enter(&isAesEnable);
|
||||
XIP_SFlash_State_Save(p_flash_cfg, &offset);
|
||||
SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid);
|
||||
arch_memcpy(jedec_id, (uint8_t *)&jid, 3);
|
||||
jid &= 0xFFFFFF;
|
||||
g_jedec_id = jid;
|
||||
ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg);
|
||||
if (ret == 0) {
|
||||
p_flash_cfg->mid = (jid & 0xff);
|
||||
}
|
||||
|
||||
/* Set flash controler from p_flash_cfg */
|
||||
flash_set_qspi_enable(p_flash_cfg);
|
||||
flash_set_l1c_wrap(p_flash_cfg);
|
||||
XIP_SFlash_State_Restore_Ext(p_flash_cfg, offset);
|
||||
XIP_SFlash_Opt_Exit(isAesEnable);
|
||||
bflb_irq_restore(flag);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief multi flash adapter
|
||||
*
|
||||
* @return int
|
||||
*/
|
||||
int ATTR_TCM_SECTION bflb_flash_init(void)
|
||||
{
|
||||
int ret = -1;
|
||||
uint8_t clkDelay = 1;
|
||||
uint8_t clkInvert = 1;
|
||||
uint32_t jedec_id = 0;
|
||||
uintptr_t flag;
|
||||
|
||||
flag = bflb_irq_save();
|
||||
SFlash_Cache_Flush();
|
||||
SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg);
|
||||
SFlash_Cache_Flush();
|
||||
bflb_irq_restore(flag);
|
||||
if (g_flash_cfg.mid != 0xff) {
|
||||
return 0;
|
||||
}
|
||||
clkDelay = g_flash_cfg.clkDelay;
|
||||
clkInvert = g_flash_cfg.clkInvert;
|
||||
g_flash_cfg.ioMode = g_flash_cfg.ioMode & 0x0f;
|
||||
|
||||
ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
|
||||
|
||||
g_flash_cfg.clkDelay = clkDelay;
|
||||
g_flash_cfg.clkInvert = clkInvert;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint32_t bflb_flash_get_jedecid(void)
|
||||
{
|
||||
uint32_t jid = 0;
|
||||
|
||||
jid = ((g_jedec_id & 0xff) << 16) + (g_jedec_id & 0xff00) + ((g_jedec_id & 0xff0000) >> 16);
|
||||
return jid;
|
||||
}
|
||||
|
||||
void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len)
|
||||
{
|
||||
*cfg_addr = (uint8_t *)&g_flash_cfg;
|
||||
*len = sizeof(SPI_Flash_Cfg_Type);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief flash erase
|
||||
*
|
||||
* @param startaddr
|
||||
* @param endaddr
|
||||
* @return int
|
||||
*/
|
||||
int ATTR_TCM_SECTION bflb_flash_erase(uint32_t startaddr, uint32_t len)
|
||||
{
|
||||
int ret = -1;
|
||||
uint8_t isAesEnable = 0;
|
||||
uintptr_t flag;
|
||||
|
||||
flag = bflb_irq_save();
|
||||
XIP_SFlash_Opt_Enter(&isAesEnable);
|
||||
ret = XIP_SFlash_Erase_Need_Lock_Ext(&g_flash_cfg, startaddr, startaddr + len - 1);
|
||||
XIP_SFlash_Opt_Exit(isAesEnable);
|
||||
bflb_irq_restore(flag);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief flash write data
|
||||
*
|
||||
* @param addr
|
||||
* @param data
|
||||
* @param len
|
||||
* @return int
|
||||
*/
|
||||
int ATTR_TCM_SECTION bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len)
|
||||
{
|
||||
int ret = -1;
|
||||
uint8_t isAesEnable = 0;
|
||||
uintptr_t flag;
|
||||
|
||||
flag = bflb_irq_save();
|
||||
XIP_SFlash_Opt_Enter(&isAesEnable);
|
||||
ret = XIP_SFlash_Write_Need_Lock_Ext(&g_flash_cfg, addr, data, len);
|
||||
XIP_SFlash_Opt_Exit(isAesEnable);
|
||||
bflb_irq_restore(flag);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief flash read data
|
||||
*
|
||||
* @param addr
|
||||
* @param data
|
||||
* @param len
|
||||
* @return int
|
||||
*/
|
||||
int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len)
|
||||
{
|
||||
int ret = -1;
|
||||
uint8_t isAesEnable = 0;
|
||||
uintptr_t flag;
|
||||
|
||||
flag = bflb_irq_save();
|
||||
XIP_SFlash_Opt_Enter(&isAesEnable);
|
||||
ret = XIP_SFlash_Read_Need_Lock_Ext(&g_flash_cfg, addr, data, len);
|
||||
XIP_SFlash_Opt_Exit(isAesEnable);
|
||||
bflb_irq_restore(flag);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config)
|
||||
{
|
||||
uint8_t hw_key_enable = 0;
|
||||
|
||||
if (config->key == NULL) {
|
||||
hw_key_enable = 1;
|
||||
}
|
||||
|
||||
SF_Ctrl_AES_Set_Key_BE(config->region, (uint8_t *)config->key, config->keybits);
|
||||
SF_Ctrl_AES_Set_IV_BE(config->region, (uint8_t *)config->iv, config->start_addr);
|
||||
SF_Ctrl_AES_Set_Region(config->region, config->region_enable, hw_key_enable, config->start_addr, config->end_addr - 1, config->lock_enable);
|
||||
}
|
||||
|
||||
void bflb_flash_aes_enable(void)
|
||||
{
|
||||
SF_Ctrl_AES_Enable();
|
||||
}
|
||||
|
||||
void bflb_flash_aes_disable(void)
|
||||
{
|
||||
SF_Ctrl_AES_Disable();
|
||||
}
|
||||
@ -187,5 +187,17 @@ __attribute__((interrupt, aligned(64))) void default_trap_handler(void)
|
||||
|
||||
__attribute__((interrupt)) __attribute__((weak)) void default_interrupt_handler(void)
|
||||
{
|
||||
__asm volatile("addi sp,sp,-8");
|
||||
__asm volatile("csrr a0,mcause");
|
||||
__asm volatile("csrr a1,mepc");
|
||||
__asm volatile("sw a0,4(sp)");
|
||||
__asm volatile("sw a1,0(sp)");
|
||||
__asm volatile("csrsi mstatus,8");
|
||||
interrupt_entry();
|
||||
__asm volatile("csrci mstatus,8");
|
||||
__asm volatile("lw a1,0(sp)");
|
||||
__asm volatile("lw a0,4(sp)");
|
||||
__asm volatile("csrw mepc,a1");
|
||||
__asm volatile("csrw mcause,a0");
|
||||
__asm volatile("addi sp,sp,8");
|
||||
}
|
||||
@ -10,23 +10,31 @@ sdk_library_add_sources(startup/interrupt.c)
|
||||
if(CONFIG_ROMAPI)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_romapi_e907.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_romapi_patch.c)
|
||||
sdk_add_compile_definitions(-DBFLB_USE_ROM_DRIVER)
|
||||
else()
|
||||
sdk_library_add_sources(bl616_std/src/bl616_aon.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_clock.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_ef_ctrl.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_glb_gpio.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_glb.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_hbn.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_l1c.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_pds.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_clock.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_glb_gpio.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_sf_cfg.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_sf_ctrl.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_sflash.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_xip_sflash.c)
|
||||
endif()
|
||||
|
||||
sdk_library_add_sources(bl616_std/src/bl616_common.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_ef_cfg.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_sdh.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_tzc_sec.c)
|
||||
sdk_library_add_sources(bl616_std/src/bl616_psram.c)
|
||||
# sdk_library_add_sources(bl616_std/src/bl616_l1c.c)
|
||||
# sdk_library_add_sources(bl616_std/src/bl616_ef_ctrl.c)
|
||||
# sdk_library_add_sources(bl616_std/src/bl616_ef_cfg.c)
|
||||
|
||||
sdk_library_add_sources(port/bl616_clock.c)
|
||||
sdk_library_add_sources(port/bl616_flash.c)
|
||||
sdk_library_add_sources(port/bl616_efuse.c)
|
||||
|
||||
sdk_add_include_directories(
|
||||
bl616_std/include
|
||||
@ -37,7 +45,7 @@ SET(MCPU "e907")
|
||||
SET(MARCH "rv32imafcpzpsfoperand_xtheade")
|
||||
SET(MABI "ilp32f")
|
||||
|
||||
sdk_add_compile_definitions(-DARCH_RISCV)
|
||||
sdk_add_compile_definitions(-DARCH_RISCV -DBFLB_USE_HAL_DRIVER)
|
||||
sdk_add_compile_options(-march=${MARCH} -mabi=${MABI} -mtune=${MCPU})
|
||||
sdk_add_link_options(-march=${MARCH} -mabi=${MABI} -mtune=${MCPU})
|
||||
|
||||
|
||||
@ -149,6 +149,16 @@ void check_failed(uint8_t *file, uint32_t line);
|
||||
*/
|
||||
#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK))
|
||||
|
||||
#define ARCH_MemCpy arch_memcpy
|
||||
#define ARCH_MemSet arch_memset
|
||||
#define ARCH_MemCmp arch_memcmp
|
||||
#define ARCH_MemCpy4 arch_memcpy4
|
||||
#define ARCH_MemCpy_Fast arch_memcpy_fast
|
||||
#define ARCH_MemSet4 arch_memset4
|
||||
#define BFLB_Soft_CRC32 bflb_soft_crc32
|
||||
#define CPU_Interrupt_Enable(irq)
|
||||
#define CPU_Interrupt_Disable(irq)
|
||||
#define Interrupt_Handler_Register(irq, callback)
|
||||
/*@} end of group COMMON_Public_Constants */
|
||||
|
||||
/** @defgroup DRIVER_Public_FunctionDeclaration
|
||||
@ -156,7 +166,7 @@ void check_failed(uint8_t *file, uint32_t line);
|
||||
* @{
|
||||
*/
|
||||
|
||||
void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun);
|
||||
// void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun);
|
||||
void ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT);
|
||||
void arch_delay_us(uint32_t cnt);
|
||||
void arch_delay_ms(uint32_t cnt);
|
||||
|
||||
@ -445,7 +445,7 @@ uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len);
|
||||
uint8_t EF_Ctrl_Read_FlashDlyCoe(void);
|
||||
|
||||
uint32_t EF_Ctrl_Get_Common_Trim_List(Efuse_Common_Trim_Cfg **trim_list);
|
||||
void EF_Ctrl_Read_Common_Trim(char *name, Efuse_Common_Trim_Type *trim);
|
||||
void EF_Ctrl_Read_Common_Trim(char *name, Efuse_Common_Trim_Type *trim, uint8_t reload);
|
||||
void EF_Ctrl_Write_Common_Trim(char *name, uint32_t value, uint8_t program);
|
||||
|
||||
/*@} end of group EF_CTRL_Public_Functions */
|
||||
|
||||
@ -7,7 +7,7 @@
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2022 Bouffalo Lab</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
@ -172,11 +172,11 @@ typedef enum {
|
||||
* @brief PSRAM Burst Length type definition
|
||||
*/
|
||||
typedef enum {
|
||||
PSRAM_WINBOND_BURST_LENGTH_128_BYTES, /*!< Burst Length 128 bytes */
|
||||
PSRAM_WINBOND_BURST_LENGTH_64_BYTES, /*!< Burst Length 64 bytes */
|
||||
PSRAM_WINBOND_BURST_LENGTH_16_BYTES, /*!< Burst Length 16 bytes */
|
||||
PSRAM_WINBOND_BURST_LENGTH_32_BYTES, /*!< Burst Length 32 bytes */
|
||||
PSRAM_WINBOND_BURST_LENGTH_512_BYTES, /*!< Burst Length 512 only for HyperBus3 */
|
||||
PSRAM_WINBOND_BURST_LENGTH_128_BYTES = 0x4, /*!< Burst Length 128 bytes */
|
||||
PSRAM_WINBOND_BURST_LENGTH_64_BYTES, /*!< Burst Length 64 bytes */
|
||||
PSRAM_WINBOND_BURST_LENGTH_16_BYTES, /*!< Burst Length 16 bytes */
|
||||
PSRAM_WINBOND_BURST_LENGTH_32_BYTES, /*!< Burst Length 32 bytes */
|
||||
PSRAM_WINBOND_BURST_LENGTH_512_BYTES, /*!< Burst Length 512 only for HyperBus3 */
|
||||
} PSRAM_Winbond_Burst_Length;
|
||||
|
||||
/**
|
||||
@ -302,8 +302,7 @@ typedef struct
|
||||
/** @defgroup PSRAM_ID_TYPE
|
||||
* @{
|
||||
*/
|
||||
#define IS_PSRAM_ID_TYPE(type) (((type) == PSRAM0_ID) || \
|
||||
((type) == PSRAM1_ID))
|
||||
#define IS_PSRAM_ID_TYPE(type) (((type) == PSRAM0_ID))
|
||||
|
||||
/** @defgroup PSRAM_CTRL_IO_MODE_TYPE
|
||||
* @{
|
||||
@ -466,12 +465,12 @@ typedef struct
|
||||
* @{
|
||||
*/
|
||||
void PSram_Ctrl_Init(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Cfg_Type *psramCtrlCfg);
|
||||
void PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal);
|
||||
void PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr,
|
||||
PSRAM_Winbond_Cfg_Type *reg_cfg);
|
||||
void PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal);
|
||||
void PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr,
|
||||
PSRAM_APMemory_Cfg_Type *reg_cfg);
|
||||
BL_Err_Type PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal);
|
||||
BL_Err_Type PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr,
|
||||
PSRAM_Winbond_Cfg_Type *reg_cfg);
|
||||
BL_Err_Type PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal);
|
||||
BL_Err_Type PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr,
|
||||
PSRAM_APMemory_Cfg_Type *reg_cfg);
|
||||
void PSram_Ctrl_ApMem_Reset(PSRAM_ID_Type PSRAM_ID);
|
||||
void PSram_Ctrl_CK_Sel(PSRAM_ID_Type PSRAM_ID, PSRAM_Clock_Type clkSel);
|
||||
void PSram_Ctrl_Winbond_Reset(PSRAM_ID_Type PSRAM_ID);
|
||||
|
||||
@ -937,9 +937,8 @@ struct SDH_Handle_Cfg_Tag {
|
||||
/** @defgroup SDH_Public_Functions
|
||||
* @{
|
||||
*/
|
||||
#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)
|
||||
void SDH_MMC1_IRQHandler(void);
|
||||
#endif
|
||||
|
||||
void SDH_Reset(void);
|
||||
void SDH_Set_Timeout(uint8_t tmo);
|
||||
void SDH_SetSdClock(uint32_t srcClock, uint32_t busClock);
|
||||
|
||||
@ -209,6 +209,8 @@ BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, ui
|
||||
uint32_t len);
|
||||
BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len);
|
||||
|
||||
BL_Err_Type SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *flashCfg);
|
||||
|
||||
/*@} end of group SFLAH_Public_Functions */
|
||||
|
||||
/*@} end of group SFLAH */
|
||||
|
||||
@ -88,6 +88,9 @@ BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, ui
|
||||
void XIP_SFlash_Opt_Enter(uint8_t *aesEnable);
|
||||
void XIP_SFlash_Opt_Exit(uint8_t aesEnable);
|
||||
|
||||
BL_Err_Type XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,
|
||||
uint8_t group, SF_Ctrl_Bank_Select bank);
|
||||
|
||||
/*@} end of group XIP_SFLASH_Public_Functions */
|
||||
|
||||
/*@} end of group XIP_SFLASH */
|
||||
|
||||
@ -1,5 +1,4 @@
|
||||
#include "bl616_common.h"
|
||||
#include <string.h>
|
||||
#include "bl616_glb.h"
|
||||
#include "bl616_clock.h"
|
||||
|
||||
@ -62,7 +61,6 @@
|
||||
* @return none
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
#ifdef ARCH_RISCV
|
||||
__WEAK
|
||||
void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT)
|
||||
@ -116,7 +114,6 @@ void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT)
|
||||
);
|
||||
}
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief delay us
|
||||
@ -126,14 +123,12 @@ void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT)
|
||||
* @return none
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
void ATTR_TCM_SECTION arch_delay_us(uint32_t cnt)
|
||||
{
|
||||
uint32_t coreFreq;
|
||||
uint32_t loopTick = 3;
|
||||
|
||||
#if __riscv_xtheade == 1
|
||||
#if defined(__riscv_xthead) || defined(__riscv_xtheadc)
|
||||
#if ((__ICACHE_PRESENT == 1U) && (__DCACHE_PRESENT == 1U))
|
||||
uint32_t iCacheEn;
|
||||
uint32_t dCacheEn;
|
||||
@ -174,7 +169,6 @@ void ATTR_TCM_SECTION arch_delay_us(uint32_t cnt)
|
||||
|
||||
ASM_Delay_Us(coreFreq, cnt, loopTick);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief delay ms
|
||||
@ -184,7 +178,6 @@ void ATTR_TCM_SECTION arch_delay_us(uint32_t cnt)
|
||||
* @return none
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
void ATTR_TCM_SECTION arch_delay_ms(uint32_t cnt)
|
||||
{
|
||||
@ -205,7 +198,6 @@ void ATTR_TCM_SECTION arch_delay_ms(uint32_t cnt)
|
||||
arch_delay_us(count * 1000);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef DEBUG
|
||||
/*******************************************************************************
|
||||
|
||||
@ -107,14 +107,14 @@ static Efuse_Common_Trim_Cfg trim_lit[] = {
|
||||
.value_len = 4,
|
||||
},
|
||||
{
|
||||
.name = "ldo33",
|
||||
.name = "ldo33_trim",
|
||||
.en_addr = 0x78 * 8 + 13,
|
||||
.parity_addr = 0x78 * 8 + 12,
|
||||
.value_addr = 0x78 * 8 + 8,
|
||||
.value_len = 4,
|
||||
},
|
||||
{
|
||||
.name = "ldo11",
|
||||
.name = "ldo11_tirm",
|
||||
.en_addr = 0x78 * 8 + 7,
|
||||
.parity_addr = 0x78 * 8 + 6,
|
||||
.value_addr = 0x78 * 8 + 2,
|
||||
@ -127,6 +127,90 @@ static Efuse_Common_Trim_Cfg trim_lit[] = {
|
||||
.value_addr = 0x7C * 8 + 4,
|
||||
.value_len = 8,
|
||||
},
|
||||
{
|
||||
.name = "hp_poffset0",
|
||||
.en_addr = 0xCC * 8 + 26,
|
||||
.parity_addr = 0xC0 * 8 + 15,
|
||||
.value_addr = 0xC0 * 8 + 0,
|
||||
.value_len = 15,
|
||||
},
|
||||
{
|
||||
.name = "hp_poffset1",
|
||||
.en_addr = 0xCC * 8 + 27,
|
||||
.parity_addr = 0xC0 * 8 + 31,
|
||||
.value_addr = 0xC0 * 8 + 16,
|
||||
.value_len = 15,
|
||||
},
|
||||
{
|
||||
.name = "hp_poffset2",
|
||||
.en_addr = 0xCC * 8 + 28,
|
||||
.parity_addr = 0xC4 * 8 + 15,
|
||||
.value_addr = 0xC4 * 8 + 0,
|
||||
.value_len = 15,
|
||||
},
|
||||
{
|
||||
.name = "lp_poffset0",
|
||||
.en_addr = 0xCC * 8 + 29,
|
||||
.parity_addr = 0xC4 * 8 + 31,
|
||||
.value_addr = 0xC4 * 8 + 16,
|
||||
.value_len = 15,
|
||||
},
|
||||
{
|
||||
.name = "lp_poffset1",
|
||||
.en_addr = 0xCC * 8 + 30,
|
||||
.parity_addr = 0xC8 * 8 + 15,
|
||||
.value_addr = 0xC8 * 8 + 0,
|
||||
.value_len = 15,
|
||||
},
|
||||
{
|
||||
.name = "lp_poffset2",
|
||||
.en_addr = 0xCC * 8 + 31,
|
||||
.parity_addr = 0xC8 * 8 + 31,
|
||||
.value_addr = 0xC8 * 8 + 16,
|
||||
.value_len = 15,
|
||||
},
|
||||
{
|
||||
.name = "bz_poffset0",
|
||||
.en_addr = 0xD0 * 8 + 26,
|
||||
.parity_addr = 0xCC * 8 + 25,
|
||||
.value_addr = 0xCC * 8 + 0,
|
||||
.value_len = 25,
|
||||
},
|
||||
{
|
||||
.name = "bz_poffset1",
|
||||
.en_addr = 0xD0 * 8 + 27,
|
||||
.parity_addr = 0xD0 * 8 + 25,
|
||||
.value_addr = 0xD0 * 8 + 0,
|
||||
.value_len = 25,
|
||||
},
|
||||
{
|
||||
.name = "bz_poffset2",
|
||||
.en_addr = 0xD0 * 8 + 28,
|
||||
.parity_addr = 0xD4 * 8 + 25,
|
||||
.value_addr = 0xD4 * 8 + 0,
|
||||
.value_len = 25,
|
||||
},
|
||||
{
|
||||
.name = "tmp_mp0",
|
||||
.en_addr = 0xD8 * 8 + 9,
|
||||
.parity_addr = 0xD8 * 8 + 8,
|
||||
.value_addr = 0xD8 * 8 + 0,
|
||||
.value_len = 8,
|
||||
},
|
||||
{
|
||||
.name = "tmp_mp1",
|
||||
.en_addr = 0xD8 * 8 + 19,
|
||||
.parity_addr = 0xD8 * 8 + 18,
|
||||
.value_addr = 0xD8 * 8 + 10,
|
||||
.value_len = 8,
|
||||
},
|
||||
{
|
||||
.name = "tmp_mp2",
|
||||
.en_addr = 0xD8 * 8 + 29,
|
||||
.parity_addr = 0xD8 * 8 + 28,
|
||||
.value_addr = 0xD8 * 8 + 20,
|
||||
.value_len = 8,
|
||||
},
|
||||
{
|
||||
.name = "auadc_gain",
|
||||
.en_addr = 0xDC * 8 + 25,
|
||||
@ -156,21 +240,21 @@ static Efuse_Common_Trim_Cfg trim_lit[] = {
|
||||
.value_len = 10,
|
||||
},
|
||||
{
|
||||
.name = "xtal1",
|
||||
.name = "xtal0",
|
||||
.en_addr = 0xEC * 8 + 7,
|
||||
.parity_addr = 0xEC * 8 + 6,
|
||||
.value_addr = 0xEC * 8 + 0,
|
||||
.value_len = 6,
|
||||
},
|
||||
{
|
||||
.name = "xtal2",
|
||||
.name = "xtal1",
|
||||
.en_addr = 0xF0 * 8 + 31,
|
||||
.parity_addr = 0xF0 * 8 + 30,
|
||||
.value_addr = 0xF4 * 8 + 26,
|
||||
.value_len = 6,
|
||||
},
|
||||
{
|
||||
.name = "xtal3",
|
||||
.name = "xtal2",
|
||||
.en_addr = 0xF0 * 8 + 29,
|
||||
.parity_addr = 0xF0 * 8 + 28,
|
||||
.value_addr = 0xF4 * 8 + 20,
|
||||
@ -298,17 +382,19 @@ uint32_t EF_Ctrl_Get_Common_Trim_List(Efuse_Common_Trim_Cfg **trim_list)
|
||||
*
|
||||
* @param name: Trim name
|
||||
* @param trim: Trim data pointer
|
||||
*
|
||||
* @param reload: Reload efuse data before read
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void EF_Ctrl_Read_Common_Trim(char *name, Efuse_Common_Trim_Type *trim)
|
||||
void EF_Ctrl_Read_Common_Trim(char *name, Efuse_Common_Trim_Type *trim, uint8_t reload)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
uint32_t i = 0;
|
||||
|
||||
/* Trigger read data from efuse */
|
||||
EF_CTRL_LOAD_BEFORE_READ_R0;
|
||||
if (reload) {
|
||||
/* Trigger read data from efuse */
|
||||
EF_CTRL_LOAD_BEFORE_READ_R0;
|
||||
}
|
||||
|
||||
trim->en = 0;
|
||||
trim->parity = 0;
|
||||
@ -363,7 +449,6 @@ void EF_Ctrl_Write_Common_Trim(char *name, uint32_t value, uint8_t program)
|
||||
tmpVal |= (1 << (trim_lit[i].en_addr % 32));
|
||||
BL_WR_WORD(EF_DATA_BASE + (trim_lit[i].en_addr / 32) * 4, tmpVal);
|
||||
|
||||
|
||||
parity = EF_Ctrl_Get_Trim_Parity(value, trim_lit[i].value_len);
|
||||
if (parity) {
|
||||
tmpVal = BL_RD_WORD(EF_DATA_BASE + (trim_lit[i].parity_addr / 32) * 4);
|
||||
|
||||
388
drivers/soc/bl616/bl616_std/src/bl616_l1c.c
Normal file
388
drivers/soc/bl616/bl616_std/src/bl616_l1c.c
Normal file
@ -0,0 +1,388 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file bl616_l1c.c
|
||||
* @version V1.0
|
||||
* @date
|
||||
* @brief This file is the standard driver c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright notice,
|
||||
* this list of conditions and the following disclaimer in the documentation
|
||||
* and/or other materials provided with the distribution.
|
||||
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
|
||||
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
|
||||
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
|
||||
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
|
||||
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
|
||||
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
******************************************************************************
|
||||
*/
|
||||
|
||||
#include "bl616_l1c.h"
|
||||
#include "bl616_common.h"
|
||||
// #include "bl616_glb.h"
|
||||
|
||||
/** @addtogroup BL616_Peripheral_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @addtogroup L1C
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** @defgroup L1C_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group L1C_Private_Macros */
|
||||
|
||||
/** @defgroup L1C_Private_Types
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group L1C_Private_Types */
|
||||
|
||||
/** @defgroup L1C_Private_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group L1C_Private_Variables */
|
||||
|
||||
/** @defgroup L1C_Global_Variables
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group L1C_Global_Variables */
|
||||
|
||||
/** @defgroup L1C_Private_Fun_Declaration
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group L1C_Private_Fun_Declaration */
|
||||
|
||||
/** @defgroup L1C_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*@} end of group L1C_Private_Functions */
|
||||
|
||||
/** @defgroup L1C_Public_Functions
|
||||
* @{
|
||||
*/
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Enable I-Cache
|
||||
*
|
||||
* @param wayDsiable: cache way disable config
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Enable(uint8_t wayDsiable)
|
||||
{
|
||||
#ifndef __riscv_32e
|
||||
csi_icache_enable();
|
||||
#endif
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Enable D-Cache
|
||||
*
|
||||
* @param wayDsiable: cache way disable config
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Enable(uint8_t wayDsiable)
|
||||
{
|
||||
#ifndef __riscv_32e
|
||||
csi_dcache_enable();
|
||||
#endif
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Disable I-Cache
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Disable(void)
|
||||
{
|
||||
#ifndef __riscv_32e
|
||||
csi_icache_disable();
|
||||
#endif
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Disable D-Cache
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Disable(void)
|
||||
{
|
||||
#ifndef __riscv_32e
|
||||
csi_dcache_disable();
|
||||
#endif
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief L1C D-Cache write set
|
||||
*
|
||||
* @param wtEn: L1C write through enable
|
||||
* @param wbEn: L1C write back enable
|
||||
* @param waEn: L1C write allocate enable
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
void ATTR_TCM_SECTION L1C_DCache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Clean all D_Cache
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_All(void)
|
||||
{
|
||||
#ifndef __riscv_32e
|
||||
csi_dcache_clean();
|
||||
#endif
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Clean and invalid all D_Cache
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_Invalid_All(void)
|
||||
{
|
||||
#ifndef __riscv_32e
|
||||
csi_dcache_clean_invalid();
|
||||
#endif
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Invalid all I-Cache
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Invalid_All(void)
|
||||
{
|
||||
#ifndef __riscv_32e
|
||||
csi_icache_invalid();
|
||||
#endif
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Invalid all D_Cache
|
||||
*
|
||||
* @param None
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Invalid_All(void)
|
||||
{
|
||||
#ifndef __riscv_32e
|
||||
csi_dcache_invalid();
|
||||
#endif
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Clean D-Cache according to address
|
||||
*
|
||||
* @param addr: Address to clean
|
||||
* @param len: Length to clean
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_By_Addr(uintptr_t addr, uint32_t len)
|
||||
{
|
||||
#ifndef __riscv_32e
|
||||
#ifdef CPU_D0
|
||||
csi_dcache_clean_range((uintptr_t *)addr, len);
|
||||
#else
|
||||
csi_dcache_clean_range((uint32_t *)(uintptr_t *)addr, len);
|
||||
#endif
|
||||
#endif
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Clean and invalid D-Cache according to address
|
||||
*
|
||||
* @param addr: Address to clean
|
||||
* @param len: Length to clean
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_Invalid_By_Addr(uintptr_t addr, uint32_t len)
|
||||
{
|
||||
#ifndef __riscv_32e
|
||||
#ifdef CPU_D0
|
||||
csi_dcache_clean_invalid_range((uintptr_t *)addr, len);
|
||||
#else
|
||||
csi_dcache_clean_invalid_range((uint32_t *)(uintptr_t *)addr, len);
|
||||
#endif
|
||||
#endif
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Invalid I-Cache according to address
|
||||
*
|
||||
* @param addr: Address to clean
|
||||
* @param len: Length to clean
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Invalid_By_Addr(uintptr_t addr, uint32_t len)
|
||||
{
|
||||
L1C_ICache_Invalid_All();
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Invalid D-Cache according to address
|
||||
*
|
||||
* @param addr: Address to clean
|
||||
* @param len: Length to clean
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Invalid_By_Addr(uintptr_t addr, uint32_t len)
|
||||
{
|
||||
#ifndef __riscv_32e
|
||||
#ifdef CPU_D0
|
||||
csi_dcache_invalid_range((uintptr_t *)addr, len);
|
||||
#else
|
||||
csi_dcache_invalid_range((uint32_t *)(uintptr_t *)addr, len);
|
||||
#endif
|
||||
#endif
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief cache wrap
|
||||
*
|
||||
* @param en: wrap enable or disable
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(uint8_t en)
|
||||
{
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief cache wrap
|
||||
*
|
||||
* @param core: cpu core
|
||||
* @param cacheSetting: cache setting
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_Set_Cache_Setting_By_ID(uint8_t core, L1C_CACHE_Cfg_Type *cacheSetting)
|
||||
{
|
||||
(void)core;
|
||||
(void)cacheSetting;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Judge addr is in cache range
|
||||
*
|
||||
* @param addr: phyical addr
|
||||
*
|
||||
* @return 1 for addr is in cache range and 0 for not in cache range
|
||||
*
|
||||
*******************************************************************************/
|
||||
int ATTR_TCM_SECTION L1C_Is_DCache_Range(uintptr_t addr)
|
||||
{
|
||||
if(((addr>>16)&0xffff)>=0x62FC){
|
||||
return 1;
|
||||
}else{
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Get None Cache address according to Cache address
|
||||
*
|
||||
* @param addr: cache addr
|
||||
*
|
||||
* @return none cache addr
|
||||
*
|
||||
*******************************************************************************/
|
||||
int ATTR_TCM_SECTION L1C_Get_None_Cache_Addr(uintptr_t addr)
|
||||
{
|
||||
return (addr&0x0FFFFFFF)|0x20000000;
|
||||
}
|
||||
|
||||
/*@} end of group L1C_Public_Functions */
|
||||
|
||||
/*@} end of group L1C */
|
||||
|
||||
/*@} end of group BL616_Peripheral_Driver */
|
||||
@ -1,13 +1,13 @@
|
||||
/**
|
||||
******************************************************************************
|
||||
* @file bl616p_psram_ctrl.c
|
||||
* @file bl616_psram_ctrl.c
|
||||
* @version V1.0
|
||||
* @date
|
||||
* @brief This file is the standard driver c file
|
||||
******************************************************************************
|
||||
* @attention
|
||||
*
|
||||
* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
|
||||
* <h2><center>© COPYRIGHT(c) 2022 Bouffalo Lab</center></h2>
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
@ -37,7 +37,7 @@
|
||||
#include "bl616_psram.h"
|
||||
#include "psram_reg.h"
|
||||
|
||||
/** @addtogroup BL616P_Peripheral_Driver
|
||||
/** @addtogroup BL616_Peripheral_Driver
|
||||
* @{
|
||||
*/
|
||||
|
||||
@ -48,7 +48,7 @@
|
||||
/** @defgroup PSRAM_CTRL_Private_Macros
|
||||
* @{
|
||||
*/
|
||||
|
||||
#define PSRAM_X8_CTRL_WAIT_TIMEOUT 1000
|
||||
/*@} end of group PSRAM_CTRL_Private_Macros */
|
||||
|
||||
/** @defgroup PSRAM_CTRL_Private_Types
|
||||
@ -141,6 +141,7 @@ static void PSram_Ctrl_Request(PSRAM_ID_Type PSRAM_ID)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
|
||||
uint32_t time_out = 0;
|
||||
|
||||
//start configure request
|
||||
tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
|
||||
@ -150,6 +151,9 @@ static void PSram_Ctrl_Request(PSRAM_ID_Type PSRAM_ID)
|
||||
//Waiting for the authorization
|
||||
do {
|
||||
tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
|
||||
if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
|
||||
break;
|
||||
}
|
||||
} while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_REG_CONFIG_GNT));
|
||||
}
|
||||
|
||||
@ -179,13 +183,14 @@ static void PSram_Ctrl_Release(PSRAM_ID_Type PSRAM_ID)
|
||||
* @param reg_addr: PSRAM Register ID CR0 or CR1
|
||||
* @param regVal: read Reister value
|
||||
*
|
||||
* @return None
|
||||
* @return SUCCESS or TIMEOUT
|
||||
*
|
||||
*******************************************************************************/
|
||||
void PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal)
|
||||
BL_Err_Type PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
|
||||
uint32_t time_out = 0;
|
||||
|
||||
CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));
|
||||
CHECK_PARAM(IS_PSRAM_CTRL_WINBOND_CFG_REG_TYPE(reg_addr));
|
||||
@ -206,6 +211,9 @@ void PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_
|
||||
//waiting confiure complete
|
||||
do {
|
||||
tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
|
||||
if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
|
||||
return TIMEOUT;
|
||||
}
|
||||
} while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_R_DONE));
|
||||
|
||||
//read reg data form sts_config_read
|
||||
@ -213,6 +221,8 @@ void PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_
|
||||
*regVal = (uint16_t)(tmpVal >> 16);
|
||||
|
||||
PSram_Ctrl_Release(PSRAM_ID);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
@ -222,14 +232,15 @@ void PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_
|
||||
* @param reg_addr: PSRAM Register ID CR0 or CR1
|
||||
* @param reg_cfg: winbond configuration
|
||||
*
|
||||
* @return None
|
||||
* @return SUCCESS or TIMEOUT
|
||||
*
|
||||
*******************************************************************************/
|
||||
void PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, PSRAM_Winbond_Cfg_Type *reg_cfg)
|
||||
BL_Err_Type PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, PSRAM_Winbond_Cfg_Type *reg_cfg)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
|
||||
PSRAM_Ctrl_Size_Type psramDensity;
|
||||
uint32_t time_out = 0;
|
||||
|
||||
CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));
|
||||
CHECK_PARAM(IS_PSRAM_CTRL_WINBOND_CFG_REG_TYPE(reg_addr));
|
||||
@ -279,9 +290,14 @@ void PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg
|
||||
//waiting confiure complete
|
||||
do {
|
||||
tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
|
||||
if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
|
||||
return TIMEOUT;
|
||||
}
|
||||
} while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_W_DONE));
|
||||
|
||||
PSram_Ctrl_Release(PSRAM_ID);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
@ -291,13 +307,14 @@ void PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg
|
||||
* @param reg_addr: PSRAM Register ID CR0 or CR1
|
||||
* @param regVal: read Reister value
|
||||
*
|
||||
* @return None
|
||||
* @return SUCCESS or TIMEOUT
|
||||
*
|
||||
*******************************************************************************/
|
||||
void PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal)
|
||||
BL_Err_Type PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
|
||||
uint32_t time_out = 0;
|
||||
|
||||
CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));
|
||||
CHECK_PARAM(IS_PSRAM_CTRL_APMEM_CFG_REG_TYPE(reg_addr));
|
||||
@ -318,6 +335,9 @@ void PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_
|
||||
//waiting confiure complete
|
||||
do {
|
||||
tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
|
||||
if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
|
||||
return TIMEOUT;
|
||||
}
|
||||
} while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_R_DONE));
|
||||
|
||||
//read reg data form sts_config_read
|
||||
@ -325,6 +345,8 @@ void PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_
|
||||
*regVal = (uint16_t)(tmpVal >> 16);
|
||||
|
||||
PSram_Ctrl_Release(PSRAM_ID);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
@ -334,13 +356,14 @@ void PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_
|
||||
* @param reg_addr: PSRAM Register ID
|
||||
* @param reg_cfg: winbond configuration
|
||||
*
|
||||
* @return None
|
||||
* @return SUCCESS or TIMEOUT
|
||||
*
|
||||
*******************************************************************************/
|
||||
void PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, PSRAM_APMemory_Cfg_Type *reg_cfg)
|
||||
BL_Err_Type PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, PSRAM_APMemory_Cfg_Type *reg_cfg)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
|
||||
uint32_t time_out = 0;
|
||||
|
||||
CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));
|
||||
CHECK_PARAM(IS_PSRAM_CTRL_APMEM_CFG_REG_TYPE(reg_addr));
|
||||
@ -378,9 +401,14 @@ void PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg
|
||||
//waiting confiure complete
|
||||
do {
|
||||
tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
|
||||
if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
|
||||
return TIMEOUT;
|
||||
}
|
||||
} while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_W_DONE));
|
||||
|
||||
PSram_Ctrl_Release(PSRAM_ID);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
@ -528,4 +556,4 @@ void PSram_Ctrl_Debug_Timout(PSRAM_ID_Type PSRAM_ID, uint8_t enable, uint32_t ti
|
||||
|
||||
/*@} end of group PSRAM_CTRL */
|
||||
|
||||
/*@} end of group BL616P_Peripheral_Driver */
|
||||
/*@} end of group BL616_Peripheral_Driver */
|
||||
|
||||
@ -246,6 +246,7 @@ void EF_Ctrl_Load_Efuse_R0(void){
|
||||
return RomDriver_EF_Ctrl_Load_Efuse_R0();
|
||||
}
|
||||
|
||||
#if 0
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len){
|
||||
return RomDriver_EF_Ctrl_Program_Direct_R0(index,data,len);
|
||||
@ -255,6 +256,7 @@ __ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
void EF_Ctrl_Program_Efuse_0(void){
|
||||
return RomDriver_EF_Ctrl_Program_Efuse_0();
|
||||
}
|
||||
#endif
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
void EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim){
|
||||
@ -293,10 +295,12 @@ void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo){
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len){
|
||||
return RomDriver_EF_Ctrl_Read_Direct_R0(index,data,len);
|
||||
}
|
||||
#endif
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
void EF_Ctrl_Read_Ldo11socVoutTrim_Trim(Efuse_Ana_Ldo11socVoutTrim_Type *trim){
|
||||
@ -672,6 +676,13 @@ BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel){
|
||||
return RomDriver_GLB_Set_ETH_REF_O_CLK_Sel(clkSel);
|
||||
}
|
||||
|
||||
#if 0
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type GLB_Set_PEC_CLK(uint8_t enable, GLB_PEC_CLK_Type clkSel, uint8_t div){
|
||||
return RomDriver_GLB_Set_PEC_CLK(enable,clkSel,div);
|
||||
}
|
||||
#endif
|
||||
|
||||
#if 0
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_Type clkSel, uint8_t div){
|
||||
@ -2071,187 +2082,6 @@ void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg){
|
||||
return RomDriver_SFlash_Volatile_Reg_Write_Enable(flashCfg);
|
||||
}
|
||||
|
||||
/*
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud){
|
||||
return RomDriver_UART_AutoBaudDetection(uartId,autoBaud);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId){
|
||||
return RomDriver_UART_ClrRtsValue(uartId);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId){
|
||||
return RomDriver_UART_ClrTxValue(uartId);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_DeInit(UART_ID_Type uartId){
|
||||
return RomDriver_UART_DeInit(uartId);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct){
|
||||
return RomDriver_UART_Disable(uartId,direct);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct){
|
||||
return RomDriver_UART_Enable(uartId,direct);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg){
|
||||
return RomDriver_UART_FifoConfig(uartId,fifoCfg);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_GetBitWidth0X55(UART_ID_Type uartId, uint16_t *width){
|
||||
return RomDriver_UART_GetBitWidth0X55(uartId,width);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg){
|
||||
return RomDriver_UART_Init(uartId,uartCfg);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType){
|
||||
return RomDriver_UART_IntClear(uartId,intType);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask){
|
||||
return RomDriver_UART_IntMask(uartId,intType,intMask);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg){
|
||||
return RomDriver_UART_IrConfig(uartId,irCfg);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId){
|
||||
return RomDriver_UART_RxFifoClear(uartId);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len){
|
||||
return RomDriver_UART_SendData(uartId,data,len);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len){
|
||||
return RomDriver_UART_SendDataBlock(uartId,data,len);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_SetAllowableError0X55(UART_ID_Type uartId, uint8_t allowableError){
|
||||
return RomDriver_UART_SetAllowableError0X55(uartId,allowableError);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet){
|
||||
return RomDriver_UART_SetBaudrate(uartId,autoBaudDet);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt){
|
||||
return RomDriver_UART_SetDeglitchCount(uartId,deglitchCnt);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_SetRS485(UART_ID_Type uartId, BL_Fun_Type enable, UART_RS485Polarity_Type polarity){
|
||||
return RomDriver_UART_SetRS485(uartId,enable,polarity);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId){
|
||||
return RomDriver_UART_SetRtsValue(uartId);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_SetRxByteCount(UART_ID_Type uartId, uint16_t count){
|
||||
return RomDriver_UART_SetRxByteCount(uartId,count);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length){
|
||||
return RomDriver_UART_SetRxDataLength(uartId,length);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time){
|
||||
return RomDriver_UART_SetRxTimeoutValue(uartId,time);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length){
|
||||
return RomDriver_UART_SetTxDataLength(uartId,length);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_SetTxValue(UART_ID_Type uartId){
|
||||
return RomDriver_UART_SetTxValue(uartId);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId){
|
||||
return RomDriver_UART_TxFifoClear(uartId);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun){
|
||||
return RomDriver_UART_TxFreeRun(uartId,txFreeRun);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType){
|
||||
return RomDriver_UART_GetIntStatus(uartId,intType);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow){
|
||||
return RomDriver_UART_GetOverflowStatus(uartId,overflow);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId){
|
||||
return RomDriver_UART_GetRxBusBusyStatus(uartId);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId){
|
||||
return RomDriver_UART_GetTxBusBusyStatus(uartId);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet){
|
||||
return RomDriver_UART_GetAutoBaudCount(uartId,autoBaudDet);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
uint16_t UART_GetRxByteCount(UART_ID_Type uartId){
|
||||
return RomDriver_UART_GetRxByteCount(uartId);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen){
|
||||
return RomDriver_UART_ReceiveData(uartId,data,maxLen);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
uint8_t UART_GetRxFifoCount(UART_ID_Type uartId){
|
||||
return RomDriver_UART_GetRxFifoCount(uartId);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
uint8_t UART_GetTxFifoCount(UART_ID_Type uartId){
|
||||
return RomDriver_UART_GetTxFifoCount(uartId);
|
||||
}
|
||||
*/
|
||||
#if 0
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, uint8_t group, SF_Ctrl_Bank_Select bank){
|
||||
|
||||
@ -36,7 +36,7 @@
|
||||
|
||||
#include "bl616_romapi_patch.h"
|
||||
#include "bl616_romdriver_e907.h"
|
||||
// #include "softcrc.h"
|
||||
#include "soft_crc.h"
|
||||
|
||||
/* WiFi PLL Config*/
|
||||
const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_32M_38P4M_40M = {
|
||||
@ -199,7 +199,7 @@ const GLB_SLAVE_GRP_0_TBL_Type ATTR_CLOCK_CONST_SECTION glb_slave_grp_0_table[GL
|
||||
{ GLB_IR_CFG0_OFFSET, GLB_IR_CLK_EN_POS, 0, GLB_IR_CLK_DIV_POS, GLB_IR_CLK_EN_LEN, 0, GLB_IR_CLK_DIV_LEN },
|
||||
{ GLB_I2C_CFG0_OFFSET, GLB_I2C_CLK_EN_POS, GLB_I2C_CLK_SEL_POS, GLB_I2C_CLK_DIV_POS, GLB_I2C_CLK_EN_LEN, GLB_I2C_CLK_SEL_LEN, GLB_I2C_CLK_DIV_LEN },
|
||||
{ GLB_SPI_CFG0_OFFSET, GLB_SPI_CLK_EN_POS, GLB_SPI_CLK_SEL_POS, GLB_SPI_CLK_DIV_POS, GLB_SPI_CLK_EN_LEN, GLB_SPI_CLK_SEL_LEN, GLB_SPI_CLK_DIV_LEN },
|
||||
{ 0, 0, 0, 0, 0, 0, 0 },
|
||||
{ GLB_PEC_CFG0_OFFSET, GLB_PEC_CLK_EN_POS, GLB_PEC_CLK_SEL_POS, GLB_PEC_CLK_DIV_POS, GLB_PEC_CLK_EN_LEN, GLB_PEC_CLK_SEL_LEN, GLB_PEC_CLK_DIV_LEN },
|
||||
{ GLB_DBI_CFG0_OFFSET, GLB_DBI_CLK_EN_POS, GLB_DBI_CLK_SEL_POS, GLB_DBI_CLK_DIV_POS, GLB_DBI_CLK_EN_LEN, GLB_DBI_CLK_SEL_LEN, GLB_DBI_CLK_DIV_LEN },
|
||||
{ GLB_AUDIO_CFG0_OFFSET, GLB_REG_AUDIO_AUTO_DIV_EN_POS, 0, 0, GLB_REG_AUDIO_AUTO_DIV_EN_LEN, 0, 0 },
|
||||
{ GLB_AUDIO_CFG0_OFFSET, GLB_REG_AUDIO_ADC_CLK_EN_POS, 0, GLB_REG_AUDIO_ADC_CLK_DIV_POS, GLB_REG_AUDIO_ADC_CLK_EN_LEN, 0, GLB_REG_AUDIO_ADC_CLK_DIV_LEN },
|
||||
@ -209,11 +209,6 @@ const GLB_SLAVE_GRP_0_TBL_Type ATTR_CLOCK_CONST_SECTION glb_slave_grp_0_table[GL
|
||||
{ GLB_PSRAM_CFG0_OFFSET, GLB_REG_PSRAMB_CLK_EN_POS, GLB_REG_PSRAMB_CLK_SEL_POS, GLB_REG_PSRAMB_CLK_DIV_POS, GLB_REG_PSRAMB_CLK_EN_LEN, GLB_REG_PSRAMB_CLK_SEL_LEN, GLB_REG_PSRAMB_CLK_DIV_LEN },
|
||||
};
|
||||
|
||||
// static const uint32_t uartAddr[UART_ID_MAX] = { UART0_BASE, UART1_BASE };
|
||||
// static intCallback_Type *uartIntCbfArra[UART_ID_MAX][UART_INT_ALL] = {
|
||||
// { NULL }
|
||||
// };
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint32_t jedecID;
|
||||
@ -907,186 +902,6 @@ static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = {
|
||||
},
|
||||
};
|
||||
|
||||
//UART
|
||||
// static void UART_IntHandler(UART_ID_Type uartId)
|
||||
// {
|
||||
// uint32_t tmpVal = 0;
|
||||
// uint32_t maskVal = 0;
|
||||
// uint32_t UARTx = uartAddr[uartId];
|
||||
|
||||
// tmpVal = BL_RD_REG(UARTx, UART_INT_STS);
|
||||
// maskVal = BL_RD_REG(UARTx, UART_INT_MASK);
|
||||
|
||||
// /* Length of uart tx data transfer arrived interrupt */
|
||||
// if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) {
|
||||
// BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_UTX_END_CLR_POS);
|
||||
|
||||
// if (uartIntCbfArra[uartId][UART_INT_TX_END] != NULL) {
|
||||
// uartIntCbfArra[uartId][UART_INT_TX_END]();
|
||||
// }
|
||||
// }
|
||||
|
||||
// /* Length of uart rx data transfer arrived interrupt */
|
||||
// if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) {
|
||||
// BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_END_CLR_POS);
|
||||
|
||||
// if (uartIntCbfArra[uartId][UART_INT_RX_END] != NULL) {
|
||||
// uartIntCbfArra[uartId][UART_INT_RX_END]();
|
||||
// }
|
||||
// }
|
||||
|
||||
// /* Tx fifo ready interrupt,auto-cleared when data is pushed */
|
||||
// if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FRDY_MASK)) {
|
||||
// if (uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ] != NULL) {
|
||||
// uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ]();
|
||||
// }
|
||||
// }
|
||||
|
||||
// /* Rx fifo ready interrupt,auto-cleared when data is popped */
|
||||
// if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FRDY_MASK)) {
|
||||
// if (uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ] != NULL) {
|
||||
// uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ]();
|
||||
// }
|
||||
// }
|
||||
|
||||
// /* Rx time-out interrupt */
|
||||
// if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) {
|
||||
// BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_RTO_CLR_POS);
|
||||
|
||||
// if (uartIntCbfArra[uartId][UART_INT_RTO] != NULL) {
|
||||
// uartIntCbfArra[uartId][UART_INT_RTO]();
|
||||
// }
|
||||
// }
|
||||
|
||||
// /* Rx parity check error interrupt */
|
||||
// if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) {
|
||||
// BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_PCE_CLR_POS);
|
||||
|
||||
// if (uartIntCbfArra[uartId][UART_INT_PCE] != NULL) {
|
||||
// uartIntCbfArra[uartId][UART_INT_PCE]();
|
||||
// }
|
||||
// }
|
||||
|
||||
// /* Tx fifo overflow/underflow error interrupt */
|
||||
// if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) {
|
||||
// if (uartIntCbfArra[uartId][UART_INT_TX_FER] != NULL) {
|
||||
// uartIntCbfArra[uartId][UART_INT_TX_FER]();
|
||||
// }
|
||||
// }
|
||||
|
||||
// /* Rx fifo overflow/underflow error interrupt */
|
||||
// if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) {
|
||||
// if (uartIntCbfArra[uartId][UART_INT_RX_FER] != NULL) {
|
||||
// uartIntCbfArra[uartId][UART_INT_RX_FER]();
|
||||
// }
|
||||
// }
|
||||
|
||||
// /* Rx lin mode sync field error interrupt */
|
||||
// if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_LSE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_LSE_MASK)) {
|
||||
// BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_LSE_CLR_POS);
|
||||
|
||||
// if (uartIntCbfArra[uartId][UART_INT_LSE] != NULL) {
|
||||
// uartIntCbfArra[uartId][UART_INT_LSE]();
|
||||
// }
|
||||
// }
|
||||
|
||||
// /* Rx byte count reached interrupt */
|
||||
// if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_BCR_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_BCR_MASK)) {
|
||||
// BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_BCR_CLR_POS);
|
||||
|
||||
// if (uartIntCbfArra[uartId][UART_INT_BCR] != NULL) {
|
||||
// uartIntCbfArra[uartId][UART_INT_BCR]();
|
||||
// }
|
||||
// }
|
||||
|
||||
// /* Rx auto baud rate detection finish interrupt using start bit */
|
||||
// if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_ADS_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_ADS_MASK)) {
|
||||
// BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_ADS_CLR_POS);
|
||||
|
||||
// if (uartIntCbfArra[uartId][UART_INT_STARTBIT] != NULL) {
|
||||
// uartIntCbfArra[uartId][UART_INT_STARTBIT]();
|
||||
// }
|
||||
// }
|
||||
|
||||
// /* Rx auto baud rate detection finish interrupt using codeword 0x55 */
|
||||
// if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_AD5_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_AD5_MASK)) {
|
||||
// BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_AD5_CLR_POS);
|
||||
|
||||
// if (uartIntCbfArra[uartId][UART_INT_0X55] != NULL) {
|
||||
// uartIntCbfArra[uartId][UART_INT_0X55]();
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
|
||||
// #if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)
|
||||
// void UART1_IRQHandler(void)
|
||||
// {
|
||||
// UART_IntHandler(UART1_ID);
|
||||
// }
|
||||
// #endif
|
||||
|
||||
// /****************************************************************************/ /**
|
||||
// * @brief Install uart interrupt callback function
|
||||
// *
|
||||
// * @param uartId: UART ID type
|
||||
// * @param intType: UART interrupt type
|
||||
// * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
|
||||
// *
|
||||
// * @return SUCCESS
|
||||
// *
|
||||
// *******************************************************************************/
|
||||
// BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun)
|
||||
// {
|
||||
// /* Check the parameters */
|
||||
// CHECK_PARAM(IS_UART_ID_TYPE(uartId));
|
||||
// CHECK_PARAM(IS_UART_INT_TYPE(intType));
|
||||
|
||||
// uartIntCbfArra[uartId][intType] = cbFun;
|
||||
|
||||
// return SUCCESS;
|
||||
// }
|
||||
|
||||
// /****************************************************************************/ /**
|
||||
// * @brief UART set baud rate function
|
||||
// *
|
||||
// * @param uartId: UART ID type
|
||||
// * @param baudRate: baudRate need to set
|
||||
// *
|
||||
// * @return SUCCESS or ERROR
|
||||
// *
|
||||
// *******************************************************************************/
|
||||
// BL_Err_Type UART_SetBaudRate(UART_ID_Type uartId, uint32_t baudRate)
|
||||
// {
|
||||
// uint32_t uartClk = 0;
|
||||
// uint32_t fraction = 0;
|
||||
// uint32_t baudRateDivisor = 0;
|
||||
// uint32_t UARTx = uartAddr[uartId];
|
||||
|
||||
// /* Check the parameters */
|
||||
// CHECK_PARAM(IS_UART_ID_TYPE(uartId));
|
||||
|
||||
// /* Get uart clk */
|
||||
// if (uartId == UART0_ID || uartId == UART1_ID) {
|
||||
// uartClk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0);
|
||||
// } else {
|
||||
// return ERROR;
|
||||
// }
|
||||
|
||||
// /* Cal the baud rate divisor */
|
||||
// fraction = uartClk * 10 / baudRate % 10;
|
||||
// baudRateDivisor = uartClk / baudRate;
|
||||
|
||||
// if (fraction >= 5) {
|
||||
// ++baudRateDivisor;
|
||||
// }
|
||||
|
||||
// /* Set the baud rate register value */
|
||||
// BL_WR_REG(UARTx, UART_BIT_PRD, ((baudRateDivisor - 1) << 0x10) | ((baudRateDivisor - 1) & 0xFFFF));
|
||||
|
||||
// return SUCCESS;
|
||||
// }
|
||||
|
||||
|
||||
//CLOCK
|
||||
//EFUSE
|
||||
//PDS
|
||||
@ -1197,6 +1012,64 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Clear flash status register
|
||||
*
|
||||
* @param flashCfg: Flash configuration pointer
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_TCM_SECTION SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *flashCfg)
|
||||
{
|
||||
uint32_t ret = 0;
|
||||
uint32_t qeValue = 0;
|
||||
uint32_t regValue = 0;
|
||||
uint32_t readValue = 0;
|
||||
uint8_t readRegValue0 = 0;
|
||||
uint8_t readRegValue1 = 0;
|
||||
|
||||
if((flashCfg->ioMode&0xf)==SF_CTRL_QO_MODE || (flashCfg->ioMode&0xf)==SF_CTRL_QIO_MODE){
|
||||
qeValue = 1;
|
||||
}
|
||||
|
||||
SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&readRegValue0, 1);
|
||||
SFlash_Read_Reg(flashCfg, 1, (uint8_t *)&readRegValue1, 1);
|
||||
readValue = (readRegValue0|(readRegValue1<<8));
|
||||
if ((readValue & (~((1<<(flashCfg->qeIndex*8+flashCfg->qeBit)) |
|
||||
(1<<(flashCfg->busyIndex*8+flashCfg->busyBit)) |
|
||||
(1<<(flashCfg->wrEnableIndex*8+flashCfg->wrEnableBit))))) == 0){
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
ret = SFlash_Write_Enable(flashCfg);
|
||||
if (SUCCESS != ret) {
|
||||
return ERROR;
|
||||
}
|
||||
if (flashCfg->qeWriteRegLen == 2) {
|
||||
regValue = (qeValue<<(flashCfg->qeIndex*8+flashCfg->qeBit));
|
||||
SFlash_Write_Reg(flashCfg, 0, (uint8_t *)®Value, 2);
|
||||
} else {
|
||||
if (flashCfg->qeIndex == 0) {
|
||||
regValue = (qeValue<<flashCfg->qeBit);
|
||||
} else {
|
||||
regValue = 0;
|
||||
}
|
||||
SFlash_Write_Reg(flashCfg, 0, (uint8_t *)®Value, 1);
|
||||
ret = SFlash_Write_Enable(flashCfg);
|
||||
if (SUCCESS != ret) {
|
||||
return ERROR;
|
||||
}
|
||||
if (flashCfg->qeIndex == 1) {
|
||||
regValue = (qeValue<<flashCfg->qeBit);
|
||||
} else {
|
||||
regValue = 0;
|
||||
}
|
||||
SFlash_Write_Reg(flashCfg, 1, (uint8_t *)®Value, 1);
|
||||
}
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Get flash config according to flash ID patch
|
||||
*
|
||||
@ -1206,43 +1079,43 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
// BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg)
|
||||
// {
|
||||
// uint32_t i;
|
||||
// uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8];
|
||||
// uint32_t crc, *pCrc;
|
||||
// uint32_t xipOffset;
|
||||
// char flashCfgMagic[] = "FCFG";
|
||||
BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg)
|
||||
{
|
||||
uint32_t i;
|
||||
uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8];
|
||||
uint32_t crc, *pCrc;
|
||||
uint32_t xipOffset;
|
||||
char flashCfgMagic[] = "FCFG";
|
||||
|
||||
// if (flashID == 0) {
|
||||
// xipOffset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0);
|
||||
// SF_Ctrl_Set_Flash_Image_Offset(0, 0, SF_CTRL_FLASH_BANK0);
|
||||
// XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL616_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8);
|
||||
// SF_Ctrl_Set_Flash_Image_Offset(xipOffset, 0, SF_CTRL_FLASH_BANK0);
|
||||
if (flashID == 0) {
|
||||
xipOffset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0);
|
||||
SF_Ctrl_Set_Flash_Image_Offset(0, 0, SF_CTRL_FLASH_BANK0);
|
||||
XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL616_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8);
|
||||
SF_Ctrl_Set_Flash_Image_Offset(xipOffset, 0, SF_CTRL_FLASH_BANK0);
|
||||
|
||||
// if (ARCH_MemCmp(buf, flashCfgMagic, 4) == 0) {
|
||||
// crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
|
||||
// pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type));
|
||||
if (ARCH_MemCmp(buf, flashCfgMagic, 4) == 0) {
|
||||
crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
|
||||
pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type));
|
||||
|
||||
// if (*pCrc == crc) {
|
||||
// ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
|
||||
// return SUCCESS;
|
||||
// }
|
||||
// }
|
||||
// } else {
|
||||
// if (RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg) == SUCCESS) {
|
||||
// return SUCCESS;
|
||||
// }
|
||||
// for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
|
||||
// if (flashInfos[i].jedecID == flashID) {
|
||||
// ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
|
||||
// return SUCCESS;
|
||||
// }
|
||||
// }
|
||||
// }
|
||||
if (*pCrc == crc) {
|
||||
ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type));
|
||||
return SUCCESS;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
if (RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg) == SUCCESS) {
|
||||
return SUCCESS;
|
||||
}
|
||||
for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) {
|
||||
if (flashInfos[i].jedecID == flashID) {
|
||||
ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type));
|
||||
return SUCCESS;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
// return ERROR;
|
||||
// }
|
||||
return ERROR;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Identify one flash patch
|
||||
@ -1567,6 +1440,35 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Clear flash status register need lock
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param group: CPU group id 0 or 1
|
||||
* @param bank: Flash bank select
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,
|
||||
uint8_t group, SF_Ctrl_Bank_Select bank)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf;
|
||||
|
||||
stat=XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank);
|
||||
if (stat != SUCCESS) {
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank);
|
||||
} else {
|
||||
stat=SFlash_Clear_Status_Register(pFlashCfg);
|
||||
XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank);
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief reconfigure WIFIPLL clock
|
||||
*
|
||||
@ -2183,6 +2085,47 @@ BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_Type clkSel, uint8_t div
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief set PEC clock
|
||||
*
|
||||
* @param enable: Enable or disable PEC clock
|
||||
* @param clkSel: clock selection
|
||||
* @param div: divider
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type GLB_Set_PEC_CLK(uint8_t enable, GLB_PEC_CLK_Type clkSel, uint8_t div)
|
||||
{
|
||||
#ifndef BOOTROM
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
CHECK_PARAM(IS_GLB_PEC_CLK_TYPE(clkSel));
|
||||
CHECK_PARAM((div <= 0x1F));
|
||||
|
||||
tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
|
||||
tmpVal >>= 1;
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PEC_CLK_EN);
|
||||
BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal);
|
||||
|
||||
tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
|
||||
tmpVal >>= 1;
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_DIV, div);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_SEL, clkSel);
|
||||
BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal);
|
||||
|
||||
tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
|
||||
tmpVal >>= 1;
|
||||
if (enable) {
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PEC_CLK_EN);
|
||||
} else {
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PEC_CLK_EN);
|
||||
}
|
||||
BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal);
|
||||
#endif
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief set DBI clock
|
||||
*
|
||||
@ -3008,3 +2951,245 @@ BL_Err_Type HBN_Set_BOD_Cfg(HBN_BOD_CFG_Type *cfg)
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
#define GLB_CLK_SET_DUMMY_WAIT \
|
||||
{ \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
__NOP(); \
|
||||
}
|
||||
const uint32_t ATTR_CLOCK_CONST_SECTION usbPllSdmin_12M = 0x28000;
|
||||
const uint32_t ATTR_CLOCK_CONST_SECTION sscDivSdmin_24M = 0x28000;
|
||||
|
||||
void glb_40M_delay_us(uint32_t us)
|
||||
{
|
||||
for (uint32_t i = 0; i < us; i++) {
|
||||
GLB_CLK_SET_DUMMY_WAIT;
|
||||
GLB_CLK_SET_DUMMY_WAIT;
|
||||
GLB_CLK_SET_DUMMY_WAIT;
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief power on wifipll quickly
|
||||
*
|
||||
* @param xtalType: XTAL frequency type
|
||||
* @param pllType: only power on xtal
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_CLOCK_SECTION GLB_Fast_Power_On_WIFIPLL(const GLB_WA_PLL_Cfg_Type *const cfg, uint8_t waitStable)
|
||||
{
|
||||
uint32_t REG_PLL_BASE_ADDRESS = 0;
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;
|
||||
|
||||
/* Step1:config parameter */
|
||||
/* cfg1:Set wifipll_refclk_sel and wifipll_refdiv_ratio */
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
|
||||
|
||||
/* cfg2:Set wifipll_int_frac_sw,wifipll_icp_1u,wifipll_icp_5u */
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 2);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_INT_FRAC_SW, cfg->basicCfg->clkpllIntFracSw);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_ICP_1U, cfg->basicCfg->clkpllIcp1u);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_ICP_5U, cfg->basicCfg->clkpllIcp5u);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 2, tmpVal);
|
||||
|
||||
/* cfg3:Set wifipll_rz,wifipll_cz,wifipll_c3,wifipll_r4_short,wifipll_r4_en */
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 3);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_RZ, cfg->basicCfg->clkpllRz);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_CZ, cfg->basicCfg->clkpllCz);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_C3, cfg->basicCfg->clkpllC3);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_R4_SHORT, cfg->basicCfg->clkpllR4Short);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_C4_EN, cfg->basicCfg->clkpllC4En);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 3, tmpVal);
|
||||
|
||||
/* cfg4:Set wifipll_sel_sample_clk */
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal);
|
||||
|
||||
/* cfg5:Set wifipll_vco_speed */
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);
|
||||
|
||||
/* cfg6:Set wifipll_sdm_bypass,wifipll_sdmin */
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_CTRL_HW, cfg->basicCfg->clkpllSdmCtrlHw);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDMIN, cfg->clkpllSdmin);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal);
|
||||
|
||||
/* cfg10:always set usbpll_sdmin */
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 10);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USBPLL_SDMIN, usbPllSdmin_12M);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 10, tmpVal);
|
||||
|
||||
/* cfg12:always set sscdiv_sdmin */
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 12);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SSCDIV_SDMIN, sscDivSdmin_24M);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 12, tmpVal);
|
||||
|
||||
/* Step2:config pu */
|
||||
/* cfg0 : pu_wifipll_sfreg=1 */
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_WIFIPLL_SFREG, 1);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
|
||||
|
||||
/* delay > 2us */
|
||||
glb_40M_delay_us(3);
|
||||
|
||||
/* cfg0 : pu_wifipll=1 */
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_WIFIPLL, 1);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
|
||||
|
||||
/* delay > 2us */
|
||||
glb_40M_delay_us(3);
|
||||
|
||||
/* toggle sdm_reset (pulse 0 > 1us) */
|
||||
/* cfg0 : wifipll_sdm_reset */
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_RSTB, 1);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
|
||||
glb_40M_delay_us(2);
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_RSTB, 0);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
|
||||
glb_40M_delay_us(2);
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_RSTB, 1);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
|
||||
|
||||
/* Step3:reset pll */
|
||||
/* cfg0 : toggle wifipll_reset_fbdv, pulse 0 > 1us */
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_FBDV_RSTB, 1);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
|
||||
glb_40M_delay_us(2);
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_FBDV_RSTB, 0);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
|
||||
glb_40M_delay_us(2);
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
|
||||
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_FBDV_RSTB, 1);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
|
||||
|
||||
/* Step4:enable output clock */
|
||||
/* cfg8 : wifipll clock enable */
|
||||
tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 8);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV3);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV4);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV5);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV6);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV8);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV10);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV12);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV20);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV30);
|
||||
BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 8, tmpVal);
|
||||
|
||||
if (waitStable) {
|
||||
/* Wait 1.5*30us */
|
||||
glb_40M_delay_us(45);
|
||||
}
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief power on xtal and wifipll quickly
|
||||
*
|
||||
* @param xtalType: XTAL frequency type
|
||||
* @param pllType: only power on xtal
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_CLOCK_SECTION GLB_Fast_Power_On_XTAL_40M_And_WIFIPLL(void)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
volatile GLB_PLL_REF_CLK_Type refClk;
|
||||
|
||||
refClk = GLB_PLL_REFCLK_XTAL;
|
||||
|
||||
/* power on xtal first */
|
||||
AON_Power_On_XTAL();
|
||||
|
||||
HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
|
||||
HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
|
||||
|
||||
HBN_Set_Xtal_Type(GLB_XTAL_40M);
|
||||
|
||||
/* power on wifipll */
|
||||
GLB_Power_Off_WIFIPLL();
|
||||
GLB_WIFIPLL_Ref_Clk_Sel(refClk);
|
||||
GLB_Fast_Power_On_WIFIPLL(&wifiPllCfg_960M[GLB_XTAL_40M], 0);
|
||||
|
||||
glb_40M_delay_us(30);
|
||||
|
||||
/* if power on xtal, always set xclk from xtal */
|
||||
HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL);
|
||||
|
||||
/* enable all PLL clock output */
|
||||
/* GLB reg_pll_en = 1, cannot be zero */
|
||||
tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN);
|
||||
BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);
|
||||
|
||||
GLB_CLK_SET_DUMMY_WAIT;
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Program data to efuse
|
||||
*
|
||||
* @param offset: offset of efuse address to program
|
||||
* @param pword: data pointer to buffer which is aligned to word
|
||||
* @param count: count of data in words to program
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void EF_Ctrl_Program_Direct(uint32_t offset, uint32_t *pword, uint32_t count)
|
||||
{
|
||||
uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + offset);
|
||||
|
||||
/* Switch to AHB clock */
|
||||
EF_Ctrl_Sw_AHB_Clk_0();
|
||||
|
||||
/* Add delay for CLK to be stable */
|
||||
arch_delay_us(4);
|
||||
|
||||
if (pword != NULL) {
|
||||
ARCH_MemCpy4(pEfuseStart0, pword, count);
|
||||
}
|
||||
|
||||
EF_Ctrl_Program_Efuse_0();
|
||||
}
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Read data from efuse
|
||||
*
|
||||
* @param offset: offset of efuse address to read
|
||||
* @param pword: data pointer to buffer which is aligned to word
|
||||
* @param count: count of data in words to read
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
void EF_Ctrl_Read_Direct(uint32_t offset, uint32_t *pword, uint32_t count)
|
||||
{
|
||||
uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + offset);
|
||||
|
||||
EF_Ctrl_Load_Efuse_R0();
|
||||
|
||||
ARCH_MemCpy4(pword, pEfuseStart0, count);
|
||||
}
|
||||
|
||||
@ -75,9 +75,7 @@ static SDH_Handle_Cfg_Type *sdhHandle = NULL;
|
||||
/** @defgroup SDH_Private_Fun_Declaration
|
||||
* @{
|
||||
*/
|
||||
#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)
|
||||
static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle);
|
||||
#endif
|
||||
|
||||
/*@} end of group SDH_Private_Fun_Declaration */
|
||||
|
||||
@ -1229,7 +1227,6 @@ void SDH_InstallHandleCallback(SDH_Handle_Cfg_Type *handle,
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)
|
||||
static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle)
|
||||
{
|
||||
uint32_t intFlag, intMask;
|
||||
@ -1345,7 +1342,6 @@ static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle)
|
||||
|
||||
SDH_ClearIntStatus(intFlag);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief SDH interrupt handler
|
||||
@ -1355,12 +1351,10 @@ static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle)
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)
|
||||
void SDH_MMC1_IRQHandler(void)
|
||||
{
|
||||
SDH_IntHandler(SDH_IRQn, sdhHandle);
|
||||
}
|
||||
#endif
|
||||
|
||||
/*@} end of group SDH_Public_Functions */
|
||||
|
||||
|
||||
@ -35,8 +35,8 @@
|
||||
*/
|
||||
|
||||
#include "bl616_sf_cfg.h"
|
||||
#include "softcrc.h"
|
||||
#include "bl616_xip_sflash.h"
|
||||
#include "soft_crc.h"
|
||||
|
||||
/** @addtogroup BL616_Peripheral_Driver
|
||||
* @{
|
||||
|
||||
@ -2157,6 +2157,65 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg,
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Clear flash status register
|
||||
*
|
||||
* @param flashCfg: Flash configuration pointer
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_TCM_SECTION SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *flashCfg)
|
||||
{
|
||||
uint32_t ret = 0;
|
||||
uint32_t qeValue = 0;
|
||||
uint32_t regValue = 0;
|
||||
uint32_t readValue = 0;
|
||||
uint8_t readRegValue0 = 0;
|
||||
uint8_t readRegValue1 = 0;
|
||||
|
||||
if((flashCfg->ioMode&0xf)==SF_CTRL_QO_MODE || (flashCfg->ioMode&0xf)==SF_CTRL_QIO_MODE){
|
||||
qeValue = 1;
|
||||
}
|
||||
|
||||
SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&readRegValue0, 1);
|
||||
SFlash_Read_Reg(flashCfg, 1, (uint8_t *)&readRegValue1, 1);
|
||||
readValue = (readRegValue0|(readRegValue1<<8));
|
||||
if ((readValue & (~((1<<(flashCfg->qeIndex*8+flashCfg->qeBit)) |
|
||||
(1<<(flashCfg->busyIndex*8+flashCfg->busyBit)) |
|
||||
(1<<(flashCfg->wrEnableIndex*8+flashCfg->wrEnableBit))))) == 0){
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
ret = SFlash_Write_Enable(flashCfg);
|
||||
if (SUCCESS != ret) {
|
||||
return ERROR;
|
||||
}
|
||||
if (flashCfg->qeWriteRegLen == 2) {
|
||||
regValue = (qeValue<<(flashCfg->qeIndex*8+flashCfg->qeBit));
|
||||
SFlash_Write_Reg(flashCfg, 0, (uint8_t *)®Value, 2);
|
||||
} else {
|
||||
if (flashCfg->qeIndex == 0) {
|
||||
regValue = (qeValue<<flashCfg->qeBit);
|
||||
} else {
|
||||
regValue = 0;
|
||||
}
|
||||
SFlash_Write_Reg(flashCfg, 0, (uint8_t *)®Value, 1);
|
||||
ret = SFlash_Write_Enable(flashCfg);
|
||||
if (SUCCESS != ret) {
|
||||
return ERROR;
|
||||
}
|
||||
if (flashCfg->qeIndex == 1) {
|
||||
regValue = (qeValue<<flashCfg->qeBit);
|
||||
} else {
|
||||
regValue = 0;
|
||||
}
|
||||
SFlash_Write_Reg(flashCfg, 1, (uint8_t *)®Value, 1);
|
||||
}
|
||||
return SUCCESS;
|
||||
}
|
||||
|
||||
/*@} end of group SFLASH_Public_Functions */
|
||||
|
||||
/*@} end of group SFLASH */
|
||||
|
||||
@ -461,6 +461,35 @@ void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable)
|
||||
}
|
||||
}
|
||||
|
||||
/****************************************************************************//**
|
||||
* @brief Clear flash status register need lock
|
||||
*
|
||||
* @param pFlashCfg: Flash config pointer
|
||||
* @param group: CPU group id 0 or 1
|
||||
* @param bank: Flash bank select
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,
|
||||
uint8_t group, SF_Ctrl_Bank_Select bank)
|
||||
{
|
||||
BL_Err_Type stat;
|
||||
uint32_t offset;
|
||||
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf;
|
||||
|
||||
stat=XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank);
|
||||
if (stat != SUCCESS) {
|
||||
SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank);
|
||||
} else {
|
||||
stat=SFlash_Clear_Status_Register(pFlashCfg);
|
||||
XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank);
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
/*@} end of group XIP_SFLASH_Public_Functions */
|
||||
|
||||
/*@} end of group XIP_SFLASH */
|
||||
|
||||
53
drivers/soc/bl616/port/bl616_efuse.c
Normal file
53
drivers/soc/bl616/port/bl616_efuse.c
Normal file
@ -0,0 +1,53 @@
|
||||
#include "bflb_efuse.h"
|
||||
#include "bl616_ef_ctrl.h"
|
||||
|
||||
float bflb_efuse_get_adc_trim(void)
|
||||
{
|
||||
Efuse_ADC_Gain_Coeff_Type trim;
|
||||
uint32_t tmp;
|
||||
|
||||
float coe = 1.0;
|
||||
|
||||
EF_Ctrl_Read_ADC_Gain_Trim(&trim);
|
||||
|
||||
if (trim.adcGainCoeffEn) {
|
||||
if (trim.adcGainCoeffParity == EF_Ctrl_Get_Trim_Parity(trim.adcGainCoeff, 12)) {
|
||||
tmp = trim.adcGainCoeff;
|
||||
|
||||
if (tmp & 0x800) {
|
||||
tmp = ~tmp;
|
||||
tmp += 1;
|
||||
tmp = tmp & 0xfff;
|
||||
coe = (1.0 + ((float)tmp / 2048.0));
|
||||
} else {
|
||||
coe = (1.0 - ((float)tmp / 2048.0));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return coe;
|
||||
}
|
||||
|
||||
uint32_t bflb_efuse_get_adc_tsen_trim(void)
|
||||
{
|
||||
Efuse_TSEN_Refcode_Corner_Type trim;
|
||||
|
||||
EF_Ctrl_Read_TSEN_Trim(&trim);
|
||||
if (trim.tsenRefcodeCornerEn) {
|
||||
if (trim.tsenRefcodeCornerParity == EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner, 12)) {
|
||||
return trim.tsenRefcodeCorner;
|
||||
}
|
||||
}
|
||||
|
||||
return 2042;
|
||||
}
|
||||
|
||||
void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
|
||||
{
|
||||
EF_Ctrl_Write_AES_Key(index, (uint32_t *)data, len, 1);
|
||||
}
|
||||
|
||||
void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
|
||||
{
|
||||
EF_Ctrl_Read_AES_Key(index, (uint32_t *)data, len);
|
||||
}
|
||||
395
drivers/soc/bl616/port/bl616_flash.c
Normal file
395
drivers/soc/bl616/port/bl616_flash.c
Normal file
@ -0,0 +1,395 @@
|
||||
#include "bl616_glb.h"
|
||||
#include "bl616_xip_sflash.h"
|
||||
#include "bl616_sf_cfg.h"
|
||||
#include "bl616_ef_cfg.h"
|
||||
#include "bflb_flash.h"
|
||||
|
||||
static uint32_t flash1_size = 4 * 1024 * 1024;
|
||||
static uint32_t flash2_size = 2 * 1024 * 1024;
|
||||
static uint32_t g_jedec_id = 0;
|
||||
static uint32_t g_jedec_id2 = 0;
|
||||
static SPI_Flash_Cfg_Type g_flash_cfg;
|
||||
static SPI_Flash_Cfg_Type g_flash2_cfg;
|
||||
|
||||
uint32_t flash2_get_jedecid(void)
|
||||
{
|
||||
uint32_t jid = 0;
|
||||
|
||||
jid = ((g_jedec_id2 & 0xff) << 16) + (g_jedec_id2 & 0xff00) + ((g_jedec_id2 & 0xff0000) >> 16);
|
||||
return jid;
|
||||
}
|
||||
|
||||
uint32_t flash_get_size(SF_Ctrl_Bank_Select bank)
|
||||
{
|
||||
if (bank == SF_CTRL_FLASH_BANK1) {
|
||||
return flash2_size;
|
||||
}
|
||||
return flash1_size;
|
||||
}
|
||||
|
||||
static void flash_get_clock_delay(SPI_Flash_Cfg_Type *cfg)
|
||||
{
|
||||
uint32_t tmpVal = 0;
|
||||
|
||||
tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0);
|
||||
/* bit0-3 for clk delay */
|
||||
if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN)) {
|
||||
cfg->clkDelay = BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1;
|
||||
} else {
|
||||
cfg->clkDelay = 0;
|
||||
}
|
||||
cfg->clkInvert = 0;
|
||||
/* bit0 for clk invert */
|
||||
cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL) & 1) << 0);
|
||||
/* bit1 for rx clk invert */
|
||||
cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL) & 1) << 1);
|
||||
|
||||
tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1);
|
||||
/* bit4-6 for do delay */
|
||||
cfg->clkDelay |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DO_DLY_SEL) & 7) << 4);
|
||||
/* bit2-4 for di delay */
|
||||
cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DI_DLY_SEL) & 7) << 2);
|
||||
/* bit5-7 for oe delay */
|
||||
cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_OE_DLY_SEL) & 7) << 5);
|
||||
}
|
||||
|
||||
static void ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg)
|
||||
{
|
||||
if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
|
||||
SFlash_Qspi_Enable(p_flash_cfg);
|
||||
}
|
||||
}
|
||||
|
||||
static void ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg)
|
||||
{
|
||||
if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) {
|
||||
L1C_Set_Wrap(DISABLE);
|
||||
} else {
|
||||
L1C_Set_Wrap(ENABLE);
|
||||
if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) {
|
||||
SFlash_SetBurstWrap(p_flash_cfg);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief flash_config_init
|
||||
*
|
||||
* @return int
|
||||
*/
|
||||
static int ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id)
|
||||
{
|
||||
int ret = -1;
|
||||
uint8_t isAesEnable = 0;
|
||||
uint32_t jid = 0;
|
||||
uint32_t offset = 0;
|
||||
uintptr_t flag;
|
||||
|
||||
flag = bflb_irq_save();
|
||||
XIP_SFlash_Opt_Enter(&isAesEnable);
|
||||
XIP_SFlash_State_Save(p_flash_cfg, &offset, 0, 0);
|
||||
SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid);
|
||||
arch_memcpy(jedec_id, (uint8_t *)&jid, 3);
|
||||
jid &= 0xFFFFFF;
|
||||
g_jedec_id = jid;
|
||||
ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg);
|
||||
if (ret == 0) {
|
||||
p_flash_cfg->mid = (jid & 0xff);
|
||||
}
|
||||
|
||||
// p_flash_cfg->ioMode = 0x11;
|
||||
// p_flash_cfg->cReadSupport = 0x00;
|
||||
|
||||
/* Set flash controler from p_flash_cfg */
|
||||
flash_set_qspi_enable(p_flash_cfg);
|
||||
flash_set_l1c_wrap(p_flash_cfg);
|
||||
XIP_SFlash_State_Restore(p_flash_cfg, offset, 0, 0);
|
||||
XIP_SFlash_Opt_Exit(isAesEnable);
|
||||
bflb_irq_restore(flag);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief flash2 init
|
||||
*
|
||||
* @return int
|
||||
*/
|
||||
static int ATTR_TCM_SECTION flash2_init(void)
|
||||
{
|
||||
int stat = -1;
|
||||
uint32_t ret = 0;
|
||||
uint32_t jid = 0;
|
||||
Efuse_Device_Info_Type deviceInfo;
|
||||
SF_Ctrl_Bank2_Cfg sfBank2Cfg = {
|
||||
.sbus2Select = ENABLE,
|
||||
.bank2RxClkInvertSrc = DISABLE,
|
||||
.bank2RxClkInvertSel = DISABLE,
|
||||
.bank2DelaySrc = DISABLE,
|
||||
.bank2ClkDelay = 1,
|
||||
.doDelay = 0,
|
||||
.diDelay = 0,
|
||||
.oeDelay = 0,
|
||||
.remap = SF_CTRL_REMAP_4MB,
|
||||
.remapLock = 1,
|
||||
};
|
||||
SF_Ctrl_Cmds_Cfg cmdsCfg = {
|
||||
.ackLatency = 1,
|
||||
.cmdsCoreEn = 1,
|
||||
.cmdsEn = 1,
|
||||
.cmdsWrapMode = 1,
|
||||
.cmdsWrapLen = SF_CTRL_WRAP_LEN_4096,
|
||||
};
|
||||
|
||||
EF_Ctrl_Read_Device_Info(&deviceInfo);
|
||||
if (deviceInfo.memoryInfo == 0) {
|
||||
/* memoryInfo==0, external flash */
|
||||
flash1_size = 64 * 1024 * 1024;
|
||||
flash2_size = 0;
|
||||
} else if (deviceInfo.memoryInfo == 1) {
|
||||
flash1_size = 2 * 1024 * 1024;
|
||||
flash2_size = 0;
|
||||
} else if (deviceInfo.memoryInfo == 2) {
|
||||
flash1_size = 4 * 1024 * 1024;
|
||||
flash2_size = 0;
|
||||
} else if (deviceInfo.memoryInfo == 3) {
|
||||
/* memoryInfo==3, embedded 4MB+2MB flash */
|
||||
flash1_size = 4 * 1024 * 1024;
|
||||
flash2_size = 2 * 1024 * 1024;
|
||||
} else {
|
||||
flash1_size = 8 * 1024 * 1024;
|
||||
flash2_size = 0;
|
||||
}
|
||||
|
||||
if (flash2_size > 0) {
|
||||
SF_Cfg_Sbus2_Flash_Init(SF_IO_EMB_SWAP_IO3IO0_AND_SF2, &sfBank2Cfg);
|
||||
SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2);
|
||||
ret = SF_Cfg_Flash_Identify_Ext(0, SF_IO_EMB_SWAP_IO3IO0_AND_SF2, 0, &g_flash2_cfg, 0, SF_CTRL_FLASH_BANK1);
|
||||
if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0) {
|
||||
return -1;
|
||||
}
|
||||
g_flash2_cfg.ioMode = 0x11;
|
||||
g_flash2_cfg.cReadSupport = 0;
|
||||
g_flash2_cfg.cReadMode = 0xff;
|
||||
SFlash_GetJedecId(&g_flash2_cfg, (uint8_t *)&jid);
|
||||
jid &= 0xFFFFFF;
|
||||
g_jedec_id2 = jid;
|
||||
|
||||
SF_Ctrl_Cmds_Set(&cmdsCfg, SF_CTRL_FLASH_BANK1);
|
||||
stat = SFlash_IDbus_Read_Enable(&g_flash2_cfg, (g_flash2_cfg.ioMode & 0xf), 0, SF_CTRL_FLASH_BANK1);
|
||||
if (0 != stat) {
|
||||
return -1;
|
||||
}
|
||||
SF_Ctrl_Sbus2_Revoke_replace();
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief multi flash adapter
|
||||
*
|
||||
* @return int
|
||||
*/
|
||||
int ATTR_TCM_SECTION bflb_flash_init(void)
|
||||
{
|
||||
int ret = -1;
|
||||
uint32_t jedec_id = 0;
|
||||
uintptr_t flag;
|
||||
|
||||
jedec_id = GLB_Get_Flash_Id_Value();
|
||||
if (jedec_id != 0) {
|
||||
ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jedec_id, &g_flash_cfg);
|
||||
if (ret == 0) {
|
||||
g_jedec_id = jedec_id;
|
||||
g_flash_cfg.ioMode &= 0x0f;
|
||||
flash_get_clock_delay(&g_flash_cfg);
|
||||
flash2_init();
|
||||
return 0;
|
||||
}
|
||||
}
|
||||
|
||||
flag = bflb_irq_save();
|
||||
L1C_ICache_Invalid_All();
|
||||
SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg);
|
||||
L1C_ICache_Invalid_All();
|
||||
bflb_irq_restore(flag);
|
||||
if (g_flash_cfg.mid != 0xff) {
|
||||
g_flash_cfg.ioMode &= 0x0f;
|
||||
flash_get_clock_delay(&g_flash_cfg);
|
||||
flash2_init();
|
||||
return 0;
|
||||
}
|
||||
g_flash_cfg.ioMode &= 0x0f;
|
||||
|
||||
ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
|
||||
|
||||
g_flash_cfg.ioMode &= 0x0f;
|
||||
flash_get_clock_delay(&g_flash_cfg);
|
||||
GLB_Set_Flash_Id_Value(g_jedec_id);
|
||||
|
||||
flash2_init();
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint32_t bflb_flash_get_jedec_id(void)
|
||||
{
|
||||
uint32_t jid = 0;
|
||||
|
||||
jid = ((g_jedec_id & 0xff) << 16) + (g_jedec_id & 0xff00) + ((g_jedec_id & 0xff0000) >> 16);
|
||||
return jid;
|
||||
}
|
||||
|
||||
void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len)
|
||||
{
|
||||
*cfg_addr = (uint8_t *)&g_flash_cfg;
|
||||
*len = sizeof(SPI_Flash_Cfg_Type);
|
||||
}
|
||||
|
||||
void bflb_flash_set_iomode(uint8_t iomode)
|
||||
{
|
||||
g_flash_cfg.ioMode &= ~0x1f;
|
||||
if (iomode == 4) {
|
||||
g_flash_cfg.ioMode |= iomode;
|
||||
} else {
|
||||
g_flash_cfg.ioMode |= 0x10;
|
||||
g_flash_cfg.ioMode |= iomode;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief erase flash via sbus
|
||||
*
|
||||
* @param flash absolute startaddr
|
||||
* @param flash absolute endaddr
|
||||
* @return int
|
||||
*/
|
||||
int ATTR_TCM_SECTION bflb_flash_erase(uint32_t startaddr, uint32_t len)
|
||||
{
|
||||
int stat = -1;
|
||||
uintptr_t flag;
|
||||
|
||||
if ((startaddr + len) > (flash1_size + flash2_size)) {
|
||||
return -ENOMEM;
|
||||
} else if ((startaddr + len) <= flash1_size) {
|
||||
flag = bflb_irq_save();
|
||||
stat = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, startaddr, len, 0, 0);
|
||||
bflb_irq_restore(flag);
|
||||
} else if (startaddr >= flash1_size) {
|
||||
SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2);
|
||||
stat = SFlash_Erase(&g_flash2_cfg, startaddr, startaddr + len - 1);
|
||||
SF_Ctrl_Sbus2_Revoke_replace();
|
||||
} else {
|
||||
flag = bflb_irq_save();
|
||||
stat = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, startaddr, flash1_size - startaddr, 0, 0);
|
||||
bflb_irq_restore(flag);
|
||||
if (stat != 0) {
|
||||
return stat;
|
||||
}
|
||||
SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2);
|
||||
stat = SFlash_Erase(&g_flash2_cfg, flash1_size, startaddr + len - flash1_size - 1);
|
||||
SF_Ctrl_Sbus2_Revoke_replace();
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief write flash data via sbus
|
||||
*
|
||||
* @param flash absolute addr
|
||||
* @param data
|
||||
* @param len
|
||||
* @return int
|
||||
*/
|
||||
int ATTR_TCM_SECTION bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len)
|
||||
{
|
||||
int stat = -1;
|
||||
uintptr_t flag;
|
||||
|
||||
if ((addr + len) > (flash1_size + flash2_size)) {
|
||||
return -ENOMEM;
|
||||
} else if ((addr + len) <= flash1_size) {
|
||||
flag = bflb_irq_save();
|
||||
stat = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, addr, data, len, 0, 0);
|
||||
bflb_irq_restore(flag);
|
||||
} else if (addr >= flash1_size) {
|
||||
SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2);
|
||||
stat = SFlash_Program(&g_flash2_cfg, SF_CTRL_DO_MODE, addr, data, len);
|
||||
SF_Ctrl_Sbus2_Revoke_replace();
|
||||
} else {
|
||||
flag = bflb_irq_save();
|
||||
stat = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0);
|
||||
bflb_irq_restore(flag);
|
||||
if (stat != 0) {
|
||||
return stat;
|
||||
}
|
||||
SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2);
|
||||
stat = SFlash_Program(&g_flash2_cfg, SF_CTRL_DO_MODE, flash1_size, data + (flash1_size - addr), addr + len - flash1_size);
|
||||
SF_Ctrl_Sbus2_Revoke_replace();
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief read flash data via sbus
|
||||
*
|
||||
* @param flash absolute addr
|
||||
* @param data
|
||||
* @param len
|
||||
* @return int
|
||||
*/
|
||||
int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len)
|
||||
{
|
||||
int stat = -1;
|
||||
uintptr_t flag;
|
||||
|
||||
if ((addr + len) > (flash1_size + flash2_size)) {
|
||||
return -ENOMEM;
|
||||
} else if ((addr + len) <= flash1_size) {
|
||||
flag = bflb_irq_save();
|
||||
stat = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, addr, data, len, 0, 0);
|
||||
bflb_irq_restore(flag);
|
||||
} else if (addr >= flash1_size) {
|
||||
SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2);
|
||||
stat = SFlash_Read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, addr, data, len);
|
||||
SF_Ctrl_Sbus2_Revoke_replace();
|
||||
} else {
|
||||
flag = bflb_irq_save();
|
||||
stat = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0);
|
||||
bflb_irq_restore(flag);
|
||||
if (stat != 0) {
|
||||
return stat;
|
||||
}
|
||||
SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2);
|
||||
stat = SFlash_Read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, flash1_size, data + (flash1_size - addr), addr + len - flash1_size);
|
||||
SF_Ctrl_Sbus2_Revoke_replace();
|
||||
}
|
||||
|
||||
return stat;
|
||||
}
|
||||
|
||||
void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config)
|
||||
{
|
||||
uint8_t hw_key_enable = 0;
|
||||
|
||||
if (config->key == NULL) {
|
||||
hw_key_enable = 1;
|
||||
}
|
||||
|
||||
SF_Ctrl_AES_Set_Key_BE(config->region, (uint8_t *)config->key, config->keybits);
|
||||
SF_Ctrl_AES_Set_IV_BE(config->region, (uint8_t *)config->iv, config->start_addr);
|
||||
SF_Ctrl_AES_Set_Region(config->region, config->region_enable, hw_key_enable, config->start_addr, config->end_addr - 1, config->lock_enable);
|
||||
}
|
||||
|
||||
void bflb_flash_aes_enable(void)
|
||||
{
|
||||
SF_Ctrl_AES_Enable();
|
||||
}
|
||||
|
||||
void bflb_flash_aes_disable(void)
|
||||
{
|
||||
SF_Ctrl_AES_Disable();
|
||||
}
|
||||
@ -101,6 +101,7 @@ default_interrupt_handler:
|
||||
* ~mem addr low:
|
||||
*/
|
||||
/* WARNING: global IRQ enabled by ipush */
|
||||
csrs mstatus, 8
|
||||
|
||||
/* keep stack 16bytes aligned */
|
||||
addi sp, sp, -88
|
||||
|
||||
@ -5,15 +5,31 @@ sdk_library_add_sources(startup/start_load.c)
|
||||
sdk_library_add_sources(startup/system_bl702.c)
|
||||
sdk_library_add_sources(startup/interrupt.c)
|
||||
|
||||
if(CONFIG_ROMAPI)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_romapi.c)
|
||||
sdk_add_compile_definitions(-DBFLB_USE_ROM_DRIVER)
|
||||
endif()
|
||||
|
||||
sdk_library_add_sources(bl702_std/src/bl702_aon.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_common.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_clock.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_ef_ctrl.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_glb.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_hbn.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_romapi.c)
|
||||
# sdk_library_add_sources(bl702_std/src/bl702_pds.c)
|
||||
# sdk_library_add_sources(bl702_std/src/bl702_common.c)
|
||||
# sdk_library_add_sources(bl702_std/src/bl702_l1c.c)
|
||||
# sdk_library_add_sources(bl702_std/src/bl702_aon.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_l1c.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_pds.c)
|
||||
|
||||
sdk_library_add_sources(bl702_std/src/bl702_sf_cfg.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_sf_cfg_ext.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_sf_ctrl.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_sflash.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_sflash_ext.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_xip_sflash.c)
|
||||
sdk_library_add_sources(bl702_std/src/bl702_xip_sflash_ext.c)
|
||||
|
||||
sdk_library_add_sources(port/bl702_clock.c)
|
||||
sdk_library_add_sources(port/bl702_flash.c)
|
||||
sdk_library_add_sources(port/bl702_efuse.c)
|
||||
|
||||
sdk_add_include_directories(
|
||||
bl702_std/include
|
||||
@ -24,7 +40,7 @@ SET(MCPU "riscv-e24")
|
||||
SET(MARCH "rv32imafc")
|
||||
SET(MABI "ilp32f")
|
||||
|
||||
sdk_add_compile_definitions(-DARCH_RISCV)
|
||||
sdk_add_compile_definitions(-DARCH_RISCV -DBFLB_USE_HAL_DRIVER)
|
||||
sdk_add_compile_options(-march=${MARCH} -mabi=${MABI})
|
||||
sdk_add_link_options(-march=${MARCH} -mabi=${MABI})
|
||||
|
||||
|
||||
@ -205,6 +205,11 @@ __ALWAYS_STATIC_INLINE void __disable_irq(void)
|
||||
#define arch_delay_us BL702_Delay_US
|
||||
#define arch_delay_ms BL702_Delay_MS
|
||||
|
||||
#define BFLB_Soft_CRC32 bflb_soft_crc32
|
||||
#define CPU_Interrupt_Enable(irq)
|
||||
#define CPU_Interrupt_Disable(irq)
|
||||
#define Interrupt_Handler_Register(irq, callback)
|
||||
|
||||
void BL702_Delay_US(uint32_t cnt);
|
||||
void BL702_Delay_MS(uint32_t cnt);
|
||||
#endif
|
||||
|
||||
@ -172,8 +172,7 @@ void L1C_BMX_TO_IRQHandler(void);
|
||||
/*----------*/
|
||||
BL_Err_Type L1C_Cache_Enable_Set(uint8_t wayDisable);
|
||||
void L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn);
|
||||
BL_Err_Type L1C_Cache_Flush(uint8_t wayDisable);
|
||||
BL_Err_Type L1C_Cache_Flush_Ext(void);
|
||||
BL_Err_Type L1C_Cache_Flush(void);
|
||||
void L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh);
|
||||
uint32_t L1C_Cache_Miss_Count_Get(void);
|
||||
void L1C_Cache_Read_Disable(void);
|
||||
|
||||
@ -98,64 +98,6 @@ static intCallback_Type *l1cBmxToIntCbfArra[L1C_BMX_TO_INT_ALL] = { NULL };
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Enable_Set(uint8_t wayDisable)
|
||||
{
|
||||
L1C_Cache_Flush(wayDisable);
|
||||
|
||||
return SUCCESS;
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief L1C cache write set
|
||||
*
|
||||
* @param wtEn: L1C write through enable
|
||||
* @param wbEn: L1C write back enable
|
||||
* @param waEn: L1C write allocate enable
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
void ATTR_TCM_SECTION L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
|
||||
|
||||
if (wtEn) {
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WT_EN);
|
||||
} else {
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WT_EN);
|
||||
}
|
||||
|
||||
if (wbEn) {
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WB_EN);
|
||||
} else {
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WB_EN);
|
||||
}
|
||||
|
||||
if (waEn) {
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WA_EN);
|
||||
} else {
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WA_EN);
|
||||
}
|
||||
|
||||
BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Flush cache
|
||||
*
|
||||
* @param wayDisable: cache way disable config
|
||||
*
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush(uint8_t wayDisable)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
uint32_t cnt = 0;
|
||||
@ -248,6 +190,46 @@ BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush(uint8_t wayDisable)
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief L1C cache write set
|
||||
*
|
||||
* @param wtEn: L1C write through enable
|
||||
* @param wbEn: L1C write back enable
|
||||
* @param waEn: L1C write allocate enable
|
||||
*
|
||||
* @return None
|
||||
*
|
||||
*******************************************************************************/
|
||||
#ifndef BFLB_USE_ROM_DRIVER
|
||||
__WEAK
|
||||
void ATTR_TCM_SECTION L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
|
||||
|
||||
if (wtEn) {
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WT_EN);
|
||||
} else {
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WT_EN);
|
||||
}
|
||||
|
||||
if (wbEn) {
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WB_EN);
|
||||
} else {
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WB_EN);
|
||||
}
|
||||
|
||||
if (waEn) {
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WA_EN);
|
||||
} else {
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WA_EN);
|
||||
}
|
||||
|
||||
BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
|
||||
}
|
||||
#endif
|
||||
|
||||
/****************************************************************************/ /**
|
||||
* @brief Flush cache external api
|
||||
*
|
||||
@ -256,13 +238,13 @@ BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush(uint8_t wayDisable)
|
||||
* @return SUCCESS or ERROR
|
||||
*
|
||||
*******************************************************************************/
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush_Ext(void)
|
||||
BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush(void)
|
||||
{
|
||||
uint32_t tmpVal;
|
||||
|
||||
/* Disable early respone */
|
||||
tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
|
||||
L1C_Cache_Flush((tmpVal >> L1C_WAY_DIS_POS) & 0xf);
|
||||
L1C_Cache_Enable_Set((tmpVal >> L1C_WAY_DIS_POS) & 0xf);
|
||||
__NOP();
|
||||
__NOP();
|
||||
__NOP();
|
||||
|
||||
@ -53,44 +53,44 @@ __ALWAYS_INLINE ATTR_TCM_SECTION void BL702_Delay_MS(uint32_t cnt)
|
||||
RomDriver_BL702_Delay_MS(cnt);
|
||||
}
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION void *BL702_MemCpy(void *dst, const void *src, uint32_t n)
|
||||
{
|
||||
return RomDriver_BL702_MemCpy(dst, src, n);
|
||||
}
|
||||
// __ALWAYS_INLINE ATTR_TCM_SECTION void *BL702_MemCpy(void *dst, const void *src, uint32_t n)
|
||||
// {
|
||||
// return RomDriver_BL702_MemCpy(dst, src, n);
|
||||
// }
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
uint32_t *
|
||||
BL702_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n)
|
||||
{
|
||||
return RomDriver_BL702_MemCpy4(dst, src, n);
|
||||
}
|
||||
// __ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
// uint32_t *
|
||||
// BL702_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n)
|
||||
// {
|
||||
// return RomDriver_BL702_MemCpy4(dst, src, n);
|
||||
// }
|
||||
|
||||
// __ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
// void* BL702_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n) {
|
||||
// return RomDriver_BL702_MemCpy_Fast(pdst, psrc, n);
|
||||
// }
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION void *ARCH_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n)
|
||||
{
|
||||
return RomDriver_ARCH_MemCpy_Fast(pdst, psrc, n);
|
||||
}
|
||||
// __ALWAYS_INLINE ATTR_TCM_SECTION void *ARCH_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n)
|
||||
// {
|
||||
// return RomDriver_ARCH_MemCpy_Fast(pdst, psrc, n);
|
||||
// }
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION void *BL702_MemSet(void *s, uint8_t c, uint32_t n)
|
||||
{
|
||||
return RomDriver_BL702_MemSet(s, c, n);
|
||||
}
|
||||
// __ALWAYS_INLINE ATTR_TCM_SECTION void *BL702_MemSet(void *s, uint8_t c, uint32_t n)
|
||||
// {
|
||||
// return RomDriver_BL702_MemSet(s, c, n);
|
||||
// }
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
uint32_t *
|
||||
BL702_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n)
|
||||
{
|
||||
return RomDriver_BL702_MemSet4(dst, val, n);
|
||||
}
|
||||
// __ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
// uint32_t *
|
||||
// BL702_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n)
|
||||
// {
|
||||
// return RomDriver_BL702_MemSet4(dst, val, n);
|
||||
// }
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION int BL702_MemCmp(const void *s1, const void *s2, uint32_t n)
|
||||
{
|
||||
return RomDriver_BL702_MemCmp(s1, s2, n);
|
||||
}
|
||||
// __ALWAYS_INLINE ATTR_TCM_SECTION int BL702_MemCmp(const void *s1, const void *s2, uint32_t n)
|
||||
// {
|
||||
// return RomDriver_BL702_MemCmp(s1, s2, n);
|
||||
// }
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
uint32_t
|
||||
@ -780,12 +780,14 @@ __ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_F
|
||||
RomDriver_L1C_Cache_Write_Set(wtEn, wbEn, waEn);
|
||||
}
|
||||
|
||||
#if 0
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION
|
||||
BL_Err_Type
|
||||
L1C_Cache_Flush(uint8_t wayDisable)
|
||||
{
|
||||
return RomDriver_L1C_Cache_Flush(wayDisable);
|
||||
}
|
||||
#endif
|
||||
|
||||
__ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh)
|
||||
{
|
||||
|
||||
@ -36,8 +36,8 @@
|
||||
|
||||
#include "bl702_glb.h"
|
||||
#include "bl702_sf_cfg.h"
|
||||
#include "softcrc.h"
|
||||
#include "bl702_xip_sflash.h"
|
||||
#include "soft_crc.h"
|
||||
|
||||
/** @addtogroup BL702_Peripheral_Driver
|
||||
* @{
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user