[feat][clock] move rc32m init into hal_clock.c
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4efd11c6f7
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@ -26,6 +26,43 @@
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#include "bl702_timer.h"
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#include "hal_clock.h"
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#if XTAL_TYPE != EXTERNAL_XTAL_32M
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static void internal_rc32m_init(void)
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{
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uint32_t tmpVal;
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tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
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tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
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BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
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tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, 0);
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BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
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tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, 0);
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BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
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tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_RDY_SEL_AON, 0);
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BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
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tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_RDY_INT_SEL_AON, 0);
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BL_WR_REG(AON_BASE, AON_TSEN, tmpVal);
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for (uint32_t i = 0; i < 20000; i++) {
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tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
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tmpVal = BL_SET_REG_BIT(tmpVal, AON_XTAL_EXT_SEL_AON);
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BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
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tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
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tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_EXT_SEL_AON);
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BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
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if (BL_IS_REG_BIT_SET(BL_RD_REG(GLB_BASE, GLB_CLK_CFG0), GLB_CHIP_RDY))
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break;
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}
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}
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#endif
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static uint32_t mtimer_get_clk_src_div(void)
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{
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return (system_clock_get(SYSTEM_CLOCK_BCLK) / 1000 / 1000 - 1);
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@ -62,6 +99,10 @@ static void peripheral_clock_gate_all()
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void system_clock_init(void)
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{
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#if XTAL_TYPE != EXTERNAL_XTAL_32M
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internal_rc32m_init();
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AON_Power_Off_XTAL();
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#endif
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/*select root clock*/
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GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE);
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#if BSP_ROOT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_57P6M
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@ -67,37 +67,6 @@ void SystemInit(void)
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/* global IRQ disable */
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__disable_irq();
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tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
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tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
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BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
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tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, 0);
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BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
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tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, 0);
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BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
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tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_RDY_SEL_AON, 0);
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BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
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tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
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tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_RDY_INT_SEL_AON, 0);
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BL_WR_REG(AON_BASE, AON_TSEN, tmpVal);
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for (i = 0; i < 20000; i++) {
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tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
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tmpVal = BL_SET_REG_BIT(tmpVal, AON_XTAL_EXT_SEL_AON);
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BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
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tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
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tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_EXT_SEL_AON);
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BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
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if (BL_IS_REG_BIT_SET(BL_RD_REG(GLB_BASE, GLB_CLK_CFG0), GLB_CHIP_RDY))
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break;
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}
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tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
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tmpVal |= (1 << 8); /*mask pds wakeup*/
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tmpVal |= (1 << 10); /*mask rf done*/
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