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[refactor][dma] rename DMA_BURST_xBYTE with DMA_BURST_INCRx

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This commit is contained in:
jzlv 2022-04-26 12:58:47 +08:00
parent c65ae0f8f2
commit d0092f878a
42 changed files with 270 additions and 394 deletions
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34
bsp/board/bl602/bl602_boot2/peripheral_config.h
View File

@ -30,7 +30,7 @@
/* ----------------------*/
/* PERIPHERAL With DMA LIST */
#define BSP_USING_DMA
#define BSP_USING_DMA0_CH0
#define BSP_USING_DMA0_CH1
#define BSP_USING_DMA0_CH2
@ -81,8 +81,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
@ -101,8 +101,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -121,8 +121,8 @@
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -141,8 +141,8 @@
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -161,8 +161,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -181,8 +181,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -201,8 +201,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -221,8 +221,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}

35
bsp/board/bl602/bl602_iot/peripheral_config.h
View File

@ -26,10 +26,11 @@
/* PERIPHERAL USING LIST */
#define BSP_USING_UART0
#define BSP_USING_DAC0
/* ----------------------*/
/* PERIPHERAL With DMA LIST */
#define BSP_USING_DAC0
#define BSP_USING_DMA
#define BSP_USING_DMA0_CH0
#define BSP_USING_DMA0_CH1
#define BSP_USING_DMA0_CH2
@ -92,8 +93,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
@ -112,8 +113,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -132,8 +133,8 @@
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -152,8 +153,8 @@
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -172,8 +173,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -192,8 +193,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -212,8 +213,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -232,8 +233,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}

34
bsp/board/bl702/bl702_boot2/peripheral_config.h
View File

@ -43,7 +43,7 @@
/* ----------------------*/
/* PERIPHERAL With DMA LIST */
#define BSP_USING_DMA
#define BSP_USING_DMA0_CH0
#define BSP_USING_DMA0_CH1
#define BSP_USING_DMA0_CH2
@ -208,8 +208,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_burst_size = DMA_BURST_INCR4, \
.dst_burst_size = DMA_BURST_INCR4, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
@ -228,8 +228,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_burst_size = DMA_BURST_INCR4, \
.dst_burst_size = DMA_BURST_INCR4, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -248,8 +248,8 @@
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -268,8 +268,8 @@
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -288,8 +288,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -308,8 +308,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -328,8 +328,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -348,8 +348,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}

38
bsp/board/bl702/bl702_iot/peripheral_config.h
View File

@ -48,7 +48,7 @@
/* ----------------------*/
/* PERIPHERAL With DMA LIST */
#define BSP_USING_DMA
#define BSP_USING_DMA0_CH0
#define BSP_USING_DMA0_CH1
#define BSP_USING_DMA0_CH2
@ -124,7 +124,7 @@
.clk_polaraity = SPI_POLARITY_LOW, \
.clk_phase = SPI_PHASE_1EDGE, \
.datasize = SPI_DATASIZE_8BIT, \
.fifo_threshold = 1, \
.fifo_threshold = 0, \
.pin_swap_enable = 1, \
.delitch_cnt = 0, \
}
@ -212,7 +212,7 @@
.channel_num = I2S_FS_CHANNELS_NUM_MONO, \
.frame_size = I2S_FRAME_LEN_16, \
.data_size = I2S_DATA_LEN_16, \
.fifo_threshold = 8, \
.fifo_threshold = 7, \
}
#endif
#endif
@ -229,8 +229,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_burst_size = DMA_BURST_INCR4, \
.dst_burst_size = DMA_BURST_INCR4, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
@ -249,8 +249,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_burst_size = DMA_BURST_INCR4, \
.dst_burst_size = DMA_BURST_INCR4, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -269,8 +269,8 @@
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -289,8 +289,8 @@
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -309,8 +309,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -329,8 +329,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -349,8 +349,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -369,8 +369,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}

34
bsp/board/bl702/bl706_avb/peripheral_config.h
View File

@ -48,7 +48,7 @@
/* ----------------------*/
/* PERIPHERAL With DMA LIST */
#define BSP_USING_DMA
#define BSP_USING_DMA0_CH0
#define BSP_USING_DMA0_CH1
#define BSP_USING_DMA0_CH2
@ -229,8 +229,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_burst_size = DMA_BURST_INCR4, \
.dst_burst_size = DMA_BURST_INCR4, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
@ -249,8 +249,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_burst_size = DMA_BURST_INCR4, \
.dst_burst_size = DMA_BURST_INCR4, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -269,8 +269,8 @@
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -289,8 +289,8 @@
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -309,8 +309,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -329,8 +329,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -349,8 +349,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -369,8 +369,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}

34
bsp/board/bl702/bl706_iot/peripheral_config.h
View File

@ -48,7 +48,7 @@
/* ----------------------*/
/* PERIPHERAL With DMA LIST */
#define BSP_USING_DMA
#define BSP_USING_DMA0_CH0
#define BSP_USING_DMA0_CH1
#define BSP_USING_DMA0_CH2
@ -229,8 +229,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_burst_size = DMA_BURST_INCR4, \
.dst_burst_size = DMA_BURST_INCR4, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
@ -249,8 +249,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_burst_size = DMA_BURST_INCR4, \
.dst_burst_size = DMA_BURST_INCR4, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -269,8 +269,8 @@
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -289,8 +289,8 @@
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -309,8 +309,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -329,8 +329,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -349,8 +349,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -369,8 +369,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}

34
bsp/board/bl702/bl706_lp/peripheral_config.h
View File

@ -29,7 +29,7 @@
/* ----------------------*/
/* PERIPHERAL With DMA LIST */
#define BSP_USING_DMA
#define BSP_USING_DMA0_CH0
#define BSP_USING_DMA0_CH1
#define BSP_USING_DMA0_CH2
@ -194,8 +194,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_burst_size = DMA_BURST_INCR4, \
.dst_burst_size = DMA_BURST_INCR4, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
@ -214,8 +214,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_burst_size = DMA_BURST_INCR4, \
.dst_burst_size = DMA_BURST_INCR4, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -234,8 +234,8 @@
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -254,8 +254,8 @@
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -274,8 +274,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -294,8 +294,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -314,8 +314,8 @@
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
@ -334,8 +334,8 @@
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}

8
bsp/bsp_common/il9341/bsp_il9341.c
View File

@ -117,8 +117,8 @@ void spi0_init(void)
DMA_DEV(dma_ch3)->dst_req = DMA_REQUEST_SPI0_TX;
DMA_DEV(dma_ch3)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch3, 0);
@ -142,8 +142,8 @@ void spi0_init(void)
DMA_DEV(dma_ch4)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch4)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch4)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch4)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch4)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch4)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch4)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch4)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch4)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch4, 0);

8
bsp/bsp_common/mcu_lcd/ili9341.c
View File

@ -108,8 +108,8 @@ static int ili9341_spi_init(void)
DMA_DEV(dma_ch3)->dst_req = DMA_REQUEST_SPI0_TX;
DMA_DEV(dma_ch3)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch3, 0);
@ -369,8 +369,8 @@ void ili9341_draw_picture_nonblocking(uint16_t x1, uint16_t y1, uint16_t x2, uin
}
// DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_32BIT;
// DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_1BYTE;
// DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_4BYTE;
// DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_INCR1;
// DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_INCR4;
ili9341_set_draw_window(x1, y1, x2, y2);
ILI9341_DC_HIGH;

4
bsp/bsp_common/mcu_lcd/st7735s.c
View File

@ -108,8 +108,8 @@ static int st7735s_spi_init(void)
DMA_DEV(dma_ch3)->dst_req = DMA_REQUEST_SPI0_TX;
DMA_DEV(dma_ch3)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch3, 0);

4
bsp/bsp_common/mcu_lcd/st7789v.c
View File

@ -110,8 +110,8 @@ static int st7789v_spi_init(void)
DMA_DEV(dma_ch3)->dst_req = DMA_REQUEST_SPI0_TX;
DMA_DEV(dma_ch3)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch3, 0);

8
bsp/bsp_common/spi_sd/bsp_spi_sd.c
View File

@ -66,8 +66,8 @@ uint8_t SD_SPI_Init(void)
DMA_DEV(dma_ch3)->dst_req = DMA_REQUEST_SPI0_TX;
DMA_DEV(dma_ch3)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch3, 0);
@ -90,8 +90,8 @@ uint8_t SD_SPI_Init(void)
DMA_DEV(dma_ch4)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch4)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch4)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch4)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch4)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch4)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch4)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch4)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch4)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch4, 0);

4
bsp/bsp_common/usb/uart_interface.c
View File

@ -80,8 +80,8 @@ void uart1_init(void)
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_UART1_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch2, 0);

26
docs/development_guide/source/api_reference/peripheral/api_dma.rst
View File

@ -137,19 +137,19 @@ DMA 设备结构体定义
.. code-block:: C
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_BURST_INCR1 0
#define DMA_BURST_INCR4 1
#define DMA_BURST_INCR8 2
#define DMA_BURST_INCR16 3
``dst_burst_size`` 提供以下类型
.. code-block:: C
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_BURST_INCR1 0
#define DMA_BURST_INCR4 1
#define DMA_BURST_INCR8 2
#define DMA_BURST_INCR16 3
``src_width`` 提供以下类型
@ -187,8 +187,8 @@ DMA 设备参数配置表
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -468,7 +468,7 @@ DMA 的效率与FIFO
- 在连续读写时，burst 突发模式的总线利用效率比 single 单次模式高得多，因此可以尽量提高 ``xxx_burst_size``，但注意，DMA0 的每个通道只有 16Byte 的 FIFO，因此 width 乘 burst_size 的积必须小于等于 16Byte。
因此在内存到内存搬运数据时，最高效的是 ``xxx_width`` 值为 ``DMA_TRANSFER_WIDTH_32BIT``, ``xxx_burst_size`` 值为 ``DMA_BURST_4BYTE``,此时完全利用了 DMA 的FIFO，读写最快，总线占用最少，但要求数据量与地址满足对齐要求。
因此在内存到内存搬运数据时，最高效的是 ``xxx_width`` 值为 ``DMA_TRANSFER_WIDTH_32BIT``, ``xxx_burst_size`` 值为 ``DMA_BURST_INCR4``,此时完全利用了 DMA 的FIFO，读写最快，总线占用最少，但要求数据量与地址满足对齐要求。
外设到内存 与 内存到外设
@ -482,7 +482,7 @@ DMA 的效率与FIFO
- 内存端配置的 burst_size 和 width 与外设端的可以不相等，但 burst_size 与 width 的乘积必须相等，并且小于 16Byte。内存端配置更高的 ``xxx_width`` 可以提高传输速度，减少对总线占用，但注意对数据量(data size)与地址的对齐要求。
如对于 I2S ,他的 tx 与 rx 的 FIFO 深度都为 8，I2S 最佳的 ``fifo_threshold`` 应为 4，DMA 的 ``xxx_burst_size`` 应该为 ``DMA_BURST_4BYTE``，这样能保证 I2S 的 FIFO 能留有一定余量防止出现 rx-FIFO 溢出与 tx-FIFO 欠载，又减少 DMA 了对总线的占用。
如对于 I2S ,他的 tx 与 rx 的 FIFO 深度都为 8，I2S 最佳的 ``fifo_threshold`` 应为 4，DMA 的 ``xxx_burst_size`` 应该为 ``DMA_BURST_INCR4``，这样能保证 I2S 的 FIFO 能留有一定余量防止出现 rx-FIFO 溢出与 tx-FIFO 欠载，又减少 DMA 了对总线的占用。
又如对于 SPI ，他的 tx 与 rx 的 FIFO 深度都为 4，若使用 burst_size 为 4 的方式传输，那么 SPI 的 ``fifo_threshold`` 只能是 4，没有冗余，若此时 CPU 在占用总线导致 DMA 传输不及时，可能会出现SPI传输间歇，在SPI从机模式下还可能出现发送欠载与接收溢出。
因此对于 SPI 而言，最佳的 ``fifo_threshold`` 应为 1，DMA 的 ``xxx_burst_size`` 应为 ``DMA_BURST_1BYTE``，此时 DMA 虽然对总线的访问效率一般，但保证了 SPI 的 FIFO 有冗余，不会出现上诉问题。
因此对于 SPI 而言，最佳的 ``fifo_threshold`` 应为 1，DMA 的 ``xxx_burst_size`` 应为 ``DMA_BURST_INCR1``，此时 DMA 虽然对总线的访问效率一般，但保证了 SPI 的 FIFO 有冗余，不会出现上诉问题。

8
docs/development_guide/source/samples/advance samples/fatfs_demo.rst
View File

@ -95,8 +95,8 @@ FatFs 文件系统读写(SD 卡)
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -115,8 +115,8 @@ FatFs 文件系统读写(SD 卡)
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}

4
docs/development_guide/source/samples/advance samples/usb/usbd_audio.rst
View File

@ -198,8 +198,8 @@ USB 协议栈可以参考 API 手册下的 USB Stack 章节的说明。
DMA_DEV(dma_ch4_usb_tx)->dst_req = DMA_REQUEST_USB_EP1;
DMA_DEV(dma_ch4_usb_tx)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch4_usb_tx)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch4_usb_tx)->src_burst_size = DMA_BURST_16BYTE;
DMA_DEV(dma_ch4_usb_tx)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch4_usb_tx)->src_burst_size = DMA_BURST_INCR16;
DMA_DEV(dma_ch4_usb_tx)->dst_burst_size = DMA_BURST_INCR1;
device_open(dma_ch4_usb_tx, 0);
// device_set_callback(dma_ch4_usb_tx, dma2_irq_callback);

8
docs/development_guide/source/samples/advance samples/usb/usbd_video.rst
View File

@ -135,8 +135,8 @@ BL706 AVB + GC0308摄像头模块 + windows 相机
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_burst_size = DMA_BURST_INCR1, \
.dst_burst_size = DMA_BURST_INCR1, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
@ -155,8 +155,8 @@ BL706 AVB + GC0308摄像头模块 + windows 相机
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_USB_EP1;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_16BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_INCR16;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch2, 0);

8
docs/development_guide/source/samples/basic samples/dma/dma_m2m_demo.rst
View File

@ -29,8 +29,8 @@ DMA - RAM间数据搬运
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_burst_size = DMA_BURST_INCR4, \
.dst_burst_size = DMA_BURST_INCR4, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
@ -53,8 +53,8 @@ DMA - RAM间数据搬运
DMA_DEV(dma_ch0)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch0)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch0)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch0)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch0)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch0)->src_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch0)->dst_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch0)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch0)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
device_open(dma_ch0, 0);

4
docs/development_guide/source/samples/basic samples/i2s/i2s_play_from_flash_demo.rst
View File

@ -156,8 +156,8 @@ DMA 的配置与使能
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_INCR4;
device_open(dma_ch2, 0);
/* connect i2s device and dma device */

10
docs/development_guide/source/samples/basic samples/i2s/i2s_play_from_record_demo.rst
View File

@ -160,8 +160,8 @@ DMA 的配置与使能
DMA_DEV(dma_ch3)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch3)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
device_open(dma_ch3, 0);
@ -185,8 +185,8 @@ DMA 的配置与使能
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_INCR4;
device_open(dma_ch2, 0);
/* connect i2s device and dma device */
@ -201,7 +201,7 @@ DMA 的配置与使能
.. important:: 这里 DMA 的传输宽度设置为了 ``DMA_TRANSFER_WIDTH_32BIT``,但前面 I2S 的配置是16位有效数据，这是因为 I2S 在初始化时默认使用了合并 FIFO 功能，\
即当双声道时有效数据位宽为8位或者16位时，会将双声道数据同时放入同一个 FIFO 中,合并为16位或32位，提高 FIFO 利用效率，具体原因请看 api_dma 文档最后一节
.. important:: 这里 DMA 的 ``src_burst_size`` 与 ``dst_burst_size`` 都为 DMA_BURST_4BYTE，这要求 I2S 初始化时，其中的 ``fifo_threshold`` 要大于等于4，具体原因请看 api_dma 文档最后一节
.. important:: 这里 DMA 的 ``src_burst_size`` 与 ``dst_burst_size`` 都为 DMA_BURST_INCR4，这要求 I2S 初始化时，其中的 ``fifo_threshold`` 要大于等于4，具体原因请看 api_dma 文档最后一节
DMA 中断回调函数
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

16
docs/development_guide_en/source/api_reference/peripheral/api_dma.rst
View File

@ -118,19 +118,19 @@ DMA Device Structure Definition
.. code-block:: C
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_BURST_INCR1 0
#define DMA_BURST_INCR4 1
#define DMA_BURST_INCR8 2
#define DMA_BURST_INCR16 3
``dst_burst_size`` provides the following types
.. code-block:: C
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_BURST_INCR1 0
#define DMA_BURST_INCR4 1
#define DMA_BURST_INCR8 2
#define DMA_BURST_INCR16 3
``src_width`` provides the following types

11
drivers/bl602_driver/hal_drv/inc/hal_dma.h
View File

@ -77,10 +77,10 @@ enum dma_index_type {
#define DMA_TRANSFER_WIDTH_16BIT 1
#define DMA_TRANSFER_WIDTH_32BIT 2
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_BURST_INCR1 0
#define DMA_BURST_INCR4 1
#define DMA_BURST_INCR8 2
#define DMA_BURST_INCR16 3
#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88)
#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C)
@ -162,7 +162,8 @@ typedef struct dma_device {
uint8_t dst_burst_size;
uint8_t src_width;
uint8_t dst_width;
dma_lli_ctrl_t *lli_cfg;
uint8_t intr; /* private param */
dma_lli_ctrl_t *lli_cfg;/* private param*/
} dma_device_t;
#define DMA_DEV(dev) ((dma_device_t *)dev)

89
drivers/bl602_driver/hal_drv/src/hal_dma.c
View File

@ -81,13 +81,13 @@ int dma_open(struct device *dev, uint16_t oflag)
/* Disable all interrupt */
DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK);
/* Enable uart interrupt*/
CPU_Interrupt_Disable(DMA_ALL_IRQn);
DMA_Disable();
DMA_Channel_Disable(dma_device->ch);
dma_device->intr = 0;
chCfg.ch = dma_device->ch;
chCfg.dir = dma_device->direction;
chCfg.srcPeriph = dma_device->src_req;
@ -103,7 +103,7 @@ int dma_open(struct device *dev, uint16_t oflag)
DMA_Enable();
Interrupt_Handler_Register(DMA_ALL_IRQn, DMA0_IRQ);
/* Enable uart interrupt*/
/* Enable dma interrupt*/
CPU_Interrupt_Enable(DMA_ALL_IRQn);
return 0;
}
@ -124,14 +124,14 @@ int dma_control(struct device *dev, int cmd, void *args)
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK);
dma_device->intr = 1;
break;
case DEVICE_CTRL_CLR_INT:
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK);
dma_device->intr = 0;
break;
case DEVICE_CTRL_GET_INT:
@ -186,6 +186,7 @@ int dma_close(struct device *dev)
DMA_Channel_Disable(dma_device->ch);
DMA_Channel_Init(&chCfg);
dma_device->intr = 0;
return 0;
}
@ -211,64 +212,6 @@ int dma_register(enum dma_index_type index, const char *name)
return device_register(dev, name);
}
static BL_Err_Type dma_scan_unregister_device(uint8_t *allocate_index)
{
struct device *dev;
dlist_t *node;
uint8_t dma_index = 0;
uint32_t dma_handle[DMA_MAX_INDEX];
for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) {
dma_handle[dma_index] = 0xff;
}
/* get registered dma handle list*/
dlist_for_each(node, device_get_list_header())
{
dev = dlist_entry(node, struct device, list);
if (dev->type == DEVICE_CLASS_DMA) {
dma_handle[(((uint32_t)dev - (uint32_t)dmax_device) / sizeof(dma_device_t)) % DMA_MAX_INDEX] = SET;
}
}
for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) {
if (dma_handle[dma_index] == 0xff) {
*allocate_index = dma_index;
return SUCCESS;
}
}
return ERROR;
}
int dma_allocate_register(const char *name)
{
struct device *dev;
uint8_t index;
if (DMA_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
if (dma_scan_unregister_device(&index) == ERROR) {
return -DEVICE_ENOSPACE;
}
dev = &(dmax_device[index].parent);
dev->open = dma_open;
dev->close = dma_close;
dev->control = dma_control;
// dev->write = dma_write;
// dev->read = dma_read;
dev->type = DEVICE_CLASS_DMA;
dev->handle = NULL;
return device_register(dev, name);
}
/**
* @brief
*
@ -280,11 +223,13 @@ int dma_allocate_register(const char *name)
*/
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size)
{
#ifdef BSP_USING_DMA
uint32_t malloc_count;
uint32_t remain_len;
uint32_t actual_transfer_len = 0;
uint32_t actual_transfer_offset = 0;
dma_control_data_t dma_ctrl_cfg;
bool intr = false;
dma_device_t *dma_device = (dma_device_t *)dev;
@ -321,6 +266,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
}
dma_ctrl_cfg = (dma_control_data_t)(BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL));
intr = dma_device->intr;
malloc_count = actual_transfer_len / 4095;
remain_len = actual_transfer_len % 4095;
@ -329,23 +275,17 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
malloc_count++;
}
if (dma_device->lli_cfg) {
free(dma_device->lli_cfg);
dma_device->lli_cfg = (dma_lli_ctrl_t *)malloc(sizeof(dma_lli_ctrl_t) * malloc_count);
} else {
dma_device->lli_cfg = (dma_lli_ctrl_t *)malloc(sizeof(dma_lli_ctrl_t) * malloc_count);
}
dma_device->lli_cfg = (dma_lli_ctrl_t *)realloc(dma_device->lli_cfg, sizeof(dma_lli_ctrl_t) * malloc_count);
if (dma_device->lli_cfg) {
dma_ctrl_cfg.bits.TransferSize = 4095;
dma_ctrl_cfg.bits.I = 0;
/*transfer_size will be integer multiple of 4095*n or 4095*2*n or 4095*4*n,(n>0) */
for (uint32_t i = 0; i < malloc_count; i++) {
dma_device->lli_cfg[i].src_addr = src_addr;
dma_device->lli_cfg[i].dst_addr = dst_addr;
dma_device->lli_cfg[i].nextlli = 0;
dma_ctrl_cfg.bits.TransferSize = 4095;
dma_ctrl_cfg.bits.I = 0;
if (dma_ctrl_cfg.bits.SI) {
src_addr += actual_transfer_offset;
}
@ -358,7 +298,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
if (remain_len) {
dma_ctrl_cfg.bits.TransferSize = remain_len;
}
dma_ctrl_cfg.bits.I = 1;
dma_ctrl_cfg.bits.I = intr;
if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) {
dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0];
@ -369,7 +309,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
dma_device->lli_cfg[i - 1].nextlli = (uint32_t)&dma_device->lli_cfg[i];
}
memcpy(&dma_device->lli_cfg[i].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t));
dma_device->lli_cfg[i].cfg = dma_ctrl_cfg;
}
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_SRCADDR, dma_device->lli_cfg[0].src_addr);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_DSTADDR, dma_device->lli_cfg[0].dst_addr);
@ -378,9 +318,10 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
} else {
return -2;
}
#endif
return 0;
}
/**
* @brief
*

12
drivers/bl702_driver/hal_drv/inc/hal_dma.h
View File

@ -81,10 +81,10 @@ enum dma_index_type {
#define DMA_TRANSFER_WIDTH_16BIT 1
#define DMA_TRANSFER_WIDTH_32BIT 2
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_BURST_INCR1 0
#define DMA_BURST_INCR4 1
#define DMA_BURST_INCR8 2
#define DMA_BURST_INCR16 3
#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88)
#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C)
@ -174,13 +174,13 @@ typedef struct dma_device {
uint8_t dst_burst_size;
uint8_t src_width;
uint8_t dst_width;
dma_lli_ctrl_t *lli_cfg;
uint8_t intr; /* private param */
dma_lli_ctrl_t *lli_cfg;/* private param*/
} dma_device_t;
#define DMA_DEV(dev) ((dma_device_t *)dev)
int dma_register(enum dma_index_type index, const char *name);
int dma_allocate_register(const char *name);
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size);
#ifdef __cplusplus

81
drivers/bl702_driver/hal_drv/src/hal_dma.c
View File

@ -81,13 +81,13 @@ int dma_open(struct device *dev, uint16_t oflag)
/* Disable all interrupt */
DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK);
/* Enable uart interrupt*/
CPU_Interrupt_Disable(DMA_ALL_IRQn);
DMA_Disable();
DMA_Channel_Disable(dma_device->ch);
dma_device->intr = 0;
chCfg.ch = dma_device->ch;
chCfg.dir = dma_device->direction;
chCfg.srcPeriph = dma_device->src_req;
@ -103,7 +103,7 @@ int dma_open(struct device *dev, uint16_t oflag)
DMA_Enable();
Interrupt_Handler_Register(DMA_ALL_IRQn, DMA0_IRQ);
/* Enable uart interrupt*/
/* Enable dma interrupt*/
CPU_Interrupt_Enable(DMA_ALL_IRQn);
return 0;
}
@ -124,14 +124,14 @@ int dma_control(struct device *dev, int cmd, void *args)
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK);
dma_device->intr = 1;
break;
case DEVICE_CTRL_CLR_INT:
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK);
dma_device->intr = 0;
break;
case DEVICE_CTRL_GET_INT:
@ -185,6 +185,7 @@ int dma_close(struct device *dev)
DMA_Channel_Disable(dma_device->ch);
DMA_Channel_Init(&chCfg);
dma_device->intr = 0;
return 0;
}
@ -210,65 +211,6 @@ int dma_register(enum dma_index_type index, const char *name)
return device_register(dev, name);
}
static BL_Err_Type dma_scan_unregister_device(uint8_t *allocate_index)
{
struct device *dev;
dlist_t *node;
uint8_t dma_index = 0;
uint32_t dma_handle[DMA_MAX_INDEX];
for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) {
dma_handle[dma_index] = 0xff;
}
/* get registered dma handle list*/
dlist_for_each(node, device_get_list_header())
{
dev = dlist_entry(node, struct device, list);
if (dev->type == DEVICE_CLASS_DMA) {
dma_handle[(((uint32_t)dev - (uint32_t)dmax_device) / sizeof(dma_device_t)) % DMA_MAX_INDEX] = SET;
}
}
for (dma_index = 0; dma_index < DMA_MAX_INDEX; dma_index++) {
if (dma_handle[dma_index] == 0xff) {
*allocate_index = dma_index;
return SUCCESS;
}
}
return ERROR;
}
int dma_allocate_register(const char *name)
{
struct device *dev;
uint8_t index;
if (DMA_MAX_INDEX == 0) {
return -DEVICE_EINVAL;
}
if (dma_scan_unregister_device(&index) == ERROR) {
return -DEVICE_ENOSPACE;
}
dev = &(dmax_device[index].parent);
dev->open = dma_open;
dev->close = dma_close;
dev->control = dma_control;
// dev->write = dma_write;
// dev->read = dma_read;
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_DMA;
dev->handle = NULL;
return device_register(dev, name);
}
/**
* @brief
*
@ -280,14 +222,13 @@ int dma_allocate_register(const char *name)
*/
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size)
{
#if defined(BSP_USING_DMA0_CH0) || defined(BSP_USING_DMA0_CH1) || defined(BSP_USING_DMA0_CH2) || defined(BSP_USING_DMA0_CH3) || \
defined(BSP_USING_DMA0_CH4) || defined(BSP_USING_DMA0_CH5) || defined(BSP_USING_DMA0_CH6) || defined(BSP_USING_DMA0_CH7)
#ifdef BSP_USING_DMA
uint32_t malloc_count;
uint32_t remain_len;
uint32_t actual_transfer_len = 0;
uint32_t actual_transfer_offset = 0;
dma_control_data_t dma_ctrl_cfg;
bool intr = false;
dma_device_t *dma_device = (dma_device_t *)dev;
@ -324,6 +265,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
}
dma_ctrl_cfg = (dma_control_data_t)(BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL));
intr = dma_device->intr;
malloc_count = actual_transfer_len / 4095;
remain_len = actual_transfer_len % 4095;
@ -335,15 +277,14 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
dma_device->lli_cfg = (dma_lli_ctrl_t *)realloc(dma_device->lli_cfg, sizeof(dma_lli_ctrl_t) * malloc_count);
if (dma_device->lli_cfg) {
dma_ctrl_cfg.bits.TransferSize = 4095;
dma_ctrl_cfg.bits.I = 0;
/*transfer_size will be integer multiple of 4095*n or 4095*2*n or 4095*4*n,(n>0) */
for (uint32_t i = 0; i < malloc_count; i++) {
dma_device->lli_cfg[i].src_addr = src_addr;
dma_device->lli_cfg[i].dst_addr = dst_addr;
dma_device->lli_cfg[i].nextlli = 0;
dma_ctrl_cfg.bits.TransferSize = 4095;
dma_ctrl_cfg.bits.I = 0;
if (dma_ctrl_cfg.bits.SI) {
src_addr += actual_transfer_offset;
}
@ -356,7 +297,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
if (remain_len) {
dma_ctrl_cfg.bits.TransferSize = remain_len;
}
dma_ctrl_cfg.bits.I = 0;
dma_ctrl_cfg.bits.I = intr;
if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) {
dma_device->lli_cfg[i].nextlli = (uint32_t)&dma_device->lli_cfg[0];

8
drivers/bl702_driver/hal_drv/src/hal_usb.c
View File

@ -408,8 +408,8 @@ int usb_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t siz
usb_lli_list.cfg.bits.TransferSize = size;
usb_lli_list.cfg.bits.DI = 0;
usb_lli_list.cfg.bits.SI = 1;
usb_lli_list.cfg.bits.SBSize = DMA_BURST_16BYTE;
usb_lli_list.cfg.bits.DBSize = DMA_BURST_1BYTE;
usb_lli_list.cfg.bits.SBSize = DMA_BURST_INCR16;
usb_lli_list.cfg.bits.DBSize = DMA_BURST_INCR1;
dma_channel_update(usb_device->tx_dma, (void *)((uint32_t)&usb_lli_list));
dma_channel_start(usb_device->tx_dma);
return 0;
@ -433,8 +433,8 @@ int usb_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
usb_lli_list.cfg.bits.TransferSize = size;
usb_lli_list.cfg.bits.DI = 1;
usb_lli_list.cfg.bits.SI = 0;
usb_lli_list.cfg.bits.SBSize = DMA_BURST_1BYTE;
usb_lli_list.cfg.bits.DBSize = DMA_BURST_16BYTE;
usb_lli_list.cfg.bits.SBSize = DMA_BURST_INCR1;
usb_lli_list.cfg.bits.DBSize = DMA_BURST_INCR16;
dma_channel_update(usb_device->rx_dma, (void *)((uint32_t)&usb_lli_list));
dma_channel_start(usb_device->rx_dma);
return 0;

4
examples/adc/adc_dma/main.c
View File

@ -79,8 +79,8 @@ int main(void)
DMA_DEV(dma_ch0)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch0)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch0)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch0)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch0)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch0)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch0)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch0)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch0)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
device_open(dma_ch0, 0);

8
examples/audio_cube/data_protocol.c
View File

@ -362,8 +362,8 @@ uint8_t isp_uart_init(isp_obj_t *isp_obj)
DMA_DEV(dma_ch0)->dst_req = DMA_REQUEST_UART0_TX;
DMA_DEV(dma_ch0)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch0)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch0)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch0)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch0)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch0)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch0)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch0)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch0, 0);
@ -384,8 +384,8 @@ uint8_t isp_uart_init(isp_obj_t *isp_obj)
// DMA_DEV(dma_ch1)->dst_req = DMA_REQUEST_NONE;
// DMA_DEV(dma_ch1)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
// DMA_DEV(dma_ch1)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
// DMA_DEV(dma_ch1)->src_burst_size = DMA_BURST_1BYTE;
// DMA_DEV(dma_ch1)->dst_burst_size = DMA_BURST_1BYTE;
// DMA_DEV(dma_ch1)->src_burst_size = DMA_BURST_INCR1;
// DMA_DEV(dma_ch1)->dst_burst_size = DMA_BURST_INCR1;
// DMA_DEV(dma_ch1)->src_width = DMA_TRANSFER_WIDTH_8BIT;
// DMA_DEV(dma_ch1)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
// device_open(dma_ch1, 0);

8
examples/audio_cube/wav_play_from_isp.c
View File

@ -221,8 +221,8 @@ static int isp_wav_play_init(struct audio_dev *audio_dev, uint8_t mode, uint8_t
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_I2S_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
switch (I2S_DEV(audio_dev->device)->data_size * I2S_DEV(audio_dev->device)->channel_num) {
@ -341,8 +341,8 @@ record_conf:
DMA_DEV(dma_ch3)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch3)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
switch (I2S_DEV(audio_dev->device)->data_size * I2S_DEV(audio_dev->device)->channel_num) {

10
examples/dac/dac_dma/main.c
View File

@ -69,11 +69,7 @@ int main(void)
MSG("device open success\r\n");
}
/* register & open dma device */
if (dma_allocate_register("dac_dma") == SUCCESS) {
MSG("dma allocate success\r\n");
}
dma_register(DMA0_CH0_INDEX, "dac_dma");
struct device *dac_dma = device_find("dac_dma");
if (dac_dma) {
@ -83,8 +79,8 @@ int main(void)
DMA_DEV(dac_dma)->dst_req = DMA_REQUEST_DAC0;
DMA_DEV(dac_dma)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dac_dma)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dac_dma)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dac_dma)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dac_dma)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dac_dma)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dac_dma)->src_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dac_dma)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
device_open(dac_dma, 0);

10
examples/dac/dac_mono_play_form_flash/main.c
View File

@ -39,11 +39,7 @@ int main(void)
MSG("device open success\r\n");
}
/* register & open dma device */
if (dma_allocate_register("dac_dma") == SUCCESS) {
MSG("dma allocate success\r\n");
}
dma_register(DMA0_CH0_INDEX, "dac_dma");
struct device *dac_dma = device_find("dac_dma");
if (dac_dma) {
@ -53,8 +49,8 @@ int main(void)
DMA_DEV(dac_dma)->dst_req = DMA_REQUEST_DAC0;
DMA_DEV(dac_dma)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dac_dma)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dac_dma)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dac_dma)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dac_dma)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dac_dma)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dac_dma)->src_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dac_dma)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
device_open(dac_dma, 0);

4
examples/dma/dma_m2m/main.c
View File

@ -57,8 +57,8 @@ int main(void)
DMA_DEV(dma_ch0)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch0)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch0)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch0)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch0)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch0)->src_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch0)->dst_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch0)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch0)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
device_open(dma_ch0, 0);

4
examples/dma/dma_uart_p2p/main.c
View File

@ -55,8 +55,8 @@ int main(void)
DMA_DEV(dma_ch0)->dst_req = DMA_REQUEST_UART1_TX;
DMA_DEV(dma_ch0)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch0)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch0)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch0)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch0)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch0)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch0)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch0)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch0, 0);

4
examples/i2s/i2s_play_from_flash/main.c
View File

@ -93,8 +93,8 @@ int main(void)
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_INCR4;
device_open(dma_ch2, 0);
/* connect i2s device and dma device */

8
examples/i2s/i2s_play_from_record/main.c
View File

@ -87,8 +87,8 @@ int main(void)
DMA_DEV(dma_ch3)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch3)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
device_open(dma_ch3, 0);
@ -110,8 +110,8 @@ int main(void)
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_I2S_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
device_open(dma_ch2, 0);

4
examples/i2s/i2s_play_from_sd/wav_play_from_sd_card.c
View File

@ -232,8 +232,8 @@ static int sd_wav_play_init(audio_dev_t *audio_dev, const TCHAR *path)
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_I2S_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
switch (I2S_DEV(audio_dev->device)->data_size * I2S_DEV(audio_dev->device)->channel_num) {

4
examples/spi/spi_i2s_mono_play/main.c
View File

@ -112,8 +112,8 @@ uint8_t spi_init(void)
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_SPI0_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
device_open(dma_ch2, 0);

8
examples/spi/spi_i2s_mono_record/main.c
View File

@ -104,8 +104,8 @@ uint8_t spi_init(void)
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_SPI0_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
device_open(dma_ch2, 0);
@ -123,8 +123,8 @@ uint8_t spi_init(void)
DMA_DEV(dma_ch3)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch3)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
device_open(dma_ch3, 0);

4
examples/uart/uart_dma/main.c
View File

@ -67,8 +67,8 @@ int main(void)
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_UART1_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch2, 0);

12
examples/usb/usb_audio_mic_speaker/main.c
View File

@ -547,8 +547,8 @@ void audio_init()
DMA_DEV(dma_ch2_i2s_tx)->dst_req = DMA_REQUEST_I2S_TX;
DMA_DEV(dma_ch2_i2s_tx)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2_i2s_tx)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2_i2s_tx)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2_i2s_tx)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2_i2s_tx)->dst_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch2_i2s_tx)->src_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch2_i2s_tx)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch2_i2s_tx)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
device_open(dma_ch2_i2s_tx, 0);
@ -570,8 +570,8 @@ void audio_init()
DMA_DEV(dma_ch3_i2s_rx)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch3_i2s_rx)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3_i2s_rx)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3_i2s_rx)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3_i2s_rx)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3_i2s_rx)->dst_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch3_i2s_rx)->src_burst_size = DMA_BURST_INCR4;
DMA_DEV(dma_ch3_i2s_rx)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch3_i2s_rx)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
device_open(dma_ch3_i2s_rx, 0);
@ -612,8 +612,8 @@ int main(void)
DMA_DEV(dma_ch4_usb_tx)->dst_req = DMA_REQUEST_USB_EP1;
DMA_DEV(dma_ch4_usb_tx)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch4_usb_tx)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch4_usb_tx)->src_burst_size = DMA_BURST_16BYTE;
DMA_DEV(dma_ch4_usb_tx)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch4_usb_tx)->src_burst_size = DMA_BURST_INCR16;
DMA_DEV(dma_ch4_usb_tx)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch4_usb_tx)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch4_usb_tx)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch4_usb_tx, 0);

4
examples/usb/usb_audio_mouse/main.c
View File

@ -734,8 +734,8 @@ int main(void)
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_USB_EP1;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_16BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_INCR16;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch2, 0);

4
examples/usb/usb_video/main.c
View File

@ -562,8 +562,8 @@ int main(void)
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_USB_EP1;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_16BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_INCR16;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_INCR1;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch2, 0);