diff --git a/drivers/bl702_driver/hal_drv/src/hal_pm.c b/drivers/bl702_driver/hal_drv/src/hal_pm.c
index 23291dd5..ed0fa45c 100644
--- a/drivers/bl702_driver/hal_drv/src/hal_pm.c
+++ b/drivers/bl702_driver/hal_drv/src/hal_pm.c
@@ -44,7 +44,7 @@ SPI_Flash_Cfg_Type *flash_cfg;
 #define PM_PDS_PLL_POWER_OFF     1
 #define PM_PDS_RF_POWER_OFF      1
 #define PM_PDS_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_1P10V
-#define PM_HBN_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_0P90V
+#define PM_HBN_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_1P00V
 
 void HBN_OUT0_IRQ(void);
 void HBN_OUT1_IRQ(void);
@@ -944,6 +944,8 @@ ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint3
         case PM_PDS_LEVEL_31:
             pPdsCfg = &pdsCfgLevel31;
             break;
+        default:
+            return;
     }
 
 #if PM_PDS_FLASH_POWER_OFF
@@ -983,10 +985,6 @@ ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint3
     pPdsCfg->pdsCtl.pdsLdoVol = PM_PDS_LDO_LEVEL_DEFAULT;
     pPdsCfg->pdsCtl.pdsLdoVselEn = 1;
 
-    if (BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_MASK)) {
-        pPdsCfg->pdsCtl.gpioIePuPd = 0;
-    }
-
 #if PM_PDS_RF_POWER_OFF == 0
     pPdsCfg->pdsCtl.pdsCtlRfSel = 0;
 #endif
@@ -1233,7 +1231,8 @@ ATTR_TCM_SECTION void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8
     BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
 
     while (1) {
-        BL702_Delay_MS(1000);
+        arch_delay_ms(100);
+        GLB_SW_POR_Reset();
     }
 }