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[feat][bl702_driver] set some bits zero in xtal_cfg at default

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This commit is contained in:
jzlv 2021-11-22 10:59:28 +08:00
parent 68977a1658
commit aa4bec3776
1 changed files with 31 additions and 0 deletions
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31
drivers/bl702_driver/startup/system_bl702.c
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@ -67,6 +67,37 @@ void SystemInit(void)
/* global IRQ disable */
__disable_irq();
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, 0);
BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, 0);
BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_RDY_SEL_AON, 0);
BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_RDY_INT_SEL_AON, 0);
BL_WR_REG(AON_BASE, AON_TSEN, tmpVal);
for (i = 0; i < 20000; i++) {
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_XTAL_EXT_SEL_AON);
BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_EXT_SEL_AON);
BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
if (BL_IS_REG_BIT_SET(BL_RD_REG(GLB_BASE, GLB_CLK_CFG0), GLB_CHIP_RDY))
break;
}
tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
tmpVal |= (1 << 8); /*mask pds wakeup*/
tmpVal |= (1 << 10); /*mask rf done*/