diff --git a/drivers/bl702_driver/hal_drv/default_config/dac_config.h b/drivers/bl702_driver/hal_drv/default_config/dac_config.h
index 7ae1e8e8..2a1e81db 100644
--- a/drivers/bl702_driver/hal_drv/default_config/dac_config.h
+++ b/drivers/bl702_driver/hal_drv/default_config/dac_config.h
@@ -1,5 +1,5 @@
-#ifndef _ADC_CONFIG_H
-#define _ADC_CONFIG_H
+#ifndef _DAC_CONFIG_H
+#define _DAC_CONFIG_H
 
 #define DAC_REF_SEL      (0)
 #define DAC_EXT_REF_GPIO (7)
diff --git a/drivers/bl702_driver/hal_drv/default_config/uart_config.h b/drivers/bl702_driver/hal_drv/default_config/uart_config.h
index 195a9c97..4a31ddd3 100644
--- a/drivers/bl702_driver/hal_drv/default_config/uart_config.h
+++ b/drivers/bl702_driver/hal_drv/default_config/uart_config.h
@@ -1,7 +1,6 @@
 #ifndef _UART_CONFIG_H
 #define _UART_CONFIG_H
 
-#define UART_CLOCK_SOURCE_96M_ENABLE (1)
 #define UART_CTS_FLOWCONTROL_ENABLE  (0)
 #define UART_RTS_FLOWCONTROL_ENABLE  (0)
 #define UART_RX_DEGLITCH_ENABLE      (0)
diff --git a/drivers/bl702_driver/hal_drv/inc/hal_acomp.h b/drivers/bl702_driver/hal_drv/inc/hal_acomp.h
index 20f3ba3d..8fc1b8d4 100644
--- a/drivers/bl702_driver/hal_drv/inc/hal_acomp.h
+++ b/drivers/bl702_driver/hal_drv/inc/hal_acomp.h
@@ -2,11 +2,10 @@
 #define __HAL_ACOMP_H__
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
 #include "hal_common.h"
-#include "drv_device.h"
 
 enum acomp_channel_type {
     ACOMP_CHANNEL_ADC_CHANNEL0, /*!< Analog compare channel,ADC input channel 0 */
@@ -38,18 +37,24 @@ enum acomp_hysteresis_vol_type {
     ACOMP_HYSTERESIS_VOLT_70MV, /*!< Analog compare hysteresis voltage 70mv */
 };
 
+enum acomp_it_type {
+    ACOMP_POSITIVE_IT = 1 << 0,
+    ACOMP_NEGATIVE_IT = 1 << 1,
+};
+
 typedef struct acomp_device {
-    struct device parent;
-    uint8_t id;
     enum acomp_channel_type pos_ch;
     enum acomp_channel_type neg_ch;
     enum acomp_hysteresis_vol_type pos_hysteresis_vol;
     enum acomp_hysteresis_vol_type neg_hysteresis_vol;
 } acomp_device_t;
 
-
-void acomp_init(acomp_device_t *device);
-int acomp_get_result(acomp_device_t *device);
+void acomp_init(uint8_t idx,acomp_device_t *device);
+void acomp_enable(uint8_t idx);
+void acomp_disable(uint8_t idx);
+void acomp_interrupt_mask(uint8_t idx,uint32_t flag);
+void acomp_interrupt_unmask(uint8_t idx,uint32_t flag);
+int acomp_get_result(uint8_t idx);
 
 #ifdef __cplusplus
 }
diff --git a/drivers/bl702_driver/hal_drv/inc/hal_adc.h b/drivers/bl702_driver/hal_drv/inc/hal_adc.h
index cdd3421c..bf9665c3 100644
--- a/drivers/bl702_driver/hal_drv/inc/hal_adc.h
+++ b/drivers/bl702_driver/hal_drv/inc/hal_adc.h
@@ -140,15 +140,13 @@ enum adc_it_type {
     ADC_FIFO_IT = 1 << 5,
 };
 
-typedef struct
-{
+typedef struct {
     uint8_t *pos_channel;
     uint8_t *neg_channel;
     uint8_t num;
 } adc_channel_cfg_t;
 
-typedef struct
-{
+typedef struct {
     int8_t posChan; /*!< Positive channel */
     int8_t negChan; /*!< Negative channel */
     uint16_t value; /*!< ADC value */
diff --git a/drivers/bl702_driver/hal_drv/inc/hal_spi.h b/drivers/bl702_driver/hal_drv/inc/hal_spi.h
index 3147418a..ea4b269a 100644
--- a/drivers/bl702_driver/hal_drv/inc/hal_spi.h
+++ b/drivers/bl702_driver/hal_drv/inc/hal_spi.h
@@ -24,7 +24,7 @@
 #define __HAL_SPI__H__
 
 #ifdef __cplusplus
-extern "C"{
+extern "C" {
 #endif
 
 #include "hal_common.h"
@@ -95,6 +95,8 @@ typedef struct spi_device {
     uint8_t clk_phase;
     uint8_t datasize;
     uint8_t fifo_threshold;
+    uint8_t pin_swap_enable; /*swap mosi and miso*/
+    uint8_t delitch_cnt;
     void *tx_dma;
     void *rx_dma;
 } spi_device_t;
diff --git a/drivers/bl702_driver/hal_drv/src/hal_acomp.c b/drivers/bl702_driver/hal_drv/src/hal_acomp.c
index 7f6080ce..79869aa6 100644
--- a/drivers/bl702_driver/hal_drv/src/hal_acomp.c
+++ b/drivers/bl702_driver/hal_drv/src/hal_acomp.c
@@ -1,12 +1,12 @@
 #include "hal_acomp.h"
 #include "bl702_acomp.h"
-#include "bl702_hbn.h"
+#include "hbn_reg.h"
 
-void acomp_init(acomp_device_t *device)
+void acomp_init(uint8_t idx, acomp_device_t *device)
 {
     uint32_t tmpVal;
 
-    if (device->id == AON_ACOMP0_ID) {
+    if (idx == 0) {
         tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
         tmpVal &= ~(1 << 20);
         tmpVal &= ~(1 << 21);
@@ -25,16 +25,8 @@ void acomp_init(acomp_device_t *device)
         tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_BIAS_PROG, AON_ACOMP_BIAS_POWER_MODE1);
         tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELP, device->pos_hysteresis_vol);
         tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELN, device->neg_hysteresis_vol);
-        /*enable acomp*/
-        tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP0_EN);
-        tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);
+        BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);
 
-        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
-        tmpVal |= (1 << 20);
-        tmpVal |= (1 << 21);
-        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
-
-        HBN_Clear_IRQ(HBN_INT_ACOMP0);
     } else {
         tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
         tmpVal &= ~(1 << 22);
@@ -54,36 +46,101 @@ void acomp_init(acomp_device_t *device)
         tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_BIAS_PROG, AON_ACOMP_BIAS_POWER_MODE1);
         tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELP, device->pos_hysteresis_vol);
         tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELN, device->neg_hysteresis_vol);
-        /*enable acomp*/
-        tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP1_EN);
-        tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);
-
-        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
-        tmpVal |= (1 << 22);
-        tmpVal |= (1 << 23);
-        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
-
-        HBN_Clear_IRQ(HBN_INT_ACOMP1);
+        BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);
     }
 }
 
-int acomp_get_result(acomp_device_t *device)
+void acomp_enable(uint8_t idx)
+{
+    uint32_t tmpVal;
+    if (idx == 0) {
+        tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL);
+        tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP0_EN);
+        BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);
+    } else {
+        tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL);
+        tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP1_EN);
+        BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);
+    }
+}
+
+void acomp_disable(uint8_t idx)
+{
+    uint32_t tmpVal;
+    if (idx == 0) {
+        tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP0_EN);
+        BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal);
+    } else {
+        tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP1_EN);
+        BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal);
+    }
+}
+
+void acomp_interrupt_mask(uint8_t idx, uint32_t flag)
+{
+    uint32_t tmpVal;
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    if (idx == 0) {
+        tmpVal &= ~(flag << 20);
+    } else {
+        tmpVal &= ~(flag << 22);
+    }
+}
+
+void acomp_interrupt_unmask(uint8_t idx, uint32_t flag)
+{
+    uint32_t tmpVal;
+
+    if (idx == 0) {
+        /* set clear bit */
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+        tmpVal |= (1 << 20);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+        /* unset clear bit */
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+        tmpVal &= (~(1 << 20));
+        BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        tmpVal |= (flag << 20);
+    } else {
+        /* set clear bit */
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+        tmpVal |= (1 << 22);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+        /* unset clear bit */
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+        tmpVal &= (~(1 << 22));
+        BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        tmpVal |= (flag << 22);
+    }
+
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+}
+
+int acomp_get_result(uint8_t idx)
 {
     uint32_t tmpVal;
     tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP_CTRL);
 
     /* Disable ACOMP first */
-    if (device->id == AON_ACOMP0_ID) {
+    if (idx == 0) {
         if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP0_OUT_RAW)) {
-            return SET;
+            return 1;
         } else {
-            return RESET;
+            return 0;
         }
     } else {
         if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP1_OUT_RAW)) {
-            return SET;
+            return 1;
         } else {
-            return RESET;
+            return 0;
         }
     }
 }
\ No newline at end of file
diff --git a/drivers/bl702_driver/hal_drv/src/hal_adc.c b/drivers/bl702_driver/hal_drv/src/hal_adc.c
index 1a32f55f..fd482fc4 100644
--- a/drivers/bl702_driver/hal_drv/src/hal_adc.c
+++ b/drivers/bl702_driver/hal_drv/src/hal_adc.c
@@ -21,7 +21,6 @@
  *
  */
 #include "hal_adc.h"
-#include "hal_gpio.h"
 #include "hal_clock.h"
 #include "bl702_glb.h"
 #include "bl702_dma.h"
@@ -50,18 +49,18 @@ uint8_t adc_check_channel_status(uint8_t *pos_list, uint8_t *neg_list, uint16_t
     uint16_t i = 0;
 
     uint8_t channel_io_reference_table[] = {
-        GPIO_PIN_8,  /* CH0 IO */
-        GPIO_PIN_15, /* CH1 IO */
-        GPIO_PIN_17, /* CH2 IO */
-        GPIO_PIN_11, /* CH3 IO */
-        GPIO_PIN_12, /* CH4 IO */
-        GPIO_PIN_14, /* CH5 IO */
-        GPIO_PIN_7,  /* CH6 IO */
-        GPIO_PIN_9,  /* CH7 IO */
-        GPIO_PIN_18, /* CH8 IO */
-        GPIO_PIN_19, /* CH9 IO */
-        GPIO_PIN_20, /* CH10 IO */
-        GPIO_PIN_21, /* CH11 IO */
+        GLB_GPIO_PIN_8,  /* CH0 IO */
+        GLB_GPIO_PIN_15, /* CH1 IO */
+        GLB_GPIO_PIN_17, /* CH2 IO */
+        GLB_GPIO_PIN_11, /* CH3 IO */
+        GLB_GPIO_PIN_12, /* CH4 IO */
+        GLB_GPIO_PIN_14, /* CH5 IO */
+        GLB_GPIO_PIN_7,  /* CH6 IO */
+        GLB_GPIO_PIN_9,  /* CH7 IO */
+        GLB_GPIO_PIN_18, /* CH8 IO */
+        GLB_GPIO_PIN_19, /* CH9 IO */
+        GLB_GPIO_PIN_20, /* CH10 IO */
+        GLB_GPIO_PIN_21, /* CH11 IO */
 
     };
 
@@ -90,6 +89,9 @@ int adc_open(struct device *dev, uint16_t oflag)
     ADC_CFG_Type adc_cfg = { 0 };
     ADC_FIFO_Cfg_Type adc_fifo_cfg = { 0 };
 
+    CPU_Interrupt_Disable(GPADC_DMA_IRQn);
+    ADC_IntMask(ADC_INT_ALL, MASK);
+
     adc_cfg.clkDiv = adc_device->clk_div;
 
     adc_cfg.vref = adc_device->vref;
@@ -125,8 +127,6 @@ int adc_open(struct device *dev, uint16_t oflag)
         adc_fifo_cfg.dmaEn = ENABLE;
     }
 
-    ADC_IntMask(ADC_INT_ALL, MASK);
-
     ADC_Disable();
     ADC_Enable();
 
@@ -146,7 +146,26 @@ int adc_open(struct device *dev, uint16_t oflag)
  */
 int adc_close(struct device *dev)
 {
-    ADC_Disable();
+    uint32_t tmpVal;
+
+    ADC_IntMask(ADC_INT_ALL, MASK);
+
+    /* disable convert start */
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CONV_START);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
+
+    /*disable adc */
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
+
+    /*disable vbat */
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
+
+    ADC_Reset();
     return 0;
 }
 
@@ -165,7 +184,7 @@ int adc_control(struct device *dev, int cmd, void *args)
     uint8_t rlt = 0;
 
     switch (cmd) {
-        case DEVICE_CTRL_SET_INT /* constant-expression */: {
+        case DEVICE_CTRL_SET_INT: {
             uint32_t offset = __builtin_ctz((uint32_t)args);
             while ((2 <= offset) && (offset < 6)) {
                 if ((uint32_t)args & (1 << offset)) {
@@ -178,7 +197,7 @@ int adc_control(struct device *dev, int cmd, void *args)
             break;
         }
 
-        case DEVICE_CTRL_CLR_INT /* constant-expression */: {
+        case DEVICE_CTRL_CLR_INT: {
             uint32_t offset = __builtin_ctz((uint32_t)args);
             while ((2 <= offset) && (offset < 6)) {
                 if ((uint32_t)args & (1 << offset)) {
@@ -191,15 +210,13 @@ int adc_control(struct device *dev, int cmd, void *args)
             break;
         }
 
-        case DEVICE_CTRL_GET_INT /* constant-expression */:
-            /* code */
+        case DEVICE_CTRL_GET_INT:
             break;
 
-        case DEVICE_CTRL_CONFIG /* constant-expression */:
-            /* code */
+        case DEVICE_CTRL_CONFIG:
             break;
 
-        case DEVICE_CTRL_ADC_CHANNEL_CONFIG /* constant-expression */:
+        case DEVICE_CTRL_ADC_CHANNEL_CONFIG:
             if (adc_channel_cfg->num == 1) {
                 ADC_Channel_Config(*adc_channel_cfg->pos_channel, *adc_channel_cfg->neg_channel, adc_device->continuous_conv_mode);
                 rlt = adc_check_channel_status(adc_channel_cfg->pos_channel, adc_channel_cfg->neg_channel, 1);
@@ -210,12 +227,23 @@ int adc_control(struct device *dev, int cmd, void *args)
 
             break;
 
-        case DEVICE_CTRL_ADC_CHANNEL_START /* constant-expression */:
-            /* code */
-            ADC_Start();
-            break;
+        case DEVICE_CTRL_ADC_CHANNEL_START: {
+            uint32_t regCmd;
 
-        case DEVICE_CTRL_ADC_CHANNEL_STOP /* constant-expression */: {
+            /* disable convert start */
+            regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+            regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START);
+            BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);
+
+            BL702_Delay_US(100);
+
+            /* enable convert start */
+            regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+            regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START);
+            BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd);
+        } break;
+
+        case DEVICE_CTRL_ADC_CHANNEL_STOP: {
             uint32_t tmpVal;
 
             /* disable convert start */
@@ -307,8 +335,6 @@ float adc_get_tsen(uint16_t tsen_offset)
  *
  * @param index
  * @param name
- * @param flag
- * @param adc_user_cfg
  * @return int
  */
 int adc_register(enum adc_index_type index, const char *name)
diff --git a/drivers/bl702_driver/hal_drv/src/hal_dac.c b/drivers/bl702_driver/hal_drv/src/hal_dac.c
index 22fd69a6..7ec2a994 100644
--- a/drivers/bl702_driver/hal_drv/src/hal_dac.c
+++ b/drivers/bl702_driver/hal_drv/src/hal_dac.c
@@ -33,7 +33,13 @@ static dac_device_t dacx_device[] = {
     DAC_CONFIG,
 #endif
 };
-
+/**
+ * @brief
+ *
+ * @param dev
+ * @param oflag
+ * @return int
+ */
 int dac_open(struct device *dev, uint16_t oflag)
 {
     GLB_GPIP_DAC_ChanA_Cfg_Type chCfg = { 0 };
@@ -136,40 +142,59 @@ int dac_open(struct device *dev, uint16_t oflag)
 
     return 0;
 }
+/**
+ * @brief
+ *
+ * @param dev
+ * @return int
+ */
 int dac_close(struct device *dev)
 {
+    GLB_GPIP_DAC_ChanA_Cfg_Type chCfg = { 0 };
+    GLB_GPIP_DAC_Cfg_Type dacCfg = { 0 };
+    GLB_GPIP_DAC_Init(&dacCfg);
+    GLB_GPIP_DAC_Set_ChanA_Config(&chCfg);
+    GLB_GPIP_DAC_Set_ChanB_Config((GLB_GPIP_DAC_ChanB_Cfg_Type *)&chCfg);
     return 0;
 }
+/**
+ * @brief
+ *
+ * @param dev
+ * @param cmd
+ * @param args
+ * @return int
+ */
 int dac_control(struct device *dev, int cmd, void *args)
 {
     dac_device_t *dac_device = (dac_device_t *)dev;
 
     switch (cmd) {
-        case DEVICE_CTRL_SET_INT /* constant-expression */:
+        case DEVICE_CTRL_SET_INT:
 
             break;
 
-        case DEVICE_CTRL_CLR_INT /* constant-expression */:
+        case DEVICE_CTRL_CLR_INT:
 
             break;
 
-        case DEVICE_CTRL_GET_INT /* constant-expression */:
+        case DEVICE_CTRL_GET_INT:
             /* code */
             break;
 
-        case DEVICE_CTRL_CONFIG /* constant-expression */:
+        case DEVICE_CTRL_CONFIG:
             /* code */
             break;
 
-        case DEVICE_CTRL_RESUME /* constant-expression */:
+        case DEVICE_CTRL_RESUME:
 
             break;
 
-        case DEVICE_CTRL_SUSPEND /* constant-expression */:
+        case DEVICE_CTRL_SUSPEND:
 
             break;
 
-        case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
+        case DEVICE_CTRL_ATTACH_TX_DMA:
             dac_device->tx_dma = (struct device *)args;
             break;
 
@@ -179,6 +204,15 @@ int dac_control(struct device *dev, int cmd, void *args)
 
     return 0;
 }
+/**
+ * @brief
+ *
+ * @param dev
+ * @param pos
+ * @param buffer
+ * @param size
+ * @return int
+ */
 int dac_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
 {
     dac_channel_t channel = (dac_channel_t)pos;
@@ -215,11 +249,14 @@ int dac_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t siz
 
     return 0;
 }
-int dac_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
-{
-    return 0;
-}
 
+/**
+ * @brief
+ *
+ * @param index
+ * @param name
+ * @return int
+ */
 int dac_register(enum dac_index_type index, const char *name)
 {
     struct device *dev;
diff --git a/drivers/bl702_driver/hal_drv/src/hal_i2c.c b/drivers/bl702_driver/hal_drv/src/hal_i2c.c
index f998fdc9..cbc88824 100644
--- a/drivers/bl702_driver/hal_drv/src/hal_i2c.c
+++ b/drivers/bl702_driver/hal_drv/src/hal_i2c.c
@@ -21,9 +21,7 @@
  *
  */
 #include "hal_i2c.h"
-#include "hal_gpio.h"
 #include "bl702_i2c.h"
-#include "bl702_i2c_gpio_sim.h"
 #include "bl702_glb.h"
 
 static i2c_device_t i2cx_device[I2C_MAX_INDEX] = {
diff --git a/drivers/bl702_driver/hal_drv/src/hal_i2s.c b/drivers/bl702_driver/hal_drv/src/hal_i2s.c
index 759a22a4..974967b1 100644
--- a/drivers/bl702_driver/hal_drv/src/hal_i2s.c
+++ b/drivers/bl702_driver/hal_drv/src/hal_i2s.c
@@ -196,14 +196,15 @@ int i2s_open(struct device *dev, uint16_t oflag)
         I2S_Enable(I2S_ROLE_MASTER);
     else if (i2s_device->iis_mode == I2S_MODE_SLAVE)
         I2S_Enable(I2S_ROLE_SLAVE);
-    return SUCCESS;
+    return 0;
 }
 
 int i2s_close(struct device *dev)
 {
     //i2s_device_t* uart_device = (i2s_device_t*)dev;
     I2S_Disable();
-    return SUCCESS;
+    GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_I2S);
+    return 0;
 }
 
 int i2s_control(struct device *dev, int cmd, void *args)
diff --git a/drivers/bl702_driver/hal_drv/src/hal_mjpeg.c b/drivers/bl702_driver/hal_drv/src/hal_mjpeg.c
index dc00bce5..8da4d90a 100644
--- a/drivers/bl702_driver/hal_drv/src/hal_mjpeg.c
+++ b/drivers/bl702_driver/hal_drv/src/hal_mjpeg.c
@@ -26,6 +26,8 @@
 
 void mjpeg_init(mjpeg_device_t *mjpeg_cfg)
 {
+    MJPEG_Packet_Type packetCfg = { 0 };
+
     MJPEG_CFG_Type mjpegCfg = {
         .burst = MJPEG_BURST_INCR16,
         .quality = mjpeg_cfg->quality,
@@ -48,17 +50,15 @@ void mjpeg_init(mjpeg_device_t *mjpeg_cfg)
         .horizationalDmy = DISABLE,
     };
 
-    static MJPEG_Packet_Type packetCfg = {
-        .packetEnable = DISABLE,
-        .endToTail = DISABLE,
-        .frameHead = 0,
-        .frameTail = DISABLE,
-        .packetHead = 0,
-        .packetBody = 0,
-        .packetTail = 0,
-    };
     GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_MJPEG);
 
+    uint32_t tmpVal;
+
+    /* Disable mjpeg module */
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);
+
     MJPEG_Init(&mjpegCfg);
 
     if (mjpeg_cfg->packet_cut_mode & MJPEG_PACKET_ADD_DEFAULT) {
@@ -89,12 +89,22 @@ void mjpeg_init(mjpeg_device_t *mjpeg_cfg)
 
 void mjpeg_start(void)
 {
-    MJPEG_Enable();
+    uint32_t tmpVal;
+
+    /* Enable mjpeg module */
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
+    tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);
 }
 
 void mjpeg_stop(void)
 {
-    MJPEG_Disable();
+    uint32_t tmpVal;
+
+    /* Disable mjpeg module */
+    tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE);
+    BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal);
 }
 
 uint8_t mjpeg_get_one_frame(uint8_t **pic, uint32_t *len, uint8_t *q)
diff --git a/drivers/bl702_driver/hal_drv/src/hal_pwm.c b/drivers/bl702_driver/hal_drv/src/hal_pwm.c
index 7623ac30..979e773c 100644
--- a/drivers/bl702_driver/hal_drv/src/hal_pwm.c
+++ b/drivers/bl702_driver/hal_drv/src/hal_pwm.c
@@ -21,12 +21,9 @@
  *
  */
 #include "hal_pwm.h"
-#include "hal_gpio.h"
 #include "hal_clock.h"
 #include "bl702_pwm.h"
-#include "bl702_gpio.h"
 #include "bl702_glb.h"
-#include "pwm_config.h"
 
 static pwm_device_t pwmx_device[PWM_MAX_INDEX] = {
 #ifdef BSP_USING_PWM_CH0
@@ -53,9 +50,12 @@ int pwm_open(struct device *dev, uint16_t oflag)
 
     uint32_t tmpVal;
     uint32_t PWMx;
-    PWM_Channel_Disable(pwm_device->ch);
+
+    CPU_Interrupt_Disable(PWM_IRQn);
     PWM_IntMask(pwm_device->ch, PWM_INT_ALL, MASK);
 
+    PWM_Channel_Disable(pwm_device->ch);
+
     uint32_t pwm_clk = peripheral_clock_get(PERIPHERAL_CLOCK_PWM);
     if (pwm_device->period > pwm_clk)
         return -1;
@@ -64,7 +64,7 @@ int pwm_open(struct device *dev, uint16_t oflag)
 
     tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
     tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_OUT_INV, pwm_device->polarity_invert_mode);
-    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, PWM_STOP_MODE_SEL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, PWM_STOP_GRACEFUL);
     BL_WR_REG(PWMx, PWM_CONFIG, tmpVal);
 
     BL_WR_REG(PWMx, PWM_THRE1, pwm_device->threshold_low);
@@ -91,7 +91,7 @@ int pwm_close(struct device *dev)
 int pwm_control(struct device *dev, int cmd, void *args)
 {
     pwm_device_t *pwm_device = (pwm_device_t *)dev;
-    pwm_dutycycle_config_t *pwm_detycycle_config = (pwm_dutycycle_config_t *)args;
+    pwm_dutycycle_config_t *config = (pwm_dutycycle_config_t *)args;
 
     switch (cmd) {
         case DEVICE_CTRL_CONFIG /* constant-expression */:
@@ -111,8 +111,8 @@ int pwm_control(struct device *dev, int cmd, void *args)
             BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_PERIOD, (uint32_t)args);
             break;
         case DEVICE_CTRL_PWM_DUTYCYCLE_CONFIG:
-            BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_THRE1, pwm_detycycle_config->threshold_low);
-            BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_THRE2, pwm_detycycle_config->threshold_high);
+            BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_THRE1, config->threshold_low);
+            BL_WR_REG(PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->ch) * 0x20, PWM_THRE2, config->threshold_high);
             break;
         case DEVICE_CTRL_PWM_IT_PULSE_COUNT_CONFIG: {
             /* Config interrupt pulse count */
diff --git a/drivers/bl702_driver/hal_drv/src/hal_rtc.c b/drivers/bl702_driver/hal_drv/src/hal_rtc.c
index 9819b95a..9b4a4368 100644
--- a/drivers/bl702_driver/hal_drv/src/hal_rtc.c
+++ b/drivers/bl702_driver/hal_drv/src/hal_rtc.c
@@ -20,8 +20,8 @@
  * under the License.
  *
  */
-#include "bl702_hbn.h"
 #include "hal_rtc.h"
+#include "bl702_hbn.h"
 
 static uint64_t current_timestamp = 0;
 /**
diff --git a/drivers/bl702_driver/hal_drv/src/hal_spi.c b/drivers/bl702_driver/hal_drv/src/hal_spi.c
index d3a3b18a..5e16af47 100644
--- a/drivers/bl702_driver/hal_drv/src/hal_spi.c
+++ b/drivers/bl702_driver/hal_drv/src/hal_spi.c
@@ -22,10 +22,8 @@
  */
 #include "hal_spi.h"
 #include "hal_dma.h"
-#include "hal_gpio.h"
 #include "bl702_glb.h"
 #include "bl702_spi.h"
-#include "spi_config.h"
 
 #ifdef BSP_USING_SPI0
 static void SPI0_IRQ(void);
@@ -48,18 +46,19 @@ int spi_open(struct device *dev, uint16_t oflag)
     spi_device_t *spi_device = (spi_device_t *)dev;
     SPI_CFG_Type spiCfg = { 0 };
     SPI_FifoCfg_Type fifoCfg = { 0 };
-#if SPI_SWAP_ENABLE
-    GLB_Swap_SPI_0_MOSI_With_MISO(ENABLE);
-#endif
 
-    SPI_IntMask(spi_device->id, SPI_INT_ALL, MASK);
+    if (spi_device->pin_swap_enable) {
+        GLB_Swap_SPI_0_MOSI_With_MISO(ENABLE);
+    }
+
     /* Enable uart interrupt*/
     CPU_Interrupt_Disable(SPI_IRQn);
+    SPI_IntMask(spi_device->id, SPI_INT_ALL, MASK);
 
     SPI_Disable(spi_device->id, spi_device->mode);
 
     GLB_Set_SPI_0_ACT_MOD_Sel(spi_device->mode);
-    GLB_Set_SPI_CLK(ENABLE, 0);
+
     /* Set SPI clock */
     SPI_ClockCfg_Type clockCfg = {
         2, /* Length of start condition */
@@ -85,8 +84,7 @@ int spi_open(struct device *dev, uint16_t oflag)
 
     SPI_ClockConfig(spi_device->id, &clockCfg);
 
-    spiCfg.deglitchEnable = SPI_DEGLITCH_ENABLE;
-    spiCfg.continuousEnable = SPI_CONTINUE_TRANSFER_ENABLE;
+    spiCfg.continuousEnable = 1;
 
     if (spi_device->direction == SPI_LSB_BYTE0_DIRECTION_FIRST) {
         spiCfg.bitSequence = SPI_BIT_INVERSE_LSB_FIRST;
@@ -106,9 +104,15 @@ int spi_open(struct device *dev, uint16_t oflag)
     spiCfg.clkPhaseInv = spi_device->clk_phase;
     spiCfg.frameSize = spi_device->datasize;
 
+    if (spi_device->delitch_cnt) {
+        spiCfg.deglitchEnable = 1;
+    }
+
     /* SPI config */
     SPI_Init(spi_device->id, &spiCfg);
 
+    SPI_SetDeglitchCount(spi_device->id, spi_device->delitch_cnt);
+
     fifoCfg.txFifoThreshold = spi_device->fifo_threshold;
     fifoCfg.txFifoDmaEnable = DISABLE;
     fifoCfg.rxFifoThreshold = spi_device->fifo_threshold;
@@ -145,6 +149,7 @@ int spi_close(struct device *dev)
     spi_device_t *spi_device = (spi_device_t *)dev;
 
     SPI_Disable(spi_device->id, spi_device->mode);
+    GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SPI);
     return 0;
 }
 /**
diff --git a/drivers/bl702_driver/hal_drv/src/hal_timer.c b/drivers/bl702_driver/hal_drv/src/hal_timer.c
index 57db1d85..560ee021 100644
--- a/drivers/bl702_driver/hal_drv/src/hal_timer.c
+++ b/drivers/bl702_driver/hal_drv/src/hal_timer.c
@@ -21,10 +21,9 @@
  *
  */
 #include "hal_timer.h"
-#include "timer_config.h"
+#include "hal_clock.h"
 #include "bl702_glb.h"
 #include "bl702_timer.h"
-#include "hal_clock.h"
 
 #ifdef BSP_USING_TIMER0
 void TIMER0_IRQ(void);
diff --git a/drivers/bl702_driver/hal_drv/src/hal_uart.c b/drivers/bl702_driver/hal_drv/src/hal_uart.c
index d4039f2f..bbcaa45d 100644
--- a/drivers/bl702_driver/hal_drv/src/hal_uart.c
+++ b/drivers/bl702_driver/hal_drv/src/hal_uart.c
@@ -22,7 +22,6 @@
  */
 #include "hal_uart.h"
 #include "hal_dma.h"
-#include "hal_gpio.h"
 #include "hal_clock.h"
 #include "bl702_uart.h"
 #include "bl702_glb.h"
diff --git a/drivers/bl702_driver/hal_drv/src/hal_usb.c b/drivers/bl702_driver/hal_drv/src/hal_usb.c
index 635ff256..2d81cd4e 100644
--- a/drivers/bl702_driver/hal_drv/src/hal_usb.c
+++ b/drivers/bl702_driver/hal_drv/src/hal_usb.c
@@ -25,8 +25,9 @@
 #include "hal_mtimer.h"
 #include "bl702_usb.h"
 #include "bl702_glb.h"
-#include "bl702_gpio.h"
-#include "usb_config.h"
+
+#define USE_INTERNAL_TRANSCEIVER
+// #define ENABLE_LPM_INT
 
 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
 
@@ -304,6 +305,7 @@ int usb_close(struct device *dev)
     usb_set_power_off();
 
     usb_xcvr_config(DISABLE);
+    GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_USB);
     return 0;
 }
 /**