From a31ce132936c14b89342b17e1cefb35b16dac687 Mon Sep 17 00:00:00 2001 From: jzlv Date: Wed, 10 Nov 2021 17:39:57 +0800 Subject: [PATCH] [refactor][dac] refactor dac driver and dac clock config --- bsp/board/bl602/bl602_boot2/clock_config.h | 3 +- bsp/board/bl602/bl602_iot/clock_config.h | 1 + bsp/board/bl702/bl702_boot2/clock_config.h | 4 +- bsp/board/bl702/bl702_iot/clock_config.h | 4 +- bsp/board/bl702/bl706_avb/clock_config.h | 2 +- bsp/board/bl702/bl706_iot/clock_config.h | 2 +- drivers/bl702_driver/hal_drv/inc/hal_dac.h | 39 ++-- drivers/bl702_driver/hal_drv/src/hal_dac.c | 223 +++++++++++-------- examples/dac/dac_mono_play_form_flash/main.c | 2 +- 9 files changed, 163 insertions(+), 117 deletions(-) diff --git a/bsp/board/bl602/bl602_boot2/clock_config.h b/bsp/board/bl602/bl602_boot2/clock_config.h index e50f297a..31a1c81d 100644 --- a/bsp/board/bl602/bl602_boot2/clock_config.h +++ b/bsp/board/bl602/bl602_boot2/clock_config.h @@ -25,6 +25,7 @@ #define _CLOCK_CONFIG_H #define XTAL_TYPE EXTERNAL_XTAL_40M +#define XTAL_32K_TYPE INTERNAL_RC_32K #define BSP_ROOT_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_160M #define BSP_FCLK_DIV 0 @@ -32,7 +33,7 @@ #if defined(BSP_USING_UART0) || defined(BSP_USING_UART1) #define BSP_UART_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_160M -#define BSP_UART_CLOCK_DIV 0 +#define BSP_UART_CLOCK_DIV 3 #endif #if defined(BSP_USING_I2C0) #define BSP_I2C_CLOCK_SOURCE ROOT_CLOCK_SOURCE_BCLK diff --git a/bsp/board/bl602/bl602_iot/clock_config.h b/bsp/board/bl602/bl602_iot/clock_config.h index e50f297a..43bdb391 100644 --- a/bsp/board/bl602/bl602_iot/clock_config.h +++ b/bsp/board/bl602/bl602_iot/clock_config.h @@ -25,6 +25,7 @@ #define _CLOCK_CONFIG_H #define XTAL_TYPE EXTERNAL_XTAL_40M +#define XTAL_32K_TYPE INTERNAL_RC_32K #define BSP_ROOT_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_160M #define BSP_FCLK_DIV 0 diff --git a/bsp/board/bl702/bl702_boot2/clock_config.h b/bsp/board/bl702/bl702_boot2/clock_config.h index b8910250..ba9d2961 100644 --- a/bsp/board/bl702/bl702_boot2/clock_config.h +++ b/bsp/board/bl702/bl702_boot2/clock_config.h @@ -75,9 +75,9 @@ #endif #if defined(BSP_USING_DAC0) #define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ -#define BSP_DAC_CLOCK_DIV 1 +#define BSP_DAC_CLOCK_DIV 2 #endif -#if defined(BSP_USING_CAM0) +#if defined(BSP_USING_CAM) #define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M #define BSP_CAM_CLOCK_DIV 3 #endif diff --git a/bsp/board/bl702/bl702_iot/clock_config.h b/bsp/board/bl702/bl702_iot/clock_config.h index 98454a8a..40eda22e 100644 --- a/bsp/board/bl702/bl702_iot/clock_config.h +++ b/bsp/board/bl702/bl702_iot/clock_config.h @@ -58,7 +58,7 @@ #endif #if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4) || defined(BSP_USING_PWM_CH5) #define BSP_PWM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_32K_CLK -#define BSP_PWM_CLOCK_DIV 32 +#define BSP_PWM_CLOCK_DIV 31 #endif #if defined(BSP_USING_IR) #define BSP_IR_CLOCK_SOURCE ROOT_CLOCK_SOURCE_XCLK @@ -70,7 +70,7 @@ #endif #if defined(BSP_USING_DAC0) #define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ -#define BSP_DAC_CLOCK_DIV 1 +#define BSP_DAC_CLOCK_DIV 2 #endif #if defined(BSP_USING_CAM0) #define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M diff --git a/bsp/board/bl702/bl706_avb/clock_config.h b/bsp/board/bl702/bl706_avb/clock_config.h index 15b3021c..9ed931fe 100644 --- a/bsp/board/bl702/bl706_avb/clock_config.h +++ b/bsp/board/bl702/bl706_avb/clock_config.h @@ -74,7 +74,7 @@ #endif #if defined(BSP_USING_DAC0) #define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ -#define BSP_DAC_CLOCK_DIV 1 +#define BSP_DAC_CLOCK_DIV 2 #endif #if defined(BSP_USING_CAM0) #define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M diff --git a/bsp/board/bl702/bl706_iot/clock_config.h b/bsp/board/bl702/bl706_iot/clock_config.h index c3a68717..40eda22e 100644 --- a/bsp/board/bl702/bl706_iot/clock_config.h +++ b/bsp/board/bl702/bl706_iot/clock_config.h @@ -70,7 +70,7 @@ #endif #if defined(BSP_USING_DAC0) #define BSP_DAC_CLOCK_SOURCE ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ -#define BSP_DAC_CLOCK_DIV 1 +#define BSP_DAC_CLOCK_DIV 2 #endif #if defined(BSP_USING_CAM0) #define BSP_CAM_CLOCK_SOURCE ROOT_CLOCK_SOURCE_PLL_96M diff --git a/drivers/bl702_driver/hal_drv/inc/hal_dac.h b/drivers/bl702_driver/hal_drv/inc/hal_dac.h index ac6bd184..d935197f 100644 --- a/drivers/bl702_driver/hal_drv/inc/hal_dac.h +++ b/drivers/bl702_driver/hal_drv/inc/hal_dac.h @@ -24,7 +24,7 @@ #define __HAL_DAC__H__ #ifdef __cplusplus -extern "C"{ +extern "C" { #endif #include "hal_common.h" @@ -38,31 +38,28 @@ enum dac_index_type { DAC_MAX_INDEX }; -typedef struct -{ - uint8_t dac0; - uint8_t dac1; - uint8_t pin_num; -} dac_pin_t; +#define DAC_CHANNEL_0 (1 << 0) +#define DAC_CHANNEL_1 (1 << 1) +#define DAC_CHANNEL_ALL (DAC_CHANNEL_0 | DAC_CHANNEL_1) -typedef enum { - DAC_CHANNEL_0, - DAC_CHANNEL_1, - DAC_CHANNEL_ALL, -} dac_channel_t; +/* default a_rng and b_rng is 0x03*/ +/*output Voltage = (1.8V-0.2V) * digital_val/1024 + 0.2V */ +#define DAC_VREF_INTERNAL 0 /*0.2V~1.8V*/ +/*output Voltage = (0.9vref-0.1vref) * digital_val/1024 + 0.1vref */ +#define DAC_VREF_EXTERNAL 1 /*0.1vref~0.9vref,using gpio7 for GPIO_FUN_ADC*/ -typedef enum { - DAC_CLK_500KHZ, - DAC_CLK_44P1KHZ, - DAC_CLK_16KHZ, - DAC_CLK_8KHZ, -} dac_clk_t; +enum dac_sample_frequence { + DAC_SAMPLE_FREQ_8KHZ, + DAC_SAMPLE_FREQ_16KHZ, + DAC_SAMPLE_FREQ_44P1KHZ, + DAC_SAMPLE_FREQ_500KHZ, +}; typedef struct dac_device { struct device parent; - dac_clk_t clk; - dac_pin_t pin; - + enum dac_sample_frequence sample_freq; + uint8_t channels; + uint8_t vref; void *tx_dma; } dac_device_t; diff --git a/drivers/bl702_driver/hal_drv/src/hal_dac.c b/drivers/bl702_driver/hal_drv/src/hal_dac.c index 7ec2a994..fb67bfa0 100644 --- a/drivers/bl702_driver/hal_drv/src/hal_dac.c +++ b/drivers/bl702_driver/hal_drv/src/hal_dac.c @@ -22,17 +22,17 @@ */ #include "hal_dac.h" #include "hal_dma.h" -#include "bl702_gpio.h" +#include "hal_clock.h" #include "bl702_dac.h" -#include "bl702_dma.h" #include "bl702_glb.h" -#include "dac_config.h" static dac_device_t dacx_device[] = { #ifdef BSP_USING_DAC0 DAC_CONFIG, #endif }; + +static uint8_t dac_channel_enable_check = 0; /** * @brief * @@ -42,102 +42,145 @@ static dac_device_t dacx_device[] = { */ int dac_open(struct device *dev, uint16_t oflag) { - GLB_GPIP_DAC_ChanA_Cfg_Type chCfg = { 0 }; - GLB_GPIP_DAC_Cfg_Type dacCfg = { 0 }; dac_device_t *dac_device = (dac_device_t *)dev; - uint8_t dac_ext_ref_pin = 0; + uint8_t dac_div = 0; + uint32_t tmpVal; - if (dac_device->pin.pin_num == 2) { - GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, (GLB_GPIO_Type *)&dac_device->pin.dac0, 2); - } else if (dac_device->pin.pin_num == 1) { - GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, (GLB_GPIO_Type *)&dac_device->pin.dac0, 1); - } else { - return ERROR; + uint32_t dac_clk = peripheral_clock_get(PERIPHERAL_CLOCK_DAC); + + if ((GLB_GPIO_Get_Fun(GLB_GPIO_PIN_11) == GPIO_FUN_ANALOG) && (dac_device->channels & DAC_CHANNEL_0)) { + dac_channel_enable_check |= DAC_CHANNEL_0; + } + if ((GLB_GPIO_Get_Fun(GLB_GPIO_PIN_17) == GPIO_FUN_ANALOG) && (dac_device->channels & DAC_CHANNEL_1)) { + dac_channel_enable_check |= DAC_CHANNEL_1; } - switch (dac_device->clk) { - case DAC_CLK_500KHZ: - PDS_Set_Audio_PLL_Freq(AUDIO_PLL_24000000_HZ); - /* 24.0000MHZ / 3 / 16 = 500KHZ*/ - GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, 3); - dacCfg.div = DAC_CLK_DIV_16; + if (dac_channel_enable_check == 0) { + return -1; + } + + switch (dac_device->sample_freq) { + case DAC_SAMPLE_FREQ_500KHZ: + dac_div = dac_clk / 500000; break; - case DAC_CLK_8KHZ: - /* set audio pll as 12.288MHZ*/ - PDS_Set_Audio_PLL_Freq(AUDIO_PLL_12288000_HZ); - /* 12.2880MHZ / 24 / 64 = 8KHZ*/ - GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, 24); - dacCfg.div = DAC_CLK_DIV_64; + case DAC_SAMPLE_FREQ_8KHZ: + dac_div = dac_clk / 8000; break; - case DAC_CLK_16KHZ: - /* set audio pll as 12.288MHZ*/ - PDS_Set_Audio_PLL_Freq(AUDIO_PLL_12288000_HZ); - /* 12.2880MHZ / 24 / 32 = 16KHZ*/ - GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, 24); - dacCfg.div = DAC_CLK_DIV_32; + case DAC_SAMPLE_FREQ_16KHZ: + dac_div = dac_clk / 16000; break; - case DAC_CLK_44P1KHZ: - /* set audio pll as 11.2896MHZ*/ - PDS_Set_Audio_PLL_Freq(AUDIO_PLL_11289600_HZ); - /* 11.2896MHZ / 16 / 16 = 44.1KHZ*/ - GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, 16); - dacCfg.div = DAC_CLK_DIV_16; + case DAC_SAMPLE_FREQ_44P1KHZ: + dac_div = dac_clk / 441000; break; default: break; } - if (DAC_REF_SEL == GLB_DAC_REF_SEL_EXTERNAL) { - dac_ext_ref_pin = DAC_EXT_REF_GPIO; - dacCfg.refSel = GLB_DAC_REF_SEL_EXTERNAL; - GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, (GLB_GPIO_Type *)&dac_ext_ref_pin, 1); + if (dac_div == 1) { + dac_div = DAC_CLK_DIV_1; + } else if (dac_div == 16) { + dac_div = DAC_CLK_DIV_16; + } else if (dac_div == 32) { + dac_div = DAC_CLK_DIV_32; + } else if (dac_div == 64) { + dac_div = DAC_CLK_DIV_64; + } else + return -2; + + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_CTRL); + /*dac vref select*/ + if (dac_device->vref == DAC_VREF_EXTERNAL) { + if (GLB_GPIO_Get_Fun(GLB_GPIO_PIN_7) != GPIO_FUN_ANALOG) + return -1; + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_REF_SEL); } else { - dacCfg.refSel = GLB_DAC_REF_SEL_INTERNAL; + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDAC_REF_SEL); + } + BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + + /*dac reset*/ + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); + BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); + BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + + /* dac clear reset */ + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); + BL_WR_REG(GLB_BASE, GLB_GPDAC_CTRL, tmpVal); + + /* Set DAC div */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_MODE, dac_div); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); + + /* select source */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, GPIP_DAC_ChanA_SRC_REG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, GPIP_DAC_ChanB_SRC_REG); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); + + /* GPIP enable or disable channel */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + if (dac_channel_enable_check & DAC_CHANNEL_0) { + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN); + } + if (dac_channel_enable_check & DAC_CHANNEL_1) { + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN2); + } + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); + + /* GLB enable or disable channel */ + if (dac_channel_enable_check & DAC_CHANNEL_0) { + /* a channel */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_ACTRL); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_IOA_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_A_EN); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_RNG, 0x03); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_ACTRL, tmpVal); + } + if (dac_channel_enable_check & DAC_CHANNEL_1) { + /* b channel */ + tmpVal = BL_RD_REG(GLB_BASE, GLB_GPDAC_BCTRL); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_RNG, 0x03); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_IOB_EN); + tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_B_EN); + tmpVal = BL_WR_REG(GLB_BASE, GLB_GPDAC_BCTRL, tmpVal); } - if (oflag & DEVICE_OFLAG_STREAM_TX) { - dacCfg.dmaEn = DISABLE; - dacCfg.resetChanA = ENABLE; - dacCfg.resetChanB = ENABLE; - dacCfg.dmaFmt = GPIP_DAC_DMA_FORMAT_0; + /* GPIP disable DMA */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); + tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); - chCfg.chanCovtEn = ENABLE; - chCfg.outputEn = ENABLE; - chCfg.chanEn = ENABLE; - chCfg.src = GPIP_DAC_ChanA_SRC_REG; + if (oflag & DEVICE_OFLAG_DMA_TX) { + /* GPIP select source */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, GPIP_DAC_ChanA_SRC_DMA); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, GPIP_DAC_ChanB_SRC_DMA); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - GLB_GPIP_DAC_Init(&dacCfg); - GLB_GPIP_DAC_Set_ChanA_Config(&chCfg); - GLB_GPIP_DAC_Set_ChanB_Config((GLB_GPIP_DAC_ChanB_Cfg_Type *)&chCfg); - - } else if (oflag & DEVICE_OFLAG_DMA_TX) { - dacCfg.dmaEn = ENABLE; - dacCfg.resetChanA = ENABLE; - dacCfg.resetChanB = ENABLE; - - if (dac_device->pin.pin_num == 2) { - dacCfg.dmaFmt = GPIP_DAC_DMA_FORMAT_1; + /* GPIP enable DMA */ + tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); + if (dac_channel_enable_check == 2) { + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, GPIP_DAC_DMA_FORMAT_1); } else { - dacCfg.dmaFmt = GPIP_DAC_DMA_FORMAT_0; + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, GPIP_DAC_DMA_FORMAT_0); } - - chCfg.chanCovtEn = ENABLE; - chCfg.outputEn = ENABLE; - chCfg.chanEn = ENABLE; - chCfg.src = GPIP_DAC_ChanA_SRC_DMA; - - GLB_GPIP_DAC_Init(&dacCfg); - GLB_GPIP_DAC_Set_ChanA_Config(&chCfg); - GLB_GPIP_DAC_Set_ChanB_Config((GLB_GPIP_DAC_ChanB_Cfg_Type *)&chCfg); - - GPIP_Set_DAC_DMA_TX_FORMAT_SEL(dacCfg.dmaFmt); - GPIP_Set_DAC_DMA_TX_Enable(); - - } else { + tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); + BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); } return 0; @@ -155,6 +198,7 @@ int dac_close(struct device *dev) GLB_GPIP_DAC_Init(&dacCfg); GLB_GPIP_DAC_Set_ChanA_Config(&chCfg); GLB_GPIP_DAC_Set_ChanB_Config((GLB_GPIP_DAC_ChanB_Cfg_Type *)&chCfg); + GPIP_Set_DAC_DMA_TX_Disable(); return 0; } /** @@ -215,7 +259,8 @@ int dac_control(struct device *dev, int cmd, void *args) */ int dac_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) { - dac_channel_t channel = (dac_channel_t)pos; + int ret = 0; + enum dac_sample_frequence channel = (enum dac_sample_frequence)pos; dac_device_t *dac_device = (dac_device_t *)dev; uint32_t i = 0; @@ -226,28 +271,30 @@ int dac_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t siz return -1; } - dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_DAC_TDR, size); + ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_DAC_TDR, size); dma_channel_start(dma_ch); - } - - if (dev->oflag & DEVICE_OFLAG_STREAM_TX) { - if (channel == DAC_CHANNEL_0) { + return ret; + } else if (dev->oflag & DEVICE_OFLAG_STREAM_TX) { + if (channel & DAC_CHANNEL_ALL) { + for (i = 0; i < size; i++) { + GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i)); + GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i)); + } + } else if (channel & DAC_CHANNEL_0) { for (i = 0; i < size; i++) { GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i)); } - } else if (channel == DAC_CHANNEL_1) { + } else if (channel & DAC_CHANNEL_1) { for (i = 0; i < size; i++) { GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i)); } } else { - for (i = 0; i < size; i++) { - GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i)); - GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i)); - } + return -1; } + return 0; } - return 0; + return -1; } /** diff --git a/examples/dac/dac_mono_play_form_flash/main.c b/examples/dac/dac_mono_play_form_flash/main.c index 0f57036b..5e92cc08 100644 --- a/examples/dac/dac_mono_play_form_flash/main.c +++ b/examples/dac/dac_mono_play_form_flash/main.c @@ -34,7 +34,7 @@ int main(void) struct device *dac = device_find("dac"); if (dac) { - ((dac_device_t *)dac)->clk = DAC_CLK_16KHZ; + ((dac_device_t *)dac)->sample_freq = DAC_SAMPLE_FREQ_16KHZ; device_open(dac, DEVICE_OFLAG_DMA_TX); MSG("device open success\r\n"); }