[feat] add XXX_DEV definition
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@ -1,9 +1,9 @@
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/****************************************************************************************
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* @file map.txt
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* @file bl702_flash.ld
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*
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* @brief This file is the map file (gnuarm or armgcc).
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*
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* Copyright (C) BouffaloLab 2018
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* Copyright (C) BouffaloLab 2021
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*
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****************************************************************************************
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*/
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@ -56,14 +56,14 @@ SECTIONS
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*(.text.*)
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/*put .rodata**/
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*(EXCLUDE_FILE( *bl602_glb.o \
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*bl602_pds.o \
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*bl602_common.o \
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*bl602_sf_cfg.o \
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*bl602_sf_ctrl.o \
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*bl602_sflash.o \
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*bl602_xip_sflash.o \
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*bl602_ef_ctrl.o) .rodata*)
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*(EXCLUDE_FILE( *bl702_glb.o \
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*bl702_pds.o \
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*bl702_common.o \
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*bl702_sf_cfg.o \
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*bl702_sf_ctrl.o \
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*bl702_sflash.o \
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*bl702_xip_sflash.o \
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*bl702_ef_ctrl.o) .rodata*)
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*(.rodata)
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*(.rodata.*)
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@ -87,14 +87,14 @@ SECTIONS
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*(.sclock_rlt_code)
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*(.sclock_rlt_const)
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*bl602_glb.o*(.rodata*)
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*bl602_pds.o*(.rodata*)
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*bl602_common.o*(.rodata*)
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*bl602_sf_cfg.o*(.rodata*)
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*bl602_sf_ctrl.o*(.rodata*)
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*bl602_sflash.o*(.rodata*)
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*bl602_xip_sflash.o*(.rodata*)
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*bl602_ef_ctrl.o*(.rodata*)
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*bl702_glb.o*(.rodata*)
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*bl702_pds.o*(.rodata*)
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*bl702_common.o*(.rodata*)
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*bl702_sf_cfg.o*(.rodata*)
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*bl702_sf_ctrl.o*(.rodata*)
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*bl702_sflash.o*(.rodata*)
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*bl702_xip_sflash.o*(.rodata*)
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*bl702_ef_ctrl.o*(.rodata*)
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. = ALIGN(4);
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__tcm_code_end__ = .;
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@ -0,0 +1,6 @@
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#ifndef _TIMER_CONFIG_H
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#define _TIMER_CONFIG_H
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#define TIMER_CLK_SRC (0)
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#endif
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@ -123,6 +123,8 @@ typedef struct adc_device
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adc_data_width_t resWidth;
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} adc_device_t;
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#define ADC_DEV(dev) ((adc_device_t*)dev)
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int adc_register(enum adc_index_type index, const char *name, uint16_t flag, adc_user_cfg_t *adc_user_cfg);
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#endif
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@ -26,8 +26,6 @@
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#include "drv_device.h"
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#include "bl702_config.h"
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#define DEVICE_CTRL_DAC_ATTACH_TX_DMA 0x12
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enum dac_index_type
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{
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#ifdef BSP_USING_DAC0
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@ -67,6 +65,7 @@ typedef struct dac_device
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void* tx_dma;
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} dac_device_t;
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#define DAC_DEV(dev) ((adc_device_t*)dev)
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int dac_register(enum dac_index_type index, const char *name, uint16_t flag);
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@ -26,10 +26,10 @@
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#include "drv_device.h"
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#include "bl702_config.h"
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#define DMA_CHANNEL_GET_STATUS_CMD 0x10
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#define DMA_CHANNEL_START_CMD 0x11
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#define DMA_CHANNEL_STOP_CMD 0x12
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#define DMA_CHANNEL_UPDATE_CMD 0x13
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#define DMA_CHANNEL_GET_STATUS 0x10
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#define DMA_CHANNEL_START 0x11
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#define DMA_CHANNEL_STOP 0x12
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#define DMA_CHANNEL_UPDATE 0x13
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enum dma_index_type
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{
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@ -60,10 +60,10 @@ enum dma_index_type
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DMA_MAX_INDEX
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};
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#define dma_channel_start(dev) device_control(dev,DMA_CHANNEL_START_CMD,NULL)
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#define dma_channel_stop(dev) device_control(dev,DMA_CHANNEL_STOP_CMD,NULL)
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#define dma_channel_update(dev,list) device_control(dev,DMA_CHANNEL_UPDATE_CMD,list)
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#define dma_channel_check_busy(dev) device_control(dev,DMA_CHANNEL_GET_STATUS_CMD,NULL)
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#define dma_channel_start(dev) device_control(dev,DMA_CHANNEL_START,NULL)
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#define dma_channel_stop(dev) device_control(dev,DMA_CHANNEL_STOP,NULL)
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#define dma_channel_update(dev,list) device_control(dev,DMA_CHANNEL_UPDATE,list)
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#define dma_channel_check_busy(dev) device_control(dev,DMA_CHANNEL_GET_STATUS,NULL)
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#define DMA_ADDR_UART0_TDR (0x4000A000+0x88)
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#define DMA_ADDR_UART0_RDR (0x4000A000+0x8C)
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@ -185,6 +185,8 @@ typedef struct dma_device
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dma_lli_ctrl_t *lli_cfg;
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} dma_device_t;
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#define DMA_DEV(dev) ((dma_device_t*)dev)
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int dma_register(enum dma_index_type, const char *name, uint16_t flag);
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int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size);
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int dma_allocate_register(const char *name, uint16_t flag);
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34
drivers/bl702_driver/hal_drv/inc/hal_flash.h
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34
drivers/bl702_driver/hal_drv/inc/hal_flash.h
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@ -0,0 +1,34 @@
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/**
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* @file hal_flash.h
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* @brief
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*
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* Copyright 2019-2030 Bouffalolab team
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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*/
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#ifndef __HAL_FLASH__H__
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#define __HAL_FLASH__H__
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#include "drv_device.h"
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#define FLASH_NOT_DETECT 0x10
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int flash_erase(uint32_t addr, uint32_t size);
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int flash_read(uint32_t addr, uint8_t *data, uint32_t size);
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int flash_write(uint32_t addr, uint8_t *data, uint32_t size);
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#endif
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@ -65,7 +65,9 @@ typedef struct i2c_device
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uint32_t phase;
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} i2c_device_t;
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#define I2C_DEV(dev) ((i2c_device_t*)dev)
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int i2c_register(enum i2c_index_type index, const char *name, uint16_t flag);
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uint32_t i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num);
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int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num);
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#endif
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@ -116,6 +116,8 @@ typedef struct i2s_device
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void* rx_dma;
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} i2s_device_t;
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#define UART_DEV(dev) ((uart_device_t*)dev)
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int i2s_register(enum i2s_index_type index,const char *name,uint16_t flag);
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#endif
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@ -29,20 +29,20 @@
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enum pwm_index_type
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{
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#ifdef BSP_USING_UART0
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PWM0_INDEX,
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#ifdef BSP_USING_PWM_CH0
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PWM_CH0_INDEX,
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#endif
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#ifdef BSP_USING_UART1
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PWM1_INDEX,
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#ifdef BSP_USING_PWM_CH1
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PWM_CH1_INDEX,
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#endif
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#ifdef BSP_USING_UART2
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PWM2_INDEX,
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#ifdef BSP_USING_PWM_CH2
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PWM_CH2_INDEX,
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#endif
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#ifdef BSP_USING_UART3
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PWM3_INDEX,
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#ifdef BSP_USING_PWM_CH3
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PWM_CH3_INDEX,
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#endif
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#ifdef BSP_USING_UART4
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PWM4_INDEX,
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#ifdef BSP_USING_PWM_CH4
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PWM_CH4_INDEX,
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#endif
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PWM_MAX_INDEX
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};
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@ -60,7 +60,8 @@ typedef struct pwm_device
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uint8_t dutyCycle;
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} pwm_device_t;
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#define PWM_DEV(dev) ((pwm_device_t*)dev)
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void pwm_register(enum pwm_index_type index, const char *name, uint16_t flag);
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int pwm_register(enum pwm_index_type index, const char *name, uint16_t flag);
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#endif
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#endif
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@ -26,9 +26,7 @@
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#include "drv_device.h"
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#include "bl702_config.h"
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#define DEVICE_CTRL_SPI_ATTACH_TX_DMA_CMD 0x10
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#define DEVICE_CTRL_SPI_ATTACH_RX_DMA_CMD 0x11
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#define DEVICE_CTRL_SPI_CONFIG_CLOCK_CMD 0x12
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#define DEVICE_CTRL_SPI_CONFIG_CLOCK 0x10
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enum spi_index_type
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{
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@ -92,9 +90,12 @@ typedef struct spi_device
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void* rx_dma;
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} spi_device_t;
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#define SPI_DEV(dev) ((spi_device_t*)dev)
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int spi_register(enum spi_index_type index, const char *name, uint16_t flag);
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int spi_transmit(struct device *dev, void *buffer, uint32_t size, uint8_t type);
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int spi_receive(struct device *dev, void *buffer, uint32_t size, uint8_t type);
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int spi_transmit_receive(struct device *dev, const void *send_buf, void *recv_buf, uint32_t length, uint8_t type);
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#endif
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@ -26,15 +26,69 @@
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#include "drv_device.h"
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#include "bl702_config.h"
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enum timer_index_type
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{
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#ifdef BSP_USING_TIMER_CH0
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TIMER_CH0_INDEX,
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#endif
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#ifdef BSP_USING_TIMER_CH1
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TIMER_CH1_INDEX,
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#endif
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TIMER_MAX_INDEX
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};
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enum timer_event_type
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{
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TIMER_EVENT_COMP0,
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TIMER_EVENT_COMP1,
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TIMER_EVENT_COMP2,
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TIMER_EVENT_UNKNOWN
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};
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enum timer_it_type
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{
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TIMER_COMP0_IT = 1 << 0,
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TIMER_COMP1_IT = 1 << 1,
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TIMER_COMP2_IT = 1 << 2,
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TIMER_ALL_IT = 1 << 3
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};
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typedef enum{
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TIMER_CLK_FCLK,
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TIMER_CLK_32K,
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TIMER_CLK_1K,
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TIMER_CLK_XTAL,
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}timer_clk_src_t;
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typedef enum{
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TIMER_PL_TRIG_NONE,
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TIMER_PL_TRIG_COMP0,
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TIMER_PL_TRIG_COMP1,
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TIMER_PL_TRIG_COMP2,
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}timer_pl_trig_t;
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typedef enum{
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TIMER_CNT_PRELOAD,
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TIMER_CNT_FREERUN,
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}timer_cnt_mode;
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typedef struct {
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uint32_t timeout_val;
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}timer_user_cfg_t;
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typedef struct timer_device
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{
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struct device parent;
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// TIMER_CFG_Type *timerAttr;
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uint8_t id;
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uint8_t ch;
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uint8_t clk_div;
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timer_cnt_mode cnt_mode;
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timer_pl_trig_t pl_trig_src;
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} timer_device_t;
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void timer_register(timer_device_t *device, const char *name, uint16_t flag);
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#define TIMER_DEV(dev) ((timer_device_t*)dev)
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int timer_register(enum timer_index_type index, const char *name, uint16_t flag, timer_user_cfg_t *timer_user_cfg);
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extern timer_device_t timerx_device;
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#endif
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@ -28,8 +28,6 @@
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#define DEVICE_CTRL_UART_GET_TX_FIFO 0x10
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#define DEVICE_CTRL_UART_GET_RX_FIFO 0x11
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#define DEVICE_CTRL_UART_ATTACH_TX_DMA 0x12
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#define DEVICE_CTRL_UART_ATTACH_RX_DMA 0x13
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enum uart_index_type
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{
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@ -132,6 +130,8 @@ typedef struct uart_device
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void* rx_dma;
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} uart_device_t;
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#define UART_DEV(dev) ((uart_device_t*)dev)
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int uart_register(enum uart_index_type index, const char *name, uint16_t flag);
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#endif
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@ -35,8 +35,9 @@
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#define DEVICE_CTRL_USB_DC_GET_STALL 0X15
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#define DEVICE_CTRL_USB_DC_CLR_NACK 0X16
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#define DEVICE_CTRL_USB_DC_CHECK_EPCAP 0X17
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#define DEVICE_CTRL_USB_DC_TX_FIFO_CNT_GET 0x18
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#define DEVICE_CTRL_USB_DC_RX_FIFO_CNT_GET 0x19
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#define DEVICE_CTRL_USB_DC_GET_TX_FIFO_CNT 0x18
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#define DEVICE_CTRL_USB_DC_GET_RX_FIFO_CNT 0x19
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#define DEVICE_CTRL_USB_DC_GET_EP_FREE 0x20
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enum usb_index_type
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{
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@ -214,7 +215,7 @@ int usb_dc_ep_open(struct device *dev, const struct usb_dc_ep_cfg *ep_cfg);
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int usb_dc_ep_is_stalled(struct device *dev, const uint8_t ep, uint8_t *stalled);
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int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes);
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int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes);
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uint16_t usb_dc_receive_to_ringbuffer(struct device *dev,Ring_Buffer_Type* rb,uint8_t ep);
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uint16_t usb_dc_send_from_ringbuffer(struct device *dev,Ring_Buffer_Type* rb,uint8_t ep);
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int usb_dc_receive_to_ringbuffer(struct device *dev,Ring_Buffer_Type* rb,uint8_t ep);
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int usb_dc_send_from_ringbuffer(struct device *dev,Ring_Buffer_Type* rb,uint8_t ep);
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#endif
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@ -157,7 +157,7 @@ int dac_control(struct device *dev, int cmd, void *args)
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case DEVICE_CTRL_SUSPEND /* constant-expression */:
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break;
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case DEVICE_CTRL_DAC_ATTACH_TX_DMA /* constant-expression */:
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case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
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dac_device->tx_dma = (struct device *)args;
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break;
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default:
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@ -139,15 +139,15 @@ int dma_control(struct device *dev, int cmd, void *args)
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break;
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}
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case DMA_CHANNEL_UPDATE_CMD:
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case DMA_CHANNEL_UPDATE:
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DMA_LLI_Update(dma_device->ch, (uint32_t)args);
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break;
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case DMA_CHANNEL_GET_STATUS_CMD /* constant-expression */:
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case DMA_CHANNEL_GET_STATUS /* constant-expression */:
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return DMA_Channel_Is_Busy(dma_device->ch);
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case DMA_CHANNEL_START_CMD /* constant-expression */:
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case DMA_CHANNEL_START /* constant-expression */:
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DMA_Channel_Enable(dma_device->ch);
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break;
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case DMA_CHANNEL_STOP_CMD /* constant-expression */:
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case DMA_CHANNEL_STOP /* constant-expression */:
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DMA_Channel_Disable(dma_device->ch);
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break;
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default:
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108
drivers/bl702_driver/hal_drv/src/hal_flash.c
Normal file
108
drivers/bl702_driver/hal_drv/src/hal_flash.c
Normal file
@ -0,0 +1,108 @@
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/**
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* @file hal_flash.c
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* @brief
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*
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* Copyright 2019-2030 Bouffalolab team
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
|
||||
* this work for additional information regarding copyright ownership. The
|
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
|
||||
* "License"); you may not use this file except in compliance with the
|
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* License. You may obtain a copy of the License at
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||||
*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
|
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
|
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
|
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* License for the specific language governing permissions and limitations
|
||||
* under the License.
|
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*
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*/
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#include "bl702_xip_sflash.h"
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#include "bl702_sf_cfg.h"
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#include "bl702_glb.h"
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#include "hal_flash.h"
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/**
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* @brief erase flash memory addr should be 4k aligned or will erase more than size Byte
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* each block have 4K Byte
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*
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* @param addr flash memory block addr
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* @param size erase bytes number
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* @return int success or not
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*/
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int flash_erase(uint32_t addr, uint32_t size)
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{
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SPI_Flash_Cfg_Type flashCfg;
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uint32_t ret = 0;
|
||||
|
||||
XIP_SFlash_Opt_Enter();
|
||||
ret = SF_Cfg_Flash_Identify(1, 1, 0, 0, &flashCfg);
|
||||
XIP_SFlash_Opt_Exit();
|
||||
|
||||
if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0)
|
||||
{
|
||||
return -FLASH_NOT_DETECT;
|
||||
}
|
||||
|
||||
XIP_SFlash_Erase_With_Lock(&flashCfg, SF_CTRL_DO_MODE, addr, size - 1);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief read data form flash
|
||||
*
|
||||
* @param addr read flash addr
|
||||
* @param data read data pointer
|
||||
* @param size read data size
|
||||
* @return int
|
||||
*/
|
||||
int flash_read(uint32_t addr, uint8_t *data, uint32_t size)
|
||||
{
|
||||
SPI_Flash_Cfg_Type flashCfg;
|
||||
uint32_t ret = 0;
|
||||
|
||||
XIP_SFlash_Opt_Enter();
|
||||
ret = SF_Cfg_Flash_Identify(1, 1, 0, 0, &flashCfg);
|
||||
XIP_SFlash_Opt_Exit();
|
||||
|
||||
if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0)
|
||||
{
|
||||
return -FLASH_NOT_DETECT;
|
||||
}
|
||||
|
||||
XIP_SFlash_Read_With_Lock(&flashCfg, SF_CTRL_DO_MODE, addr, data, size);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief write data to flash
|
||||
*
|
||||
* @param addr write flash addr
|
||||
* @param data write data pointer
|
||||
* @param size write data size
|
||||
* @return int
|
||||
*/
|
||||
int flash_write(uint32_t addr, uint8_t *data, uint32_t size)
|
||||
{
|
||||
SPI_Flash_Cfg_Type flashCfg;
|
||||
uint32_t ret = 0;
|
||||
|
||||
XIP_SFlash_Opt_Enter();
|
||||
ret = SF_Cfg_Flash_Identify(1, 1, 0, 0, &flashCfg);
|
||||
XIP_SFlash_Opt_Exit();
|
||||
|
||||
if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0)
|
||||
{
|
||||
return -FLASH_NOT_DETECT;
|
||||
}
|
||||
|
||||
XIP_SFlash_Write_With_Lock(&flashCfg, SF_CTRL_DO_MODE, addr, data, size);
|
||||
|
||||
return 0;
|
||||
}
|
@ -138,7 +138,7 @@ int i2c_register(enum i2c_index_type index, const char *name, uint16_t flag)
|
||||
* @param num
|
||||
* @return uint32_t
|
||||
*/
|
||||
uint32_t i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num)
|
||||
int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num)
|
||||
{
|
||||
i2c_msg_t *msg;
|
||||
I2C_Transfer_Cfg i2cCfg;
|
||||
|
@ -39,6 +39,9 @@ int i2s_open(struct device *dev, uint16_t oflag)
|
||||
I2S_CFG_Type i2sCfg;
|
||||
I2S_FifoCfg_Type fifoCfg;
|
||||
|
||||
GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_I2S_REF_CLK);
|
||||
GLB_Set_I2S_CLK(ENABLE,GLB_I2S_OUT_REF_CLK_SRC);
|
||||
|
||||
/*Finding the right frequency*/
|
||||
if(12288000 %(i2s_device->sampl_freq_hz) == 0)
|
||||
{
|
||||
|
@ -25,24 +25,23 @@
|
||||
#include "bl702_pwm.h"
|
||||
#include "bl702_gpio.h"
|
||||
#include "bl702_glb.h"
|
||||
#include "bl702_config.h"
|
||||
#include "pwm_config.h"
|
||||
|
||||
pwm_device_t pwmx_device[PWM_MAX_INDEX] = {
|
||||
#ifdef BSP_USING_PWM0
|
||||
PWM_CONFIG_0,
|
||||
#ifdef BSP_USING_PWM_CH0
|
||||
PWM_CH0_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM1
|
||||
PWM_CONFIG_1,
|
||||
#ifdef BSP_USING_PWM_CH1
|
||||
PWM_CH1_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM2
|
||||
PWM_CONFIG_2,
|
||||
#ifdef BSP_USING_PWM_CH2
|
||||
PWM_CH2_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM3
|
||||
PWM_CONFIG_3,
|
||||
#ifdef BSP_USING_PWM_CH3
|
||||
PWM_CH3_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_PWM4
|
||||
PWM_CONFIG_4,
|
||||
#ifdef BSP_USING_PWM_CH4
|
||||
PWM_CH4_CONFIG,
|
||||
#endif
|
||||
};
|
||||
|
||||
@ -56,7 +55,6 @@ static void pwm_set(struct device *dev, PWM_CH_CFG_Type * pwmCfg ,uint32_t freq
|
||||
|
||||
pwm_device_t *pwm_device = (pwm_device_t *)dev;
|
||||
|
||||
|
||||
switch(unit)
|
||||
{
|
||||
case HZ:
|
||||
@ -183,10 +181,13 @@ int pwm_control(struct device *dev, int cmd, void *args)
|
||||
}
|
||||
|
||||
|
||||
void pwm_register(enum pwm_index_type index, const char *name, uint16_t flag)
|
||||
int pwm_register(enum pwm_index_type index, const char *name, uint16_t flag)
|
||||
{
|
||||
struct device *dev;
|
||||
|
||||
if (PWM_MAX_INDEX == 0)
|
||||
return -DEVICE_EINVAL;
|
||||
|
||||
dev = &(pwmx_device[index].parent);
|
||||
|
||||
dev->open = pwm_open;
|
||||
@ -199,5 +200,5 @@ void pwm_register(enum pwm_index_type index, const char *name, uint16_t flag)
|
||||
dev->type = DEVICE_CLASS_PWM;
|
||||
dev->handle = NULL;
|
||||
|
||||
device_register(dev, name, flag);
|
||||
return device_register(dev, name, flag);
|
||||
}
|
||||
|
@ -83,8 +83,8 @@ int spi_open(struct device *dev, uint16_t oflag)
|
||||
}
|
||||
else
|
||||
{
|
||||
clockCfg.dataPhase0Len = length % 2;
|
||||
clockCfg.dataPhase1Len = length / 2;
|
||||
clockCfg.dataPhase0Len = length / 2;
|
||||
clockCfg.dataPhase1Len = length / 2 + 1;
|
||||
}
|
||||
SPI_ClockConfig(spi_device->id, &clockCfg);
|
||||
|
||||
@ -193,15 +193,43 @@ int spi_control(struct device *dev, int cmd, void *args)
|
||||
case DEVICE_CTRL_CONFIG /* constant-expression */:
|
||||
/* code */
|
||||
break;
|
||||
case DEVICE_CTRL_SPI_ATTACH_TX_DMA_CMD /* constant-expression */:
|
||||
case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
|
||||
spi_device->tx_dma = (struct device *)args;
|
||||
break;
|
||||
case DEVICE_CTRL_SPI_ATTACH_RX_DMA_CMD /* constant-expression */:
|
||||
case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */:
|
||||
spi_device->rx_dma = (struct device *)args;
|
||||
break;
|
||||
case DEVICE_CTRL_SPI_CONFIG_CLOCK_CMD /* constant-expression */:
|
||||
case DEVICE_CTRL_SPI_CONFIG_CLOCK /* constant-expression */:
|
||||
SPI_SetClock(spi_device->id,(uint32_t)args);
|
||||
break;
|
||||
case DEVICE_CTRL_TX_DMA_SUSPEND:
|
||||
{
|
||||
uint32_t tmpVal = BL_RD_REG(SPI_BASE+spi_device->id*0x100,SPI_FIFO_CONFIG_0);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal,SPI_DMA_TX_EN);
|
||||
BL_WR_REG(SPI_BASE+spi_device->id*0x100,SPI_FIFO_CONFIG_0,tmpVal);
|
||||
break;
|
||||
}
|
||||
case DEVICE_CTRL_RX_DMA_SUSPEND:
|
||||
{
|
||||
uint32_t tmpVal = BL_RD_REG(SPI_BASE+spi_device->id*0x100,SPI_FIFO_CONFIG_0);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal,SPI_DMA_RX_EN);
|
||||
BL_WR_REG(SPI_BASE+spi_device->id*0x100,SPI_FIFO_CONFIG_0,tmpVal);
|
||||
break;
|
||||
}
|
||||
case DEVICE_CTRL_TX_DMA_RESUME:
|
||||
{
|
||||
uint32_t tmpVal = BL_RD_REG(SPI_BASE+spi_device->id*0x100,SPI_FIFO_CONFIG_0);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_DMA_TX_EN);
|
||||
BL_WR_REG(SPI_BASE+spi_device->id*0x100,SPI_FIFO_CONFIG_0,tmpVal);
|
||||
break;
|
||||
}
|
||||
case DEVICE_CTRL_RX_DMA_RESUME:
|
||||
{
|
||||
uint32_t tmpVal = BL_RD_REG(SPI_BASE+spi_device->id*0x100,SPI_FIFO_CONFIG_0);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal,SPI_DMA_RX_EN);
|
||||
BL_WR_REG(SPI_BASE+spi_device->id*0x100,SPI_FIFO_CONFIG_0,tmpVal);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
@ -21,73 +21,145 @@
|
||||
*
|
||||
*/
|
||||
#include "hal_timer.h"
|
||||
#include "timer_config.h"
|
||||
#include "bl702_glb.h"
|
||||
#include "bl702_timer.h"
|
||||
|
||||
// extern struct device * timer;
|
||||
// /****************************************************************************/ /**
|
||||
// * @brief TIMER match 0 interrupt calllbaeck funtion
|
||||
// *
|
||||
// * @param None
|
||||
// *
|
||||
// * @return None
|
||||
// *
|
||||
// *******************************************************************************/
|
||||
// static void Timer_Match0_Cbf(void)
|
||||
// {
|
||||
// MSG("Timer_Match0_Cbf\r\n"); //match0Arrived=1;
|
||||
// //device_close(timer);
|
||||
// }
|
||||
#define TIMER_MAX_VALUE (0xFFFFFFFF)
|
||||
#define TIMER_CLK_DIV (0)
|
||||
|
||||
// /****************************************************************************/ /**
|
||||
// * @brief TIMER match 1 interrupt calllbaeck funtion
|
||||
// *
|
||||
// * @param None
|
||||
// *
|
||||
// * @return None
|
||||
// *
|
||||
// *******************************************************************************/
|
||||
// static void Timer_Match1_Cbf(void)
|
||||
// {
|
||||
// MSG("Timer_Match1_Cbf\r\n"); //match1Arrived=1;
|
||||
// // device_close(timer);
|
||||
// }
|
||||
void TIMER_CH0_IRQ(void);
|
||||
void TIMER_CH1_IRQ(void);
|
||||
|
||||
// /****************************************************************************/ /**
|
||||
// * @brief TIMER match 2 interrupt calllbaeck funtion
|
||||
// *
|
||||
// * @param None
|
||||
// *
|
||||
// * @return None
|
||||
// *
|
||||
// *******************************************************************************/
|
||||
// static void Timer_Match2_Cbf(void)
|
||||
// {
|
||||
// MSG("Timer_Match2_Cbf\r\n"); //match2Arrived=1;
|
||||
// device_close(timer);
|
||||
// }
|
||||
timer_device_t timerx_device[TIMER_MAX_INDEX] =
|
||||
{
|
||||
#ifdef BSP_USING_TIMER_CH0
|
||||
TIMER_CH0_CONFIG,
|
||||
#endif
|
||||
#ifdef BSP_USING_TIMER_CH1
|
||||
TIMER_CH1_CONFIG,
|
||||
#endif
|
||||
};
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @param dev
|
||||
* @param oflag
|
||||
* @return int
|
||||
*/
|
||||
int timer_open(struct device *dev, uint16_t oflag)
|
||||
{
|
||||
timer_device_t *timer_device = (timer_device_t *)dev;
|
||||
TIMER_CFG_Type timer_cfg;
|
||||
|
||||
timer_cfg.timerCh = timer_device->ch;
|
||||
timer_cfg.clkSrc = TIMER_CLK_SRC;
|
||||
timer_cfg.plTrigSrc = timer_device->pl_trig_src;
|
||||
timer_cfg.countMode = timer_device->cnt_mode;
|
||||
timer_cfg.clockDivision = TIMER_CLK_DIV;
|
||||
timer_cfg.matchVal0 = TIMER_MAX_VALUE;
|
||||
timer_cfg.matchVal1 = TIMER_MAX_VALUE;
|
||||
timer_cfg.matchVal2 = TIMER_MAX_VALUE;
|
||||
timer_cfg.preLoadVal = TIMER_MAX_VALUE;
|
||||
|
||||
/* Disable all interrupt */
|
||||
TIMER_IntMask(timer_device->ch,TIMER_INT_ALL, MASK);
|
||||
/* Disable timer before config */
|
||||
TIMER_Disable(timer_device->ch);
|
||||
|
||||
/* Timer init with default configuration */
|
||||
TIMER_Init(&timer_cfg);
|
||||
|
||||
/* Clear interrupt status*/
|
||||
TIMER_ClearIntStatus(timer_device->ch,TIMER_COMP_ID_0);
|
||||
TIMER_ClearIntStatus(timer_device->ch,TIMER_COMP_ID_1);
|
||||
TIMER_ClearIntStatus(timer_device->ch,TIMER_COMP_ID_2);
|
||||
|
||||
#ifdef BSP_USING_TIMER_CH0
|
||||
if( timer_device->ch == TIMER_CH0)
|
||||
Interrupt_Handler_Register(TIMER_CH0_IRQn, TIMER_CH0_IRQ);
|
||||
#endif
|
||||
#ifdef BSP_USING_TIMER_CH1
|
||||
if( timer_device->ch == TIMER_CH1)
|
||||
Interrupt_Handler_Register(TIMER_CH1_IRQn, TIMER_CH1_IRQ);
|
||||
#endif
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @param dev
|
||||
* @return int
|
||||
*/
|
||||
int timer_close(struct device *dev)
|
||||
{
|
||||
|
||||
timer_device_t *timer_device = (timer_device_t *)(dev);
|
||||
TIMER_Disable(timer_device->ch);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @param dev
|
||||
* @param cmd
|
||||
* @param args
|
||||
* @return int
|
||||
*/
|
||||
int timer_control(struct device *dev, int cmd, void *args)
|
||||
{
|
||||
|
||||
timer_device_t* timer_device = (timer_device_t*)dev;
|
||||
switch (cmd)
|
||||
{
|
||||
case DEVICE_CTRL_SET_INT /* constant-expression */:
|
||||
|
||||
break;
|
||||
case DEVICE_CTRL_CLR_INT /* constant-expression */:
|
||||
/* code */
|
||||
{
|
||||
uint32_t offset = __builtin_ctz((uint32_t)args);
|
||||
while((0 <= offset) && (offset < 4))
|
||||
{
|
||||
if((uint32_t)args & (1 << offset))
|
||||
{
|
||||
TIMER_IntMask(timer_device->ch, offset, UNMASK);
|
||||
}
|
||||
offset ++;
|
||||
}
|
||||
if(timer_device->ch == TIMER_CH0)
|
||||
{
|
||||
NVIC_ClearPendingIRQ(TIMER_CH0_IRQn);
|
||||
NVIC_EnableIRQ(TIMER_CH0_IRQn);
|
||||
}
|
||||
else if(timer_device->ch == TIMER_CH1)
|
||||
{
|
||||
NVIC_ClearPendingIRQ(TIMER_CH1_IRQn);
|
||||
NVIC_EnableIRQ(TIMER_CH1_IRQn);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
case DEVICE_CTRL_CLR_INT /* constant-expression */:
|
||||
{
|
||||
uint32_t offset = __builtin_ctz((uint32_t)args);
|
||||
while((0 <= offset) && (offset < 4))
|
||||
{
|
||||
if ((uint32_t)args & (1 << offset))
|
||||
{
|
||||
TIMER_IntMask(timer_device->ch, offset, MASK);
|
||||
}
|
||||
offset ++;
|
||||
}
|
||||
if(timer_device->ch == TIMER_CH0)
|
||||
{
|
||||
NVIC_DisableIRQ(TIMER_CH0_IRQn);
|
||||
}
|
||||
else if (timer_device->ch == TIMER_CH1)
|
||||
{
|
||||
NVIC_DisableIRQ(TIMER_CH1_IRQn);
|
||||
}
|
||||
|
||||
break;
|
||||
}
|
||||
case DEVICE_CTRL_GET_INT /* constant-expression */:
|
||||
/* code */
|
||||
break;
|
||||
@ -95,46 +167,167 @@ int timer_control(struct device *dev, int cmd, void *args)
|
||||
/* code */
|
||||
break;
|
||||
case DEVICE_CTRL_RESUME /* constant-expression */:
|
||||
/* code */
|
||||
{
|
||||
uint32_t offset = __builtin_ctz((uint32_t)args);
|
||||
timer_user_cfg_t *timer_user_cfg = ((timer_user_cfg_t *)(timer_device->parent.handle));
|
||||
uint32_t timeout = (timer_user_cfg->timeout_val * 144 * 1000);
|
||||
TIMER_SetPreloadValue(timer_device->ch, 0);
|
||||
|
||||
if(timer_device->ch == TIMER_CH0)
|
||||
{
|
||||
NVIC_ClearPendingIRQ(TIMER_CH0_IRQn);
|
||||
NVIC_EnableIRQ(TIMER_CH0_IRQn);
|
||||
}
|
||||
else if(timer_device->ch == TIMER_CH1)
|
||||
{
|
||||
NVIC_ClearPendingIRQ(TIMER_CH1_IRQn);
|
||||
NVIC_EnableIRQ(TIMER_CH1_IRQn);
|
||||
}
|
||||
while((0 <= offset) && (offset < 4))
|
||||
{
|
||||
if((uint32_t)args & (1 << offset))
|
||||
{
|
||||
TIMER_SetCompValue(timer_device->ch,offset,timeout);
|
||||
TIMER_IntMask(timer_device->ch, offset, UNMASK);
|
||||
}
|
||||
offset ++;
|
||||
}
|
||||
/* Enable timer */
|
||||
TIMER_Enable(timer_device->ch);
|
||||
break;
|
||||
}
|
||||
case DEVICE_CTRL_SUSPEND /* constant-expression */:
|
||||
/* code */
|
||||
{
|
||||
TIMER_Disable(timer_device->ch);
|
||||
uint32_t offset = __builtin_ctz((uint32_t)args);
|
||||
|
||||
if(timer_device->ch == TIMER_CH0)
|
||||
{
|
||||
NVIC_DisableIRQ(TIMER_CH0_IRQn);
|
||||
}
|
||||
else if (timer_device->ch == TIMER_CH1)
|
||||
{
|
||||
NVIC_DisableIRQ(TIMER_CH1_IRQn);
|
||||
}
|
||||
while((0 <= offset) && (offset < 4))
|
||||
{
|
||||
if ((uint32_t)args & (1 << offset))
|
||||
{
|
||||
TIMER_SetCompValue(timer_device->ch,offset,TIMER_MAX_VALUE);
|
||||
TIMER_IntMask(timer_device->ch, offset, MASK);
|
||||
}
|
||||
offset ++;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case DEVICE_CTRL_GET_CONFIG:
|
||||
return TIMER_GetCounterValue(timer_device->ch);
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
int timer_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
|
||||
{
|
||||
|
||||
return 0;
|
||||
}
|
||||
int timer_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
|
||||
{
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void timer_register(timer_device_t *device, const char *name, uint16_t flag)
|
||||
/**
|
||||
* @brief timer register
|
||||
*
|
||||
* @param index
|
||||
* @param name
|
||||
* @param flag
|
||||
* @param timer_user_cfg
|
||||
* @return int
|
||||
*/
|
||||
|
||||
int timer_register(enum timer_index_type index, const char *name, uint16_t flag, timer_user_cfg_t *timer_user_cfg)
|
||||
{
|
||||
struct device *dev;
|
||||
|
||||
dev = &(device->parent);
|
||||
if(TIMER_MAX_INDEX == 0)
|
||||
return -DEVICE_EINVAL;
|
||||
|
||||
dev = &(timerx_device[index].parent);
|
||||
|
||||
dev->open = timer_open;
|
||||
dev->close = timer_close;
|
||||
dev->control = timer_control;
|
||||
dev->write = NULL;
|
||||
dev->read = NULL;
|
||||
// dev->write = NULL;
|
||||
// dev->read = NULL;
|
||||
|
||||
dev->status = DEVICE_UNREGISTER;
|
||||
dev->type = DEVICE_CLASS_TIMER;
|
||||
dev->handle = NULL;
|
||||
dev->handle = timer_user_cfg;
|
||||
|
||||
device_register(dev, name, flag);
|
||||
return device_register(dev, name, flag);
|
||||
}
|
||||
|
||||
|
||||
void timer_isr(timer_device_t *handle)
|
||||
{
|
||||
uint32_t intId = 0;
|
||||
uint32_t tmpVal = 0;
|
||||
uint32_t tmpAddr = 0;
|
||||
|
||||
intId = BL_RD_WORD(TIMER_BASE + TIMER_TMSR2_OFFSET + 4 * handle->ch);
|
||||
tmpAddr = TIMER_BASE + TIMER_TICR2_OFFSET + 4 * handle->ch;
|
||||
tmpVal = BL_RD_WORD(tmpAddr);
|
||||
|
||||
if(!handle->parent.callback)
|
||||
return;
|
||||
|
||||
/* Comparator 0 match interrupt */
|
||||
if( BL_IS_REG_BIT_SET(intId, TIMER_TMSR_0) ){
|
||||
BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TCLR_0));
|
||||
handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP0);
|
||||
}
|
||||
|
||||
/* Comparator 1 match interrupt */
|
||||
if( BL_IS_REG_BIT_SET(intId,TIMER_TMSR_1) ){
|
||||
BL_WR_WORD(tmpAddr,BL_SET_REG_BIT(tmpVal,TIMER_TCLR_1));
|
||||
handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP1);
|
||||
}
|
||||
|
||||
/* Comparator 2 match interrupt */
|
||||
if( BL_IS_REG_BIT_SET(intId,TIMER_TMSR_2) ){
|
||||
BL_WR_WORD(tmpAddr,BL_SET_REG_BIT(tmpVal,TIMER_TCLR_2));
|
||||
handle->parent.callback(&handle->parent, NULL, 0, TIMER_EVENT_COMP2);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
#ifdef BSP_USING_TIMER_CH0
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
*/
|
||||
void TIMER_CH0_IRQ(void)
|
||||
{
|
||||
timer_isr(&timerx_device[TIMER_CH0_INDEX]);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#ifdef BSP_USING_TIMER_CH1
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
*/
|
||||
void TIMER_CH1_IRQ(void)
|
||||
{
|
||||
timer_isr(&timerx_device[TIMER_CH1_INDEX]);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
|
@ -220,12 +220,40 @@ int uart_control(struct device *dev, int cmd, void *args)
|
||||
}
|
||||
case DEVICE_CTRL_GET_CONFIG /* constant-expression */:
|
||||
break;
|
||||
case DEVICE_CTRL_UART_ATTACH_TX_DMA /* constant-expression */:
|
||||
case DEVICE_CTRL_ATTACH_TX_DMA /* constant-expression */:
|
||||
uart_device->tx_dma = (struct device *)args;
|
||||
break;
|
||||
case DEVICE_CTRL_UART_ATTACH_RX_DMA /* constant-expression */:
|
||||
case DEVICE_CTRL_ATTACH_RX_DMA /* constant-expression */:
|
||||
uart_device->rx_dma = (struct device *)args;
|
||||
break;
|
||||
case DEVICE_CTRL_TX_DMA_SUSPEND:
|
||||
{
|
||||
uint32_t tmpVal = BL_RD_REG(UART0_BASE+uart_device->id*0x100,UART_FIFO_CONFIG_0);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal,UART_DMA_TX_EN);
|
||||
BL_WR_REG(UART0_BASE+uart_device->id*0x100,UART_FIFO_CONFIG_0,tmpVal);
|
||||
break;
|
||||
}
|
||||
case DEVICE_CTRL_RX_DMA_SUSPEND:
|
||||
{
|
||||
uint32_t tmpVal = BL_RD_REG(UART0_BASE+uart_device->id*0x100,UART_FIFO_CONFIG_0);
|
||||
tmpVal = BL_CLR_REG_BIT(tmpVal,UART_DMA_RX_EN);
|
||||
BL_WR_REG(UART0_BASE+uart_device->id*0x100,UART_FIFO_CONFIG_0,tmpVal);
|
||||
break;
|
||||
}
|
||||
case DEVICE_CTRL_TX_DMA_RESUME:
|
||||
{
|
||||
uint32_t tmpVal = BL_RD_REG(UART0_BASE+uart_device->id*0x100,UART_FIFO_CONFIG_0);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal,UART_DMA_TX_EN);
|
||||
BL_WR_REG(UART0_BASE+uart_device->id*0x100,UART_FIFO_CONFIG_0,tmpVal);
|
||||
break;
|
||||
}
|
||||
case DEVICE_CTRL_RX_DMA_RESUME:
|
||||
{
|
||||
uint32_t tmpVal = BL_RD_REG(UART0_BASE+uart_device->id*0x100,UART_FIFO_CONFIG_0);
|
||||
tmpVal = BL_SET_REG_BIT(tmpVal,UART_DMA_RX_EN);
|
||||
BL_WR_REG(UART0_BASE+uart_device->id*0x100,UART_FIFO_CONFIG_0,tmpVal);
|
||||
break;
|
||||
}
|
||||
case DEVICE_CTRL_UART_GET_TX_FIFO /* constant-expression */:
|
||||
return UART_GetTxFifoCount(uart_device->id);
|
||||
case DEVICE_CTRL_UART_GET_RX_FIFO /* constant-expression */:
|
||||
@ -369,16 +397,23 @@ void uart_isr(uart_device_t *handle)
|
||||
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FIFO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FIFO_MASK))
|
||||
{
|
||||
uint8_t buffer[UART_FIFO_MAX_LEN];
|
||||
UART_ReceiveData(handle->id, buffer, handle->fifo_threshold);
|
||||
handle->parent.callback(&handle->parent, &buffer[0], handle->fifo_threshold, UART_EVENT_RX_FIFO);
|
||||
uint8_t len = UART_ReceiveData(handle->id, buffer, handle->fifo_threshold);
|
||||
if(len)
|
||||
{
|
||||
handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RX_FIFO);
|
||||
}
|
||||
}
|
||||
|
||||
/* Rx time-out interrupt */
|
||||
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK))
|
||||
{
|
||||
uint8_t buffer[UART_FIFO_MAX_LEN];
|
||||
uint8_t len = UART_ReceiveData(handle->id, buffer, handle->fifo_threshold);
|
||||
handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO);
|
||||
uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN);
|
||||
if(len)
|
||||
{
|
||||
handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO);
|
||||
}
|
||||
|
||||
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10);
|
||||
}
|
||||
|
||||
|
@ -213,6 +213,13 @@ int usb_open(struct device *dev, uint16_t oflag)
|
||||
/* Init Device */
|
||||
USB_Set_Config(DISABLE, &usbCfg);
|
||||
|
||||
usb_fs_device.out_ep[0].ep_ena = 1U;
|
||||
usb_fs_device.in_ep[0].ep_ena = 1U;
|
||||
usb_fs_device.out_ep[0].ep_cfg.ep_mps = USB_CTRL_EP_MPS;
|
||||
usb_fs_device.out_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL;
|
||||
usb_fs_device.in_ep[0].ep_cfg.ep_mps = USB_CTRL_EP_MPS;
|
||||
usb_fs_device.in_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL;
|
||||
|
||||
/* USB interrupt enable config */
|
||||
USB_IntEn(USB_INT_ALL, DISABLE); //all
|
||||
USB_IntEn(USB_INT_RESET, ENABLE); //1
|
||||
@ -366,25 +373,111 @@ int usb_control(struct device *dev, int cmd, void *args)
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
case DEVICE_CTRL_USB_DC_TX_FIFO_CNT_GET:
|
||||
case DEVICE_CTRL_USB_DC_GET_TX_FIFO_CNT:
|
||||
return USB_Get_EPx_TX_FIFO_CNT(((uint32_t)args) & 0x7f);
|
||||
case DEVICE_CTRL_USB_DC_RX_FIFO_CNT_GET:
|
||||
case DEVICE_CTRL_USB_DC_GET_RX_FIFO_CNT:
|
||||
return USB_Get_EPx_RX_FIFO_CNT(((uint32_t)args) & 0x7f);
|
||||
case DEVICE_CTRL_USB_DC_GET_EP_FREE:
|
||||
return USB_Is_EPx_RDY_Free(((uint32_t)args) & 0x7f);
|
||||
default:
|
||||
break;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
// int usb_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
|
||||
// {
|
||||
int usb_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
|
||||
{
|
||||
uint8_t ret = 0;
|
||||
uint8_t *p = (uint8_t*)buffer;
|
||||
|
||||
// }
|
||||
while(size)
|
||||
{
|
||||
if(USB_Is_EPx_RDY_Free(pos & 0x7f))
|
||||
{
|
||||
uint8_t len = USB_Get_EPx_TX_FIFO_CNT(pos & 0x7f);
|
||||
if(len)
|
||||
{
|
||||
if(len < size)
|
||||
{
|
||||
ret = usb_dc_ep_write(dev,pos,p,len,NULL);
|
||||
size -= len;
|
||||
p += len;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = usb_dc_ep_write(dev,pos,p,size,NULL);
|
||||
p += size;
|
||||
size = 0;
|
||||
}
|
||||
|
||||
// int usb_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
|
||||
// {
|
||||
}
|
||||
}
|
||||
}
|
||||
if(!(size%64))
|
||||
{
|
||||
ret = usb_dc_ep_write(dev,pos,NULL,0,NULL);
|
||||
}
|
||||
return ret;
|
||||
}
|
||||
|
||||
// }
|
||||
int usb_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
|
||||
{
|
||||
uint32_t total_rx_len = 0;
|
||||
uint8_t ret = 0;
|
||||
uint8_t *p = (uint8_t*)buffer;
|
||||
|
||||
while(total_rx_len < size)
|
||||
{
|
||||
if(USB_Is_EPx_RDY_Free(pos))
|
||||
{
|
||||
uint8_t len = USB_Get_EPx_RX_FIFO_CNT(pos);
|
||||
if(len)
|
||||
{
|
||||
ret = usb_dc_ep_read(dev,pos,p,len,NULL);
|
||||
ret = usb_dc_ep_read(dev,pos,NULL,0,NULL);
|
||||
total_rx_len += len;
|
||||
p += len;
|
||||
}
|
||||
else
|
||||
{
|
||||
ret = usb_dc_ep_read(dev,pos,NULL,0,NULL);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @param index
|
||||
* @param name
|
||||
* @param flag
|
||||
* @return int
|
||||
*/
|
||||
int usb_dc_register(enum usb_index_type index, const char *name, uint16_t flag)
|
||||
{
|
||||
struct device *dev;
|
||||
|
||||
if (USB_MAX_INDEX == 0)
|
||||
return -DEVICE_EINVAL;
|
||||
|
||||
dev = &(usb_fs_device.parent);
|
||||
|
||||
dev->open = usb_open;
|
||||
dev->close = usb_close;
|
||||
dev->control = usb_control;
|
||||
dev->write = usb_write;
|
||||
dev->read = usb_read;
|
||||
|
||||
dev->status = DEVICE_UNREGISTER;
|
||||
dev->type = DEVICE_CLASS_USB;
|
||||
dev->handle = NULL;
|
||||
|
||||
return device_register(dev, name, flag);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief configure and enable endpoint
|
||||
@ -476,21 +569,13 @@ int usb_dc_ep_open(struct device *dev, const struct usb_dc_ep_cfg *ep_cfg)
|
||||
/**
|
||||
* @brief Check if the selected endpoint is stalled
|
||||
*
|
||||
* @param dev usb device
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
* @param[out] stalled Endpoint stall status
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @param dev
|
||||
* @param ep
|
||||
* @param stalled
|
||||
* @return int
|
||||
*/
|
||||
int usb_dc_ep_is_stalled(struct device *dev, const uint8_t ep, uint8_t *stalled)
|
||||
{
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
@ -514,6 +599,7 @@ int usb_dc_ep_is_stalled(struct device *dev, const uint8_t ep, uint8_t *stalled)
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write data to the specified endpoint
|
||||
*
|
||||
@ -521,6 +607,7 @@ int usb_dc_ep_is_stalled(struct device *dev, const uint8_t ep, uint8_t *stalled)
|
||||
* supplied usbd_endpoint_callback function will be called when data is transmitted
|
||||
* out.
|
||||
*
|
||||
* @param dev
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
* @param[in] data Pointer to data to write
|
||||
@ -532,23 +619,13 @@ int usb_dc_ep_is_stalled(struct device *dev, const uint8_t ep, uint8_t *stalled)
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @param dev
|
||||
* @param ep
|
||||
* @param data
|
||||
* @param data_len
|
||||
* @param ret_bytes
|
||||
* @return int
|
||||
*/
|
||||
int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes)
|
||||
{
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
uint8_t ep_idx;
|
||||
uint32_t timeout = 0x00FFFFFF;
|
||||
uint32_t ep_tx_fifo_addr;
|
||||
|
||||
ep_idx = USB_EP_GET_IDX(ep);
|
||||
/* Check if IN ep */
|
||||
if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN)
|
||||
{
|
||||
@ -602,8 +679,6 @@ int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, u
|
||||
{
|
||||
break;
|
||||
}
|
||||
/* Make sure we don't hog the CPU */
|
||||
// k_yield();
|
||||
//USB_DC_LOG_ERR("EP%d have remain data\r\n", ep_idx);
|
||||
}
|
||||
while (1);
|
||||
@ -618,12 +693,20 @@ int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, u
|
||||
* before accessing the register."
|
||||
*/
|
||||
ep_tx_fifo_addr = USB_BASE + USB_EP0_TX_FIFO_WDATA_OFFSET + ep_idx * 0x10;
|
||||
|
||||
if((data_len == 1) && (ep_idx == 0))
|
||||
{
|
||||
USB_Set_EPx_Xfer_Size(EP_ID0,1);
|
||||
}
|
||||
else if(ep_idx == 0)
|
||||
{
|
||||
USB_Set_EPx_Xfer_Size(EP_ID0,64);
|
||||
}
|
||||
|
||||
memcopy_to_fifo((void *)ep_tx_fifo_addr, (uint8_t *)data, data_len);
|
||||
/* Clear NAK and enable ep */
|
||||
USB_Set_EPx_Status(USB_EP_GET_IDX(ep), USB_EP_STATUS_ACK);
|
||||
|
||||
// irq_unlock(key);
|
||||
|
||||
USB_DC_LOG_DBG("EP%d write %u bytes\r\n", ep_idx, data_len);
|
||||
|
||||
if (ret_bytes)
|
||||
@ -633,6 +716,7 @@ int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, u
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Read data from the specified endpoint
|
||||
*
|
||||
@ -640,7 +724,8 @@ int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, u
|
||||
* clear the endpoint NAKs so that the consumer is not bogged down by further
|
||||
* upcalls till he is done with the processing of the data. The caller should
|
||||
* reactivate ep by invoking usb_dc_ep_read_continue() do so.
|
||||
*
|
||||
*
|
||||
* @param dev
|
||||
* @param[in] ep Endpoint address corresponding to the one
|
||||
* listed in the device configuration table
|
||||
* @param[in] data Pointer to data buffer to write to
|
||||
@ -651,17 +736,6 @@ int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, u
|
||||
*
|
||||
* @return 0 on success, negative errno code on fail.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @param dev
|
||||
* @param ep
|
||||
* @param data
|
||||
* @param data_len
|
||||
* @param read_bytes
|
||||
* @return int
|
||||
*/
|
||||
int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes)
|
||||
{
|
||||
uint8_t ep_idx = USB_EP_GET_IDX(ep);
|
||||
@ -718,45 +792,15 @@ int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t
|
||||
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @param index
|
||||
* @param name
|
||||
* @param flag
|
||||
* @return int
|
||||
*/
|
||||
int usb_dc_register(enum usb_index_type index, const char *name, uint16_t flag)
|
||||
{
|
||||
struct device *dev;
|
||||
|
||||
if (USB_MAX_INDEX == 0)
|
||||
return -DEVICE_EINVAL;
|
||||
|
||||
dev = &(usb_fs_device.parent);
|
||||
|
||||
dev->open = usb_open;
|
||||
dev->close = usb_close;
|
||||
dev->control = usb_control;
|
||||
// dev->write = usb_write;
|
||||
// dev->read = usb_read;
|
||||
|
||||
dev->status = DEVICE_UNREGISTER;
|
||||
dev->type = DEVICE_CLASS_USB;
|
||||
dev->handle = NULL;
|
||||
|
||||
return device_register(dev, name, flag);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief
|
||||
*
|
||||
* @param dev
|
||||
* @param rb
|
||||
* @param ep
|
||||
* @return uint16_t
|
||||
* @return int
|
||||
*/
|
||||
uint16_t usb_dc_receive_to_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep)
|
||||
int usb_dc_receive_to_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep)
|
||||
{
|
||||
uint8_t ep_idx;
|
||||
uint8_t recv_len;
|
||||
@ -791,28 +835,26 @@ uint16_t usb_dc_receive_to_ringbuffer(struct device *dev, Ring_Buffer_Type *rb,
|
||||
/*if rx fifo count equal 0,it means last is send nack and ringbuffer is smaller than 64,
|
||||
* so,if ringbuffer is larger than 64,set ack to recv next data.
|
||||
*/
|
||||
if(overflow_flag && (Ring_Buffer_Get_Empty_Length(rb)>64))
|
||||
if(overflow_flag && (Ring_Buffer_Get_Empty_Length(rb)>64) && (!recv_len))
|
||||
{
|
||||
overflow_flag = false;
|
||||
USB_Set_EPx_Rdy(ep_idx);
|
||||
return -USB_DC_RB_SIZE_SMALL_ERR;
|
||||
return 0;
|
||||
}
|
||||
|
||||
else if(recv_len)
|
||||
else
|
||||
{
|
||||
uint32_t addr = USB_BASE + 0x11C + (ep_idx - 1) * 0x10;
|
||||
uint32_t actual_len = Ring_Buffer_Write_Callback(rb, recv_len, fifocopy_to_mem, (void *)addr);
|
||||
Ring_Buffer_Write_Callback(rb, recv_len, fifocopy_to_mem, (void *)addr);
|
||||
|
||||
if(Ring_Buffer_Get_Empty_Length(rb) < 64)
|
||||
{
|
||||
overflow_flag = true;
|
||||
return actual_len;
|
||||
return -USB_DC_RB_SIZE_SMALL_ERR;
|
||||
}
|
||||
|
||||
USB_Set_EPx_Rdy(ep_idx);
|
||||
return actual_len;
|
||||
return 0;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
/**
|
||||
* @brief
|
||||
@ -820,15 +862,17 @@ uint16_t usb_dc_receive_to_ringbuffer(struct device *dev, Ring_Buffer_Type *rb,
|
||||
* @param dev
|
||||
* @param rb
|
||||
* @param ep
|
||||
* @return uint16_t
|
||||
* @return int
|
||||
*/
|
||||
uint16_t usb_dc_send_from_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep)
|
||||
int usb_dc_send_from_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep)
|
||||
{
|
||||
uint8_t ep_idx;
|
||||
uint32_t timeout = 0x00FFFFFF;
|
||||
static bool zlp_flag = false;
|
||||
static uint32_t send_total_len = 0;
|
||||
|
||||
ep_idx = USB_EP_GET_IDX(ep);
|
||||
|
||||
/* Check if IN ep */
|
||||
if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN)
|
||||
{
|
||||
@ -855,17 +899,18 @@ uint16_t usb_dc_send_from_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, u
|
||||
|
||||
if(zlp_flag == false)
|
||||
{
|
||||
if (USB_Get_EPx_TX_FIFO_CNT(ep_idx) == USB_FS_MAX_PACKET_SIZE && Ring_Buffer_Get_Length(rb))
|
||||
if ((USB_Get_EPx_TX_FIFO_CNT(ep_idx) == USB_FS_MAX_PACKET_SIZE) && Ring_Buffer_Get_Length(rb))
|
||||
{
|
||||
uint32_t actual_len = Ring_Buffer_Read_Callback(rb, USB_FS_MAX_PACKET_SIZE, memcopy_to_fifo, (void *)addr);
|
||||
uint32_t actual_len = Ring_Buffer_Read_Callback(rb, USB_FS_MAX_PACKET_SIZE, memcopy_to_fifo, (void *)addr);
|
||||
send_total_len += actual_len;
|
||||
|
||||
if(!Ring_Buffer_Get_Length(rb) && (!(send_total_len % 64)))
|
||||
{
|
||||
zlp_flag = true;
|
||||
}
|
||||
USB_Set_EPx_Rdy(ep_idx);
|
||||
|
||||
return actual_len;
|
||||
USB_Set_EPx_Rdy(ep_idx);
|
||||
return 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -879,8 +924,6 @@ uint16_t usb_dc_send_from_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, u
|
||||
USB_Set_EPx_Rdy(ep_idx);
|
||||
return -USB_DC_ZLP_ERR;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/**
|
||||
|
Reference in New Issue
Block a user