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[update][drivers] add misc functions

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This commit is contained in:
jzlv 2021-11-10 16:58:18 +08:00
parent a9ea715135
commit 70d8bbde68
21 changed files with 142 additions and 144 deletions
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1
drivers/bl602_driver/hal_drv/inc/hal_common.h
View File

@ -27,6 +27,7 @@
void cpu_global_irq_enable(void);
void cpu_global_irq_disable(void);
void hal_por_reset(void);
void hal_system_reset(void);
void hal_cpu_reset(void);
void hal_get_chip_id(uint8_t chip_id[8]);

9
drivers/bl602_driver/hal_drv/inc/hal_uart.h
View File

@ -110,14 +110,6 @@ enum uart_event_type {
UART_EVENT_UNKNOWN
};
typedef struct
{
uint8_t tx;
uint8_t rx;
uint8_t cts;
uint8_t rts;
} uart_pin_t;
enum uart_it_type {
UART_TX_END_IT = 1 << 0,
UART_RX_END_IT = 1 << 1,
@ -146,7 +138,6 @@ typedef struct uart_device {
uart_stopbits_t stopbits;
uart_parity_t parity;
uint8_t fifo_threshold;
uart_pin_t pin;
void *tx_dma;
void *rx_dma;
} uart_device_t;

36
drivers/bl602_driver/hal_drv/src/hal_clock.c
View File

@ -13,18 +13,18 @@ void system_clock_init(void)
/*set fclk/hclk and bclk clock*/
GLB_Set_System_CLK_Div(BSP_FCLK_DIV, BSP_BCLK_DIV);
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
#if 1
#if XTAL_32K_TYPE == INTERNAL_RC_32K
HBN_32K_Sel(HBN_32K_RC);
HBN_Power_Off_Xtal_32K();
#else
HBN_32K_Sel(HBN_32K_XTAL);
HBN_Power_On_Xtal_32K();
#endif
if ((XTAL_TYPE == INTERNAL_RC_32M) || (XTAL_TYPE == XTAL_NONE)) {
HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_RC32M);
} else {
HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_XTAL);
}
#if (XTAL_TYPE == INTERNAL_RC_32M) || (XTAL_TYPE == XTAL_NONE)
HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_RC32M);
#else
HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_XTAL);
#endif
}
void system_mtimer_clock_init(void)
@ -148,31 +148,31 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
uint32_t div;
switch (type) {
case PERIPHERAL_CLOCK_UART:
#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1)
#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_160M
return 160000000;
#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
return system_clock_get(SYSTEM_CLOCK_FCLK) / (GLB_Get_HCLK_Div() + 1));
#endif
#endif
case PERIPHERAL_CLOCK_UART:
tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL);
case PERIPHERAL_CLOCK_SPI:
div = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
div = BL_GET_REG_BITS_VAL(div, GLB_UART_CLK_DIV);
if (tmpVal == HBN_UART_CLK_FCLK) {
return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
} else if (tmpVal == HBN_UART_CLK_160M) {
return 160000000 / (div + 1);
}
#endif
#if defined(BSP_USING_SPI0)
#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
case PERIPHERAL_CLOCK_SPI:
tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV);
return system_clock_get(SYSTEM_CLOCK_BCLK) / (div + 1);
#endif
#endif
case PERIPHERAL_CLOCK_I2C:
#if defined(BSP_USING_I2C0)
#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
div = BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV);
return system_clock_get(SYSTEM_CLOCK_BCLK) / (div + 1);
#endif
#endif
case PERIPHERAL_CLOCK_ADC:

5
drivers/bl602_driver/hal_drv/src/hal_common.c
View File

@ -41,6 +41,11 @@ void ATTR_TCM_SECTION cpu_global_irq_disable(void)
nesting++;
}
void hal_por_reset(void)
{
RomDriver_GLB_SW_POR_Reset();
}
void hal_system_reset(void)
{
RomDriver_GLB_SW_System_Reset();

10
drivers/bl602_driver/hal_drv/src/hal_uart.c
View File

@ -35,14 +35,11 @@
*/
#include "hal_uart.h"
#include "hal_dma.h"
#include "hal_gpio.h"
#include "hal_clock.h"
#include "bl602_uart.h"
#include "bl602_glb.h"
#include "uart_config.h"
#define UART_CLOCK (40000000)
#ifdef BSP_USING_UART0
void UART0_IRQ(void);
#endif
@ -76,18 +73,17 @@ int uart_open(struct device *dev, uint16_t oflag)
/* disable uart before config */
UART_Disable(uart_device->id, UART_TXRX);
//uint32_t uart_clk = peripheral_clock_get(PERIPHERAL_CLOCK_UART);
uint32_t uart_clk = peripheral_clock_get(PERIPHERAL_CLOCK_UART);
uart_cfg.baudRate = uart_device->baudrate;
uart_cfg.dataBits = uart_device->databits;
uart_cfg.stopBits = uart_device->stopbits;
uart_cfg.parity = uart_device->parity;
uart_cfg.uartClk = UART_CLOCK;
uart_cfg.uartClk = uart_clk;
uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE;
uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE;
uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE;
GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_160M, 160000000 / UART_CLOCK - 1);
/* uart init with default configuration */
UART_Init(uart_device->id, &uart_cfg);
@ -173,10 +169,8 @@ int uart_control(struct device *dev, int cmd, void *args)
}
if (uart_device->id == UART0_ID) {
Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ);
CPU_Interrupt_Enable(UART0_IRQn);
} else if (uart_device->id == UART1_ID) {
Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ);
CPU_Interrupt_Enable(UART1_IRQn);
}

4
drivers/bl702_driver/hal_drv/default_config/i2c_config.h
View File

@ -1,4 +0,0 @@
#ifndef _I2C_CONFIG_H
#define _I2C_CONFIG_H
#endif

17
drivers/bl702_driver/hal_drv/default_config/power_config.h
View File

@ -1,17 +0,0 @@
#ifndef _POWER_CONFIG_H
#define _POWER_CONFIG_H
#define DEAULT_LP_XTAL_TYPE GLB_DLL_XTAL_32M
#define DEFAULT_LP_LDO_LEVEL PDS_LDO_LEVEL_1P10V
#define DEFAULT_LP_PDS_AON_GPIO_WAKE_UP_SRC PDS_AON_WAKEUP_GPIO_10
#define DEFAULT_LP_PDS_AON_GPIO_TRIG_TYPE PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE
#define DEFAULT_LP_PDS_FLASH_POWER_DOWN 1
#define DEFAULT_LP_PDS_HOLD_GPIO 0
#define DEFAULT_LP_PDS_TURN_OFF_FLASH_PAD 1
#define DEFAULT_LP_PDS_TURN_OFF_XTAL_32M 1
#define DEFAULT_LP_PDS_TURN_OFF_DLL 1
#define DEFAULT_LP_PDS_TURN_OFF_RF 1
#define DEFAULT_LP_PDS_USE_XTAL_32K 0
#endif

6
drivers/bl702_driver/hal_drv/default_config/pwm_config.h
View File

@ -1,6 +0,0 @@
#ifndef _PWM_CONFIG_H
#define _PWM_CONFIG_H
#define PWM_STOP_MODE_SEL (PWM_STOP_GRACEFUL)
#endif

8
drivers/bl702_driver/hal_drv/default_config/spi_config.h
View File

@ -1,8 +0,0 @@
#ifndef _SPI_CONFIG_H
#define _SPI_CONFIG_H
#define SPI_DEGLITCH_ENABLE (0)
#define SPI_CONTINUE_TRANSFER_ENABLE (1)
#define SPI_SWAP_ENABLE (1)
#endif

6
drivers/bl702_driver/hal_drv/default_config/timer_config.h
View File

@ -1,6 +0,0 @@
#ifndef _TIMER_CONFIG_H
#define _TIMER_CONFIG_H
#define TIMER_CLK_SRC (0)
#endif

10
drivers/bl702_driver/hal_drv/default_config/usb_config.h
View File

@ -1,10 +0,0 @@
#ifndef _USB_CONFIG_H
#define _USB_CONFIG_H
//#define USE_EXTERNAL_TRANSCEIVER
#define USE_INTERNAL_TRANSCEIVER
#define ENABLE_LPM_INT
//#define ENABLE_SOF3MS_INT
//#define ENABLE_ERROR_INT
#endif

3
drivers/bl702_driver/hal_drv/inc/hal_cam.h
View File

@ -32,8 +32,9 @@ extern "C" {
#include "drv_device.h"
#include "bl702_config.h"
#define DEVICE_CTRL_CAM_FRAME_CUT 0x10
#define DEVICE_CTRL_CAM_FRAME_CUT 0x10
#define DEVICE_CTRL_CAM_FRAME_DROP 0x11
#define DEVICE_CTRL_CAM_FRAME_WRAP 0x12
enum cam_index_type {
#ifdef BSP_USING_CAM0

1
drivers/bl702_driver/hal_drv/inc/hal_common.h
View File

@ -31,6 +31,7 @@ extern "C" {
void cpu_global_irq_enable(void);
void cpu_global_irq_disable(void);
void hal_por_reset(void);
void hal_system_reset(void);
void hal_cpu_reset(void);
void hal_get_chip_id(uint8_t chip_id[8]);

6
drivers/bl702_driver/hal_drv/inc/hal_pm.h
View File

@ -48,19 +48,23 @@ enum pm_hbn_sleep_level {
};
enum pm_event_type {
PM_HBN_WAKEUP_EVENT_NONE,
PM_HBN_GPIO9_WAKEUP_EVENT,
PM_HBN_GPIO10_WAKEUP_EVENT,
PM_HBN_GPIO11_WAKEUP_EVENT,
PM_HBN_GPIO12_WAKEUP_EVENT,
PM_HBN_RTC_WAKEUP_EVENT,
PM_HBN_BOR_WAKEUP_EVENT,
PM_HBN_ACOMP0_WAKEUP_EVENT,
PM_HBN_ACOMP1_WAKEUP_EVENT,
};
void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time);
void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8_t sleep_time);
void pm_set_wakeup_callback(void (*wakeup_callback)(void));
void pm_hbn_enter_again(bool reset);
void pm_set_wakeup_callback(void (*wakeup_callback)(void));
enum pm_event_type pm_get_wakeup_event(void);
void pm_bor_init(void);
void pm_hbn_out0_irq_register(void);
void pm_hbn_out1_irq_register(void);
void pm_irq_callback(enum pm_event_type event);

7
drivers/bl702_driver/hal_drv/src/hal_cam.c
View File

@ -147,6 +147,13 @@ int cam_control(struct device *dev, int cmd, void *args)
BL_WR_REG(CAM_BASE, CAM_DVP_FRAME_FIFO_POP, 3);
}
break;
case DEVICE_CTRL_CAM_FRAME_WRAP: {
uint32_t tmpVal;
tmpVal = BL_RD_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_HW_MODE_FWRAP, ((uint32_t)args) & 0x01);
BL_WR_REG(CAM_BASE, CAM_DVP2AXI_CONFIGUE, tmpVal);
} break;
default:
break;
}

16
drivers/bl702_driver/hal_drv/src/hal_clock.c
View File

@ -72,9 +72,11 @@ void system_clock_init(void)
GLB_Set_System_CLK_Div(BSP_FCLK_DIV, BSP_BCLK_DIV);
/* Set MTimer the same frequency as SystemCoreClock */
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
#ifndef FAST_WAKEUP
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
PDS_Set_Audio_PLL_Freq(BSP_AUDIO_PLL_CLOCK_SOURCE - ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ);
#endif
#endif
#if XTAL_32K_TYPE == INTERNAL_RC_32K
HBN_32K_Sel(HBN_32K_RC);
HBN_Power_Off_Xtal_32K();
@ -82,11 +84,11 @@ void system_clock_init(void)
HBN_Power_On_Xtal_32K();
HBN_32K_Sel(HBN_32K_XTAL);
#endif
if ((XTAL_TYPE == INTERNAL_RC_32M) || (XTAL_TYPE == XTAL_NONE)) {
HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_RC32M);
} else {
HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_XTAL);
}
#if XTAL_TYPE == EXTERNAL_XTAL_32M
HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_XTAL);
#else
HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_RC32M);
#endif
}
void peripheral_clock_init(void)
@ -360,7 +362,7 @@ void peripheral_clock_init(void)
#endif
#if defined(BSP_USING_ADC0)
//tmpVal |= (1 << BL_AHB_SLAVE1_GPIP);
tmpVal |= (1 << BL_AHB_SLAVE1_GPIP);
#if BSP_ADC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_AUDIO_PLL, BSP_ADC_CLOCK_DIV);
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
@ -371,7 +373,7 @@ void peripheral_clock_init(void)
#endif
#if defined(BSP_USING_DAC0)
//tmpVal |= (1 << BL_AHB_SLAVE1_GPIP);
tmpVal |= (1 << BL_AHB_SLAVE1_GPIP);
#if BSP_DAC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, BSP_DAC_CLOCK_DIV + 1);
#elif BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK

7
drivers/bl702_driver/hal_drv/src/hal_common.c
View File

@ -43,6 +43,11 @@ void ATTR_TCM_SECTION cpu_global_irq_disable(void)
nesting++;
}
void hal_por_reset(void)
{
RomDriver_GLB_SW_POR_Reset();
}
void hal_system_reset(void)
{
RomDriver_GLB_SW_System_Reset();
@ -63,7 +68,7 @@ void hal_enter_usb_iap(void)
BL_WR_WORD(HBN_BASE + HBN_RSV0_OFFSET, 0x00425355); //"\0BSU"
arch_delay_ms(1000);
RomDriver_GLB_SW_System_Reset();
RomDriver_GLB_SW_POR_Reset();
}
void ATTR_TCM_SECTION hal_jump2app(uint32_t flash_offset)

100
drivers/bl702_driver/hal_drv/src/hal_pm.c
View File

@ -401,6 +401,7 @@ static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel3 = {
.MiscDigPwrOff = 1,
}
};
#if 0
static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel4 = {
.pdsCtl = {
.pdsStart = 1,
@ -749,6 +750,7 @@ static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel7 = {
.MiscDigPwrOff = 1,
}
};
#endif
static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel31 = {
.pdsCtl = {
.pdsStart = 1,
@ -928,17 +930,13 @@ ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint3
pPdsCfg = &pdsCfgLevel3;
break;
case PM_PDS_LEVEL_4:
pPdsCfg = &pdsCfgLevel4;
break;
return;
case PM_PDS_LEVEL_5:
pPdsCfg = &pdsCfgLevel5;
break;
return;
case PM_PDS_LEVEL_6:
pPdsCfg = &pdsCfgLevel6;
break;
return;
case PM_PDS_LEVEL_7:
pPdsCfg = &pdsCfgLevel7;
break;
return;
case PM_PDS_LEVEL_31:
pPdsCfg = &pdsCfgLevel31;
break;
@ -1237,13 +1235,6 @@ ATTR_TCM_SECTION void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8
}
}
void pm_set_wakeup_callback(void (*wakeup_callback)(void))
{
BL_WR_REG(HBN_BASE, HBN_RSV1, (uint32_t)wakeup_callback);
/* Set HBN flag */
BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
}
ATTR_HBN_RAM_SECTION void pm_hbn_enter_again(bool reset)
{
uint32_t tmpVal;
@ -1258,6 +1249,60 @@ ATTR_HBN_RAM_SECTION void pm_hbn_enter_again(bool reset)
tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
}
void pm_set_wakeup_callback(void (*wakeup_callback)(void))
{
BL_WR_REG(HBN_BASE, HBN_RSV1, (uint32_t)wakeup_callback);
/* Set HBN flag */
BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
}
enum pm_event_type pm_get_wakeup_event(void)
{
if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO9)) {
return PM_HBN_GPIO9_WAKEUP_EVENT;
} else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO10)) {
return PM_HBN_GPIO10_WAKEUP_EVENT;
} else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO11)) {
return PM_HBN_GPIO11_WAKEUP_EVENT;
} else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO12)) {
return PM_HBN_GPIO12_WAKEUP_EVENT;
} else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_GPIO10)) {
} else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_PIR)) {
} else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_BOR)) {
return PM_HBN_BOR_WAKEUP_EVENT;
} else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_ACOMP0)) {
return PM_HBN_ACOMP0_WAKEUP_EVENT;
} else if (BL_RD_REG(HBN_BASE, HBN_IRQ_STAT) & (1 << HBN_INT_ACOMP1)) {
return PM_HBN_ACOMP1_WAKEUP_EVENT;
}
return PM_HBN_WAKEUP_EVENT_NONE;
}
void pm_bor_init(void)
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOR);
BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOR);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, HBN_BOR_THRES_2P4V);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_SEL, HBN_BOR_MODE_POR_INDEPENDENT);
BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
}
void pm_hbn_out0_irq_register(void)
{
Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT0_IRQ);
@ -1275,23 +1320,16 @@ void HBN_OUT0_IRQ(void)
if (SET == HBN_Get_INT_State(HBN_INT_GPIO9)) {
HBN_Clear_IRQ(HBN_INT_GPIO9);
pm_irq_callback(PM_HBN_GPIO9_WAKEUP_EVENT);
}
if (SET == HBN_Get_INT_State(HBN_INT_GPIO10)) {
} else if (SET == HBN_Get_INT_State(HBN_INT_GPIO10)) {
HBN_Clear_IRQ(HBN_INT_GPIO10);
pm_irq_callback(PM_HBN_GPIO10_WAKEUP_EVENT);
}
if (SET == HBN_Get_INT_State(HBN_INT_GPIO11)) {
} else if (SET == HBN_Get_INT_State(HBN_INT_GPIO11)) {
HBN_Clear_IRQ(HBN_INT_GPIO11);
pm_irq_callback(PM_HBN_GPIO11_WAKEUP_EVENT);
}
if (SET == HBN_Get_INT_State(HBN_INT_GPIO12)) {
} else if (SET == HBN_Get_INT_State(HBN_INT_GPIO12)) {
HBN_Clear_IRQ(HBN_INT_GPIO12);
pm_irq_callback(PM_HBN_GPIO12_WAKEUP_EVENT);
}
if (SET == HBN_Get_INT_State(HBN_INT_RTC)) {
} else {
HBN_Clear_IRQ(HBN_INT_RTC);
HBN_Clear_RTC_INT();
pm_irq_callback(PM_HBN_RTC_WAKEUP_EVENT);
@ -1304,20 +1342,18 @@ void HBN_OUT1_IRQ(void)
if (SET == HBN_Get_INT_State(HBN_INT_PIR)) {
HBN_Clear_IRQ(HBN_INT_PIR);
}
/* BOR */
if (SET == HBN_Get_INT_State(HBN_INT_BOR)) {
else if (SET == HBN_Get_INT_State(HBN_INT_BOR)) {
HBN_Clear_IRQ(HBN_INT_BOR);
pm_irq_callback(PM_HBN_BOR_WAKEUP_EVENT);
}
/* ACOMP0 */
if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) {
else if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) {
HBN_Clear_IRQ(HBN_INT_ACOMP0);
pm_irq_callback(PM_HBN_ACOMP0_WAKEUP_EVENT);
}
/* ACOMP1 */
if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) {
else if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) {
HBN_Clear_IRQ(HBN_INT_ACOMP1);
pm_irq_callback(PM_HBN_ACOMP1_WAKEUP_EVENT);
}

18
drivers/bl702_driver/hal_drv/src/hal_spi.c
View File

@ -251,6 +251,7 @@ int spi_control(struct device *dev, int cmd, void *args)
*/
int spi_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
int ret = 0;
spi_device_t *spi_device = (spi_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_TX) {
@ -280,13 +281,12 @@ int spi_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t siz
break;
}
dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_SPI_TDR, size);
ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_SPI_TDR, size);
dma_channel_start(dma_ch);
}
return 0;
return ret;
} else if (dev->oflag & DEVICE_OFLAG_INT_TX) {
return -1;
return -2;
} else {
if (spi_device->datasize == SPI_DATASIZE_8BIT) {
return SPI_Send_8bits(spi_device->id, (uint8_t *)buffer, size, SPI_TIMEOUT_DISABLE);
@ -310,6 +310,7 @@ int spi_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t siz
*/
int spi_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
int ret = 0;
spi_device_t *spi_device = (spi_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_RX) {
@ -337,16 +338,13 @@ int spi_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
break;
default:
break;
dma_reload(dma_ch, (uint32_t)DMA_ADDR_SPI_RDR, (uint32_t)buffer, size);
dma_channel_start(dma_ch);
}
dma_reload(dma_ch, (uint32_t)DMA_ADDR_SPI_RDR, (uint32_t)buffer, size);
ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_SPI_RDR, (uint32_t)buffer, size);
dma_channel_start(dma_ch);
}
return 0;
return ret;
} else if (dev->oflag & DEVICE_OFLAG_INT_TX) {
return -1;
return -2;
} else {
if (spi_device->datasize == SPI_DATASIZE_8BIT) {
return SPI_Recv_8bits(spi_device->id, (uint8_t *)buffer, size, SPI_TIMEOUT_DISABLE);

14
drivers/bl702_driver/hal_drv/src/hal_uart.c
View File

@ -270,6 +270,7 @@ int uart_control(struct device *dev, int cmd, void *args)
*/
int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size)
{
int ret = 0;
uart_device_t *uart_device = (uart_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_TX) {
struct device *dma_ch = (struct device *)uart_device->tx_dma;
@ -277,13 +278,13 @@ int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t si
return -1;
if (uart_device->id == 0) {
dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART0_TDR, size);
ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART0_TDR, size);
dma_channel_start(dma_ch);
} else if (uart_device->id == 1) {
dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART1_TDR, size);
ret = dma_reload(dma_ch, (uint32_t)buffer, (uint32_t)DMA_ADDR_UART1_TDR, size);
dma_channel_start(dma_ch);
}
return 0;
return ret;
} else if (dev->oflag & DEVICE_OFLAG_INT_TX) {
return -2;
} else
@ -300,6 +301,7 @@ int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t si
*/
int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
int ret = -1;
uart_device_t *uart_device = (uart_device_t *)dev;
if (dev->oflag & DEVICE_OFLAG_DMA_RX) {
struct device *dma_ch = (struct device *)uart_device->rx_dma;
@ -307,13 +309,13 @@ int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
return -1;
if (uart_device->id == 0) {
dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART0_RDR, (uint32_t)buffer, size);
ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART0_RDR, (uint32_t)buffer, size);
dma_channel_start(dma_ch);
} else if (uart_device->id == 1) {
dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART1_RDR, (uint32_t)buffer, size);
ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART1_RDR, (uint32_t)buffer, size);
dma_channel_start(dma_ch);
}
return 0;
return ret;
} else if (dev->oflag & DEVICE_OFLAG_INT_RX) {
return -2;
} else {

2
drivers/bl702_driver/hal_drv/src/hal_usb.c
View File

@ -410,6 +410,7 @@ int usb_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t siz
usb_lli_list.cfg.bits.DBSize = DMA_BURST_1BYTE;
device_control(usb_device->tx_dma, DMA_CHANNEL_UPDATE, (void *)((uint32_t)&usb_lli_list));
dma_channel_start(usb_device->tx_dma);
return 0;
} else {
}
@ -434,6 +435,7 @@ int usb_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
usb_lli_list.cfg.bits.DBSize = DMA_BURST_16BYTE;
device_control(usb_device->rx_dma, DMA_CHANNEL_UPDATE, (void *)((uint32_t)&usb_lli_list));
dma_channel_start(usb_device->rx_dma);
return 0;
} else {
}