diff --git a/drivers/lhal/CMakeLists.txt b/drivers/lhal/CMakeLists.txt index 4f2e3aae..ce0c1d30 100644 --- a/drivers/lhal/CMakeLists.txt +++ b/drivers/lhal/CMakeLists.txt @@ -3,9 +3,11 @@ sdk_generate_library() sdk_library_add_sources(src/bflb_common.c) sdk_library_add_sources(src/bflb_adc.c) +if((NOT ("${CHIP}" STREQUAL "bl702l"))) sdk_library_add_sources(src/bflb_dac.c) +endif() sdk_library_add_sources(src/bflb_dma.c) -if((NOT ("${CHIP}" STREQUAL "bl602"))) +if((NOT ("${CHIP}" STREQUAL "bl602")) AND (NOT ("${CHIP}" STREQUAL "bl702l"))) sdk_library_add_sources(src/bflb_emac.c) endif() sdk_library_add_sources(src/bflb_gpio.c) @@ -17,10 +19,9 @@ sdk_library_add_sources(src/bflb_rtc.c) sdk_library_add_sources(src/bflb_sec_aes.c) sdk_library_add_sources(src/bflb_sec_sha.c) sdk_library_add_sources(src/bflb_sec_trng.c) -# sdk_library_add_sources(src/bflb_sec_pka.c) sdk_library_add_sources(src/bflb_timer.c) sdk_library_add_sources(src/bflb_wdg.c) - +sdk_library_add_sources(src/bflb_cks.c) # sdk_library_add_sources(src/bflb_clock.c) if(("${CHIP}" STREQUAL "bl702") OR ("${CHIP}" STREQUAL "bl602")) @@ -37,7 +38,6 @@ if("${CHIP}" STREQUAL "bl702") sdk_library_add_sources(src/bflb_usb_v1.c) elseif(("${CHIP}" STREQUAL "bl602") OR ("${CHIP}" STREQUAL "bl702l")) # no usb -else() sdk_library_add_sources(src/bflb_usb_v2.c) endif() endif() @@ -65,4 +65,8 @@ sdk_add_compile_definitions(-D${CHIPNAME}) if(CPU_ID) string(TOUPPER ${CPU_ID} CPU_ID_NAME) sdk_add_compile_definitions(-DCPU_${CPU_ID_NAME}) -endif() \ No newline at end of file +endif() + +sdk_add_link_libraries(${CMAKE_CURRENT_SOURCE_DIR}/src/pka/libpka.a) +sdk_add_link_options(-ubflb_trng_readlen) +#add_subdirectory(src/pka) \ No newline at end of file diff --git a/drivers/lhal/config/bl602/device_table.c b/drivers/lhal/config/bl602/device_table.c index cd9c382d..7c410f5f 100644 --- a/drivers/lhal/config/bl602/device_table.c +++ b/drivers/lhal/config/bl602/device_table.c @@ -155,6 +155,13 @@ struct bflb_device_s bl602_device_table[] = { .sub_idx = 0, .dev_type = BFLB_DEVICE_TYPE_TRNG, .user_data = NULL }, + { .name = "pka", + .reg_base = SEC_ENG_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_PKA, + .user_data = NULL }, }; struct bflb_device_s *bflb_device_get_by_name(const char *name) diff --git a/drivers/lhal/config/bl616/device_table.c b/drivers/lhal/config/bl616/device_table.c index 03bc69e2..35d5a080 100644 --- a/drivers/lhal/config/bl616/device_table.c +++ b/drivers/lhal/config/bl616/device_table.c @@ -156,6 +156,13 @@ struct bflb_device_s bl616_device_table[] = { .sub_idx = 0, .dev_type = BFLB_DEVICE_TYPE_TRNG, .user_data = NULL }, + { .name = "pka", + .reg_base = SEC_ENG_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_PKA, + .user_data = NULL }, { .name = "emac0", .reg_base = EMAC_BASE, .irq_num = BL616_IRQ_EMAC, diff --git a/drivers/lhal/config/bl702/device_table.c b/drivers/lhal/config/bl702/device_table.c index ba03fc45..4df8a243 100644 --- a/drivers/lhal/config/bl702/device_table.c +++ b/drivers/lhal/config/bl702/device_table.c @@ -155,6 +155,13 @@ struct bflb_device_s bl702_device_table[] = { .sub_idx = 0, .dev_type = BFLB_DEVICE_TYPE_TRNG, .user_data = NULL }, + { .name = "pka", + .reg_base = SEC_ENG_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_PKA, + .user_data = NULL }, { .name = "emac0", .reg_base = EMAC_BASE, .irq_num = BL702_IRQ_EMAC, diff --git a/drivers/lhal/config/bl808/device_table.c b/drivers/lhal/config/bl808/device_table.c index dbe5b2a1..4f57e6e0 100644 --- a/drivers/lhal/config/bl808/device_table.c +++ b/drivers/lhal/config/bl808/device_table.c @@ -156,6 +156,13 @@ struct bflb_device_s bl808_device_table[] = { .sub_idx = 0, .dev_type = BFLB_DEVICE_TYPE_TRNG, .user_data = NULL }, + { .name = "pka", + .reg_base = SEC_ENG_BASE, + .irq_num = 0xff, + .idx = 0, + .sub_idx = 0, + .dev_type = BFLB_DEVICE_TYPE_PKA, + .user_data = NULL }, { .name = "emac0", .reg_base = EMAC_BASE, .irq_num = BL808_IRQ_EMAC, diff --git a/drivers/lhal/include/arch/risc-v/t-head/rv_hpm.h b/drivers/lhal/include/arch/risc-v/t-head/rv_hpm.h index b4466058..78311671 100644 --- a/drivers/lhal/include/arch/risc-v/t-head/rv_hpm.h +++ b/drivers/lhal/include/arch/risc-v/t-head/rv_hpm.h @@ -5,7 +5,7 @@ #if (__riscv_xlen == 32) -#define RV_HPM_SET_CPUNTER(name, val) \ +#define RV_HPM_SET_COUNTER(name, val) \ do { \ uint32_t value = (uint32_t)val; \ __asm volatile("csrw " #name ", %0" \ @@ -46,7 +46,7 @@ #else -#define RV_HPM_SET_CPUNTER(name, val) \ +#define RV_HPM_SET_COUNTER(name, val) \ do { \ uint64_t value = val; \ __asm volatile("csrw " #name ", %0" \ @@ -114,8 +114,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_ICache_Miss_Init_M(void) : : : "memory"); - RV_HPM_SET_CPUNTER(mhpmcounter3, 0); - RV_HPM_SET_CPUNTER(mhpmcounter4, 0); + RV_HPM_SET_COUNTER(mhpmcounter3, 0); + RV_HPM_SET_COUNTER(mhpmcounter4, 0); } /* M-mode: L1 ICache Miss rate measure end */ @@ -142,8 +142,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_BrPredict_Miss_Init_M(void) : : : "memory"); - RV_HPM_SET_CPUNTER(mhpmcounter8, 0); - RV_HPM_SET_CPUNTER(mhpmcounter9, 0); + RV_HPM_SET_COUNTER(mhpmcounter8, 0); + RV_HPM_SET_COUNTER(mhpmcounter9, 0); #endif #ifdef CPU_D0 __asm volatile("csrw mhpmevent9, 6" @@ -154,8 +154,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_BrPredict_Miss_Init_M(void) : : : "memory"); - RV_HPM_SET_CPUNTER(mhpmcounter9, 0); - RV_HPM_SET_CPUNTER(mhpmcounter10, 0); + RV_HPM_SET_COUNTER(mhpmcounter9, 0); + RV_HPM_SET_COUNTER(mhpmcounter10, 0); #endif } @@ -187,8 +187,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_DCache_RdMiss_Init_M(void) : : : "memory"); - RV_HPM_SET_CPUNTER(mhpmcounter14, 0); - RV_HPM_SET_CPUNTER(mhpmcounter15, 0); + RV_HPM_SET_COUNTER(mhpmcounter14, 0); + RV_HPM_SET_COUNTER(mhpmcounter15, 0); #endif #ifdef CPU_D0 __asm volatile("csrw mhpmevent5, 12" @@ -199,8 +199,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_DCache_RdMiss_Init_M(void) : : : "memory"); - RV_HPM_SET_CPUNTER(mhpmcounter5, 0); - RV_HPM_SET_CPUNTER(mhpmcounter6, 0); + RV_HPM_SET_COUNTER(mhpmcounter5, 0); + RV_HPM_SET_COUNTER(mhpmcounter6, 0); #endif } @@ -232,8 +232,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_DCache_WrMiss_Init_M(void) : : : "memory"); - RV_HPM_SET_CPUNTER(mhpmcounter16, 0); - RV_HPM_SET_CPUNTER(mhpmcounter17, 0); + RV_HPM_SET_COUNTER(mhpmcounter16, 0); + RV_HPM_SET_COUNTER(mhpmcounter17, 0); #endif #ifdef CPU_D0 __asm volatile("csrw mhpmevent7, 14" @@ -244,8 +244,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_DCache_WrMiss_Init_M(void) : : : "memory"); - RV_HPM_SET_CPUNTER(mhpmcounter7, 0); - RV_HPM_SET_CPUNTER(mhpmcounter8, 0); + RV_HPM_SET_COUNTER(mhpmcounter7, 0); + RV_HPM_SET_COUNTER(mhpmcounter8, 0); #endif } @@ -280,9 +280,9 @@ inline __attribute__((always_inline)) void RV_HPM_TLB_Miss_Init_M(void) : : : "memory"); - RV_HPM_SET_CPUNTER(mhpmcounter5, 0); - RV_HPM_SET_CPUNTER(mhpmcounter6, 0); - RV_HPM_SET_CPUNTER(mhpmcounter7, 0); + RV_HPM_SET_COUNTER(mhpmcounter5, 0); + RV_HPM_SET_COUNTER(mhpmcounter6, 0); + RV_HPM_SET_COUNTER(mhpmcounter7, 0); } /* M-mode: TLB miss count measure end */ @@ -307,7 +307,7 @@ inline __attribute__((always_inline)) void RV_HPM_Store_Insn_Init_M(void) : : : "memory"); - RV_HPM_SET_CPUNTER(mhpmcounter13, 0); + RV_HPM_SET_COUNTER(mhpmcounter13, 0); } /* M-mode: Store Instruction counter measure end */ @@ -323,7 +323,7 @@ inline __attribute__((always_inline)) void RV_HPM_Store_Insn_Stop_M(uint64_t *sc /* M-Mode: Set cycle counter */ inline __attribute__((always_inline)) void RV_HPM_Cycle_Init_M(void) { - RV_HPM_SET_CPUNTER(mcycle, 0); + RV_HPM_SET_COUNTER(mcycle, 0); } /* M-Mode: Get cycle counter */ @@ -338,7 +338,7 @@ inline __attribute__((always_inline)) void RV_HPM_Cycle_Get_M(uint64_t *cycle) /* M-Mode: Set minstret counter */ inline __attribute__((always_inline)) void RV_HPM_Instret_Init_M(void) { - RV_HPM_SET_CPUNTER(minstret, 0); + RV_HPM_SET_COUNTER(minstret, 0); } /* M-Mode: Get minstret counter */ diff --git a/drivers/lhal/include/bflb_adc.h b/drivers/lhal/include/bflb_adc.h index 5cd5e9f0..0da23490 100644 --- a/drivers/lhal/include/bflb_adc.h +++ b/drivers/lhal/include/bflb_adc.h @@ -158,6 +158,7 @@ void bflb_adc_parse_result(struct bflb_device_s *dev, uint32_t *buffer, struct b void bflb_adc_tsen_init(struct bflb_device_s *dev, uint8_t tsen_mod); float bflb_adc_tsen_get_temp(struct bflb_device_s *dev, uint32_t tsen_offset); void bflb_adc_vbat_enable(struct bflb_device_s *dev); +void bflb_adc_vbat_disable(struct bflb_device_s *dev); #ifdef __cplusplus } diff --git a/drivers/lhal/include/bflb_cks.h b/drivers/lhal/include/bflb_cks.h new file mode 100644 index 00000000..77210827 --- /dev/null +++ b/drivers/lhal/include/bflb_cks.h @@ -0,0 +1,27 @@ +#ifndef _BFLB_CKS_H +#define _BFLB_CKS_H + +#include "bflb_core.h" + +/** @defgroup CKS_ENDIAN cks endian definition + * @{ + */ +#define CKS_LITTLE_ENDIAN 0 +#define CKS_BIG_ENDIAN 1 +/** + * @} + */ + +#ifdef __cplusplus +extern "C" { +#endif + +void bflb_cks_reset(struct bflb_device_s *dev); +void bflb_cks_set_endian(struct bflb_device_s *dev, uint8_t endian); +uint16_t bflb_cks_compute(struct bflb_device_s *dev, uint8_t *data, uint32_t length); + +#ifdef __cplusplus +} +#endif + +#endif diff --git a/drivers/lhal/include/bflb_clock.h b/drivers/lhal/include/bflb_clock.h index 55bdef12..a480e098 100644 --- a/drivers/lhal/include/bflb_clock.h +++ b/drivers/lhal/include/bflb_clock.h @@ -8,9 +8,8 @@ #define BFLB_SYSTEM_PBCLK 2 #define BFLB_SYSTEM_XCLK 3 #define BFLB_SYSTEM_32K_CLK 4 -#define BFLB_SYSTEM_1K_CLK 5 -#if defined(BL702) || defined(BL602) +#if defined(BL702) || defined(BL602) || defined(BL702L) #define BFLB_GLB_CGEN1_BASE (0x40000000 + 0x24) #elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) #define BFLB_GLB_CGEN1_BASE (0x20000000 + 0x584) diff --git a/drivers/lhal/include/bflb_common.h b/drivers/lhal/include/bflb_common.h index 5cd19b89..8e0ca16d 100644 --- a/drivers/lhal/include/bflb_common.h +++ b/drivers/lhal/include/bflb_common.h @@ -1,7 +1,7 @@ #ifndef _BFLB_COMMON_H #define _BFLB_COMMON_H -#include "bflb_core.h" +#include "stdint.h" #ifdef __cplusplus extern "C" { diff --git a/drivers/lhal/include/bflb_core.h b/drivers/lhal/include/bflb_core.h index 3a5f73ef..3a081f97 100644 --- a/drivers/lhal/include/bflb_core.h +++ b/drivers/lhal/include/bflb_core.h @@ -12,8 +12,11 @@ #include #include #include "bflb_list.h" +#include "bflb_mtimer.h" +#include "bflb_common.h" -#if !defined(BL602) && !defined(BL702) && !defined(BL616) && !defined(BL606P) && !defined(BL808) && !defined(BL628) +#if !defined(BL602) && !defined(BL702) && !defined(BL702L) && \ + !defined(BL616) && !defined(BL606P) && !defined(BL808) && !defined(BL628) #error please define a supported chip #endif @@ -56,6 +59,8 @@ void assert_func(uint8_t *file, uint32_t line, uint8_t *function, uint8_t *strin #define BFLB_DEVICE_TYPE_SHA 29 #define BFLB_DEVICE_TYPE_MD5 30 #define BFLB_DEVICE_TYPE_TRNG 31 +#define BFLB_DEVICE_TYPE_PKA 32 +#define BFLB_DEVICE_TYPE_CKS 33 struct bflb_device_s { const char *name; diff --git a/drivers/lhal/include/bflb_dma.h b/drivers/lhal/include/bflb_dma.h index b4ab0987..19c038bd 100644 --- a/drivers/lhal/include/bflb_dma.h +++ b/drivers/lhal/include/bflb_dma.h @@ -194,6 +194,54 @@ * @} */ +#elif defined(BL628) +/** @defgroup DMA_PERIPHERAL_REGBASE dma peripheral data register address definition + * @{ + */ +#define DMA_ADDR_UART0_TDR (0x20010000 + 0x88) +#define DMA_ADDR_UART0_RDR (0x20010000 + 0x8C) +#define DMA_ADDR_UART1_TDR (0x20011000 + 0x88) +#define DMA_ADDR_UART1_RDR (0x20011000 + 0x8C) +#define DMA_ADDR_UART2_TDR (0x20012000 + 0x88) +#define DMA_ADDR_UART2_RDR (0x20012000 + 0x8C) +#define DMA_ADDR_I2C0_TDR (0x20014000 + 0x88) +#define DMA_ADDR_I2C0_RDR (0x20014000 + 0x8C) +#define DMA_ADDR_I2C1_TDR (0x20015000 + 0x88) +#define DMA_ADDR_I2C1_RDR (0x20015000 + 0x8C) +#define DMA_ADDR_SPI0_TDR (0x20018000 + 0x88) +#define DMA_ADDR_SPI0_RDR (0x20018000 + 0x8C) +#define DMA_ADDR_I2S_TDR (0x2001E000 + 0x88) +#define DMA_ADDR_I2S_RDR (0x2001E000 + 0x8C) +#define DMA_ADDR_ADC_RDR (0x20002000 + 0x04) +#define DMA_ADDR_DAC_TDR (0x20002000 + 0x48) +/** + * @} + */ + +/** @defgroup DMA_PERIPHERAL_REQUEST dma peripheral request definition + * @{ + */ +#define DMA_REQUEST_NONE 0x00000000 +#define DMA_REQUEST_UART0_RX 0x00000000 +#define DMA_REQUEST_UART0_TX 0x00000001 +#define DMA_REQUEST_UART1_RX 0x00000002 +#define DMA_REQUEST_UART1_TX 0x00000003 +#define DMA_REQUEST_UART2_RX 0x00000004 +#define DMA_REQUEST_UART2_TX 0x00000005 +#define DMA_REQUEST_I2C0_RX 0x00000006 +#define DMA_REQUEST_I2C0_TX 0x00000007 +#define DMA_REQUEST_I2C1_RX 0x00000008 +#define DMA_REQUEST_I2C1_TX 0x00000009 +#define DMA_REQUEST_SPI0_RX 0x0000000A +#define DMA_REQUEST_SPI0_TX 0x0000000B +#define DMA_REQUEST_I2S_RX 0x00000010 +#define DMA_REQUEST_I2S_TX 0x00000011 +#define DMA_REQUEST_ADC 0x00000016 +#define DMA_REQUEST_DAC 0x00000017 +/** + * @} + */ + #endif /** @defgroup DMA_CMD dma feature control cmd definition @@ -294,7 +342,7 @@ int bflb_dma_channel_lli_reload(struct bflb_device_s *dev, struct bflb_dma_channel_lli_pool_s *lli_pool, uint32_t max_lli_count, struct bflb_dma_channel_lli_transfer_s *transfer, uint32_t count); -void bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); +int bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); /* Not use */ void bflb_dma_channel_tcint_mask(struct bflb_device_s *dev, bool mask); diff --git a/drivers/lhal/include/bflb_gpio.h b/drivers/lhal/include/bflb_gpio.h index 31c9dfae..8f853c43 100644 --- a/drivers/lhal/include/bflb_gpio.h +++ b/drivers/lhal/include/bflb_gpio.h @@ -83,18 +83,24 @@ #define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_EMAC (19 << GPIO_FUNC_SHIFT) +#elif defined(BL702L) +#define GPIO_FUNC_SPI0 (4 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_I2C0 (6 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_PWM0 (8 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_KEYSCAN (13 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT) #elif defined(BL616) -#define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_SPI0 (1 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_I2S (3 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_PDM (4 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_I2C0 (5 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_I2C1 (6 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_EMAC (8 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_SDU (12 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_JTAG (26 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_SPI0 (1 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_I2S (3 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_PDM (4 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_I2C0 (5 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_I2C1 (6 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_EMAC (8 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_SDU (12 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_JTAG (26 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT) #elif defined(BL606P) || defined(BL808) #define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT) @@ -118,19 +124,20 @@ #define GPIO_FUNC_JTAG_M0 (26 << GPIO_FUNC_SHIFT) #define GPIO_FUNC_JTAG_D0 (27 << GPIO_FUNC_SHIFT) #elif defined(BL628) -#define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_SPI0 (1 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_I2S (3 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_PDM (4 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_I2C0 (5 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_I2C1 (6 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_UART (7 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_EMAC (8 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_SDU (12 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_DBI_B (22 << GPIO_FUNC_SHIFT) -#define GPIO_FUNC_DBI_C (23 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_SDH (0 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_SPI0 (1 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_I2S (3 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_PDM (4 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_I2C0 (5 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_I2C1 (6 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_UART (7 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_EMAC (8 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_CAM (9 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_SDU (12 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_PWM0 (16 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_DBI_B (22 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_DBI_C (23 << GPIO_FUNC_SHIFT) +#define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT) #endif #define GPIO_MODE_SHIFT (5) /* Bits 5-6: Port Mode */ @@ -190,6 +197,14 @@ #define GPIO_UART_FUNC_UART2_RX 11 #endif +/** @defgroup GPIO_CMD gpio feature control cmd definition + * @{ + */ +#define GPIO_CMD_GET_GPIO_FUN (0x01) +/** + * @} + */ + #ifdef __cplusplus extern "C" { #endif @@ -206,7 +221,7 @@ void bflb_gpio_int_clear(struct bflb_device_s *dev, uint8_t pin); void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_func); -void bflb_gpio_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); +int bflb_gpio_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); #ifdef __cplusplus } diff --git a/drivers/lhal/include/bflb_i2c.h b/drivers/lhal/include/bflb_i2c.h index cc4bfc6b..434f8ab9 100644 --- a/drivers/lhal/include/bflb_i2c.h +++ b/drivers/lhal/include/bflb_i2c.h @@ -36,16 +36,51 @@ #define I2C_M_READ 0x0001 /* Read data, from slave to master */ #define I2C_M_TEN 0x0002 /* Ten bit address */ +#define I2C_M_DMA 0x0004 /* Enable dma mode */ #define I2C_M_NOSTOP 0x0040 /* Message should not end with a STOP */ #define I2C_M_NOSTART 0x0080 /* Message should not begin with a START */ -/* I2c bus speed */ +/* I2C bus speed */ #define I2C_SPEED_STANDARD 100000 /* Standard speed (100Khz) */ #define I2C_SPEED_FAST 400000 /* Fast speed (400Khz) */ #define I2C_SPEED_FAST_PLUS 1000000 /* Fast+ speed ( 1Mhz) */ #define I2C_SPEED_HIGH 3400000 /* High speed (3.4Mhz) */ +/** @defgroup I2C_INTSTS i2c interrupt status definition + * @{ + */ +#define I2C_INTSTS_END (1 << 0) /* Transfer end interrupt */ +#define I2C_INTSTS_TX_FIFO (1 << 1) /* TX FIFO ready interrupt */ +#define I2C_INTSTS_RX_FIFO (1 << 2) /* RX FIFO ready interrupt */ +#define I2C_INTSTS_NACK (1 << 3) /* NACK interrupt */ +#define I2C_INTSTS_ARB (1 << 4) /* Arbitration lost interrupt */ +#define I2C_INTSTS_FER (1 << 5) /* TX/RX FIFO error interrupt */ +/** + * @} + */ + +/** @defgroup I2C_INTCLR i2c interrupt clear definition + * @{ + */ +#define I2C_INTCLR_END (1 << 0) /* Transfer end interrupt */ +#define I2C_INTCLR_TX_FIFO (1 << 1) /* TX FIFO ready interrupt */ +#define I2C_INTCLR_RX_FIFO (1 << 2) /* RX FIFO ready interrupt */ +#define I2C_INTCLR_NACK (1 << 3) /* NACK interrupt */ +#define I2C_INTCLR_ARB (1 << 4) /* Arbitration lost interrupt */ +#define I2C_INTCLR_FER (1 << 5) /* TX/RX FIFO error interrupt */ +/** + * @} + */ + +/* I2C interrupt type */ +#define I2C_INT_END (1 << 0) /* Transfer end interrupt */ +#define I2C_INT_TX_FIFO (1 << 1) /* TX FIFO ready interrupt */ +#define I2C_INT_RX_FIFO (1 << 2) /* RX FIFO ready interrupt */ +#define I2C_INT_NACK (1 << 3) /* NACK interrupt */ +#define I2C_INT_ARB (1 << 4) /* Arbitration lost interrupt */ +#define I2C_INT_FER (1 << 5) /* TX/RX FIFO error interrupt */ + /** * @brief I2C message structure * @@ -70,11 +105,14 @@ void bflb_i2c_deinit(struct bflb_device_s *dev); void bflb_i2c_link_txdma(struct bflb_device_s *dev, bool enable); void bflb_i2c_link_rxdma(struct bflb_device_s *dev, bool enable); int bflb_i2c_transfer(struct bflb_device_s *dev, struct bflb_i2c_msg_s *msgs, int count); +void bflb_i2c_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask); +void bflb_i2c_int_clear(struct bflb_device_s *dev, uint32_t int_clear); +uint32_t bflb_i2c_get_intstatus(struct bflb_device_s *dev); -void bflb_i2c_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); +int bflb_i2c_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); #ifdef __cplusplus } #endif -#endif \ No newline at end of file +#endif diff --git a/drivers/lhal/include/bflb_l1c.h b/drivers/lhal/include/bflb_l1c.h index 404b92d0..bb0b48cc 100644 --- a/drivers/lhal/include/bflb_l1c.h +++ b/drivers/lhal/include/bflb_l1c.h @@ -3,10 +3,11 @@ #include "bflb_core.h" -#if defined(BL616) || defined(BL606P) || defined(BL808) +#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) #include "csi_core.h" #define bflb_l1c_icache_enable() csi_icache_enable() #define bflb_l1c_icache_disable() csi_icache_disable() +#define bflb_l1c_icache_invalid_all() csi_icache_invalid() #define bflb_l1c_dcache_enable() csi_dcache_enable() #define bflb_l1c_dcache_disable() csi_dcache_disable() #define bflb_l1c_dcache_clean_all() csi_dcache_clean() @@ -18,6 +19,7 @@ #else #define bflb_l1c_icache_enable() #define bflb_l1c_icache_disable() +#define bflb_l1c_icache_invalid_all() #define bflb_l1c_dcache_enable() #define bflb_l1c_dcache_disable() #define bflb_l1c_dcache_clean_all() diff --git a/drivers/lhal/include/bflb_mtimer.h b/drivers/lhal/include/bflb_mtimer.h index acb565af..2654374b 100644 --- a/drivers/lhal/include/bflb_mtimer.h +++ b/drivers/lhal/include/bflb_mtimer.h @@ -1,14 +1,15 @@ #ifndef _BFLB_MTIMER_H #define _BFLB_MTIMER_H -#include "bflb_core.h" -#include "bflb_irq.h" +#include "stdint.h" +#include "stdio.h" #ifdef __cplusplus extern "C" { #endif void bflb_mtimer_config(uint64_t ticks, void (*interruptfun)(void)); +uint32_t bflb_mtimer_get_freq(void); void bflb_mtimer_delay_ms(uint32_t time); void bflb_mtimer_delay_us(uint32_t time); uint64_t bflb_mtimer_get_time_us(); diff --git a/drivers/lhal/include/bflb_pwm_v1.h b/drivers/lhal/include/bflb_pwm_v1.h index 96577281..02f32188 100644 --- a/drivers/lhal/include/bflb_pwm_v1.h +++ b/drivers/lhal/include/bflb_pwm_v1.h @@ -90,7 +90,7 @@ void bflb_pwm_v1_int_enable(struct bflb_device_s *dev, uint8_t ch, bool enable); uint32_t bflb_pwm_v1_get_intstatus(struct bflb_device_s *dev); void bflb_pwm_v1_int_clear(struct bflb_device_s *dev, uint32_t int_clear); -void bflb_pwm_v1_feature_control(struct bflb_device_s *dev, uint8_t ch, int cmd, size_t arg); +int bflb_pwm_v1_feature_control(struct bflb_device_s *dev, uint8_t ch, int cmd, size_t arg); #ifdef __cplusplus } diff --git a/drivers/lhal/include/bflb_pwm_v2.h b/drivers/lhal/include/bflb_pwm_v2.h index 31b32d3f..0dbdba15 100644 --- a/drivers/lhal/include/bflb_pwm_v2.h +++ b/drivers/lhal/include/bflb_pwm_v2.h @@ -174,7 +174,7 @@ void bflb_pwm_v2_int_enable(struct bflb_device_s *dev, uint32_t int_en, bool ena uint32_t bflb_pwm_v2_get_intstatus(struct bflb_device_s *dev); void bflb_pwm_v2_int_clear(struct bflb_device_s *dev, uint32_t int_clear); -void bflb_pwm_v2_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); +int bflb_pwm_v2_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); #ifdef __cplusplus } diff --git a/drivers/lhal/include/bflb_sec_aes.h b/drivers/lhal/include/bflb_sec_aes.h index 368d9a2d..5d018116 100644 --- a/drivers/lhal/include/bflb_sec_aes.h +++ b/drivers/lhal/include/bflb_sec_aes.h @@ -8,12 +8,88 @@ #define AES_MODE_CBC 2 #define AES_MODE_XTS 3 +#define AES_LINK_KEY_128BITS 0 +#define AES_LINK_KEY_192BITS 1 +#define AES_LINK_KEY_256BITS 2 +#define AES_LINK_KEY_DOUBLE_128BITS 3 + +struct bflb_aes_link_s { + uint32_t : 3; /*!< [2:0]Reserved */ + uint32_t aes_key : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */ + uint32_t aes_dec_en : 1; /*!< [5]Encode or decode */ + uint32_t aes_newkey_dis : 1; /*!< [6]Use new key or use same key as last one */ + uint32_t aes_hwkey_en : 1; /*!< [7]Enable or disable using hardware hey */ + uint32_t : 1; /*!< [8]Reserved */ + uint32_t aes_intclr : 1; /*!< [9]Clear interrupt */ + uint32_t aes_intset : 1; /*!< [10]Set interrupt */ + uint32_t : 1; /*!< [11]Reserved */ + uint32_t aes_mode : 2; /*!< [13:12]ECB/CTR/CBC mode select */ + uint32_t aes_newiv_dis : 1; /*!< [14]Use new iv or use same iv as last one */ + uint32_t aes_xts : 1; /*!< [15]XTS mode select */ + uint32_t aes_msglen : 16; /*!< [31:16]Number of 128-bit block */ + uint32_t aes_srcaddr; /*!< Message source address */ + uint32_t aes_dstaddr; /*!< Message destination address */ + uint32_t aes_iv0; /*!< Big endian initial vector(MSB) */ + uint32_t aes_iv1; /*!< Big endian initial vector */ + uint32_t aes_iv2; /*!< Big endian initial vector */ + uint32_t aes_iv3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */ + uint32_t aes_key0; /*!< Big endian aes key(aes-128/256 key MSB) */ + uint32_t aes_key1; /*!< Big endian aes key */ + uint32_t aes_key2; /*!< Big endian aes key */ + uint32_t aes_key3; /*!< Big endian aes key(aes-128 key LSB) */ + uint32_t aes_key4; /*!< Big endian aes key */ + uint32_t aes_key5; /*!< Big endian aes key */ + uint32_t aes_key6; /*!< Big endian aes key */ + uint32_t aes_key7; /*!< Big endian aes key(aes-256 key LSB) */ +} __attribute__((aligned(4))); + +struct bflb_aes_xts_link_s { + uint32_t : 3; /*!< [2:0]Reserved */ + uint32_t aes_key : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */ + uint32_t aes_dec_en : 1; /*!< [5]Encode or decode */ + uint32_t aes_newkey_dis : 1; /*!< [6]Use new key or use same key as last one */ + uint32_t aes_hwkey_en : 1; /*!< [7]Enable or disable using hardware hey */ + uint32_t : 1; /*!< [8]Reserved */ + uint32_t aes_intclr : 1; /*!< [9]Clear interrupt */ + uint32_t aes_intset : 1; /*!< [10]Set interrupt */ + uint32_t : 1; /*!< [11]Reserved */ + uint32_t aes_mode : 2; /*!< [13:12]ECB/CTR/CBC mode select */ + uint32_t aes_newiv_dis : 1; /*!< [14]Use new iv or use same iv as last one */ + uint32_t aes_xts : 1; /*!< [15]XTS mode select */ + uint32_t aes_msglen : 16; /*!< [31:16]Number of 128-bit block */ + uint32_t aes_srcaddr; /*!< Message source address */ + uint32_t aes_dstaddr; /*!< Message destination address */ + uint32_t aes_iv0; /*!< Big endian initial vector(MSB) */ + uint32_t aes_iv1; /*!< Big endian initial vector */ + uint32_t aes_iv2; /*!< Big endian initial vector */ + uint32_t aes_iv3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */ + uint32_t aes_key10; /*!< Big endian aes key(aes-128/256 key MSB) */ + uint32_t aes_key11; /*!< Big endian aes key1 */ + uint32_t aes_key12; /*!< Big endian aes key1 */ + uint32_t aes_key13; /*!< Big endian aes key1(aes-128 key LSB) */ + uint32_t aes_key14; /*!< Big endian aes key1 */ + uint32_t aes_key15; /*!< Big endian aes key1 */ + uint32_t aes_key16; /*!< Big endian aes key1 */ + uint32_t aes_key17; /*!< Big endian aes key1(aes-256 key LSB) */ + uint32_t : 16; /*!< [15:0]Reserved */ + uint32_t aes_unitlen : 16; /*!< [31:16]Big endian aes unit len */ + uint32_t aes_key20; /*!< Big endian aes key2(aes-128/256 key MSB) */ + uint32_t aes_key21; /*!< Big endian aes key2 */ + uint32_t aes_key22; /*!< Big endian aes key2 */ + uint32_t aes_key23; /*!< Big endian aes key2(aes-128 key LSB) */ + uint32_t aes_key24; /*!< Big endian aes key2 */ + uint32_t aes_key25; /*!< Big endian aes key2 */ + uint32_t aes_key26; /*!< Big endian aes key2 */ + uint32_t aes_key27; /*!< Big endian aes key2(aes-256 key LSB) */ +} __attribute__((aligned(4))); + #ifdef __cplusplus extern "C" { #endif void bflb_aes_init(struct bflb_device_s *dev); void bflb_aes_deinit(struct bflb_device_s *dev); +void bflb_aes_set_hwkey(uint8_t keysel); void bflb_aes_set_mode(struct bflb_device_s *dev, uint8_t mode); void bflb_aes_setkey(struct bflb_device_s *dev, const uint8_t *key, uint16_t keybits); int bflb_aes_encrypt(struct bflb_device_s *dev, @@ -27,6 +103,18 @@ int bflb_aes_decrypt(struct bflb_device_s *dev, uint8_t *output, uint32_t len); +void bflb_aes_link_init(struct bflb_device_s *dev); +void bflb_aes_link_deinit(struct bflb_device_s *dev); +int bflb_aes_link_update(struct bflb_device_s *dev, + uint32_t link_addr, + const uint8_t *input, + uint8_t *output, + uint32_t len); + +void bflb_group0_request_aes_access(struct bflb_device_s *dev); +void bflb_group0_release_aes_access(struct bflb_device_s *dev); +void bflb_aes_set_hwkey_source(struct bflb_device_s *dev, uint8_t source); + #ifdef __cplusplus } #endif diff --git a/drivers/lhal/include/bflb_sec_ecdsa.h b/drivers/lhal/include/bflb_sec_ecdsa.h new file mode 100644 index 00000000..5cfcb5e0 --- /dev/null +++ b/drivers/lhal/include/bflb_sec_ecdsa.h @@ -0,0 +1,43 @@ +#ifndef _BFLB_SEC_ECDSA_H +#define _BFLB_SEC_ECDSA_H + +#include "bflb_core.h" + +#define ECP_SECP256R1 0 +#define ECP_SECP256K1 1 + +struct bflb_ecdsa_s { + uint8_t ecpId; + uint32_t *privateKey; + uint32_t *publicKeyx; + uint32_t *publicKeyy; +}; + +struct bflb_ecdh_s { + uint8_t ecpId; +}; + +#ifdef __cplusplus +extern "C" { +#endif + +int bflb_sec_ecdsa_init(struct bflb_ecdsa_s *handle, uint8_t id); +int bflb_sec_ecdsa_deinit(struct bflb_ecdsa_s *handle); +int bflb_sec_ecdsa_sign(struct bflb_ecdsa_s *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s); +int bflb_sec_ecdsa_verify(struct bflb_ecdsa_s *handle, const uint32_t *hash, uint32_t hashLen, const uint32_t *r, const uint32_t *s); +int bflb_sec_ecdsa_get_private_key(struct bflb_ecdsa_s *handle, uint32_t *private_key); +int bflb_sec_ecdsa_get_public_key(struct bflb_ecdsa_s *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); + +int bflb_sec_ecdh_init(struct bflb_ecdh_s *handle, uint8_t id); +int bflb_sec_ecdh_deinit(struct bflb_ecdh_s *handle); +int bflb_sec_ecdh_get_encrypt_key(struct bflb_ecdh_s *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); +int bflb_sec_ecdh_get_public_key(struct bflb_ecdh_s *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); +int bflb_sec_ecc_get_random_value(uint32_t *data, uint32_t *max_ref, uint32_t size); + +#define SEC_CODEPATH_STATE_SIGN 0x48672386 + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/drivers/lhal/include/bflb_sec_pka.h b/drivers/lhal/include/bflb_sec_pka.h new file mode 100644 index 00000000..2a3e7364 --- /dev/null +++ b/drivers/lhal/include/bflb_sec_pka.h @@ -0,0 +1,269 @@ +#ifndef _BFLB_SEC_PKA_H +#define _BFLB_SEC_PKA_H + +#include "bflb_core.h" + +#define SEC_ENG_PKA_REG_SIZE_8 1 +#define SEC_ENG_PKA_REG_SIZE_16 2 +#define SEC_ENG_PKA_REG_SIZE_32 3 +#define SEC_ENG_PKA_REG_SIZE_64 4 +#define SEC_ENG_PKA_REG_SIZE_96 5 +#define SEC_ENG_PKA_REG_SIZE_128 6 +#define SEC_ENG_PKA_REG_SIZE_192 7 +#define SEC_ENG_PKA_REG_SIZE_256 8 +#define SEC_ENG_PKA_REG_SIZE_384 9 +#define SEC_ENG_PKA_REG_SIZE_512 10 + +#define SEC_ENG_PKA_OP_PPSEL 0x00 +#define SEC_ENG_PKA_OP_LMOD2N 0x11 +#define SEC_ENG_PKA_OP_LDIV2N 0x12 +#define SEC_ENG_PKA_OP_LMUL2N 0x13 +#define SEC_ENG_PKA_OP_LDIV 0x14 +#define SEC_ENG_PKA_OP_LSQR 0x15 +#define SEC_ENG_PKA_OP_LMUL 0x16 +#define SEC_ENG_PKA_OP_LSUB 0x17 +#define SEC_ENG_PKA_OP_LADD 0x18 +#define SEC_ENG_PKA_OP_LCMP 0x19 +#define SEC_ENG_PKA_OP_MDIV2 0x21 +#define SEC_ENG_PKA_OP_MINV 0x22 +#define SEC_ENG_PKA_OP_MEXP 0x23 +#define SEC_ENG_PKA_OP_MSQR 0x24 +#define SEC_ENG_PKA_OP_MMUL 0x25 +#define SEC_ENG_PKA_OP_MREM 0x26 +#define SEC_ENG_PKA_OP_MSUB 0x27 +#define SEC_ENG_PKA_OP_MADD 0x28 +#define SEC_ENG_PKA_OP_RESIZE 0x31 +#define SEC_ENG_PKA_OP_MOVDAT 0x32 +#define SEC_ENG_PKA_OP_NLIR 0x33 +#define SEC_ENG_PKA_OP_SLIR 0x34 +#define SEC_ENG_PKA_OP_CLIR 0x35 +#define SEC_ENG_PKA_OP_CFLIRI_BUFFER 0x36 +#define SEC_ENG_PKA_OP_CTLIRI_PLD 0x37 +#define SEC_ENG_PKA_OP_CFLIR_BUFFER 0x38 +#define SEC_ENG_PKA_OP_CTLIR_PLD 0x39 + +#ifdef __cplusplus +extern "C" { +#endif + +void bflb_pka_init(struct bflb_device_s *dev); +void bflb_pka_deinit(struct bflb_device_s *dev); + +void bflb_pka_lmod2n(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint16_t bit_shift, + uint8_t lastop); + +void bflb_pka_ldiv2n(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint16_t bit_shift, + uint8_t lastop); + +void bflb_pka_lmul2n(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint16_t bit_shift, + uint8_t lastop); + +void bflb_pka_ldiv(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t s2_regindex, + uint8_t s2_regsize, + uint8_t lastop); + +void bflb_pka_lsqr(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t lastop); + +void bflb_pka_lmul(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t s1_regindex, + uint8_t s1_regsize, + uint8_t lastop); + +void bflb_pka_lsub(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t s1_regindex, + uint8_t s1_regsize, + uint8_t lastop); + +void bflb_pka_ladd(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t s1_regindex, + uint8_t s1_regsize, + uint8_t lastop); + +uint8_t bflb_pka_lcmp(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t s1_regindex, + uint8_t s1_regsize); + +void bflb_pka_minv(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t s2_regindex, + uint8_t s2_regsize, + uint8_t lastop); + +void bflb_pka_mexp(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t s1_regindex, + uint8_t s1_regsize, + uint8_t s2_regindex, + uint8_t s2_regsize, + uint8_t lastop); + +void bflb_pka_msqr(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t s2_regindex, + uint8_t s2_regsize, + uint8_t lastop); + +void bflb_pka_mmul(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t s1_regindex, + uint8_t s1_regsize, + uint8_t s2_regindex, + uint8_t s2_regsize, + uint8_t lastop); + +void bflb_pka_mrem(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t s2_regindex, + uint8_t s2_regsize, + uint8_t lastop); + +void bflb_pka_msub(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t s1_regindex, + uint8_t s1_regsize, + uint8_t s2_regindex, + uint8_t s2_regsize, + uint8_t lastop); + +void bflb_pka_madd(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t s1_regindex, + uint8_t s1_regsize, + uint8_t s2_regindex, + uint8_t s2_regsize, + uint8_t lastop); + +void bflb_pka_regsize(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t lastop); + +void bflb_pka_movdat(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t lastop); + +void bflb_pka_nlir(struct bflb_device_s *dev, + uint8_t s0_regindex, + uint8_t s0_regsize, + uint8_t d0_regindex, + uint8_t d0_regsize, + uint8_t lastop); + +void bflb_pka_slir(struct bflb_device_s *dev, + uint8_t regindex, + uint8_t regsize, + uint32_t data, + uint8_t lastop); + +void bflb_pka_clir(struct bflb_device_s *dev, + uint8_t regindex, + uint8_t regsize, + uint16_t size, + uint8_t lastop); + +void bflb_pka_write(struct bflb_device_s *dev, + uint8_t regindex, + uint8_t regsize, + const uint32_t *data, + uint16_t size, + uint8_t lastop); + +void bflb_pka_read(struct bflb_device_s *dev, + uint8_t regindex, + uint8_t regsize, + uint32_t *data, + uint16_t size); + +void bflb_pka_gf2mont(struct bflb_device_s *dev, + uint8_t s_regindex, + uint8_t s_regsize, + uint8_t d_regindex, + uint8_t d_regsize, + uint8_t t_regindex, + uint8_t t_regsize, + uint8_t p_regindex, + uint8_t p_regsize, + uint32_t size); + +void bflb_pka_mont2gf(struct bflb_device_s *dev, + uint8_t s_regindex, + uint8_t s_regsize, + uint8_t d_regindex, + uint8_t d_regsize, + uint8_t invt_regindex, + uint8_t invt_regsize, + uint8_t t_regindex, + uint8_t t_regsize, + uint8_t p_regindex, + uint8_t p_regsize); + +#ifdef __cplusplus +} +#endif + +#endif \ No newline at end of file diff --git a/drivers/lhal/include/bflb_sec_sha.h b/drivers/lhal/include/bflb_sec_sha.h index 7d179665..a1a96540 100644 --- a/drivers/lhal/include/bflb_sec_sha.h +++ b/drivers/lhal/include/bflb_sec_sha.h @@ -3,11 +3,13 @@ #include "bflb_core.h" -#define SHA_MODE_SHA1 0 -#define SHA_MODE_SHA224 1 -#define SHA_MODE_SHA256 2 -#define SHA_MODE_SHA384 3 -#define SHA_MODE_SHA512 4 +#define SHA_MODE_SHA256 0 +#define SHA_MODE_SHA224 1 +#define SHA_MODE_SHA1 2 +#define SHA_MODE_SHA512 4 +#define SHA_MODE_SHA384 5 +#define SHA_MODE_SHA512T224 6 +#define SHA_MODE_SHA512T256 7 struct bflb_sha1_ctx_s { uint32_t total[2]; /*!< Number of bytes processed */ @@ -30,6 +32,22 @@ struct bflb_sha512_ctx_s { uint8_t sha_feed; /*!< Sha has feed data */ }; +struct bflb_sha_link_s { + uint32_t : 2; /*!< [1:0]Reserved */ + uint32_t sha_mode : 3; /*!< [4:2]Sha-256/sha-224/sha-1/sha-1/sha-512/sha-384/sha-512T224/sha-512T256 */ + uint32_t : 1; /*!< [5]Reserved */ + uint32_t sha_newhash_dis : 1; /*!< [6]New hash or accumulate last hash */ + uint32_t : 2; /*!< [8:7]Reserved */ + uint32_t sha_intclr : 1; /*!< [9]Clear interrupt */ + uint32_t sha_intset : 1; /*!< [10]Set interrupt */ + uint32_t : 1; /*!< [11]Reserved */ + uint32_t sha_mode_ext : 2; /*!< [13:12]Extention,0:sha 1:md5 2:crc16 3:crc32 */ + uint32_t : 2; /*!< [15:14]Reserved */ + uint32_t sha_msglen : 16; /*!< [31:16]Number of 512-bit block */ + uint32_t sha_srcaddr; /*!< Message source address */ + uint32_t result[16]; /*!< Result of SHA */ +}; + #ifdef __cplusplus extern "C" { #endif @@ -45,6 +63,42 @@ void bflb_sha1_finish(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, ui void bflb_sha256_finish(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, uint8_t *output); void bflb_sha512_finish(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, uint8_t *output); +void bflb_sha_link_init(struct bflb_device_s *dev); +void bflb_sha_link_deinit(struct bflb_device_s *dev); +void bflb_sha1_link_start(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx); +void bflb_sha256_link_start(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx); +void bflb_sha512_link_start(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx); +int bflb_sha1_link_update(struct bflb_device_s *dev, + struct bflb_sha1_ctx_s *ctx, + uint32_t link_addr, + const uint8_t *input, + uint32_t len); +int bflb_sha256_link_update(struct bflb_device_s *dev, + struct bflb_sha256_ctx_s *ctx, + uint32_t link_addr, + const uint8_t *input, + uint32_t len); +int bflb_sha512_link_update(struct bflb_device_s *dev, + struct bflb_sha512_ctx_s *ctx, + uint32_t link_addr, + const uint8_t *input, + uint32_t len); +void bflb_sha1_link_finish(struct bflb_device_s *dev, + struct bflb_sha1_ctx_s *ctx, + uint32_t link_addr, + uint8_t *output); +void bflb_sha256_link_finish(struct bflb_device_s *dev, + struct bflb_sha256_ctx_s *ctx, + uint32_t link_addr, + uint8_t *output); +void bflb_sha512_link_finish(struct bflb_device_s *dev, + struct bflb_sha512_ctx_s *ctx, + uint32_t link_addr, + uint8_t *output); + +void bflb_group0_request_sha_access(struct bflb_device_s *dev); +void bflb_group0_release_sha_access(struct bflb_device_s *dev); + #ifdef __cplusplus } #endif diff --git a/drivers/lhal/include/bflb_sec_trng.h b/drivers/lhal/include/bflb_sec_trng.h index 165f6116..badca279 100644 --- a/drivers/lhal/include/bflb_sec_trng.h +++ b/drivers/lhal/include/bflb_sec_trng.h @@ -7,7 +7,12 @@ extern "C" { #endif -void bflb_trng_read(struct bflb_device_s *dev, uint8_t data[32]); +int bflb_trng_read(struct bflb_device_s *dev, uint8_t data[32]); +int bflb_trng_readlen(uint8_t *data, uint32_t len); +long random(void); + +void bflb_group0_request_trng_access(struct bflb_device_s *dev); +void bflb_group0_release_trng_access(struct bflb_device_s *dev); #ifdef __cplusplus } diff --git a/drivers/lhal/include/bflb_spi.h b/drivers/lhal/include/bflb_spi.h index cc557df1..c3cbad04 100644 --- a/drivers/lhal/include/bflb_spi.h +++ b/drivers/lhal/include/bflb_spi.h @@ -70,7 +70,7 @@ * @} */ -/** @defgroup SPI_CMD uart feature control cmd definition +/** @defgroup SPI_CMD spi feature control cmd definition * @{ */ #define SPI_CMD_SET_DATA_WIDTH (0x01) @@ -78,7 +78,6 @@ #define SPI_CMD_CLEAR_TX_FIFO (0x03) #define SPI_CMD_CLEAR_RX_FIFO (0x04) #define SPI_CMD_SET_CS_INTERVAL (0x05) - /** * @} */ @@ -116,7 +115,7 @@ void bflb_spi_link_txdma(struct bflb_device_s *dev, bool enable); void bflb_spi_link_rxdma(struct bflb_device_s *dev, bool enable); uint32_t bflb_spi_poll_send(struct bflb_device_s *dev, uint32_t data); int bflb_spi_poll_exchange(struct bflb_device_s *dev, const void *txbuffer, void *rxbuffer, size_t nbytes); -int bflb_spi_isbusy(struct bflb_device_s *dev); +bool bflb_spi_isbusy(struct bflb_device_s *dev); void bflb_spi_txint_mask(struct bflb_device_s *dev, bool mask); void bflb_spi_rxint_mask(struct bflb_device_s *dev, bool mask); void bflb_spi_errint_mask(struct bflb_device_s *dev, bool mask); diff --git a/drivers/lhal/include/bflb_timer.h b/drivers/lhal/include/bflb_timer.h index d52335d2..c04cbe8b 100644 --- a/drivers/lhal/include/bflb_timer.h +++ b/drivers/lhal/include/bflb_timer.h @@ -4,6 +4,19 @@ #include "bflb_core.h" #include "bflb_clock.h" +/** @defgroup TIMER_CLK_SOURCE timer clock source definition + * @{ + */ +#define TIMER_CLKSRC_BCLK 0 +#define TIMER_CLKSRC_32K 1 +#define TIMER_CLKSRC_1K 2 +#define TIMER_CLKSRC_XTAL 3 +#define TIMER_CLKSRC_GPIO 4 +#define TIMER_CLKSRC_NO 5 +/** + * @} + */ + /** @defgroup TIMER_COUNTER_MODE timer counter mode definition * @{ */ @@ -24,11 +37,20 @@ * @} */ +/** @defgroup TIMER_CAPTURE_POLARITY timer capture polarity definition + * @{ + */ +#define TIMER_CAPTURE_POLARITY_RISING 0 +#define TIMER_CAPTURE_POLARITY_FALLING 1 +/** + * @} + */ + /** * @brief TIMER configuration structure * * @param counter_mode Timer counter mode, use @ref TIMER_COUNTER_MODE - * @param clock_source Timer clock source, use BFLB_SYSTEM_* definition + * @param clock_source Timer clock source, use @ref TIMER_CLK_SOURCE * @param clock_div Timer clock divison value, from 0 to 255 * @param trigger_comp_id Timer count register preload trigger source slelect, use @ref TIMER_COMP_ID * @param comp0_val Timer compare 0 value @@ -47,6 +69,17 @@ struct bflb_timer_config_s { uint32_t preload_val; }; +/** + * @brief TIMER capture configuration structure + * + * @param pin Timer capture pin + * @param polarity Timer capture polarity, use @ref TIMER_CAPTURE_POLARITY + */ +struct bflb_timer_capture_config_s { + uint8_t pin; + uint8_t polarity; +}; + #ifdef __cplusplus extern "C" { #endif @@ -63,8 +96,9 @@ void bflb_timer_compint_mask(struct bflb_device_s *dev, uint8_t cmp_no, bool mas bool bflb_timer_get_compint_status(struct bflb_device_s *dev, uint8_t cmp_no); void bflb_timer_compint_clear(struct bflb_device_s *dev, uint8_t cmp_no); +void bflb_timer_capture_init(struct bflb_device_s *dev, const struct bflb_timer_capture_config_s *config); + #ifdef __cplusplus } #endif - #endif \ No newline at end of file diff --git a/drivers/lhal/include/bflb_uart.h b/drivers/lhal/include/bflb_uart.h index 1e687a37..996361b3 100644 --- a/drivers/lhal/include/bflb_uart.h +++ b/drivers/lhal/include/bflb_uart.h @@ -87,6 +87,9 @@ #define UART_INTSTS_RX_ADS (1 << 10) #define UART_INTSTS_RX_AD5 (1 << 11) #endif +/** + * @} + */ /** @defgroup UART_INTCLR uart interrupt clear definition * @{ @@ -103,7 +106,6 @@ #define UART_INTCLR_RX_ADS (1 << 10) #define UART_INTCLR_RX_AD5 (1 << 11) #endif - /** * @} */ @@ -111,27 +113,26 @@ /** @defgroup UART_CMD uart feature control cmd definition * @{ */ -#define UART_CMD_SET_BAUD_RATE (0x01) -#define UART_CMD_SET_DATA_BITS (0x02) -#define UART_CMD_SET_STOP_BITS (0x03) -#define UART_CMD_SET_PARITY_BITS (0x04) -#define UART_CMD_CLR_TX_FIFO (0x05) -#define UART_CMD_CLR_RX_FIFO (0x06) -#define UART_CMD_SET_RTO_VALUE (0x07) -#define UART_CMD_SET_RTS_VALUE (0x08) -#define UART_CMD_GET_TX_FIFO_CNT (0x09) -#define UART_CMD_GET_RX_FIFO_CNT (0x0a) -#define UART_CMD_SET_AUTO_BAUD (0x0b) -#define UART_CMD_GET_AUTO_BAUD (0x0c) -#define UART_CMD_SET_BREAK_VALUE (0x0d) -#define UART_CMD_SET_TX_LIN_VALUE (0x0e) -#define UART_CMD_SET_RX_LIN_VALUE (0x0f) -#define UART_CMD_SET_TX_RX_EN (0x10) -#if !defined(BL602) && !defined(BL702) -#define UART_CMD_SET_TX_RS485_EN (0x11) -#define UART_CMD_SET_TX_RS485_POL (0x12) -#endif -#define UART_CMD_SET_ABR_PW_VALUE (0x13) +#define UART_CMD_SET_BAUD_RATE (0x01) +#define UART_CMD_SET_DATA_BITS (0x02) +#define UART_CMD_SET_STOP_BITS (0x03) +#define UART_CMD_SET_PARITY_BITS (0x04) +#define UART_CMD_CLR_TX_FIFO (0x05) +#define UART_CMD_CLR_RX_FIFO (0x06) +#define UART_CMD_SET_RTO_VALUE (0x07) +#define UART_CMD_SET_RTS_VALUE (0x08) +#define UART_CMD_GET_TX_FIFO_CNT (0x09) +#define UART_CMD_GET_RX_FIFO_CNT (0x0a) +#define UART_CMD_SET_AUTO_BAUD (0x0b) +#define UART_CMD_GET_AUTO_BAUD (0x0c) +#define UART_CMD_SET_BREAK_VALUE (0x0d) +#define UART_CMD_SET_TX_LIN_VALUE (0x0e) +#define UART_CMD_SET_RX_LIN_VALUE (0x0f) +#define UART_CMD_SET_TX_RX_EN (0x10) +#define UART_CMD_SET_TX_RS485_EN (0x11) +#define UART_CMD_SET_TX_RS485_POLARITY (0x12) +#define UART_CMD_SET_ABR_ALLOWABLE_ERROR (0x13) +#define UART_CMD_SET_SW_RTS_CONTROL (0x14) /** * @} */ @@ -170,10 +171,14 @@ extern "C" { void bflb_uart_init(struct bflb_device_s *dev, const struct bflb_uart_config_s *config); void bflb_uart_deinit(struct bflb_device_s *dev); +void bflb_uart_enable(struct bflb_device_s *dev); +void bflb_uart_disable(struct bflb_device_s *dev); void bflb_uart_link_txdma(struct bflb_device_s *dev, bool enable); void bflb_uart_link_rxdma(struct bflb_device_s *dev, bool enable); void bflb_uart_putchar(struct bflb_device_s *dev, int ch); int bflb_uart_getchar(struct bflb_device_s *dev); +void bflb_uart_put(struct bflb_device_s *dev, uint8_t *data, uint32_t len); +int bflb_uart_get(struct bflb_device_s *dev, uint8_t *data, uint32_t len); bool bflb_uart_txready(struct bflb_device_s *dev); bool bflb_uart_txempty(struct bflb_device_s *dev); bool bflb_uart_rxavailable(struct bflb_device_s *dev); @@ -183,7 +188,7 @@ void bflb_uart_errint_mask(struct bflb_device_s *dev, bool mask); uint32_t bflb_uart_get_intstatus(struct bflb_device_s *dev); void bflb_uart_int_clear(struct bflb_device_s *dev, uint32_t int_clear); -void bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); +int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg); #ifdef __cplusplus } diff --git a/drivers/lhal/include/bflb_wdg.h b/drivers/lhal/include/bflb_wdg.h index 22301308..e05124b8 100644 --- a/drivers/lhal/include/bflb_wdg.h +++ b/drivers/lhal/include/bflb_wdg.h @@ -4,6 +4,13 @@ #include "bflb_core.h" #include "bflb_clock.h" +#define WDG_CLKSRC_BCLK 0 +#define WDG_CLKSRC_32K 1 +#define WDG_CLKSRC_1K 2 +#define WDG_CLKSRC_XTAL 3 +#define WDG_CLKSRC_GPIO 4 +#define WDG_CLKSRC_NO 5 + /** @defgroup WDG_MODE Watch-dog reset/interrupt mode definition * @{ */ diff --git a/drivers/lhal/include/hardware/adc_reg.h b/drivers/lhal/include/hardware/adc_reg.h index 3eee688f..3bdc3623 100644 --- a/drivers/lhal/include/hardware/adc_reg.h +++ b/drivers/lhal/include/hardware/adc_reg.h @@ -72,7 +72,7 @@ #define GPIP_GPADC_RDY (1 << 4U) #define GPIP_GPADC_FIFO_OVERRUN (1 << 5U) #define GPIP_GPADC_FIFO_UNDERRUN (1 << 6U) -#if defined(BL702) +#if defined(BL702) || defined(BL702L) #define GPIP_GPADC_FIFO_RDY (1 << 7U) #endif #define GPIP_GPADC_RDY_CLR (1 << 8U) @@ -81,7 +81,7 @@ #define GPIP_GPADC_RDY_MASK (1 << 12U) #define GPIP_GPADC_FIFO_OVERRUN_MASK (1 << 13U) #define GPIP_GPADC_FIFO_UNDERRUN_MASK (1 << 14U) -#if defined(BL702) +#if defined(BL702) || defined(BL702L) #define GPIP_GPADC_FIFO_RDY_MASK (1 << 15U) #endif #define GPIP_GPADC_FIFO_DATA_COUNT_SHIFT (16U) @@ -127,7 +127,7 @@ #if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) #define AON_GPADC_SEN_SEL_MASK (0x7 << AON_GPADC_SEN_SEL_SHIFT) #define AON_GPADC_SEN_TEST_EN (1 << 31U) -#elif defined(BL702) || defined(BL602) +#elif defined(BL702) || defined(BL602) || defined(BL702L) #define AON_GPADC_SEN_SEL_MASK (0x3 << AON_GPADC_SEN_SEL_SHIFT) #define AON_GPADC_SEN_TEST_EN (1 << 30U) #endif diff --git a/drivers/lhal/include/hardware/cks_reg.h b/drivers/lhal/include/hardware/cks_reg.h new file mode 100644 index 00000000..323bb5c9 --- /dev/null +++ b/drivers/lhal/include/hardware/cks_reg.h @@ -0,0 +1,64 @@ +/** + ****************************************************************************** + * @file cks_reg.h + * @version V1.0 + * @date 2022-10-25 + * @brief This file is the description of.IP register + ****************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ +#ifndef __CKS_REG_H__ +#define __CKS_REG_H__ + +/**************************************************************************** + * Pre-processor Definitions +****************************************************************************/ + +/* Register offsets *********************************************************/ + +#define CKS_CONFIG_OFFSET (0x0)/* cks_config */ +#define CKS_DATA_IN_OFFSET (0x4)/* data_in */ +#define CKS_OUT_OFFSET (0x8)/* cks_out */ + +/* Register Bitfield definitions *****************************************************/ + +/* 0x0 : cks_config */ +#define CKS_CR_CKS_CLR (1<<0U) +#define CKS_CR_CKS_BYTE_SWAP (1<<1U) + +/* 0x4 : data_in */ +#define CKS_DATA_IN_SHIFT (0U) +#define CKS_DATA_IN_MASK (0xff< 1) { - return -1; + return -EINVAL; } regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET); @@ -587,4 +587,16 @@ void bflb_adc_vbat_enable(struct bflb_device_s *dev) regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET); regval |= AON_GPADC_VBAT_EN; putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET); +} + +void bflb_adc_vbat_disable(struct bflb_device_s *dev) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + + regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET); + regval &= ~AON_GPADC_VBAT_EN; + putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET); } \ No newline at end of file diff --git a/drivers/lhal/src/bflb_cks.c b/drivers/lhal/src/bflb_cks.c new file mode 100644 index 00000000..830702ae --- /dev/null +++ b/drivers/lhal/src/bflb_cks.c @@ -0,0 +1,34 @@ +#include "bflb_cks.h" +#include "hardware/cks_reg.h" + +void bflb_cks_reset(struct bflb_device_s *dev) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + regval = getreg32(reg_base + CKS_CONFIG_OFFSET); + regval |= CKS_CR_CKS_CLR; + putreg32(regval, reg_base + CKS_CONFIG_OFFSET); +} + +void bflb_cks_set_endian(struct bflb_device_s *dev, uint8_t endian) +{ + uint32_t reg_base; + + reg_base = dev->reg_base; + putreg32(endian << 1, reg_base + CKS_CONFIG_OFFSET); +} + +uint16_t bflb_cks_compute(struct bflb_device_s *dev, uint8_t *data, uint32_t length) +{ + uint32_t reg_base; + uint32_t i; + + reg_base = dev->reg_base; + for (i = 0; i < length; i++) { + putreg32(data[i], reg_base + CKS_DATA_IN_OFFSET); + } + + return ((uint16_t)(getreg32(reg_base + CKS_OUT_OFFSET) & 0xffff)); +} diff --git a/drivers/lhal/src/bflb_common.c b/drivers/lhal/src/bflb_common.c index 556ea3a9..39e6545e 100644 --- a/drivers/lhal/src/bflb_common.c +++ b/drivers/lhal/src/bflb_common.c @@ -1,4 +1,5 @@ #include "bflb_common.h" +#include "bflb_core.h" void *ATTR_TCM_SECTION arch_memcpy(void *dst, const void *src, uint32_t n) { diff --git a/drivers/lhal/src/bflb_dac.c b/drivers/lhal/src/bflb_dac.c index 1f20196b..be0a7ba0 100644 --- a/drivers/lhal/src/bflb_dac.c +++ b/drivers/lhal/src/bflb_dac.c @@ -1,7 +1,7 @@ #include "bflb_dac.h" #include "hardware/dac_reg.h" -#if defined(BL702) || defined(BL602) +#if defined(BL702) || defined(BL602) || defined(BL702L) #define DAC_GPIP_BASE ((uint32_t)0x40002000) #elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) #define DAC_GPIP_BASE ((uint32_t)0x20002000) diff --git a/drivers/lhal/src/bflb_dma.c b/drivers/lhal/src/bflb_dma.c index c623a011..89d64565 100644 --- a/drivers/lhal/src/bflb_dma.c +++ b/drivers/lhal/src/bflb_dma.c @@ -8,7 +8,7 @@ struct bflb_dma_irq_callback { void *arg; }; -#if defined(BL702) || defined(BL602) +#if defined(BL702) || defined(BL602) || defined(BL702L) const uint32_t dma_base[] = { 0x4000C000 }; struct bflb_dma_irq_callback dma_callback[1][8]; #elif defined(BL616) @@ -246,7 +246,7 @@ int bflb_dma_channel_lli_reload(struct bflb_device_s *dev, struct bflb_dma_chann lli_count_used_offset += current_lli_count; if (lli_count_used_offset > max_lli_count) { - return -2; + return -ENOMEM; } } @@ -365,8 +365,9 @@ void bflb_dma_channel_tcint_clear(struct bflb_device_s *dev) putreg32(1 << dev->sub_idx, dma_base[dev->idx] + DMA_INTTCCLEAR_OFFSET); } -void bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) +int bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) { + int ret = 0; uint32_t regval; uint32_t channel_base; @@ -394,6 +395,8 @@ void bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) break; default: + ret = -EPERM; break; } + return ret; } \ No newline at end of file diff --git a/drivers/lhal/src/bflb_emac.c b/drivers/lhal/src/bflb_emac.c index 4bd25f9a..12bd5ef2 100644 --- a/drivers/lhal/src/bflb_emac.c +++ b/drivers/lhal/src/bflb_emac.c @@ -34,12 +34,9 @@ ****************************************************************************** */ #include "bflb_core.h" -#include "bflb_common.h" #include "bflb_emac.h" #include "bflb_clock.h" -#include "bflb_mtimer.h" #include "bflb_l1c.h" - #include "hardware/emac_reg.h" /* private definition */ @@ -634,6 +631,7 @@ int bflb_emac_phy_reg_write(struct bflb_device_s *dev, uint16_t phy_reg, uint16_ */ int bflb_emac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) { + int ret = 0; uint32_t reg_val; uint32_t reg_base; @@ -748,10 +746,10 @@ int bflb_emac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) break; default: - return -1; + ret = -EPERM; break; } - return 0; + return ret; } /** diff --git a/drivers/lhal/src/bflb_gpio.c b/drivers/lhal/src/bflb_gpio.c index 7221b3e6..95fcabcd 100644 --- a/drivers/lhal/src/bflb_gpio.c +++ b/drivers/lhal/src/bflb_gpio.c @@ -16,7 +16,7 @@ void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset) mode = (cfgset & GPIO_MODE_MASK); drive = (cfgset & GPIO_DRV_MASK) >> GPIO_DRV_SHIFT; -#if defined(BL702) || defined(BL602) +#if defined(BL702) || defined(BL602) || defined(BL702L) uint32_t regval; uint8_t is_odd = 0; @@ -61,7 +61,10 @@ void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset) cfg |= (drive << (is_odd * 16 + 2)); cfg |= (function << (is_odd * 16 + 8)); - +#if defined(BL702L) + /* configure output mode:set and clr mode */ + cfg |= (1 << (is_odd * 16 + 15)); +#endif #elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) cfg_address = reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2); cfg = 0; @@ -106,7 +109,7 @@ void bflb_gpio_deinit(struct bflb_device_s *dev, uint8_t pin) void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin) { -#if defined(BL702) || defined(BL602) +#if defined(BL702) || defined(BL602) || defined(BL702L) putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET); #elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG138_OFFSET + ((pin >> 5) << 2)); @@ -115,7 +118,7 @@ void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin) void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin) { -#if defined(BL702) || defined(BL602) +#if defined(BL702) || defined(BL602) || defined(BL702L) putreg32(0 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET); #elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG140_OFFSET + ((pin >> 5) << 2)); @@ -124,7 +127,7 @@ void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin) bool bflb_gpio_read(struct bflb_device_s *dev, uint8_t pin) { -#if defined(BL702) || defined(BL602) +#if defined(BL702) || defined(BL602) || defined(BL702L) return (getreg32(dev->reg_base + GLB_GPIO_CFGCTL30_OFFSET) & (1 << pin)); #elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) return (getreg32(dev->reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2)) & GLB_REG_GPIO_0_I); @@ -144,7 +147,7 @@ void bflb_gpio_int_init(struct bflb_device_s *dev, uint8_t pin, uint8_t trig_mod bflb_gpio_int_mask(dev, pin, true); bflb_gpio_int_clear(dev, pin); -#if defined(BL702) || defined(BL602) +#if defined(BL702) || defined(BL602) || defined(BL702L) cfg_address = reg_base + GLB_GPIO_INT_MODE_SET1_OFFSET + ((pin / 10) << 2); regval = getreg32(cfg_address); regval &= ~(0x07 << ((pin % 10) * 3)); @@ -165,7 +168,7 @@ void bflb_gpio_int_mask(struct bflb_device_s *dev, uint8_t pin, bool mask) uint32_t regval; reg_base = dev->reg_base; -#if defined(BL702) || defined(BL602) +#if defined(BL702) || defined(BL602) || defined(BL702L) cfg_address = reg_base + GLB_GPIO_INT_MASK1_OFFSET; regval = getreg32(cfg_address); @@ -189,7 +192,7 @@ void bflb_gpio_int_mask(struct bflb_device_s *dev, uint8_t pin, bool mask) bool bflb_gpio_get_intstatus(struct bflb_device_s *dev, uint8_t pin) { -#if defined(BL702) || defined(BL602) +#if defined(BL702) || defined(BL602) || defined(BL702L) return (getreg32(dev->reg_base + GLB_GPIO_INT_STAT1_OFFSET) & (1 << pin)); #elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) return (getreg32(dev->reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2)) & GLB_GPIO_0_INT_STAT); @@ -203,7 +206,7 @@ void bflb_gpio_int_clear(struct bflb_device_s *dev, uint8_t pin) uint32_t regval; reg_base = dev->reg_base; -#if defined(BL702) || defined(BL602) +#if defined(BL702) || defined(BL602) || defined(BL702L) cfg_address = reg_base + GLB_GPIO_INT_CLR1_OFFSET; regval = getreg32(cfg_address); @@ -249,6 +252,26 @@ void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_fu } } + putreg32(regval, reg_base + GLB_UART_SIG_SEL_0_OFFSET); +#elif defined(BL702L) +#define GLB_UART_SIG_SEL_0_OFFSET (0xC0) + regval = getreg32(reg_base + GLB_UART_SIG_SEL_0_OFFSET); + + sig = pin % 4; + sig_pos = sig << 2; + + regval &= (~(0x0f << sig_pos)); + regval |= (uart_func << sig_pos); + + for (uint8_t i = 0; i < 4; i++) { + /* reset other sigs which are the same with uart_func */ + sig_pos = i << 2; + if (((regval & (0x0f << sig_pos)) == (uart_func << sig_pos)) && (i != sig) && (uart_func != 0x0f)) { + regval &= (~(0x0f << sig_pos)); + regval |= (0x0f << sig_pos); + } + } + putreg32(regval, reg_base + GLB_UART_SIG_SEL_0_OFFSET); #elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) #define GLB_UART_CFG1_OFFSET (0x154) @@ -313,4 +336,34 @@ void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_fu } #endif bflb_gpio_init(dev, pin, (7 << GPIO_FUNC_SHIFT) | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1); +} + +int bflb_gpio_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) +{ + int ret = 0; + uint32_t reg_base; + uint32_t regval; + uint8_t pin = arg; + + reg_base = dev->reg_base; + switch (cmd) { + case GPIO_CMD_GET_GPIO_FUN: +#if defined(BL702) || defined(BL602) || defined(BL702L) + if ((pin % 2)) { + regval = getreg32(reg_base + GLB_GPIO_CFGCTL0_OFFSET + (pin / 2 * 4)) & GLB_REG_GPIO_0_FUNC_SEL_MASK; + regval >>= GLB_REG_GPIO_0_FUNC_SEL_SHIFT; + } else { + regval = getreg32(reg_base + GLB_GPIO_CFGCTL0_OFFSET + (pin / 2 * 4)) & GLB_REG_GPIO_1_FUNC_SEL_MASK; + regval >>= GLB_REG_GPIO_1_FUNC_SEL_SHIFT; + } +#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628) + regval = getreg32(reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2)) & GLB_REG_GPIO_0_FUNC_SEL_MASK; + regval >>= GLB_REG_GPIO_0_FUNC_SEL_SHIFT; +#endif + return regval; + default: + ret = -EPERM; + break; + } + return ret; } \ No newline at end of file diff --git a/drivers/lhal/src/bflb_i2c.c b/drivers/lhal/src/bflb_i2c.c index 9b2f3da1..1de2535f 100644 --- a/drivers/lhal/src/bflb_i2c.c +++ b/drivers/lhal/src/bflb_i2c.c @@ -261,13 +261,14 @@ void bflb_i2c_init(struct bflb_device_s *dev, uint32_t frequency) bflb_i2c_disable(dev); - regval = (I2C_CR_I2C_END_EN | - I2C_CR_I2C_END_MASK | - I2C_CR_I2C_TXF_MASK | - I2C_CR_I2C_RXF_MASK | - I2C_CR_I2C_NAK_MASK | - I2C_CR_I2C_ARB_MASK | - I2C_CR_I2C_FER_MASK); + regval = getreg32(reg_base + I2C_INT_STS_OFFSET); + + regval |= (I2C_CR_I2C_END_MASK | + I2C_CR_I2C_TXF_MASK | + I2C_CR_I2C_RXF_MASK | + I2C_CR_I2C_NAK_MASK | + I2C_CR_I2C_ARB_MASK | + I2C_CR_I2C_FER_MASK); putreg32(regval, reg_base + I2C_INT_STS_OFFSET); @@ -283,12 +284,14 @@ void bflb_i2c_deinit(struct bflb_device_s *dev) bflb_i2c_disable(dev); - regval = (I2C_CR_I2C_END_MASK | - I2C_CR_I2C_TXF_MASK | - I2C_CR_I2C_RXF_MASK | - I2C_CR_I2C_NAK_MASK | - I2C_CR_I2C_ARB_MASK | - I2C_CR_I2C_FER_MASK); + regval = getreg32(reg_base + I2C_INT_STS_OFFSET); + + regval |= (I2C_CR_I2C_END_MASK | + I2C_CR_I2C_TXF_MASK | + I2C_CR_I2C_RXF_MASK | + I2C_CR_I2C_NAK_MASK | + I2C_CR_I2C_ARB_MASK | + I2C_CR_I2C_FER_MASK); putreg32(regval, reg_base + I2C_INT_STS_OFFSET); } @@ -352,17 +355,69 @@ int bflb_i2c_transfer(struct bflb_device_s *dev, struct bflb_i2c_msg_s *msgs, in } if (msgs[i].length > 256) { - return -1; + return -EINVAL; } bflb_i2c_set_datalen(dev, msgs[i].length); if (msgs[i].flags & I2C_M_READ) { bflb_i2c_set_dir(dev, 1); - bflb_i2c_read_bytes(dev, msgs[i].buffer, msgs[i].length); + if ((msgs[i].flags & I2C_M_DMA) == 0) { + bflb_i2c_read_bytes(dev, msgs[i].buffer, msgs[i].length); + } else { + bflb_i2c_enable(dev); + } } else { bflb_i2c_set_dir(dev, 0); - bflb_i2c_write_bytes(dev, msgs[i].buffer, msgs[i].length); + if ((msgs[i].flags & I2C_M_DMA) == 0) { + bflb_i2c_write_bytes(dev, msgs[i].buffer, msgs[i].length); + } else { + bflb_i2c_enable(dev); + } } } return 0; -} \ No newline at end of file +} + +void bflb_i2c_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + regval = getreg32(reg_base + I2C_INT_STS_OFFSET); + regval &= ~((int_type & 0xff) << 8); + if (mask) { + regval |= (int_type & 0xff) << 8; + } + putreg32(regval, reg_base + I2C_INT_STS_OFFSET); +} + +void bflb_i2c_int_clear(struct bflb_device_s *dev, uint32_t int_clear) +{ + uint32_t reg_base; + uint32_t regval; + + reg_base = dev->reg_base; + regval = getreg32(reg_base + I2C_INT_STS_OFFSET); + regval |= (int_clear & 0xff) << 16; + putreg32(regval, reg_base + I2C_INT_STS_OFFSET); +} + +uint32_t bflb_i2c_get_intstatus(struct bflb_device_s *dev) +{ + uint32_t reg_base; + + reg_base = dev->reg_base; + return(getreg32(reg_base + I2C_INT_STS_OFFSET) & 0xff); +} + +int bflb_i2c_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) +{ + int ret = 0; + switch (cmd) { + default: + ret = -EPERM; + break; + } + return ret; +} diff --git a/drivers/lhal/src/bflb_irq.c b/drivers/lhal/src/bflb_irq.c index 82d834df..f4b7d7c8 100644 --- a/drivers/lhal/src/bflb_irq.c +++ b/drivers/lhal/src/bflb_irq.c @@ -46,7 +46,7 @@ void bflb_irq_restore(uint32_t flags) int bflb_irq_attach(int irq, irq_callback isr, void *arg) { if (irq > CONFIG_IRQ_NUM) { - return -1; + return -EINVAL; } g_irqvector[irq].handler = isr; g_irqvector[irq].arg = arg; @@ -56,7 +56,7 @@ int bflb_irq_attach(int irq, irq_callback isr, void *arg) int bflb_irq_detach(int irq) { if (irq > CONFIG_IRQ_NUM) { - return -1; + return -EINVAL; } return 0; } diff --git a/drivers/lhal/src/bflb_mtimer.c b/drivers/lhal/src/bflb_mtimer.c index 95bcc4b7..351d960d 100644 --- a/drivers/lhal/src/bflb_mtimer.c +++ b/drivers/lhal/src/bflb_mtimer.c @@ -1,4 +1,6 @@ #include "bflb_mtimer.h" +#include "bflb_core.h" +#include "bflb_irq.h" #if defined(BL602) || defined(BL702) || defined(BL702L) #include #else @@ -34,6 +36,11 @@ void bflb_mtimer_config(uint64_t ticks, void (*interruptfun)(void)) bflb_irq_enable(7); } +__WEAK uint32_t bflb_mtimer_get_freq(void) +{ + return 1 * 1000 * 1000; +} + uint64_t bflb_mtimer_get_time_us() { volatile uint64_t tmp_low, tmp_high, tmp_low1, tmp_high1; @@ -51,8 +58,11 @@ uint64_t bflb_mtimer_get_time_us() tmp_high1 = (uint64_t)csi_coret_get_valueh(); #endif } while (tmp_low > tmp_low1 || tmp_high != tmp_high1); - - return (uint64_t)((tmp_high1 << 32) + tmp_low1); +#ifdef CONFIG_MTIMER_CUSTOM_FREQUENCE + return ((uint64_t)(((tmp_high1 << 32) + tmp_low1)) * ((uint64_t)(1 * 1000 * 1000)) / bflb_mtimer_get_freq()); +#else + return (uint64_t)(((tmp_high1 << 32) + tmp_low1)); +#endif } uint64_t bflb_mtimer_get_time_ms() diff --git a/drivers/lhal/src/bflb_pwm_v1.c b/drivers/lhal/src/bflb_pwm_v1.c index 16dd3ca0..323cc993 100644 --- a/drivers/lhal/src/bflb_pwm_v1.c +++ b/drivers/lhal/src/bflb_pwm_v1.c @@ -25,6 +25,7 @@ void bflb_pwm_v1_channel_init(struct bflb_device_s *dev, uint8_t ch, const struc regval |= (1 << PWM_REG_CLK_SEL_SHIFT); } else if (config->clk_source == BFLB_SYSTEM_32K_CLK) { regval |= (2 << PWM_REG_CLK_SEL_SHIFT); + } else { } putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20); @@ -189,8 +190,9 @@ void bflb_pwm_v1_int_clear(struct bflb_device_s *dev, uint32_t int_clear) putreg32(regval, dev->reg_base + PWM_INT_CONFIG_OFFSET); } -void bflb_pwm_v1_feature_control(struct bflb_device_s *dev, uint8_t ch, int cmd, size_t arg) +int bflb_pwm_v1_feature_control(struct bflb_device_s *dev, uint8_t ch, int cmd, size_t arg) { + int ret = 0; uint32_t reg_base; uint32_t regval; @@ -244,6 +246,8 @@ void bflb_pwm_v1_feature_control(struct bflb_device_s *dev, uint8_t ch, int cmd, break; default: + ret = -EPERM; break; } + return ret; } \ No newline at end of file diff --git a/drivers/lhal/src/bflb_pwm_v2.c b/drivers/lhal/src/bflb_pwm_v2.c index e53c96fa..f38786d9 100644 --- a/drivers/lhal/src/bflb_pwm_v2.c +++ b/drivers/lhal/src/bflb_pwm_v2.c @@ -25,6 +25,7 @@ void bflb_pwm_v2_init(struct bflb_device_s *dev, const struct bflb_pwm_v2_config regval |= (1 << PWM_REG_CLK_SEL_SHIFT); } else if (config->clk_source == BFLB_SYSTEM_32K_CLK) { regval |= (2 << PWM_REG_CLK_SEL_SHIFT); + } else { } regval &= ~PWM_CLK_DIV_MASK; regval |= (uint32_t)config->clk_div << PWM_CLK_DIV_SHIFT; @@ -292,8 +293,9 @@ uint32_t bflb_pwm_v2_get_intstatus(struct bflb_device_s *dev) return (regval_sts & ~regval_mask & regval_en); } -void bflb_pwm_v2_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) +int bflb_pwm_v2_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) { + int ret = 0; uint32_t reg_base; uint32_t regval; @@ -354,6 +356,8 @@ void bflb_pwm_v2_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) break; default: + ret = -EPERM; break; } + return ret; } diff --git a/drivers/lhal/src/bflb_sec_aes.c b/drivers/lhal/src/bflb_sec_aes.c index 9a87099d..d6c21443 100644 --- a/drivers/lhal/src/bflb_sec_aes.c +++ b/drivers/lhal/src/bflb_sec_aes.c @@ -2,11 +2,12 @@ #include "hardware/sec_eng_reg.h" #define CONFIG_BFLB_AES_USE_BE -#define CONFIG_BFLB_AES_HW_KEY_SEL 1 #define BFLB_PUT_LE32(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0])) #define BFLB_PUT_BE32(p) ((p[0] << 24) | (p[1] << 16) | (p[2] << 8) | (p[3])) +volatile uint8_t hw_key_sel = 1; + void bflb_aes_init(struct bflb_device_s *dev) { uint32_t regval; @@ -37,6 +38,11 @@ void bflb_aes_deinit(struct bflb_device_s *dev) putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET); } +void bflb_aes_set_hwkey(uint8_t keysel) +{ + hw_key_sel = keysel; +} + void bflb_aes_set_mode(struct bflb_device_s *dev, uint8_t mode) { uint32_t regval; @@ -89,12 +95,12 @@ void bflb_aes_setkey(struct bflb_device_s *dev, const uint8_t *key, uint16_t key if (key == NULL) { regval = getreg32(reg_base + SEC_ENG_SE_AES_0_KEY_SEL_OFFSET); regval &= ~SEC_ENG_SE_AES_0_KEY_SEL_MASK; - regval |= (CONFIG_BFLB_AES_HW_KEY_SEL << SEC_ENG_SE_AES_0_KEY_SEL_SHIFT); + regval |= (hw_key_sel << SEC_ENG_SE_AES_0_KEY_SEL_SHIFT); putreg32(regval, reg_base + SEC_ENG_SE_AES_0_KEY_SEL_OFFSET); regval = getreg32(reg_base + SEC_ENG_SE_AES_1_KEY_SEL_OFFSET); regval &= ~SEC_ENG_SE_AES_1_KEY_SEL_MASK; - regval |= (CONFIG_BFLB_AES_HW_KEY_SEL << SEC_ENG_SE_AES_1_KEY_SEL_SHIFT); + regval |= (hw_key_sel << SEC_ENG_SE_AES_1_KEY_SEL_SHIFT); putreg32(regval, reg_base + SEC_ENG_SE_AES_1_KEY_SEL_OFFSET); } else { putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_0_OFFSET); @@ -137,15 +143,11 @@ int bflb_aes_encrypt(struct bflb_device_s *dev, reg_base = dev->reg_base; - regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET); - - if (regval & SEC_ENG_SE_AES_0_BUSY) { - return -1; - } if (len % 16) { - return -2; + return -EINVAL; } + regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET); regval &= ~SEC_ENG_SE_AES_0_TRIG_1T; regval &= ~SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select new iv */ regval &= ~SEC_ENG_SE_AES_0_DEC_EN; /* Set AES encryption */ @@ -202,16 +204,11 @@ int bflb_aes_decrypt(struct bflb_device_s *dev, reg_base = dev->reg_base; - regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET); - - if (regval & SEC_ENG_SE_AES_0_BUSY) { - return -1; - } - if (len % 16) { - return -2; + return -EINVAL; } + regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET); regval &= ~SEC_ENG_SE_AES_0_TRIG_1T; regval &= ~SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select new iv */ regval |= SEC_ENG_SE_AES_0_DEC_EN; /* Set AES decryption */ @@ -254,3 +251,115 @@ int bflb_aes_decrypt(struct bflb_device_s *dev, } return 0; } + +void bflb_aes_link_init(struct bflb_device_s *dev) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + +#ifdef CONFIG_BFLB_AES_USE_BE + putreg32(0x1f, reg_base + SEC_ENG_SE_AES_0_ENDIAN_OFFSET); +#else + putreg32(0x10, reg_base + SEC_ENG_SE_AES_0_ENDIAN_OFFSET); +#endif + + regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET); + regval |= SEC_ENG_SE_AES_0_LINK_MODE; + regval |= SEC_ENG_SE_AES_0_EN; + putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET); +} + +void bflb_aes_link_deinit(struct bflb_device_s *dev) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + + regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET); + regval &= ~SEC_ENG_SE_AES_0_LINK_MODE; + regval &= ~SEC_ENG_SE_AES_0_EN; + putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET); +} + +int bflb_aes_link_update(struct bflb_device_s *dev, + uint32_t link_addr, + const uint8_t *input, + uint8_t *output, + uint32_t len) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + + if ((len % 16) || ((link_addr & 0x03))) { + return -EINVAL; + } + + regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET); + regval &= ~SEC_ENG_SE_AES_0_TRIG_1T; + putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET); + + /* Set link address */ + putreg32(link_addr, reg_base + SEC_ENG_SE_AES_0_LINK_OFFSET); + + /* Change source buffer address and destination buffer address */ + *(uint32_t *)(uintptr_t)(link_addr + 4) = (uint32_t)(uintptr_t)input; + *(uint32_t *)(uintptr_t)(link_addr + 8) = (uint32_t)(uintptr_t)output; + + /* Set data length */ + *((uint16_t *)(uintptr_t)link_addr + 1) = len / 16; + + regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET); + regval |= SEC_ENG_SE_AES_0_TRIG_1T; + putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET); + + __asm volatile("nop"); + __asm volatile("nop"); + + while (getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET) & SEC_ENG_SE_AES_0_BUSY) { + } + + return 0; +} + +void bflb_group0_request_aes_access(struct bflb_device_s *dev) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + + regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET); + if (((regval >> 2) & 0x03) == 0x03) { + putreg32(0x02, reg_base + SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET); + + regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET); + if (((regval >> 2) & 0x03) == 0x01) { + } + } +} + +void bflb_group0_release_aes_access(struct bflb_device_s *dev) +{ + uint32_t reg_base; + + reg_base = dev->reg_base; + + putreg32(0x06, reg_base + SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET); +} + +void bflb_aes_set_hwkey_source(struct bflb_device_s *dev, uint8_t source) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + + regval = getreg32(reg_base + SEC_ENG_SE_AES_0_SBOOT_OFFSET); + regval |= (source << 0); + putreg32(0x02, reg_base + SEC_ENG_SE_AES_0_SBOOT_OFFSET); +} diff --git a/drivers/lhal/src/bflb_sec_sha.c b/drivers/lhal/src/bflb_sec_sha.c index e8923442..53b303d2 100644 --- a/drivers/lhal/src/bflb_sec_sha.c +++ b/drivers/lhal/src/bflb_sec_sha.c @@ -27,14 +27,6 @@ (b)[(i) + 7] = (uint8_t)((n)); \ } -#define SEC_ENG_SHA256 0 -#define SEC_ENG_SHA224 1 -#define SEC_ENG_SHA1 2 -#define SEC_ENG_SHA512 4 -#define SEC_ENG_SHA384 5 -#define SEC_ENG_SHA512T224 6 -#define SEC_ENG_SHA512T256 7 - void bflb_sha_init(struct bflb_device_s *dev, uint8_t mode) { uint32_t regval; @@ -45,18 +37,7 @@ void bflb_sha_init(struct bflb_device_s *dev, uint8_t mode) regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); regval &= ~SEC_ENG_SE_SHA_0_MODE_EXT_MASK; regval &= ~SEC_ENG_SE_SHA_0_MODE_MASK; - - if (mode == SHA_MODE_SHA1) { - regval |= (SEC_ENG_SHA1 << SEC_ENG_SE_SHA_0_MODE_SHIFT); - } else if (mode == SHA_MODE_SHA224) { - regval |= (SEC_ENG_SHA224 << SEC_ENG_SE_SHA_0_MODE_SHIFT); - } else if (mode == SHA_MODE_SHA256) { - regval |= (SEC_ENG_SHA256 << SEC_ENG_SE_SHA_0_MODE_SHIFT); - } else if (mode == SHA_MODE_SHA384) { - regval |= (SEC_ENG_SHA384 << SEC_ENG_SE_SHA_0_MODE_SHIFT); - } else if (mode == SHA_MODE_SHA512) { - regval |= (SEC_ENG_SHA512 << SEC_ENG_SE_SHA_0_MODE_SHIFT); - } + regval |= (mode << SEC_ENG_SE_SHA_0_MODE_SHIFT); putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); } @@ -78,18 +59,7 @@ void bflb_sha1_start(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx) void bflb_sha256_start(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx) { - uint32_t regval; - uint32_t reg_base; - - reg_base = dev->reg_base; - - memset(ctx, 0, sizeof(struct bflb_sha256_ctx_s)); - ctx->sha_padding[0] = 0x80; - - regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); - regval |= SEC_ENG_SE_SHA_0_EN; - regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL; - putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); + return bflb_sha1_start(dev, (struct bflb_sha1_ctx_s *)ctx); } void bflb_sha512_start(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx) @@ -118,16 +88,10 @@ int bflb_sha1_update(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, con if (len == 0) { return 0; } - if (((uint32_t)input) & 0x1f) { - return -1; - } reg_base = dev->reg_base; regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); - if (regval & SEC_ENG_SE_SHA_0_BUSY) { - return -1; - } if (ctx->sha_feed) { regval |= SEC_ENG_SE_SHA_0_HASH_SEL; @@ -146,7 +110,7 @@ int bflb_sha1_update(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, con } if (left && len >= fill) { - memcpy((void *)((uint8_t *)ctx->sha_buf + left), input, fill); + arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill); putreg32((uint32_t)ctx->sha_buf, reg_base + SEC_ENG_SE_SHA_0_MSA_OFFSET); regval &= ~SEC_ENG_SE_SHA_0_MSG_LEN_MASK; @@ -195,7 +159,7 @@ int bflb_sha1_update(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, con } /* Copy left data into temp buffer */ - memcpy((void *)((uint8_t *)ctx->sha_buf + left), input, len); + arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len); } while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) { @@ -205,98 +169,7 @@ int bflb_sha1_update(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, con int bflb_sha256_update(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, const uint8_t *input, uint32_t len) { - uint32_t regval; - uint32_t reg_base; - uint32_t fill; - uint32_t left; - - if (len == 0) { - return 0; - } - - if (((uint32_t)input) & 0x1f) { - return -1; - } - - reg_base = dev->reg_base; - - regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); - if (regval & SEC_ENG_SE_SHA_0_BUSY) { - return -1; - } - - if (ctx->sha_feed) { - regval |= SEC_ENG_SE_SHA_0_HASH_SEL; - } else { - regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL; - } - - left = ctx->total[0] & 0x3F; - fill = 64 - left; - - ctx->total[0] += len; - ctx->total[0] &= 0xFFFFFFFF; - - if (ctx->total[0] < len) { - ctx->total[1]++; - } - - if (left && len >= fill) { - memcpy((void *)((uint8_t *)ctx->sha_buf + left), input, fill); - putreg32((uint32_t)ctx->sha_buf, reg_base + SEC_ENG_SE_SHA_0_MSA_OFFSET); - - regval &= ~SEC_ENG_SE_SHA_0_MSG_LEN_MASK; - regval |= (1 << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT); - putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); - - regval |= SEC_ENG_SE_SHA_0_TRIG_1T; - putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); - - ctx->sha_feed = 1; - input += fill; - len -= fill; - left = 0; - } - - fill = len / 64; - len = len % 64; - - if (fill > 0) { - while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) { - } - - /* SHA need set se_sha_sel to 1 to keep the last sha state */ - regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); - if (ctx->sha_feed) { - regval |= SEC_ENG_SE_SHA_0_HASH_SEL; - } else { - regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL; - } - /* Fill data */ - putreg32((uintptr_t)input, reg_base + SEC_ENG_SE_SHA_0_MSA_OFFSET); - - regval &= ~SEC_ENG_SE_SHA_0_MSG_LEN_MASK; - regval |= (fill << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT); - putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); - - regval |= SEC_ENG_SE_SHA_0_TRIG_1T; - putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); - - input += (fill * 64); - ctx->sha_feed = 1; - } - - if (len > 0) { - while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) { - } - - /* Copy left data into temp buffer */ - memcpy((void *)((uint8_t *)ctx->sha_buf + left), input, len); - } - - while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) { - } - return 0; + return bflb_sha1_update(dev, (struct bflb_sha1_ctx_s *)ctx, input, len); } int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, const uint8_t *input, uint32_t len) @@ -309,16 +182,10 @@ int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, if (len == 0) { return 0; } - if (((uint32_t)input) & 0x1f) { - return -1; - } reg_base = dev->reg_base; regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); - if (regval & SEC_ENG_SE_SHA_0_BUSY) { - return -1; - } if (ctx->sha_feed) { regval |= SEC_ENG_SE_SHA_0_HASH_SEL; @@ -336,7 +203,7 @@ int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, } if (left && len >= fill) { - memcpy((void *)((uint8_t *)ctx->sha_buf + left), input, fill); + arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill); putreg32((uint32_t)ctx->sha_buf, reg_base + SEC_ENG_SE_SHA_0_MSA_OFFSET); regval &= ~SEC_ENG_SE_SHA_0_MSG_LEN_MASK; @@ -385,7 +252,7 @@ int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, } /* Copy left data into temp buffer */ - memcpy((void *)((uint8_t *)ctx->sha_buf + left), input, len); + arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len); } while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) { @@ -414,7 +281,7 @@ void bflb_sha1_finish(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, ui padn = (last < 56) ? (56 - last) : (120 - last); bflb_sha1_update(dev, ctx, (uint8_t *)ctx->sha_padding, padn); - memcpy(ctx->sha_padding, msgLen, 8); + arch_memcpy_fast(ctx->sha_padding, msgLen, 8); bflb_sha1_update(dev, ctx, (uint8_t *)ctx->sha_padding, 8); /* Copy SHA value */ @@ -453,81 +320,7 @@ void bflb_sha1_finish(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, ui void bflb_sha256_finish(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, uint8_t *output) { - uint32_t last, padn; - uint32_t high, low; - uint8_t msgLen[8]; - uint8_t mode; - uint32_t regval; - uint32_t reg_base; - uint8_t *p = (uint8_t *)output; - - reg_base = dev->reg_base; - - high = (ctx->total[0] >> 29) | (ctx->total[1] << 3); - low = (ctx->total[0] << 3); - - PUT_UINT32_BE(high, msgLen, 0); - PUT_UINT32_BE(low, msgLen, 4); - - last = ctx->total[0] & 0x3F; - padn = (last < 56) ? (56 - last) : (120 - last); - - bflb_sha256_update(dev, ctx, (uint8_t *)ctx->sha_padding, padn); - memcpy(ctx->sha_padding, msgLen, 8); - bflb_sha256_update(dev, ctx, (uint8_t *)ctx->sha_padding, 8); - - /* Copy SHA value */ - regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET); - *p++ = (regval & 0xff); - *p++ = ((regval >> 8) & 0xff); - *p++ = ((regval >> 16) & 0xff); - *p++ = ((regval >> 24) & 0xff); - regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET); - *p++ = (regval & 0xff); - *p++ = ((regval >> 8) & 0xff); - *p++ = ((regval >> 16) & 0xff); - *p++ = ((regval >> 24) & 0xff); - regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET); - *p++ = (regval & 0xff); - *p++ = ((regval >> 8) & 0xff); - *p++ = ((regval >> 16) & 0xff); - *p++ = ((regval >> 24) & 0xff); - regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET); - *p++ = (regval & 0xff); - *p++ = ((regval >> 8) & 0xff); - *p++ = ((regval >> 16) & 0xff); - *p++ = ((regval >> 24) & 0xff); - regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET); - *p++ = (regval & 0xff); - *p++ = ((regval >> 8) & 0xff); - *p++ = ((regval >> 16) & 0xff); - *p++ = ((regval >> 24) & 0xff); - regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET); - *p++ = (regval & 0xff); - *p++ = ((regval >> 8) & 0xff); - *p++ = ((regval >> 16) & 0xff); - *p++ = ((regval >> 24) & 0xff); - regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET); - *p++ = (regval & 0xff); - *p++ = ((regval >> 8) & 0xff); - *p++ = ((regval >> 16) & 0xff); - *p++ = ((regval >> 24) & 0xff); - - mode = (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_MODE_MASK) >> SEC_ENG_SE_SHA_0_MODE_SHIFT; - - if (mode == SEC_ENG_SHA256) { - regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET); - *p++ = (regval & 0xff); - *p++ = ((regval >> 8) & 0xff); - *p++ = ((regval >> 16) & 0xff); - *p++ = ((regval >> 24) & 0xff); - } - - /* Disable SHA engine*/ - regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); - regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL; - regval &= ~SEC_ENG_SE_SHA_0_EN; - putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); + return bflb_sha1_finish(dev, (struct bflb_sha1_ctx_s *)ctx, output); } void bflb_sha512_finish(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, uint8_t *output) @@ -552,7 +345,7 @@ void bflb_sha512_finish(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx padn = (last < 112) ? (112 - last) : (240 - last); bflb_sha512_update(dev, ctx, (uint8_t *)ctx->sha_padding, padn); - memcpy(ctx->sha_padding, msgLen, 16); + arch_memcpy_fast(ctx->sha_padding, msgLen, 16); bflb_sha512_update(dev, ctx, (uint8_t *)ctx->sha_padding, 16); /* Copy SHA value */ @@ -594,14 +387,14 @@ void bflb_sha512_finish(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx mode = (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_MODE_MASK) >> SEC_ENG_SE_SHA_0_MODE_SHIFT; - if ((mode == SEC_ENG_SHA512) || (mode == SEC_ENG_SHA384) || (mode == SEC_ENG_SHA512T256)) { + if ((mode == SHA_MODE_SHA512) || (mode == SHA_MODE_SHA384) || (mode == SHA_MODE_SHA512T256)) { regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET); *p++ = (regval & 0xff); *p++ = ((regval >> 8) & 0xff); *p++ = ((regval >> 16) & 0xff); *p++ = ((regval >> 24) & 0xff); - if ((mode == SEC_ENG_SHA512) || (mode == SEC_ENG_SHA384)) { + if ((mode == SHA_MODE_SHA512) || (mode == SHA_MODE_SHA384)) { regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_4_OFFSET); *p++ = (regval & 0xff); *p++ = ((regval >> 8) & 0xff); @@ -623,7 +416,7 @@ void bflb_sha512_finish(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx *p++ = ((regval >> 16) & 0xff); *p++ = ((regval >> 24) & 0xff); - if (mode == SEC_ENG_SHA512) { + if (mode == SHA_MODE_SHA512) { regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_6_OFFSET); *p++ = (regval & 0xff); *p++ = ((regval >> 8) & 0xff); @@ -653,4 +446,363 @@ void bflb_sha512_finish(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL; regval &= ~SEC_ENG_SE_SHA_0_EN; putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); -} \ No newline at end of file +} + +void bflb_sha_link_init(struct bflb_device_s *dev) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + + regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); + regval |= SEC_ENG_SE_SHA_0_EN; + regval |= SEC_ENG_SE_SHA_0_LINK_MODE; + putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); +} + +void bflb_sha_link_deinit(struct bflb_device_s *dev) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + + regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); + regval &= ~SEC_ENG_SE_SHA_0_EN; + regval &= ~SEC_ENG_SE_SHA_0_LINK_MODE; + putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); +} + +void bflb_sha1_link_start(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx) +{ + memset(ctx, 0, sizeof(struct bflb_sha1_ctx_s)); + ctx->sha_padding[0] = 0x80; +} + +void bflb_sha256_link_start(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx) +{ + return bflb_sha1_link_start(dev, (struct bflb_sha1_ctx_s *)ctx); +} + +void bflb_sha512_link_start(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx) +{ + memset(ctx, 0, sizeof(struct bflb_sha512_ctx_s)); + ctx->sha_padding[0] = 0x80; +} + +int bflb_sha1_link_update(struct bflb_device_s *dev, + struct bflb_sha1_ctx_s *ctx, + uint32_t link_addr, + const uint8_t *input, + uint32_t len) +{ + uint32_t regval; + uint32_t reg_base; + uint32_t fill; + uint32_t left; + + if (len == 0) { + return 0; + } + + reg_base = dev->reg_base; + + /* Set link address */ + putreg32(link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET); + + left = ctx->total[0] & 0x3F; + fill = 64 - left; + + ctx->total[0] += len; + ctx->total[0] &= 0xFFFFFFFF; + + if (ctx->total[0] < len) { + ctx->total[1]++; + } + + if (left && len >= fill) { + arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill); + /* Set data source address */ + *(uint32_t *)(uintptr_t)(link_addr + 4) = (uint32_t)(uintptr_t)ctx->sha_buf; + + /* Set data length */ + *((uint16_t *)(uintptr_t)link_addr + 1) = 1; + + regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); + regval |= SEC_ENG_SE_SHA_0_TRIG_1T; + putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); + + /* Choose accumulating last hash in the next time */ + *((uint32_t *)(uintptr_t)link_addr) |= 0x40; + input += fill; + len -= fill; + left = 0; + } + + fill = len / 64; + len = len % 64; + + if (fill > 0) { + while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) { + } + + /* Fill data */ + *(uint32_t *)(uintptr_t)(link_addr + 4) = (uint32_t)(uintptr_t)input; + *((uint16_t *)(uintptr_t)link_addr + 1) = fill; + + regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); + regval |= SEC_ENG_SE_SHA_0_TRIG_1T; + putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); + + input += (fill * 64); + /* Choose accumulating last hash in the next time */ + *((uint32_t *)(uintptr_t)link_addr) |= 0x40; + } + + if (len > 0) { + while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) { + } + + /* Copy left data into temp buffer */ + arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len); + } + + while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) { + } + return 0; +} + +int bflb_sha256_link_update(struct bflb_device_s *dev, + struct bflb_sha256_ctx_s *ctx, + uint32_t link_addr, + const uint8_t *input, + uint32_t len) +{ + return bflb_sha1_link_update(dev, (struct bflb_sha1_ctx_s *)ctx, link_addr, input, len); +} + +int bflb_sha512_link_update(struct bflb_device_s *dev, + struct bflb_sha512_ctx_s *ctx, + uint32_t link_addr, + const uint8_t *input, + uint32_t len) +{ + uint32_t regval; + uint32_t reg_base; + uint32_t fill; + uint32_t left; + + if (len == 0) { + return 0; + } + + reg_base = dev->reg_base; + + /* Set link address */ + putreg32(link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET); + + left = ctx->total[0] & 0x7F; + fill = 128 - left; + + ctx->total[0] += len; + + if (ctx->total[0] < len) { + ctx->total[1]++; + } + + if (left && len >= fill) { + arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill); + /* Set data source address */ + *(uint32_t *)(uintptr_t)(link_addr + 4) = (uint32_t)(uintptr_t)ctx->sha_buf; + + /* Set data length */ + *((uint16_t *)(uintptr_t)link_addr + 1) = 1; + + regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); + regval |= SEC_ENG_SE_SHA_0_TRIG_1T; + putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); + + /* Choose accumulating last hash in the next time */ + *((uint32_t *)(uintptr_t)link_addr) |= 0x40; + input += fill; + len -= fill; + left = 0; + } + + fill = len / 128; + len = len % 128; + + if (fill > 0) { + while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) { + } + + /* Fill data */ + *(uint32_t *)(uintptr_t)(link_addr + 4) = (uint32_t)(uintptr_t)input; + *((uint16_t *)(uintptr_t)link_addr + 1) = fill; + + regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); + regval |= SEC_ENG_SE_SHA_0_TRIG_1T; + putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET); + + input += (fill * 128); + /* Choose accumulating last hash in the next time */ + *((uint32_t *)(uintptr_t)link_addr) |= 0x40; + } + + if (len > 0) { + while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) { + } + + /* Copy left data into temp buffer */ + arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len); + } + + while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) { + } + return 0; +} + +void bflb_sha1_link_finish(struct bflb_device_s *dev, + struct bflb_sha1_ctx_s *ctx, + uint32_t link_addr, + uint8_t *output) +{ + uint32_t last, padn; + uint32_t high, low; + uint8_t msgLen[8]; + + uint32_t reg_base; + uint32_t sha_mode = (*(uint32_t *)(uintptr_t)link_addr) >> 2 & 0x7; + + reg_base = dev->reg_base; + + /* Set link address */ + putreg32(link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET); + + high = (ctx->total[0] >> 29) | (ctx->total[1] << 3); + low = (ctx->total[0] << 3); + + PUT_UINT32_BE(high, msgLen, 0); + PUT_UINT32_BE(low, msgLen, 4); + + last = ctx->total[0] & 0x3F; + padn = (last < 56) ? (56 - last) : (120 - last); + + bflb_sha1_link_update(dev, ctx, link_addr, (uint8_t *)ctx->sha_padding, padn); + bflb_sha1_link_update(dev, ctx, link_addr, msgLen, 8); + + /* Get result according to SHA mode,result is placed in (link address + offset:8) */ + switch (sha_mode) { + case 0: + arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 32); + break; + + case 1: + arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 28); + break; + + case 2: + arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 20); + break; + + case 3: + arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 20); + break; + + default: + break; + } + + /* Choose new hash in the next time */ + *((uint32_t *)(uintptr_t)link_addr) &= ~0x40; +} + +void bflb_sha256_link_finish(struct bflb_device_s *dev, + struct bflb_sha256_ctx_s *ctx, + uint32_t link_addr, + uint8_t *output) +{ + return bflb_sha1_link_finish(dev, (struct bflb_sha1_ctx_s *)ctx, link_addr, output); +} + +void bflb_sha512_link_finish(struct bflb_device_s *dev, + struct bflb_sha512_ctx_s *ctx, + uint32_t link_addr, + uint8_t *output) +{ + uint32_t last, padn; + uint32_t high, low; + uint8_t msgLen[16]; + + uint32_t reg_base; + uint32_t sha_mode = (*(uint32_t *)(uintptr_t)link_addr) >> 2 & 0x7; + + reg_base = dev->reg_base; + + /* Set link address */ + putreg32(link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET); + + high = (ctx->total[0] >> 61) | (ctx->total[1] << 3); + low = (ctx->total[0] << 3); + + PUT_UINT32_BE(high, msgLen, 0); + PUT_UINT32_BE(low, msgLen, 8); + + last = ctx->total[0] & 0x7F; + padn = (last < 112) ? (112 - last) : (240 - last); + + bflb_sha512_link_update(dev, ctx, link_addr, (uint8_t *)ctx->sha_padding, padn); + bflb_sha512_link_update(dev, ctx, link_addr, msgLen, 16); + + /* Get result according to SHA mode,result is placed in (link address + offset:8) */ + switch (sha_mode) { + case 4: + arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 64); + break; + + case 5: + arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 48); + break; + + case 6: + arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 28); + break; + + case 7: + arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(link_addr + 8), 32); + break; + + default: + break; + } + + /* Choose new hash in the next time */ + *((uint32_t *)(uintptr_t)link_addr) &= ~0x40; +} + +void bflb_group0_request_sha_access(struct bflb_device_s *dev) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + + regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET); + if ((regval & 0x03) == 0x03) { + putreg32(0x02, reg_base + SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET); + + regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET); + if ((regval & 0x03) == 0x01) { + } + } +} + +void bflb_group0_release_sha_access(struct bflb_device_s *dev) +{ + uint32_t reg_base; + + reg_base = dev->reg_base; + + putreg32(0x06, reg_base + SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET); +} diff --git a/drivers/lhal/src/bflb_sec_trng.c b/drivers/lhal/src/bflb_sec_trng.c index 111ca326..eec914aa 100644 --- a/drivers/lhal/src/bflb_sec_trng.c +++ b/drivers/lhal/src/bflb_sec_trng.c @@ -9,7 +9,7 @@ p[3] = (val >> 24) & 0xff; \ } -void bflb_trng_read(struct bflb_device_s *dev, uint8_t data[32]) +int bflb_trng_read(struct bflb_device_s *dev, uint8_t data[32]) { uint32_t regval; uint32_t reg_base; @@ -90,4 +90,74 @@ void bflb_trng_read(struct bflb_device_s *dev, uint8_t data[32]) regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); regval |= SEC_ENG_SE_TRNG_0_INT_CLR_1T; putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET); + + return 0; +} + +int bflb_trng_readlen(uint8_t *data, uint32_t len) +{ + struct bflb_device_s *trng; + + uint8_t tmp_buf[32]; + uint32_t readlen = 0; + uint32_t i = 0, cnt = 0; + + trng = bflb_device_get_by_name("trng"); + + while (readlen < len) { + if (bflb_trng_read(trng, tmp_buf) != 0) { + return -ETIMEDOUT; + } + + cnt = len - readlen; + + if (cnt > sizeof(tmp_buf)) { + cnt = sizeof(tmp_buf); + } + + for (i = 0; i < cnt; i++) { + data[readlen + i] = tmp_buf[i]; + } + + readlen += cnt; + } + + return 0; +} + +long random(void) +{ + uint32_t data[8]; + struct bflb_device_s *trng; + + trng = bflb_device_get_by_name("trng"); + bflb_trng_read(trng, (uint8_t *)data); + + return data[0]; +} + +void bflb_group0_request_trng_access(struct bflb_device_s *dev) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + + regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET); + if (((regval >> 4) & 0x03) == 0x03) { + putreg32(0x04, reg_base + SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET); + + regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET); + if (((regval >> 4) & 0x03) == 0x01) { + } + } +} + +void bflb_group0_release_trng_access(struct bflb_device_s *dev) +{ + uint32_t reg_base; + + reg_base = dev->reg_base; + + putreg32(0x06, reg_base + SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET); } \ No newline at end of file diff --git a/drivers/lhal/src/bflb_spi.c b/drivers/lhal/src/bflb_spi.c index d8a15014..45da67f5 100644 --- a/drivers/lhal/src/bflb_spi.c +++ b/drivers/lhal/src/bflb_spi.c @@ -472,7 +472,7 @@ void bflb_spi_int_clear(struct bflb_device_s *dev, uint32_t int_clear) putreg32(regval, reg_base + SPI_INT_STS_OFFSET); } -int bflb_spi_isbusy(struct bflb_device_s *dev) +bool bflb_spi_isbusy(struct bflb_device_s *dev) { uint32_t reg_base; uint32_t regval; @@ -483,21 +483,21 @@ int bflb_spi_isbusy(struct bflb_device_s *dev) regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET); #if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT) if ((regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT < SPI_FIFO_BYTE_NUM_MAX) { - return 1; + return true; } #else if ((regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT < SPI_FIFO_WORD_NUM_MAX) { - return 1; + return true; } #endif /* check busy bit */ regval = getreg32(reg_base + SPI_BUS_BUSY_OFFSET); if (regval) { - return 1; + return true; } - return 0; + return false; } int bflb_spi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) @@ -556,7 +556,7 @@ int bflb_spi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) break; default: - ret = -1; + ret = -EPERM; break; } diff --git a/drivers/lhal/src/bflb_timer.c b/drivers/lhal/src/bflb_timer.c index 15c3f7ce..c72e0a3b 100644 --- a/drivers/lhal/src/bflb_timer.c +++ b/drivers/lhal/src/bflb_timer.c @@ -5,7 +5,6 @@ void bflb_timer_init(struct bflb_device_s *dev, const struct bflb_timer_config_s { uint32_t regval; uint32_t reg_base; - uint8_t clk_source = 3; reg_base = dev->reg_base; @@ -14,24 +13,19 @@ void bflb_timer_init(struct bflb_device_s *dev, const struct bflb_timer_config_s regval &= ~(1 << (dev->idx + 1)); putreg32(regval, reg_base + TIMER_TCER_OFFSET); - /* Configure clock source */ - if (config->clock_source == BFLB_SYSTEM_CPU_CLK) { - clk_source = 0; - } else if (config->clock_source == BFLB_SYSTEM_XCLK) { - clk_source = 3; - } else if (config->clock_source == BFLB_SYSTEM_32K_CLK) { - clk_source = 1; - } else if (config->clock_source == BFLB_SYSTEM_1K_CLK) { - clk_source = 2; - } + /* Timer interrupr clear */ + bflb_timer_compint_clear(dev, TIMER_COMP_ID_0); + bflb_timer_compint_clear(dev, TIMER_COMP_ID_1); + bflb_timer_compint_clear(dev, TIMER_COMP_ID_2); + /* Configure clock source */ regval = getreg32(reg_base + TIMER_TCCR_OFFSET); if (dev->idx == 0) { regval &= ~TIMER_CS_0_MASK; - regval |= (clk_source << TIMER_CS_0_SHIFT); + regval |= (config->clock_source << TIMER_CS_0_SHIFT); } else { regval &= ~TIMER_CS_1_MASK; - regval |= (clk_source << TIMER_CS_1_SHIFT); + regval |= (config->clock_source << TIMER_CS_1_SHIFT); } putreg32(regval, reg_base + TIMER_TCCR_OFFSET); @@ -76,16 +70,28 @@ void bflb_timer_init(struct bflb_device_s *dev, const struct bflb_timer_config_s bflb_timer_set_compvalue(dev, TIMER_COMP_ID_0, config->comp0_val - 2); bflb_timer_set_compvalue(dev, TIMER_COMP_ID_1, config->comp1_val - 2); bflb_timer_set_compvalue(dev, TIMER_COMP_ID_2, 0xffffffff); - } else { + } else if (config->trigger_comp_id < TIMER_COMP_NONE) { bflb_timer_compint_mask(dev, TIMER_COMP_ID_0, false); bflb_timer_compint_mask(dev, TIMER_COMP_ID_1, false); bflb_timer_compint_mask(dev, TIMER_COMP_ID_2, false); bflb_timer_set_compvalue(dev, TIMER_COMP_ID_0, config->comp0_val - 2); bflb_timer_set_compvalue(dev, TIMER_COMP_ID_1, config->comp1_val - 2); bflb_timer_set_compvalue(dev, TIMER_COMP_ID_2, config->comp2_val - 2); + } else { + bflb_timer_compint_mask(dev, TIMER_COMP_ID_0, true); + bflb_timer_compint_mask(dev, TIMER_COMP_ID_1, true); + bflb_timer_compint_mask(dev, TIMER_COMP_ID_2, true); + bflb_timer_set_compvalue(dev, TIMER_COMP_ID_0, 0xffffffff); + bflb_timer_set_compvalue(dev, TIMER_COMP_ID_1, 0xffffffff); + bflb_timer_set_compvalue(dev, TIMER_COMP_ID_2, 0xffffffff); } } +void bflb_timer_deinit(struct bflb_device_s *dev) +{ + +} + void bflb_timer_start(struct bflb_device_s *dev) { uint32_t regval; @@ -185,4 +191,22 @@ void bflb_timer_compint_clear(struct bflb_device_s *dev, uint8_t cmp_no) regval = getreg32(reg_base + TIMER_TICR0_OFFSET + 4 * dev->idx); regval |= (1 << cmp_no); putreg32(regval, reg_base + TIMER_TICR0_OFFSET + 4 * dev->idx); -} \ No newline at end of file +} + +#if !defined(BL702) || !defined(BL602) +void bflb_timer_capture_init(struct bflb_device_s *dev, const struct bflb_timer_capture_config_s *config) +{ + uint32_t regval; + uint32_t reg_base; + + reg_base = dev->reg_base; + regval = getreg32(reg_base + TIMER_GPIO_OFFSET); + /* polarity: 1->neg, 0->pos */ + if (config->polarity == TIMER_CAPTURE_POLARITY_FALLING) { + regval |= (1 << (5 + dev->idx)); + } else { + regval &= ~(1 << (5 + dev->idx)); + } + putreg32(regval, reg_base + TIMER_GPIO_OFFSET); +} +#endif diff --git a/drivers/lhal/src/bflb_uart.c b/drivers/lhal/src/bflb_uart.c index 23e2ec92..b27ef3e7 100644 --- a/drivers/lhal/src/bflb_uart.c +++ b/drivers/lhal/src/bflb_uart.c @@ -72,25 +72,14 @@ void bflb_uart_init(struct bflb_device_s *dev, const struct bflb_uart_config_s * putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET); putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET); #if defined(BL602) - if (config->flow_ctrl & UART_FLOWCTRL_RTS) { - regval = getreg32(reg_base + UART_URX_CONFIG_OFFSET); - regval |= UART_CR_URX_RTS_SW_MODE; - putreg32(regval, reg_base + UART_URX_CONFIG_OFFSET); - } else { - regval = getreg32(reg_base + UART_URX_CONFIG_OFFSET); - regval &= ~UART_CR_URX_RTS_SW_MODE; - putreg32(regval, reg_base + UART_URX_CONFIG_OFFSET); - } + regval = getreg32(reg_base + UART_URX_CONFIG_OFFSET); + regval &= ~UART_CR_URX_RTS_SW_MODE; + putreg32(regval, reg_base + UART_URX_CONFIG_OFFSET); + #else - if (config->flow_ctrl & UART_FLOWCTRL_RTS) { - regval = getreg32(reg_base + UART_SW_MODE_OFFSET); - regval |= UART_CR_URX_RTS_SW_MODE; - putreg32(regval, reg_base + UART_SW_MODE_OFFSET); - } else { - regval = getreg32(reg_base + UART_SW_MODE_OFFSET); - regval &= ~UART_CR_URX_RTS_SW_MODE; - putreg32(regval, reg_base + UART_SW_MODE_OFFSET); - } + regval = getreg32(reg_base + UART_SW_MODE_OFFSET); + regval &= ~UART_CR_URX_RTS_SW_MODE; + putreg32(regval, reg_base + UART_SW_MODE_OFFSET); #endif regval = getreg32(reg_base + UART_DATA_CONFIG_OFFSET); regval &= ~UART_CR_UART_BIT_INV; @@ -113,8 +102,12 @@ void bflb_uart_init(struct bflb_device_s *dev, const struct bflb_uart_config_s * regval = getreg32(reg_base + UART_FIFO_CONFIG_0_OFFSET); regval |= UART_TX_FIFO_CLR; regval |= UART_RX_FIFO_CLR; + regval &= ~UART_DMA_TX_EN; + regval &= ~UART_DMA_RX_EN; putreg32(regval, reg_base + UART_FIFO_CONFIG_0_OFFSET); + putreg32(0xFFFFFFFF, reg_base + UART_INT_MASK_OFFSET); + /* Enable UART tx rx unit */ tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET); rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET); @@ -139,6 +132,36 @@ void bflb_uart_deinit(struct bflb_device_s *dev) putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET); } +void bflb_uart_enable(struct bflb_device_s *dev) +{ + uint32_t reg_base; + uint32_t tx_cfg; + uint32_t rx_cfg; + + reg_base = dev->reg_base; + tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET); + rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET); + tx_cfg |= UART_CR_UTX_EN; + rx_cfg |= UART_CR_URX_EN; + putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET); + putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET); +} + +void bflb_uart_disable(struct bflb_device_s *dev) +{ + uint32_t reg_base; + uint32_t tx_cfg; + uint32_t rx_cfg; + + reg_base = dev->reg_base; + tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET); + rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET); + tx_cfg &= ~UART_CR_UTX_EN; + rx_cfg &= ~UART_CR_URX_EN; + putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET); + putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET); +} + void bflb_uart_link_txdma(struct bflb_device_s *dev, bool enable) { uint32_t reg_base; @@ -192,6 +215,28 @@ int bflb_uart_getchar(struct bflb_device_s *dev) return ch; } +void bflb_uart_put(struct bflb_device_s *dev, uint8_t *data, uint32_t len) +{ + for (uint32_t i = 0; i < len; i++) { + bflb_uart_putchar(dev, data[i]); + } +} + +int bflb_uart_get(struct bflb_device_s *dev, uint8_t *data, uint32_t len) +{ + int ch = -1; + uint32_t count = 0; + + while (count < len) { + if ((ch = bflb_uart_getchar(dev)) < 0) { + break; + } + data[count] = ch; + count++; + } + return count; +} + bool bflb_uart_txready(struct bflb_device_s *dev) { uint32_t reg_base; @@ -301,8 +346,9 @@ void bflb_uart_int_clear(struct bflb_device_s *dev, uint32_t int_clear) putreg32(int_clear, reg_base + UART_INT_CLEAR_OFFSET); } -void bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) +int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) { + int ret = 0; uint32_t reg_base; uint32_t tmp; uint32_t tx_tmp; @@ -401,13 +447,11 @@ void bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) case UART_CMD_GET_TX_FIFO_CNT: /* Get tx fifo count */ - *(uint32_t *)arg = getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK; - break; + return (getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) >> UART_TX_FIFO_CNT_SHIFT; case UART_CMD_GET_RX_FIFO_CNT: /* Get rx fifo count */ - *(uint32_t *)arg = (getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_RX_FIFO_CNT_MASK) >> UART_RX_FIFO_CNT_SHIFT; - break; + return (getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_RX_FIFO_CNT_MASK) >> UART_RX_FIFO_CNT_SHIFT; case UART_CMD_SET_AUTO_BAUD: /* Set auto baudrate detection */ @@ -432,12 +476,11 @@ void bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) case UART_CMD_GET_AUTO_BAUD: /* Get auto baudrate detection count value */ tmp = getreg32(reg_base + UART_STS_URX_ABR_PRD_OFFSET); - if (*(uint32_t *)arg == UART_AUTO_BAUD_START) { - *((uint32_t *)arg + 1) = tmp & UART_STS_URX_ABR_PRD_START_MASK; + if (arg == UART_AUTO_BAUD_START) { + return (tmp & UART_STS_URX_ABR_PRD_START_MASK); } else { - *((uint32_t *)arg + 1) = (tmp & UART_STS_URX_ABR_PRD_0X55_MASK) >> UART_STS_URX_ABR_PRD_0X55_SHIFT; + return ((tmp & UART_STS_URX_ABR_PRD_0X55_MASK) >> UART_STS_URX_ABR_PRD_0X55_SHIFT); } - break; #if !defined(BL602) case UART_CMD_SET_BREAK_VALUE: /* Set lin mode break value */ @@ -498,7 +541,7 @@ void bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) putreg32(tx_tmp, reg_base + UART_UTX_RS485_CFG_OFFSET); break; - case UART_CMD_SET_TX_RS485_POL: + case UART_CMD_SET_TX_RS485_POLARITY: /* Set tx rs485 de pin polarity */ tx_tmp = getreg32(reg_base + UART_UTX_RS485_CFG_OFFSET); tx_tmp &= ~UART_CR_UTX_RS485_POL; @@ -510,7 +553,7 @@ void bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) putreg32(tx_tmp, reg_base + UART_UTX_RS485_CFG_OFFSET); break; - case UART_CMD_SET_ABR_PW_VALUE: + case UART_CMD_SET_ABR_ALLOWABLE_ERROR: /* Set auto baudrate detection mode pulse-width tolerance value for codeword 0x55 */ rx_tmp = getreg32(reg_base + UART_URX_ABR_PW_TOL_OFFSET); rx_tmp &= ~UART_CR_URX_ABR_PW_TOL_MASK; @@ -519,7 +562,33 @@ void bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg) putreg32(rx_tmp, reg_base + UART_URX_ABR_PW_TOL_OFFSET); break; #endif + case UART_CMD_SET_SW_RTS_CONTROL: +#if defined(BL602) + if (arg) { + rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET); + rx_tmp |= UART_CR_URX_RTS_SW_MODE; + putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET); + } else { + rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET); + rx_tmp &= ~UART_CR_URX_RTS_SW_MODE; + putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET); + } +#else + if (arg) { + rx_tmp = getreg32(reg_base + UART_SW_MODE_OFFSET); + rx_tmp |= UART_CR_URX_RTS_SW_MODE; + putreg32(rx_tmp, reg_base + UART_SW_MODE_OFFSET); + + } else { + rx_tmp = getreg32(reg_base + UART_SW_MODE_OFFSET); + rx_tmp &= ~UART_CR_URX_RTS_SW_MODE; + putreg32(rx_tmp, reg_base + UART_SW_MODE_OFFSET); + } +#endif + break; default: + ret = -EPERM; break; } + return ret; } diff --git a/drivers/lhal/src/bflb_usb_v2.c b/drivers/lhal/src/bflb_usb_v2.c index c12d83c2..7b2e4824 100644 --- a/drivers/lhal/src/bflb_usb_v2.c +++ b/drivers/lhal/src/bflb_usb_v2.c @@ -1,10 +1,11 @@ #include "bflb_core.h" -#include "bflb_mtimer.h" #include "bflb_irq.h" #include "usbd_core.h" #include "usbh_core.h" #include "hardware/usb_v2_reg.h" +// #define CONFIG_USB_PINGPONG_ENABLE + #define BLFB_USB_BASE ((uint32_t)0x20072000) #define BFLB_PDS_BASE ((uint32_t)0x2000e000) @@ -673,6 +674,22 @@ int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg) #else if (ep_cfg->ep_mps > 512) { bflb_usb_set_ep_fifomap(1, USB_FIFO_F0); + + bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F2, 1, USB_FIFO_DIR_BID); + bflb_usb_set_fifo_epmap(USB_FIFO_F3, 1, USB_FIFO_DIR_BID); + + if (ep_idx == 1) { + bflb_usb_fifo_config(USB_FIFO_F0, ep_cfg->ep_type, 1024, 2, true); + bflb_usb_fifo_config(USB_FIFO_F1, ep_cfg->ep_type, 1024, 2, false); + bflb_usb_fifo_config(USB_FIFO_F2, ep_cfg->ep_type, 1024, 2, false); + bflb_usb_fifo_config(USB_FIFO_F3, ep_cfg->ep_type, 1024, 2, false); + } else { + return -1; + } + } else { + bflb_usb_set_ep_fifomap(1, USB_FIFO_F0); bflb_usb_set_ep_fifomap(2, USB_FIFO_F2); bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID); @@ -689,22 +706,6 @@ int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg) } else { return -1; } - } else { - bflb_usb_set_ep_fifomap(1, USB_FIFO_F0); - - bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID); - bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID); - bflb_usb_set_fifo_epmap(USB_FIFO_F2, 1, USB_FIFO_DIR_BID); - bflb_usb_set_fifo_epmap(USB_FIFO_F3, 1, USB_FIFO_DIR_BID); - - if (ep_idx == 1) { - bflb_usb_fifo_config(USB_FIFO_F0, ep_cfg->ep_type, 1024, 2, true); - bflb_usb_fifo_config(USB_FIFO_F1, ep_cfg->ep_type, 1024, 2, false); - bflb_usb_fifo_config(USB_FIFO_F2, ep_cfg->ep_type, 1024, 2, false); - bflb_usb_fifo_config(USB_FIFO_F3, ep_cfg->ep_type, 1024, 2, false); - } else { - return -1; - } } #endif regval = getreg32(BLFB_USB_BASE + USB_DEV_ADR_OFFSET); diff --git a/drivers/lhal/src/bflb_wdg.c b/drivers/lhal/src/bflb_wdg.c index 9c887ec8..da1bbd93 100644 --- a/drivers/lhal/src/bflb_wdg.c +++ b/drivers/lhal/src/bflb_wdg.c @@ -6,7 +6,6 @@ void bflb_wdg_init(struct bflb_device_s *dev, const struct bflb_wdg_config_s *co { uint32_t regval; uint32_t reg_base; - uint8_t clk_source; reg_base = dev->reg_base; @@ -23,19 +22,9 @@ void bflb_wdg_init(struct bflb_device_s *dev, const struct bflb_wdg_config_s *co putreg32(regval, reg_base + TIMER_WMER_OFFSET); /* Configure clock source */ - if (config->clock_source == BFLB_SYSTEM_CPU_CLK) { - clk_source = 0; - } else if (config->clock_source == BFLB_SYSTEM_XCLK) { - clk_source = 3; - } else if (config->clock_source == BFLB_SYSTEM_32K_CLK) { - clk_source = 1; - } else { - clk_source = 2; - } - regval = getreg32(reg_base + TIMER_TCCR_OFFSET); regval &= ~TIMER_CS_WDT_MASK; - regval |= (clk_source << TIMER_CS_WDT_SHIFT); + regval |= (config->clock_source << TIMER_CS_WDT_SHIFT); putreg32(regval, reg_base + TIMER_TCCR_OFFSET); /* Configure clock div */ diff --git a/drivers/lhal/src/pka/libpka.a b/drivers/lhal/src/pka/libpka.a new file mode 100644 index 00000000..82fee0e8 Binary files /dev/null and b/drivers/lhal/src/pka/libpka.a differ diff --git a/examples/peripherals/timer/CMakeLists.txt b/examples/peripherals/cks/cks_dma/CMakeLists.txt similarity index 89% rename from examples/peripherals/timer/CMakeLists.txt rename to examples/peripherals/cks/cks_dma/CMakeLists.txt index 86cfea3b..d69e7970 100644 --- a/examples/peripherals/timer/CMakeLists.txt +++ b/examples/peripherals/cks/cks_dma/CMakeLists.txt @@ -6,4 +6,4 @@ find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) sdk_set_main_file(main.c) -project(timer) +project(cks_dma) diff --git a/examples/peripherals/cks/cks_dma/Makefile b/examples/peripherals/cks/cks_dma/Makefile new file mode 100644 index 00000000..93f8cb7b --- /dev/null +++ b/examples/peripherals/cks/cks_dma/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl628 +BOARD ?= bl628dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/peripherals/cks/cks_dma/main.c b/examples/peripherals/cks/cks_dma/main.c new file mode 100644 index 00000000..bfdcc211 --- /dev/null +++ b/examples/peripherals/cks/cks_dma/main.c @@ -0,0 +1,152 @@ +#include "board.h" +#include "bflb_cks.h" +#include "bflb_dma.h" +#include "bflb_mtimer.h" +#include "bl628_memorymap.h" +#include "bflb_core.h" + +#define DATA_LEN 1024 + +static volatile uint8_t dma_tc_flag0 = 0; +struct bflb_device_s *cks; +struct bflb_device_s *dma0_ch0; + +void dma0_ch0_isr(void *arg) +{ + dma_tc_flag0++; + printf("tc done\r\n"); +} + +uint16_t sw_chksum(uint8_t *data, uint32_t len) { + uint32_t sum = 0; + uint16_t chksum = 0; + uint32_t size = len; + + if (len % 2 == 1) { + size=len-1; + sum += data[size]; + } + + for (uint32_t i = 0; i < size; i = i + 2) { + sum += ((uint32_t)data[i]); + sum += ((uint32_t)data[i + 1] << 8); + } + + while (sum >> 16) { + sum = (sum >> 16) + (sum & 0x0000FFFF); + } + + chksum = (uint16_t)sum; + return ~chksum; +} + +uint16_t get_cks_with_dma(uint8_t* data,uint32_t length) +{ + uint16_t checksum = 0; + + struct bflb_dma_channel_lli_pool_s lli[20]; /* max trasnfer size 4064 * 20 */ + struct bflb_dma_channel_lli_transfer_s transfers[1]; + + transfers[0].src_addr = (uint32_t)data; + transfers[0].dst_addr = (uint32_t)(CKS_BASE+0x4); + transfers[0].nbytes = length; + + bflb_dma_channel_lli_reload(dma0_ch0, lli, 20, transfers, 1); + bflb_dma_channel_start(dma0_ch0); + + while(dma_tc_flag0 == 0) { + } + dma_tc_flag0 = 0; + + checksum = bflb_cks_compute(cks, data, 0); + + return checksum; +} + +static void test_case1(void){ + uint16_t dma_cks = 0; + uint16_t hw_cks = 0; + uint16_t sw_cks = 0; + uint32_t time = 0, i; + struct bflb_dma_channel_config_s config; + + static uint32_t data_src1[DATA_LEN/4]; + + for(i = 0;i < DATA_LEN; i++){ + ((uint8_t *)data_src1)[i] = i&0xff; + } + + time = (unsigned int)bflb_mtimer_get_time_us(); + + sw_cks = sw_chksum((uint8_t *)data_src1, sizeof(data_src1)); + + printf("software checksum time=%ldus\r\n", (unsigned int)bflb_mtimer_get_time_us() - time); + + printf("sw_cks is %04x\r\n", sw_cks); + + bflb_cks_reset(cks); + bflb_cks_set_endian(cks, CKS_BIG_ENDIAN); + + time = (unsigned int)bflb_mtimer_get_time_us(); + + hw_cks = bflb_cks_compute(cks, (uint8_t *)data_src1, sizeof(data_src1)); + + printf("hardware checksum time=%ldus\r\n", (unsigned int)bflb_mtimer_get_time_us() - time); + + printf("hw_cks is %04x\r\n", hw_cks); + + bflb_cks_reset(cks); + bflb_cks_set_endian(cks, CKS_BIG_ENDIAN); + + printf("\r\ndma case 1:\n"); + + config.direction = DMA_MEMORY_TO_MEMORY; + config.src_req = 0; + config.dst_req = 0; + config.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE; + config.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE; + config.src_burst_count = DMA_BURST_INCR1; + config.dst_burst_count = DMA_BURST_INCR1; + config.src_width = DMA_DATA_WIDTH_8BIT; + config.dst_width = DMA_DATA_WIDTH_8BIT; + bflb_dma_channel_init(dma0_ch0, &config); + bflb_dma_channel_irq_attach(dma0_ch0, dma0_ch0_isr, NULL); + + time = (unsigned int)bflb_mtimer_get_time_us(); + + dma_cks = get_cks_with_dma((uint8_t *)data_src1, sizeof(data_src1)); + printf("dma checksum time=%ldus\r\n", (unsigned int)bflb_mtimer_get_time_us() - time); + printf("dma_cks is %04x\r\n", dma_cks); + + bflb_cks_reset(cks); + bflb_cks_set_endian(cks, CKS_BIG_ENDIAN); + + printf("\r\ndma case 2:\n"); + config.src_width = DMA_DATA_WIDTH_32BIT; + config.src_burst_count = DMA_BURST_INCR4; + config.dst_width = DMA_DATA_WIDTH_8BIT; + config.dst_burst_count = DMA_BURST_INCR16; + time = (unsigned int)bflb_mtimer_get_time_us(); + + dma_cks = get_cks_with_dma((uint8_t *)data_src1, sizeof(data_src1)); + printf("dma checksum time=%ldus\r\n", (unsigned int)bflb_mtimer_get_time_us() - time); + printf("dma_cks is %04x\r\n", dma_cks); +} + +/* main */ +int main(void) +{ + board_init(); + + printf("CKS dma case:\r\n"); + + cks = bflb_device_get_by_name("cks"); + dma0_ch0 = bflb_device_get_by_name("dma0_ch0"); + + test_case1(); + + printf("\r\nend\r\n"); + + while (1) { + } +} diff --git a/examples/peripherals/timer/proj.conf b/examples/peripherals/cks/cks_dma/proj.conf similarity index 100% rename from examples/peripherals/timer/proj.conf rename to examples/peripherals/cks/cks_dma/proj.conf diff --git a/examples/peripherals/cks/cks_normal/CMakeLists.txt b/examples/peripherals/cks/cks_normal/CMakeLists.txt new file mode 100644 index 00000000..0007ba88 --- /dev/null +++ b/examples/peripherals/cks/cks_normal/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(cks_normal) diff --git a/examples/peripherals/cks/cks_normal/Makefile b/examples/peripherals/cks/cks_normal/Makefile new file mode 100644 index 00000000..93f8cb7b --- /dev/null +++ b/examples/peripherals/cks/cks_normal/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl628 +BOARD ?= bl628dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/peripherals/cks/cks_normal/main.c b/examples/peripherals/cks/cks_normal/main.c new file mode 100644 index 00000000..709fd4d3 --- /dev/null +++ b/examples/peripherals/cks/cks_normal/main.c @@ -0,0 +1,260 @@ +#include "board.h" +#include "bflb_cks.h" +#include "bflb_mtimer.h" +#include "bflb_core.h" + +#define USER_UNUSED(a) ((void)(a)) + +struct bflb_device_s *cks; + +static void test_case1(struct bflb_device_s *dev) { + /*case from wiki: https://en.wikipedia.org/wiki/IPv4_header_checksum*/ + static const uint8_t data_src1[] = {0x45, 0x00, 0x00, 0x73, 0x00, 0x00, 0x40, + 0x00, 0x40, 0x11, 0x00, 0x00, 0xc0, 0xa8, + 0x00, 0x01, 0xc0, 0xa8, 0x00, 0xc7}; + static const uint8_t data_src1_cks[] = {0xB8, 0x61}; + uint16_t cks; + USER_UNUSED(cks); + USER_UNUSED(data_src1_cks); + + bflb_cks_reset(dev); + bflb_cks_set_endian(dev, CKS_LITTLE_ENDIAN); + cks = bflb_cks_compute(dev, (uint8_t *)data_src1, sizeof(data_src1)); + + if (cks != (data_src1_cks[0] << 8 | data_src1_cks[1])) { + printf("Error! CKS result with LE is %04x, should be %02x%02x\r\n", cks, data_src1_cks[1], data_src1_cks[0]); + } else { + printf("Pass\r\n"); + } + + bflb_cks_reset(dev); + bflb_cks_set_endian(dev, CKS_BIG_ENDIAN); + cks = bflb_cks_compute(dev, (uint8_t *)data_src1, sizeof(data_src1)); + + if (cks != (data_src1_cks[1] << 8 | data_src1_cks[0])) { + printf("Error! CKS result with BE is %04x, should be %02x%02x\r\n", cks, data_src1_cks[1], data_src1_cks[0]); + } else { + printf("Pass\r\n"); + } +} + +static void test_case2(struct bflb_device_s *dev) { + uint16_t data_segment_one = 0x3F1F; + int i; + uint32_t checksum; + uint16_t cks; + uint8_t data; + + bflb_cks_reset(dev); + bflb_cks_set_endian(dev, CKS_LITTLE_ENDIAN); + checksum = 0; + for (i = 0; i < 1; i++) { + checksum += data_segment_one; + data = data_segment_one & 0xff; + cks = bflb_cks_compute(dev, &data, 1); + data = data_segment_one >> 8 & 0xff; + cks = bflb_cks_compute(dev, &data, 1); + } + while (checksum >> 16) { + checksum = (checksum >> 16) + (checksum & 0xFFFF); + } + + printf("CKS LE result is %04x, %04x\r\n", cks, (uint16_t)~checksum); + + bflb_cks_reset(dev); + bflb_cks_set_endian(dev, CKS_BIG_ENDIAN); + checksum = 0; + for (i = 0; i < 1; i++) { + checksum += data_segment_one; + data = data_segment_one & 0xff; + cks = bflb_cks_compute(dev, &data, 1); + data = data_segment_one >> 8 & 0xff; + cks = bflb_cks_compute(dev, &data, 1); + } + while (checksum >> 16) { + checksum = (checksum >> 16) + (checksum & 0xFFFF); + } + + printf("CKS BE result is %04x, %04x\r\n", cks, (uint16_t)~checksum); + if (cks == ((uint16_t)~checksum)) { + printf("====== Success %04X Checksum=====\r\n", cks); + } else { + printf("====== Failed %04X Checksum======\r\n", cks); + } +} + +static void test_case3(struct bflb_device_s *dev) { + uint16_t data_segment_one = 0x3F1F; + int i; + uint32_t checksum; + uint16_t cks; + uint8_t data; + + bflb_cks_reset(dev); + bflb_cks_set_endian(dev, CKS_LITTLE_ENDIAN); + checksum = 0; + for (i = 0; i < 1000; i++) { + checksum += data_segment_one; + data = data_segment_one & 0xff; + cks = bflb_cks_compute(dev, &data, 1); + data = data_segment_one >> 8 & 0xff; + cks = bflb_cks_compute(dev, &data, 1); + } + while (checksum >> 16) { + checksum = (checksum >> 16) + (checksum & 0xFFFF); + } + + printf("CKS LE result is %04x, %04x\r\n", cks, (uint16_t)~checksum); + + bflb_cks_reset(dev); + bflb_cks_set_endian(dev, CKS_BIG_ENDIAN); + checksum = 0; + for (i = 0; i < 1000; i++) { + checksum += data_segment_one; + data = data_segment_one & 0xff; + cks = bflb_cks_compute(dev, &data, 1); + data = data_segment_one >> 8 & 0xff; + cks = bflb_cks_compute(dev, &data, 1); + } + while (checksum >> 16) { + checksum = (checksum >> 16) + (checksum & 0xFFFF); + } + + printf("CKS BE result is %04x, %04x\r\n", cks, (uint16_t)~checksum); + if (cks == ((uint16_t)~checksum)) { + printf("====== Success %04X Checksum=====\r\n", cks); + } else { + printf("====== Failed %04X Checksum======\r\n", cks); + } +} + +static void test_case4(struct bflb_device_s *dev) { + uint16_t data_segment_one = 0x3F1F; + uint8_t data_segment_two = 0xa1; + int i; + uint32_t checksum; + uint16_t cks; + uint8_t data; + + bflb_cks_reset(dev); + bflb_cks_set_endian(dev, CKS_LITTLE_ENDIAN); + checksum = 0; + for (i = 0; i < 1; i++) { + checksum += data_segment_one; + data = data_segment_one & 0xff; + cks = bflb_cks_compute(dev, &data, 1); + data = data_segment_one >> 8 & 0xff; + cks = bflb_cks_compute(dev, &data, 1); + } + checksum += data_segment_two; + while (checksum >> 16) { + checksum = (checksum >> 16) + (checksum & 0xFFFF); + } + cks = bflb_cks_compute(dev, &data_segment_two, 1); + + printf("CKS LE result is %04x, %04x\r\n", cks, (uint16_t)~checksum); + + bflb_cks_reset(dev); + bflb_cks_set_endian(dev, CKS_BIG_ENDIAN); + checksum = 0; + for (i = 0; i < 1; i++) { + checksum += data_segment_one; + data = data_segment_one & 0xff; + cks = bflb_cks_compute(dev, &data, 1); + data = data_segment_one >> 8 & 0xff; + cks = bflb_cks_compute(dev, &data, 1); + } + checksum += data_segment_two; + while (checksum >> 16) { + checksum = (checksum >> 16) + (checksum & 0xFFFF); + } + cks = bflb_cks_compute(dev, &data_segment_two, 1); + + printf("CKS BE result is %04x, %04x\r\n", cks, (uint16_t)~checksum); + if (cks == ((uint16_t)~checksum)) { + printf("====== Success %04X Checksum=====\r\n", cks); + } else { + printf("====== Failed %04X Checksum======\r\n", cks); + } +} + +uint16_t sw_chksum(uint8_t *data, uint32_t len) { + uint32_t sum = 0; + uint16_t chksum = 0; + uint32_t size = len; + + if (len % 2 == 1) { + size=len-1; + sum += data[size]; + } + + for (uint32_t i = 0; i < size; i = i + 2) { + sum += ((uint32_t)data[i]); + sum += ((uint32_t)data[i + 1] << 8); + } + + while (sum >> 16) { + sum = (sum >> 16) + (sum & 0x0000FFFF); + } + + chksum = (uint16_t)sum; + return ~chksum; +} + +static void test_case5(struct bflb_device_s *dev) { + uint16_t sw_cks = 0; + uint16_t hw_cks = 0; + uint32_t time = 0; + + static const uint8_t data_src1[] = {0x45, 0x00, 0x00, 0x73, 0x00, 0x00, 0x40, + 0x00, 0x40, 0x11, 0x00, 0x00, 0xc0, 0xa8, + 0x00, 0x01, 0xc0, 0xa8, 0x00, 0xc7}; + time = (unsigned int)bflb_mtimer_get_time_us(); + + sw_cks = sw_chksum((uint8_t *)data_src1, sizeof(data_src1)); + + printf("software checksum time=%ldus\r\n", (unsigned int)bflb_mtimer_get_time_us() - time); + + printf("sw_cks is %04x\r\n", sw_cks); + + bflb_cks_reset(dev); + bflb_cks_set_endian(dev, CKS_BIG_ENDIAN); + + time = (unsigned int)bflb_mtimer_get_time_us(); + + hw_cks = bflb_cks_compute(dev, (uint8_t *)data_src1, sizeof(data_src1)); + + printf("hardware checksum time=%ldus\r\n", (unsigned int)bflb_mtimer_get_time_us() - time); + + printf("hw_cks is %04x\r\n", hw_cks); + + if (sw_cks != hw_cks) { + printf("Error!\r\n"); + } +} + +/* main */ +int main(void) +{ + board_init(); + + printf("CKS normal case:\r\n"); + + cks = bflb_device_get_by_name("cks"); + + printf("\r\n--->>> case1 test\r\n"); + test_case1(cks); + printf("\r\n--->>> case2 test\r\n"); + test_case2(cks); + printf("\r\n--->>> case3 test\r\n"); + test_case3(cks); + printf("\r\n--->>> case4 test\r\n"); + test_case4(cks); + printf("\r\n--->>> case5 test\r\n"); + test_case5(cks); + + printf("\r\nend\r\n"); + + while (1) { + } +} diff --git a/examples/peripherals/cks/cks_normal/proj.conf b/examples/peripherals/cks/cks_normal/proj.conf new file mode 100644 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/cks/cks_normal/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/i2c/i2c_10_bit/CMakeLists.txt b/examples/peripherals/i2c/i2c_10_bit/CMakeLists.txt new file mode 100644 index 00000000..4c90c624 --- /dev/null +++ b/examples/peripherals/i2c/i2c_10_bit/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(i2c_10_bit) diff --git a/examples/peripherals/timer/Makefile b/examples/peripherals/i2c/i2c_10_bit/Makefile similarity index 82% rename from examples/peripherals/timer/Makefile rename to examples/peripherals/i2c/i2c_10_bit/Makefile index 9b01b7fe..44367c02 100644 --- a/examples/peripherals/timer/Makefile +++ b/examples/peripherals/i2c/i2c_10_bit/Makefile @@ -1,5 +1,5 @@ SDK_DEMO_PATH ?= . -BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../.. +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. export BL_SDK_BASE diff --git a/examples/peripherals/i2c/i2c_10_bit/main.c b/examples/peripherals/i2c/i2c_10_bit/main.c new file mode 100644 index 00000000..1872c352 --- /dev/null +++ b/examples/peripherals/i2c/i2c_10_bit/main.c @@ -0,0 +1,49 @@ +#include "bflb_mtimer.h" +#include "bflb_i2c.h" +#include "board.h" + +#define I2C_10BIT_SLAVE_ADDR 0x355 +#define I2C_10BIT_TRANSFER_LENGTH 32 + +static struct bflb_device_s *i2c0; + +int main(void) +{ + struct bflb_i2c_msg_s msgs[2]; + uint8_t subaddr[2] = { 0x00, 0x04}; + uint8_t write_data[I2C_10BIT_TRANSFER_LENGTH]; + + board_init(); + board_i2c0_gpio_init(); + + i2c0 = bflb_device_get_by_name("i2c0"); + + bflb_i2c_init(i2c0, 400000); + + /* Write buffer init */ + write_data[0] = 0x55; + write_data[1] = 0x11; + write_data[2] = 0x22; + for (size_t i = 3; i < I2C_10BIT_TRANSFER_LENGTH; i++) { + write_data[i] = i; + } + + /* Write data */ + msgs[0].addr = I2C_10BIT_SLAVE_ADDR; + msgs[0].flags = I2C_M_NOSTOP | I2C_M_TEN; + msgs[0].buffer = subaddr; + msgs[0].length = 2; + + msgs[1].addr = I2C_10BIT_SLAVE_ADDR; + msgs[1].flags = 0; + msgs[1].buffer = write_data; + msgs[1].length = I2C_10BIT_TRANSFER_LENGTH; + + bflb_i2c_transfer(i2c0, msgs, 2); + printf("write over, check slave and wave\r\n"); + + printf("end\r\n"); + + while(1){ + } +} diff --git a/examples/peripherals/i2c/i2c_10_bit/proj.conf b/examples/peripherals/i2c/i2c_10_bit/proj.conf new file mode 100644 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/i2c/i2c_10_bit/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/i2c/i2c_eeprom/main.c b/examples/peripherals/i2c/i2c_eeprom/main.c index f822376b..25c3a06b 100644 --- a/examples/peripherals/i2c/i2c_eeprom/main.c +++ b/examples/peripherals/i2c/i2c_eeprom/main.c @@ -2,25 +2,32 @@ #include "bflb_i2c.h" #include "board.h" +#define EEPROM_TRANSFER_LENGTH 32 +#define EEPROM_SELECT_PAGE0 (0 << 5) + +static struct bflb_device_s *i2c0; + int main(void) { + struct bflb_i2c_msg_s msgs[2]; + uint8_t subaddr[2] = { 0x00, EEPROM_SELECT_PAGE0}; + uint8_t write_data[256]; + uint8_t read_data[256]; + board_init(); board_i2c0_gpio_init(); - struct bflb_device_s *i2c0; i2c0 = bflb_device_get_by_name("i2c0"); bflb_i2c_init(i2c0, 400000); - struct bflb_i2c_msg_s msgs[2]; - uint8_t subaddr[2] = { 0x00, 0x00 }; - uint8_t write_data[8]; - uint8_t read_data[8]; - - for (size_t i = 0; i < 8; i++) { + /* Write and read buffer init */ + for (size_t i = 0; i < 256; i++) { write_data[i] = i; + read_data[i] = 0; } + /* Write page 0 */ msgs[0].addr = 0x50; msgs[0].flags = I2C_M_NOSTOP; msgs[0].buffer = subaddr; @@ -29,27 +36,30 @@ int main(void) msgs[1].addr = 0x50; msgs[1].flags = 0; msgs[1].buffer = write_data; - msgs[1].length = 8; + msgs[1].length = EEPROM_TRANSFER_LENGTH; bflb_i2c_transfer(i2c0, msgs, 2); printf("write over\r\n"); - bflb_mtimer_delay_ms(200); + bflb_mtimer_delay_ms(100); + /* Read page 0 */ msgs[1].addr = 0x50; msgs[1].flags = I2C_M_READ; msgs[1].buffer = read_data; - msgs[1].length = 8; + msgs[1].length = EEPROM_TRANSFER_LENGTH; bflb_i2c_transfer(i2c0, msgs, 2); printf("read over\r\n"); - for (uint8_t i = 0; i < 8; i++) { + bflb_mtimer_delay_ms(100); + + /* Check read data */ + for (uint8_t i = 0; i < EEPROM_TRANSFER_LENGTH; i++) { if (write_data[i] != read_data[i]) { - printf("check fail\r\n"); - while (1) { - } + printf("check fail, %d write: %02x, read: %02x\r\n", i, write_data[i], read_data[i]); } } - while (1) { - printf("helloworld\r\n"); - bflb_mtimer_delay_ms(2000); + printf("check over\r\n"); + printf("end\r\n"); + + while(1){ } } diff --git a/examples/peripherals/i2c/i2c_eeprom_dma/CMakeLists.txt b/examples/peripherals/i2c/i2c_eeprom_dma/CMakeLists.txt new file mode 100644 index 00000000..7226f71f --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom_dma/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(i2c_eeprom_dma) diff --git a/examples/peripherals/i2c/i2c_eeprom_dma/Makefile b/examples/peripherals/i2c/i2c_eeprom_dma/Makefile new file mode 100644 index 00000000..44367c02 --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom_dma/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/peripherals/i2c/i2c_eeprom_dma/main.c b/examples/peripherals/i2c/i2c_eeprom_dma/main.c new file mode 100644 index 00000000..0a1ee6f0 --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom_dma/main.c @@ -0,0 +1,150 @@ +#include "bflb_mtimer.h" +#include "bflb_i2c.h" +#include "bflb_dma.h" +#include "board.h" + +#define EEPROM_TRANSFER_LENGTH 32 +#define EEPROM_SELECT_PAGE0 (0 << 5) + +struct bflb_device_s *i2c0; +struct bflb_device_s *dma0_ch0; +struct bflb_device_s *dma0_ch1; + +static ATTR_NOCACHE_RAM_SECTION uint32_t send_buffer[8]; +static ATTR_NOCACHE_RAM_SECTION uint32_t receive_buffer[8]; +static volatile uint32_t dma_tc_flag0 = 0; +static volatile uint32_t dma_tc_flag1 = 0; + +void dma0_ch0_isr(void *arg) +{ + dma_tc_flag0++; + printf("Send done\r\n"); +} + +void dma0_ch1_isr(void *arg) +{ + dma_tc_flag1++; + printf("Receive done\r\n"); +} + +int main(void) +{ + struct bflb_i2c_msg_s msgs[2]; + uint8_t subaddr[2] = { 0x00, EEPROM_SELECT_PAGE0}; + + board_init(); + board_i2c0_gpio_init(); + + /* Send and receive buffer init */ + for (size_t i = 0; i < 32; i++) { + ((uint8_t *)send_buffer)[i] = i; + ((uint8_t *)receive_buffer)[i] = 0; + } + + i2c0 = bflb_device_get_by_name("i2c0"); + + bflb_i2c_init(i2c0, 400000); + bflb_i2c_link_txdma(i2c0, true); + bflb_i2c_link_rxdma(i2c0, true); + + /* Write page 0 */ + dma0_ch0 = bflb_device_get_by_name("dma0_ch0"); + + struct bflb_dma_channel_config_s tx_config; + + tx_config.direction = DMA_MEMORY_TO_PERIPH; + tx_config.src_req = DMA_REQUEST_NONE; + tx_config.dst_req = DMA_REQUEST_I2C0_TX; + tx_config.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE; + tx_config.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE; + tx_config.src_burst_count = DMA_BURST_INCR1; + tx_config.dst_burst_count = DMA_BURST_INCR1; + tx_config.src_width = DMA_DATA_WIDTH_32BIT; + tx_config.dst_width = DMA_DATA_WIDTH_32BIT; + bflb_dma_channel_init(dma0_ch0, &tx_config); + + bflb_dma_channel_irq_attach(dma0_ch0, dma0_ch0_isr, NULL); + + struct bflb_dma_channel_lli_pool_s tx_llipool[20]; /* max trasnfer size 4064 * 20 */ + struct bflb_dma_channel_lli_transfer_s tx_transfers[1]; + tx_transfers[0].src_addr = (uint32_t)send_buffer; + tx_transfers[0].dst_addr = (uint32_t)DMA_ADDR_I2C0_TDR; + tx_transfers[0].nbytes = 32; + bflb_dma_channel_lli_reload(dma0_ch0, tx_llipool, 20, tx_transfers, 1); + + msgs[0].addr = 0x50; + msgs[0].flags = I2C_M_NOSTOP; + msgs[0].buffer = subaddr; + msgs[0].length = 2; + + msgs[1].addr = 0x50; + msgs[1].flags = I2C_M_DMA; + msgs[1].buffer = NULL; + msgs[1].length = 32; + bflb_i2c_transfer(i2c0, msgs, 2); + + bflb_dma_channel_start(dma0_ch0); + + while (dma_tc_flag0 == 0) { + } + while ((bflb_i2c_get_intstatus(i2c0) & I2C_INT_END) == 0) { + } + bflb_i2c_deinit(i2c0); + + printf("write over\r\n"); + bflb_mtimer_delay_ms(100); + + /* Read page 0 */ + dma0_ch1 = bflb_device_get_by_name("dma0_ch1"); + + struct bflb_dma_channel_config_s rx_config; + + rx_config.direction = DMA_PERIPH_TO_MEMORY; + rx_config.src_req = DMA_REQUEST_I2C0_RX; + rx_config.dst_req = DMA_REQUEST_NONE; + rx_config.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE; + rx_config.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE; + rx_config.src_burst_count = DMA_BURST_INCR1; + rx_config.dst_burst_count = DMA_BURST_INCR1; + rx_config.src_width = DMA_DATA_WIDTH_32BIT; + rx_config.dst_width = DMA_DATA_WIDTH_32BIT; + bflb_dma_channel_init(dma0_ch1, &rx_config); + + bflb_dma_channel_irq_attach(dma0_ch1, dma0_ch1_isr, NULL); + + struct bflb_dma_channel_lli_pool_s rx_llipool[20]; + struct bflb_dma_channel_lli_transfer_s rx_transfers[1]; + rx_transfers[0].src_addr = (uint32_t)DMA_ADDR_I2C0_RDR; + rx_transfers[0].dst_addr = (uint32_t)receive_buffer; + rx_transfers[0].nbytes = 32; + + bflb_dma_channel_lli_reload(dma0_ch1, rx_llipool, 20, rx_transfers, 1); + + msgs[1].addr = 0x50; + msgs[1].flags = I2C_M_DMA | I2C_M_READ; + msgs[1].buffer = NULL; + msgs[1].length = 32; + bflb_i2c_transfer(i2c0, msgs, 2); + + bflb_dma_channel_start(dma0_ch1); + + while (dma_tc_flag1 == 0) { + } + while ((bflb_i2c_get_intstatus(i2c0) & I2C_INT_END) == 0) { + } + bflb_i2c_deinit(i2c0); + + printf("read over\r\n"); + + /* Check read data */ + for (uint8_t i = 0; i < 32; i++) { + if (((uint8_t *)send_buffer)[i] != ((uint8_t *)receive_buffer)[i]) { + printf("check fail, %d write: %02x, read: %02x\r\n", i, ((uint8_t *)send_buffer)[i], ((uint8_t *)receive_buffer)[i]); + } + } + printf("check over\r\n"); + printf("end\r\n"); + + while(1){ + } +} diff --git a/examples/peripherals/i2c/i2c_eeprom_dma/proj.conf b/examples/peripherals/i2c/i2c_eeprom_dma/proj.conf new file mode 100644 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom_dma/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/i2c/i2c_eeprom_interrupt/CMakeLists.txt b/examples/peripherals/i2c/i2c_eeprom_interrupt/CMakeLists.txt new file mode 100644 index 00000000..34520e1f --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom_interrupt/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(i2c_eeprom_interrupt) diff --git a/examples/peripherals/i2c/i2c_eeprom_interrupt/Makefile b/examples/peripherals/i2c/i2c_eeprom_interrupt/Makefile new file mode 100644 index 00000000..44367c02 --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom_interrupt/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/peripherals/i2c/i2c_eeprom_interrupt/main.c b/examples/peripherals/i2c/i2c_eeprom_interrupt/main.c new file mode 100644 index 00000000..aefad4bb --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom_interrupt/main.c @@ -0,0 +1,132 @@ +#include "bflb_mtimer.h" +#include "bflb_i2c.h" +#include "board.h" + +#define EEPROM_TRANSFER_LENGTH 32 +#define EEPROM_SELECT_PAGE0 (0 << 5) +#define EEPROM_SELECT_PAGE1 (1 << 5) + +static struct bflb_device_s *i2c0; + +void i2c_isr(int irq, void *arg) +{ + uint32_t status; + + status = bflb_i2c_get_intstatus(i2c0); + + if (status & I2C_INTSTS_END) { + bflb_i2c_int_mask(i2c0, I2C_INT_END, true); + printf("Transfer end interrupt\r\n"); + } + if (status & I2C_INTSTS_NACK) { + bflb_i2c_int_mask(i2c0, I2C_INT_NACK, true); + printf("Error! NACK interrupt\r\n"); + } + if (status & I2C_INTSTS_ARB) { + bflb_i2c_int_mask(i2c0, I2C_INT_ARB, true); + printf("Error! Arbitration lost interrupt\r\n"); + } + if (status & I2C_INTSTS_FER) { + bflb_i2c_int_mask(i2c0, I2C_INT_FER, true); + printf("Error! TX/RX FIFO error interrupt\r\n"); + } +} + +int main(void) +{ + board_init(); + board_i2c0_gpio_init(); + + i2c0 = bflb_device_get_by_name("i2c0"); + + bflb_i2c_init(i2c0, 400000); + + /* Set i2c interrupt */ + bflb_i2c_int_mask(i2c0, I2C_INT_END | I2C_INT_NACK | I2C_INT_ARB | I2C_INT_FER, false); + bflb_irq_attach(i2c0->irq_num, i2c_isr, i2c0); + bflb_irq_enable(i2c0->irq_num); + + struct bflb_i2c_msg_s msgs[2]; + uint8_t subaddr[2] = { 0x00, 0x00 }; + + uint8_t write_data[256]; + uint8_t read_data[256]; + + /* Write and read buffer init */ + for (size_t i = 0; i < 256; i++) { + write_data[i] = i; + read_data[i] = 0; + } + + /* Write page 0 */ + subaddr[1] = EEPROM_SELECT_PAGE0; + + msgs[0].addr = 0x50; + msgs[0].flags = I2C_M_NOSTOP; + msgs[0].buffer = subaddr; + msgs[0].length = 2; + + msgs[1].addr = 0x50; + msgs[1].flags = 0; + msgs[1].buffer = write_data; + msgs[1].length = EEPROM_TRANSFER_LENGTH; + + bflb_i2c_transfer(i2c0, msgs, 2); + printf("write over\r\n\r\n"); + bflb_mtimer_delay_ms(100); + + /* Unmask interrupt */ + bflb_i2c_int_mask(i2c0, I2C_INT_END | I2C_INT_NACK | I2C_INT_ARB | I2C_INT_FER, false); + + /* Write page 1 */ + subaddr[1] = EEPROM_SELECT_PAGE1; + + msgs[1].addr = 0x50; + msgs[1].flags = 0; + msgs[1].buffer = write_data + EEPROM_TRANSFER_LENGTH; + msgs[1].length = EEPROM_TRANSFER_LENGTH; + + bflb_i2c_transfer(i2c0, msgs, 2); + printf("write over\r\n\r\n"); + bflb_mtimer_delay_ms(100); + + /* Unmask interrupt */ + bflb_i2c_int_mask(i2c0, I2C_INT_END | I2C_INT_NACK | I2C_INT_ARB | I2C_INT_FER, false); + + /* Read page 0 */ + subaddr[1] = EEPROM_SELECT_PAGE0; + + msgs[1].addr = 0x50; + msgs[1].flags = I2C_M_READ; + msgs[1].buffer = read_data; + msgs[1].length = EEPROM_TRANSFER_LENGTH; + bflb_i2c_transfer(i2c0, msgs, 2); + printf("read over\r\n\r\n"); + bflb_mtimer_delay_ms(100); + + /* Unmask interrupt */ + bflb_i2c_int_mask(i2c0, I2C_INT_END | I2C_INT_NACK | I2C_INT_ARB | I2C_INT_FER, false); + + /* Read page 1 */ + subaddr[1] = EEPROM_SELECT_PAGE1; + + msgs[1].addr = 0x50; + msgs[1].flags = I2C_M_READ; + msgs[1].buffer = read_data + EEPROM_TRANSFER_LENGTH; + msgs[1].length = EEPROM_TRANSFER_LENGTH; + bflb_i2c_transfer(i2c0, msgs, 2); + printf("read over\r\n\r\n"); + bflb_mtimer_delay_ms(100); + + /* Check read data */ + for (uint8_t i = 0; i < 2 * EEPROM_TRANSFER_LENGTH; i++) { + if (write_data[i] != read_data[i]) { + printf("check fail, %d write: %02x, read: %02x\r\n", i, write_data[i], read_data[i]); + } + } + printf("check over\r\n"); + printf("end\r\n"); + + while (1) { + } +} diff --git a/examples/peripherals/i2c/i2c_eeprom_interrupt/proj.conf b/examples/peripherals/i2c/i2c_eeprom_interrupt/proj.conf new file mode 100644 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/i2c/i2c_eeprom_interrupt/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/CMakeLists.txt b/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/CMakeLists.txt new file mode 100644 index 00000000..339b24ca --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(sec_eng_aes_link_sw_key) diff --git a/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/Makefile b/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/Makefile new file mode 100644 index 00000000..44367c02 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/main.c b/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/main.c new file mode 100644 index 00000000..dfcc44c3 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/main.c @@ -0,0 +1,365 @@ +#include "bflb_mtimer.h" +#include "bflb_sec_aes.h" +#include "board.h" + +const uint8_t aes_ecb_128bit_pt[16] = { + 0x32, 0x43, 0xf6, 0xa8, 0x88, 0x5a, 0x30, 0x8d, + 0x31, 0x31, 0x98, 0xa2, 0xe0, 0x37, 0x07, 0x34 +}; + +const uint8_t aes_ecb_128bit_ct[16] = { + 0x39, 0x25, 0x84, 0x1d, 0x02, 0xDc, 0x09, 0xfb, + 0xdc, 0x11, 0x85, 0x97, 0x19, 0x6a, 0x0b, 0x32 +}; + +const uint8_t aes_cbc_128bit_pt[48] = { + 0x6b, 0xc1, 0xbe, 0xe2, 0x2e, 0x40, 0x9f, 0x96, + 0xe9, 0x3d, 0x7e, 0x11, 0x73, 0x93, 0x17, 0x2a, + 0xae, 0x2d, 0x8a, 0x57, 0x1e, 0x03, 0xac, 0x9c, + 0x9e, 0xb7, 0x6f, 0xac, 0x45, 0xaf, 0x8e, 0x51, + 0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77, + 0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff +}; + +const uint8_t aes_cbc_128bit_ct[48] = { + 0x76, 0x49, 0xab, 0xac, 0x81, 0x19, 0xb2, 0x46, + 0xce, 0xe9, 0x8e, 0x9b, 0x12, 0xe9, 0x19, 0x7d, + 0x50, 0x86, 0xcb, 0x9b, 0x50, 0x72, 0x19, 0xee, + 0x95, 0xdb, 0x11, 0x3a, 0x91, 0x76, 0x78, 0xb2, + 0x7f, 0xee, 0xdb, 0x79, 0xc5, 0x87, 0x1f, 0x16, + 0x59, 0xd4, 0x60, 0xa6, 0x76, 0xd1, 0xc0, 0x18 +}; + +const uint8_t aes_ctr_128bit_pt[16] = { + 0x6B, 0xC1, 0xBE, 0xE2, 0x2E, 0x40, 0x9F, 0x96, + 0xE9, 0x3D, 0x7E, 0x11, 0x73, 0x93, 0x17, 0x2A +}; + +const uint8_t aes_ctr_128bit_ct[16] = { + 0x87, 0x4D, 0x61, 0x91, 0xB6, 0x20, 0xE3, 0x26, + 0x1B, 0xEF, 0x68, 0x64, 0x99, 0x0D, 0xB6, 0xCE +}; + +const uint8_t aes_xts_128bit_pt[64] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +const uint8_t aes_xts_128bit_ct[64] = { + 0x91, 0x7c, 0xf6, 0x9e, 0xbd, 0x68, 0xb2, 0xec, 0x9b, 0x9f, 0xe9, 0xa3, 0xea, 0xdd, 0xa6, 0x92, + 0xcd, 0x43, 0xd2, 0xf5, 0x95, 0x98, 0xed, 0x85, 0x8c, 0x02, 0xc2, 0x65, 0x2f, 0xbf, 0x92, 0x2e, + 0xc4, 0xcf, 0xc5, 0xa3, 0x8b, 0x75, 0x84, 0x30, 0xd5, 0x16, 0x51, 0x18, 0x7f, 0x65, 0xbb, 0xe6, + 0x16, 0x6b, 0xc3, 0x60, 0xd7, 0xbb, 0x56, 0xe9, 0xbb, 0xe4, 0x54, 0x10, 0x72, 0x2e, 0x46, 0x75 +}; + +const uint8_t aes_xts_192bit_pt[64] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; +const uint8_t aes_xts_192bit_ct[64] = { + 0x82, 0xba, 0x63, 0x7a, 0xd6, 0xfb, 0x48, 0xe1, 0x5c, 0xc2, 0x3e, 0x8e, 0x36, 0xf9, 0x63, 0x53, + 0x0c, 0xd8, 0xda, 0x20, 0x87, 0x90, 0xdf, 0x03, 0x82, 0x97, 0xe5, 0x65, 0xee, 0xe2, 0x54, 0xa5, + 0xe8, 0x3d, 0x20, 0xa1, 0x23, 0xd2, 0xcc, 0x22, 0xe1, 0x6e, 0xc2, 0x14, 0x49, 0x19, 0xdc, 0x09, + 0x4c, 0x1c, 0xdb, 0xe1, 0xbd, 0xc1, 0x5b, 0xa6, 0xdf, 0x7a, 0x71, 0xc7, 0x9e, 0x11, 0x62, 0xdb + +}; + +const uint8_t aes_xts_256bit_pt[64] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 +}; + +/* key1=000102030405060708090a0b0c0d0e0ffffefdfcfbfaf9f8f7f6f5f4f3f2f1f0 + key2=fffefdfcfbfaf9f8f7f6f5f4f3f2f1f0000102030405060708090a0b0c0d0e0f*/ +const uint8_t aes_xts_256bit_ct[64] = { + 0x06, 0x87, 0xea, 0x7b, 0xf9, 0x87, 0x4b, 0x5a, 0xa6, 0xa5, 0xf1, 0x23, 0x6e, 0xda, 0x73, 0x0a, + 0x73, 0x8d, 0x30, 0x6c, 0x9d, 0x4f, 0xc1, 0x6b, 0xfb, 0x47, 0x2c, 0x58, 0x68, 0x16, 0xfd, 0x07, + 0xe9, 0x59, 0x84, 0xd9, 0x36, 0x84, 0xcd, 0xfc, 0x77, 0xce, 0x30, 0xdf, 0x6d, 0x49, 0xef, 0x54, + 0x66, 0xb2, 0x7f, 0x06, 0x46, 0xbb, 0xb2, 0x46, 0x00, 0xf8, 0x6b, 0x0c, 0xc0, 0x5f, 0xb5, 0x20 +}; + +static struct bflb_aes_link_s aes_ecb_link = { + .aes_key = AES_LINK_KEY_128BITS, /* 128-bit key mode select */ + .aes_dec_en = 0, /* Encode */ + .aes_newkey_dis = 0, /* Use new key */ + .aes_hwkey_en = 0, /* Use sw key */ + .aes_intclr = 0, /* Not clear intrrupt */ + .aes_intset = 0, /* Not set interrupt */ + .aes_mode = AES_MODE_ECB, /* ECB mode select */ + .aes_newiv_dis = 0, /* Use new iv */ + .aes_xts = 0, /* XTS mode select */ + .aes_msglen = 1, /* Number of 128-bit block */ + .aes_srcaddr = 0, /* Message source address */ + .aes_dstaddr = 0, /* Message destination address */ + .aes_iv0 = 0, /* Big endian initial vector(MSB) */ + .aes_iv1 = 0, /* Big endian initial vector */ + .aes_iv2 = 0, /* Big endian initial vector */ + .aes_iv3 = 0, /* Big endian initial vector(LSB)(CTR mode:counter initial value) */ + .aes_key0 = 0x16157e2b, /* Big endian aes key(aes-128/256 key MSB) */ + .aes_key1 = 0xa6d2ae28, /* Big endian aes key */ + .aes_key2 = 0x8815f7ab, /* Big endian aes key */ + .aes_key3 = 0x3c4fcf09, /* Big endian aes key(aes-128 key LSB) */ + .aes_key4 = 0, /* Big endian aes key */ + .aes_key5 = 0, /* Big endian aes key */ + .aes_key6 = 0, /* Big endian aes key */ + .aes_key7 = 0 /* Big endian aes key(aes-256 key LSB) */ +}; + +static struct bflb_aes_link_s aes_cbc_link = { + .aes_key = AES_LINK_KEY_128BITS, /* 128-bit key mode select */ + .aes_dec_en = 0, /* Encode */ + .aes_newkey_dis = 0, /* Use new key */ + .aes_hwkey_en = 0, /* Use sw key */ + .aes_intclr = 0, /* Not clear intrrupt */ + .aes_intset = 0, /* Not set interrupt */ + .aes_mode = AES_MODE_CBC, /* ECB mode select */ + .aes_newiv_dis = 0, /* Use new iv */ + .aes_xts = 0, /* XTS mode select */ + .aes_msglen = 1, /* Number of 128-bit block */ + .aes_srcaddr = 0, /* Message source address */ + .aes_dstaddr = 0, /* Message destination address */ + .aes_iv0 = 0x03020100, /* Big endian initial vector(MSB) */ + .aes_iv1 = 0x07060504, /* Big endian initial vector */ + .aes_iv2 = 0x0b0a0908, /* Big endian initial vector */ + .aes_iv3 = 0x0f0e0d0c, /* Big endian initial vector(LSB)(CTR mode:counter initial value) */ + .aes_key0 = 0x16157e2b, /* Big endian aes key(aes-128/256 key MSB) */ + .aes_key1 = 0xa6d2ae28, /* Big endian aes key */ + .aes_key2 = 0x8815f7ab, /* Big endian aes key */ + .aes_key3 = 0x3c4fcf09, /* Big endian aes key(aes-128 key LSB) */ + .aes_key4 = 0, /* Big endian aes key */ + .aes_key5 = 0, /* Big endian aes key */ + .aes_key6 = 0, /* Big endian aes key */ + .aes_key7 = 0 /* Big endian aes key(aes-256 key LSB) */ +}; + +static struct bflb_aes_link_s aes_cbc_link2 = { + .aes_key = AES_LINK_KEY_128BITS, /* 128-bit key mode select */ + .aes_dec_en = 0, /* Encode */ + .aes_newkey_dis = 0, /* Use new key */ + .aes_hwkey_en = 0, /* Use sw key */ + .aes_intclr = 0, /* Not clear intrrupt */ + .aes_intset = 0, /* Not set interrupt */ + .aes_mode = AES_MODE_CBC, /* ECB mode select */ + .aes_newiv_dis = 0, /* Use new iv */ + .aes_xts = 0, /* XTS mode select */ + .aes_msglen = 1, /* Number of 128-bit block */ + .aes_srcaddr = 0, /* Message source address */ + .aes_dstaddr = 0, /* Message destination address */ + .aes_iv0 = 0x03020100, /* Big endian initial vector(MSB) */ + .aes_iv1 = 0x07060504, /* Big endian initial vector */ + .aes_iv2 = 0x0b0a0908, /* Big endian initial vector */ + .aes_iv3 = 0x0f0e0d0c, /* Big endian initial vector(LSB)(CTR mode:counter initial value) */ + .aes_key0 = 0x16157e2b, /* Big endian aes key(aes-128/256 key MSB) */ + .aes_key1 = 0xa6d2ae28, /* Big endian aes key */ + .aes_key2 = 0x8815f7ab, /* Big endian aes key */ + .aes_key3 = 0x3c4fcf09, /* Big endian aes key(aes-128 key LSB) */ + .aes_key4 = 0, /* Big endian aes key */ + .aes_key5 = 0, /* Big endian aes key */ + .aes_key6 = 0, /* Big endian aes key */ + .aes_key7 = 0 /* Big endian aes key(aes-256 key LSB) */ +}; + +static struct bflb_aes_link_s aes_ctr_link = { + .aes_key = AES_LINK_KEY_128BITS, /* 128-bit key mode select */ + .aes_dec_en = 0, /* Encode */ + .aes_newkey_dis = 0, /* Use new key */ + .aes_hwkey_en = 0, /* Use sw key */ + .aes_intclr = 0, /* Not clear intrrupt */ + .aes_intset = 0, /* Not set interrupt */ + .aes_mode = AES_MODE_CTR, /* ECB mode select */ + .aes_newiv_dis = 0, /* Use new iv */ + .aes_xts = 0, /* XTS mode select */ + .aes_msglen = 1, /* Number of 128-bit block */ + .aes_srcaddr = 0, /* Message source address */ + .aes_dstaddr = 0, /* Message destination address */ + .aes_iv0 = 0xf3f2f1f0, /* Big endian initial vector(MSB) */ + .aes_iv1 = 0xf7f6f5f4, /* Big endian initial vector */ + .aes_iv2 = 0xfbfaf9f8, /* Big endian initial vector */ + .aes_iv3 = 0xfffefdfc, /* Big endian initial vector(LSB)(CTR mode:counter initial value) */ + .aes_key0 = 0x16157e2b, /* Big endian aes key(aes-128/256 key MSB) */ + .aes_key1 = 0xa6d2ae28, /* Big endian aes key */ + .aes_key2 = 0x8815f7ab, /* Big endian aes key */ + .aes_key3 = 0x3c4fcf09, /* Big endian aes key(aes-128 key LSB) */ + .aes_key4 = 0, /* Big endian aes key */ + .aes_key5 = 0, /* Big endian aes key */ + .aes_key6 = 0, /* Big endian aes key */ + .aes_key7 = 0 /* Big endian aes key(aes-256 key LSB) */ +}; + +static struct bflb_aes_xts_link_s aes_xts_link1 = { + .aes_key = AES_LINK_KEY_128BITS, /* 128-bit key mode select */ + .aes_dec_en = 0, /* Encode */ + .aes_newkey_dis = 0, /* Use new key */ + .aes_hwkey_en = 0, /* Use sw key */ + .aes_intclr = 0, /* Not clear intrrupt */ + .aes_intset = 0, /* Not set interrupt */ + .aes_mode = AES_MODE_XTS, /* ECB mode select */ + .aes_newiv_dis = 0, /* Use new iv */ + .aes_xts = 0, /* XTS mode select */ + .aes_msglen = 1, /* Number of 128-bit block */ + .aes_srcaddr = 0, /* Message source address */ + .aes_dstaddr = 0, /* Message destination address */ + .aes_iv0 = 0x00000000, /* Big endian initial vector(MSB) */ + .aes_iv1 = 0x00000000, /* Big endian initial vector */ + .aes_iv2 = 0x00000000, /* Big endian initial vector */ + .aes_iv3 = 0x00000000, /* Big endian initial vector(LSB)(CTR mode:counter initial value) */ + .aes_key10 = 0x00000000, /* Big endian aes key(aes-128/256 key MSB) */ + .aes_key11 = 0x00000000, /* Big endian aes key */ + .aes_key12 = 0x00000000, /* Big endian aes key */ + .aes_key13 = 0x00000000, /* Big endian aes key(aes-128 key LSB) */ + .aes_key14 = 0x00000000, /* Big endian aes key */ + .aes_key15 = 0x00000000, /* Big endian aes key */ + .aes_key16 = 0x00000000, /* Big endian aes key */ + .aes_key17 = 0x00000000, /* Big endian aes key(aes-256 key LSB) */ + .aes_unitlen = 2, /* Big endian aes unit len*/ + .aes_key20 = 0x00000000, /* Big endian aes key2(aes-128/256 key MSB) */ + .aes_key21 = 0x00000000, /* Big endian aes key2 */ + .aes_key22 = 0x00000000, /* Big endian aes key2 */ + .aes_key23 = 0x00000000, /* Big endian aes key2(aes-128 key LSB) */ + .aes_key24 = 0x00000000, /* Big endian aes key2 */ + .aes_key25 = 0x00000000, /* Big endian aes key2 */ + .aes_key26 = 0x00000000, /* Big endian aes key2 */ + .aes_key27 = 0x00000000 /* Big endian aes key2(aes-256 key LSB) */ +}; + +static struct bflb_aes_xts_link_s aes_xts_link2 = { + .aes_key = AES_LINK_KEY_192BITS, /* 128-bit key mode select */ + .aes_dec_en = 0, /* Encode */ + .aes_newkey_dis = 0, /* Use new key */ + .aes_hwkey_en = 0, /* Use sw key */ + .aes_intclr = 0, /* Not clear intrrupt */ + .aes_intset = 0, /* Not set interrupt */ + .aes_mode = AES_MODE_XTS, /* ECB mode select */ + .aes_newiv_dis = 0, /* Use new iv */ + .aes_xts = 0, /* XTS mode select */ + .aes_msglen = 1, /* Number of 128-bit block */ + .aes_srcaddr = 0, /* Message source address */ + .aes_dstaddr = 0, /* Message destination address */ + .aes_iv0 = 0x00000000, /* Big endian initial vector(MSB) */ + .aes_iv1 = 0x00000000, /* Big endian initial vector */ + .aes_iv2 = 0x00000000, /* Big endian initial vector */ + .aes_iv3 = 0x00000000, /* Big endian initial vector(LSB)(CTR mode:counter initial value) */ + .aes_key10 = 0x03020100, /* Big endian aes key(aes-128/256 key MSB) */ + .aes_key11 = 0x07060504, /* Big endian aes key */ + .aes_key12 = 0x0b0a0908, /* Big endian aes key */ + .aes_key13 = 0x0f0e0d0c, /* Big endian aes key(aes-128 key LSB) */ + .aes_key14 = 0xfcfdfeff, /* Big endian aes key */ + .aes_key15 = 0xf8f9fafb, /* Big endian aes key */ + .aes_key16 = 0x00000000, /* Big endian aes key */ + .aes_key17 = 0x00000000, /* Big endian aes key(aes-256 key LSB) */ + .aes_unitlen = 2, /* Big endian aes unit len*/ + .aes_key20 = 0x03020100, /* Big endian aes key2(aes-128/256 key MSB) */ + .aes_key21 = 0x07060504, /* Big endian aes key2 */ + .aes_key22 = 0x0b0a0908, /* Big endian aes key2 */ + .aes_key23 = 0x0f0e0d0c, /* Big endian aes key2(aes-128 key LSB) */ + .aes_key24 = 0xfcfdfeff, /* Big endian aes key2 */ + .aes_key25 = 0xf8f9fafb, /* Big endian aes key2 */ + .aes_key26 = 0x00000000, /* Big endian aes key2 */ + .aes_key27 = 0x00000000 /* Big endian aes key2(aes-256 key LSB) */ +}; + +static struct bflb_aes_xts_link_s aes_xts_link3 = { + .aes_key = AES_LINK_KEY_256BITS, /* 128-bit key mode select */ + .aes_dec_en = 0, /* Encode */ + .aes_newkey_dis = 0, /* Use new key */ + .aes_hwkey_en = 0, /* Use sw key */ + .aes_intclr = 0, /* Not clear intrrupt */ + .aes_intset = 0, /* Not set interrupt */ + .aes_mode = AES_MODE_XTS, /* ECB mode select */ + .aes_newiv_dis = 0, /* Use new iv */ + .aes_xts = 0, /* XTS mode select */ + .aes_msglen = 1, /* Number of 128-bit block */ + .aes_srcaddr = 0, /* Message source address */ + .aes_dstaddr = 0, /* Message destination address */ + .aes_iv0 = 0x00000000, /* Big endian initial vector(MSB) */ + .aes_iv1 = 0x00000000, /* Big endian initial vector */ + .aes_iv2 = 0x00000000, /* Big endian initial vector */ + .aes_iv3 = 0x00000000, /* Big endian initial vector(LSB)(CTR mode:counter initial value) */ + .aes_key10 = 0x03020100, /* Big endian aes key(aes-128/256 key MSB) */ + .aes_key11 = 0x07060504, /* Big endian aes key */ + .aes_key12 = 0x0b0a0908, /* Big endian aes key */ + .aes_key13 = 0x0f0e0d0c, /* Big endian aes key(aes-128 key LSB) */ + .aes_key14 = 0xfcfdfeff, /* Big endian aes key */ + .aes_key15 = 0xf8f9fafb, /* Big endian aes key */ + .aes_key16 = 0xf4f5f6f7, /* Big endian aes key */ + .aes_key17 = 0xf0f1f2f3, /* Big endian aes key(aes-256 key LSB) */ + .aes_unitlen = 2, /* Big endian aes unit len*/ + .aes_key20 = 0xfcfdfeff, /* Big endian aes key2(aes-128/256 key MSB) */ + .aes_key21 = 0xf8f9fafb, /* Big endian aes key2 */ + .aes_key22 = 0xf4f5f6f7, /* Big endian aes key2 */ + .aes_key23 = 0xf0f1f2f3, /* Big endian aes key2(aes-128 key LSB) */ + .aes_key24 = 0x03020100, /* Big endian aes key2 */ + .aes_key25 = 0x07060504, /* Big endian aes key2 */ + .aes_key26 = 0x0b0a0908, /* Big endian aes key2 */ + .aes_key27 = 0x0f0e0d0c /* Big endian aes key2(aes-256 key LSB) */ +}; + +static uint32_t bflb_data_compare(const uint8_t *expected, uint8_t *input, uint32_t len) +{ + int i = 0; + for (i = 0; i < len; i++) { + if (input[i] != expected[i]) { + printf("Compare fail at %d,input %02x, but expect %02x\r\n", i, input[i], expected[i]); + while (1) { + } + } + } + + return 0; +} + +ATTR_NOCACHE_RAM_SECTION uint8_t aes_enc_buf[512]; +ATTR_NOCACHE_RAM_SECTION uint8_t aes_dec_buf[512]; + +int main(void) +{ + board_init(); + + struct bflb_device_s *aes; + + aes = bflb_device_get_by_name("aes"); + + bflb_group0_request_aes_access(aes); + + bflb_aes_link_init(aes); + + bflb_aes_link_update(aes, (uint32_t)&aes_ecb_link, aes_ecb_128bit_pt, aes_enc_buf, 16); + bflb_data_compare(aes_ecb_128bit_ct, aes_enc_buf, 16); + printf("aes link ecb 128 success\r\n"); + + bflb_aes_link_update(aes, (uint32_t)&aes_cbc_link, aes_cbc_128bit_pt, aes_enc_buf, 16); + bflb_data_compare(aes_cbc_128bit_ct, aes_enc_buf, 16); + printf("aes link cbc 128 success\r\n"); + + bflb_aes_link_update(aes, (uint32_t)&aes_cbc_link2, aes_cbc_128bit_pt, aes_enc_buf, 48); + bflb_data_compare(aes_cbc_128bit_ct, aes_enc_buf, 48); + printf("aes link cbc 128 success\r\n"); + + bflb_aes_link_update(aes, (uint32_t)&aes_ctr_link, aes_ctr_128bit_pt, aes_enc_buf, 16); + bflb_data_compare(aes_ctr_128bit_ct, aes_enc_buf, 16); + printf("aes link ctr 128 success\r\n"); + + bflb_aes_link_update(aes, (uint32_t)&aes_xts_link1, aes_xts_128bit_pt, aes_enc_buf, 16); + bflb_data_compare(aes_xts_128bit_ct, aes_enc_buf, 16); + printf("aes link xts 128 success\r\n"); + + bflb_aes_link_update(aes, (uint32_t)&aes_xts_link2, aes_xts_192bit_pt, aes_enc_buf, 16); + bflb_data_compare(aes_xts_192bit_ct, aes_enc_buf, 16); + printf("aes link xts 192 success\r\n"); + + bflb_aes_link_update(aes, (uint32_t)&aes_xts_link3, aes_xts_256bit_pt, aes_enc_buf, 16); + bflb_data_compare(aes_xts_256bit_ct, aes_enc_buf, 16); + printf("aes link xts 256 success\r\n"); + + printf("aes link success\r\n"); + bflb_group0_release_aes_access(aes); + while (1) { + bflb_mtimer_delay_ms(2000); + } +} \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/proj.conf b/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/proj.conf new file mode 100644 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_aes_link_sw_key/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_aes_sw_key/main.c b/examples/peripherals/sec_eng/sec_eng_aes_sw_key/main.c index c771c8bf..5e1c4c1e 100644 --- a/examples/peripherals/sec_eng/sec_eng_aes_sw_key/main.c +++ b/examples/peripherals/sec_eng/sec_eng_aes_sw_key/main.c @@ -490,6 +490,8 @@ int main(void) aes = bflb_device_get_by_name("aes"); + bflb_group0_request_aes_access(aes); + bflb_aes_init(aes); bflb_aes_set_mode(aes, AES_MODE_ECB); @@ -589,6 +591,7 @@ int main(void) printf("aes xts 256 success\r\n"); printf("aes success\r\n"); + bflb_group0_release_aes_access(aes); while (1) { bflb_mtimer_delay_ms(2000); } diff --git a/examples/peripherals/sec_eng/sec_eng_ecdh/CMakeLists.txt b/examples/peripherals/sec_eng/sec_eng_ecdh/CMakeLists.txt new file mode 100644 index 00000000..a1b1f691 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_ecdh/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(sec_eng_ecdh) diff --git a/examples/peripherals/sec_eng/sec_eng_ecdh/Makefile b/examples/peripherals/sec_eng/sec_eng_ecdh/Makefile new file mode 100644 index 00000000..44367c02 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_ecdh/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/peripherals/sec_eng/sec_eng_ecdh/main.c b/examples/peripherals/sec_eng/sec_eng_ecdh/main.c new file mode 100644 index 00000000..88a753f2 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_ecdh/main.c @@ -0,0 +1,228 @@ +#include "bflb_mtimer.h" +#include "bflb_sec_ecdsa.h" +#include "board.h" + +#define ALGORITHM_TYPE 0 + +/* We use following two case to show how ECDH works*/ +//========================== +//Alice's secret key: 1672493697407246559549867004310108600574958080780180188771300643695147736525 +//Alice's public key: (8186931993451804108690395451499266320135437983074928011404785122795116228120L, 42583342814291813019381020879433259376088942101048764740128506039642196631017L) +//Bob's secret key: 80820894835688796582966945354468122770925276582929501754975915934762303146292 +//Bob's public key: (110419239604359817300303235482162221248952850592986847629047641306847745620659L, 19394459839852358891515335116028197103691369259799083720249515230794728385441L) +//========================== +//Alice's shared key: (89478371667134321617252675049711550685663874249668539239111908843552332917927L, 817906898059826893312335918167859928021104862259509866199871605894193053448L) +//Bob's shared key: (89478371667134321617252675049711550685663874249668539239111908843552332917927L, 817906898059826893312335918167859928021104862259509866199871605894193053448L) +//========================== +//The shared value is the x-value: 89478371667134321617252675049711550685663874249668539239111908843552332917927 +uint8_t secp256r1_ecdh_private_key1[32] = { 0x03, 0xb2, 0x99, 0xf, 0x18, 0x16, 0x38, 0x78, 0x88, 0xb1, 0x9, 0xfd, 0xd4, 0x33, 0x94, 0x1a, + 0x1f, 0x7e, 0x7c, 0x8b, 0xf7, 0xf2, 0x34, 0x15, 0xb0, 0xc1, 0x21, 0x61, 0xc0, 0xe9, 0xdd, 0xcd }; +uint8_t secp256r1_ecdh_public_keyx1[32] = { 0x12, 0x19, 0xa3, 0xa9, 0xd, 0xbf, 0xfa, 0xf3, 0xd5, 0x1b, 0x8c, 0xa0, 0xa6, 0xec, 0xd9, 0xa8, + 0xca, 0xf0, 0x6, 0xaf, 0x3b, 0x52, 0x4b, 0x9f, 0x93, 0x96, 0xcb, 0xa, 0xe6, 0xa6, 0xee, 0x18 }; +uint8_t secp256r1_ecdh_public_keyy1[32] = { 0x5e, 0x25, 0x51, 0x62, 0xd6, 0x5, 0x89, 0xe3, 0x65, 0x3d, 0xde, 0xf1, 0x59, 0xcb, 0xee, 0x70, + 0x56, 0x40, 0x71, 0x55, 0x9e, 0xec, 0xe0, 0x4, 0x81, 0xa4, 0xfc, 0x7a, 0xf, 0xe5, 0x5d, 0xe9 }; +uint8_t secp256r1_ecdh_shared_keyx1[32] = { 0xc5, 0xd2, 0xf6, 0xb1, 0x69, 0x8c, 0x4f, 0xff, 0x1b, 0x4a, 0x9d, 0x4, 0x4d, 0x7a, 0x3d, 0xbf, + 0xa5, 0xed, 0xfc, 0xd6, 0xc9, 0x12, 0xe7, 0x67, 0x32, 0x1e, 0x3f, 0x31, 0x4b, 0xf1, 0x2c, 0xa7 }; + +uint8_t secp256r1_ecdh_private_key2[32] = { 0xb2, 0xaf, 0x1, 0x62, 0x49, 0x36, 0x12, 0xee, 0x36, 0xfb, 0x72, 0x20, 0xc9, 0xcc, 0xba, 0xe7, + 0x86, 0x5, 0x11, 0x84, 0x72, 0xed, 0x1c, 0xa4, 0xf8, 0x2c, 0x3a, 0xb, 0xf6, 0x9e, 0xc9, 0x34 }; +uint8_t secp256r1_ecdh_public_keyx2[32] = { 0xf4, 0x1f, 0x13, 0x2a, 0xf2, 0x7b, 0x67, 0x22, 0xcb, 0x6a, 0x73, 0xb5, 0x21, 0x17, 0x32, 0x32, + 0x7d, 0x8c, 0x42, 0x71, 0x3, 0x9d, 0x54, 0xc, 0x68, 0xdc, 0xac, 0x8b, 0x1d, 0x63, 0x3a, 0xb3 }; +uint8_t secp256r1_ecdh_public_keyy2[32] = { 0x2a, 0xe0, 0xe0, 0x11, 0x45, 0xbc, 0x5e, 0x1b, 0x30, 0x4, 0x1b, 0xc3, 0x45, 0x3b, 0xb9, 0xb6, + 0x77, 0x64, 0x6b, 0x7e, 0x96, 0x1a, 0xad, 0x22, 0xd2, 0xe4, 0x9f, 0x29, 0x8e, 0x64, 0xab, 0xa1 }; +uint8_t secp256r1_ecdh_shared_keyx2[32] = { 0xc5, 0xd2, 0xf6, 0xb1, 0x69, 0x8c, 0x4f, 0xff, 0x1b, 0x4a, 0x9d, 0x4, 0x4d, 0x7a, 0x3d, 0xbf, + 0xa5, 0xed, 0xfc, 0xd6, 0xc9, 0x12, 0xe7, 0x67, 0x32, 0x1e, 0x3f, 0x31, 0x4b, 0xf1, 0x2c, 0xa7 }; + +uint8_t secp256r1_ecdh_private_key[32] = { 0xba, 0x25, 0xf6, 0xc1, 0xa7, 0x82, 0x9a, 0x18, 0x51, 0x08, 0x0c, 0xa8, 0x79, 0x50, 0xb9, 0xd5, + 0x17, 0x7a, 0x8a, 0x65, 0x72, 0xd3, 0x12, 0x87, 0x07, 0x04, 0x9c, 0x74, 0x95, 0x3e, 0xf6, 0x11 }; +uint8_t secp256r1_ecdh_public_keyx[32] = { 0xbe, 0xbb, 0x36, 0x3c, 0xfd, 0x53, 0x8d, 0x94, 0x86, 0x7c, 0xf5, 0xbb, 0x35, 0xd8, 0xb6, 0x7b, + 0x74, 0x8c, 0x7a, 0xcf, 0x05, 0xa4, 0x5c, 0x70, 0x79, 0xb4, 0x78, 0x50, 0x8e, 0x87, 0xea, 0x4c }; +uint8_t secp256r1_ecdh_public_keyy[32] = { 0x84, 0x3c, 0x5b, 0x9c, 0x9c, 0x6b, 0x6c, 0xca, 0xe0, 0xfe, 0x1b, 0x2b, 0xdc, 0xce, 0xb0, 0x24, + 0x3b, 0x4c, 0xc3, 0x58, 0x4c, 0x59, 0x28, 0x4c, 0xda, 0x26, 0x8d, 0x67, 0x9e, 0x8c, 0x29, 0xd4 }; +uint8_t secp256r1_ecdh_shared_keyx[32] = { 0x58, 0xa7, 0x3b, 0x0f, 0x15, 0x58, 0x4e, 0x3a, 0xed, 0x9e, 0x01, 0x3c, 0xbc, 0xdd, 0x9f, 0x56, + 0x16, 0xac, 0x5f, 0xe4, 0x8f, 0x2f, 0xad, 0x38, 0x98, 0x50, 0x43, 0x5e, 0x4e, 0xed, 0x74, 0x53 }; + +uint8_t secp256k1_ecdh_private_key1[32] = { 0x85, 0xE6, 0xDC, 0xDB, 0x9D, 0x9C, 0x00, 0x72, + 0xC0, 0xB7, 0x7C, 0x85, 0xF3, 0x34, 0x83, 0xFC, + 0x8A, 0x3A, 0xDF, 0xC5, 0xAC, 0x64, 0xB5, 0xA0, + 0xC2, 0xFA, 0xD6, 0xDA, 0xAA, 0x51, 0x04, 0xEE }; +uint8_t secp256k1_ecdh_public_keyx1[32] = { 0x10, 0xC8, 0x99, 0xD4, 0x8B, 0xA1, 0x23, 0x90, + 0xBC, 0x54, 0xE3, 0x1F, 0x32, 0x09, 0x7B, 0x3F, + 0xFF, 0xF2, 0x50, 0xB2, 0xBA, 0xBA, 0x82, 0xFB, + 0x64, 0x58, 0x12, 0xDD, 0x14, 0x17, 0x89, 0x53 }; +uint8_t secp256k1_ecdh_public_keyy1[32] = { 0xC3, 0x71, 0x10, 0x3B, 0xF3, 0x00, 0x4B, 0x6E, + 0x4E, 0x6A, 0x95, 0xF1, 0xAB, 0xCE, 0xDE, 0x10, + 0x91, 0x38, 0x7A, 0x9C, 0xCF, 0x0D, 0x9B, 0x67, + 0x55, 0x79, 0xFD, 0x16, 0x30, 0xFB, 0x0B, 0xC4 }; +uint8_t secp256k1_ecdh_shared_keyx1[32] = { 0x4B, 0xA5, 0xE0, 0xFD, 0x2C, 0x36, 0xC4, 0xA4, + 0xB5, 0xAA, 0x6D, 0x05, 0xF6, 0x3D, 0xAF, 0x99, + 0x58, 0x38, 0x84, 0x6A, 0xE1, 0xD3, 0x0E, 0x2E, + 0xE6, 0x2D, 0xCF, 0x3C, 0x96, 0x70, 0xC0, 0x86 }; + +uint8_t secp256k1_ecdh_private_key2[32] = { 0x07, 0xDF, 0xAB, 0x47, 0x68, 0xA1, 0x2B, 0x99, + 0xDF, 0x8F, 0xE0, 0x1A, 0x5D, 0x04, 0x83, 0xB2, + 0xB1, 0x64, 0x45, 0xB5, 0xB5, 0xC7, 0x7B, 0x09, + 0x17, 0xC9, 0x07, 0x04, 0x2C, 0xFB, 0xBF, 0x40 }; +uint8_t secp256k1_ecdh_public_keyx2[32] = { 0xBD, 0x50, 0xB9, 0x7C, 0x60, 0xB5, 0x23, 0x6B, + 0xDA, 0xCD, 0xA8, 0xB6, 0xCF, 0x9F, 0x01, 0xDF, + 0xAC, 0x00, 0x5D, 0x23, 0xA3, 0x21, 0xEC, 0xDB, + 0xC2, 0x0C, 0x03, 0x70, 0x9B, 0x2B, 0x15, 0x7B }; +uint8_t secp256k1_ecdh_public_keyy2[32] = { 0x95, 0xE3, 0x6C, 0x9C, 0xE2, 0xB3, 0x08, 0x8B, + 0x80, 0x95, 0x54, 0xFD, 0x73, 0x6D, 0xF5, 0xB4, + 0x3B, 0xDE, 0x5B, 0xD7, 0x90, 0x5C, 0x89, 0x73, + 0xF0, 0x08, 0xF5, 0x23, 0x7B, 0x2D, 0x31, 0xD3 }; +uint8_t secp256k1_ecdh_shared_keyx2[32] = { 0x4B, 0xA5, 0xE0, 0xFD, 0x2C, 0x36, 0xC4, 0xA4, + 0xB5, 0xAA, 0x6D, 0x05, 0xF6, 0x3D, 0xAF, 0x99, + 0x58, 0x38, 0x84, 0x6A, 0xE1, 0xD3, 0x0E, 0x2E, + 0xE6, 0x2D, 0xCF, 0x3C, 0x96, 0x70, 0xC0, 0x86 }; + +uint8_t secp256k1_ecdh_private_key[32] = { 0x07, 0xDF, 0xAB, 0x47, 0x68, 0xA1, 0x2B, 0x99, + 0xDF, 0x8F, 0xE0, 0x1A, 0x5D, 0x04, 0x83, 0xB2, + 0xB1, 0x64, 0x45, 0xB5, 0xB5, 0xC7, 0x7B, 0x09, + 0x17, 0xC9, 0x07, 0x04, 0x2C, 0xFB, 0xBF, 0x40 }; +uint8_t secp256k1_ecdh_public_keyx[32] = { 0xBD, 0x50, 0xB9, 0x7C, 0x60, 0xB5, 0x23, 0x6B, + 0xDA, 0xCD, 0xA8, 0xB6, 0xCF, 0x9F, 0x01, 0xDF, + 0xAC, 0x00, 0x5D, 0x23, 0xA3, 0x21, 0xEC, 0xDB, + 0xC2, 0x0C, 0x03, 0x70, 0x9B, 0x2B, 0x15, 0x7B }; +uint8_t secp256k1_ecdh_public_keyy[32] = { 0x95, 0xE3, 0x6C, 0x9C, 0xE2, 0xB3, 0x08, 0x8B, + 0x80, 0x95, 0x54, 0xFD, 0x73, 0x6D, 0xF5, 0xB4, + 0x3B, 0xDE, 0x5B, 0xD7, 0x90, 0x5C, 0x89, 0x73, + 0xF0, 0x08, 0xF5, 0x23, 0x7B, 0x2D, 0x31, 0xD3 }; +uint8_t secp256k1_ecdh_shared_keyx[32] = { 0x15, 0x5C, 0x1B, 0x6F, 0xE7, 0xF9, 0x99, 0xCC, + 0xBD, 0x9E, 0x1E, 0x3B, 0x71, 0xA0, 0x10, 0x5F, + 0xA7, 0x74, 0x9C, 0xAF, 0xE9, 0x92, 0xFB, 0xE8, + 0x9E, 0x9C, 0x54, 0x6B, 0x23, 0x39, 0x22, 0xEE }; + +#define BUFF_COPY(G) \ + { \ + memcpy(ecdh_private_key1, G##_ecdh_private_key1, 32); \ + memcpy(ecdh_public_keyx1, G##_ecdh_public_keyx1, 32); \ + memcpy(ecdh_public_keyy1, G##_ecdh_public_keyy1, 32); \ + memcpy(ecdh_shared_keyx1, G##_ecdh_shared_keyx1, 32); \ + memcpy(ecdh_private_key2, G##_ecdh_private_key2, 32); \ + memcpy(ecdh_public_keyx2, G##_ecdh_public_keyx2, 32); \ + memcpy(ecdh_public_keyy2, G##_ecdh_public_keyy2, 32); \ + memcpy(ecdh_shared_keyx2, G##_ecdh_shared_keyx2, 32); \ + memcpy(ecdh_private_key, G##_ecdh_private_key, 32); \ + memcpy(ecdh_public_keyx, G##_ecdh_public_keyx, 32); \ + memcpy(ecdh_public_keyy, G##_ecdh_public_keyy, 32); \ + memcpy(ecdh_shared_keyx, G##_ecdh_shared_keyx, 32); \ + } + +int main(void) +{ + uint8_t ecdh_private_key1[32]; + uint8_t ecdh_public_keyx1[32]; + uint8_t ecdh_public_keyy1[32]; + uint8_t ecdh_shared_keyx1[32]; + + uint8_t ecdh_private_key2[32]; + uint8_t ecdh_public_keyx2[32]; + uint8_t ecdh_public_keyy2[32]; + uint8_t ecdh_shared_keyx2[32]; + + uint8_t ecdh_private_key[32]; + uint8_t ecdh_public_keyx[32]; + uint8_t ecdh_public_keyy[32]; + uint8_t ecdh_shared_keyx[32]; + + uint32_t ecdh_keyx[8]; + uint32_t ecdh_keyy[8]; + + int32_t i; + uint8_t *p; + + struct bflb_ecdh_s ecdh_handle; + uint32_t time1, time2; + + board_init(); + + printf("ECDH Case\r\n"); + + for (int type_id = 0; type_id < 2; type_id++) { + if (type_id == 0) { + bflb_sec_ecdh_init(&ecdh_handle, ECP_SECP256R1); + printf("ECP_SECP256R1\r\n"); + BUFF_COPY(secp256r1); + } else if (type_id == 1) { + bflb_sec_ecdh_init(&ecdh_handle, ECP_SECP256K1); + printf("ECP_SECP256K1\r\n"); + BUFF_COPY(secp256k1); + } + + printf("Bob calculate encrypt key\r\n"); + time1 = (unsigned int)bflb_mtimer_get_time_us(); + bflb_sec_ecdh_get_encrypt_key(&ecdh_handle, (uint32_t *)ecdh_public_keyx1, (uint32_t *)ecdh_public_keyy1, (uint32_t *)ecdh_private_key2, ecdh_keyx, ecdh_keyy); + time2 = (unsigned int)bflb_mtimer_get_time_us(); + printf("Get encrypt key time=%dus\r\n", (time2 - time1)); + + p = (uint8_t *)ecdh_keyx; + + for (i = 0; i < 32; i++) { + if (ecdh_shared_keyx2[i] != p[i]) { + printf("ECDH Compare fail\r\n"); + printf("p[%d]=0x%x\r\n", i, p[i]); + } + } + + printf("Alice calculate encrypt key\r\n"); + time1 = (unsigned int)bflb_mtimer_get_time_us(); + bflb_sec_ecdh_get_encrypt_key(&ecdh_handle, (uint32_t *)ecdh_public_keyx2, (uint32_t *)ecdh_public_keyy2, (uint32_t *)ecdh_private_key1, ecdh_keyx, ecdh_keyy); + time2 = (unsigned int)bflb_mtimer_get_time_us(); + printf("Get encrypt key time=%dus\r\n", (time2 - time1)); + + p = (uint8_t *)ecdh_keyx; + + for (i = 0; i < 32; i++) { + if (ecdh_shared_keyx1[i] != p[i]) { + printf("ECDH Compare fail\r\n"); + printf("p[%d]=0x%x\r\n", i, p[i]); + } + } + + printf("Another case\r\n"); + printf("Get Public key\r\n"); + time1 = (unsigned int)bflb_mtimer_get_time_us(); + bflb_sec_ecdh_get_public_key(&ecdh_handle, (uint32_t *)ecdh_private_key, ecdh_keyx, ecdh_keyy); + time2 = (unsigned int)bflb_mtimer_get_time_us(); + printf("Get public key time=%dus\r\n", (time2 - time1)); + + p = (uint8_t *)ecdh_keyx; + + for (i = 0; i < 32; i++) { + if (ecdh_public_keyx[i] != p[i]) { + printf("ECDH Compare fail\r\n"); + printf("p[%d]=0x%x\r\n", i, p[i]); + } + } + + p = (uint8_t *)ecdh_keyy; + + for (i = 0; i < 32; i++) { + if (ecdh_public_keyy[i] != p[i]) { + printf("ECDH Compare fail\r\n"); + printf("p[%d]=0x%x\r\n", i, p[i]); + } + } + + printf("Get shared key\r\n"); + + time1 = (unsigned int)bflb_mtimer_get_time_us(); + bflb_sec_ecdh_get_encrypt_key(&ecdh_handle, ecdh_keyx, ecdh_keyy, (uint32_t *)ecdh_private_key, ecdh_keyx, ecdh_keyy); + time2 = (unsigned int)bflb_mtimer_get_time_us(); + printf("Get share key time=%dus\r\n", (time2 - time1)); + + p = (uint8_t *)ecdh_keyx; + + for (i = 0; i < 32; i++) { + if (ecdh_shared_keyx[i] != p[i]) { + printf("ECDH Compare fail\r\n"); + printf("p[%d]=0x%x\r\n", i, p[i]); + } + } + } + + while (1) { + bflb_mtimer_delay_ms(2000); + } +} \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_ecdh/proj.conf b/examples/peripherals/sec_eng/sec_eng_ecdh/proj.conf new file mode 100644 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_ecdh/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_ecdsa/CMakeLists.txt b/examples/peripherals/sec_eng/sec_eng_ecdsa/CMakeLists.txt new file mode 100644 index 00000000..a3f3ee67 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_ecdsa/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(sec_eng_ecdsa) diff --git a/examples/peripherals/sec_eng/sec_eng_ecdsa/Makefile b/examples/peripherals/sec_eng/sec_eng_ecdsa/Makefile new file mode 100644 index 00000000..44367c02 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_ecdsa/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/peripherals/sec_eng/sec_eng_ecdsa/main.c b/examples/peripherals/sec_eng/sec_eng_ecdsa/main.c new file mode 100644 index 00000000..ddb80101 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_ecdsa/main.c @@ -0,0 +1,156 @@ +#include "bflb_mtimer.h" +#include "bflb_sec_ecdsa.h" +#include "board.h" + +int main(void) +{ + board_init(); + + /* We use following test vector to show how BFLB_ECDSA works�� + * this can be found in https://tools.ietf.org/html/rfc6979#page-33 */ +#if 0 + A.2.5. ECDSA, 256 Bits (Prime Field) + + Key pair: + + curve: NIST P-256 + + q = FFFFFFFF00000000FFFFFFFFFFFFFFFFBCE6FAADA7179E84F3B9CAC2FC632551 + (qlen = 256 bits) + + private key: + + x = C9AFA9D845BA75166B5C215767B1D6934E50C3DB36E89B127B8A622B120F6721 + + public key: U = xG + + Ux = 60FED4BA255A9D31C961EB74C6356D68C049B8923B61FA6CE669622E60F29FB6 + + Uy = 7903FE1008B8BC99A41AE9E95628BC64F2F1B20C2D7E9F5177A3C294D4462299 + + Signatures: + + With SHA-1, message = "sample": + k = 882905F1227FD620FBF2ABF21244F0BA83D0DC3A9103DBBEE43A1FB858109DB4 + r = 61340C88C3AAEBEB4F6D667F672CA9759A6CCAA9FA8811313039EE4A35471D32 + s = 6D7F147DAC089441BB2E2FE8F7A3FA264B9C475098FDCF6E00D7C996E1B8B7EB + + With SHA-224, message = "sample": + k = 103F90EE9DC52E5E7FB5132B7033C63066D194321491862059967C715985D473 + r = 53B2FFF5D1752B2C689DF257C04C40A587FABABB3F6FC2702F1343AF7CA9AA3F + s = B9AFB64FDC03DC1A131C7D2386D11E349F070AA432A4ACC918BEA988BF75C74C + + With SHA-256, message = "sample": + k = A6E3C57DD01ABE90086538398355DD4C3B17AA873382B0F24D6129493D8AAD60 + r = EFD48B2AACB6A8FD1140DD9CD45E81D69D2C877B56AAF991C34D0EA84EAF3716 + s = F7CB1C942D657C41D436C7A1B6E29F65F3E900DBB9AFF4064DC4AB2F843ACDA8 + + With SHA-384, message = "sample": + k = 09F634B188CEFD98E7EC88B1AA9852D734D0BC272F7D2A47DECC6EBEB375AAD4 + r = 0EAFEA039B20E9B42309FB1D89E213057CBF973DC0CFC8F129EDDDC800EF7719 + s = 4861F0491E6998B9455193E34E7B0D284DDD7149A74B95B9261F13ABDE940954 + + With SHA-512, message = "sample": + k = 5FA81C63109BADB88C1F367B47DA606DA28CAD69AA22C4FE6AD7DF73A7173AA5 + r = 8496A60B5E9B47C825488827E0495B0E3FA109EC4568FD3F8D1097678EB97F00 + s = 2362AB1ADBE2B8ADF9CB9EDAB740EA6049C028114F2460F96554F61FAE3302FE +#endif + uint32_t i = 0; + uint8_t *p; + uint32_t time = 0; + + uint8_t ecdsa_hash[32] = { 0xAF, 0x2B, 0xDB, 0xE1, 0xAA, 0x9B, 0x6E, 0xC1, 0xE2, 0xAD, 0xE1, 0xD6, 0x94, 0xF4, 0x1F, 0xC7, + 0x1A, 0x83, 0x1D, 0x02, 0x68, 0xE9, 0x89, 0x15, 0x62, 0x11, 0x3D, 0x8A, 0x62, 0xAD, 0xD1, 0xBF }; + uint8_t ecdsa_private_key[32] = { 0xC9, 0xAF, 0xA9, 0xD8, 0x45, 0xBA, 0x75, 0x16, 0x6B, 0x5C, 0x21, 0x57, 0x67, 0xB1, 0xD6, 0x93, + 0x4E, 0x50, 0xC3, 0xDB, 0x36, 0xE8, 0x9B, 0x12, 0x7B, 0x8A, 0x62, 0x2B, 0x12, 0x0F, 0x67, 0x21 }; + uint8_t ecdsa_public_keyx[32] = { 0x60, 0xFE, 0xD4, 0xBA, 0x25, 0x5A, 0x9D, 0x31, 0xC9, 0x61, 0xEB, 0x74, 0xC6, 0x35, 0x6D, 0x68, + 0xC0, 0x49, 0xB8, 0x92, 0x3B, 0x61, 0xFA, 0x6C, 0xE6, 0x69, 0x62, 0x2E, 0x60, 0xF2, 0x9F, 0xB6 }; + uint8_t ecdsa_public_keyy[32] = { 0x79, 0x03, 0xFE, 0x10, 0x08, 0xB8, 0xBC, 0x99, 0xA4, 0x1A, 0xE9, 0xE9, 0x56, 0x28, 0xBC, 0x64, + 0xF2, 0xF1, 0xB2, 0x0C, 0x2D, 0x7E, 0x9F, 0x51, 0x77, 0xA3, 0xC2, 0x94, 0xD4, 0x46, 0x22, 0x99 }; + uint8_t ecdsa_k[32] = { 0xA6, 0xE3, 0xC5, 0x7D, 0xD0, 0x1A, 0xBE, 0x90, 0x08, 0x65, 0x38, 0x39, 0x83, 0x55, 0xDD, 0x4C, + 0x3B, 0x17, 0xAA, 0x87, 0x33, 0x82, 0xB0, 0xF2, 0x4D, 0x61, 0x29, 0x49, 0x3D, 0x8A, 0xAD, 0x60 }; + uint8_t ecdsa_r[32] = { 0xEF, 0xD4, 0x8B, 0x2A, 0xAC, 0xB6, 0xA8, 0xFD, 0x11, 0x40, 0xDD, 0x9C, 0xD4, 0x5E, 0x81, 0xD6, + 0x9D, 0x2C, 0x87, 0x7B, 0x56, 0xAA, 0xF9, 0x91, 0xC3, 0x4D, 0x0E, 0xA8, 0x4E, 0xAF, 0x37, 0x16 }; + uint8_t ecdsa_s[32] = { 0xF7, 0xCB, 0x1C, 0x94, 0x2D, 0x65, 0x7C, 0x41, 0xD4, 0x36, 0xC7, 0xA1, 0xB6, 0xE2, 0x9F, 0x65, + 0xF3, 0xE9, 0x00, 0xDB, 0xB9, 0xAF, 0xF4, 0x06, 0x4D, 0xC4, 0xAB, 0x2F, 0x84, 0x3A, 0xCD, 0xA8 }; + + uint32_t tmp_keyx[8]; + uint32_t tmp_keyy[8]; + struct bflb_ecdsa_s ecdsa_handle; + + printf("ECDSA Case\r\n"); + + bflb_sec_ecdsa_init(&ecdsa_handle, ECP_SECP256R1); + ecdsa_handle.privateKey = (uint32_t *)ecdsa_private_key; + ecdsa_handle.publicKeyx = (uint32_t *)ecdsa_public_keyx; + ecdsa_handle.publicKeyy = (uint32_t *)ecdsa_public_keyy; + +#if 0 + time = (unsigned int)bflb_mtimer_get_time_ms(); + bflb_sec_ecdsa_get_public_key(&ecdsa_handle, (uint32_t *)ecdsa_private_key, tmp_keyx, tmp_keyy); + printf("Get public key time=%dms\r\n", (unsigned int)bflb_mtimer_get_time_ms() - time); + + p = (uint8_t *)tmp_keyx; + + for(i = 0; i < 32; i++) + { + if(ecdsa_public_keyx[i] != p[i]) + { + printf("ECDSA Compare fail\r\n"); + bflb_mtimer_delay_ms(1000); + } + } + + p = (uint8_t *)tmp_keyy; + + for(i = 0; i < 32; i++) + { + if(ecdsa_public_keyy[i] != p[i]) + { + printf("ECDSA Compare fail\r\n"); + bflb_mtimer_delay_ms(1000); + } + } + +#endif + + time = (unsigned int)bflb_mtimer_get_time_ms(); + + if (0 != bflb_sec_ecdsa_sign(&ecdsa_handle, (uint32_t *)ecdsa_k, (uint32_t *)ecdsa_hash, sizeof(ecdsa_hash) / 4, tmp_keyx, tmp_keyy)) { + printf("Sign Fail\r\n"); + } + + printf("ECDSA sign time=%dms\r\n", (unsigned int)bflb_mtimer_get_time_ms() - time); + + printf("Check sign\r\n"); + p = (uint8_t *)tmp_keyx; + + for (i = 0; i < 32; i++) { + if (ecdsa_r[i] != p[i]) { + printf("ECDSA Compare fail\r\n"); + bflb_mtimer_delay_ms(1000); + } + } + + p = (uint8_t *)tmp_keyy; + + for (i = 0; i < 32; i++) { + if (ecdsa_s[i] != p[i]) { + printf("ECDSA Compare fail\r\n"); + bflb_mtimer_delay_ms(1000); + } + } + + time = (unsigned int)bflb_mtimer_get_time_ms(); + + if (0 != bflb_sec_ecdsa_verify(&ecdsa_handle, (uint32_t *)ecdsa_hash, sizeof(ecdsa_hash) / 4, tmp_keyx, tmp_keyy)) { + printf("Verify Fail\r\n"); + } else { + printf("ECDSA verify time=%dms\r\n", (unsigned int)bflb_mtimer_get_time_ms() - time); + printf("Verify Success\r\n"); + } + + while (1) { + bflb_mtimer_delay_ms(2000); + } +} \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_ecdsa/proj.conf b/examples/peripherals/sec_eng/sec_eng_ecdsa/proj.conf new file mode 100644 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_ecdsa/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_sha/main.c b/examples/peripherals/sec_eng/sec_eng_sha/main.c index 5c16940e..c1d29682 100644 --- a/examples/peripherals/sec_eng/sec_eng_sha/main.c +++ b/examples/peripherals/sec_eng/sec_eng_sha/main.c @@ -156,6 +156,8 @@ int main(void) sha = bflb_device_get_by_name("sha"); + bflb_group0_request_sha_access(sha); + bflb_sha_init(sha, SHA_MODE_SHA1); for (uint8_t i = 0; i < 3; i++) { @@ -247,6 +249,7 @@ int main(void) bflb_data_compare(sha512_test_sum[i + 3], sha_output_buf, 20); } printf("sha512 success\r\n"); + bflb_group0_release_sha_access(sha); while (1) { bflb_mtimer_delay_ms(2000); } diff --git a/examples/peripherals/sec_eng/sec_eng_sha_link/CMakeLists.txt b/examples/peripherals/sec_eng/sec_eng_sha_link/CMakeLists.txt new file mode 100644 index 00000000..04d7ac85 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_sha_link/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(sec_eng_sha_link) diff --git a/examples/peripherals/sec_eng/sec_eng_sha_link/Makefile b/examples/peripherals/sec_eng/sec_eng_sha_link/Makefile new file mode 100644 index 00000000..44367c02 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_sha_link/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/peripherals/sec_eng/sec_eng_sha_link/main.c b/examples/peripherals/sec_eng/sec_eng_sha_link/main.c new file mode 100644 index 00000000..bf84e318 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_sha_link/main.c @@ -0,0 +1,123 @@ +#include "bflb_mtimer.h" +#include "bflb_sec_sha.h" +#include "board.h" + +const uint8_t sha256_testbuf[2][104 + 1] = { + { "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz" }, + { "zyxwvutsrqponmlkjihgfedcbazyxwvutsrqponmlkjihgfedcbazyxwvutsrqponmlkjihgfedcbazyxwvutsrqponmlkjihgfedcba" } +}; + +const uint8_t sha256_testsum[2][32] = { + { 0x94, 0x1a, 0xc3, 0x78, 0x68, 0x2e, 0x3d, 0xc6, + 0x62, 0x75, 0xdd, 0x49, 0xd5, 0xfb, 0x09, 0x97, + 0x87, 0x54, 0xec, 0xf4, 0x23, 0x1d, 0x18, 0xd3, + 0x03, 0x26, 0xfa, 0x51, 0x96, 0x26, 0x48, 0xec }, + { 0x0a, 0x9e, 0xfa, 0x03, 0x71, 0xcb, 0xf6, 0x78, + 0xe2, 0xd9, 0x59, 0x90, 0xa0, 0x22, 0x29, 0xe7, + 0x00, 0x78, 0x8d, 0x4a, 0x55, 0xc7, 0x8c, 0x46, + 0xab, 0xac, 0xe1, 0x40, 0x27, 0x6b, 0x7e, 0x5f } +}; + +const uint8_t sha512_testbuf[2][208 + 1] = { + { "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz" + "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz" }, + { "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz" + "abcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyzabcdefghijklmnopqrstuvwxyz" } +}; + +const uint8_t sha512_testsum[2][128] = { + { 0xa8, 0xf0, 0x5c, 0x44, 0x2c, 0x9f, 0xe7, 0xad, + 0xdb, 0x7b, 0xec, 0xc4, 0x13, 0xe3, 0x5b, 0xf4, + 0x81, 0x86, 0x5c, 0x8a, 0xd7, 0x85, 0xb0, 0xd0, + 0x17, 0x60, 0x40, 0x22, 0xca, 0xfd, 0xd1, 0x4e, + 0xb5, 0x82, 0xb8, 0xa0, 0xa6, 0x78, 0x59, 0x72, + 0xc9, 0xf9, 0x9c, 0x31, 0x9c, 0x7b, 0xf0, 0x27, + 0xb6, 0x28, 0x16, 0x7a, 0x0b, 0xad, 0xf6, 0xd5, + 0x84, 0x21, 0xc5, 0x75, 0x9c, 0x85, 0xc3, 0x37 }, + + { 0xa8, 0xf0, 0x5c, 0x44, 0x2c, 0x9f, 0xe7, 0xad, + 0xdb, 0x7b, 0xec, 0xc4, 0x13, 0xe3, 0x5b, 0xf4, + 0x81, 0x86, 0x5c, 0x8a, 0xd7, 0x85, 0xb0, 0xd0, + 0x17, 0x60, 0x40, 0x22, 0xca, 0xfd, 0xd1, 0x4e, + 0xb5, 0x82, 0xb8, 0xa0, 0xa6, 0x78, 0x59, 0x72, + 0xc9, 0xf9, 0x9c, 0x31, 0x9c, 0x7b, 0xf0, 0x27, + 0xb6, 0x28, 0x16, 0x7a, 0x0b, 0xad, 0xf6, 0xd5, + 0x84, 0x21, 0xc5, 0x75, 0x9c, 0x85, 0xc3, 0x37 } +}; + +static struct bflb_sha_link_s sha256_link = { + .sha_mode = SHA_MODE_SHA256, /* Sha-256 */ + .sha_newhash_dis = 0, /* New hash */ + .sha_intclr = 0, /* Not clear interrupt */ + .sha_intset = 0, /* Not set interrupt */ + .sha_mode_ext = 0, + .sha_msglen = 1, /* Number of 512-bit block */ + .sha_srcaddr = 0, /* Message source address */ + { 0 } /* Result of SHA */ +}; + +static struct bflb_sha_link_s sha512_link = { + .sha_mode = SHA_MODE_SHA512, /* Sha-512 */ + .sha_newhash_dis = 0, /* New hash */ + .sha_intclr = 0, /* Not clear interrupt */ + .sha_intset = 0, /* Not set interrupt */ + .sha_mode_ext = 0, + .sha_msglen = 1, /* Number of 512-bit block */ + .sha_srcaddr = 0, /* Message source address */ + { 0 } /* Result of SHA */ +}; + +ATTR_NOCACHE_RAM_SECTION __attribute__((aligned(32))) uint8_t sha_input_buf[1000]; + +uint8_t sha_output_buf[128]; + +ATTR_NOCACHE_RAM_SECTION struct bflb_sha256_ctx_s ctx_sha256; +ATTR_NOCACHE_RAM_SECTION struct bflb_sha512_ctx_s ctx_sha512; + +static uint32_t bflb_data_compare(const uint8_t *expected, uint8_t *input, uint32_t len) +{ + int i = 0; + for (i = 0; i < len; i++) { + if (input[i] != expected[i]) { + printf("Compare fail at %d,input %02x, but expect %02x\r\n", i, input[i], expected[i]); + while (1) { + } + } + } + + return 0; +} + +int main(void) +{ + board_init(); + + struct bflb_device_s *sha; + + sha = bflb_device_get_by_name("sha"); + + bflb_group0_request_sha_access(sha); + + bflb_sha_link_init(sha); + + bflb_sha256_link_start(sha, &ctx_sha256); + memcpy(sha_input_buf, sha256_testbuf[0], 104); + bflb_sha256_link_update(sha, &ctx_sha256, (uint32_t)&sha256_link, sha_input_buf, 80); + bflb_sha256_link_update(sha, &ctx_sha256, (uint32_t)&sha256_link, &sha_input_buf[80], 104 - 80); + bflb_sha256_link_finish(sha, &ctx_sha256, (uint32_t)&sha256_link, sha_output_buf); + bflb_data_compare(sha256_testsum[0], sha_output_buf, 32); + printf("sha256 link success\r\n"); + + bflb_sha512_link_start(sha, &ctx_sha512); + memcpy(sha_input_buf, sha512_testbuf[0], 208); + bflb_sha512_link_update(sha, &ctx_sha512, (uint32_t)&sha512_link, sha_input_buf, 160); + bflb_sha512_link_update(sha, &ctx_sha512, (uint32_t)&sha512_link, &sha_input_buf[160], 208 - 80); + bflb_sha512_link_finish(sha, &ctx_sha512, (uint32_t)&sha512_link, sha_output_buf); + bflb_data_compare(sha512_testsum[0], sha_output_buf, 64); + printf("sha512 link success\r\n"); + + bflb_group0_release_sha_access(sha); + while (1) { + bflb_mtimer_delay_ms(2000); + } +} \ No newline at end of file diff --git a/examples/peripherals/sec_eng/sec_eng_sha_link/proj.conf b/examples/peripherals/sec_eng/sec_eng_sha_link/proj.conf new file mode 100644 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/sec_eng/sec_eng_sha_link/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/timer/main.c b/examples/peripherals/timer/main.c deleted file mode 100644 index ff83f80a..00000000 --- a/examples/peripherals/timer/main.c +++ /dev/null @@ -1,53 +0,0 @@ -#include "bflb_mtimer.h" -#include "bflb_timer.h" -#include "board.h" - -#define TEST_TIMER_COMP_ID TIMER_COMP_ID_0 - -struct bflb_device_s *timer0; - -void timer0_isr(int irq, void *arg) -{ - bool status = bflb_timer_get_compint_status(timer0, TIMER_COMP_ID_0); - if (status) { - printf("timer0 comp0 trigger\r\n"); - bflb_timer_compint_clear(timer0, TIMER_COMP_ID_0); - } - status = bflb_timer_get_compint_status(timer0, TIMER_COMP_ID_1); - if (status) { - printf("timer0 comp1 trigger\r\n"); - bflb_timer_compint_clear(timer0, TIMER_COMP_ID_1); - } - status = bflb_timer_get_compint_status(timer0, TIMER_COMP_ID_2); - if (status) { - printf("timer0 comp2 trigger\r\n"); - bflb_timer_compint_clear(timer0, TIMER_COMP_ID_2); - } -} - -int main(void) -{ - board_init(); - - /* timer clk = XCLK/(div + 1 )*/ - struct bflb_timer_config_s cfg; - cfg.counter_mode = TIMER_COUNTER_MODE_PROLOAD; - cfg.clock_source = BFLB_SYSTEM_XCLK; - cfg.clock_div = 39; /* for bl616/bl808/bl606p is 39, for bl702 is 31 */ - cfg.trigger_comp_id = TEST_TIMER_COMP_ID; - cfg.comp0_val = 1000000; - cfg.comp1_val = 2000000; - cfg.comp2_val = 3000000; - cfg.preload_val = 0; - - timer0 = bflb_device_get_by_name("timer0"); - - bflb_timer_init(timer0, &cfg); - bflb_irq_attach(timer0->irq_num, timer0_isr, timer0); - bflb_irq_enable(timer0->irq_num); - bflb_timer_start(timer0); - while (1) { - printf("helloworld\r\n"); - bflb_mtimer_delay_ms(1500); - } -} diff --git a/examples/peripherals/timer/timer_int/CMakeLists.txt b/examples/peripherals/timer/timer_int/CMakeLists.txt new file mode 100644 index 00000000..a6bae051 --- /dev/null +++ b/examples/peripherals/timer/timer_int/CMakeLists.txt @@ -0,0 +1,9 @@ +cmake_minimum_required(VERSION 3.15) + +include(proj.conf) + +find_package(bouffalo_sdk REQUIRED HINTS $ENV{BL_SDK_BASE}) + +sdk_set_main_file(main.c) + +project(timer_int) diff --git a/examples/peripherals/timer/timer_int/Makefile b/examples/peripherals/timer/timer_int/Makefile new file mode 100644 index 00000000..44367c02 --- /dev/null +++ b/examples/peripherals/timer/timer_int/Makefile @@ -0,0 +1,13 @@ +SDK_DEMO_PATH ?= . +BL_SDK_BASE ?= $(SDK_DEMO_PATH)/../../../.. + +export BL_SDK_BASE + +CHIP ?= bl616 +BOARD ?= bl616dk +CROSS_COMPILE ?= riscv64-unknown-elf- + +# add custom cmake definition +#cmake_definition+=-Dxxx=sss + +include $(BL_SDK_BASE)/project.build diff --git a/examples/peripherals/timer/timer_int/main.c b/examples/peripherals/timer/timer_int/main.c new file mode 100644 index 00000000..3bc57ef6 --- /dev/null +++ b/examples/peripherals/timer/timer_int/main.c @@ -0,0 +1,93 @@ +#include "bflb_mtimer.h" +#include "bflb_timer.h" +#include "board.h" +#define TEST_TIMER_COMP_ID TIMER_COMP_ID_2 + +struct bflb_device_s *timer0; +struct bflb_device_s *timer1; + +void timer0_isr(int irq, void *arg) +{ + bool status = bflb_timer_get_compint_status(timer0, TIMER_COMP_ID_0); + if (status) { + printf("timer0 comp0 trigger\r\n"); + bflb_timer_compint_clear(timer0, TIMER_COMP_ID_0); + } + status = bflb_timer_get_compint_status(timer0, TIMER_COMP_ID_1); + if (status) { + printf("timer0 comp1 trigger\r\n"); + bflb_timer_compint_clear(timer0, TIMER_COMP_ID_1); + } + status = bflb_timer_get_compint_status(timer0, TIMER_COMP_ID_2); + if (status) { + printf("timer0 comp2 trigger\r\n"); + bflb_timer_compint_clear(timer0, TIMER_COMP_ID_2); + } +} + +void timer1_isr(int irq, void *arg) +{ + bool status = bflb_timer_get_compint_status(timer1, TIMER_COMP_ID_0); + if (status) { + printf("timer1 comp0 trigger\r\n"); + bflb_timer_compint_clear(timer1, TIMER_COMP_ID_0); + } + status = bflb_timer_get_compint_status(timer1, TIMER_COMP_ID_1); + if (status) { + printf("timer1 comp1 trigger\r\n"); + bflb_timer_compint_clear(timer1, TIMER_COMP_ID_1); + } + status = bflb_timer_get_compint_status(timer1, TIMER_COMP_ID_2); + if (status) { + printf("timer1 comp2 trigger\r\n"); + bflb_timer_compint_clear(timer1, TIMER_COMP_ID_2); + } +} + +int main(void) +{ + board_init(); + printf("Timer basic test\n"); + + /* timer clk = XCLK/(div + 1 )*/ + struct bflb_timer_config_s cfg0; + cfg0.counter_mode = TIMER_COUNTER_MODE_PROLOAD; /* preload when match occur */ + cfg0.clock_source = TIMER_CLKSRC_XTAL; + cfg0.clock_div = 0; /* for bl616/bl808/bl606p is 39, for bl702 is 31 */ + cfg0.trigger_comp_id = TEST_TIMER_COMP_ID; + cfg0.comp0_val = 230000; /* match value 0 */ + cfg0.comp1_val = 260000; /* match value 1 */ + cfg0.comp2_val = 290000; /* match value 2 */ + cfg0.preload_val = 0; /* preload value */ + + struct bflb_timer_config_s cfg1; + cfg1.counter_mode = TIMER_COUNTER_MODE_PROLOAD; + cfg1.clock_source = TIMER_CLKSRC_XTAL; + cfg1.clock_div = 0; /* for bl616/bl808/bl606p is 39, for bl702 is 31 */ + cfg1.trigger_comp_id = TEST_TIMER_COMP_ID; + cfg1.comp0_val = 330000; /* match value 0 */ + cfg1.comp1_val = 360000; /* match value 1 */ + cfg1.comp2_val = 390000; /* match value 2 */ + cfg1.preload_val = 0; /* preload value */ + + timer0 = bflb_device_get_by_name("timer0"); + timer1 = bflb_device_get_by_name("timer1"); + + /* Timer init with default configuration */ + bflb_timer_init(timer0, &cfg0); + bflb_timer_init(timer1, &cfg1); + + bflb_irq_attach(timer0->irq_num, timer0_isr, timer0); + bflb_irq_attach(timer1->irq_num, timer1_isr, timer1); + bflb_irq_enable(timer0->irq_num); + bflb_irq_enable(timer1->irq_num); + + /* Enable timer */ + bflb_timer_start(timer0); + bflb_timer_start(timer1); + + printf("case success.\r\n"); + while (1) { + bflb_mtimer_delay_ms(1500); + } +} diff --git a/examples/peripherals/timer/timer_int/proj.conf b/examples/peripherals/timer/timer_int/proj.conf new file mode 100644 index 00000000..13320d67 --- /dev/null +++ b/examples/peripherals/timer/timer_int/proj.conf @@ -0,0 +1 @@ +#set(CONFIG_XXX 1) \ No newline at end of file diff --git a/examples/peripherals/uart/uart_auto_baudrate/main.c b/examples/peripherals/uart/uart_auto_baudrate/main.c index c794e9d6..30a273e9 100644 --- a/examples/peripherals/uart/uart_auto_baudrate/main.c +++ b/examples/peripherals/uart/uart_auto_baudrate/main.c @@ -5,28 +5,25 @@ struct bflb_device_s *uart1; -static uint32_t uart_txbuf[3]; - void uart_isr(int irq, void *arg) { uint32_t intstatus = bflb_uart_get_intstatus(uart1); + int ret; + uint32_t baudrate; if (intstatus & UART_INTSTS_RX_AD5) { - uart_txbuf[0] = UART_AUTO_BAUD_0X55; - bflb_uart_feature_control(uart1, UART_CMD_GET_AUTO_BAUD, (uint32_t)uart_txbuf); - uint32_t baudrate = 40000000 / (uart_txbuf[1] + 1); + ret = bflb_uart_feature_control(uart1, UART_CMD_GET_AUTO_BAUD, UART_AUTO_BAUD_0X55); + baudrate = 40000000 / (ret + 1); printf("Detected baudrate by 0x55 is %d\r\n", baudrate); } bflb_uart_int_clear(uart1, UART_INTCLR_RX_AD5); if (intstatus & UART_INTSTS_RX_ADS) { - uart_txbuf[0] = UART_AUTO_BAUD_START; - bflb_uart_feature_control(uart1, UART_CMD_GET_AUTO_BAUD, (uint32_t)uart_txbuf); - uint32_t baudrate = 40000000 / (uart_txbuf[1] + 1); + ret = bflb_uart_feature_control(uart1, UART_CMD_GET_AUTO_BAUD, UART_AUTO_BAUD_START); + baudrate = 40000000 / (ret + 1); printf("Detected baudrate by startbit is %d\r\n", baudrate); } bflb_uart_int_clear(uart1, UART_INTCLR_RX_ADS); - } int main(void) @@ -48,9 +45,11 @@ int main(void) bflb_uart_init(uart1, &cfg); bflb_uart_feature_control(uart1, UART_CMD_SET_AUTO_BAUD, 1); - bflb_uart_feature_control(uart1, UART_CMD_SET_ABR_PW_VALUE, 3); + bflb_uart_feature_control(uart1, UART_CMD_SET_ABR_ALLOWABLE_ERROR, 3); bflb_irq_attach(uart1->irq_num, uart_isr, uart1); bflb_irq_enable(uart1->irq_num); + while (1) { + } } diff --git a/examples/peripherals/uart/uart_cts_rts/main.c b/examples/peripherals/uart/uart_cts_rts/main.c index 8dbc65b1..b3b5bf39 100644 --- a/examples/peripherals/uart/uart_cts_rts/main.c +++ b/examples/peripherals/uart/uart_cts_rts/main.c @@ -37,7 +37,7 @@ int main(void) cfg.data_bits = UART_DATA_BITS_8; cfg.stop_bits = UART_STOP_BITS_1; cfg.parity = UART_PARITY_NONE; - cfg.flow_ctrl = UART_FLOWCTRL_RTS; + cfg.flow_ctrl = 0; cfg.tx_fifo_threshold = 7; cfg.rx_fifo_threshold = 7; bflb_uart_init(uart1, &cfg); @@ -46,8 +46,9 @@ int main(void) bflb_irq_attach(uart1->irq_num, uart_isr, uart1); bflb_irq_enable(uart1->irq_num); + bflb_uart_feature_control(uart1, UART_CMD_SET_SW_RTS_CONTROL, true); + bflb_uart_feature_control(uart1, UART_CMD_SET_RTS_VALUE, 0); while (1) { - printf("helloworld\r\n"); bflb_mtimer_delay_ms(2000); } } diff --git a/examples/peripherals/uart/uart_dma/main.c b/examples/peripherals/uart/uart_dma/main.c index 2c1a0b3b..0f5c2fda 100644 --- a/examples/peripherals/uart/uart_dma/main.c +++ b/examples/peripherals/uart/uart_dma/main.c @@ -130,7 +130,6 @@ int main(void) printf("receive data:%02x\r\n", receive_buffer[i]); } while (1) { - printf("helloworld\r\n"); bflb_mtimer_delay_ms(2000); } } diff --git a/examples/peripherals/uart/uart_fifo_interrupt/main.c b/examples/peripherals/uart/uart_fifo_interrupt/main.c index c88889fa..39e4fe55 100644 --- a/examples/peripherals/uart/uart_fifo_interrupt/main.c +++ b/examples/peripherals/uart/uart_fifo_interrupt/main.c @@ -62,7 +62,6 @@ int main(void) bflb_irq_enable(uart1->irq_num); while (1) { - printf("helloworld\r\n"); bflb_mtimer_delay_ms(2000); } } diff --git a/examples/peripherals/uart/uart_rs485/main.c b/examples/peripherals/uart/uart_rs485/main.c index fe77bc42..96b1ec86 100644 --- a/examples/peripherals/uart/uart_rs485/main.c +++ b/examples/peripherals/uart/uart_rs485/main.c @@ -47,7 +47,7 @@ int main(void) bflb_uart_init(uart1, &cfg); bflb_uart_feature_control(uart1, UART_CMD_SET_TX_RS485_EN, 1); - bflb_uart_feature_control(uart1, UART_CMD_SET_TX_RS485_POL, 1); + bflb_uart_feature_control(uart1, UART_CMD_SET_TX_RS485_POLARITY, 1); for (uint8_t i = 0; i < 128; i++) { bflb_uart_putchar(uart1, uart_txbuf[i]); @@ -58,7 +58,6 @@ int main(void) bflb_irq_enable(uart1->irq_num); while (1) { - printf("helloworld\r\n"); bflb_mtimer_delay_ms(2000); } } diff --git a/examples/peripherals/wdg/wdg_int/main.c b/examples/peripherals/wdg/wdg_int/main.c index 16f57926..f685ad83 100644 --- a/examples/peripherals/wdg/wdg_int/main.c +++ b/examples/peripherals/wdg/wdg_int/main.c @@ -17,7 +17,7 @@ int main(void) printf("Watchdog interrupt test\r\n"); struct bflb_wdg_config_s wdg_cfg; - wdg_cfg.clock_source = BFLB_SYSTEM_32K_CLK; + wdg_cfg.clock_source = WDG_CLKSRC_32K; wdg_cfg.clock_div = 0; wdg_cfg.comp_val = 64000; wdg_cfg.mode = WDG_MODE_INTERRUPT; diff --git a/examples/peripherals/wdg/wdg_reset/main.c b/examples/peripherals/wdg/wdg_reset/main.c index d43d3732..0c270bee 100644 --- a/examples/peripherals/wdg/wdg_reset/main.c +++ b/examples/peripherals/wdg/wdg_reset/main.c @@ -11,7 +11,7 @@ int main(void) printf("Watchdog interrupt test\r\n"); struct bflb_wdg_config_s wdg_cfg; - wdg_cfg.clock_source = BFLB_SYSTEM_32K_CLK; + wdg_cfg.clock_source = WDG_CLKSRC_32K; wdg_cfg.clock_div = 0; wdg_cfg.comp_val = 64000; wdg_cfg.mode = WDG_MODE_RESET;