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[refactor][bl702_driver] refactor std and hal common include file, drop some flash api

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This commit is contained in:
jzlv 2021-09-26 13:53:05 +08:00
parent 26c22a0e30
commit 66ec110725
72 changed files with 1411 additions and 2655 deletions
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41
bsp/board/bl702/board.c
View File

@ -168,6 +168,8 @@ static void board_pin_mux_init(void)
uint32_t tmpVal;
gpio_cfg.drive = 0;
gpio_cfg.smtCtrl = 1;
uint8_t hbn_gpio_mask = 0x1f;
uint8_t hbn_aon_ie = 0;
for (int i = 0; i < sizeof(af_pin_table) / sizeof(af_pin_table[0]); i++) {
gpio_cfg.gpioMode = GPIO_MODE_AF;
@ -175,6 +177,12 @@ static void board_pin_mux_init(void)
gpio_cfg.gpioPin = af_pin_table[i].pin;
gpio_cfg.gpioFun = af_pin_table[i].func;
/*if using gpio9-gpio12 and func is not analog and output ,should set reg_aon_pad_ie_smt corresponding bit = 1*/
if ((af_pin_table[i].pin > GPIO_PIN_8) && (af_pin_table[i].pin < GPIO_PIN_13)) {
if ((af_pin_table[i].func != 10) && ((af_pin_table[i].func < GPIO_FUN_GPIO_OUTPUT_UP) || (af_pin_table[i].func > GPIO_FUN_GPIO_OUTPUT_NONE)))
hbn_aon_ie |= (1 << (af_pin_table[i].pin - 9));
}
/*if reset state*/
if (af_pin_table[i].func == GPIO_FUN_UNUSED) {
continue;
@ -184,14 +192,11 @@ static void board_pin_mux_init(void)
/*enable pds gpio wakeup and irq unmask*/
tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_SELECT, af_pin_table[i].pin);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_MODE, PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE);
tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_MASK);
BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
} else if ((af_pin_table[i].pin > GPIO_PIN_8) && (af_pin_table[i].pin < GPIO_PIN_13)) {
/*enable hbn gpio wakeup and irq unmask*/
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
tmpVal &= ~(1 << (af_pin_table[i].pin - 6)); //gpio unmask
tmpVal |= (1 << (af_pin_table[i].pin - 1)); //gpio ie smt
BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
hbn_gpio_mask &= ~(1 << (af_pin_table[i].pin - 9));
}
continue;
} else if (af_pin_table[i].func == GPIO_FUN_PWM) {
@ -231,6 +236,7 @@ static void board_pin_mux_init(void)
gpio_cfg.gpioFun = GPIO_FUN_GPIO;
gpio_cfg.gpioMode = GPIO_MODE_INPUT;
gpio_cfg.pullType = GPIO_PULL_UP;
if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_FALLING_EDGE) {
GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_NEG_PULSE);
} else if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_LOW_LEVEL) {
@ -240,6 +246,7 @@ static void board_pin_mux_init(void)
gpio_cfg.gpioFun = GPIO_FUN_GPIO;
gpio_cfg.gpioMode = GPIO_MODE_INPUT;
gpio_cfg.pullType = GPIO_PULL_DOWN;
if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_RISING_EDGE) {
GLB_Set_GPIO_IntMod(af_pin_table[i].pin, GLB_GPIO_INT_CONTROL_ASYNC, GLB_GPIO_INT_TRIG_POS_PULSE);
} else if (af_pin_table[i].func == GPIO_FUN_GPIO_EXTI_HIGH_LEVEL) {
@ -264,6 +271,14 @@ static void board_pin_mux_init(void)
}
GLB_GPIO_Init(&gpio_cfg);
}
/*disable unused reg_aon_pad_ie_smt bits and hbn_pin_wakeup_mask bits*/
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, hbn_gpio_mask);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, hbn_aon_ie);
tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE);
BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
}
static void board_clock_init(void)
@ -298,22 +313,6 @@ void bl_show_info(void)
void board_init(void)
{
HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_1P10V);
board_clock_init();
board_pin_mux_init();
}
int bflb_get_board_config(uint8_t func, uint8_t *pinlist)
{
uint16_t i = 0;
int len = 0;
for (i = 0; i < sizeof(af_pin_table) / sizeof(struct pin_mux_cfg); i++) {
if (af_pin_table[i].func == func) {
pinlist[len] = af_pin_table[i].pin;
len++;
}
}
return len;
}

4
drivers/bl702_driver/CMakeLists.txt
View File

@ -4,7 +4,7 @@ list(APPEND ADD_INCLUDE
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/inc"
"${CMAKE_CURRENT_SOURCE_DIR}/regs"
"${CMAKE_CURRENT_SOURCE_DIR}/startup"
"${CMAKE_CURRENT_SOURCE_DIR}/risc-v/Core/Include"
"${CMAKE_CURRENT_SOURCE_DIR}"
)
#######################################################
@ -26,6 +26,8 @@ file(GLOB_RECURSE sources
list(APPEND ADD_SRCS ${sources})
# aux_source_directory(src ADD_SRCS)
list(REMOVE_ITEM ADD_SRCS "${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl702_snflash.c"
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl702_romdriver.c"
"${CMAKE_CURRENT_SOURCE_DIR}/std_drv/src/bl702_clock.c"
)
#######################################################

53
drivers/bl702_driver/bl702_flash.ld
View File

@ -61,16 +61,17 @@ SECTIONS
*(.text.*)
/*put .rodata**/
*(EXCLUDE_FILE( *bl702_glb.o \
*bl702_pds.o \
*bl702_common.o \
*bl702_sf_cfg.o \
*bl702_sf_ctrl.o \
*bl702_sflash.o \
*bl702_xip_sflash.o \
*bl702_ef_ctrl.o) .rodata*)
*(.rodata)
*(.rodata.*)
*(EXCLUDE_FILE( *bl702_glb*.o* \
*bl702_pds*.o* \
*bl702_common*.o* \
*bl702_sf_cfg*.o* \
*bl702_sf_cfg_ext*.o* \
*bl702_sf_ctrl*.o* \
*bl702_sflash*.o* \
*bl702_sflash_ext*.o* \
*bl702_xip_sflash*.o* \
*bl702_xip_sflash_ext*.o* \
*bl702_ef_ctrl*.o*) .rodata*)
*(.srodata)
*(.srodata.*)
@ -87,19 +88,22 @@ SECTIONS
. = ALIGN(4);
__tcm_code_start__ = .;
*(.tcm_code)
*(.tcm_const)
*(.sclock_rlt_code)
*(.sclock_rlt_const)
*(.tcm_code.*)
*(.tcm_const.*)
*(.sclock_rlt_code.*)
*(.sclock_rlt_const.*)
*bl702_glb.o*(.rodata*)
*bl702_pds.o*(.rodata*)
*bl702_common.o*(.rodata*)
*bl702_sf_cfg.o*(.rodata*)
*bl702_sf_ctrl.o*(.rodata*)
*bl702_sflash.o*(.rodata*)
*bl702_xip_sflash.o*(.rodata*)
*bl702_ef_ctrl.o*(.rodata*)
*bl702_glb*.o*(.rodata*)
*bl702_pds*.o*(.rodata*)
*bl702_common*.o*(.rodata*)
*bl702_sf_cfg*.o*(.rodata*)
*bl702_sf_cfg_ext*.o*(.rodata*)
*bl702_sf_ctrl*.o*(.rodata*)
*bl702_sflash*.o*(.rodata*)
*bl702_sflash_ext*.o*(.rodata*)
*bl702_xip_sflash*.o*(.rodata*)
*bl702_xip_sflash_ext*.o*(.rodata*)
*bl702_ef_ctrl*.o*(.rodata*)
. = ALIGN(4);
__tcm_code_end__ = .;
@ -111,9 +115,8 @@ SECTIONS
{
. = ALIGN(4);
__hbn_ram_start__ = .;
*(EXCLUDE_FILE(*bl702_hbn_wakeup.o).rodata*)
*bl702_hbn_wakeup.o*(.rodata*)
*(.hbn_ram_code)
*bl702_hbn_wakeup*.o*(.rodata*)
*(.hbn_ram_code*)
*(.hbn_ram_data)
. = ALIGN(4);
__hbn_ram_end__ = .;

8
drivers/bl702_driver/bl702_ram.ld
View File

@ -48,10 +48,10 @@ SECTIONS
*(.srodata)
*(.srodata.*)
*(.tcm_code)
*(.tcm_const)
*(.sclock_rlt_code)
*(.sclock_rlt_const)
*(.tcm_code.*)
*(.tcm_const.*)
*(.sclock_rlt_code.*)
*(.sclock_rlt_const.*)
. = ALIGN(4);
__text_code_end__ = .;

34
drivers/bl702_driver/blsp_boot2_iap_flash.ld
View File

@ -40,15 +40,7 @@ SECTIONS
KEEP (*(.text.metal.init.enter))
KEEP (*(SORT_NONE(.init)))
/* section information for finsh shell */
. = ALIGN(4);
_shell_command_start = .;
KEEP(*(shellCommand))
_shell_command_end = .;
*(EXCLUDE_FILE ( *bl702_uart.c.obj* *hal_uart.c.obj* ) .text*)
/* section information for usb desc */
. = ALIGN(4);
_usb_desc_start = .;
@ -56,6 +48,8 @@ SECTIONS
. = ALIGN(4);
_usb_desc_end = .;
*(EXCLUDE_FILE ( *bl702_uart*.o* *hal_uart*.o* ) .text*)
*(.rodata)
*(.rodata.*)
*(.srodata)
@ -72,18 +66,18 @@ SECTIONS
{
. = ALIGN(4);
__tcm_code_start__ = .;
*(.tcm_code)
*(.tcm_const)
*(.sclock_rlt_code)
*(.sclock_rlt_const)
*bl602_romapi.o(.text)
*bl602_romapi.o(.text.*)
*bl602_romapi.o(.rodata)
*bl602_romapi.o(.rodata.*)
*bl602_romapi.o(.srodata)
*bl602_romapi.o(.srodata.*)
*bl702_uart.c.obj* (.text*)
*hal_uart.c.obj* (.text*)
*(.tcm_code.*)
*(.tcm_const.*)
*(.sclock_rlt_code.*)
*(.sclock_rlt_const.*)
*bl702_romapi*.o*(.text)
*bl702_romapi*.o*(.text.*)
*bl702_romapi*.o*(.rodata)
*bl702_romapi*.o*(.rodata.*)
*bl702_romapi*.o*(.srodata)
*bl702_romapi*.o*(.srodata.*)
*bl702_uart*.o* (.text*)
*hal_uart*.o* (.text*)
. = ALIGN(4);
__tcm_code_end__ = .;

12
drivers/bl702_driver/hal_drv/inc/hal_acomp.h
View File

@ -1,8 +1,11 @@
#ifndef __HAL_ACOMP_H__
#define __HAL_ACOMP_H__
#include "drv_device.h"
#include "bl702_config.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
enum acomp_channel_type {
ACOMP_CHANNEL_ADC_CHANNEL0, /*!< Analog compare channel,ADC input channel 0 */
@ -43,6 +46,11 @@ typedef struct acomp_device {
enum acomp_hysteresis_vol_type neg_hysteresis_vol;
} acomp_device_t;
void acomp_init(acomp_device_t *device);
int acomp_get_result(acomp_device_t *device);
#ifdef __cplusplus
}
#endif
#endif

37
drivers/bl702_driver/hal_drv/inc/hal_adc.h
View File

@ -23,8 +23,11 @@
#ifndef __HAL_ADC__H__
#define __HAL_ADC__H__
#include "drv_device.h"
#include "bl702_config.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#define DEVICE_CTRL_ADC_CHANNEL_START 0x10
#define DEVICE_CTRL_ADC_CHANNEL_STOP 0x11
@ -41,24 +44,6 @@ enum adc_index_type {
ADC_MAX_INDEX
};
enum adc_event_type {
ADC_EVEN_INT_POS_SATURATION,
ADC_EVEN_INT_NEG_SATURATION,
ADC_EVENT_UNDERRUN,
ADC_EVENT_OVERRUN,
ADC_EVENT_REVERSED,
ADC_EVENT_FIFO_READY,
ADC_EVEN_MAX,
};
enum adc_it_type {
ADC_EVENT_FIFO_READY_IT = 1 << 0,
ADC_EVENT_OVERRUN_IT = 1 << 1,
ADC_EVENT_UNDERRUN_IT = 1 << 2,
ADC_EVEN_INT_POS_SATURATION_IT = 1 << 3,
ADC_EVEN_INT_NEG_SATURATION_IT = 1 << 4,
};
#define adc_channel_start(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_START, NULL)
#define adc_channel_stop(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_STOP, NULL)
#define adc_channel_config(dev, list) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_CONFIG, list)
@ -140,6 +125,15 @@ typedef enum {
ADC_GAIN_32, /*!< PGA gain 32 */
} adc_pga_gain_t;
enum adc_event_type {
ADC_EVENT_FIFO,
UART_EVENT_UNKNOWN
};
enum adc_it_type {
ADC_FIFO_IT = 1 << 0,
};
typedef struct
{
uint8_t *pos_channel;
@ -172,4 +166,7 @@ int adc_register(enum adc_index_type index, const char *name);
int adc_trim_tsen(uint16_t *tsen_offset);
float adc_get_tsen(uint16_t tsen_offset);
#ifdef __cplusplus
}
#endif
#endif

14
drivers/bl702_driver/hal_drv/inc/hal_boot2.h
View File

@ -36,7 +36,11 @@
#ifndef __HAL_BOOT2_H__
#define __HAL_BOOT2_H__
#include "drv_device.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "bl702_sflash.h"
#include "bl702_glb.h"
@ -54,8 +58,6 @@
#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM 0 /* 1 support decompress, 0 not support */
#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 1 /* 1 support decompress, 0 not support */
typedef struct
{
uint8_t encrypted[HAL_EFUSE_CPU_MAX];
@ -108,4 +110,10 @@ void hal_boot2_debug_uart_gpio_init(void);
#if HAL_BOOT2_SUPPORT_USB_IAP
void hal_boot2_debug_usb_port_init(void);
#endif
void hal_boot2_debug_uart_gpio_deinit(void);
#ifdef __cplusplus
}
#endif
#endif

10
drivers/bl702_driver/hal_drv/inc/hal_cam.h
View File

@ -24,9 +24,12 @@
#ifndef __HAL_CAM_H__
#define __HAL_CAM_H__
#include "drv_device.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "bl702_cam.h"
#include "bl702_config.h"
#define DEVICE_OFLAG_INT 0x01
#define DEVICE_OFLAG_POLL 0x02
@ -90,4 +93,7 @@ void cam_vsync_crop(uint16_t start, uint16_t end);
void cam_hw_mode_wrap(uint8_t enbale);
void CAM_Int_Callback_set(CAM_INT_Type intType, intCallback_Type *cbFun);
#ifdef __cplusplus
}
#endif
#endif

22
drivers/bl702_driver/hal_drv/inc/hal_clock.h
View File

@ -23,8 +23,11 @@
#ifndef __HAL_CLOCK__H__
#define __HAL_CLOCK__H__
#include "drv_device.h"
#include "bl702_config.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
/*XTAL_TYPE*/
#define XTAL_NONE 0
@ -48,13 +51,14 @@
#define ROOT_CLOCK_SOURCE_32K_CLK 5
#define ROOT_CLOCK_SOURCE_FCLK 6
#define ROOT_CLOCK_SOURCE_BCLK 7
#define ROOT_CLOCK_SOURCE_1K_CLK 8
/*BSP_AUDIO_PLL_CLOCK_SOURCE*/
#define ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ 8
#define ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ 9
#define ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ 10
#define ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ 11
#define ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ 12
#define ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ 9
#define ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ 10
#define ROOT_CLOCK_SOURCE_AUPLL_5644800_HZ 11
#define ROOT_CLOCK_SOURCE_AUPLL_24576000_HZ 12
#define ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ 13
enum system_clock_type {
SYSTEM_CLOCK_ROOT_CLOCK = 0, /* clock source before fclk_div*/
@ -79,7 +83,11 @@ enum peripheral_clock_type {
void system_clock_init(void);
void system_mtimer_clock_init(void);
void system_mtimer_clock_reinit(void);
void peripheral_clock_init(void);
uint32_t system_clock_get(enum system_clock_type type);
uint32_t peripheral_clock_get(enum peripheral_clock_type type);
#ifdef __cplusplus
}
#endif
#endif

47
drivers/bl702_driver/hal_drv/inc/hal_common.h Normal file
View File

@ -0,0 +1,47 @@
/**
* @file hal_common.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_COMMON__H__
#define __HAL_COMMON__H__
#ifdef __cplusplus
extern "C" {
#endif
#include "drv_device.h"
#include "bl702_common.h"
#include "bl702_config.h"
void cpu_global_irq_enable(void);
void cpu_global_irq_disable(void);
void hal_system_reset(void);
void hal_cpu_reset(void);
void hal_get_chip_id(uint8_t chip_id[8]);
void hal_enter_usb_iap(void);
void hal_jump2app(uint32_t flash_offset);
int hal_get_trng_seed(void);
#ifdef __cplusplus
}
#endif
#endif

11
drivers/bl702_driver/hal_drv/inc/hal_dac.h
View File

@ -23,8 +23,11 @@
#ifndef __HAL_DAC__H__
#define __HAL_DAC__H__
#include "drv_device.h"
#include "bl702_config.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
enum dac_index_type {
#ifdef BSP_USING_DAC0
@ -64,5 +67,7 @@ typedef struct dac_device {
#define DAC_DEV(dev) ((adc_device_t *)dev)
int dac_register(enum dac_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

11
drivers/bl702_driver/hal_drv/inc/hal_dma.h
View File

@ -23,8 +23,11 @@
#ifndef __HAL_DMA__H__
#define __HAL_DMA__H__
#include "drv_device.h"
#include "bl702_config.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#define DMA_CHANNEL_GET_STATUS 0x10
#define DMA_CHANNEL_START 0x11
@ -195,5 +198,7 @@ typedef struct dma_device {
int dma_register(enum dma_index_type index, const char *name);
int dma_allocate_register(const char *name);
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size);
#ifdef __cplusplus
}
#endif
#endif

26
drivers/bl702_driver/hal_drv/inc/hal_emac.h
View File

@ -24,9 +24,12 @@
#ifndef __HAL_EMAC_H__
#define __HAL_EMAC_H__
#include "drv_device.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#include "bl702_emac.h"
#include "bl702_config.h"
typedef struct emac_device {
struct device parent;
@ -53,6 +56,17 @@ typedef struct
uint32_t phy_id; /*!< PHY OUI */
} emac_phy_cfg_t;
#define FULL_PACKET (uint32_t)(-1)
#define NOFULL_PACKET (uint32_t)(0)
#ifndef ETH_TX_BUFFER_SIZE
#define ETH_TX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE)
#endif
#ifndef ETH_RX_BUFFER_SIZE
#define ETH_RX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE)
#endif
#define EMAC_TX_COMMON_FLAGS (EMAC_BD_FIELD_MSK(TX_RD) | \
EMAC_BD_FIELD_MSK(TX_IRQ) | \
EMAC_BD_FIELD_MSK(TX_PAD) | \
@ -84,5 +98,11 @@ int emac_phy_reg_read(uint16_t phyReg, uint16_t *regValue);
int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue);
int emac_stop(void);
int emac_start(void);
int emac_start_tx(void);
int emac_stop_tx(void);
int emac_start_rx(void);
int emac_stop_rx(void);
#ifdef __cplusplus
}
#endif
#endif

9
drivers/bl702_driver/hal_drv/inc/hal_flash.h
View File

@ -23,8 +23,11 @@
#ifndef __HAL_FLASH__H__
#define __HAL_FLASH__H__
#include "drv_device.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#define FLASH_NOT_DETECT 0x10
#define BL_FLASH_XIP_BASE BL702_FLASH_XIP_BASE
@ -37,5 +40,7 @@ BL_Err_Type flash_write(uint32_t addr, uint8_t *data, uint32_t len);
BL_Err_Type flash_erase(uint32_t startaddr, uint32_t len);
BL_Err_Type flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset);
BL_Err_Type flash_get_cfg(uint8_t **cfg_addr, uint32_t *len);
#ifdef __cplusplus
}
#endif
#endif

10
drivers/bl702_driver/hal_drv/inc/hal_gpio.h
View File

@ -23,7 +23,11 @@
#ifndef __HAL_GPIO__H__
#define __HAL_GPIO__H__
#include "drv_device.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
enum gpio_pin_type {
GPIO_PIN_0 = 0,
@ -83,4 +87,8 @@ void gpio_toggle(uint32_t pin);
int gpio_read(uint32_t pin);
void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin));
void gpio_irq_enable(uint32_t pin, uint8_t enabled);
#ifdef __cplusplus
}
#endif
#endif

10
drivers/bl702_driver/hal_drv/inc/hal_i2c.h
View File

@ -23,8 +23,11 @@
#ifndef __HAL_I2C__H__
#define __HAL_I2C__H__
#include "drv_device.h"
#include "bl702_config.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
enum i2c_index_type {
#ifdef BSP_USING_I2C0
@ -64,4 +67,7 @@ typedef struct i2c_device {
int i2c_register(enum i2c_index_type index, const char *name);
int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num);
#ifdef __cplusplus
}
#endif
#endif

15
drivers/bl702_driver/hal_drv/inc/hal_i2s.h
View File

@ -23,11 +23,14 @@
#ifndef __HAL_I2S__H__
#define __HAL_I2S__H__
#include "drv_device.h"
#include "bl702_config.h"
#ifdef __cplusplus
extern "C"{
#endif
#define I2S_GET_TX_FIFO_CMD 0x10
#define I2S_GET_RX_FIFO_CMD 0x11
#include "hal_common.h"
#define DEVICE_CTRL_I2S_GET_TX_FIFO 0x10
#define DEVICE_CTRL_I2S_GET_RX_FIFO 0x11
enum i2s_index_type {
#ifdef BSP_USING_I2S0
@ -111,4 +114,8 @@ typedef struct i2s_device {
int i2s_register(enum i2s_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

9
drivers/bl702_driver/hal_drv/inc/hal_keyscan.h
View File

@ -22,9 +22,11 @@
*/
#ifndef __HAL_KEYSCAN__H__
#define __HAL_KEYSCAN__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "drv_device.h"
#include "bl702_config.h"
#include "hal_common.h"
#define DEVICE_CTRL_KEYSCAN_GET_KEYCODE 0x10
@ -86,4 +88,7 @@ typedef struct keyscan_device {
int keyscan_register(enum keyscan_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

9
drivers/bl702_driver/hal_drv/inc/hal_mjpeg.h
View File

@ -22,9 +22,11 @@
*/
#ifndef __HAL_MJPEG__H__
#define __HAL_MJPEG__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "drv_device.h"
#include "bl702_config.h"
#include "hal_common.h"
#define MJPEG_PACKET_ADD_NONE 0
#define MJPEG_PACKET_ADD_DEFAULT 1 << 0
@ -66,4 +68,7 @@ void mjpeg_stop(void);
uint8_t mjpeg_get_one_frame(uint8_t **pic, uint32_t *len, uint8_t *q);
void mjpeg_drop_one_frame(void);
#ifdef __cplusplus
}
#endif
#endif

9
drivers/bl702_driver/hal_drv/inc/hal_mtimer.h
View File

@ -25,9 +25,18 @@
#include "stdint.h"
#ifdef __cplusplus
extern "C"{
#endif
void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void));
uint64_t mtimer_get_time_ms();
uint64_t mtimer_get_time_us();
void mtimer_delay_ms(uint32_t time);
void mtimer_delay_us(uint32_t time);
#ifdef __cplusplus
}
#endif
#endif

11
drivers/bl702_driver/hal_drv/inc/hal_pm.h
View File

@ -23,8 +23,11 @@
#ifndef __HAL_PM__H__
#define __HAL_PM__H__
#include "drv_device.h"
#include "bl702_config.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
enum pm_pds_sleep_level {
PM_PDS_LEVEL_0,
@ -61,5 +64,9 @@ void pm_hbn_enter_again(bool reset);
void pm_hbn_out0_irq_register(void);
void pm_hbn_out1_irq_register(void);
void pm_irq_callback(enum pm_event_type event);
uint32_t hal_pds_enter_with_time_compensation(uint32_t pdsLevel, uint32_t pdsSleepCycles);
#ifdef __cplusplus
}
#endif
#endif

57
drivers/bl702_driver/hal_drv/inc/hal_power.h
View File

@ -1,57 +0,0 @@
/**
* @file hal_power.h
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#ifndef __HAL_POWER__H__
#define __HAL_POWER__H__
#include "drv_device.h"
#include "bl702_config.h"
typedef enum {
CLOCK_AHB_UART0_GATE = 0x10,
CLOCK_AHB_UART1_GATE = 0x11,
CLOCK_AHB_SPI_GATE = 0x12,
CLOCK_AHB_I2C_GATE = 0x13,
CLOCK_AHB_PWM_GATE = 0x14,
CLOCK_AHB_TMR_GATE = 0x15,
CLOCK_AHB_IRR_GATE = 0x16,
CLOCK_AHB_CKS_GATE = 0x17,
CLOCK_AHB_QDEC_GATE = 0x18,
CLOCK_AHB_KYS_GATE = 0x19,
CLOCK_AHB_I2S_GATE = 0x1A,
CLOCK_AHB_USB_GATE = 0x1C,
CLOCK_AHB_CAM_GATE = 0x1D,
CLOCK_AHB_MJPEG_GATE = 0x1E,
CLOCK_AHB_ALL = 0x1F,
} Clock_Gate_Type;
int lp_set_clock_gate(uint8_t enable, Clock_Gate_Type clockType);
void lp_set_all_gpio_hz(void);
void lp_power_off_dll(void);
int hbn_set_wakeup_addr(uint32_t addr);
int hbn_set_status_flag(uint32_t flag);
int lp_enter_wfi(void);
int lp_enter_pds(uint32_t sleep_time, void (*preCbFun)(void), void (*postCbFun)(void));
int lp_enter_hbn(uint32_t sleepTime, uint8_t hbn_level);
#endif

11
drivers/bl702_driver/hal_drv/inc/hal_pwm.h
View File

@ -22,9 +22,10 @@
*/
#ifndef __HAL_PWM__H__
#define __HAL_PWM__H__
#include "drv_device.h"
#include "bl702_config.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#define DEVICE_CTRL_PWM_FREQUENCE_CONFIG 0x10
#define DEVICE_CTRL_PWM_DUTYCYCLE_CONFIG 0x11
@ -79,5 +80,7 @@ typedef struct pwm_device {
#define PWM_DEV(dev) ((pwm_device_t *)dev)
int pwm_register(enum pwm_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

11
drivers/bl702_driver/hal_drv/inc/hal_qdec.h
View File

@ -23,9 +23,10 @@
#ifndef __HAL_QDEC__H__
#define __HAL_QDEC__H__
#include "drv_device.h"
#include "bl702_config.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#define DEVICE_CTRL_GET_SAMPLE_VAL (0x10)
#define DEVICE_CTRL_GET_SAMPLE_DIR (0x11)
@ -72,5 +73,7 @@ typedef struct qdec_device {
#define QDEC_DEV(dev) ((qdec_device_t *)dev)
int qdec_register(enum qdec_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif // __HAL_QDEC_H__

10
drivers/bl702_driver/hal_drv/inc/hal_rtc.h
View File

@ -22,12 +22,16 @@
*/
#ifndef __HAL_RTC__H__
#define __HAL_RTC__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "drv_device.h"
#include "bl702_config.h"
#include "hal_common.h"
void rtc_init(uint64_t sleep_time);
void rtc_set_timestamp(uint64_t time_stamp);
uint64_t rtc_get_timestamp(void);
#ifdef __cplusplus
}
#endif
#endif

22
drivers/bl702_driver/hal_drv/inc/hal_sec_aes.h
View File

@ -22,20 +22,22 @@
*/
#ifndef __HAL_SEC_AES__H__
#define __HAL_SEC_AES__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "drv_device.h"
#include "bl702_config.h"
#include "hal_common.h"
typedef enum {
SEC_ASE_CBC,
SEC_ASE_CTR,
SEC_ASE_ECB
SEC_AES_CBC,
SEC_AES_CTR,
SEC_AES_ECB
} sec_aes_type;
typedef enum {
SEC_ASE_KEY_128,
SEC_ASE_KEY_256,
SEC_ASE_KEY_192
SEC_AES_KEY_128,
SEC_AES_KEY_256,
SEC_AES_KEY_192
} sec_aes_key_type;
typedef struct sec_aes_handle_t {
@ -53,5 +55,7 @@ int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len
int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out);
int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out);
int sec_aes_deinit(sec_aes_handle_t *handle);
#ifdef __cplusplus
}
#endif
#endif

10
drivers/bl702_driver/hal_drv/inc/hal_sec_dsa.h
View File

@ -22,9 +22,11 @@
*/
#ifndef __HAL_SEC_DSA__H__
#define __HAL_SEC_DSA__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "drv_device.h"
#include "bl702_config.h"
#include "hal_common.h"
typedef struct sec_dsa_crt_cfg_tag {
uint32_t *dP;
@ -54,5 +56,7 @@ int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint
int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r);
int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s);
int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s);
#ifdef __cplusplus
}
#endif
#endif

10
drivers/bl702_driver/hal_drv/inc/hal_sec_ecdsa.h
View File

@ -22,9 +22,11 @@
*/
#ifndef __HAL_SEC_ECDSA__H__
#define __HAL_SEC_ECDSA__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "drv_device.h"
#include "bl702_config.h"
#include "hal_common.h"
typedef enum {
ECP_SECP256R1 = 0,
@ -58,5 +60,7 @@ int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t si
int sec_eng_trng_enable(void);
void sec_eng_trng_disable(void);
int sec_eng_trng_read(uint8_t data[32]);
#ifdef __cplusplus
}
#endif
#endif

10
drivers/bl702_driver/hal_drv/inc/hal_sec_hash.h
View File

@ -22,9 +22,11 @@
*/
#ifndef __HAL_SEC_HASH__H__
#define __HAL_SEC_HASH__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "drv_device.h"
#include "bl702_config.h"
#include "hal_common.h"
enum sec_hash_index_type {
SEC_HASH0_INDEX,
@ -49,5 +51,7 @@ typedef struct sec_hash_device {
int sec_hash_register(enum sec_hash_index_type index, const char *name);
int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

10
drivers/bl702_driver/hal_drv/inc/hal_spi.h
View File

@ -22,9 +22,11 @@
*/
#ifndef __HAL_SPI__H__
#define __HAL_SPI__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "drv_device.h"
#include "bl702_config.h"
#include "hal_common.h"
#define DEVICE_CTRL_SPI_CONFIG_CLOCK 0x10
@ -101,5 +103,7 @@ int spi_register(enum spi_index_type index, const char *name);
int spi_transmit(struct device *dev, void *buffer, uint32_t size, uint8_t type);
int spi_receive(struct device *dev, void *buffer, uint32_t size, uint8_t type);
int spi_transmit_receive(struct device *dev, const void *send_buf, void *recv_buf, uint32_t length, uint8_t type);
#ifdef __cplusplus
}
#endif
#endif

10
drivers/bl702_driver/hal_drv/inc/hal_timer.h
View File

@ -23,8 +23,10 @@
#ifndef __HAL_TIMER__H__
#define __HAL_TIMER__H__
#include "drv_device.h"
#include "bl702_config.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
enum timer_index_type {
#ifdef BSP_USING_TIMER0
@ -86,5 +88,7 @@ typedef struct timer_device {
#define TIMER_DEV(dev) ((timer_device_t *)dev)
int timer_register(enum timer_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

15
drivers/bl702_driver/hal_drv/inc/hal_uart.h
View File

@ -22,14 +22,18 @@
*/
#ifndef __HAL_UART__H__
#define __HAL_UART__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "drv_device.h"
#include "bl702_config.h"
#include "hal_common.h"
#define UART_FIFO_LEN 128
#define DEVICE_CTRL_UART_GET_TX_FIFO 0x10
#define DEVICE_CTRL_UART_GET_RX_FIFO 0x11
#define DEVICE_CTRL_UART_CLEAR_TX_FIFO 0x12
#define DEVICE_CTRL_UART_CLEAR_RX_FIFO 0x13
enum uart_index_type {
#ifdef BSP_USING_UART0
@ -82,6 +86,9 @@ enum uart_event_type {
UART_EVENT_RX_END,
UART_EVENT_RX_FIFO,
UART_EVENT_RTO,
UART_EVENT_PCE,
UART_EVENT_TX_FER,
UART_EVENT_RX_FER,
UART_EVENT_UNKNOWN
};
@ -120,5 +127,7 @@ typedef struct uart_device {
#define UART_DEV(dev) ((uart_device_t *)dev)
int uart_register(enum uart_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

10
drivers/bl702_driver/hal_drv/inc/hal_usb.h
View File

@ -22,10 +22,12 @@
*/
#ifndef __HAL_USB__H__
#define __HAL_USB__H__
#ifdef __cplusplus
extern "C"{
#endif
#include "drv_device.h"
#include "hal_common.h"
#include "ring_buffer.h"
#include "bl702_config.h"
#define DEVICE_CTRL_USB_DC_SET_ACK 0X10
#define DEVICE_CTRL_USB_DC_ENUM_ON 0X11
@ -215,5 +217,7 @@ int usb_dc_ep_write(struct device *dev, const uint8_t ep, const uint8_t *data, u
int usb_dc_ep_read(struct device *dev, const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes);
int usb_dc_receive_to_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep);
int usb_dc_send_from_ringbuffer(struct device *dev, Ring_Buffer_Type *rb, uint8_t ep);
#ifdef __cplusplus
}
#endif
#endif

11
drivers/bl702_driver/hal_drv/inc/hal_wdt.h
View File

@ -22,9 +22,10 @@
*/
#ifndef __HAL_WDT__H__
#define __HAL_WDT__H__
#include "drv_device.h"
#include "bl702_config.h"
#ifdef __cplusplus
extern "C"{
#endif
#include "hal_common.h"
#define DEVICE_CTRL_GET_WDT_COUNTER (0x10)
#define DEVICE_CTRL_RST_WDT_COUNTER (0x11)
@ -53,5 +54,7 @@ typedef struct wdt_device {
int wdt_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size);
int wdt_register(enum wdt_index_type index, const char *name);
#ifdef __cplusplus
}
#endif
#endif

123
drivers/bl702_driver/hal_drv/src/hal_adc.c
View File

@ -107,11 +107,15 @@ int adc_open(struct device *dev, uint16_t oflag)
adc_cfg.offsetCalibVal = ADC_OFFSER_CALIB_VAL;
adc_fifo_cfg.dmaEn = DISABLE;
adc_fifo_cfg.fifoThreshold = adc_device->fifo_threshold;
if (oflag & DEVICE_OFLAG_STREAM_TX) {
}
if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) {
#ifdef BSP_USING_ADC0
Interrupt_Handler_Register(GPADC_DMA_IRQn, ADC_IRQ);
#endif
}
if (oflag & DEVICE_OFLAG_DMA_TX) {
@ -121,11 +125,7 @@ int adc_open(struct device *dev, uint16_t oflag)
adc_fifo_cfg.dmaEn = ENABLE;
}
adc_fifo_cfg.fifoThreshold = adc_device->fifo_threshold;
#ifdef BSP_USING_ADC0
Interrupt_Handler_Register(GPADC_DMA_IRQn, ADC_IRQ);
#endif
ADC_IntMask(ADC_INT_ALL, MASK);
ADC_Disable();
ADC_Enable();
@ -136,10 +136,6 @@ int adc_open(struct device *dev, uint16_t oflag)
ADC_FIFO_Cfg(&adc_fifo_cfg);
ADC_IntMask(ADC_INT_ALL, MASK);
CPU_Interrupt_Enable(GPADC_DMA_IRQn);
return 0;
}
/**
@ -167,48 +163,17 @@ int adc_control(struct device *dev, int cmd, void *args)
adc_device_t *adc_device = (adc_device_t *)dev;
adc_channel_cfg_t *adc_channel_cfg = (adc_channel_cfg_t *)args;
uint8_t rlt = 0;
uint32_t mask = 0;
switch (cmd) {
case DEVICE_CTRL_SET_INT /* constant-expression */:
mask = (uint32_t)args;
if (mask & ADC_EVENT_FIFO_READY_IT) {
ADC_IntMask(ADC_EVENT_FIFO_READY, UNMASK);
}
if (mask & ADC_EVENT_OVERRUN_IT) {
ADC_IntMask(ADC_EVENT_OVERRUN, UNMASK);
}
if (mask & ADC_EVENT_UNDERRUN_IT) {
ADC_IntMask(ADC_EVENT_UNDERRUN, UNMASK);
}
if (mask & ADC_EVEN_INT_POS_SATURATION_IT) {
ADC_IntMask(ADC_EVEN_INT_POS_SATURATION, UNMASK);
}
if (mask & ADC_EVEN_INT_NEG_SATURATION_IT) {
ADC_IntMask(ADC_EVEN_INT_NEG_SATURATION, UNMASK);
}
ADC_IntMask(ADC_INT_FIFO_READY, UNMASK);
CPU_Interrupt_Enable(GPADC_DMA_IRQn);
break;
case DEVICE_CTRL_CLR_INT /* constant-expression */:
mask = (uint32_t)args;
if (mask & ADC_EVENT_FIFO_READY_IT) {
ADC_IntMask(ADC_EVENT_FIFO_READY, MASK);
}
if (mask & ADC_EVENT_OVERRUN_IT) {
ADC_IntMask(ADC_EVENT_OVERRUN, MASK);
}
if (mask & ADC_EVENT_UNDERRUN_IT) {
ADC_IntMask(ADC_EVENT_UNDERRUN, MASK);
}
if (mask & ADC_EVEN_INT_POS_SATURATION_IT) {
ADC_IntMask(ADC_EVEN_INT_POS_SATURATION, MASK);
}
if (mask & ADC_EVEN_INT_NEG_SATURATION_IT) {
ADC_IntMask(ADC_EVEN_INT_NEG_SATURATION, MASK);
}
ADC_IntMask(ADC_INT_FIFO_READY, MASK);
CPU_Interrupt_Disable(GPADC_DMA_IRQn);
break;
@ -236,18 +201,33 @@ int adc_control(struct device *dev, int cmd, void *args)
ADC_Start();
break;
case DEVICE_CTRL_ADC_CHANNEL_STOP /* constant-expression */:
/* code */
ADC_Stop();
break;
case DEVICE_CTRL_ADC_CHANNEL_STOP /* constant-expression */: {
uint32_t tmpVal;
case DEVICE_CTRL_ADC_VBAT_ON:
ADC_Vbat_Enable();
/* disable convert start */
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CONV_START);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
break;
}
case DEVICE_CTRL_ADC_VBAT_OFF:
ADC_Vbat_Disable();
case DEVICE_CTRL_ADC_VBAT_ON: {
uint32_t tmpVal;
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
break;
}
case DEVICE_CTRL_ADC_VBAT_OFF: {
uint32_t tmpVal;
tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2);
tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN);
BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal);
break;
}
case DEVICE_CTRL_ADC_TSEN_ON:
ADC_Tsen_Init(ADC_TSEN_MOD_INTERNAL_DIODE);
@ -279,18 +259,20 @@ int adc_control(struct device *dev, int cmd, void *args)
*/
int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size)
{
if (dev->oflag & DEVICE_OFLAG_STREAM_RX || dev->oflag & DEVICE_OFLAG_INT_RX) {
while (ADC_Get_FIFO_Count() == 0)
;
uint32_t adc_fifo_val[32];
do {
uint32_t regVal = ADC_Read_FIFO();
if (regVal) {
ADC_Result_Type *result = (ADC_Result_Type *)buffer;
ADC_Parse_Result(&regVal, size, result);
if (dev->oflag & DEVICE_OFLAG_STREAM_RX) {
if (size > 32)
return -1;
while (ADC_Get_FIFO_Count() < size) {
}
} while (ADC_Get_FIFO_Count() != 0);
for (uint32_t i = 0; i < size; i++) {
adc_fifo_val[i] = ADC_Read_FIFO();
}
adc_channel_val_t *adc_parse_val = (adc_channel_val_t *)buffer;
ADC_Parse_Result(adc_fifo_val, size, (ADC_Result_Type *)adc_parse_val);
return size;
}
return 0;
@ -348,27 +330,34 @@ void adc_isr(adc_device_t *handle)
return;
if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET && ADC_IntGetMask(ADC_INT_POS_SATURATION) == UNMASK) {
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_POS_SATURATION);
//handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_POS_SATURATION);
ADC_IntClr(ADC_INT_POS_SATURATION);
}
if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET && ADC_IntGetMask(ADC_INT_NEG_SATURATION) == UNMASK) {
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_NEG_SATURATION);
//handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_NEG_SATURATION);
ADC_IntClr(ADC_INT_NEG_SATURATION);
}
if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK) {
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_UNDERRUN);
//handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_UNDERRUN);
ADC_IntClr(ADC_INT_FIFO_UNDERRUN);
}
if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK) {
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_OVERRUN);
//handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_OVERRUN);
ADC_IntClr(ADC_INT_FIFO_OVERRUN);
}
if (ADC_GetIntStatus(ADC_INT_FIFO_READY) == SET && ADC_IntGetMask(ADC_INT_FIFO_READY) == UNMASK) {
handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_FIFO_READY);
uint32_t adc_count = ADC_Get_FIFO_Count();
uint32_t adc_fifo_val[32];
adc_channel_val_t adc_parse_val[32];
for (uint32_t i = 0; i < adc_count; i++) {
adc_fifo_val[i] = ADC_Read_FIFO();
}
ADC_Parse_Result(adc_fifo_val, adc_count, (ADC_Result_Type *)adc_parse_val);
handle->parent.callback(&handle->parent, (void *)adc_parse_val, adc_count, ADC_EVENT_FIFO);
ADC_IntClr(ADC_INT_FIFO_READY);
}
}

26
drivers/bl702_driver/hal_drv/src/hal_boot2.c
View File

@ -18,8 +18,6 @@ uint32_t hal_boot2_custom(void)
return 0;
}
/**
* @brief get efuse Boot2 config
*
@ -54,7 +52,10 @@ void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *g_efuse_cfg)
/* restore bclk fclk div and root clock sel */
GLB_Set_System_CLK_Div(hdiv, bdiv);
BL_WR_REG(HBN_BASE, HBN_GLB, rootClk);
__NOP();__NOP();__NOP();__NOP();
__NOP();
__NOP();
__NOP();
__NOP();
}
/**
* @brief reset sec eng clock
@ -76,7 +77,6 @@ void hal_boot2_sw_system_reset(void)
GLB_SW_System_Reset();
}
/**
* @brief
*
@ -175,7 +175,6 @@ void hal_boot2_debug_uart_gpio_init(void)
GLB_UART_Fun_Sel((GPIO_PIN_17 % 8), GLB_UART_SIG_FUN_UART1_TXD);
}
/**
* @brief hal_boot2_debug_usb_port_init
*
@ -184,14 +183,23 @@ void hal_boot2_debug_uart_gpio_init(void)
#if HAL_BOOT2_SUPPORT_USB_IAP
void hal_boot2_debug_usb_port_init(void)
{
/* must do this , or usb can not be recognized */
__disable_irq();
__enable_irq();
cpu_global_irq_disable();
cpu_global_irq_enable();
GLB_GPIO_Type gpios[] = { GPIO_PIN_7, GPIO_PIN_8 };
GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, gpios, 2);
}
#endif
/**
* @brief hal_boot2_debug_uart_gpio_deinit
*
* @return
*/
void hal_boot2_debug_uart_gpio_deinit(void)
{
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0);
GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1);
GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);
}

204
drivers/bl702_driver/hal_drv/src/hal_clock.c
View File

@ -25,7 +25,6 @@
#include "bl702_pwm.h"
#include "bl702_timer.h"
#include "hal_clock.h"
#include "hal_mtimer.h"
static uint32_t mtimer_get_clk_src_div(void)
{
@ -36,6 +35,11 @@ static void peripheral_clock_gate_all()
{
uint32_t tmpVal;
tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
// tmpVal &= (~(1 << BL_AHB_SLAVE1_GPIP));
// tmpVal &= (~(1 << BL_AHB_SLAVE1_SEC_DBG));
// tmpVal &= (~(1 << BL_AHB_SLAVE1_SEC));
tmpVal &= (~(1 << BL_AHB_SLAVE1_TZ1));
tmpVal &= (~(1 << BL_AHB_SLAVE1_TZ2));
tmpVal &= (~(1 << BL_AHB_SLAVE1_DMA));
tmpVal &= (~(1 << BL_AHB_SLAVE1_EMAC));
tmpVal &= (~(1 << BL_AHB_SLAVE1_UART0));
@ -45,9 +49,11 @@ static void peripheral_clock_gate_all()
tmpVal &= (~(1 << BL_AHB_SLAVE1_PWM));
tmpVal &= (~(1 << BL_AHB_SLAVE1_TMR));
tmpVal &= (~(1 << BL_AHB_SLAVE1_IRR));
tmpVal &= (~(1 << BL_AHB_SLAVE1_QDEC));
tmpVal &= (~(1 << BL_AHB_SLAVE1_KYS));
tmpVal &= (~(1 << BL_AHB_SLAVE1_I2S));
tmpVal &= (~(1 << BL_AHB_SLAVE1_CKS));
tmpVal &= (~(1 << 24)); //QDEC0
tmpVal &= (~(1 << 25)); //QDEC1
tmpVal &= (~(1 << 26)); //QDEC2/I2S
tmpVal &= (~(1 << 27)); //KYS
tmpVal &= (~(1 << BL_AHB_SLAVE1_USB));
tmpVal &= (~(1 << BL_AHB_SLAVE1_CAM));
tmpVal &= (~(1 << BL_AHB_SLAVE1_MJPEG));
@ -58,6 +64,10 @@ void system_clock_init(void)
{
/*select root clock*/
GLB_Set_System_CLK(XTAL_TYPE, BSP_ROOT_CLOCK_SOURCE);
#if BSP_ROOT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_57P6M
/* fix 57.6M */
SystemCoreClockSet(57.6 * 1000 * 1000);
#endif
/*set fclk/hclk and bclk clock*/
GLB_Set_System_CLK_Div(BSP_FCLK_DIV, BSP_BCLK_DIV);
/* Set MTimer the same frequency as SystemCoreClock */
@ -84,25 +94,29 @@ void system_mtimer_clock_init(void)
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, mtimer_get_clk_src_div());
}
void system_mtimer_clock_reinit(void)
{
/* reinit clock to 10M */
GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 7);
}
void peripheral_clock_init(void)
{
uint32_t tmpVal = 0;
peripheral_clock_gate_all();
tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1)
#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
#if defined(BSP_USING_UART0)
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_UART0);
tmpVal |= (1 << BL_AHB_SLAVE1_UART0);
#endif
#if defined(BSP_USING_UART1)
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_UART1);
tmpVal |= (1 << BL_AHB_SLAVE1_UART1);
#endif
#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, BSP_UART_CLOCK_DIV);
#elif BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
#if defined(BSP_USING_UART0)
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_UART0);
#endif
#if defined(BSP_USING_UART1)
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_UART1);
#endif
GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_FCLK, BSP_UART_CLOCK_DIV);
#else
#error "please select correct uart clock source"
@ -111,7 +125,7 @@ void peripheral_clock_init(void)
#if defined(BSP_USING_I2C0)
#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_I2C);
tmpVal |= (1 << BL_AHB_SLAVE1_I2C);
GLB_Set_I2C_CLK(ENABLE, BSP_I2C_CLOCK_DIV);
#else
#error "please select correct i2c clock source"
@ -120,7 +134,7 @@ void peripheral_clock_init(void)
#if defined(BSP_USING_SPI0)
#if BSP_SPI_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_BCLK
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_SPI);
tmpVal |= (1 << BL_AHB_SLAVE1_SPI);
GLB_Set_SPI_CLK(ENABLE, BSP_SPI_CLOCK_DIV);
#else
#error "please select correct spi clock source"
@ -128,8 +142,10 @@ void peripheral_clock_init(void)
#endif
#if defined(BSP_USING_TIMER0)
tmpVal |= (1 << BL_AHB_SLAVE1_TMR);
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
#if BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR);
/* Configure timer clock source */
uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_FCLK);
@ -140,7 +156,6 @@ void peripheral_clock_init(void)
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR);
/* Configure timer clock source */
uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_XTAL);
@ -151,12 +166,21 @@ void peripheral_clock_init(void)
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR);
/* Configure timer clock source */
uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_32K);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);
/* Configure timer clock division */
tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp);
#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
/* Configure timer clock source */
uint32_t tmp = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_CS_1, TIMER_CLKSRC_1K);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp);
/* Configure timer clock division */
tmp = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmp = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR2, BSP_TIMER0_CLOCK_DIV);
@ -167,8 +191,10 @@ void peripheral_clock_init(void)
#endif
#if defined(BSP_USING_TIMER1)
tmpVal |= (1 << BL_AHB_SLAVE1_TMR);
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
#if BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR);
/* Configure timer clock source */
uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_FCLK);
@ -179,7 +205,6 @@ void peripheral_clock_init(void)
tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR);
/* Configure timer clock source */
uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_XTAL);
@ -190,12 +215,21 @@ void peripheral_clock_init(void)
tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR);
/* Configure timer clock source */
uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_32K);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);
/* Configure timer clock division */
tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmp1 = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmp1);
#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
/* Configure timer clock source */
uint32_t tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmp1 = BL_SET_REG_BITS_VAL(tmp1, TIMER_CS_2, TIMER_CLKSRC_1K);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmp1);
/* Configure timer clock division */
tmp1 = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmp1 = BL_SET_REG_BITS_VAL(tmp, TIMER_TCDR3, BSP_TIMER1_CLOCK_DIV);
@ -206,8 +240,10 @@ void peripheral_clock_init(void)
#endif
#if defined(BSP_USING_WDT)
tmpVal |= (1 << BL_AHB_SLAVE1_TMR);
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
#if BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR);
/* Configure watchdog timer clock source */
uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_FCLK);
@ -218,7 +254,6 @@ void peripheral_clock_init(void)
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR);
/* Configure watchdog timer clock source */
uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_XTAL);
@ -229,12 +264,21 @@ void peripheral_clock_init(void)
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_TMR);
/* Configure watchdog timer clock source */
uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_32K);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);
/* Configure watchdog timer clock division */
tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
BL_WR_REG(TIMER_BASE, TIMER_TCDR, tmpwdt);
#elif BSP_WDT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
/* Configure watchdog timer clock source */
uint32_t tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_CS_WDT, TIMER_CLKSRC_1K);
BL_WR_REG(TIMER_BASE, TIMER_TCCR, tmpwdt);
/* Configure watchdog timer clock division */
tmpwdt = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
tmpwdt = BL_SET_REG_BITS_VAL(tmpwdt, TIMER_WCDR, BSP_WDT_CLOCK_DIV);
@ -244,18 +288,19 @@ void peripheral_clock_init(void)
#endif
#endif
#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4) || defined(BSP_USING_PWM_CH5)
/* Disable clock gate */
GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_PWM);
#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4)
tmpVal |= (1 << BL_AHB_SLAVE1_PWM);
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
uint32_t timeoutCnt = 160 * 1000;
uint32_t tmpVal;
uint32_t tmp_pwm;
uint32_t PWMx;
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
for (int i = 0; i < 5; i++) {
PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20;
tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN));
tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmp_pwm, PWM_STOP_EN));
while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
timeoutCnt--;
@ -264,9 +309,9 @@ void peripheral_clock_init(void)
return;
}
}
tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, PWM_CLK_32K);
BL_WR_REG(PWMx, PWM_CONFIG, tmpVal);
tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
tmp_pwm = BL_SET_REG_BITS_VAL(tmp_pwm, PWM_REG_CLK_SEL, PWM_CLK_32K);
BL_WR_REG(PWMx, PWM_CONFIG, tmp_pwm);
/* Config pwm division */
BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV);
}
@ -274,8 +319,8 @@ void peripheral_clock_init(void)
for (int i = 0; i < 5; i++) {
PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20;
tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN));
tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmp_pwm, PWM_STOP_EN));
while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
timeoutCnt--;
@ -284,9 +329,9 @@ void peripheral_clock_init(void)
return;
}
}
tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, PWM_CLK_BCLK);
BL_WR_REG(PWMx, PWM_CONFIG, tmpVal);
tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
tmp_pwm = BL_SET_REG_BITS_VAL(tmp_pwm, PWM_REG_CLK_SEL, PWM_CLK_BCLK);
BL_WR_REG(PWMx, PWM_CONFIG, tmp_pwm);
/* Config pwm division */
BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV);
}
@ -294,8 +339,8 @@ void peripheral_clock_init(void)
for (int i = 0; i < 5; i++) {
PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (i)*0x20;
tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN));
tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
BL_WR_REG(PWMx, PWM_CONFIG, BL_SET_REG_BIT(tmp_pwm, PWM_STOP_EN));
while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG), PWM_STS_TOP)) {
timeoutCnt--;
@ -304,9 +349,9 @@ void peripheral_clock_init(void)
return;
}
}
tmpVal = BL_RD_REG(PWMx, PWM_CONFIG);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, PWM_CLK_XCLK);
BL_WR_REG(PWMx, PWM_CONFIG, tmpVal);
tmp_pwm = BL_RD_REG(PWMx, PWM_CONFIG);
tmp_pwm = BL_SET_REG_BITS_VAL(tmp_pwm, PWM_REG_CLK_SEL, PWM_CLK_XCLK);
BL_WR_REG(PWMx, PWM_CONFIG, tmp_pwm);
/* Config pwm division */
BL_WR_REG(PWMx, PWM_CLKDIV, BSP_PWM_CLOCK_DIV);
}
@ -316,16 +361,17 @@ void peripheral_clock_init(void)
#endif
#if defined(BSP_USING_IR)
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_IRR);
tmpVal |= (1 << BL_AHB_SLAVE1_IRR);
GLB_Set_IR_CLK(ENABLE, 0, BSP_IR_CLOCK_DIV);
#endif
#if defined(BSP_USING_I2S0)
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_I2S);
tmpVal |= (1 << BL_AHB_SLAVE1_I2S);
GLB_Set_I2S_CLK(ENABLE, GLB_I2S_OUT_REF_CLK_NONE);
#endif
#if defined(BSP_USING_ADC0)
//tmpVal |= (1 << BL_AHB_SLAVE1_GPIP);
#if BSP_ADC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_AUDIO_PLL, BSP_ADC_CLOCK_DIV);
#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
@ -336,6 +382,7 @@ void peripheral_clock_init(void)
#endif
#if defined(BSP_USING_DAC0)
//tmpVal |= (1 << BL_AHB_SLAVE1_GPIP);
#if BSP_DAC_CLOCK_SOURCE >= ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ
GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_AUDIO_PLL, BSP_DAC_CLOCK_DIV);
#elif BSP_DAC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
@ -346,12 +393,11 @@ void peripheral_clock_init(void)
#endif
#if defined(BSP_USING_CAM)
tmpVal |= (1 << BL_AHB_SLAVE1_CAM);
#if BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_PLL_96M
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_CAM);
GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_DLL96M, BSP_CAM_CLOCK_DIV);
GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM);
#elif BSP_CAM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_CAM);
GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_XCLK, BSP_CAM_CLOCK_DIV);
GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_CAM);
#else
@ -360,21 +406,21 @@ void peripheral_clock_init(void)
#endif
#if defined(BSP_USING_QDEC0) || defined(BSP_USING_QDEC1) || defined(BSP_USING_QDEC2) || defined(BSP_USING_KEYSCAN)
#if BSP_QDEC_KEYSCAN_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
#ifdef BSP_USING_KEYSCAN
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_KYS);
tmpVal |= (1 << 27);
#endif
#if defined(BSP_USING_QDEC0) || defined(BSP_USING_QDEC1) || defined(BSP_USING_QDEC2)
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_QDEC);
#if defined(BSP_USING_QDEC0)
tmpVal |= (1 << 24);
#endif
#if defined(BSP_USING_QDEC1)
tmpVal |= (1 << 25);
#endif
#if defined(BSP_USING_QDEC2)
tmpVal |= (1 << 26);
#endif
#if BSP_QDEC_KEYSCAN_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
GLB_Set_QDEC_CLK(GLB_QDEC_CLK_F32K, BSP_QDEC_KEYSCAN_CLOCK_DIV);
#elif BSP_QDEC_KEYSCAN_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
#if defined(BSP_USING_KEYSCAN)
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_KYS);
#endif
#if defined(BSP_USING_QDEC0) || defined(BSP_USING_QDEC1) || defined(BSP_USING_QDEC2)
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_QDEC);
#endif
GLB_Set_QDEC_CLK(GLB_QDEC_CLK_XCLK, BSP_QDEC_KEYSCAN_CLOCK_DIV);
#else
#error "please select correct qdec or keyscan clock source"
@ -382,27 +428,44 @@ void peripheral_clock_init(void)
#endif
#if defined(BSP_USING_USB)
GLB_AHB_Slave1_Clock_Gate(0, BL_AHB_SLAVE1_USB);
tmpVal |= (1 << BL_AHB_SLAVE1_USB);
GLB_Set_USB_CLK(1);
#endif
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
}
uint32_t system_clock_get(enum system_clock_type type)
{
switch (type) {
case SYSTEM_CLOCK_ROOT_CLOCK:
return SystemCoreClockGet() * (GLB_Get_HCLK_Div() + 1);
if (GLB_Get_Root_CLK_Sel() == 0) {
return 32 * 1000 * 1000;
} else if (GLB_Get_Root_CLK_Sel() == 1)
return 32 * 1000 * 1000;
else {
uint32_t tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL);
if (tmpVal == 0) {
return 57.6 * 1000 * 1000;
} else if (tmpVal == 1) {
return 96 * 1000 * 1000;
} else if (tmpVal == 2) {
return 144 * 1000 * 1000;
} else {
return 0;
}
}
case SYSTEM_CLOCK_FCLK:
return SystemCoreClockGet();
return system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK) / (GLB_Get_HCLK_Div() + 1);
case SYSTEM_CLOCK_BCLK:
return SystemCoreClockGet() / (GLB_Get_BCLK_Div() + 1);
return system_clock_get(SYSTEM_CLOCK_ROOT_CLOCK) / (GLB_Get_HCLK_Div() + 1) / (GLB_Get_BCLK_Div() + 1);
case SYSTEM_CLOCK_XCLK:
return 32000000;
case SYSTEM_CLOCK_32K_CLK:
return 32000;
case SYSTEM_CLOCK_AUPLL:
#ifdef BSP_AUDIO_PLL_CLOCK_SOURCE
if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_12288000_HZ) {
return 12288000;
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_11289600_HZ) {
@ -414,6 +477,7 @@ uint32_t system_clock_get(enum system_clock_type type)
} else if (BSP_AUDIO_PLL_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_24000000_HZ) {
return 24000000;
}
#endif
default:
break;
}
@ -508,29 +572,37 @@ uint32_t peripheral_clock_get(enum peripheral_clock_type type)
tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR2);
return system_clock_get(SYSTEM_CLOCK_32K_CLK) / (div + 1);
#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR2);
return 1000 / (div + 1);
#else
break;
#endif
#endif
#if defined(BSP_USING_TIMER1)
case PERIPHERAL_CLOCK_TIMER1:
#if BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
#if BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_FCLK
tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR3);
return system_clock_get(SYSTEM_CLOCK_FCLK) / (div + 1);
#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK
tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR3);
return system_clock_get(SYSTEM_CLOCK_XCLK) / (div + 1);
#elif BSP_TIMER0_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR3);
return system_clock_get(SYSTEM_CLOCK_32K_CLK) / (div + 1);
#elif BSP_TIMER1_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_1K_CLK
tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCDR);
div = BL_GET_REG_BITS_VAL(tmpVal, TIMER_TCDR3);
return 1000 / (div + 1);
#else
break;
#endif
#endif
#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4) || defined(BSP_USING_PWM_CH5)
#if defined(BSP_USING_PWM_CH0) || defined(BSP_USING_PWM_CH1) || defined(BSP_USING_PWM_CH2) || defined(BSP_USING_PWM_CH3) || defined(BSP_USING_PWM_CH4)
case PERIPHERAL_CLOCK_PWM:
#if BSP_PWM_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_32K_CLK
div = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV);

98
drivers/bl702_driver/hal_drv/src/hal_common.c Normal file
View File

@ -0,0 +1,98 @@
/**
* @file hal_common.c
* @brief
*
* Copyright (c) 2021 Bouffalolab team
*
* Licensed to the Apache Software Foundation (ASF) under one or more
* contributor license agreements. See the NOTICE file distributed with
* this work for additional information regarding copyright ownership. The
* ASF licenses this file to you under the Apache License, Version 2.0 (the
* "License"); you may not use this file except in compliance with the
* License. You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
* License for the specific language governing permissions and limitations
* under the License.
*
*/
#include "hal_common.h"
#include "bl702_ef_ctrl.h"
#include "bl702_romdriver.h"
#include "bl702_sec_eng.h"
#include "bl702_l1c.h"
#include "hbn_reg.h"
volatile uint32_t nesting = 0;
void ATTR_TCM_SECTION cpu_global_irq_enable(void)
{
nesting--;
if (nesting == 0) {
__enable_irq();
}
}
void ATTR_TCM_SECTION cpu_global_irq_disable(void)
{
__disable_irq();
nesting++;
}
void hal_system_reset(void)
{
RomDriver_GLB_SW_System_Reset();
}
void hal_cpu_reset(void)
{
RomDriver_GLB_SW_CPU_Reset();
}
void hal_get_chip_id(uint8_t chip_id[8])
{
EF_Ctrl_Read_MAC_Address(chip_id);
}
void hal_enter_usb_iap(void)
{
BL_WR_WORD(HBN_BASE + HBN_RSV0_OFFSET, 0x00425355); //"\0BSU"
bflb_platform_delay_ms(1000);
RomDriver_GLB_SW_System_Reset();
}
void ATTR_TCM_SECTION hal_jump2app(uint32_t flash_offset)
{
/*flash_offset from 48K to 3.98M*/
if ((flash_offset >= 0xc000) && (flash_offset < (0x400000 - 20 * 1024))) {
void (*app_main)(void) = (void (*)(void))0x23000000;
BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, flash_offset);
L1C_Cache_Flush_Ext();
app_main();
} else {
MSG("Illegal app flash offset:%d\r\n", flash_offset);
}
}
int hal_get_trng_seed(void)
{
uint32_t seed[8];
uint32_t tmpVal;
tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
tmpVal |= (1 << BL_AHB_SLAVE1_SEC);
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
Sec_Eng_Trng_Enable();
Sec_Eng_Trng_Read((uint8_t *)seed);
Sec_Eng_Trng_Disable();
tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
tmpVal &= (~(1 << BL_AHB_SLAVE1_SEC));
BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
return seed[0];
}

1
drivers/bl702_driver/hal_drv/src/hal_dac.c
View File

@ -25,7 +25,6 @@
#include "bl702_gpio.h"
#include "bl702_dac.h"
#include "bl702_dma.h"
#include "bl702_config.h"
#include "bl702_glb.h"
#include "dac_config.h"

53
drivers/bl702_driver/hal_drv/src/hal_emac.c
View File

@ -94,6 +94,19 @@ static int emac_bd_rx_enqueue(uint32_t index)
*/
static void emac_bd_rx_on_err(uint32_t index)
{
/* to do index - 1 */
// uint32_t tmp_bd = 0;
// tmp_bd = BL_RD_REG(EMAC_BASE, EMAC_TX_BD_NUM);
// if (index == tmp_bd) {
// index += (tmp_bd - 1);
// } else {
// index -= 1;
// }
// MSG("i:%x,csl%x\r\n", 5, thiz->bd[5].C_S_L);
// MSG("i:%x,csl%x\r\n", 6, thiz->bd[6].C_S_L);
// MSG("i:%x,csl%x\r\n", 7, thiz->bd[7].C_S_L);
// MSG("i:%x,csl%x\r\n", 8, thiz->bd[8].C_S_L);
// MSG("i:%x,csl%x\r\n", 9, thiz->bd[9].C_S_L);
/* handle error */
if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_OR)) {
MSG("EMAC RX OR Error at %s:%d\r\n", __func__, __LINE__);
@ -307,7 +320,7 @@ int emac_init(emac_device_t *emac_cfg)
.maxTxRetry = 16, /*!< Maximum tx retry count */
.interFrameGapValue = 24, /*!< Inter frame gap vaule in clock cycles(default 24)*/
.minFrameLen = 64, /*!< Minimum frame length */
.maxFrameLen = 1500, /*!< Maximum frame length */
.maxFrameLen = ETH_MAX_PACKET_SIZE, /*!< Maximum frame length */
.collisionValid = 16, /*!< Collision valid value */
.macAddr[0] = 0x18, /*!< MAC Address */
.macAddr[1] = 0xB0,
@ -389,7 +402,11 @@ int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in)
DMADesc = &thiz->bd[thiz->txIndexCPU];
if ((uint32_t)(-1) == flags) {
if (FULL_PACKET == flags) {
// MSG("full packet,len:%d\r\n", len);
flags = (EMAC_TX_COMMON_FLAGS | EMAC_BD_FIELD_MSK(TX_EOF));
} else if (NOFULL_PACKET == flags) {
// MSG("nofull packet\r\n");
flags = EMAC_TX_COMMON_FLAGS;
}
@ -398,8 +415,10 @@ int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in)
err = NORESC;
// MSG_ERR(TAG"%s:%d\n", __func__, __LINE__);
} else {
//DMADesc->TXBuffer = (uint32_t)data_in;
ARCH_MemCpy_Fast((void *)DMADesc->Buffer, data_in, len);
DMADesc->Buffer = (uint32_t)data_in;
// MSG("tx q flags:%d,len:%d,data:0x%x\r\n", flags, len, data_in);
// ARCH_MemCpy_Fast((void *)DMADesc->Buffer, data_in, len);
DMADesc->C_S_L = flags | (len << BD_TX_LEN_POS);
@ -514,13 +533,33 @@ int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue)
return 0;
}
int emac_stop()
int emac_stop(void)
{
return 0;
return EMAC_Disable();
}
int emac_start()
int emac_start(void)
{
EMAC_Enable();
return 0;
}
int emac_start_tx(void)
{
return EMAC_Enable_TX();
}
int emac_stop_tx(void)
{
return EMAC_Disable_TX();
}
int emac_start_rx(void)
{
return EMAC_Enable_RX();
}
int emac_stop_rx(void)
{
return EMAC_Disable_RX();
}

47
drivers/bl702_driver/hal_drv/src/hal_flash.c
View File

@ -86,7 +86,7 @@ static BL_Err_Type ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flas
uint32_t jid = 0;
uint32_t offset = 0;
__disable_irq();
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
XIP_SFlash_State_Save(p_flash_cfg, &offset);
SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid);
@ -102,7 +102,7 @@ static BL_Err_Type ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flas
flash_set_l1c_wrap(p_flash_cfg);
XIP_SFlash_State_Restore(p_flash_cfg, p_flash_cfg->ioMode & 0x0f, offset);
XIP_SFlash_Opt_Exit();
__enable_irq();
cpu_global_irq_enable();
return ret;
}
@ -119,11 +119,11 @@ BL_Err_Type ATTR_TCM_SECTION flash_init(void)
uint8_t clkInvert = 1;
uint32_t jedec_id = 0;
__disable_irq();
cpu_global_irq_disable();
L1C_Cache_Flush_Ext();
SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg);
L1C_Cache_Flush_Ext();
__enable_irq();
cpu_global_irq_enable();
if (g_flash_cfg.mid != 0xff) {
return SUCCESS;
}
@ -153,11 +153,11 @@ BL_Err_Type ATTR_TCM_SECTION flash_read_jedec_id(uint8_t *data)
{
uint32_t jid = 0;
__disable_irq();
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
XIP_SFlash_GetJedecId_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, (uint8_t *)&jid);
XIP_SFlash_Opt_Exit();
__enable_irq();
cpu_global_irq_enable();
jid &= 0xFFFFFF;
arch_memcpy(data, (void *)&jid, 4);
@ -174,11 +174,11 @@ BL_Err_Type ATTR_TCM_SECTION flash_read_jedec_id(uint8_t *data)
*/
BL_Err_Type ATTR_TCM_SECTION flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len)
{
__disable_irq();
cpu_global_irq_disable();
L1C_Cache_Flush_Ext();
XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len);
L1C_Cache_Flush_Ext();
__enable_irq();
cpu_global_irq_enable();
return SUCCESS;
}
@ -195,9 +195,11 @@ BL_Err_Type ATTR_TCM_SECTION flash_read(uint32_t addr, uint8_t *data, uint32_t l
{
BL_Err_Type ret = ERROR;
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
ret = XIP_SFlash_Read_With_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len);
ret = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len);
XIP_SFlash_Opt_Exit();
cpu_global_irq_enable();
return ret;
}
@ -214,9 +216,11 @@ BL_Err_Type ATTR_TCM_SECTION flash_write(uint32_t addr, uint8_t *data, uint32_t
{
BL_Err_Type ret = ERROR;
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
ret = XIP_SFlash_Write_With_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len);
ret = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, addr, data, len);
XIP_SFlash_Opt_Exit();
cpu_global_irq_enable();
return ret;
}
@ -232,9 +236,30 @@ BL_Err_Type ATTR_TCM_SECTION flash_erase(uint32_t startaddr, uint32_t len)
{
BL_Err_Type ret = ERROR;
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
ret = XIP_SFlash_Erase_With_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, startaddr, len);
ret = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, g_flash_cfg.ioMode & 0x0f, startaddr, startaddr + len - 1);
XIP_SFlash_Opt_Exit();
cpu_global_irq_enable();
return ret;
}
/**
* @brief flash clear status register
*
* @param None
* @return BL_Err_Type
*/
BL_Err_Type ATTR_TCM_SECTION flash_clear_status_register(void)
{
BL_Err_Type ret = ERROR;
cpu_global_irq_disable();
XIP_SFlash_Opt_Enter();
ret = XIP_SFlash_Clear_Status_Register_Need_Lock(&g_flash_cfg);
XIP_SFlash_Opt_Exit();
cpu_global_irq_enable();
return ret;
}

2
drivers/bl702_driver/hal_drv/src/hal_gpio.c
View File

@ -172,7 +172,7 @@ void gpio_toggle(uint32_t pin)
*/
int gpio_read(uint32_t pin)
{
return (BL_RD_REG(GLB_BASE, GLB_GPIO_INPUT) & (1 << pin));
return ((BL_RD_REG(GLB_BASE, GLB_GPIO_INPUT) & (1 << pin)) ? 1 : 0);
}
/**
* @brief

12
drivers/bl702_driver/hal_drv/src/hal_i2s.c
View File

@ -285,20 +285,12 @@ int i2s_control(struct device *dev, int cmd, void *args)
i2s_device->rx_dma = (struct device *)args;
break;
case DEVICE_CTRL_GET_CONFIG:
switch ((uint32_t)args) {
case I2S_GET_TX_FIFO_CMD:
case DEVICE_CTRL_I2S_GET_TX_FIFO:
return I2S_GetTxFIFO_AvlCnt();
case I2S_GET_RX_FIFO_CMD:
case DEVICE_CTRL_I2S_GET_RX_FIFO:
return I2S_GetRxFIFO_AvlCnt();
default:
break;
}
break;
default:
return ERROR;
break;

63
drivers/bl702_driver/hal_drv/src/hal_pm.c
View File

@ -26,9 +26,9 @@
#include "hal_clock.h"
#include "hal_rtc.h"
#include "hal_flash.h"
#include "hal_common.h"
#define PM_PDS_FLASH_POWER_OFF 1
#define PM_PDS_EXTERNAL_XTAL_32M_POWER_OFF 1
#define PM_PDS_DLL_POWER_OFF 1
#define PM_PDS_PLL_POWER_OFF 1
#define PM_PDS_RF_POWER_OFF 1
@ -869,19 +869,14 @@ ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint8
uint32_t flash_cfg_len;
/* To make it simple and safe*/
__disable_irq();
cpu_global_irq_disable();
flash_get_cfg((uint8_t **)&flash_cfg, &flash_cfg_len);
HBN_Set_Ldo11_All_Vout(PM_PDS_LDO_LEVEL_DEFAULT);
PDS_WAKEUP_IRQHandler_Install();
HBN_Clear_IRQ(HBN_INT_GPIO9);
HBN_Clear_IRQ(HBN_INT_GPIO10);
HBN_Clear_IRQ(HBN_INT_GPIO11);
HBN_Clear_IRQ(HBN_INT_GPIO12);
HBN_Clear_IRQ(HBN_INT_GPIO13);
HBN_Clear_IRQ(HBN_INT_ACOMP0);
HBN_Clear_IRQ(HBN_INT_ACOMP1);
BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);
tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
tmpVal &= ~(1 << 8); //unmask pds wakeup
@ -945,17 +940,14 @@ ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint8
pPdsCfg->pdsCtl.puFlash = 1;
#endif
#if PM_PDS_EXTERNAL_XTAL_32M_POWER_OFF
HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);
AON_Power_Off_XTAL();
#if PM_PDS_PLL_POWER_OFF
PDS_Power_Off_PLL();
#endif
#if PM_PDS_DLL_POWER_OFF
GLB_Power_Off_DLL();
#endif
#if PM_PDS_PLL_POWER_OFF
GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M);
AON_Power_Off_XTAL();
GLB_Power_Off_DLL();
PDS_Update_Flash_Ctrl_Setting(0);
PDS_Power_Off_PLL();
#endif
/* pds0-pds7 : ldo11rt_iload_sel=3 */
@ -968,7 +960,6 @@ ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint8
/* pdsLevel error */
}
pPdsCfg->pdsCtl.gpioIePuPd = 0;
pPdsCfg->pdsCtl.pdsLdoVol = PM_PDS_LDO_LEVEL_DEFAULT;
pPdsCfg->pdsCtl.pdsLdoVselEn = 1;
@ -995,7 +986,7 @@ ATTR_TCM_SECTION void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint8
SFlash_Restore_From_Powerdown(flash_cfg, 0);
#endif
__enable_irq();
cpu_global_irq_enable();
}
/**
* @brief
@ -1014,7 +1005,7 @@ ATTR_TCM_SECTION void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8
uint32_t tmpVal;
/* To make it simple and safe*/
__disable_irq();
cpu_global_irq_disable();
CPU_Interrupt_Pending_Clear(HBN_OUT0_IRQn);
CPU_Interrupt_Pending_Clear(HBN_OUT1_IRQn);
@ -1041,6 +1032,8 @@ ATTR_TCM_SECTION void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8
GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M);
/* power off xtal */
AON_Power_Off_XTAL();
GLB_Power_Off_DLL();
PDS_Power_Off_PLL();
/* HBN mode LDO level */
tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
@ -1174,3 +1167,35 @@ void HBN_OUT1_IRQ(void)
__WEAK void pm_irq_callback(enum pm_event_type event)
{
}
/**
* @brief hal_pds_enter_with_time_compensation
*
* @param pdsLevel pds level support 0~3,31
* @param pdsSleepCycles if user set sleep time, pdsSleepCycles cannot be less than 32768, pdsSleepCycles is a multiple of 32768 preferably.
* @return uint32_t actual sleep time(ms)
*
* @note If necessary，please application layer call vTaskStepTick，
*/
uint32_t hal_pds_enter_with_time_compensation(uint32_t pdsLevel, uint32_t pdsSleepCycles)
{
uint32_t rtcLowBeforeSleep = 0, rtcHighBeforeSleep = 0;
uint32_t rtcLowAfterSleep = 0, rtcHighAfterSleep = 0;
uint32_t actualSleepDuration_32768cycles = 0;
uint32_t actualSleepDuration_ms = 0;
HBN_Get_RTC_Timer_Val(&rtcLowBeforeSleep, &rtcHighBeforeSleep);
pm_pds_mode_enter(pdsLevel, pdsSleepCycles / 32768);
HBN_Get_RTC_Timer_Val(&rtcLowAfterSleep, &rtcHighAfterSleep);
CHECK_PARAM((rtcHighAfterSleep - rtcHighBeforeSleep) <= 1); // make sure sleep less than 1 hour (2^32 us > 1 hour)
actualSleepDuration_32768cycles = (rtcLowAfterSleep - rtcLowBeforeSleep);
actualSleepDuration_ms = (actualSleepDuration_32768cycles >> 5) - (actualSleepDuration_32768cycles >> 11) - (actualSleepDuration_32768cycles >> 12);
// vTaskStepTick(actualSleepDuration_ms);
return actualSleepDuration_ms;
}

1499
drivers/bl702_driver/hal_drv/src/hal_power.c
View File

File diff suppressed because it is too large Load Diff

12
drivers/bl702_driver/hal_drv/src/hal_sec_aes.c
View File

@ -38,15 +38,15 @@ static SEC_ENG_AES_Key_Type sec_aes_get_key_type(sec_aes_handle_t *handle)
SEC_ENG_AES_Key_Type type = 0;
switch (handle->key_type) {
case SEC_ASE_KEY_128:
case SEC_AES_KEY_128:
type = SEC_ENG_AES_KEY_128BITS;
break;
case SEC_ASE_KEY_256:
case SEC_AES_KEY_256:
type = SEC_ENG_AES_KEY_256BITS;
break;
case SEC_ASE_KEY_192:
case SEC_AES_KEY_192:
type = SEC_ENG_AES_KEY_192BITS;
break;
@ -62,19 +62,19 @@ int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len
SEC_ENG_AES_Key_Type type = sec_aes_get_key_type(handle);
switch (handle->aes_type) {
case SEC_ASE_CBC:
case SEC_AES_CBC:
Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0);
Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CBC, type,
SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION);
break;
case SEC_ASE_CTR:
case SEC_AES_CTR:
Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0);
Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CTR, type,
SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION);
break;
case SEC_ASE_ECB:
case SEC_AES_ECB:
break;
default:

125
drivers/bl702_driver/hal_drv/src/hal_timer.c
View File

@ -54,9 +54,12 @@ int timer_open(struct device *dev, uint16_t oflag)
timer_device_t *timer_device = (timer_device_t *)dev;
uint32_t tmpval;
uint64_t compare_count1;
uint64_t compare_count2;
uint64_t compare_count3;
uint32_t compare_count1 = 0;
uint32_t compare_count2 = 0;
uint32_t compare_count3 = 0;
uint32_t reload_val = 0;
uint32_t clkval = 0;
uint32_t unit = 0;
/* Disable all interrupt */
TIMER_IntMask(timer_device->id, TIMER_INT_ALL, MASK);
@ -75,65 +78,45 @@ int timer_open(struct device *dev, uint16_t oflag)
if (timer_device->cnt_mode == TIMER_CNT_PRELOAD) {
BL_WR_WORD(TIMER_BASE + TIMER_TPLVR2_OFFSET + 4 * timer_device->id, timer_device->reload);
reload_val = timer_device->reload;
}
if (timer_device->id == TIMER_CH0) {
compare_count1 = timer_device->timeout1 * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER0) / (1000 * 1000)) + timer_device->reload;
compare_count2 = timer_device->timeout2 * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER0) / (1000 * 1000)) + timer_device->reload;
compare_count3 = timer_device->timeout3 * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER0) / (1000 * 1000)) + timer_device->reload;
clkval = peripheral_clock_get(PERIPHERAL_CLOCK_TIMER0);
} else {
compare_count1 = timer_device->timeout1 * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER1) / (1000 * 1000)) + timer_device->reload;
compare_count2 = timer_device->timeout2 * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER1) / (1000 * 1000)) + timer_device->reload;
compare_count3 = timer_device->timeout3 * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER1) / (1000 * 1000)) + timer_device->reload;
clkval = peripheral_clock_get(PERIPHERAL_CLOCK_TIMER1);
}
if (clkval % 1000000 == 0) {
unit = 1000000; //1us
} else if (clkval % 100000 == 0) {
unit = 100000; //10us
} else if (clkval % 10000 == 0) {
unit = 10000; //100us
} else if (clkval % 1000 == 0) {
unit = 1000; //1ms
} else if (clkval % 100 == 0) {
unit = 100; //10ms
} else if (clkval % 10 == 0) {
unit = 10; //100ms
} else if (clkval % 1 == 0) {
unit = 1; //s
} else {
}
compare_count1 = timer_device->timeout1 / (1000000 / unit) * (clkval / unit) + reload_val;
compare_count2 = timer_device->timeout2 / (1000000 / unit) * (clkval / unit) + reload_val;
compare_count3 = timer_device->timeout3 / (1000000 / unit) * (clkval / unit) + reload_val;
/* Configure match compare values */
if (compare_count1 > 1) {
if ((compare_count1 < 1) || (compare_count2 < 1) || (compare_count3 < 1)) {
return -1;
}
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_0, compare_count1 - 2);
} else {
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_0, compare_count1);
}
if (compare_count2 > 1) {
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_1, compare_count2 - 2);
} else {
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_1, timer_device->timeout2);
}
if (compare_count3 > 1) {
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_2, compare_count3 - 2);
} else {
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_2, timer_device->timeout3);
}
} else {
if (timer_device->id == TIMER_CH0) {
compare_count1 = timer_device->timeout1 * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER0) / (1000 * 1000));
compare_count2 = timer_device->timeout2 * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER0) / (1000 * 1000));
compare_count3 = timer_device->timeout3 * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER0) / (1000 * 1000));
} else {
compare_count1 = timer_device->timeout1 * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER1) / (1000 * 1000));
compare_count2 = timer_device->timeout2 * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER1) / (1000 * 1000));
compare_count3 = timer_device->timeout3 * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER1) / (1000 * 1000));
}
/* Configure match compare values */
if (compare_count1 > 1) {
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_0, compare_count1 - 2);
} else {
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_0, compare_count1);
}
if (compare_count2 > 1) {
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_1, compare_count2 - 2);
} else {
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_1, compare_count2);
}
if (compare_count3 > 1) {
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_2, compare_count3 - 2);
} else {
TIMER_SetCompValue(timer_device->id, TIMER_COMP_ID_2, compare_count3);
}
}
/* Clear interrupt status*/
TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_0);
TIMER_ClearIntStatus(timer_device->id, TIMER_COMP_ID_1);
@ -265,7 +248,10 @@ int timer_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t s
{
timer_device_t *timer_device = (timer_device_t *)dev;
timer_timeout_cfg_t *timeout_cfg = (timer_timeout_cfg_t *)buffer;
uint64_t compare_count;
uint32_t compare_count = 0;
uint32_t reload_val = 0;
uint32_t clkval = 0;
uint32_t unit = 0;
if (size % sizeof(timer_timeout_cfg_t)) {
return -1;
@ -273,11 +259,38 @@ int timer_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t s
/* Disable timer before config */
TIMER_Disable(timer_device->id);
for (uint32_t i = 0; i < size / sizeof(timer_timeout_cfg_t); i++) {
if (timer_device->cnt_mode == TIMER_CNT_PRELOAD) {
reload_val = timer_device->reload;
}
if (timer_device->id == TIMER_CH0) {
compare_count = timeout_cfg->timeout_val * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER0) / (1000 * 1000));
clkval = peripheral_clock_get(PERIPHERAL_CLOCK_TIMER0);
} else {
compare_count = timeout_cfg->timeout_val * (peripheral_clock_get(PERIPHERAL_CLOCK_TIMER1) / (1000 * 1000));
clkval = peripheral_clock_get(PERIPHERAL_CLOCK_TIMER1);
}
if (clkval % 1000000 == 0) {
unit = 1000000; //1us
} else if (clkval % 100000 == 0) {
unit = 100000; //10us
} else if (clkval % 10000 == 0) {
unit = 10000; //100us
} else if (clkval % 1000 == 0) {
unit = 1000; //1ms
} else if (clkval % 100 == 0) {
unit = 100; //10ms
} else if (clkval % 10 == 0) {
unit = 10; //100ms
} else if (clkval % 1 == 0) {
unit = 1; //s
} else {
}
for (uint32_t i = 0; i < size / sizeof(timer_timeout_cfg_t); i++) {
compare_count = timeout_cfg->timeout_val / (1000000 / unit) * (clkval / unit) + reload_val;
if (compare_count < 1) {
return -1;
}
TIMER_SetCompValue(timer_device->id, timeout_cfg->timeout_id, compare_count - 2);
}

10
drivers/bl702_driver/hal_drv/src/hal_uart.c
View File

@ -250,6 +250,10 @@ int uart_control(struct device *dev, int cmd, void *args)
return UART_GetTxFifoCount(uart_device->id);
case DEVICE_CTRL_UART_GET_RX_FIFO /* constant-expression */:
return UART_GetRxFifoCount(uart_device->id);
case DEVICE_CTRL_UART_CLEAR_TX_FIFO /* constant-expression */:
return UART_TxFifoClear(uart_device->id);
case DEVICE_CTRL_UART_CLEAR_RX_FIFO /* constant-expression */:
return UART_RxFifoClear(uart_device->id);
default:
break;
}
@ -402,17 +406,17 @@ void uart_isr(uart_device_t *handle)
/* Rx parity check error interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) {
BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20);
handle->parent.callback(&handle->parent, NULL, 0, UART_PCE_IT);
handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_PCE);
}
/* Tx fifo overflow/underflow error interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) {
handle->parent.callback(&handle->parent, NULL, 0, UART_TX_FER_IT);
handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_FER);
}
/* Rx fifo overflow/underflow error interrupt */
if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) {
handle->parent.callback(&handle->parent, NULL, 0, UART_RX_FER_IT);
handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_RX_FER);
}
}

68
drivers/bl702_driver/hal_drv/src/hal_usb.c
View File

@ -567,15 +567,77 @@ int usb_dc_ep_close(const uint8_t ep)
*/
int usb_dc_ep_set_stall(const uint8_t ep)
{
uint32_t tmpVal = 0;
uint8_t ep_idx = USB_EP_GET_IDX(ep);
if (USB_EP_DIR_IS_OUT(ep)) {
USB_Set_EPx_Status(ep_idx, USB_EP_STATUS_STALL);
usb_fs_device.out_ep[ep_idx].is_stalled = 1U;
} else {
USB_Set_EPx_Status(ep_idx, USB_EP_STATUS_STALL);
usb_fs_device.in_ep[ep_idx].is_stalled = 1U;
}
switch (ep_idx) {
case 0:
tmpVal = BL_RD_REG(USB_BASE, USB_CONFIG);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_RDY);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_OUT);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_NACK_IN);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_USB_EP0_SW_STALL);
BL_WR_REG(USB_BASE, USB_CONFIG, tmpVal);
break;
case 1:
tmpVal = BL_RD_REG(USB_BASE, USB_EP1_CONFIG);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_RDY);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_NACK);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP1_STALL);
BL_WR_REG(USB_BASE, USB_EP1_CONFIG, tmpVal);
break;
case 2:
tmpVal = BL_RD_REG(USB_BASE, USB_EP2_CONFIG);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_RDY);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_NACK);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP2_STALL);
BL_WR_REG(USB_BASE, USB_EP2_CONFIG, tmpVal);
break;
case 3:
tmpVal = BL_RD_REG(USB_BASE, USB_EP3_CONFIG);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_RDY);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_NACK);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP3_STALL);
BL_WR_REG(USB_BASE, USB_EP3_CONFIG, tmpVal);
break;
case 4:
tmpVal = BL_RD_REG(USB_BASE, USB_EP4_CONFIG);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_RDY);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_NACK);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP4_STALL);
BL_WR_REG(USB_BASE, USB_EP4_CONFIG, tmpVal);
break;
case 5:
tmpVal = BL_RD_REG(USB_BASE, USB_EP5_CONFIG);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_RDY);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_NACK);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP5_STALL);
BL_WR_REG(USB_BASE, USB_EP5_CONFIG, tmpVal);
break;
case 6:
tmpVal = BL_RD_REG(USB_BASE, USB_EP6_CONFIG);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_RDY);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_NACK);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP6_STALL);
BL_WR_REG(USB_BASE, USB_EP6_CONFIG, tmpVal);
break;
case 7:
tmpVal = BL_RD_REG(USB_BASE, USB_EP7_CONFIG);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_RDY);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_NACK);
tmpVal = BL_SET_REG_BIT(tmpVal, USB_CR_EP7_STALL);
BL_WR_REG(USB_BASE, USB_EP7_CONFIG, tmpVal);
break;
default:
break;
}
return 0;
}
/**
@ -952,7 +1014,7 @@ void usb_dc_isr(usb_dc_device_t *device)
}
}
/* reset */
/* sof */
if (USB_Get_IntStatus(USB_INT_SOF)) {
USB_DC_LOG("sof\r\n");
device->parent.callback(&device->parent, NULL, 0, USB_DC_EVENT_SOF);

5
drivers/bl702_driver/regs/bl702.h
View File

@ -311,9 +311,8 @@ typedef enum {
/* RISCV CPU include files */
#ifdef ARCH_RISCV
#ifdef __GNUC__
#include "cmsis_compatible_gcc.h"
#include "clic.h"
#include "riscv_encoding.h"
#include "../risc-v/Core/Include/clic.h"
#include "../risc-v/Core/Include/riscv_encoding.h"
#endif
#endif

132
drivers/bl702_driver/risc-v/Core/Include/cmsis_compatible_gcc.h
View File

@ -1,132 +0,0 @@
#ifndef __CMSIS_COMPATIBLE_GCC_H
#define __CMSIS_COMPATIBLE_GCC_H
/* CMSIS compiler specific defines */
#ifndef __ASM
#define __ASM __asm
#endif
#ifndef __INLINE
#define __INLINE inline
#endif
#ifndef __ALWAYS_INLINE
#define __ALWAYS_INLINE inline __attribute__((always_inline))
#endif
#ifndef __STATIC_INLINE
#define __STATIC_INLINE static inline
#endif
#ifndef __NO_RETURN
#define __NO_RETURN __attribute__((noreturn))
#endif
#ifndef __USED
#define __USED __attribute__((used))
#endif
#ifndef __WEAK
#define __WEAK __attribute__((weak))
#endif
#ifndef __PACKED
#define __PACKED __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_STRUCT
#define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
#endif
#ifndef __PACKED_UNION
#define __PACKED_UNION union __attribute__((packed, aligned(1)))
#endif
#ifndef __IRQ
#define __IRQ __attribute__((interrupt))
#endif
#ifndef __IRQ_ALIGN64
#define __IRQ_ALIGN64 __attribute__((interrupt, aligned(64)))
#endif
#ifndef ALIGN4
#define ALIGN4 __attribute((aligned(4)))
#endif
/**
\brief No Operation
\details No Operation does nothing. This instruction can be used for code alignment purposes.
*/
//__attribute__((always_inline)) __STATIC_INLINE void __NOP(void)
//{
// __ASM volatile ("nop");
//}
#define __NOP() __ASM volatile("nop") /* This implementation generates debug information */
/**
\brief Wait For Interrupt
\details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs.
*/
//__attribute__((always_inline)) __STATIC_INLINE void __WFI(void)
//{
// __ASM volatile ("wfi");
//}
#define __WFI() __ASM volatile("wfi") /* This implementation generates debug information */
/**
\brief Wait For Event
\details Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
//__attribute__((always_inline)) __STATIC_INLINE void __WFE(void)
//{
// __ASM volatile ("wfe");
//}
#define __WFE() __ASM volatile("wfe") /* This implementation generates debug information */
/**
\brief Send Event
\details Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
//__attribute__((always_inline)) __STATIC_INLINE void __SEV(void)
//{
// __ASM volatile ("sev");
//}
#define __SEV() __ASM volatile("sev") /* This implementation generates debug information */
static uint8_t nesting2 = 0;
__attribute__((always_inline)) __STATIC_INLINE void __enable_irq(void)
{
nesting2--;
if (nesting2 == 0) {
__ASM volatile("csrsi mstatus, 8");
}
}
__attribute__((always_inline)) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile("csrci mstatus, 8");
nesting2++;
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
//return __builtin_bswap32(value);
uint32_t res = 0;
res = (value << 24) | (value >> 24);
res &= 0xFF0000FF; /* only for sure */
res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000);
return res;
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
return __builtin_bswap16(value);
}
extern void clic_enable_interrupt(uint32_t source);
extern void clic_disable_interrupt(uint32_t source);
extern void clic_set_pending(uint32_t source);
extern void clic_clear_pending(uint32_t source);
#define CPU_Interrupt_Enable clic_enable_interrupt
#define CPU_Interrupt_Disable clic_disable_interrupt
#define CPU_Interrupt_Pending_Clear clic_clear_pending
//#define __set_MSP(val) __ASM volatile ("lw sp,0(%0)":: "r"(val))
#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp))
#endif /* __CMSIS_COMPATIBLE_GCC_H */

2
drivers/bl702_driver/startup/GCC/entry.S
View File

@ -1,6 +1,6 @@
/* Copyright 2018 SiFive, Inc */
/* SPDX-License-Identifier: Apache-2.0 */
#include "riscv_encoding.h"
#include "../risc-v/Core/Include/riscv_encoding.h"
/* This code executes before _start, which is contained inside the C library.
* In embedded systems we want to ensure that _enter, which contains the first

164
drivers/bl702_driver/startup/interrupt.c
View File

@ -20,15 +20,11 @@
* under the License.
*
*/
#include "bl702_common.h"
#include "bl702.h"
#include <stdint.h>
pFunc __Interrupt_Handlers[IRQn_LAST] = { 0 };
#include "../risc-v/Core/Include/clic.h"
#include "../risc-v/Core/Include/cmsis_compatible_gcc.h"
typedef void (*pFunc)(void);
extern void Trap_Handler(void);
extern void Interrupt_Handler(void);
void Interrupt_Handler_Stub(void);
void clic_msip_handler_Wrapper(void) __attribute__((weak, alias("Interrupt_Handler_Stub")));
@ -175,6 +171,134 @@ const pFunc __Vectors[] __attribute__((section(".init"), aligned(64))) = {
WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */
};
void Trap_Handler(void)
{
unsigned long cause;
unsigned long epc;
unsigned long tval;
uint8_t isecall = 0;
MSG("Trap_Handler\r\n");
cause = read_csr(mcause);
MSG("mcause=%08x\r\n", (uint32_t)cause);
epc = read_csr(mepc);
MSG("mepc:%08x\r\n", (uint32_t)epc);
tval = read_csr(mtval);
MSG("mtval:%08x\r\n", (uint32_t)tval);
cause = (cause & 0x3ff);
switch (cause) {
case 1:
MSG("Instruction access fault\r\n");
break;
case 2:
MSG("Illegal instruction\r\n");
break;
case 3:
MSG("Breakpoint\r\n");
break;
case 4:
MSG("Load address misaligned\r\n");
break;
case 5:
MSG("Load access fault\r\n");
break;
case 6:
MSG("Store/AMO address misaligned\r\n");
break;
case 7:
MSG("Store/AMO access fault\r\n");
break;
case 8:
MSG("Environment call from U-mode\r\n");
epc += 4;
write_csr(mepc, epc);
break;
case 11:
MSG("Environment call from M-mode\r\n");
epc += 4;
write_csr(mepc, epc);
isecall = 1;
break;
default:
MSG("Cause num=%d\r\n", (uint32_t)cause);
epc += 4;
write_csr(mepc, epc);
break;
}
if (!isecall) {
while (1)
;
}
}
void Interrupt_Handler(void)
{
pFunc interruptFun;
uint32_t num = 0;
volatile uint32_t ulMEPC = 0UL, ulMCAUSE = 0UL;
/* Store a few register values that might be useful when determining why this
function was called. */
__asm volatile("csrr %0, mepc"
: "=r"(ulMEPC));
__asm volatile("csrr %0, mcause"
: "=r"(ulMCAUSE));
if ((ulMCAUSE & 0x80000000) == 0) {
/*Exception*/
MSG("Exception should not be here\r\n");
} else {
num = ulMCAUSE & 0x3FF;
if (num < IRQn_LAST) {
interruptFun = __Interrupt_Handlers[num];
if (NULL != interruptFun) {
interruptFun();
} else {
MSG("Interrupt num:%d IRQHandler not installed\r\n", (unsigned int)num);
if (num >= IRQ_NUM_BASE) {
MSG("Peripheral Interrupt num:%d \r\n", (unsigned int)num - IRQ_NUM_BASE);
}
while (1)
;
}
} else {
MSG("Unexpected interrupt num:%d\r\n", (unsigned int)num);
}
}
}
void handle_trap(void)
{
#define MCAUSE_INT_MASK 0x80000000 // [31]=1 interrupt, else exception
#define MCAUSE_CODE_MASK 0x7FFFFFFF // low bits show code
unsigned long mcause_value = read_csr(mcause);
if (mcause_value & MCAUSE_INT_MASK) {
// Branch to interrupt handler here
Interrupt_Handler();
} else {
// Branch to exception handle
Trap_Handler();
}
}
void __IRQ_ALIGN64 Trap_Handler_Stub(void)
{
Trap_Handler();
@ -185,6 +309,22 @@ void __IRQ Interrupt_Handler_Stub(void)
Interrupt_Handler();
}
void FreeRTOS_Interrupt_Handler(void)
{
Interrupt_Handler();
}
void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun)
{
if (irq < IRQn_LAST) {
__Interrupt_Handlers[irq] = interruptFun;
}
}
void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
}
void clic_enable_interrupt(uint32_t source)
{
*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 1;
@ -195,16 +335,16 @@ void clic_disable_interrupt(uint32_t source)
*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 0;
}
void clic_set_pending(uint32_t source)
{
*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1;
}
void clic_clear_pending(uint32_t source)
{
*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 0;
}
void clic_set_pending(uint32_t source)
{
*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1;
}
void clic_set_intcfg(uint32_t source, uint32_t intcfg)
{
*(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTCFG + source) = intcfg;

20
drivers/bl702_driver/startup/system_bl702.c
View File

@ -20,11 +20,9 @@
* under the License.
*
*/
#include "bl702.h"
#include "bl702_glb.h"
#include "bl702_hbn.h"
#include "system_bl702.h"
#ifdef BFLB_EFLASH_LOADER
#include "bl702_usb.h"
@ -69,16 +67,6 @@ void SystemInit(void)
/* global IRQ disable */
__disable_irq();
/*disable wakeup irq and aon ie*/
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, 0x1f);
/* disable aon_pad_ie_smt (reg_aon_pad_ie_smt = 0) */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, 0);
/* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE);
BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
tmpVal |= (1 << 8); /*mask pds wakeup*/
tmpVal |= (1 << 10); /*mask rf done*/
@ -86,10 +74,6 @@ void SystemInit(void)
tmpVal &= ~(0xff << 16); /*mask all pds wakeup source int*/
BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_MODE, PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE);
BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
/* GLB_Set_EM_Sel(GLB_EM_0KB); */
tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, GLB_EM_0KB);
@ -160,7 +144,3 @@ void System_Post_Init(void)
flash_init();
bflb_platform_print_set(0);
}
void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
{
}

14
drivers/bl702_driver/startup/system_bl702.h
View File

@ -29,11 +29,17 @@
*/
extern uint32_t SystemCoreClock;
typedef void (*pFunc)(void);
#define CPU_Interrupt_Enable clic_enable_interrupt
#define CPU_Interrupt_Disable clic_disable_interrupt
#define CPU_Interrupt_Pending_Clear clic_clear_pending
extern void SystemCoreClockUpdate(void);
extern void SystemInit(void);
extern void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
extern void Systick_Stop(void);
extern void Systick_Start(void);
void clic_enable_interrupt(uint32_t source);
void clic_disable_interrupt(uint32_t source);
void clic_clear_pending(uint32_t source);
void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun);
void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
#endif

96
drivers/bl702_driver/std_drv/inc/bl702_common.h
View File

@ -4,58 +4,62 @@
#include "bl702.h"
#include "bflb_platform.h"
/** @addtogroup BL606_Peripheral_Driver
* @{
#ifndef __NOP
#define __NOP() __ASM volatile("nop") /* This implementation generates debug information */
#endif
#ifndef __WFI
#define __WFI() __ASM volatile("wfi") /* This implementation generates debug information */
#endif
#ifndef __WFE
#define __WFE() __ASM volatile("wfe") /* This implementation generates debug information */
#endif
#ifndef __SEV
#define __SEV() __ASM volatile("sev") /* This implementation generates debug information */
#endif
#ifndef __set_MSP
#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp))
#endif
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
//return __builtin_bswap32(value);
uint32_t res = 0;
res = (value << 24) | (value >> 24);
res &= 0xFF0000FF; /* only for sure */
res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000);
return res;
}
__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
return __builtin_bswap16(value);
}
/**
\brief Enable IRQ Interrupts
\details Enables IRQ interrupts by setting the IE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __enable_irq(void)
{
__ASM volatile("csrs mstatus, 8");
}
/** @addtogroup COMMON
* @{
/**
\brief Disable IRQ Interrupts
\details Disables IRQ interrupts by clearing the IE-bit in the PSR.
Can only be executed in Privileged modes.
*/
__ALWAYS_STATIC_INLINE void __disable_irq(void)
{
__ASM volatile("csrc mstatus, 8");
}
/** @defgroup COMMON_Public_Types
* @{
*/
/*@} end of group COMMON_Public_Types */
/** @defgroup COMMON_Public_Constants
* @{
*/
/** @defgroup DRIVER_INT_PERIPH
* @{
*/
#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST)
/*@} end of group DRIVER_INT_PERIPH */
/** @defgroup DRIVER_INT_MASK
* @{
*/
#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK))
/*@} end of group COMMON_Public_Constants */
/** @defgroup COMMON_Public_Macros
* @{
*/
/*@} end of group DRIVER_Public_Macro */
/** @defgroup DRIVER_Public_FunctionDeclaration
* @brief DRIVER functions declaration
* @{
*/
#define ARCH_Delay_US BL702_Delay_US
#define ARCH_Delay_MS BL702_Delay_MS
#define arch_delay_us BL702_Delay_US
#define arch_delay_ms BL702_Delay_MS
void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun);
void ASM_Delay_Us(uint32_t core, uint32_t cnt);
void BL702_Delay_US(uint32_t cnt);
void BL702_Delay_MS(uint32_t cnt);
/*@} end of group DRIVER_COMMON */
#endif /* __BL702_COMMON_H__ */
#endif

8
drivers/bl702_driver/std_drv/inc/bl702_emac.h
View File

@ -118,7 +118,6 @@ typedef struct
uint8_t macAddr[6]; /*!< MAC Address */
} EMAC_CFG_Type;
/**
* @brief EMAC TX DMA description type definition
*/
@ -206,6 +205,8 @@ typedef struct
#define BD_TX_RTRY_LEN (4)
#define BD_TX_UR_POS (8) /*!< Underrun */
#define BD_TX_UR_LEN (1)
#define BD_TX_EOF_POS (10) /*!< EOF */
#define BD_TX_EOF_LEN (1)
#define BD_TX_CRC_POS (11) /*!< CRC Enable */
#define BD_TX_CRC_LEN (1)
#define BD_TX_PAD_POS (12) /*!< PAD enable */
@ -250,7 +251,10 @@ typedef struct
#define EMAC_BD_FIELD_UMSK(field) (~(((1U << BD_##field##_LEN) - 1) << BD_##field##_POS))
/* DMA Descriptor offset */
#define EMAC_DMA_DESC_OFFSET 0x400
/* ETH packet size */
// ETH | Header | Extra | VLAN tag | Payload | CRC |
// Size | 14 | 2 | 4 | 46 ~ 1500 | 4 |
#define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
#define ETH_HEADER_SZIE ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
#define ETH_CRC_SIZE ((uint32_t)4U) /*!< Ethernet CRC */
@ -287,6 +291,8 @@ BL_Err_Type EMAC_Phy_Write(uint16_t phyReg, uint16_t regValue);
BL_Err_Type EMAC_Enable_TX(void);
BL_Err_Type EMAC_Disable_TX(void);
BL_Err_Type EMAC_Enable_RX(void);
BL_Err_Type EMAC_Disable_RX(void);
void EMAC_Phy_SetAddress(uint16_t phyAddress);
void EMAC_Phy_Set_Full_Duplex(uint8_t fullDuplex);

23
drivers/bl702_driver/std_drv/inc/bl702_gpio.h
View File

@ -147,16 +147,6 @@ typedef enum {
GPIO_FUN_KEY_SCAN_DRIVE = 22,
GPIO_FUN_KEY_SCAN_COL = 22,
GPIO_FUN_CAM_MISC = 23,
GPIO_FUN_GPIO_INPUT_UP = 0x0B,
GPIO_FUN_GPIO_INPUT_DOWN = 0x1B,
GPIO_FUN_GPIO_INPUT_NONE = 0x2B,
GPIO_FUN_GPIO_OUTPUT_UP = 0x9B,
GPIO_FUN_GPIO_OUTPUT_DOWN = 0xAB,
GPIO_FUN_GPIO_OUTPUT_NONE = 0xBB,
GPIO_FUN_GPIO_EXTI_RISING_EDGE = 0xfe,
GPIO_FUN_GPIO_EXTI_FALLING_EDGE = 0xfc,
GPIO_FUN_GPIO_EXTI_HIGH_LEVEL = 0xfb,
GPIO_FUN_GPIO_EXTI_LOW_LEVEL = 0xfa,
GPIO_FUN_UART0_RTS = 0x70,
GPIO_FUN_UART0_CTS = 0x71,
GPIO_FUN_UART0_TX = 0x72,
@ -165,8 +155,17 @@ typedef enum {
GPIO_FUN_UART1_CTS = 0x75,
GPIO_FUN_UART1_TX = 0x76,
GPIO_FUN_UART1_RX = 0x77,
GPIO_FUN_WAKEUP = 254,
GPIO_FUN_LP_WAKEUP_DUMMY = 254,
GPIO_FUN_GPIO_OUTPUT_UP = 240,
GPIO_FUN_GPIO_OUTPUT_DOWN = 241,
GPIO_FUN_GPIO_OUTPUT_NONE = 242,
GPIO_FUN_GPIO_INPUT_UP = 243,
GPIO_FUN_GPIO_INPUT_DOWN = 244,
GPIO_FUN_GPIO_INPUT_NONE = 245,
GPIO_FUN_GPIO_EXTI_RISING_EDGE = 246,
GPIO_FUN_GPIO_EXTI_FALLING_EDGE = 247,
GPIO_FUN_GPIO_EXTI_HIGH_LEVEL = 248,
GPIO_FUN_GPIO_EXTI_LOW_LEVEL = 249,
GPIO_FUN_WAKEUP = 250,
GPIO_FUN_UNUSED = 255
} GLB_GPIO_FUNC_Type;

1
drivers/bl702_driver/std_drv/inc/bl702_hbn.h
View File

@ -450,6 +450,7 @@ typedef struct
#define HBN_STATUS_ENTER_FLAG 0x4e424845
#define HBN_STATUS_WAKEUP_FLAG 0x4e424857
#define HBN_WAKEUP_GPIO_NONE 0x00
#define HBN_WAKEUP_GPIO_9 0x01
#define HBN_WAKEUP_GPIO_10 0x02
#define HBN_WAKEUP_GPIO_11 0x04
#define HBN_WAKEUP_GPIO_12 0x08

1
drivers/bl702_driver/std_drv/inc/bl702_sflash_ext.h
View File

@ -72,6 +72,7 @@ BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readR
uint8_t regLen);
BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue,
uint8_t regLen);
BL_Err_Type SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *pFlashCfg);
/*@} end of group SFLAH_EXT_Public_Functions */

4
drivers/bl702_driver/std_drv/inc/bl702_xip_sflash.h
View File

@ -85,10 +85,6 @@ BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_C
BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode,
uint8_t *data, uint8_t idLen);
BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len);
int XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *dst, int len);
int XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *src,
int len);
int XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, int len);
/*@} end of group XIP_SFLASH_Public_Functions */

7
drivers/bl702_driver/std_drv/inc/bl702_xip_sflash_ext.h
View File

@ -39,6 +39,8 @@
#include "bl702_common.h"
#include "bl702_sflash.h"
#include "bl702_xip_sflash.h"
#include "bl702_sflash.h"
#include "bl702_sflash_ext.h"
#include "bl702_sf_cfg.h"
#include "bl702_sf_cfg_ext.h"
@ -72,10 +74,7 @@
* @{
*/
BL_Err_Type XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg);
int XIP_SFlash_Read(uint32_t addr, uint8_t *dst, int len);
int XIP_SFlash_Write(uint32_t addr, uint8_t *src, int len);
int XIP_SFlash_Erase(uint32_t addr, int len);
BL_Err_Type XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg);
/*@} end of group XIP_SFLASH_EXT_Public_Functions */

172
drivers/bl702_driver/std_drv/src/bl702_common.c
View File

@ -40,177 +40,6 @@
* @{
*/
/** @defgroup DRIVER_COMMON DRIVER_COMMON
* @brief Digger driver common functions
* @{
*/
/** @defgroup DRIVER_Private_Type
* @{
*/
/*@} end of group DRIVER_Private_Type*/
/** @defgroup DRIVER_Private_Defines
* @{
*/
/*@} end of group DRIVER_Private_Defines */
/** @defgroup DRIVER_Private_Variables
* @{
*/
pFunc __Interrupt_Handlers[IRQn_LAST] = { 0 };
/*@} end of group DRIVER_Private_Variables */
/** @defgroup DRIVER_Global_Variables
* @{
*/
/*@} end of group DRIVER_Global_Variables */
/** @defgroup DRIVER_Private_FunctionDeclaration
* @{
*/
/*@} end of group DRIVER_Private_FunctionDeclaration */
/** @defgroup DRIVER_Private_Functions
* @{
*/
/*@} end of group DRIVER_Private_Functions */
/** @defgroup DRIVER_Public_Functions
* @{
*/
void Trap_Handler(void)
{
unsigned long cause;
unsigned long epc;
unsigned long tval;
uint8_t isecall = 0;
MSG("Trap_Handler\r\n");
cause = read_csr(mcause);
MSG("mcause=%08x\r\n", (uint32_t)cause);
epc = read_csr(mepc);
MSG("mepc:%08x\r\n", (uint32_t)epc);
tval = read_csr(mtval);
MSG("mtval:%08x\r\n", (uint32_t)tval);
cause = (cause & 0x3ff);
switch (cause) {
case 1:
MSG("Instruction access fault\r\n");
break;
case 2:
MSG("Illegal instruction\r\n");
break;
case 3:
MSG("Breakpoint\r\n");
break;
case 4:
MSG("Load address misaligned\r\n");
break;
case 5:
MSG("Load access fault\r\n");
break;
case 6:
MSG("Store/AMO address misaligned\r\n");
break;
case 7:
MSG("Store/AMO access fault\r\n");
break;
case 8:
MSG("Environment call from U-mode\r\n");
epc += 4;
write_csr(mepc, epc);
break;
case 11:
MSG("Environment call from M-mode\r\n");
epc += 4;
write_csr(mepc, epc);
isecall = 1;
break;
default:
MSG("Cause num=%d\r\n", (uint32_t)cause);
epc += 4;
write_csr(mepc, epc);
break;
}
if (!isecall) {
while (1)
;
}
}
void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun)
{
if (irq < IRQn_LAST) {
__Interrupt_Handlers[irq] = interruptFun;
}
}
void Interrupt_Handler(void)
{
pFunc interruptFun;
uint32_t num = 0;
volatile uint32_t ulMEPC = 0UL, ulMCAUSE = 0UL;
/* Store a few register values that might be useful when determining why this
function was called. */
__asm volatile("csrr %0, mepc"
: "=r"(ulMEPC));
__asm volatile("csrr %0, mcause"
: "=r"(ulMCAUSE));
if ((ulMCAUSE & 0x80000000) == 0) {
/*Exception*/
MSG("Exception should not be here\r\n");
} else {
num = ulMCAUSE & 0x3FF;
if (num < IRQn_LAST) {
interruptFun = __Interrupt_Handlers[num];
if (NULL != interruptFun) {
interruptFun();
} else {
MSG("Interrupt num:%d IRQHandler not installed\r\n", (unsigned int)num);
if (num >= IRQ_NUM_BASE) {
MSG("Peripheral Interrupt num:%d \r\n", (unsigned int)num - IRQ_NUM_BASE);
}
while (1)
;
}
} else {
MSG("Unexpected interrupt num:%d\r\n", (unsigned int)num);
}
}
}
void FreeRTOS_Interrupt_Handler(void)
{
Interrupt_Handler();
}
/****************************************************************************/ /**
* @brief delay us
*
@ -363,6 +192,7 @@ void ATTR_TCM_SECTION BL702_Delay_MS(uint32_t cnt)
//BL702_Delay_US(((cnt<<10)-(cnt<<4)-(cnt<<3)));
}
#endif
/*
char *_sbrk(int incr)
{}

40
drivers/bl702_driver/std_drv/src/bl702_emac.c
View File

@ -424,6 +424,46 @@ BL_Err_Type EMAC_Disable_TX(void)
return SUCCESS;
}
/****************************************************************************/ /**
* @brief EMAC_Enable_RX
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type EMAC_Enable_RX(void)
{
uint32_t tmpval;
/* Enable EMAC TX*/
tmpval = BL_RD_REG(EMAC_BASE, EMAC_MODE);
tmpval = BL_SET_REG_BIT(tmpval, EMAC_RXEN);
BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpval);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief EMAC_Disable_RX
*
* @param None
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type EMAC_Disable_RX(void)
{
uint32_t tmpval;
/* Disable EMAC RX*/
tmpval = BL_RD_REG(EMAC_BASE, EMAC_MODE);
tmpval = BL_CLR_REG_BIT(tmpval, EMAC_RXEN);
BL_WR_REG(EMAC_BASE, EMAC_MODE, tmpval);
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Disable EMAC module
*

6
drivers/bl702_driver/std_drv/src/bl702_glb.c
View File

@ -150,8 +150,6 @@ GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void)
* @return SUCCESS or ERROR
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv)
{
/***********************************************************************************/
@ -179,7 +177,6 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t b
return SUCCESS;
}
#endif
/****************************************************************************/ /**
* @brief Get Bus clock divider
@ -3085,7 +3082,6 @@ BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
uint32_t pos;
uint32_t tmpOut;
uint32_t tmpVal;
uint32_t aonPadIeSmt;
/* drive strength(drive) = 0 <=> 8.0mA @ 3.3V */
/* drive strength(drive) = 1 <=> 9.6mA @ 3.3V */
@ -3188,7 +3184,7 @@ BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
/* always on pads IE control (in HBN) */
if (gpioPin >= 9 && gpioPin <= 13) {
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
uint32_t aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
if (cfg->gpioMode != GPIO_MODE_ANALOG) {
/* not analog mode */

11
drivers/bl702_driver/std_drv/src/bl702_hbn.c
View File

@ -111,7 +111,6 @@ void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg)
{
uint32_t valLow = 0, valHigh = 0;
uint64_t val;
uint32_t tmpVal = 0, tmpVal2 = 0;
/* work clock select */
if (cfg->useXtal32k) {
@ -147,16 +146,6 @@ void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg)
HBN_Aon_Pad_IeSmt_Cfg(0);
}
/* always disable and mask aon_pad_GPIO9, mask/unmask and ie_enable/ie_disable */
tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK);
tmpVal2 |= (1 << 0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, tmpVal2);
tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
tmpVal2 &= ~(1 << 0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, tmpVal2);
BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
/* HBN RTC config and enable */
if (cfg->sleepTime != 0) {
// set rtc enable flag

4
drivers/bl702_driver/std_drv/src/bl702_romapi.c
View File

@ -107,14 +107,14 @@ __ALWAYS_INLINE ATTR_CLOCK_SECTION
{
return RomDriver_GLB_Get_Root_CLK_Sel();
}
#if 0
__ALWAYS_INLINE ATTR_CLOCK_SECTION
BL_Err_Type
GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv)
{
return RomDriver_GLB_Set_System_CLK_Div(hclkDiv, bclkDiv);
}
#endif
__ALWAYS_INLINE ATTR_CLOCK_SECTION
uint8_t
GLB_Get_BCLK_Div(void)

58
drivers/bl702_driver/std_drv/src/bl702_sflash_ext.c
View File

@ -174,6 +174,64 @@ BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flash
return SUCCESS;
}
/****************************************************************************//**
* @brief Clear flash status register
*
* @param pFlashCfg: Flash configuration pointer
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type ATTR_TCM_SECTION SFlash_Clear_Status_Register(SPI_Flash_Cfg_Type *pFlashCfg)
{
uint32_t ret = 0;
uint32_t qeValue = 0;
uint32_t regValue = 0;
uint32_t readValue = 0;
uint8_t readRegValue0 = 0;
uint8_t readRegValue1 = 0;
if((pFlashCfg->ioMode&0xf)==SF_CTRL_QO_MODE || (pFlashCfg->ioMode&0xf)==SF_CTRL_QIO_MODE){
qeValue = 1;
}
SFlash_Read_Reg(pFlashCfg, 0, (uint8_t *)&readRegValue0, 1);
SFlash_Read_Reg(pFlashCfg, 1, (uint8_t *)&readRegValue1, 1);
readValue = (readRegValue0|(readRegValue1<<8));
if ((readValue & (~((1<<(pFlashCfg->qeIndex*8+pFlashCfg->qeBit)) |
(1<<(pFlashCfg->busyIndex*8+pFlashCfg->busyBit)) |
(1<<(pFlashCfg->wrEnableIndex*8+pFlashCfg->wrEnableBit))))) == 0){
return SUCCESS;
}
ret = SFlash_Write_Enable(pFlashCfg);
if (SUCCESS != ret) {
return ERROR;
}
if (pFlashCfg->qeWriteRegLen == 2) {
regValue = (qeValue<<(pFlashCfg->qeIndex*8+pFlashCfg->qeBit));
SFlash_Write_Reg(pFlashCfg, 0, (uint8_t *)&regValue, 2);
} else {
if (pFlashCfg->qeIndex == 0) {
regValue = (qeValue<<pFlashCfg->qeBit);
} else {
regValue = 0;
}
SFlash_Write_Reg(pFlashCfg, 0, (uint8_t *)&regValue, 1);
ret = SFlash_Write_Enable(pFlashCfg);
if (SUCCESS != ret) {
return ERROR;
}
if (pFlashCfg->qeIndex == 1) {
regValue = (qeValue<<pFlashCfg->qeBit);
} else {
regValue = 0;
}
SFlash_Write_Reg(pFlashCfg, 1, (uint8_t *)&regValue, 1);
}
return SUCCESS;
}
/*@} end of group SFLASH_EXT_Public_Functions */
/*@} end of group SFLASH_EXT */

21
drivers/bl702_driver/std_drv/src/bl702_spi.c
View File

@ -303,20 +303,25 @@ BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk)
uint32_t tmpVal;
uint32_t SPIx = spiAddr[spiNo];
if (clk < 4395) {
clk = 4395;
}
if(clk > 36000000) {
clk = 36000000;
}
if (clk > 140625) {
glb_div = 1;
spi_div = 1;
} else if(clk > 140625) {
glb_div = 1;
spi_div = 36000000 / clk;
} else if(clk > 70312) {
glb_div = 2;
spi_div = 18000000 / clk;
} else if(clk > 35156) {
glb_div = 4;
spi_div = 9000000 / clk;
} else if(clk > 4394) {
glb_div = 32;
spi_div = 1125000 / clk;
} else {
glb_div = 32;
spi_div = 256;
glb_div = clk >> 8;
}
/* Configure length of data phase1/0 and start/stop condition */

68
drivers/bl702_driver/std_drv/src/bl702_xip_sflash.c
View File

@ -397,74 +397,6 @@ BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr,
}
#endif
/****************************************************************************/ /**
* @brief Read data from flash with lock
*
* @param pFlashCfg: Flash config pointer
* @param ioMode: flash controller interface mode
* @param addr: flash read start address
* @param dst: data pointer to store data read from flash
* @param len: data length to read
*
* @return 0
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Read_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *dst, int len)
{
__disable_irq();
XIP_SFlash_Read_Need_Lock(pFlashCfg, ioMode, addr, dst, len);
__enable_irq();
return 0;
}
#endif
/****************************************************************************/ /**
* @brief Program flash one region with lock
*
* @param pFlashCfg: Flash config pointer
* @param ioMode: flash controller interface mode
* @param addr: Start address to be programed
* @param src: Data pointer to be programed
* @param len: Data length to be programed
*
* @return 0
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Write_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *src, int len)
{
__disable_irq();
XIP_SFlash_Write_Need_Lock(pFlashCfg, ioMode, addr, src, len);
__enable_irq();
return 0;
}
#endif
/****************************************************************************/ /**
* @brief Erase flash one region with lock
*
* @param pFlashCfg: Flash config pointer
* @param ioMode: flash controller interface mode
* @param addr: Start address to be erased
* @param len: Data length to be erased
*
* @return 0
*
*******************************************************************************/
#ifndef BFLB_USE_ROM_DRIVER
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Erase_With_Lock(SPI_Flash_Cfg_Type *pFlashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, int len)
{
__disable_irq();
XIP_SFlash_Erase_Need_Lock(pFlashCfg, ioMode, addr, addr + len - 1);
__enable_irq();
return 0;
}
#endif
/*@} end of group XIP_SFLASH_Public_Functions */
/*@} end of group XIP_SFLASH */

89
drivers/bl702_driver/std_drv/src/bl702_xip_sflash_ext.c
View File

@ -61,8 +61,6 @@
* @{
*/
static SPI_Flash_Cfg_Type flashCfg;
/*@} end of group XIP_SFLASH_EXT_Private_Variables */
/** @defgroup XIP_SFLASH_EXT_Global_Variables
@ -82,7 +80,7 @@ static SPI_Flash_Cfg_Type flashCfg;
*/
/****************************************************************************//**
* @brief Read data from flash with lock
* @brief Clear flash status register need lock
*
* @param pFlashCfg: Flash config pointer
*
@ -90,86 +88,21 @@ static SPI_Flash_Cfg_Type flashCfg;
*
*******************************************************************************/
__WEAK
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Init(SPI_Flash_Cfg_Type *pFlashCfg)
BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Clear_Status_Register_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg)
{
uint32_t ret;
BL_Err_Type stat;
uint32_t offset;
SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode&0xf;
if (pFlashCfg == NULL) {
/* Get flash config identify */
XIP_SFlash_Opt_Enter();
ret = SF_Cfg_Flash_Identify_Ext(1, 1, 0, 0, &flashCfg);
XIP_SFlash_Opt_Exit();
if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0) {
return ERROR;
}
stat=XIP_SFlash_State_Save(pFlashCfg, &offset);
if (stat != SUCCESS) {
SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32);
} else {
memcpy(&flashCfg, pFlashCfg, sizeof(flashCfg));
stat=SFlash_Clear_Status_Register(pFlashCfg);
XIP_SFlash_State_Restore(pFlashCfg, ioMode, offset);
}
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Read data from flash with lock
*
* @param addr: flash read start address
* @param dst: data pointer to store data read from flash
* @param len: data length to read
*
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Read(uint32_t addr, uint8_t *dst, int len)
{
__disable_irq();
XIP_SFlash_Opt_Enter();
XIP_SFlash_Read_Need_Lock(&flashCfg, flashCfg.ioMode & 0x0f, addr, dst, len);
XIP_SFlash_Opt_Exit();
__enable_irq();
return 0;
}
/****************************************************************************/ /**
* @brief Program flash one region with lock
*
* @param addr: Start address to be programed
* @param src: Data pointer to be programed
* @param len: Data length to be programed
*
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Write(uint32_t addr, uint8_t *src, int len)
{
__disable_irq();
XIP_SFlash_Opt_Enter();
XIP_SFlash_Write_Need_Lock(&flashCfg, flashCfg.ioMode & 0x0f, addr, src, len);
XIP_SFlash_Opt_Exit();
__enable_irq();
return 0;
}
/****************************************************************************/ /**
* @brief Erase flash one region with lock
*
* @param addr: Start address to be erased
* @param len: Data length to be erased
*
* @return 0
*
*******************************************************************************/
__WEAK
int ATTR_TCM_SECTION XIP_SFlash_Erase(uint32_t addr, int len)
{
__disable_irq();
XIP_SFlash_Opt_Enter();
XIP_SFlash_Erase_Need_Lock(&flashCfg, flashCfg.ioMode & 0x0f, addr, addr + len - 1);
XIP_SFlash_Opt_Exit();
__enable_irq();
return 0;
return stat;
}
/*@} end of group XIP_SFLASH_EXT_Public_Functions */