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[refactor][dma] refactor dma driver,add DMA_SI,DMA_DI and dma burst size config

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This commit is contained in:
jzlv 2021-11-10 17:42:04 +08:00
parent a31ce13293
commit 5d5c6a2f32
27 changed files with 1434 additions and 1087 deletions
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299
bsp/board/bl602/bl602_boot2/peripheral_config.h
View File

@ -41,32 +41,6 @@
#define BSP_USING_DMA0_CH7
/* PERIPHERAL CONFIG */
#if defined(BSP_USING_ADC0)
#ifndef ADC0_CONFIG
#define ADC0_CONFIG \
{ \
.clk_div = ADC_CLOCK_DIV_32, \
.vref = ADC_VREF_3P2V, \
.continuous_conv_mode = DISABLE, \
.differential_mode = DISABLE, \
.data_width = ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, \
.fifo_threshold = ADC_FIFO_THRESHOLD_1BYTE, \
.gain = ADC_GAIN_1 \
}
#endif
#endif
#if defined(BSP_USING_DAC0)
#ifndef DAC_CONFIG
#define DAC_CONFIG \
{ \
.clk = DAC_CLK_500KHZ, \
.pin.dac0 = GLB_GPIO_PIN_11, \
.pin.pin_num = 1, \
}
#endif
#endif
#if defined(BSP_USING_UART0)
#ifndef UART0_CONFIG
#define UART0_CONFIG \
@ -76,7 +50,7 @@
.databits = UART_DATA_LEN_8, \
.stopbits = UART_STOP_ONE, \
.parity = UART_PAR_NONE, \
.fifo_threshold = 16, \
.fifo_threshold = 16, \
}
#endif
#endif
@ -95,209 +69,162 @@
#endif
#endif
#if defined(BSP_USING_SPI0)
#ifndef SPI0_CONFIG
#define SPI0_CONFIG \
{ \
.id = 0, \
.clk = 18000000, \
.mode = SPI_MASTER_MODE, \
.direction = SPI_MSB_BYTE0_DIRECTION_FIRST, \
.clk_polaraity = SPI_POLARITY_LOW, \
.clk_phase = SPI_PHASE_1EDGE, \
.datasize = SPI_DATASIZE_8BIT, \
.fifo_threshold = 1, \
}
#endif
#endif
#if defined(BSP_USING_PWM_CH2)
#ifndef PWM_CH2_CONFIG
#define PWM_CH2_CONFIG \
{ \
.ch = 2, \
.frequency = 1000000, \
.dutycycle = 0, \
.it_pulse_count = 0, \
}
#endif
#endif
#if defined(BSP_USING_I2S0)
#ifndef I2S0_CONFIG
#define I2S0_CONFIG \
{ \
.id = 0, \
.iis_mode = I2S_MODE_MASTER, \
.interface_mode = I2S_MODE_LEFT, \
.sampl_freq_hz = 16 * 1000, \
.channel_num = I2S_FS_CHANNELS_NUM_MONO, \
.frame_size = I2S_FRAME_LEN_16, \
.data_size = I2S_DATA_LEN_16, \
.fifo_threshold = 8, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH0)
#ifndef DMA0_CH0_CONFIG
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH1)
#ifndef DMA0_CH1_CONFIG
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH2)
#ifndef DMA0_CH2_CONFIG
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH3)
#ifndef DMA0_CH3_CONFIG
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH4)
#ifndef DMA0_CH4_CONFIG
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH5)
#ifndef DMA0_CH5_CONFIG
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH6)
#ifndef DMA0_CH6_CONFIG
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH7)
#ifndef DMA0_CH7_CONFIG
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif
#if defined(BSP_USING_I2C0)
#ifndef I2C0_CONFIG
#define I2C0_CONFIG \
{ \
.id = 0, \
.mode = I2C_HW_MODE, \
.phase = 15, \
}
#endif
#endif
#if defined(BSP_USING_TIMER_CH0)
#ifndef TIMER_CH0_CONFIG
#define TIMER_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.cnt_mode = TIMER_CNT_PRELOAD, \
.pl_trig_src = TIMER_PL_TRIG_COMP0, \
}
#endif
#endif
#if defined(BSP_USING_TIMER_CH1)
#ifndef TIMER_CH1_CONFIG
#define TIMER_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.cnt_mode = TIMER_CNT_PRELOAD, \
.pl_trig_src = TIMER_PL_TRIG_COMP0, \
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 7, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif

297
bsp/board/bl602/bl602_iot/peripheral_config.h
View File

@ -40,32 +40,6 @@
#define BSP_USING_DMA0_CH7
/* PERIPHERAL CONFIG */
#if defined(BSP_USING_ADC0)
#ifndef ADC0_CONFIG
#define ADC0_CONFIG \
{ \
.clk_div = ADC_CLOCK_DIV_32, \
.vref = ADC_VREF_3P2V, \
.continuous_conv_mode = DISABLE, \
.differential_mode = DISABLE, \
.data_width = ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, \
.fifo_threshold = ADC_FIFO_THRESHOLD_1BYTE, \
.gain = ADC_GAIN_1 \
}
#endif
#endif
#if defined(BSP_USING_DAC0)
#ifndef DAC_CONFIG
#define DAC_CONFIG \
{ \
.clk = DAC_CLK_500KHZ, \
.pin.dac0 = GLB_GPIO_PIN_11, \
.pin.pin_num = 1, \
}
#endif
#endif
#if defined(BSP_USING_UART0)
#ifndef UART0_CONFIG
#define UART0_CONFIG \
@ -94,209 +68,162 @@
#endif
#endif
#if defined(BSP_USING_SPI0)
#ifndef SPI0_CONFIG
#define SPI0_CONFIG \
{ \
.id = 0, \
.clk = 18000000, \
.mode = SPI_MASTER_MODE, \
.direction = SPI_MSB_BYTE0_DIRECTION_FIRST, \
.clk_polaraity = SPI_POLARITY_LOW, \
.clk_phase = SPI_PHASE_1EDGE, \
.datasize = SPI_DATASIZE_8BIT, \
.fifo_threshold = 1, \
}
#endif
#endif
#if defined(BSP_USING_PWM_CH2)
#ifndef PWM_CH2_CONFIG
#define PWM_CH2_CONFIG \
{ \
.ch = 2, \
.frequency = 1000000, \
.dutycycle = 0, \
.it_pulse_count = 0, \
}
#endif
#endif
#if defined(BSP_USING_I2S0)
#ifndef I2S0_CONFIG
#define I2S0_CONFIG \
{ \
.id = 0, \
.iis_mode = I2S_MODE_MASTER, \
.interface_mode = I2S_MODE_LEFT, \
.sampl_freq_hz = 16 * 1000, \
.channel_num = I2S_FS_CHANNELS_NUM_MONO, \
.frame_size = I2S_FRAME_LEN_16, \
.data_size = I2S_DATA_LEN_16, \
.fifo_threshold = 8, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH0)
#ifndef DMA0_CH0_CONFIG
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH1)
#ifndef DMA0_CH1_CONFIG
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH2)
#ifndef DMA0_CH2_CONFIG
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH3)
#ifndef DMA0_CH3_CONFIG
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH4)
#ifndef DMA0_CH4_CONFIG
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH5)
#ifndef DMA0_CH5_CONFIG
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH6)
#ifndef DMA0_CH6_CONFIG
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH7)
#ifndef DMA0_CH7_CONFIG
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif
#if defined(BSP_USING_I2C0)
#ifndef I2C0_CONFIG
#define I2C0_CONFIG \
{ \
.id = 0, \
.mode = I2C_HW_MODE, \
.phase = 15, \
}
#endif
#endif
#if defined(BSP_USING_TIMER_CH0)
#ifndef TIMER_CH0_CONFIG
#define TIMER_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.cnt_mode = TIMER_CNT_PRELOAD, \
.pl_trig_src = TIMER_PL_TRIG_COMP0, \
}
#endif
#endif
#if defined(BSP_USING_TIMER_CH1)
#ifndef TIMER_CH1_CONFIG
#define TIMER_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.cnt_mode = TIMER_CNT_PRELOAD, \
.pl_trig_src = TIMER_PL_TRIG_COMP0, \
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 7, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif

202
bsp/board/bl702/bl702_boot2/peripheral_config.h
View File

@ -71,11 +71,11 @@
#if defined(BSP_USING_DAC0)
#ifndef DAC_CONFIG
#define DAC_CONFIG \
{ \
.clk = DAC_CLK_500KHZ, \
.pin.dac0 = GLB_GPIO_PIN_11, \
.pin.pin_num = 1, \
#define DAC_CONFIG \
{ \
.channels = DAC_CHANNEL_0, \
.sample_freq = DAC_SAMPLE_FREQ_500KHZ, \
.vref = DAC_VREF_INTERNAL, \
}
#endif
#endif
@ -198,128 +198,160 @@
#if defined(BSP_USING_DMA0_CH0)
#ifndef DMA0_CH0_CONFIG
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH1)
#ifndef DMA0_CH1_CONFIG
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH2)
#ifndef DMA0_CH2_CONFIG
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH3)
#ifndef DMA0_CH3_CONFIG
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH4)
#ifndef DMA0_CH4_CONFIG
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH5)
#ifndef DMA0_CH5_CONFIG
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH6)
#ifndef DMA0_CH6_CONFIG
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH7)
#ifndef DMA0_CH7_CONFIG
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 7, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif

204
bsp/board/bl702/bl702_iot/peripheral_config.h
View File

@ -76,11 +76,11 @@
#if defined(BSP_USING_DAC0)
#ifndef DAC_CONFIG
#define DAC_CONFIG \
{ \
.clk = DAC_CLK_500KHZ, \
.pin.dac0 = GLB_GPIO_PIN_11, \
.pin.pin_num = 1, \
#define DAC_CONFIG \
{ \
.channels = DAC_CHANNEL_0, \
.sample_freq = DAC_SAMPLE_FREQ_500KHZ, \
.vref = DAC_VREF_INTERNAL, \
}
#endif
#endif
@ -125,6 +125,8 @@
.clk_phase = SPI_PHASE_1EDGE, \
.datasize = SPI_DATASIZE_8BIT, \
.fifo_threshold = 1, \
.pin_swap_enable = 1, \
.delitch_cnt = 0, \
}
#endif
#endif
@ -217,128 +219,160 @@
#if defined(BSP_USING_DMA0_CH0)
#ifndef DMA0_CH0_CONFIG
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH1)
#ifndef DMA0_CH1_CONFIG
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH2)
#ifndef DMA0_CH2_CONFIG
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH3)
#ifndef DMA0_CH3_CONFIG
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH4)
#ifndef DMA0_CH4_CONFIG
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH5)
#ifndef DMA0_CH5_CONFIG
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH6)
#ifndef DMA0_CH6_CONFIG
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH7)
#ifndef DMA0_CH7_CONFIG
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 7, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 7, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif

203
bsp/board/bl702/bl706_avb/peripheral_config.h
View File

@ -76,11 +76,11 @@
#if defined(BSP_USING_DAC0)
#ifndef DAC_CONFIG
#define DAC_CONFIG \
{ \
.clk = DAC_CLK_500KHZ, \
.pin.dac0 = GLB_GPIO_PIN_11, \
.pin.pin_num = 1, \
#define DAC_CONFIG \
{ \
.channels = DAC_CHANNEL_0, \
.sample_freq = DAC_SAMPLE_FREQ_500KHZ, \
.vref = DAC_VREF_INTERNAL, \
}
#endif
#endif
@ -219,132 +219,163 @@
#if defined(BSP_USING_DMA0_CH0)
#ifndef DMA0_CH0_CONFIG
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH1)
#ifndef DMA0_CH1_CONFIG
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH2)
#ifndef DMA0_CH2_CONFIG
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH3)
#ifndef DMA0_CH3_CONFIG
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH4)
#ifndef DMA0_CH4_CONFIG
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH5)
#ifndef DMA0_CH5_CONFIG
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH6)
#ifndef DMA0_CH6_CONFIG
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH7)
#ifndef DMA0_CH7_CONFIG
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 7, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 7, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif
#if defined(BSP_USING_I2C0)
#ifndef I2C0_CONFIG
#define I2C0_CONFIG \

202
bsp/board/bl702/bl706_iot/peripheral_config.h
View File

@ -76,11 +76,11 @@
#if defined(BSP_USING_DAC0)
#ifndef DAC_CONFIG
#define DAC_CONFIG \
{ \
.clk = DAC_CLK_500KHZ, \
.pin.dac0 = GLB_GPIO_PIN_11, \
.pin.pin_num = 1, \
#define DAC_CONFIG \
{ \
.channels = DAC_CHANNEL_0, \
.sample_freq = DAC_SAMPLE_FREQ_500KHZ, \
.vref = DAC_VREF_INTERNAL, \
}
#endif
#endif
@ -219,128 +219,160 @@
#if defined(BSP_USING_DMA0_CH0)
#ifndef DMA0_CH0_CONFIG
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH1)
#ifndef DMA0_CH1_CONFIG
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH2)
#ifndef DMA0_CH2_CONFIG
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH3)
#ifndef DMA0_CH3_CONFIG
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH4)
#ifndef DMA0_CH4_CONFIG
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH5)
#ifndef DMA0_CH5_CONFIG
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH6)
#ifndef DMA0_CH6_CONFIG
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH7)
#ifndef DMA0_CH7_CONFIG
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 7, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 7, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif

202
bsp/board/bl702/bl706_lp/peripheral_config.h
View File

@ -57,11 +57,11 @@
#if defined(BSP_USING_DAC0)
#ifndef DAC_CONFIG
#define DAC_CONFIG \
{ \
.clk = DAC_CLK_500KHZ, \
.pin.dac0 = GLB_GPIO_PIN_11, \
.pin.pin_num = 1, \
#define DAC_CONFIG \
{ \
.channels = DAC_CHANNEL_0, \
.sample_freq = DAC_SAMPLE_FREQ_500KHZ, \
.vref = DAC_VREF_INTERNAL, \
}
#endif
#endif
@ -184,128 +184,160 @@
#if defined(BSP_USING_DMA0_CH0)
#ifndef DMA0_CH0_CONFIG
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
#define DMA0_CH0_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH1)
#ifndef DMA0_CH1_CONFIG
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH1_CONFIG \
{ \
.id = 0, \
.ch = 1, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_4BYTE, \
.dst_burst_size = DMA_BURST_4BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH2)
#ifndef DMA0_CH2_CONFIG
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH2_CONFIG \
{ \
.id = 0, \
.ch = 2, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_UART1_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH3)
#ifndef DMA0_CH3_CONFIG
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH3_CONFIG \
{ \
.id = 0, \
.ch = 3, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_SPI0_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH4)
#ifndef DMA0_CH4_CONFIG
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
#define DMA0_CH4_CONFIG \
{ \
.id = 0, \
.ch = 4, \
.direction = DMA_PERIPH_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_SPI0_RX, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_8BIT, \
.dst_width = DMA_TRANSFER_WIDTH_8BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH5)
#ifndef DMA0_CH5_CONFIG
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH5_CONFIG \
{ \
.id = 0, \
.ch = 5, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH6)
#ifndef DMA0_CH6_CONFIG
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
#define DMA0_CH6_CONFIG \
{ \
.id = 0, \
.ch = 6, \
.direction = DMA_MEMORY_TO_PERIPH, \
.transfer_mode = DMA_LLI_CYCLE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_I2S_TX, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_16BIT, \
.dst_width = DMA_TRANSFER_WIDTH_16BIT, \
}
#endif
#endif
#if defined(BSP_USING_DMA0_CH7)
#ifndef DMA0_CH7_CONFIG
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 0, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
#define DMA0_CH7_CONFIG \
{ \
.id = 0, \
.ch = 7, \
.direction = DMA_MEMORY_TO_MEMORY, \
.transfer_mode = DMA_LLI_ONCE_MODE, \
.src_req = DMA_REQUEST_NONE, \
.dst_req = DMA_REQUEST_NONE, \
.src_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE, \
.src_burst_size = DMA_BURST_1BYTE, \
.dst_burst_size = DMA_BURST_1BYTE, \
.src_width = DMA_TRANSFER_WIDTH_32BIT, \
.dst_width = DMA_TRANSFER_WIDTH_32BIT, \
}
#endif
#endif

82
drivers/bl602_driver/hal_drv/inc/hal_dma.h
View File

@ -27,10 +27,12 @@
#include "drv_device.h"
#include "bl602_config.h"
#define DMA_CHANNEL_GET_STATUS 0x10
#define DMA_CHANNEL_START 0x11
#define DMA_CHANNEL_STOP 0x12
#define DMA_CHANNEL_UPDATE 0x13
#define DMA_CHANNEL_GET_STATUS 0x10
#define DMA_CHANNEL_START 0x11
#define DMA_CHANNEL_STOP 0x12
#define DMA_CHANNEL_UPDATE 0x13
#define DEVICE_CTRL_DMA_CONFIG_SI 0x14
#define DEVICE_CTRL_DMA_CONFIG_DI 0x15
enum dma_index_type {
#ifdef BSP_USING_DMA0_CH0
@ -65,6 +67,21 @@ enum dma_index_type {
#define dma_channel_update(dev, list) device_control(dev, DMA_CHANNEL_UPDATE, list)
#define dma_channel_check_busy(dev) device_control(dev, DMA_CHANNEL_GET_STATUS, NULL)
#define DMA_LLI_ONCE_MODE 0
#define DMA_LLI_CYCLE_MODE 1
#define DMA_ADDR_INCREMENT_DISABLE 0 /*!< Addr increment mode disable */
#define DMA_ADDR_INCREMENT_ENABLE 1 /*!< Addr increment mode enable */
#define DMA_TRANSFER_WIDTH_8BIT 0
#define DMA_TRANSFER_WIDTH_16BIT 1
#define DMA_TRANSFER_WIDTH_32BIT 2
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88)
#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C)
#define DMA_ADDR_UART1_TDR (0x4000A100 + 0x88)
@ -76,25 +93,7 @@ enum dma_index_type {
#define DMA_ADDR_I2S_TDR (0x4000AA00 + 0x88)
#define DMA_ADDR_I2S_RDR (0x4000AA00 + 0x8C)
#define DMA_ADDR_ADC0_DR (0x40002000 + 0x04)
#define DMA_ADDR_ADC1_DR (0x40002000 + 0x04)
#define DMA_ADDR_DAC_TDR (0x40002048)
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @brief DMA peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE 1 /*!< Peripheral increment mode enable */
#define DMA_PINC_DISABLE 0 /*!< Peripheral increment mode disable */
/**
* @}
*/
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @brief DMA memory incremented mode
* @{
*/
#define DMA_MINC_ENABLE 1 /*!< Memory increment mode enable */
#define DMA_MINC_DISABLE 0 /*!< Memory increment mode disable */
#define DMA_ADDR_DAC_TDR (0x40002000 + 0X48)
#define DMA_REQUEST_NONE 0x00000000 /*!< DMA request peripheral:None */
#define DMA_REQUEST_UART0_RX 0x00000000 /*!< DMA request peripheral:UART0 RX */
@ -107,29 +106,17 @@ enum dma_index_type {
#define DMA_REQUEST_SPI0_TX 0x0000000B /*!< DMA request peripheral:SPI TX */
#define DMA_REQUEST_I2S_RX 0x00000014 /*!< DMA request peripheral:I2S RX */
#define DMA_REQUEST_I2S_TX 0x00000015 /*!< DMA request peripheral:I2S TX */
#define DMA_REQUEST_ADC0 0x00000016 /*!< DMA request peripheral:GPADC0 */
#define DMA_REQUEST_DAC0 0x00000017 /*!< DMA request peripheral:GPADC1 */
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_TRANSFER_WIDTH_8BIT 0
#define DMA_TRANSFER_WIDTH_16BIT 1
#define DMA_TRANSFER_WIDTH_32BIT 2
#define DMA_LLI_ONCE_MODE 0
#define DMA_LLI_CYCLE_MODE 1
#define DMA_REQUEST_ADC0 0x00000016 /*!< DMA request peripheral:ADC0 */
#define DMA_REQUEST_DAC0 0x00000017 /*!< DMA request peripheral:DAC0 */
/**
* @brief DMA transfer direction type definition
*/
typedef enum {
DMA_MEMORY_TO_MEMORY = 0, /*!< DMA transfer tyep:memory to memory */
DMA_MEMORY_TO_PERIPH, /*!< DMA transfer tyep:memory to peripheral */
DMA_PERIPH_TO_MEMORY, /*!< DMA transfer tyep:peripheral to memory */
DMA_PERIPH_TO_PERIPH, /*!< DMA transfer tyep:peripheral to peripheral */
DMA_MEMORY_TO_MEMORY = 0, /*!< DMA transfer type:memory to memory */
DMA_MEMORY_TO_PERIPH, /*!< DMA transfer type:memory to peripheral */
DMA_PERIPH_TO_MEMORY, /*!< DMA transfer type:peripheral to memory */
DMA_PERIPH_TO_PERIPH, /*!< DMA transfer type:peripheral to peripheral */
} dma_transfer_dir_type;
typedef union {
@ -161,21 +148,16 @@ typedef struct
dma_control_data_t cfg;
} dma_lli_ctrl_t;
typedef struct
{
uint8_t direction;
uint32_t src_req;
uint32_t dst_req;
} dma_ctrl_param_t;
typedef struct dma_device {
struct device parent;
uint8_t id;
uint8_t ch;
uint8_t direction;
uint8_t transfer_mode;
uint8_t direction;
uint32_t src_req;
uint32_t dst_req;
uint8_t src_addr_inc;
uint8_t dst_addr_inc;
uint8_t src_burst_size;
uint8_t dst_burst_size;
uint8_t src_width;
@ -185,7 +167,7 @@ typedef struct dma_device {
#define DMA_DEV(dev) ((dma_device_t *)dev)
int dma_register(enum dma_index_type, const char *name);
int dma_register(enum dma_index_type index, const char *name);
int dma_allocate_register(const char *name);
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size);

135
drivers/bl602_driver/hal_drv/src/hal_dma.c
View File

@ -23,11 +23,25 @@
#include "hal_dma.h"
#include "bl602_dma.h"
dma_control_data_t dma_ctrl_cfg;
#define DMA_CHANNEL_BASE(id_base, ch) ((id_base) + DMA_CHANNEL_OFFSET + (ch)*0x100)
void DMA0_IRQ(void);
static const uint32_t dma_channel_base[][8] = {
{
DMA_CHANNEL_BASE(DMA_BASE, 0),
DMA_CHANNEL_BASE(DMA_BASE, 1),
DMA_CHANNEL_BASE(DMA_BASE, 2),
DMA_CHANNEL_BASE(DMA_BASE, 3),
DMA_CHANNEL_BASE(DMA_BASE, 4),
DMA_CHANNEL_BASE(DMA_BASE, 5),
DMA_CHANNEL_BASE(DMA_BASE, 6),
DMA_CHANNEL_BASE(DMA_BASE, 7),
}
dma_device_t dmax_device[DMA_MAX_INDEX] = {
};
static void DMA0_IRQ(void);
static dma_device_t dmax_device[DMA_MAX_INDEX] = {
#ifdef BSP_USING_DMA0_CH0
DMA0_CH0_CONFIG,
#endif
@ -63,8 +77,7 @@ dma_device_t dmax_device[DMA_MAX_INDEX] = {
int dma_open(struct device *dev, uint16_t oflag)
{
dma_device_t *dma_device = (dma_device_t *)dev;
DMA_LLI_Cfg_Type lliCfg = { 0 };
DMA_Channel_Cfg_Type chCfg = { 0 };
/* Disable all interrupt */
DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK);
@ -75,20 +88,23 @@ int dma_open(struct device *dev, uint16_t oflag)
DMA_Channel_Disable(dma_device->ch);
lliCfg.dir = dma_device->direction;
lliCfg.srcPeriph = dma_device->src_req;
lliCfg.dstPeriph = dma_device->dst_req;
DMA_LLI_Init(dma_device->ch, &lliCfg);
dma_ctrl_cfg.bits.fix_cnt = 0;
dma_ctrl_cfg.bits.dst_min_mode = 0;
dma_ctrl_cfg.bits.dst_add_mode = 0;
chCfg.ch = dma_device->ch;
chCfg.dir = dma_device->direction;
chCfg.srcPeriph = dma_device->src_req;
chCfg.dstPeriph = dma_device->dst_req;
chCfg.srcAddrInc = dma_device->src_addr_inc;
chCfg.destAddrInc = dma_device->dst_addr_inc;
chCfg.srcBurstSzie = dma_device->src_burst_size;
chCfg.dstBurstSzie = dma_device->dst_burst_size;
chCfg.srcTransfWidth = dma_device->src_width;
chCfg.dstTransfWidth = dma_device->dst_width;
DMA_Channel_Init(&chCfg);
DMA_Enable();
Interrupt_Handler_Register(DMA_ALL_IRQn, DMA0_IRQ);
/* Enable uart interrupt*/
CPU_Interrupt_Enable(DMA_ALL_IRQn);
return 0;
}
/**
@ -104,56 +120,53 @@ int dma_control(struct device *dev, int cmd, void *args)
dma_device_t *dma_device = (dma_device_t *)dev;
switch (cmd) {
case DEVICE_CTRL_SET_INT /* constant-expression */:
case DEVICE_CTRL_SET_INT:
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK);
/* Enable uart interrupt*/
CPU_Interrupt_Enable(DMA_ALL_IRQn);
break;
case DEVICE_CTRL_CLR_INT /* constant-expression */:
case DEVICE_CTRL_CLR_INT:
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK);
/* Enable uart interrupt*/
CPU_Interrupt_Disable(DMA_ALL_IRQn);
break;
case DEVICE_CTRL_GET_INT /* constant-expression */:
/* code */
case DEVICE_CTRL_GET_INT:
break;
case DEVICE_CTRL_CONFIG /* constant-expression */: {
dma_ctrl_param_t *cfg = (dma_ctrl_param_t *)args;
DMA_LLI_Cfg_Type lliCfg = { 0 };
lliCfg.dir = cfg->direction;
lliCfg.srcPeriph = cfg->src_req;
lliCfg.dstPeriph = cfg->dst_req;
DMA_LLI_Init(dma_device->ch, &lliCfg);
case DEVICE_CTRL_CONFIG:
break;
}
case DMA_CHANNEL_UPDATE:
DMA_LLI_Update(dma_device->ch, (uint32_t)args);
break;
case DMA_CHANNEL_GET_STATUS /* constant-expression */:
case DMA_CHANNEL_GET_STATUS:
return DMA_Channel_Is_Busy(dma_device->ch);
case DMA_CHANNEL_START /* constant-expression */:
case DMA_CHANNEL_START:
DMA_Channel_Enable(dma_device->ch);
break;
case DMA_CHANNEL_STOP /* constant-expression */:
case DMA_CHANNEL_STOP:
DMA_Channel_Disable(dma_device->ch);
break;
case DEVICE_CTRL_DMA_CONFIG_SI: {
uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, ((uint32_t)args) & 0x01);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal);
} break;
case DEVICE_CTRL_DMA_CONFIG_DI: {
uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, ((uint32_t)args) & 0x01);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal);
} break;
default:
break;
}
@ -168,7 +181,11 @@ int dma_control(struct device *dev, int cmd, void *args)
*/
int dma_close(struct device *dev)
{
DMA_Disable();
dma_device_t *dma_device = (dma_device_t *)dev;
DMA_Channel_Cfg_Type chCfg = { 0 };
DMA_Channel_Disable(dma_device->ch);
DMA_Channel_Init(&chCfg);
return 0;
}
@ -188,7 +205,6 @@ int dma_register(enum dma_index_type index, const char *name)
// dev->write = dma_write;
// dev->read = dma_read;
dev->status = DEVICE_UNREGISTER;
dev->type = DEVICE_CLASS_DMA;
dev->handle = NULL;
@ -268,6 +284,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
uint32_t remain_len;
uint32_t actual_transfer_len = 0;
uint32_t actual_transfer_offset = 0;
dma_control_data_t dma_ctrl_cfg;
dma_device_t *dma_device = (dma_device_t *)dev;
@ -277,34 +294,6 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
return 0;
}
switch (dma_device->direction) {
case DMA_MEMORY_TO_MEMORY:
dma_ctrl_cfg.bits.SI = 1;
dma_ctrl_cfg.bits.DI = 1;
break;
case DMA_MEMORY_TO_PERIPH:
dma_ctrl_cfg.bits.SI = 1;
dma_ctrl_cfg.bits.DI = 0;
break;
case DMA_PERIPH_TO_MEMORY:
dma_ctrl_cfg.bits.SI = 0;
dma_ctrl_cfg.bits.DI = 1;
break;
case DMA_PERIPH_TO_PERIPH:
dma_ctrl_cfg.bits.SI = 0;
dma_ctrl_cfg.bits.DI = 0;
break;
default:
return -3;
break;
}
dma_ctrl_cfg.bits.SBSize = dma_device->src_burst_size;
dma_ctrl_cfg.bits.DBSize = dma_device->dst_burst_size;
dma_ctrl_cfg.bits.SWidth = dma_device->src_width;
dma_ctrl_cfg.bits.DWidth = dma_device->dst_width;
switch (dma_device->src_width) {
case DMA_TRANSFER_WIDTH_8BIT:
actual_transfer_offset = 4095;
@ -331,6 +320,8 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
break;
}
dma_ctrl_cfg = (dma_control_data_t)(BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL));
malloc_count = actual_transfer_len / 4095;
remain_len = actual_transfer_len % 4095;
@ -380,8 +371,10 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
memcpy(&dma_device->lli_cfg[i].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t));
}
DMA_LLI_Update(dma_device->ch, (uint32_t)dma_device->lli_cfg);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_SRCADDR, dma_device->lli_cfg[0].src_addr);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_DSTADDR, dma_device->lli_cfg[0].dst_addr);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_LLI, dma_device->lli_cfg[0].nextlli);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, dma_device->lli_cfg[0].cfg.WORD);
} else {
return -2;
}
@ -402,7 +395,7 @@ void dma_isr(dma_device_t *handle)
if (handle->id == 0) {
uint32_t DMAChs = DMA_BASE;
for (uint8_t i = 0; i < DMA_CH_MAX; i++) {
for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) {
tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS);
if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle[i].ch)) != 0) {
@ -419,7 +412,7 @@ void dma_isr(dma_device_t *handle)
}
}
for (uint8_t i = 0; i < DMA_CH_MAX; i++) {
for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) {
tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS);
if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle[i].ch)) != 0) {
@ -442,7 +435,7 @@ void dma_isr(dma_device_t *handle)
* @brief
*
*/
void DMA0_IRQ(void)
static void DMA0_IRQ(void)
{
dma_isr(&dmax_device[0]);
}

80
drivers/bl702_driver/hal_drv/inc/hal_dma.h
View File

@ -24,17 +24,19 @@
#define __HAL_DMA__H__
#ifdef __cplusplus
extern "C"{
extern "C" {
#endif
#include "hal_common.h"
#include "drv_device.h"
#include "bl702_config.h"
#define DMA_CHANNEL_GET_STATUS 0x10
#define DMA_CHANNEL_START 0x11
#define DMA_CHANNEL_STOP 0x12
#define DMA_CHANNEL_UPDATE 0x13
#define DMA_CHANNEL_GET_STATUS 0x10
#define DMA_CHANNEL_START 0x11
#define DMA_CHANNEL_STOP 0x12
#define DMA_CHANNEL_UPDATE 0x13
#define DEVICE_CTRL_DMA_CONFIG_SI 0x14
#define DEVICE_CTRL_DMA_CONFIG_DI 0x15
enum dma_index_type {
#ifdef BSP_USING_DMA0_CH0
@ -69,6 +71,21 @@ enum dma_index_type {
#define dma_channel_update(dev, list) device_control(dev, DMA_CHANNEL_UPDATE, list)
#define dma_channel_check_busy(dev) device_control(dev, DMA_CHANNEL_GET_STATUS, NULL)
#define DMA_LLI_ONCE_MODE 0
#define DMA_LLI_CYCLE_MODE 1
#define DMA_ADDR_INCREMENT_DISABLE 0 /*!< Addr increment mode disable */
#define DMA_ADDR_INCREMENT_ENABLE 1 /*!< Addr increment mode enable */
#define DMA_TRANSFER_WIDTH_8BIT 0
#define DMA_TRANSFER_WIDTH_16BIT 1
#define DMA_TRANSFER_WIDTH_32BIT 2
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88)
#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C)
#define DMA_ADDR_UART1_TDR (0x4000A100 + 0x88)
@ -80,25 +97,7 @@ enum dma_index_type {
#define DMA_ADDR_I2S_TDR (0x4000AA00 + 0x88)
#define DMA_ADDR_I2S_RDR (0x4000AA00 + 0x8C)
#define DMA_ADDR_ADC0_DR (0x40002000 + 0x04)
#define DMA_ADDR_ADC1_DR (0x40002000 + 0x04)
#define DMA_ADDR_DAC_TDR (0x40002048)
/** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
* @brief DMA peripheral incremented mode
* @{
*/
#define DMA_PINC_ENABLE 1 /*!< Peripheral increment mode enable */
#define DMA_PINC_DISABLE 0 /*!< Peripheral increment mode disable */
/**
* @}
*/
/** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
* @brief DMA memory incremented mode
* @{
*/
#define DMA_MINC_ENABLE 1 /*!< Memory increment mode enable */
#define DMA_MINC_DISABLE 0 /*!< Memory increment mode disable */
#define DMA_ADDR_DAC_TDR (0x40002000 + 0X48)
#define DMA_REQUEST_NONE 0x00000000 /*!< DMA request peripheral:None */
#define DMA_REQUEST_UART0_RX 0x00000000 /*!< DMA request peripheral:UART0 RX */
@ -122,26 +121,14 @@ enum dma_index_type {
#define DMA_REQUEST_USB_EP6 0x0000001E /*!< DMA request peripheral:USB EP6*/
#define DMA_REQUEST_USB_EP7 0x0000001F /*!< DMA request peripheral:USB EP7 */
#define DMA_BURST_1BYTE 0
#define DMA_BURST_4BYTE 1
#define DMA_BURST_8BYTE 2
#define DMA_BURST_16BYTE 3
#define DMA_TRANSFER_WIDTH_8BIT 0
#define DMA_TRANSFER_WIDTH_16BIT 1
#define DMA_TRANSFER_WIDTH_32BIT 2
#define DMA_LLI_ONCE_MODE 0
#define DMA_LLI_CYCLE_MODE 1
/**
* @brief DMA transfer direction type definition
*/
typedef enum {
DMA_MEMORY_TO_MEMORY = 0, /*!< DMA transfer tyep:memory to memory */
DMA_MEMORY_TO_PERIPH, /*!< DMA transfer tyep:memory to peripheral */
DMA_PERIPH_TO_MEMORY, /*!< DMA transfer tyep:peripheral to memory */
DMA_PERIPH_TO_PERIPH, /*!< DMA transfer tyep:peripheral to peripheral */
DMA_MEMORY_TO_MEMORY = 0, /*!< DMA transfer type:memory to memory */
DMA_MEMORY_TO_PERIPH, /*!< DMA transfer type:memory to peripheral */
DMA_PERIPH_TO_MEMORY, /*!< DMA transfer type:peripheral to memory */
DMA_PERIPH_TO_PERIPH, /*!< DMA transfer type:peripheral to peripheral */
} dma_transfer_dir_type;
typedef union {
@ -173,21 +160,16 @@ typedef struct
dma_control_data_t cfg;
} dma_lli_ctrl_t;
typedef struct
{
uint8_t direction;
uint32_t src_req;
uint32_t dst_req;
} dma_ctrl_param_t;
typedef struct dma_device {
struct device parent;
uint8_t id;
uint8_t ch;
uint8_t direction;
uint8_t transfer_mode;
uint8_t direction;
uint32_t src_req;
uint32_t dst_req;
uint8_t src_addr_inc;
uint8_t dst_addr_inc;
uint8_t src_burst_size;
uint8_t dst_burst_size;
uint8_t src_width;
@ -200,7 +182,9 @@ typedef struct dma_device {
int dma_register(enum dma_index_type index, const char *name);
int dma_allocate_register(const char *name);
int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size);
#ifdef __cplusplus
}
#endif
#endif

118
drivers/bl702_driver/hal_drv/src/hal_dma.c
View File

@ -23,7 +23,21 @@
#include "hal_dma.h"
#include "bl702_dma.h"
static dma_control_data_t dma_ctrl_cfg;
#define DMA_CHANNEL_BASE(id_base, ch) ((id_base) + DMA_CHANNEL_OFFSET + (ch)*0x100)
static const uint32_t dma_channel_base[][8] = {
{
DMA_CHANNEL_BASE(DMA_BASE, 0),
DMA_CHANNEL_BASE(DMA_BASE, 1),
DMA_CHANNEL_BASE(DMA_BASE, 2),
DMA_CHANNEL_BASE(DMA_BASE, 3),
DMA_CHANNEL_BASE(DMA_BASE, 4),
DMA_CHANNEL_BASE(DMA_BASE, 5),
DMA_CHANNEL_BASE(DMA_BASE, 6),
DMA_CHANNEL_BASE(DMA_BASE, 7),
}
};
static void DMA0_IRQ(void);
@ -63,8 +77,7 @@ static dma_device_t dmax_device[DMA_MAX_INDEX] = {
int dma_open(struct device *dev, uint16_t oflag)
{
dma_device_t *dma_device = (dma_device_t *)dev;
DMA_LLI_Cfg_Type lliCfg = { 0 };
DMA_Channel_Cfg_Type chCfg = { 0 };
/* Disable all interrupt */
DMA_IntMask(dma_device->ch, DMA_INT_ALL, MASK);
@ -75,15 +88,17 @@ int dma_open(struct device *dev, uint16_t oflag)
DMA_Channel_Disable(dma_device->ch);
lliCfg.dir = dma_device->direction;
lliCfg.srcPeriph = dma_device->src_req;
lliCfg.dstPeriph = dma_device->dst_req;
DMA_LLI_Init(dma_device->ch, &lliCfg);
dma_ctrl_cfg.bits.fix_cnt = 0;
dma_ctrl_cfg.bits.dst_min_mode = 0;
dma_ctrl_cfg.bits.dst_add_mode = 0;
chCfg.ch = dma_device->ch;
chCfg.dir = dma_device->direction;
chCfg.srcPeriph = dma_device->src_req;
chCfg.dstPeriph = dma_device->dst_req;
chCfg.srcAddrInc = dma_device->src_addr_inc;
chCfg.destAddrInc = dma_device->dst_addr_inc;
chCfg.srcBurstSzie = dma_device->src_burst_size;
chCfg.dstBurstSzie = dma_device->dst_burst_size;
chCfg.srcTransfWidth = dma_device->src_width;
chCfg.dstTransfWidth = dma_device->dst_width;
DMA_Channel_Init(&chCfg);
DMA_Enable();
@ -105,52 +120,52 @@ int dma_control(struct device *dev, int cmd, void *args)
dma_device_t *dma_device = (dma_device_t *)dev;
switch (cmd) {
case DEVICE_CTRL_SET_INT /* constant-expression */:
case DEVICE_CTRL_SET_INT:
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, UNMASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, UNMASK);
break;
case DEVICE_CTRL_CLR_INT /* constant-expression */:
case DEVICE_CTRL_CLR_INT:
/* Dma interrupt configuration */
DMA_IntMask(dma_device->ch, DMA_INT_TCOMPLETED, MASK);
DMA_IntMask(dma_device->ch, DMA_INT_ERR, MASK);
break;
case DEVICE_CTRL_GET_INT /* constant-expression */:
/* code */
case DEVICE_CTRL_GET_INT:
break;
case DEVICE_CTRL_CONFIG /* constant-expression */: {
dma_ctrl_param_t *cfg = (dma_ctrl_param_t *)args;
DMA_LLI_Cfg_Type lliCfg = { 0 };
lliCfg.dir = cfg->direction;
lliCfg.srcPeriph = cfg->src_req;
lliCfg.dstPeriph = cfg->dst_req;
DMA_LLI_Init(dma_device->ch, &lliCfg);
case DEVICE_CTRL_CONFIG:
break;
}
case DMA_CHANNEL_UPDATE:
DMA_LLI_Update(dma_device->ch, (uint32_t)args);
break;
case DMA_CHANNEL_GET_STATUS /* constant-expression */:
case DMA_CHANNEL_GET_STATUS:
return DMA_Channel_Is_Busy(dma_device->ch);
case DMA_CHANNEL_START /* constant-expression */:
case DMA_CHANNEL_START:
DMA_Channel_Enable(dma_device->ch);
break;
case DMA_CHANNEL_STOP /* constant-expression */:
case DMA_CHANNEL_STOP:
DMA_Channel_Disable(dma_device->ch);
break;
case DEVICE_CTRL_DMA_CONFIG_SI: {
uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, ((uint32_t)args) & 0x01);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal);
} break;
case DEVICE_CTRL_DMA_CONFIG_DI: {
uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, ((uint32_t)args) & 0x01);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal);
} break;
default:
break;
}
@ -165,7 +180,11 @@ int dma_control(struct device *dev, int cmd, void *args)
*/
int dma_close(struct device *dev)
{
DMA_Disable();
dma_device_t *dma_device = (dma_device_t *)dev;
DMA_Channel_Cfg_Type chCfg = { 0 };
DMA_Channel_Disable(dma_device->ch);
DMA_Channel_Init(&chCfg);
return 0;
}
@ -265,6 +284,7 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
uint32_t remain_len;
uint32_t actual_transfer_len = 0;
uint32_t actual_transfer_offset = 0;
dma_control_data_t dma_ctrl_cfg;
dma_device_t *dma_device = (dma_device_t *)dev;
@ -274,34 +294,6 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
return 0;
}
switch (dma_device->direction) {
case DMA_MEMORY_TO_MEMORY:
dma_ctrl_cfg.bits.SI = 1;
dma_ctrl_cfg.bits.DI = 1;
break;
case DMA_MEMORY_TO_PERIPH:
dma_ctrl_cfg.bits.SI = 1;
dma_ctrl_cfg.bits.DI = 0;
break;
case DMA_PERIPH_TO_MEMORY:
dma_ctrl_cfg.bits.SI = 0;
dma_ctrl_cfg.bits.DI = 1;
break;
case DMA_PERIPH_TO_PERIPH:
dma_ctrl_cfg.bits.SI = 0;
dma_ctrl_cfg.bits.DI = 0;
break;
default:
return -3;
break;
}
dma_ctrl_cfg.bits.SBSize = dma_device->src_burst_size;
dma_ctrl_cfg.bits.DBSize = dma_device->dst_burst_size;
dma_ctrl_cfg.bits.SWidth = dma_device->src_width;
dma_ctrl_cfg.bits.DWidth = dma_device->dst_width;
switch (dma_device->src_width) {
case DMA_TRANSFER_WIDTH_8BIT:
actual_transfer_offset = 4095;
@ -328,6 +320,8 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
break;
}
dma_ctrl_cfg = (dma_control_data_t)(BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL));
malloc_count = actual_transfer_len / 4095;
remain_len = actual_transfer_len % 4095;
@ -377,8 +371,10 @@ int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_
memcpy(&dma_device->lli_cfg[i].cfg, &dma_ctrl_cfg, sizeof(dma_control_data_t));
}
DMA_LLI_Update(dma_device->ch, (uint32_t)dma_device->lli_cfg);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_SRCADDR, dma_device->lli_cfg[0].src_addr);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_DSTADDR, dma_device->lli_cfg[0].dst_addr);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_LLI, dma_device->lli_cfg[0].nextlli);
BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, dma_device->lli_cfg[0].cfg.WORD);
} else {
return -2;
}

8
examples/audio_cube/data_protocol.c
View File

@ -360,6 +360,10 @@ uint8_t isp_uart_init(isp_obj_t *isp_obj)
DMA_DEV(dma_ch0)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch0)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch0)->dst_req = DMA_REQUEST_UART0_TX;
DMA_DEV(dma_ch0)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch0)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch0)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch0)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch0)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch0)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch0, 0);
@ -378,6 +382,10 @@ uint8_t isp_uart_init(isp_obj_t *isp_obj)
// DMA_DEV(dma_ch1)->transfer_mode = DMA_LLI_ONCE_MODE;
// DMA_DEV(dma_ch1)->src_req = DMA_REQUEST_UART0_RX;
// DMA_DEV(dma_ch1)->dst_req = DMA_REQUEST_NONE;
// DMA_DEV(dma_ch1)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
// DMA_DEV(dma_ch1)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
// DMA_DEV(dma_ch1)->src_burst_size = DMA_BURST_1BYTE;
// DMA_DEV(dma_ch1)->dst_burst_size = DMA_BURST_1BYTE;
// DMA_DEV(dma_ch1)->src_width = DMA_TRANSFER_WIDTH_8BIT;
// DMA_DEV(dma_ch1)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
// device_open(dma_ch1, 0);

10
examples/audio_cube/wav_play_from_isp.c
View File

@ -219,9 +219,12 @@ static int isp_wav_play_init(struct audio_dev *audio_dev, uint8_t mode, uint8_t
DMA_DEV(dma_ch2)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch2)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_I2S_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
switch (I2S_DEV(audio_dev->device)->data_size * I2S_DEV(audio_dev->device)->channel_num) {
case 1:
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
@ -336,9 +339,12 @@ record_conf:
DMA_DEV(dma_ch3)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch3)->src_req = DMA_REQUEST_I2S_RX;
DMA_DEV(dma_ch3)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch3)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
switch (I2S_DEV(audio_dev->device)->data_size * I2S_DEV(audio_dev->device)->channel_num) {
case 1:
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_8BIT;

8
examples/audiocube_sph0645/data_protocol.c
View File

@ -357,6 +357,10 @@ uint8_t isp_uart_init(isp_obj_t *isp_obj)
DMA_DEV(dma_ch0)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch0)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch0)->dst_req = DMA_REQUEST_UART0_TX;
DMA_DEV(dma_ch0)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch0)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch0)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch0)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch0)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch0)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch0, 0);
@ -375,6 +379,10 @@ uint8_t isp_uart_init(isp_obj_t *isp_obj)
// DMA_DEV(dma_ch1)->transfer_mode = DMA_LLI_ONCE_MODE;
// DMA_DEV(dma_ch1)->src_req = DMA_REQUEST_UART0_RX;
// DMA_DEV(dma_ch1)->dst_req = DMA_REQUEST_NONE;
// DMA_DEV(dma_ch1)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
// DMA_DEV(dma_ch1)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
// DMA_DEV(dma_ch1)->src_burst_size = DMA_BURST_1BYTE;
// DMA_DEV(dma_ch1)->dst_burst_size = DMA_BURST_1BYTE;
// DMA_DEV(dma_ch1)->src_width = DMA_TRANSFER_WIDTH_8BIT;
// DMA_DEV(dma_ch1)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
// device_open(dma_ch1, 0);

12
examples/audiocube_sph0645/wav_play_from_isp.c
View File

@ -176,7 +176,7 @@ static int isp_wav_play_init(struct audio_dev *audio_dev, uint8_t mode, uint8_t
if ((audio_dev->device) && dma_ch2) {
/* I2S Config */
I2S_DEV(audio_dev->device)->interface_mode = I2S_MODE_LEFT;
I2S_DEV(audio_dev->device)->interface_mode = I2S_MODE_STD;
I2S_DEV(audio_dev->device)->sampl_freq_hz = audio_dev->wav_information->chunk_format.sample_rate;
I2S_DEV(audio_dev->device)->channel_num = audio_dev->wav_information->chunk_format.num_of_channels;
uint8_t pcm_w = audio_dev->wav_information->chunk_format.bits_per_sample / 8;
@ -217,9 +217,12 @@ static int isp_wav_play_init(struct audio_dev *audio_dev, uint8_t mode, uint8_t
DMA_DEV(dma_ch2)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch2)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_I2S_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
switch (I2S_DEV(audio_dev->device)->data_size * I2S_DEV(audio_dev->device)->channel_num) {
case 1:
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
@ -326,9 +329,12 @@ record_conf:
DMA_DEV(dma_ch3)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch3)->src_req = DMA_REQUEST_I2S_RX;
DMA_DEV(dma_ch3)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch3)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
switch (I2S_DEV(audio_dev->device)->data_size * I2S_DEV(audio_dev->device)->channel_num) {
case 1:
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_8BIT;

3
examples/camera/camera_interleave_pbuf/main.c
View File

@ -181,8 +181,6 @@ int ATTR_TCM_SECTION main(void)
}
// MSG("dma open \r\n");
//CAM_HW_Mode_Wrap(DISABLE);
cam_clk_out();
if (SUCCESS != image_sensor_init(DISABLE, &camera_cfg, &mjpeg_cfg)) {
@ -199,6 +197,7 @@ int ATTR_TCM_SECTION main(void)
cfg.y1 = CAMERA_RESOLUTION_Y;
struct device *cam0 = device_find("camera0");
device_control(cam0, DEVICE_CTRL_CAM_FRAME_WRAP, (void *)0);
device_control(cam0, DEVICE_CTRL_CAM_FRAME_CUT, &cfg);
device_set_callback(cam0, cam_irq_callback);
device_control(cam0, DEVICE_CTRL_SET_INT, (void *)CAM_FRAME_IT);

14
examples/camera/camera_lcd/CMakeLists.txt
View File

@ -1,9 +1,13 @@
set(BSP_COMMON_DIR ${CMAKE_SOURCE_DIR}/bsp/bsp_common)
set(LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/bl706_camera_psram.ld)
set(TARGET_REQUIRED_PRIVATE_INCLUDE ${BSP_COMMON_DIR}/psram ${BSP_COMMON_DIR}/image_sensor
${BSP_COMMON_DIR}/il9341)
set(TARGET_REQUIRED_SRCS ${BSP_COMMON_DIR}/psram/bsp_sf_psram.c
${BSP_COMMON_DIR}/image_sensor/bsp_image_sensor.c
${BSP_COMMON_DIR}/il9341/bsp_il9341.c)
set(TARGET_REQUIRED_PRIVATE_INCLUDE ${BSP_COMMON_DIR}/psram ${BSP_COMMON_DIR}/image_sensor
# ${BSP_COMMON_DIR}/il9341
${BSP_COMMON_DIR}/mcu_lcd)
set(TARGET_REQUIRED_SRCS ${BSP_COMMON_DIR}/psram/bsp_sf_psram.c
${BSP_COMMON_DIR}/image_sensor/bsp_image_sensor.c
# ${BSP_COMMON_DIR}/il9341/bsp_il9341.c
${BSP_COMMON_DIR}/mcu_lcd/mcu_lcd.c
${BSP_COMMON_DIR}/mcu_lcd/ili9341.c
${BSP_COMMON_DIR}/mcu_lcd/font.c)
set(mains main.c)
generate_bin()

53
examples/camera/camera_lcd/main.c
View File

@ -27,12 +27,13 @@
#include "hal_spi.h"
#include "hal_gpio.h"
#include "hal_dma.h"
#include "bsp_il9341.h"
// #include "bsp_il9341.h"
#include "mcu_lcd.h"
#include "picture.c"
#define CAMERA_RESOLUTION_X (240)
#define CAMERA_RESOLUTION_Y (320)
#define CAMERA_RESOLUTION_X (128)
#define CAMERA_RESOLUTION_Y (128)
#define YUV422_FRAME_SIZE (CAMERA_RESOLUTION_X * CAMERA_RESOLUTION_Y * 2)
#define YUV420_FRAME_SIZE (CAMERA_RESOLUTION_X * CAMERA_RESOLUTION_Y * 2 * 3 / 4)
@ -44,11 +45,11 @@
#define CAMERA_WRITE_ADDR (0x26000000)
#define CAMERA_BUFFER_SIZE (CAMERA_FRAME_SIZE)
#define CAMERA_WRITE_ADDR1 (0x26000000 + CAMERA_BUFFER_SIZE)
#define CAMERA_BUFFER_SIZE1 (0x200000)
#define CAMERA_BUFFER_SIZE1 (CAMERA_FRAME_SIZE)
#define YUV_USE (1)
// #define TEST_TIM
#define TEST_TIM
/* Turn 24-bit RGB color to 16-bit */
#define RGB(r, g, b) (((r >> 3) << 3 | (g >> 5) | (g >> 2) << 13 | (b >> 3) << 8) & 0xffff)
@ -234,13 +235,21 @@ int main(void)
#endif
uint32_t length;
#ifdef TEST_TIM
uint8_t str[64];
uint32_t timer_start = 0;
uint32_t timer_end = 0;
uint32_t time = 0;
#endif
bflb_platform_init(0);
LCD_Init();
LCD_Clear(0);
// LCD_Init();
// LCD_Clear(0);
if (lcd_init()) {
MSG("lcd err \r\n");
}
lcd_set_dir(0, 0);
lcd_clear(0xFFFF);
lcd_auto_swap_set(0);
bsp_sf_psram_init(1);
@ -253,16 +262,16 @@ int main(void)
}
}
cam_frame_area_t cfg;
cfg.x0 = 200;
cfg.x1 = CAMERA_RESOLUTION_X + 200;
cfg.y0 = 80;
cfg.y1 = CAMERA_RESOLUTION_Y + 80;
cfg.x0 = 96;
cfg.x1 = CAMERA_RESOLUTION_X + 96;
cfg.y0 = 56;
cfg.y1 = CAMERA_RESOLUTION_Y + 56;
struct device *cam0 = device_find("camera0");
device_control(cam0, DEVICE_CTRL_CAM_FRAME_CUT, &cfg);
device_control(cam0, DEVICE_CTRL_RESUME, NULL);
LCD_Set_Addr(0, 0, CAMERA_RESOLUTION_X, CAMERA_RESOLUTION_Y);
// LCD_Set_Addr(0, 0, CAMERA_RESOLUTION_X, CAMERA_RESOLUTION_Y);
while (1) {
#ifdef TEST_TIM
@ -276,16 +285,30 @@ int main(void)
#ifdef USE_YUV422
yuv422sp_to_rgb24(picture, rgb_pic, CAMERA_RESOLUTION_X, CAMERA_RESOLUTION_Y);
rgb24_to_rgb565(rgb_pic, rgb16_pic);
LCD_DrawPicture_cam(0, 0, CAMERA_RESOLUTION_X, CAMERA_RESOLUTION_Y, picture);
// LCD_DrawPicture_cam(0, 0, CAMERA_RESOLUTION_X, CAMERA_RESOLUTION_Y, picture);
#else
LCD_WR_SPI_DMA((uint16_t *)picture, (CAMERA_FRAME_SIZE));
// LCD_WR_SPI_DMA((uint16_t *)picture, (CAMERA_FRAME_SIZE));
while (ili9341_draw_is_busy()) {
};
#ifdef TEST_TIM
sprintf((char *)str, "camera lcd test: time:%ld fps:%ld", time, 1000 / time);
lcd_set_dir(1, 0);
lcd_draw_str_ascii16(0, 0, 0x00f8, 0xffff, str, sizeof(str));
sprintf((char *)str, "camera size:%d x %d", CAMERA_RESOLUTION_X, CAMERA_RESOLUTION_Y);
lcd_draw_str_ascii16(80, 196, 0x00f8, 0xffff, str, sizeof(str));
#endif
lcd_set_dir(0, 0);
lcd_draw_picture_nonblocking(50, 96, CAMERA_RESOLUTION_X + 50 - 1, CAMERA_RESOLUTION_Y + 96 - 1, (uint16_t *)picture);
#endif
device_control(cam0, DEVICE_CTRL_CAM_FRAME_DROP, NULL);
device_control(cam0, DEVICE_CTRL_RESUME, NULL);
#ifdef TEST_TIM
timer_end = bflb_platform_get_time_ms();
MSG("time:%d\r\n", (timer_end - timer_start));
time = timer_end - timer_start;
// MSG("time:%d,FPS:%d\r\n", (timer_end - timer_start), (1000 / (timer_end - timer_start)));
#endif
}
}

2
examples/i2s/i2s_play_from_flash/main.c
View File

@ -89,6 +89,8 @@ int main(void)
DMA_DEV(dma_ch2)->transfer_mode = DMA_LLI_CYCLE_MODE;
DMA_DEV(dma_ch2)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_I2S_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_4BYTE;

12
examples/i2s/i2s_play_from_record/main.c
View File

@ -85,10 +85,12 @@ int main(void)
DMA_DEV(dma_ch3)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch3)->src_req = DMA_REQUEST_I2S_RX;
DMA_DEV(dma_ch3)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch3)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
device_open(dma_ch3, 0);
/* connect i2s device and dma device */
@ -106,10 +108,12 @@ int main(void)
DMA_DEV(dma_ch2)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch2)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_I2S_TX;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
device_open(dma_ch2, 0);
/* connect i2s device and dma device */

5
examples/i2s/i2s_play_from_sd/wav_play_from_sd_card.c
View File

@ -230,9 +230,12 @@ static int sd_wav_play_init(audio_dev_t *audio_dev, const TCHAR *path)
DMA_DEV(dma_ch2)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch2)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_I2S_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
switch (I2S_DEV(audio_dev->device)->data_size * I2S_DEV(audio_dev->device)->channel_num) {
case I2S_DATA_LEN_8:
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;

18
examples/spi/spi_i2s_mono_play/main.c
View File

@ -106,14 +106,16 @@ uint8_t spi_init(void)
dma_ch2 = device_find("ch2");
if (dma_ch2) {
((dma_device_t *)dma_ch2)->direction = DMA_MEMORY_TO_PERIPH;
((dma_device_t *)dma_ch2)->transfer_mode = DMA_LLI_CYCLE_MODE;
((dma_device_t *)dma_ch2)->src_req = DMA_REQUEST_NONE;
((dma_device_t *)dma_ch2)->dst_req = DMA_REQUEST_SPI0_TX;
((dma_device_t *)dma_ch2)->src_width = DMA_TRANSFER_WIDTH_16BIT;
((dma_device_t *)dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
((dma_device_t *)dma_ch2)->src_burst_size = 0;
((dma_device_t *)dma_ch2)->dst_burst_size = 0;
DMA_DEV(dma_ch2)->direction = DMA_MEMORY_TO_PERIPH;
DMA_DEV(dma_ch2)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch2)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_SPI0_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
device_open(dma_ch2, 0);
device_set_callback(dma_ch2, NULL);
device_control(dma_ch2, DEVICE_CTRL_SET_INT, NULL);

32
examples/spi/spi_i2s_mono_record/main.c
View File

@ -98,12 +98,16 @@ uint8_t spi_init(void)
dma_ch2 = device_find("ch2");
if (dma_ch2) {
((dma_device_t *)dma_ch2)->direction = DMA_MEMORY_TO_PERIPH;
((dma_device_t *)dma_ch2)->transfer_mode = DMA_LLI_ONCE_MODE;
((dma_device_t *)dma_ch2)->src_req = DMA_REQUEST_NONE;
((dma_device_t *)dma_ch2)->dst_req = DMA_REQUEST_SPI0_TX;
((dma_device_t *)dma_ch2)->src_width = DMA_TRANSFER_WIDTH_16BIT;
((dma_device_t *)dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch2)->direction = DMA_MEMORY_TO_PERIPH;
DMA_DEV(dma_ch2)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch2)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_SPI0_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
device_open(dma_ch2, 0);
device_set_callback(dma_ch2, dma_ch2_irq_callback);
device_control(dma_ch2, DEVICE_CTRL_SET_INT, NULL);
@ -113,12 +117,16 @@ uint8_t spi_init(void)
dma_register(DMA0_CH3_INDEX, "ch3");
dma_ch3 = device_find("ch3");
if (dma_ch3) {
((dma_device_t *)dma_ch3)->direction = DMA_PERIPH_TO_MEMORY;
((dma_device_t *)dma_ch3)->transfer_mode = DMA_LLI_ONCE_MODE;
((dma_device_t *)dma_ch3)->src_req = DMA_REQUEST_SPI0_RX;
((dma_device_t *)dma_ch3)->dst_req = DMA_REQUEST_NONE;
((dma_device_t *)dma_ch3)->src_width = DMA_TRANSFER_WIDTH_16BIT;
((dma_device_t *)dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch3)->direction = DMA_PERIPH_TO_MEMORY;
DMA_DEV(dma_ch3)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch3)->src_req = DMA_REQUEST_SPI0_RX;
DMA_DEV(dma_ch3)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch3)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch3)->src_width = DMA_TRANSFER_WIDTH_16BIT;
DMA_DEV(dma_ch3)->dst_width = DMA_TRANSFER_WIDTH_16BIT;
device_open(dma_ch3, 0);
device_set_callback(dma_ch3, NULL);
device_control(dma_ch3, DEVICE_CTRL_SET_INT, NULL);

10
examples/uart/uart_dma/main.c
View File

@ -61,6 +61,16 @@ int main(void)
struct device *dma_ch2 = device_find("ch2");
if (dma_ch2) {
DMA_DEV(dma_ch2)->direction = DMA_MEMORY_TO_PERIPH;
DMA_DEV(dma_ch2)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch2)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_UART1_TX;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch2, 0);
device_set_callback(dma_ch2, dma_ch2_irq_callback);
device_control(dma_ch2, DEVICE_CTRL_SET_INT, NULL);

19
examples/usb/usb_audio_mic_speaker/main.c
View File

@ -545,10 +545,12 @@ void audio_init()
DMA_DEV(dma_ch2_i2s_tx)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch2_i2s_tx)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch2_i2s_tx)->dst_req = DMA_REQUEST_I2S_TX;
DMA_DEV(dma_ch2_i2s_tx)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch2_i2s_tx)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch2_i2s_tx)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2_i2s_tx)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2_i2s_tx)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2_i2s_tx)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch2_i2s_tx)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch2_i2s_tx)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
device_open(dma_ch2_i2s_tx, 0);
/* connect i2s device and dma device */
@ -566,10 +568,12 @@ void audio_init()
DMA_DEV(dma_ch3_i2s_rx)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch3_i2s_rx)->src_req = DMA_REQUEST_I2S_RX;
DMA_DEV(dma_ch3_i2s_rx)->dst_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch3_i2s_rx)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch3_i2s_rx)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch3_i2s_rx)->src_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch3_i2s_rx)->dst_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch3_i2s_rx)->dst_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3_i2s_rx)->src_burst_size = DMA_BURST_4BYTE;
DMA_DEV(dma_ch3_i2s_rx)->src_width = DMA_TRANSFER_WIDTH_32BIT;
DMA_DEV(dma_ch3_i2s_rx)->dst_width = DMA_TRANSFER_WIDTH_32BIT;
device_open(dma_ch3_i2s_rx, 0);
/* connect i2s device and dma device */
@ -606,11 +610,12 @@ int main(void)
DMA_DEV(dma_ch4_usb_tx)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch4_usb_tx)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch4_usb_tx)->dst_req = DMA_REQUEST_USB_EP1;
DMA_DEV(dma_ch4_usb_tx)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch4_usb_tx)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch4_usb_tx)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch4_usb_tx)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch4_usb_tx)->src_burst_size = DMA_BURST_16BYTE;
DMA_DEV(dma_ch4_usb_tx)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch4_usb_tx)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch4_usb_tx)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch4_usb_tx, 0);
// device_set_callback(dma_ch4_usb_tx, dma2_irq_callback);
// device_control(dma_ch4_usb_tx, DEVICE_CTRL_SET_INT, NULL);

282
examples/usb/usb_audio_mouse/main.c
View File

@ -55,6 +55,7 @@
#define MIC_FU_ID 0x02
#define MIC_OT_ID 0x03
#if 0
#define USB_AUDIO_CONFIG_DESC_SIZ (unsigned long)(9 + \
9 + \
9 + \
@ -281,7 +282,7 @@ USB_DESC_SECTION const uint8_t audio_descriptor[] = {
'D', 0x00, /* wcChar15 */
'E', 0x00, /* wcChar16 */
'M', 0x00, /* wcChar17 */
'O', 0x00, /* wcChar18 */
'm', 0x00, /* wcChar18 */
///////////////////////////////////////
/// string3 descriptor
///////////////////////////////////////
@ -315,6 +316,276 @@ USB_DESC_SECTION const uint8_t audio_descriptor[] = {
0x00
};
#else
#define USB_AUDIO_CONFIG_DESC_SIZ (unsigned long)(9 + \
9 + \
9 + \
12 + \
9 + \
7 + \
10 + \
9 + \
9 + \
7 + \
11 + \
9 + \
7 + \
25)
USB_DESC_SECTION const uint8_t audio_descriptor[] = {
USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01),
USB_CONFIG_DESCRIPTOR_INIT(USB_AUDIO_CONFIG_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER),
/* ------------------ AudioControl Interface ------------------ */
/* USB Microphone Standard AC Interface Descriptor */
0x09, /* bLength */
USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */
0x00, /* bInterfaceNumber */
0x00, /* bAlternateSetting */
0x00, /* bNumEndpoints */
USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */
AUDIO_SUBCLASS_AUDIOCONTROL, /* bInterfaceSubClass */
AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */
0x00, /* iInterface */
/* 09 byte*/
/* USB Microphone Class-specific AC Interface Descriptor */
0x09, /* bLength */
AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
AUDIO_CONTROL_HEADER, /* bDescriptorSubtype */
0x00, /* 1.00 */ /* bcdADC */
0x01,
0x2f, /* wTotalLength */
0x00,
0x01, /* bInCollection */
0x01, /* baInterfaceNr */
/* 09 byte*/
/* USB Microphone Input Terminal Descriptor */
0x0C, /* bLength */
AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
AUDIO_CONTROL_INPUT_TERMINAL, /* bDescriptorSubtype */
0x02, /* bTerminalID */
0x05, /* wTerminalType : Microphone 0x0201 */
0x02,
0x00, /* bAssocTerminal */
0x02, /* bNrChannels */
0x03, /* wChannelConfig : Mono sets no position bits */
0x00,
0x00, /* iChannelNames */
0x00, /* iTerminal */
/* 12 byte*/
/*USB Microphone Output Terminal Descriptor */
0x09, /* bLength */
AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
AUDIO_CONTROL_OUTPUT_TERMINAL, /* bDescriptorSubtype */
0x12, /* bTerminalID */
0x01, /* wTerminalType : speaker */
0x01,
0x02, /* bAssocTerminal */
0x21, /* bSourceID */
0x00, /* iTerminal */
/* 09 byte*/
0x07,
AUDIO_INTERFACE_DESCRIPTOR_TYPE,
AUDIO_CONTROL_SELECTOR_UNIT,
0x21, // bUnitID
0x01, //bNrInPins
0x32, //baSourceID0
0x00, //iSelector
/* USB Microphone Audio Feature Unit Descriptor */
0x0a, /* bLength */
AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
AUDIO_CONTROL_FEATURE_UNIT, /* bDescriptorSubtype */
0x32, /* bUnitID */
0x02, /* bSourceID */
0x01, /* bControlSize */
0x03, /* bmaControls(0) Mute */
0x00, /* bmaControls(1) Volume */
0x00, /* bmaControls(2) Volume */
0x00, /* iFeature */
/* 10 byte*/
/* --------------- AudioStreaming Interface --------------- */
/* USB Microphone Standard AS Interface Descriptor - Audio Streaming Zero Bandwith */
/* Interface 1, Alternate Setting 0 */
0x09, /* bLength */
USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */
0x01, /* bInterfaceNumber */
0x00, /* bAlternateSetting */
0x00, /* bNumEndpoints */
USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */
AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */
AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */
0x00, /* iInterface */
/* 09 byte*/
/* USB Microphone Standard AS Interface Descriptor - Audio Streaming Operational */
/* Interface 1, Alternate Setting 1 */
0x09, /* bLength */
USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */
0x01, /* bInterfaceNumber */
0x01, /* bAlternateSetting */
0x01, /* bNumEndpoints */
USB_DEVICE_CLASS_AUDIO, /* bInterfaceClass */
AUDIO_SUBCLASS_AUDIOSTREAMING, /* bInterfaceSubClass */
AUDIO_PROTOCOL_UNDEFINED, /* bInterfaceProtocol */
0x00, /* iInterface */
/* 09 byte*/
/* USB Microphone Class-specific AS General Interface Descriptor */
0X07, /* bLength */
AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
AUDIO_STREAMING_GENERAL, /* bDescriptorSubtype */
0x12, /* bTerminalLink : Unit ID of the Output Terminal*/
0x01, /* bDelay */
0x01, /* wFormatTag : AUDIO_FORMAT_PCM */
0x00,
/* 07 byte*/
/* USB Microphone Audio Type I Format Type Descriptor */
0x0b, /* bLength */
AUDIO_INTERFACE_DESCRIPTOR_TYPE, /* bDescriptorType */
AUDIO_STREAMING_FORMAT_TYPE, /* bDescriptorSubtype */
AUDIO_FORMAT_TYPE_I, /* bFormatType */
0x02, /* bNrChannels */
0x02, /* bSubFrameSize : 2 Bytes per audio subframe */
0x10, /* bBitResolution : 16 bits per sample */
0x01, /* bSamFreqType : only one frequency supported */
AUDIO_SAMPLE_FREQ(USBD_AUDIO_FREQ), /* tSamFreq : Audio sampling frequency coded on 3 bytes */
/* 11 byte*/
/* USB Microphone Standard AS Audio Data Endpoint Descriptor */
0x09, /* bLength */
USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */
AUDIO_IN_EP, /* bEndpointAddress : IN endpoint 1 */
0x01, /* bmAttributes */
LO_BYTE(AUDIO_IN_PACKET), /* wMaxPacketSize */
HI_BYTE(AUDIO_IN_PACKET),
0x01, /* bInterval : one packet per frame */
0x00, /* bRefresh */
0x00, /* bSynchAddress */
/* 09 byte*/
/* USB Microphone Class-specific Isoc. Audio Data Endpoint Descriptor */
0x07, /* bLength */
AUDIO_ENDPOINT_DESCRIPTOR_TYPE, /* bDescriptorType */
AUDIO_ENDPOINT_GENERAL, /* bDescriptor */
0x00, /* bmAttributes AUDIO_SAMPLING_FREQ_CONTROL */
0x00, /* bLockDelayUnits */
0x00, /* wLockDelay */
0x00,
/* 07 byte*/
/************** Descriptor of Joystick Mouse interface ****************/
/* 09 */
0x09, /* bLength: Interface Descriptor size */
USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */
0x02, /* bInterfaceNumber: Number of Interface */
0x00, /* bAlternateSetting: Alternate setting */
0x01, /* bNumEndpoints */
0x03, /* bInterfaceClass: HID */
0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */
0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
0, /* iInterface: Index of string descriptor */
/******************** Descriptor of Joystick Mouse HID ********************/
/* 18 */
0x09, /* bLength: HID Descriptor size */
HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */
0x11, /* bcdHID: HID Class Spec release number */
0x01,
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
HID_MOUSE_REPORT_DESC_SIZE, /* wItemLength: Total length of Report descriptor */
0x00,
/******************** Descriptor of Mouse endpoint ********************/
/* 27 */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */
HID_INT_EP, /* bEndpointAddress: Endpoint Address (IN) */
0x03, /* bmAttributes: Interrupt endpoint */
HID_INT_EP_SIZE, /* wMaxPacketSize: 4 Byte max */
0x00,
HID_INT_EP_INTERVAL, /* bInterval: Polling Interval */
///////////////////////////////////////
/// string0 descriptor
///////////////////////////////////////
USB_LANGID_INIT(USBD_LANGID_STRING),
///////////////////////////////////////
/// string1 descriptor
///////////////////////////////////////
0x12, /* bLength */
USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */
'B', 0x00, /* wcChar0 */
'o', 0x00, /* wcChar1 */
'u', 0x00, /* wcChar2 */
'f', 0x00, /* wcChar3 */
'f', 0x00, /* wcChar4 */
'a', 0x00, /* wcChar5 */
'l', 0x00, /* wcChar6 */
'o', 0x00, /* wcChar7 */
///////////////////////////////////////
/// string2 descriptor
///////////////////////////////////////
0x28, /* bLength */
USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */
'B', 0x00, /* wcChar0 */
'o', 0x00, /* wcChar1 */
'u', 0x00, /* wcChar2 */
'f', 0x00, /* wcChar3 */
'f', 0x00, /* wcChar4 */
'a', 0x00, /* wcChar5 */
'l', 0x00, /* wcChar6 */
'o', 0x00, /* wcChar7 */
' ', 0x00, /* wcChar8 */
'A', 0x00, /* wcChar9 */
'U', 0x00, /* wcChar10 */
'D', 0x00, /* wcChar11 */
'I', 0x00, /* wcChar12 */
'O', 0x00, /* wcChar13 */
' ', 0x00, /* wcChar14 */
'D', 0x00, /* wcChar15 */
'E', 0x00, /* wcChar16 */
'M', 0x00, /* wcChar17 */
'O', 0x00, /* wcChar18 */
///////////////////////////////////////
/// string3 descriptor
///////////////////////////////////////
0x16, /* bLength */
USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */
'2', 0x00, /* wcChar0 */
'0', 0x00, /* wcChar1 */
'2', 0x00, /* wcChar2 */
'1', 0x00, /* wcChar3 */
'0', 0x00, /* wcChar4 */
'3', 0x00, /* wcChar5 */
'1', 0x00, /* wcChar6 */
'0', 0x00, /* wcChar7 */
'0', 0x00, /* wcChar8 */
'0', 0x00, /* wcChar9 */
///////////////////////////////////////
/// device qualifier descriptor
///////////////////////////////////////
0x0a,
USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER,
0x00,
0x02,
0x00,
0x00,
0x00,
0x40,
0x01,
0x00,
0x00
};
#endif
static const uint8_t hid_mouse_report_desc[HID_MOUSE_REPORT_DESC_SIZE] = {
0x05, 0x01, // USAGE_PAGE (Generic Desktop)
0x09, 0x02, // USAGE (Mouse)
@ -457,7 +728,16 @@ int main(void)
dma_ch2 = device_find("ch2");
if (dma_ch2) {
DMA_DEV(dma_ch2)->direction = DMA_MEMORY_TO_PERIPH;
DMA_DEV(dma_ch2)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch2)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_USB_EP1;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_16BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch2, 0);
// device_set_callback(dma_ch2, dma2_irq_callback);
// device_control(dma_ch2, DEVICE_CTRL_SET_INT, NULL);

9
examples/usb/usb_video/main.c
View File

@ -556,7 +556,16 @@ int main(void)
dma_ch2 = device_find("ch2");
if (dma_ch2) {
DMA_DEV(dma_ch2)->direction = DMA_MEMORY_TO_PERIPH;
DMA_DEV(dma_ch2)->transfer_mode = DMA_LLI_ONCE_MODE;
DMA_DEV(dma_ch2)->src_req = DMA_REQUEST_NONE;
DMA_DEV(dma_ch2)->dst_req = DMA_REQUEST_USB_EP1;
DMA_DEV(dma_ch2)->src_addr_inc = DMA_ADDR_INCREMENT_ENABLE;
DMA_DEV(dma_ch2)->dst_addr_inc = DMA_ADDR_INCREMENT_DISABLE;
DMA_DEV(dma_ch2)->src_burst_size = DMA_BURST_16BYTE;
DMA_DEV(dma_ch2)->dst_burst_size = DMA_BURST_1BYTE;
DMA_DEV(dma_ch2)->src_width = DMA_TRANSFER_WIDTH_8BIT;
DMA_DEV(dma_ch2)->dst_width = DMA_TRANSFER_WIDTH_8BIT;
device_open(dma_ch2, 0);
// device_set_callback(dma_ch2, dma2_irq_callback);
// device_control(dma_ch2, DEVICE_CTRL_SET_INT, NULL);