diff --git a/examples/boot2_isp/CMakeLists.txt b/examples/boot2_isp/CMakeLists.txt index b8b9d894..2f3f8c10 100644 --- a/examples/boot2_isp/CMakeLists.txt +++ b/examples/boot2_isp/CMakeLists.txt @@ -16,11 +16,14 @@ target_sources(app PRIVATE blsp_ram_image_boot.c partition.c softcrc.c - rv32i_xtheade_lz4.S ${CMAKE_SOURCE_DIR}/port/${CHIP}/bflb_port_boot2.c ) +if("${CHIP}" STREQUAL "bl616") +target_sources(app PRIVATE rv32i_xtheade_lz4.S) +endif() + if(IS_DIRECTORY ${CMAKE_SOURCE_DIR}/port/${CHIP}) include_directories(${CMAKE_SOURCE_DIR}/port/${CHIP}) else() @@ -30,8 +33,31 @@ include_directories(${CMAKE_SOURCE_DIR}) sdk_set_main_file(main.c) sdk_set_linker_script(port/${CHIP}/blsp_boot2_iap_flash.ld) -if(CONFIG_DEBUG) +if("${CONFIG_DEBUG}" STREQUAL "y") sdk_add_compile_definitions(-DCONFIG_DEBUG) endif() +sdk_add_compile_definitions(-DBFLB_BOOT2_VER="${CONFIG_BOOT2_VER}") +message(${CONFIG_BOOT2_VER}) +if((${CHIP} STREQUAL "bl602")) + sdk_add_compile_definitions(-DCHIP_BL602) +endif() + +if((${CHIP} STREQUAL "bl702")) + sdk_add_compile_definitions(-DCHIP_BL702) +endif() + +if((${CHIP} STREQUAL "bl808")) + sdk_add_compile_definitions(-DCHIP_BL808) +endif() + +if((${CHIP} STREQUAL "bl606p")) + sdk_add_compile_definitions(-DCHIP_BL606P) +endif() + +if((${CHIP} STREQUAL "bl616")) + sdk_add_compile_definitions(-DCHIP_BL616) +endif() + + project(boot2_isp) diff --git a/examples/boot2_isp/Makefile b/examples/boot2_isp/Makefile index 34b2f3fa..0632633c 100644 --- a/examples/boot2_isp/Makefile +++ b/examples/boot2_isp/Makefile @@ -6,8 +6,8 @@ export BL_SDK_BASE CHIP ?= bl616 BOARD ?= bl616dk CROSS_COMPILE ?= riscv64-unknown-elf- - +CONFIG_BOOT2_VER ?= 1.0.0 # add custom cmake definition -#cmake_definition+=-Dxxx=sss +cmake_definition+=-DCONFIG_BOOT2_VER=${CONFIG_BOOT2_VER} include $(BL_SDK_BASE)/project.build diff --git a/examples/boot2_isp/ReadMe b/examples/boot2_isp/ReadMe new file mode 100644 index 00000000..76789cfd --- /dev/null +++ b/examples/boot2_isp/ReadMe @@ -0,0 +1,11 @@ +compile cmd: + +make CHIP=bl602 BOARD=bl602dk + +make CHIP=bl702 BOARD=bl702dk + +make CHIP=bl808 CPU_ID=m0 BOARD=bl808dk + +make CHIP=bl606p CPU_ID=m0 BOARD=bl606pdk + +make CHIP=bl616 CPU_ID=m0 BOARD=bl616dk \ No newline at end of file diff --git a/examples/boot2_isp/bflb_eflash_loader_cmds.c b/examples/boot2_isp/bflb_eflash_loader_cmds.c index a19b4241..15572974 100644 --- a/examples/boot2_isp/bflb_eflash_loader_cmds.c +++ b/examples/boot2_isp/bflb_eflash_loader_cmds.c @@ -43,11 +43,11 @@ #include "bflb_sec_sha.h" #include "blsp_media_boot.h" #include "blsp_common.h" +#include "bflb_flash.h" #define BFLB_EFLASH_LOADER_CHECK_LEN 2048 #define BFLB_EFLASH_MAX_SIZE 2 * 1024 * 1024 -extern struct device *download_uart; #if BLSP_BOOT2_SUPPORT_EFLASH_LOADER_RAM static struct image_cfg_t image_cfg; @@ -331,7 +331,7 @@ static int32_t bflb_bootrom_cmd_load_segdata(uint16_t cmd, uint8_t *data, uint16 } /*no encryption,copy directlly */ - ARCH_MemCpy_Fast((void *)segment_hdr.destaddr, data, len); + arch_memcpy_fast((void *)segment_hdr.destaddr, data, len); //LOG_F("segment_hdr.destaddr 0x%08x, len %d,data %02x %02x %02x %02x \r\n", segment_hdr.destaddr, len, data[0], data[1], data[2], data[3]); img_ctrl.segdata_recv_len += len; segment_hdr.destaddr += len; @@ -479,7 +479,7 @@ static int32_t bflb_eflash_loader_cmd_read_jedec_id(uint16_t cmd, uint8_t *data, /*ack read jedec ID */ tmp_buf[2] = 4; tmp_buf[3] = 0; - flash_read_jedec_id((uint8_t *)&ackdata[1]); + ackdata[0] = bflb_flash_get_jedec_id(); ackdata[1] &= 0x00ffffff; ackdata[1] |= 0x80000000; bflb_eflash_loader_if_write((uint32_t *)ackdata, 4 + 4); @@ -499,7 +499,7 @@ static int32_t bflb_eflash_loader_cmd_reset(uint16_t cmd, uint8_t *data, uint16_ hal_boot2_set_psmode_status(0x594c440B); /* FPGA POR RST NOT work,so add system reset */ - bflb_platform_delay_us(10); + arch_delay_us(10); hal_boot2_sw_system_reset(); return ret; @@ -523,7 +523,7 @@ static int32_t bflb_eflash_loader_cmd_erase_flash(uint16_t cmd, uint8_t *data, u //LOG_F("from%08xto%08x\n", startaddr, endaddr); - if (SUCCESS != flash_erase(startaddr, endaddr - startaddr + 1)) { + if (SUCCESS != bflb_flash_erase(startaddr, endaddr - startaddr + 1)) { //LOG_F("fail\n"); ret = BFLB_EFLASH_LOADER_FLASH_ERASE_ERROR; } @@ -547,7 +547,7 @@ static int32_t ATTR_TCM_SECTION bflb_eflash_loader_cmd_write_flash(uint16_t cmd, write_len = len - 4; //LOG_F("to%08x,%d\n", startaddr, write_len); if (startaddr < 0xffffffff) { - if (SUCCESS != flash_write(startaddr, data + 4, write_len)) { + if (SUCCESS != bflb_flash_write(startaddr, data + 4, write_len)) { /*error , response again with error */ //LOG_F("fail\r\n"); ret = BFLB_EFLASH_LOADER_FLASH_WRITE_ERROR; @@ -584,7 +584,7 @@ static int32_t bflb_eflash_loader_cmd_read_flash(uint16_t cmd, uint8_t *data, ui ackdata[1] = 'K'; ackdata[2] = read_len & 0xff; ackdata[3] = (read_len >> 8) & 0xff; - flash_read(startaddr, &ackdata[4], read_len); + bflb_flash_read(startaddr, &ackdata[4], read_len); bflb_eflash_loader_cmd_response((uint32_t *)ackdata, read_len + 4); } diff --git a/examples/boot2_isp/bflb_eflash_loader_cmds.h b/examples/boot2_isp/bflb_eflash_loader_cmds.h index 202ff5b5..d19a57b0 100644 --- a/examples/boot2_isp/bflb_eflash_loader_cmds.h +++ b/examples/boot2_isp/bflb_eflash_loader_cmds.h @@ -38,7 +38,7 @@ #include "stdint.h" #include "bflb_core.h" -#include "bl616_sflash.h" +#include "bflb_port_boot2.h" #define BFLB_EFLASH_LOADER_CMD_GET_BOOTINFO 0x0010 #define BFLB_EFLASH_LOADER_CMD_LOAD_BOOTHEADER 0x0011 diff --git a/examples/boot2_isp/bflb_eflash_loader_uart.c b/examples/boot2_isp/bflb_eflash_loader_uart.c index a088ece0..94a15340 100644 --- a/examples/boot2_isp/bflb_eflash_loader_uart.c +++ b/examples/boot2_isp/bflb_eflash_loader_uart.c @@ -38,6 +38,7 @@ #include "blsp_common.h" #include "partition.h" #include "bflb_uart.h" +#include "bflb_port_boot2.h" static uint32_t g_detected_baudrate; struct bflb_device_s *uartx; @@ -74,6 +75,7 @@ static void bflb_eflash_loader_usart_if_init(uint32_t bdrate) void bflb_eflash_loader_usart_if_enable_int(void) { + bflb_uart_rxint_mask(uartx,false); } void bflb_eflash_loader_usart_if_send(uint8_t *data, uint32_t len) @@ -116,7 +118,6 @@ int32_t bflb_eflash_loader_uart_handshake_poll(uint32_t timeout) uint32_t handshake_count = 0; uint32_t rcv_buf_len = 0; //rcv_buf_len = UART_ReceiveData(g_uart_if_id,buf,128); - //struct device *download_uart = device_find("download_uart"); uartx = bflb_device_get_by_name("uart0"); rcv_buf_len = bflb_uart_get(uartx, buf, UART_FIFO_LEN); @@ -139,7 +140,7 @@ int32_t bflb_eflash_loader_uart_handshake_poll(uint32_t timeout) return -1; } -#if 1 //defined(CHIP_BL606P) || defined(CHIP_BL808) || defined(CHIP_BL616) || defined(CHIP_WB03) +#if defined(CHIP_BL606P) || defined(CHIP_BL808) || defined(CHIP_BL616) || defined(CHIP_WB03) /*receive shake hanad signal*/ bflb_eflash_loader_usart_if_send((uint8_t *)"Boot2 ISP Ready", strlen("Boot2 ISP Ready")); bflb_mtimer_delay_ms(2); @@ -159,30 +160,19 @@ int32_t bflb_eflash_loader_uart_handshake_poll(uint32_t timeout) /* consume the remaining bytes when shake hand(0x55) if needed */ nowtime = bflb_mtimer_get_time_ms(); do { - rcv_buf_len = device_read(download_uart, 0, buf, UART_FIFO_LEN); + + rcv_buf_len = bflb_uart_get(uartx,buf,UART_FIFO_LEN); if (rcv_buf_len > 0) { - nowtime = bflb_platform_get_time_ms(); + nowtime = bflb_mtimer_get_time_ms(); } - } while (bflb_platform_get_time_ms() - nowtime < BFLB_EFLASH_LAODER_COMSUME_55_TIMEOUT); + } while (bflb_mtimer_get_time_ms() - nowtime < BFLB_EFLASH_LAODER_COMSUME_55_TIMEOUT); bflb_eflash_loader_usart_if_send((uint8_t *)"Boot2 ISP Ready", strlen("Boot2 ISP Ready")); /*init rx info */ g_rx_buf_index = 0; g_rx_buf_len = 0; -#if (BLSP_BOOT2_MODE == BOOT2_MODE_DEBUG) - arch_delay_ms(2); - bflb_platform_print_set(1); - device_unregister("debug_log"); - uart_register(0, "iap_download"); - download_uart = device_find("iap_download"); - - if (download_uart) { - UART_DEV(download_uart)->fifo_threshold = 16; - device_open(download_uart, DEVICE_OFLAG_STREAM_TX); - } -#endif simple_malloc_init(g_malloc_buf, sizeof(g_malloc_buf)); g_eflash_loader_readbuf[0] = vmalloc(BFLB_EFLASH_LOADER_READBUF_SIZE); diff --git a/examples/boot2_isp/bflb_eflash_loader_usb.c b/examples/boot2_isp/bflb_eflash_loader_usb.c index 197a533b..dbcb6b1c 100644 --- a/examples/boot2_isp/bflb_eflash_loader_usb.c +++ b/examples/boot2_isp/bflb_eflash_loader_usb.c @@ -248,7 +248,7 @@ int32_t bflb_eflash_loader_usb_handshake_poll(uint32_t timeout) uint32_t handshake_count = 0; uint8_t *buf = g_eflash_loader_readbuf[g_rx_buf_index]; - time_now = bflb_platform_get_time_ms(); + time_now = bflb_mtimer_get_time_ms(); LOG_D("usb iap handshake poll\r\n"); do { @@ -266,7 +266,7 @@ int32_t bflb_eflash_loader_usb_handshake_poll(uint32_t timeout) break; } } - } while ((timeout == 0) ? 1 : (bflb_platform_get_time_ms() - time_now < timeout * 1000)); + } while ((timeout == 0) ? 1 : (bflb_mtimer_get_time_ms() - time_now < timeout * 1000)); if (handshake_count >= BFLB_EFLASH_LAODER_HAND_SHAKE_SUSS_COUNT) { LOG_D("iap handshake %d 0x55 rcv\r\n", handshake_count); @@ -284,17 +284,17 @@ int32_t bflb_eflash_loader_usb_handshake_poll(uint32_t timeout) g_rx_buf_index = 0; g_rx_buf_len = 0; - time_now = bflb_platform_get_time_ms(); + time_now = bflb_mtimer_get_time_ms(); do { if (g_rx_buf_len > 0) { if (0 == bflb_eflash_loader_check_handshake_buf(buf, g_rx_buf_len)) { g_rx_buf_len = 0; - time_now = bflb_platform_get_time_ms(); + time_now = bflb_mtimer_get_time_ms(); } else { break; } } - } while (bflb_platform_get_time_ms() - time_now < 50); + } while (bflb_mtimer_get_time_ms() - time_now < 50); return BFLB_EFLASH_LOADER_SUCCESS; } diff --git a/examples/boot2_isp/blsp_boot_parser.c b/examples/boot2_isp/blsp_boot_parser.c index 91660c61..b6f96bff 100644 --- a/examples/boot2_isp/blsp_boot_parser.c +++ b/examples/boot2_isp/blsp_boot_parser.c @@ -86,7 +86,6 @@ int32_t blsp_boot_parse_pkey(boot2_image_config *g_boot_img_cfg, uint8_t *data, /* Check public key with data info in OTP*/ bflb_sha256_update(sha, &ctx_sha256, data, HAL_BOOT2_ECC_KEYXSIZE + HAL_BOOT2_ECC_KEYYSIZE); bflb_sha256_finish(sha, &ctx_sha256, (uint8_t *)pk_hash); - //bflb_sha_deinit(&hash_handle);//ToDo bflb_sha_init(sha, SHA_MODE_SHA256); bflb_sha256_start(sha, &ctx_sha256); @@ -100,8 +99,8 @@ int32_t blsp_boot_parse_pkey(boot2_image_config *g_boot_img_cfg, uint8_t *data, } if (own == 1) { - ARCH_MemCpy_Fast(g_boot_img_cfg->eckye_x, cfg->eckye_x, sizeof(cfg->eckye_x)); - ARCH_MemCpy_Fast(g_boot_img_cfg->eckey_y, cfg->eckey_y, sizeof(cfg->eckey_y)); + arch_memcpy_fast(g_boot_img_cfg->eckye_x, cfg->eckye_x, sizeof(cfg->eckye_x)); + arch_memcpy_fast(g_boot_img_cfg->eckey_y, cfg->eckey_y, sizeof(cfg->eckey_y)); } } else { LOG_E("PK crc error\r\n"); @@ -135,10 +134,10 @@ int32_t blsp_boot_parse_signature(boot2_image_config *g_boot_img_cfg, uint8_t *d if (memcmp(&crc, &cfg->signature[cfg->sig_len], 4) == 0) { if (own == 1) { - ARCH_MemCpy_Fast(g_boot_img_cfg->signature, cfg->signature, cfg->sig_len); + arch_memcpy_fast(g_boot_img_cfg->signature, cfg->signature, cfg->sig_len); //g_boot_img_cfg->sig_len = cfg->sig_len; } else { - ARCH_MemCpy_Fast(g_boot_img_cfg->signature2, cfg->signature, cfg->sig_len); + arch_memcpy_fast(g_boot_img_cfg->signature2, cfg->signature, cfg->sig_len); //g_boot_img_cfg->sig_len2 = cfg->sig_len; } } else { @@ -236,7 +235,6 @@ int32_t blsp_boot_parser_check_hash(boot2_image_config *g_boot_img_cfg) if (!g_boot_img_cfg->basic_cfg.hash_ignore) { //Sec_Eng_SHA256_Finish(&g_sha_ctx, SEC_ENG_SHA_ID0, (uint8_t *)img_hash_cal); bflb_sha256_finish(sha, &ctx_sha256, (uint8_t *)img_hash_cal); - //sec_hash_deinit(&hash_handle);//ToDo if (memcmp(img_hash_cal, g_boot_img_cfg->basic_cfg.hash, 32) != 0) { LOG_E("Hash error\r\n"); diff --git a/examples/boot2_isp/blsp_media_boot.c b/examples/boot2_isp/blsp_media_boot.c index 03ab4eb2..fb28cc73 100644 --- a/examples/boot2_isp/blsp_media_boot.c +++ b/examples/boot2_isp/blsp_media_boot.c @@ -121,7 +121,7 @@ static int32_t blsp_mediaboot_read_signaure(uint32_t addr, uint32_t *len) return ret; } - ARCH_MemCpy_Fast(g_boot2_read_buf, &sig_len, sizeof(sig_len)); + arch_memcpy_fast(g_boot2_read_buf, &sig_len, sizeof(sig_len)); addr += (sig_len + 4); *len = sig_len; diff --git a/examples/boot2_isp/blsp_port.c b/examples/boot2_isp/blsp_port.c index a888e62e..80f4d6dd 100644 --- a/examples/boot2_isp/blsp_port.c +++ b/examples/boot2_isp/blsp_port.c @@ -41,7 +41,6 @@ #include "blsp_bootinfo.h" #include "blsp_common.h" #include "blsp_media_boot.h" -#include "tzc_sec_reg.h" extern uint32_t __boot2_pass_param_addr; static uint32_t start_time = 0; @@ -99,6 +98,21 @@ uint8_t blsp_read_power_save_mode(void) *******************************************************************************/ void blsp_boot2_pass_parameter(void *data, uint32_t len) { + static uint8_t *p_parameter = NULL; + + if (len == 0) { + //GLB_Set_EM_Sel(0); //system init has done + //p_parameter = (uint8_t *)(0x42020000 + 60 * 1024); + //p_parameter = (uint8_t *)(0x42030000+103*1024); + p_parameter = (uint8_t *)&__boot2_pass_param_addr; + return; + } + + if(p_parameter!=NULL){ + LOG_F("pass param addr %08x,len %d\r\n", p_parameter,len); + arch_memcpy_fast(p_parameter, data, len); + p_parameter += len; + } } /****************************************************************************/ /** diff --git a/examples/boot2_isp/blsp_ram_image_boot.c b/examples/boot2_isp/blsp_ram_image_boot.c index 58687a0a..940cdf37 100644 --- a/examples/boot2_isp/blsp_ram_image_boot.c +++ b/examples/boot2_isp/blsp_ram_image_boot.c @@ -40,7 +40,6 @@ #include "blsp_media_boot.h" #include "blsp_boot_decompress.h" #include "blsp_common.h" -#include "blsp_version.h" #include "partition.h" #include "softcrc.h" #include "bflb_flash.h" @@ -82,7 +81,6 @@ static int blsp_cal_ram_img_hash(uint32_t src, uint32_t total_len, uint8_t *hash cur_len += read_len; } bflb_sha256_finish(sha, &ctx_sha256, (uint8_t *)cal_hash); - //sec_hash_deinit(&hash_handle); //ToDo if (memcmp(hash, cal_hash, 32) != 0) { LOG_E("Cal hash error\r\n"); return -1; diff --git a/examples/boot2_isp/boot2_release.py b/examples/boot2_isp/boot2_release.py new file mode 100644 index 00000000..a9ddbf9b --- /dev/null +++ b/examples/boot2_isp/boot2_release.py @@ -0,0 +1,95 @@ +import sys,os,shutil +import hashlib, sys, binascii, struct +import time +import subprocess +import re +import zipfile +import argparse + +git_cmd=r'git describe --tags '#--dirty +tag_standard="boot2_v1.0.0" + +release_list = [ +[r'make clean;make CHIP=bl602 BOARD=bl602dk ',"bl602","release"], +[r'make clean;make CHIP=bl702 BOARD=bl702dk ',"bl702","release"], +[r'make clean;make CHIP=bl808 CPU_ID=m0 BOARD=bl808dk ',"bl808","release"], +[r'make clean;make CHIP=bl606p CPU_ID=m0 BOARD=bl606pdk ',"bl606p","release"], +[r'make clean;make CHIP=bl616 CPU_ID=m0 BOARD=bl616dk ',"bl616","release"], +] + + + +def zipDir(dirpath,outFullName): + """ + 压缩指定文件夹 + :param dirpath: 目标文件夹路径 + :param outFullName: 压缩文件保存路径+xxxx.zip + :return: 无 + """ + zip = zipfile.ZipFile(outFullName,"w",zipfile.ZIP_DEFLATED) + for path,dirnames,filenames in os.walk(dirpath): + # 去掉目标跟路径，只对目标文件夹下边的文件及文件夹进行压缩 + fpath = path.replace(dirpath,'') + + for filename in filenames: + zip.write(os.path.join(path,filename),os.path.join(fpath,filename)) + zip.close() + +def recreate_release_dir(dir): + if os.path.exists(dir): + shutil.rmtree(dir)#删除再建立 + os.makedirs(dir) + else: + os.makedirs(dir) + +def boot2_release(cmd, ver): + output,err = subprocess.Popen(cmd[0] + r' CONFIG_BOOT2_VER=' + ver,stdout=subprocess.PIPE,shell=True).communicate() + if err==None: + print(output) + else: + print("Build error") + sys.exit() + + for root, dirs, files in os.walk(".", topdown=False): + for file in files: + if file.endswith(".bin"): + if cmd[1] in file: + binfile = os.path.join(root, file) + print(binfile) + print('boot2_isp_' + cmd[1] + '_v' + ver + "/" + 'boot2_isp_' + cmd[2] + ".bin") + shutil.copy(binfile, 'boot2_isp_' + cmd[1] + '_v' + ver + "/" + 'boot2_isp' + ".bin") + + + +def get_release_ver(): + + print("get release ver") + output,err = subprocess.Popen(git_cmd,stdout=subprocess.PIPE,shell=True).communicate() + if err==None: + release_name = bytes.decode(output) + release_name = release_name.rstrip() + + + if(len(release_name) != len(tag_standard)): + print("ver len err, workspace may dirty? or has no tag?") + print("release failed!") + sys.exit() + release_name = release_name[7:12] + return release_name + + else: + print("get ver error,please push correct tag") + sys.exit() + + + +if __name__ == '__main__' : + + ver = get_release_ver() + print(ver) + + for x in release_list: + recreate_release_dir('boot2_isp_' + x[1] + '_v' + ver ) + for x in release_list: + boot2_release(x,ver) + print("release suss") \ No newline at end of file diff --git a/examples/boot2_isp/main.c b/examples/boot2_isp/main.c index 5d1d8a28..2d6158b0 100644 --- a/examples/boot2_isp/main.c +++ b/examples/boot2_isp/main.c @@ -40,7 +40,6 @@ #include "blsp_media_boot.h" #include "blsp_boot_decompress.h" #include "blsp_common.h" -#include "blsp_version.h" #include "partition.h" #include "softcrc.h" #include "bflb_flash.h" @@ -400,7 +399,7 @@ int main(void) LOG_F("BLSP Boot2 start:%s,%s\r\n", __DATE__, __TIME__); LOG_F("Group=%d,CPU Count=%d\r\n", BLSP_BOOT2_CPU_GROUP_MAX, BLSP_BOOT2_CPU_MAX); - LOG_F("ver:%s\r\n", BL_SDK_VER); + LOG_F("ver:%s\r\n", BFLB_BOOT2_VER); /* Reset Sec_Eng */ hal_boot2_reset_sec_eng(); diff --git a/examples/boot2_isp/partition.c b/examples/boot2_isp/partition.c index 38b6f235..2f57a470 100644 --- a/examples/boot2_isp/partition.c +++ b/examples/boot2_isp/partition.c @@ -210,7 +210,7 @@ pt_table_error_type pt_table_get_active_entries_by_id(pt_table_stuff_config *pt_ for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) { if (pt_stuff->pt_entries[i].type == type) { - ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); + arch_memcpy_fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); return PT_ERROR_SUCCESS; } } @@ -242,7 +242,7 @@ pt_table_error_type pt_table_get_active_entries_by_name(pt_table_stuff_config *p for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) { if (strlen((char *)pt_stuff->pt_entries[i].name) == len && memcmp((char *)pt_stuff->pt_entries[i].name, (char *)name, len) == 0) { - ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); + arch_memcpy_fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); return PT_ERROR_SUCCESS; } } @@ -291,7 +291,7 @@ pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id, for (i = 0; i < pt_table->entryCnt; i++) { if (pt_entries[i].type == pt_entry->type) { - ARCH_MemCpy_Fast(&pt_entries[i], pt_entry, sizeof(pt_table_entry_config)); + arch_memcpy_fast(&pt_entries[i], pt_entry, sizeof(pt_table_entry_config)); break; } } @@ -299,7 +299,7 @@ pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id, if (i == pt_table->entryCnt) { /* Not found this entry ,add new one */ if (pt_table->entryCnt < PT_ENTRY_MAX) { - ARCH_MemCpy_Fast(&pt_entries[pt_table->entryCnt], pt_entry, sizeof(pt_table_entry_config)); + arch_memcpy_fast(&pt_entries[pt_table->entryCnt], pt_entry, sizeof(pt_table_entry_config)); pt_table->entryCnt++; } else { return PT_ERROR_ENTRY_UPDATE_FAIL; @@ -491,7 +491,7 @@ pt_table_error_type pt_table_set_iap_para(pt_table_iap_param_type *para) gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff, sizeof(pt_table_stuff_config)); } - ARCH_MemCpy_Fast((void *)&pt_stuff_write, (void *)&pt_stuff, sizeof(pt_table_stuff_config)); + arch_memcpy_fast((void *)&pt_stuff_write, (void *)&pt_stuff, sizeof(pt_table_stuff_config)); pt_stuff_write.pt_table.age += 1; pt_stuff_write.pt_entries[0].active_index = !(pt_stuff_write.pt_entries[0].active_index & 0x01); pt_stuff_write.pt_table.crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_stuff_write, sizeof(pt_table_config) - 4); diff --git a/examples/boot2_isp/partition.h b/examples/boot2_isp/partition.h index 0d832d02..79092888 100644 --- a/examples/boot2_isp/partition.h +++ b/examples/boot2_isp/partition.h @@ -37,7 +37,7 @@ #define __PARTITION_H__ #include "blsp_port.h" -#include "bl616_common.h" +#include "bflb_port_boot2.h" /** @addtogroup BFLB_Common_Driver * @{ diff --git a/examples/boot2_isp/port/bl602/bflb_port_boot2.c b/examples/boot2_isp/port/bl602/bflb_port_boot2.c new file mode 100644 index 00000000..6e4c8dad --- /dev/null +++ b/examples/boot2_isp/port/bl602/bflb_port_boot2.c @@ -0,0 +1,563 @@ +#include "bflb_port_boot2.h" +#include "bflb_flash.h" +#include "bl602_glb.h" +#include "bl602_ef_ctrl.h" +#include "bl602_hbn.h" +#include "bl602_xip_sflash.h" +#include "bl602_sf_cfg.h" +#include "bl602_sf_cfg_ext.h" +#include "bl602_glb.h" +#include "bl602_xip_sflash_ext.h" +#include "bl602_clock.h" +#include "softcrc.h" +#include "bflb_gpio.h" +#include "bflb_common.h" +#include "bflb_efuse.h" +#include "tzc_sec_reg.h" + +/****************************************************************************/ /** + * @brief clear mtimer + * + * @param None + * + * @return None + * +*******************************************************************************/ +static void hal_boot2_mtimer_clear_time() +{ + *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME) = 0; + *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4) = 0; +} + +/****************************************************************************/ /** + * @brief init clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_init_clock(void) +{ + hal_boot2_mtimer_clear_time(); + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK) / 1000 / 1000 - 1); + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_160M, 3); +} + +/****************************************************************************/ /** + * @brief hal_boot2_custom + * + * @param custom_param + * + * @return 0 + * +*******************************************************************************/ +uint32_t hal_boot2_custom(void *custom_param) +{ + uint32_t sw_cfg, flash_pin_cfg; + bflb_efuse_read_sw_usage(0, (uint32_t *)&sw_cfg); + /* flash_pin_cfg + * 0:internal flash with io switch, + * 1:internal flash no io switch, + * 2:GPIO 17-22 + * 3:GPIO 0-2 & 20-22 + */ + flash_pin_cfg = ((sw_cfg >> 16) & 0x3); + if ((flash_pin_cfg == 0) || (flash_pin_cfg == 1)) { + struct bflb_device_s *gpio = bflb_device_get_by_name("gpio"); + bflb_gpio_init(gpio, GPIO_PIN_20, GPIO_OUTPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_0); + bflb_gpio_reset(gpio, GPIO_PIN_20); + } + return 0; +} + +/****************************************************************************/ /** + * @brief hal_boot2_get_efuse_cfg + * + * @param efuse_cfg + * + * @return None + * +*******************************************************************************/ +void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg) +{ + uint32_t tmp; + uint32_t rootClk; + uint8_t hdiv = 0, bdiv = 0; + + /* save bclk fclk div and root clock sel */ + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); + rootClk = BL_RD_REG(HBN_BASE, HBN_GLB); + + /* change root clock to rc32m for efuse operation */ + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M); + + /* Get sign and aes type*/ + //EF_Ctrl_Read_Secure_Boot((EF_Ctrl_Sign_Type *)efuse_cfg->sign, (EF_Ctrl_SF_AES_Type *)efuse_cfg->encrypted); + bflb_efuse_read_secure_boot((EF_Ctrl_Sign_Type *)efuse_cfg->sign, (EF_Ctrl_SF_AES_Type *)efuse_cfg->encrypted); + /* Get hash:aes key slot 0 and slot1*/ + //EF_Ctrl_Read_AES_Key(0, (uint32_t *)efuse_cfg->pk_hash_cpu0, 8); + bflb_efuse_read_aes_key(0, (uint8_t *)efuse_cfg->pk_hash_cpu0, 8); + //EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id); + bflb_efuse_get_chipid(efuse_cfg->chip_id); + /* Get HBN check sign config */ + //EF_Ctrl_Read_Sw_Usage(0, &tmp); + bflb_efuse_read_sw_usage(0, &tmp); + efuse_cfg->hbn_check_sign = (tmp >> 22) & 0x01; + + /* restore bclk fclk div and root clock sel */ + GLB_Set_System_CLK_Div(hdiv, bdiv); + BL_WR_REG(HBN_BASE, HBN_GLB, rootClk); + __NOP(); + __NOP(); + __NOP(); + __NOP(); +} + +/****************************************************************************/ /** + * @brief reset sec eng clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_reset_sec_eng(void) +{ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SEC); + GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_PLL120M); +} + +/****************************************************************************/ /** + * @brief system soft reset + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_sw_system_reset(void) +{ + GLB_SW_System_Reset(); +} + +/****************************************************************************/ /** + * @brief hal_boot2_set_psmode_status + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_set_psmode_status(uint32_t flag) +{ + HBN_Set_Status_Flag(flag); +} + +/****************************************************************************/ /** + * @brief hal_boot2_get_psmode_status + * + * @param None + * + * @return status flag + * +*******************************************************************************/ +uint32_t hal_boot2_get_psmode_status(void) +{ + return HBN_Get_Status_Flag(); +} + +/****************************************************************************/ /** + * @brief hal_boot2_get_user_fw + * + * @param None + * + * @return None + * +*******************************************************************************/ +uint32_t hal_boot2_get_user_fw(void) +{ + return BL_RD_WORD(HBN_BASE + HBN_RSV0_OFFSET); +} + +/****************************************************************************/ /** + * @brief hal_boot2_clr_user_fw + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_clr_user_fw(void) +{ + uint32_t *p = (uint32_t *)(HBN_BASE + HBN_RSV0_OFFSET); + *p = 0; +} + +/****************************************************************************/ /** + * @brief hal_boot2_sboot_finish + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION hal_boot2_sboot_finish(void) +{ + uint32_t tmp_val; + + tmp_val = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TZC_SEC_TZC_SBOOT_DONE, 0xf); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmp_val); +} + +/****************************************************************************/ /** + * @brief uart gpio init + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_uart_gpio_init(void) +{ + GLB_GPIO_Type gpios[] = { GLB_GPIO_PIN_7, GLB_GPIO_PIN_16 }; + + GLB_GPIO_Func_Init(GPIO_FUN_UART, gpios, 2); + + GLB_UART_Fun_Sel((GLB_GPIO_PIN_7 % 8), GLB_UART_SIG_FUN_UART0_RXD); + GLB_UART_Fun_Sel((GLB_GPIO_PIN_16 % 8), GLB_UART_SIG_FUN_UART0_TXD); +} + +/****************************************************************************/ /** + * @brief uart gpio init + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_debug_uart_gpio_init(void) +{ + GLB_GPIO_Type gpios[] = { GLB_GPIO_PIN_8 }; + + GLB_GPIO_Func_Init(GPIO_FUN_UART, gpios, 1); + + GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_GPIO8_GPIO15); + GLB_UART_Fun_Sel(GLB_UART_SIG_4, GLB_UART_SIG_FUN_UART1_TXD); +} + +/****************************************************************************/ /** + * @brief usb init + * + * @param None + * + * @return None + * +*******************************************************************************/ +#if HAL_BOOT2_SUPPORT_USB_IAP +void hal_boot2_debug_usb_port_init(void) +{ +} +#endif + +/****************************************************************************/ /** + * @brief uart deinit + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_debug_uart_gpio_deinit(void) +{ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0); + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1); + GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); +} + +/****************************************************************************/ /** + * @brief Check bootheader crc + * + * @param data: bootheader data pointer + * + * @return boot_error_code type + * +*******************************************************************************/ +static uint32_t hal_boot_check_bootheader(struct hal_bootheader_t *header) +{ + uint32_t crc_pass = 0; + uint32_t crc; + + if (header->bootCfg.bval.crcIgnore == 1 && header->crc32 == HAL_BOOT2_DEADBEEF_VAL) { + //MSG("Crc ignored\r\n"); + crc_pass = 1; + } else { + crc = BFLB_Soft_CRC32((uint8_t *)header, sizeof(struct hal_bootheader_t) - sizeof(header->crc32)); + + if (header->crc32 == crc) { + crc_pass = 1; + } + } + return crc_pass; +} + +/****************************************************************************/ /** + * @brief Check if the input public key is the same as burned in the efuse + * + * @param g_boot_img_cfg: Boot image config pointer + * @param data: Image data pointer + * + * @return boot_error_code type + * +*******************************************************************************/ +int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data) +{ + struct hal_bootheader_t *header = (struct hal_bootheader_t *)data; + uint32_t crc_pass = 0; + uint32_t i = 0; + uint32_t *phash = (uint32_t *)header->hash; + + crc_pass = hal_boot_check_bootheader(header); + + if (!crc_pass) { + //MSG_ERR("bootheader crc error\r\n"); + //blsp_dump_data((uint8_t *)&crc, 4); + return 0x0204; + } + + if (header->bootCfg.bval.notLoadInBoot) { + return 0x0202; + } + + /* Get which CPU's img it is*/ + for (i = 0; i < HAL_BOOT2_CPU_MAX; i++) { + if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU0_MAGIC, + sizeof(header->magicCode))) { + break; + } else if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU1_MAGIC, + sizeof(header->magicCode))) { + break; + } + } + + if (i == HAL_BOOT2_CPU_MAX) { + /* No cpu img magic match */ + //MSG_ERR("Magic code error\r\n"); + return 0x0203; + } + + if (boot_img_cfg == NULL) { + return 0; + } + + boot_img_cfg->pk_src = i; + boot_img_cfg->img_valid = 0; + + /* Deal with pll config */ + + /* Encrypt and sign */ + boot_img_cfg->basic_cfg.encrypt_type = header->bootCfg.bval.encrypt_type; + boot_img_cfg->basic_cfg.sign_type = header->bootCfg.bval.sign; + boot_img_cfg->basic_cfg.key_sel = header->bootCfg.bval.key_sel; + + /* Xip relative */ + boot_img_cfg->basic_cfg.no_segment = header->bootCfg.bval.no_segment; + boot_img_cfg->cpu_cfg[0].cache_enable = header->bootCfg.bval.cache_enable; + boot_img_cfg->basic_cfg.aes_region_lock = header->bootCfg.bval.aes_region_lock; + //boot_img_cfg->cpu_cfg[1].halt_cpu = header->bootCfg.bval.halt_cpu1; + boot_img_cfg->cpu_cfg[0].cache_way_dis = header->bootCfg.bval.cache_way_disable; + boot_img_cfg->basic_cfg.hash_ignore = header->bootCfg.bval.hash_ignore; + /* Firmware len*/ + boot_img_cfg->basic_cfg.img_len_cnt = header->img_segment_info.img_len; + + /* Boot entry and flash offset */ + boot_img_cfg->cpu_cfg[0].boot_entry = header->bootEntry; + boot_img_cfg->basic_cfg.group_image_offset = header->img_start.flash_offset; + + boot_img_cfg->cpu_cfg[0].config_enable = 1; + boot_img_cfg->cpu_cfg[0].halt_cpu = 0; + + //MSG("sign %d,encrypt:%d\r\n", boot_img_cfg->sign_type,boot_img_cfg->encrypt_type); + + /* Check encrypt and sign match*/ + if (g_efuse_cfg.encrypted[i] != 0) { + if (boot_img_cfg->basic_cfg.encrypt_type == 0) { + //MSG_ERR("Encrypt not fit\r\n"); + return 0x0205; + } + } + + if (g_efuse_cfg.sign[i] != boot_img_cfg->basic_cfg.sign_type) { + //MSG_ERR("sign not fit\r\n"); + boot_img_cfg->basic_cfg.sign_type = g_efuse_cfg.sign[i]; + return 0x0206; + } + + if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) { + /* In HBN Mode, if user select to ignore hash and sign*/ + boot_img_cfg->basic_cfg.hash_ignore = 1; + } else if ((boot_img_cfg->basic_cfg.hash_ignore == 1 && *phash != HAL_BOOT2_DEADBEEF_VAL) || + g_efuse_cfg.sign[i] != 0) { + /* If signed or user not really want to ignore, hash can't be ignored*/ + boot_img_cfg->basic_cfg.hash_ignore = 0; + } + + if (g_user_hash_ignored) { + boot_img_cfg->basic_cfg.hash_ignore = 1; + } + + arch_memcpy_fast(boot_img_cfg->basic_cfg.hash, header->hash, sizeof(header->hash)); + + if (boot_img_cfg->basic_cfg.img_len_cnt == 0) { + return 0x0207; + } + + return 0; +} + +/****************************************************************************/ /** + * @brief clean cache + * + * @param + * + * @return cache set result + * +*******************************************************************************/ +void ATTR_TCM_SECTION hal_boot2_clean_cache(void) +{ + /* no need clean again since hal_boot2_set_cache will also clean + unused way,and bl602 no data cache */ +} + +/****************************************************************************/ /** + * @brief set cache + * + * @param cont_read: continue read mode + * boot_img_cfg: cache set param + * + * @return cache set result + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg) +{ + return bflb_flash_set_cache(cont_read, boot_img_cfg->cpu_cfg[0].cache_enable, + boot_img_cfg->cpu_cfg[0].cache_way_dis, + boot_img_cfg->basic_cfg.group_image_offset); +} + +/****************************************************************************/ /** + * @brief get the ram image name and count + * + * @param img_name: ram image name in partition + * @param ram_img_cnt: ram image count that support boot from flash + * + * @return None + * +*******************************************************************************/ +void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt) +{ + *ram_img_cnt = 0; +} + +/****************************************************************************/ /** + * @brief get the ram image info + * + * @param data: bootheader information + * @param image_offset: ram image offset in flash(from of bootheader) + * @param img_len: ram image length + * @param hash: pointer to hash pointer + * + * @return None + * +*******************************************************************************/ +void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash) +{ + *img_len = 0; +} + +/****************************************************************************/ /** + * @brief release other cpu to boot up + * + * @param core: core number + * @param boot_addr: boot address + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr) +{ +} + +/****************************************************************************/ /** + * @brief get xip address according to flash addr + * + * @param flash_addr: flash address + * + * @return XIP Address + * +*******************************************************************************/ +uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr) +{ + uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(); + if (flash_addr >= img_offset) { + return BL602_FLASH_XIP_BASE + (flash_addr - img_offset); + } else { + return 0; + } +} + +/****************************************************************************/ /** + * @brief get multi-group count + * + * @param None + * + * @return 1 for multi-group 0 for not + * +*******************************************************************************/ +uint32_t hal_boot2_get_grp_count(void) +{ + return 1; +} + +/****************************************************************************/ /** + * @brief get cpu count + * + * @param None + * + * @return 1 for multi-group 0 for not + * +*******************************************************************************/ +uint32_t hal_boot2_get_cpu_count(void) +{ + return 1; +} + +/****************************************************************************/ /** + * @brief get cpu count + * + * @param None + * + * @return 1 for multi-group 0 for not + * +*******************************************************************************/ +uint32_t ATTR_TCM_SECTION hal_boot2_get_feature_flag(void) +{ + return HAL_BOOT2_SP_FLAG; +} + +/****************************************************************************/ /** + * @brief get boot header offset + * + * @param None + * + * @return bootheader offset + * +*******************************************************************************/ +uint32_t hal_boot2_get_bootheader_offset(void) +{ + return 0x00; +} diff --git a/examples/boot2_isp/port/bl602/bflb_port_boot2.h b/examples/boot2_isp/port/bl602/bflb_port_boot2.h new file mode 100644 index 00000000..b1e64dc2 --- /dev/null +++ b/examples/boot2_isp/port/bl602/bflb_port_boot2.h @@ -0,0 +1,273 @@ +/** + * ***************************************************************************** + * @file bflb_port_boot2.h + * @version 0.1 + * @date 2022-12-12 + * @brief + * ***************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#ifndef __BFLB_PORT_BOOT2_H__ +#define __BFLB_PORT_BOOT2_H__ + +#include "bl602_sflash.h" +#include "bl602_glb.h" + +#define BL_TCM_BASE BL602_TCM_BASE +#define BL_SYS_CLK_PLL GLB_SYS_CLK_PLL160M +#define BL_SFLASH_CLK GLB_SFLASH_CLK_80M +#define HAL_PLL_CFG_MAGICCODE "PCFG" + +#define HAL_BOOT2_PK_HASH_SIZE 256 / 8 +#define HAL_BOOT2_IMG_HASH_SIZE 256 / 8 +#define HAL_BOOT2_ECC_KEYXSIZE 256 / 8 +#define HAL_BOOT2_ECC_KEYYSIZE 256 / 8 +#define HAL_BOOT2_SIGN_MAXSIZE (2048 / 8) +#define HAL_BOOT2_DEADBEEF_VAL 0xdeadbeef +#define HAL_BOOT2_CPU0_MAGIC "BFNP" +#define HAL_BOOT2_CPU1_MAGIC "BFAP" +#define HAL_BOOT2_CP_FLAG 0x02 +#define HAL_BOOT2_MP_FLAG 0x01 +#define HAL_BOOT2_SP_FLAG 0x00 + +#define HAL_BOOT2_SUPPORT_DECOMPRESS 1 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_USB_IAP 0 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM 1 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 0 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_SIGN_ENCRYPT 1 /* 1 support sign and encrypt, 0 not support */ + +#define HAL_BOOT2_CPU_GROUP_MAX 1 +#define HAL_BOOT2_CPU_MAX 1 +#define HAL_BOOT2_RAM_IMG_COUNT_MAX 0 + +#define HAL_BOOT2_FW_IMG_OFFSET_AFTER_HEADER 4 * 1024 +#define HAL_BOOT2_MFG_START_REQUEST_OFFSET 188 * 1024 + +#define CLIC_CTRL_ADDR 0x02000000UL +#define CLIC_HART0_ADDR 0x02800000UL + +#define CLIC_MSIP 0x0000 +#define CLIC_MSIP_size 0x4 +#define CLIC_MTIMECMP 0x4000 +#define CLIC_MTIMECMP_size 0x8 +#define CLIC_MTIME 0xBFF8 +#define CLIC_MTIME_size 0x8 + +#define CLIC_INTIP 0x000 +#define CLIC_INTIE 0x400 +#define CLIC_INTCFG 0x800 +#define CLIC_CFG 0xc00 + +typedef struct +{ + uint32_t encrypted[HAL_BOOT2_CPU_GROUP_MAX]; + uint32_t sign[HAL_BOOT2_CPU_GROUP_MAX]; + uint8_t hbn_check_sign; + uint8_t rsvd[1]; + uint8_t chip_id[8]; + uint32_t pk_hash_cpu0[HAL_BOOT2_PK_HASH_SIZE / 4]; + uint32_t pk_hash_cpu1[HAL_BOOT2_PK_HASH_SIZE / 4]; + uint8_t uart_download_cfg; + uint8_t sf_pin_cfg; + uint8_t keep_dbg_port_closed; + uint8_t boot_pin_cfg; +} boot2_efuse_hw_config; + +struct __attribute__((packed, aligned(4))) hal_flash_config { + uint32_t magicCode; /*'FCFG'*/ + SPI_Flash_Cfg_Type cfg; + uint32_t crc32; +}; + +typedef struct +{ + uint8_t xtal_type; + uint8_t pll_clk; + uint8_t hclk_div; + uint8_t bclk_div; + + uint8_t flash_clk_type; + uint8_t flash_clk_div; + uint8_t rsvd[2]; +} hal_sys_clk_config; + +typedef struct +{ + uint32_t magicCode; /*'PCFG'*/ + hal_sys_clk_config cfg; + uint32_t crc32; +} hal_pll_config; + +struct __attribute__((packed, aligned(4))) hal_basic_cfg_t { + uint32_t sign_type : 2; /* [1: 0] for sign */ + uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ + uint32_t key_sel : 2; /* [5: 4] key slot */ + uint32_t xts_mode : 1; /* [6] for xts mode */ + uint32_t aes_region_lock : 1; /* [7] rsvd */ + uint32_t no_segment : 1; /* [8] no segment info */ + uint32_t boot2_enable : 1; /* [9] boot2 enable */ + uint32_t boot2_rollback : 1; /* [10] boot2 rollback */ + uint32_t cpu_master_id : 4; /* [14: 11] master id */ + uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */ + uint32_t crc_ignore : 1; /* [16] ignore crc */ + uint32_t hash_ignore : 1; /* [17] hash ignore */ + uint32_t power_on_mm : 1; /* [18] power on mm */ + uint32_t em_sel : 3; /* [21: 19] em_sel */ + uint32_t cmds_en : 1; /* [22] command spliter enable */ + uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */ + uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */ + uint32_t icache_invalid : 1; /* [29] icache invalid */ + uint32_t dcache_invalid : 1; /* [30] dcache invalid */ + uint32_t fpga_halt_release : 1; /* [31] FPGA halt release function */ + + uint32_t group_image_offset; /* flash controller offset */ + uint32_t aes_region_len; /* aes region length */ + + uint32_t img_len_cnt; /* image length or segment count */ + uint32_t hash[8]; /* hash of the image */ +}; + +struct __attribute__((packed, aligned(4))) hal_cpu_cfg_t { + uint8_t config_enable; /* coinfig this cpu */ + uint8_t halt_cpu; /* halt this cpu */ + uint8_t cache_enable : 1; /* cache setting */ + uint8_t cache_wa : 1; /* cache setting */ + uint8_t cache_wb : 1; /* cache setting */ + uint8_t cache_wt : 1; /* cache setting */ + uint8_t cache_way_dis : 4; /* cache setting */ + uint8_t rsvd; + + uint32_t image_address_offset; /* image address on flash */ + uint32_t boot_entry; /* entry point of the m0 image */ + uint32_t msp_val; /* msp value */ +}; + +struct hal_bootheader_t { + uint32_t magicCode; /*'BFXP'*/ + uint32_t rivison; + struct hal_flash_config flash_cfg; + hal_pll_config clk_cfg; + __PACKED_UNION + { + __PACKED_STRUCT + { + uint32_t sign : 2; /* [1: 0] for sign*/ + uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ + uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface*/ + uint32_t rsvd6_7 : 2; /* [7: 6] for encrypt*/ + uint32_t no_segment : 1; /* [8] no segment info */ + uint32_t cache_enable : 1; /* [9] for cache */ + uint32_t notLoadInBoot : 1; /* [10] not load this img in bootrom */ + uint32_t aes_region_lock : 1; /* [11] aes region lock */ + uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info*/ + uint32_t crcIgnore : 1; /* [16] ignore crc */ + uint32_t hash_ignore : 1; /* [17] hash crc */ + uint32_t halt_cpu1 : 1; /* [18] halt ap */ + uint32_t rsvd19_31 : 13; /* [31:19] rsvd */ + } + bval; + uint32_t wval; + } + bootCfg; + + __PACKED_UNION + { + uint32_t segment_cnt; + uint32_t img_len; + } + img_segment_info; + + uint32_t bootEntry; /* entry point of the image*/ + __PACKED_UNION + { + uint32_t ram_addr; + uint32_t flash_offset; + } + img_start; + + uint8_t hash[HAL_BOOT2_IMG_HASH_SIZE]; /*hash of the image*/ + + uint32_t rsv1; + uint32_t rsv2; + uint32_t crc32; +}; + +typedef struct +{ + uint8_t img_valid; + uint8_t pk_src; + uint8_t rsvd[2]; + + struct hal_basic_cfg_t basic_cfg; + + struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX]; + + uint8_t aes_iv[16 + 4]; //iv in boot header + + uint8_t eckye_x[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header + uint8_t eckey_y[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header + uint8_t eckey_x2[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header + uint8_t eckey_y2[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header + + uint8_t signature[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header + uint8_t signature2[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header + +} boot2_image_config; + +extern boot2_efuse_hw_config g_efuse_cfg; +extern uint8_t g_ps_mode; +extern uint32_t g_user_hash_ignored; +extern struct device *dev_check_hash; + +void hal_boot2_init_clock(void); +uint32_t hal_boot2_custom(void *custom_param); +void hal_boot2_reset_sec_eng(void); +void hal_boot2_sw_system_reset(void); +void hal_boot2_set_psmode_status(uint32_t flag); +uint32_t hal_boot2_get_psmode_status(void); +uint32_t hal_boot2_get_user_fw(void); +void hal_boot2_clr_user_fw(void); +void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg); +int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg); +void hal_boot2_sboot_finish(void); +void hal_boot2_uart_gpio_init(void); +void hal_boot2_debug_uart_gpio_init(void); +void hal_boot2_debug_uart_gpio_deinit(void); +int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data); +void hal_boot2_clean_cache(void); +BL_Err_Type hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg); +void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt); +void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash); +void hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr); +uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr); +uint32_t hal_boot2_get_grp_count(void); +uint32_t hal_boot2_get_cpu_count(void); +uint32_t hal_boot2_get_feature_flag(void); +uint32_t hal_boot2_get_bootheader_offset(void); +#endif diff --git a/examples/boot2_isp/port/bl602/blsp_boot2_iap_flash.ld b/examples/boot2_isp/port/bl602/blsp_boot2_iap_flash.ld new file mode 100644 index 00000000..ebf5d3d3 --- /dev/null +++ b/examples/boot2_isp/port/bl602/blsp_boot2_iap_flash.ld @@ -0,0 +1,201 @@ +/**************************************************************************************** +* @file map.txt +* +* @brief This file is the map file (gnuarm or armgcc). +* +* Copyright (C) BouffaloLab 2018 +* +**************************************************************************************** +*/ + +/* configure the CPU type */ +OUTPUT_ARCH( "riscv" ) +/* link with the standard c library */ +INPUT(-lc) +/* link with the standard GCC library */ +INPUT(-lgcc) +/* configure the entry point */ +ENTRY(__start) + +StackSize = 0x1000; /* 4KB */ +HeapSize = 0x0; /* 0KB */ +PROVIDE(__boot2_pass_param_addr = 0x42049C00);/* 0x42030000+103*1024 */ +MEMORY +{ + xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 48K + itcm_memory (rx) : ORIGIN = 0x2201c000, LENGTH = 16K + dtcm_memory (rx) : ORIGIN = 0x42020000, LENGTH = 4K + ram_memory (!rx) : ORIGIN = 0x42021000, LENGTH = 156K +} + +SECTIONS +{ + PROVIDE(__metal_chicken_bit = 0); + + .text : + { + . = ALIGN(4); + __text_code_start__ = .; + + KEEP (*(SORT_NONE(.init))) + KEEP (*(SORT_NONE(.vector))) + + KEEP (*(.text.metal.init.enter)) + + *(EXCLUDE_FILE ( *bl602_uart*.o* *hal_uart*.o* ) .text*) + + *(.rodata) + *(.rodata.*) + *(.srodata) + *(.srodata.*) + + . = ALIGN(4); + __text_code_end__ = .; + } > xip_memory + + . = ALIGN(4); + __itcm_load_addr = .; + + .itcm_region : AT (__itcm_load_addr) + { + . = ALIGN(4); + __tcm_code_start__ = .; + *(.tcm_code.*) + *(.tcm_const.*) + *(.sclock_rlt_code.*) + *(.sclock_rlt_const.*) + *bl602_romapi*.o*(.text) + *bl602_romapi*.o*(.text.*) + *bl602_romapi*.o*(.rodata) + *bl602_romapi*.o*(.rodata.*) + *bl602_romapi*.o*(.srodata) + *bl602_romapi*.o*(.srodata.*) + *bl602_uart*.o* (.text*) + *hal_uart*.o* (.text*) + . = ALIGN(4); + __tcm_code_end__ = .; + + } > itcm_memory + + __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .dtcm_region : AT (__dtcm_load_addr) + { + . = ALIGN(4); + __tcm_data_start__ = .; + + *(.tcm_data.*) + /* *finger_print.o(.data*) */ + + . = ALIGN(4); + __tcm_data_end__ = .; + } > dtcm_memory + + /* .heap_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of heap sections, and assign + * values to heap symbols later */ + .heap_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + HeapSize; + . = ALIGN(0x4); + } > dtcm_memory + + __HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize; + __HeapSize = HeapSize; + __HeapLimit = __HeapBase + __HeapSize; + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__HeapBase >= __tcm_data_end__, "region RAM overflowed with stack") + + /*************************************************************************/ + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + StackSize; + . = ALIGN(0x4); + } > dtcm_memory + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + + __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + + .system_ram_data_region : AT (__system_ram_load_addr) + { + . = ALIGN(4); + __system_ram_data_start__ = .; + + *(.system_ram) + + . = ALIGN(4); + __system_ram_data_end__ = .; + } > ram_memory + + __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); + + /* Data section */ + RAM_DATA : AT (__ram_load_addr) + { + . = ALIGN(4); + __ram_data_start__ = .; + + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.sdata2) + *(.sdata2.*) + + . = ALIGN(4); + __ram_data_end__ = .; + } > ram_memory + + .bss (NOLOAD) :AT(__bss_start__) + { + . = ALIGN(4); + __bss_start__ = .; + + *(.bss*) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > ram_memory + + .noinit_data (NOLOAD) :AT(__noinit_data_start__) + { + . = ALIGN(4); + __noinit_data_start__ = .; + + *(.noinit_data*) + + . = ALIGN(4); + __noinit_data_end__ = .; + } > ram_memory + + .nocache_noinit_ram_region (NOLOAD) : AT(__nocache_ram_data_start__) + { + . = ALIGN(4); + __nocache_ram_data_start__ = .; + + *(.nocache_noinit_ram) + + . = ALIGN(4); + __nocache_ram_data_end__ = .; + } > ram_memory + + +} + diff --git a/examples/boot2_isp/port/bl606p/bflb_port_boot2.c b/examples/boot2_isp/port/bl606p/bflb_port_boot2.c new file mode 100644 index 00000000..ef6405c8 --- /dev/null +++ b/examples/boot2_isp/port/bl606p/bflb_port_boot2.c @@ -0,0 +1,944 @@ +#include "bflb_port_boot2.h" +#include "bflb_flash.h" +#include "bl606p_ef_ctrl.h" +#include "bl606p_ef_cfg.h" +#include "bl606p_hbn.h" +#include "bl606p_glb.h" +#include "bl606p_pds.h" +#include "bl606p_xip_sflash.h" +#include "bl606p_tzc_sec.h" +#include "bflb_gpio.h" +#include "softcrc.h" +#include "bl606p_psram.h" +#include "bflb_efuse.h" +#include "ef_data_0_reg.h" +#include "log.h" + +/****************************************************************************/ /** + * @brief init clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_init_clock(void) +{ + CPU_Reset_MTimer(); + /* set mtimer clock 1M */ + CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000000 - 1); + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0); +} + +/****************************************************************************/ /** + * @brief init psram gpio + * + * @param None + * + * @return None + * +*******************************************************************************/ +static void hal_boot2_init_psram_gpio(void) +{ + + struct bflb_device_s *gpio = bflb_device_get_by_name("gpio"); + for (uint8_t i = 0; i < 12; i++) { + bflb_gpio_init(gpio, 52 + i, GPIO_INPUT | GPIO_PULL_NONE | GPIO_SMT_EN | GPIO_DRV_0); + } +} + +/****************************************************************************/ /** + * @brief init psram data queue strobe clock + * + * @param burst_len: burst length + * is_fixLatency: fixedLatency or not + * latency: clocks latency + * dqs_delay: data queue strobe clock delay + * + * @return reg id0 value + * +*******************************************************************************/ +static uint16_t hal_boot2_psram_winbond_init_dqs(int8_t burst_len, uint8_t is_fixLatency, uint8_t latency, uint16_t dqs_delay) +{ + uint16_t reg_read = 0; + PSRAM_Ctrl_Cfg_Type psramCtrlCfg = { + .vendor = PSRAM_CTRL_VENDOR_WINBOND, + .ioMode = PSRAM_CTRL_X8_MODE, + .size = PSRAM_SIZE_32MB, + .dqs_delay = 0xffc0, + }; + + PSRAM_Winbond_Cfg_Type winbondCfg = { + .rst = DISABLE, + .clockType = PSRAM_CLOCK_DIFF, + .inputPowerDownMode = DISABLE, + .hybridSleepMode = DISABLE, + .linear_dis = ENABLE, + .PASR = PSRAM_PARTIAL_REFRESH_FULL, + .disDeepPowerDownMode = ENABLE, + .fixedLatency = DISABLE, + .brustLen = PSRAM_WINBOND_BURST_LENGTH_64_BYTES, + .brustType = PSRAM_WRAPPED_BURST, + .latency = PSRAM_WINBOND_6_CLOCKS_LATENCY, + .driveStrength = PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M, + }; + + winbondCfg.brustLen = burst_len; + winbondCfg.fixedLatency = is_fixLatency; + winbondCfg.latency = latency; + + psramCtrlCfg.dqs_delay = dqs_delay; + PSram_Ctrl_Init(PSRAM0_ID, &psramCtrlCfg); + /*PSram_Ctrl_Winbond_Reset(PSRAM0_ID); */ /*Different psram there are differences, in order to unify the change to not configured*/ + if (0 != PSram_Ctrl_Winbond_Write_Reg(PSRAM0_ID, PSRAM_WINBOND_REG_CR0, &winbondCfg)) { + pm_pds_mode_enter(7, 32768 * 2 /*2s*/); + } + + if (0 != PSram_Ctrl_Winbond_Read_Reg(PSRAM0_ID, PSRAM_WINBOND_REG_ID0, ®_read)) { + pm_pds_mode_enter(7, 32768 * 2 /*2s*/); + } + return reg_read; +} + +#define PSRAM_BASIC_ADDR (0x54000000) +#define TEST_MEMORY_SIZE (1 * 1024 * 1024) + +/****************************************************************************/ /** + * @brief psram read write check + * + * @param None + * + * @return Suss or Error + * +*******************************************************************************/ +uint8_t hal_boot2_psram_rw_check(void) +{ + uint32_t i = 0; + uint32_t test_pattern_val[] = { + 0xaa55aa55, + 0x33cc33cc, + 0x55aa55aa, + 0xcc33cc33, + }; + volatile uint32_t *p = (uint32_t *)PSRAM_BASIC_ADDR; + volatile uint32_t q = 0; + + p[0] = 0xaa55aa55; + p[1] = 0x33cc33cc; + p[2] = 0x55aa55aa; + p[3] = 0xcc33cc33; + + __ISB(); + + for (i = 0; i < 4; i++) { + q = p[i]; + if (q != test_pattern_val[i]) { + /* printf("RW ERROR 0x%x != 0x%x\r\n", i, q); */ + return ERROR; + } + } + + /* clear PSRAM 1M Byte */ + for (i = 0; i < TEST_MEMORY_SIZE; i++) { + p[i] = 0xffffffff; + } + + /* check PSRAM 1M Byte */ + for (i = 0; i < TEST_MEMORY_SIZE; i++) { + p[i] = i; + } + + for (i = 0; i < TEST_MEMORY_SIZE; i++) { + q = p[i]; + + if (q != i) { + /* printf("RW ERROR 0x%x != 0x%x\r\n", i, q); */ + return ERROR; + } + } + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief psram calibration + * + * @param psram_data queue strock clock window number + * + * @return Error or psram id number + * +*******************************************************************************/ +static uint16_t hal_boot2_x8_psram_calibration(int32_t *psram_dqs_win_num) +{ + int16_t psram_id = 0, before_ef = 0; + int32_t left_flag = 0, right_flag = 0, c_val = 0; + int32_t dqs_win_min = 16, dqs_win_max = 0; + + uint16_t dqs_val[] = { + 0x8000, + 0xC000, + 0xE000, + 0xF000, + 0xF800, + 0xFC00, + 0xFE00, + 0xFF00, + 0xFF80, + 0xFFC0, + 0xFFE0, + 0xFFF0, + 0xFFF8, + 0xFFFC, + 0xFFFE, + 0xFFFF, + }; + + LOG_F("r ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg); + before_ef = g_efuse_cfg.psram_dqs_cfg; + if ((g_efuse_cfg.psram_dqs_cfg & (0x1000)) && (g_efuse_cfg.psram_dqs_cfg != 0xffff)) { + left_flag = ((g_efuse_cfg.psram_dqs_cfg & (0xf0)) >> 0x4); + right_flag = (g_efuse_cfg.psram_dqs_cfg & (0xf)); + c_val = ((left_flag + right_flag) >> 0x1); + *psram_dqs_win_num = right_flag - left_flag; + // printf("ef window: 0x%02x ~ 0x%02x; c_val: 0x%02x; dqs:0x%04x; code num:%d\r\n", left_flag, right_flag, c_val, dqs_val[c_val], (right_flag - left_flag)); + psram_id = hal_boot2_psram_winbond_init_dqs(PSRAM_WINBOND_BURST_LENGTH_64_BYTES, 0, PSRAM_WINBOND_6_CLOCKS_LATENCY, dqs_val[c_val]); + if ((psram_id != HAL_BOOT2_PSRAM_ID1_WINBOND_4MB) && (psram_id != HAL_BOOT2_PSRAM_ID2_WINBOND_16MB) && (psram_id != HAL_BOOT2_PSRAM_ID3_WINBOND_32MB)) { + return ERROR; + } + } else { + for (uint32_t dqs_index = 0; dqs_index < 16; dqs_index++) { + psram_id = hal_boot2_psram_winbond_init_dqs(PSRAM_WINBOND_BURST_LENGTH_64_BYTES, 0, PSRAM_WINBOND_6_CLOCKS_LATENCY, dqs_val[dqs_index]); + if ((psram_id == HAL_BOOT2_PSRAM_ID1_WINBOND_4MB) || (psram_id == HAL_BOOT2_PSRAM_ID2_WINBOND_16MB) || (psram_id == HAL_BOOT2_PSRAM_ID3_WINBOND_32MB)) { + if (hal_boot2_psram_rw_check() == SUCCESS) { + if (dqs_index < dqs_win_min) { + dqs_win_min = dqs_index; + dqs_win_max = dqs_index; + } else if (dqs_index > dqs_win_max) { + dqs_win_max = dqs_index; + } + } + } + } + + left_flag = dqs_win_min; + right_flag = dqs_win_max; + c_val = ((left_flag + right_flag) >> 1); + + g_efuse_cfg.psram_dqs_cfg = (((left_flag << 0x4) | (right_flag)) & (0xff)); + if (bflb_ef_ctrl_get_trim_parity(g_efuse_cfg.psram_dqs_cfg, 11)) { + g_efuse_cfg.psram_dqs_cfg = ((0x1800) | (g_efuse_cfg.psram_dqs_cfg)); + } else { + g_efuse_cfg.psram_dqs_cfg = ((0x1000) | (g_efuse_cfg.psram_dqs_cfg)); + } + LOG_F("c ef:0x%08lx\r\n", g_efuse_cfg.psram_dqs_cfg); + *psram_dqs_win_num = right_flag - left_flag; + if (((*psram_dqs_win_num) <= 4) || ((*psram_dqs_win_num) > 0xf)) { + return ERROR; + } + psram_id = hal_boot2_psram_winbond_init_dqs(PSRAM_WINBOND_BURST_LENGTH_64_BYTES, 0, PSRAM_WINBOND_6_CLOCKS_LATENCY, dqs_val[c_val]); + if ((psram_id != HAL_BOOT2_PSRAM_ID1_WINBOND_4MB) && (psram_id != HAL_BOOT2_PSRAM_ID2_WINBOND_16MB) && (psram_id != HAL_BOOT2_PSRAM_ID3_WINBOND_32MB)) { + return ERROR; + } + /* to do write efuse psram dqs delay */ + if (!(before_ef & 0x1fff)) { + bflb_ef_ctrl_write_common_trim(NULL,"psram",g_efuse_cfg.psram_dqs_cfg,1); + } + } + return psram_id; +} + + +/****************************************************************************/ /** + * @brief trim dcdc and ldo + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_efuse_trim(void) +{ + uint32_t tmpVal = 0; + + bflb_ef_ctrl_com_trim_t trim = {0}; + bflb_ef_ctrl_read_common_trim(NULL, "dcdc11", &trim, 1); + if (trim.en) { + if(trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value,trim.len)){ + tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC11_VOUT_TRIM_AON, trim.value); + BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal); + } + } + + bflb_ef_ctrl_read_common_trim(NULL, "dcdc18", &trim, 1); + if (trim.en) { + if(trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value,trim.len)){ + tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_0); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VOUT_TRIM_AON, trim.value); + BL_WR_REG(AON_BASE, AON_DCDC18_TOP_0, tmpVal); + } + } + + bflb_ef_ctrl_read_common_trim(NULL, "ldo28cis", &trim, 1); + if (trim.en) { + if(trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value,trim.len)){ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO28CIS); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO28CIS_VOUT_TRIM, trim.value); + BL_WR_REG(GLB_BASE, GLB_LDO28CIS, tmpVal); + } + } + + bflb_ef_ctrl_read_common_trim(NULL, "ldo15cis", &trim, 1); + if (trim.en) { + if(trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value,trim.len)){ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO15CIS); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO15CIS_VOUT_TRIM, trim.value); + BL_WR_REG(GLB_BASE, GLB_LDO15CIS, tmpVal); + } + } + + bflb_ef_ctrl_read_common_trim(NULL, "ldo18flash", &trim, 1); + if (trim.en) { + if(trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value,trim.len)){ + tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO18FLASH); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO18FLASH_VOUT_TRIM, trim.value); + BL_WR_REG(GLB_BASE, GLB_LDO18FLASH, tmpVal); + } + } + + bflb_ef_ctrl_read_common_trim(NULL, "usb20", &trim, 1); + if (trim.en) { + if(trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value,trim.len)){ + tmpVal = BL_RD_REG(AON_BASE, AON_PSW_IRRCV); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_USB20_RCAL_CODE_AON, trim.value); + BL_WR_REG(AON_BASE, AON_PSW_IRRCV, tmpVal); + } + } + + bflb_ef_ctrl_read_common_trim(NULL, "ldo18io", &trim, 1); + if (trim.en) { + if(trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value,trim.len)){ + tmpVal = BL_RD_REG(AON_BASE, AON_LDO18IO); + tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO18IO_VOUT_SEL_AON, 0x2); + BL_WR_REG(AON_BASE, AON_LDO18IO, tmpVal); + } + } + + +} + + + +/****************************************************************************/ /** + * @brief hal_boot2_custom + * + * @param custom_param + * + * @return 0 + * +*******************************************************************************/ +uint32_t hal_boot2_custom(void *custom_param) +{ + int32_t psram_dqs_win_num = 0; + + hal_boot2_efuse_trim(); + + /* for pds wakeup clock related to RF */ + GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_PDS); + PDS_Power_On_MM_System(); + + /* psram calibration */ + uint32_t ret = 0; + if (((g_efuse_cfg.dev_info & HAL_BOOT2_PSRAM_INFO_MASK) >> HAL_BOOT2_PSRAM_INFO_POS) != 0) { + hal_boot2_init_psram_gpio(); + /* ToDo: if WIFIPLL_320m not work */ + GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_EMI_WIFIPLL_320M); + GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_EMI_CPUPLL_400M); + GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_EMI_AUPLL_DIV1); + //GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_PSRAM0_CTRL | GLB_AHB_CLOCK_PSRAM1_CTRL); + GLB_PSRAM_PER_Clock_UnGate(); + GLB_Set_PSram_CLK(1, ENABLE, GLB_PSRAM_EMI_AUPLL_DIV1, 1); + + hal_boot2_psram_winbond_init_dqs(PSRAM_WINBOND_BURST_LENGTH_64_BYTES, 0, PSRAM_WINBOND_6_CLOCKS_LATENCY, 0xffc0); + Tzc_Sec_PSRAMB_Access_Release(); + ret = hal_boot2_x8_psram_calibration(&psram_dqs_win_num); + if (ret == ERROR) { + while (1) { + printf("psram:%d\r\n", (int)psram_dqs_win_num); + arch_delay_ms(500); + } + } + printf("psram:%d \r\n", (int)psram_dqs_win_num); + + /* Flush i-cache in case branch prediction logic is wrong when + psram is not inited by hal_boot2_custom but cpu has already prefetch psram */ + __ISB(); + } + return ret; +} + +/****************************************************************************/ /** + * @brief hal_boot2_read_secure_boot + * + * @param aes + * + * @return None + * +*******************************************************************************/ +void hal_boot2_read_secure_boot(uint8_t aes[HAL_BOOT2_CPU_GROUP_MAX]) +{ + uint32_t tmpval = 0; + bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_CFG_0_OFFSET, &tmpval, 1, 1); + tmpval &= EF_DATA_0_EF_SF_AES_MODE_MSK; + tmpval = tmpval >> EF_DATA_0_EF_SF_AES_MODE_POS; + + aes[1] = aes[0] = tmpval & 0xff; +} + +/****************************************************************************/ /** + * @brief hal_boot2_get_efuse_cfg + * + * @param efuse_cfg + * + * @return None + * +*******************************************************************************/ +void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg) +{ + uint32_t i = 0; + struct boot_efuse_sw_cfg0_t sw_cfg0; + + /* get hw cfg (signature and aes type) */ + hal_boot2_read_secure_boot(efuse_cfg->encrypted); + + + for (i = 0; i < HAL_BOOT2_CPU_GROUP_MAX; i++) { + if (efuse_cfg->encrypted[i] == EF_CTRL_SF_AES_192) { + efuse_cfg->encrypted[i] = SF_CTRL_AES_192BITS + 1; + } else if (efuse_cfg->encrypted[i] == EF_CTRL_SF_AES_256) { + efuse_cfg->encrypted[i] = SF_CTRL_AES_256BITS + 1; + } + } + + /* get sw uasge 0 */ + bflb_efuse_read_sw_usage(0, (uint32_t *)&sw_cfg0); + /* get sw uasge 1 */ + //EF_Ctrl_Read_Sw_Usage(1, &sw_cfg1); + + for (i = 0; i < HAL_BOOT2_CPU_GROUP_MAX; i++) { + efuse_cfg->sign[i] = ((struct boot_efuse_sw_cfg0_t)sw_cfg0).sign_cfg; + } + for (i = 1; i < HAL_BOOT2_CPU_GROUP_MAX; i++) { + efuse_cfg->encrypted[i] = EF_CTRL_SF_AES_NONE; + } + + efuse_cfg->hbn_check_sign = (uint8_t)(sw_cfg0.hbn_check_sign); + efuse_cfg->sf_pin_cfg = (uint8_t)(sw_cfg0.sf_pin_cfg); + efuse_cfg->uart_download_cfg = (uint8_t)(sw_cfg0.uart_download_cfg); + efuse_cfg->keep_dbg_port_closed = (uint8_t)(sw_cfg0.keep_dbg_port_closed); + efuse_cfg->boot_pin_cfg = (uint8_t)(sw_cfg0.boot_pin_cfg); + + /* get psram dqs delay info */ + bflb_ef_ctrl_com_trim_t trim; + efuse_cfg->psram_dqs_cfg = 0xffff; + bflb_ef_ctrl_read_common_trim(NULL, "psram", &trim, 1); + if (trim.en) { + if(trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value,trim.len)){ + efuse_cfg->psram_dqs_cfg = trim.value; + } + } + + /* get device info */ + //EF_Ctrl_Get_Chip_Info((Efuse_Chip_Info_Type *)&efuse_cfg->dev_info); + + /* get chip id */ + bflb_efuse_get_chipid(efuse_cfg->chip_id); + + /* get public key hash */ + bflb_efuse_read_aes_key(0, (uint8_t *)efuse_cfg->pk_hash_cpu0, HAL_BOOT2_PK_HASH_SIZE / 4); + bflb_efuse_read_aes_key(8, (uint8_t *)efuse_cfg->pk_hash_cpu1, HAL_BOOT2_PK_HASH_SIZE / 4); + +} + +/****************************************************************************/ /** + * @brief reset sec eng clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_reset_sec_eng(void) +{ + GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SEC_ENG); + //Sec_Eng_Group0_Request_SHA_Access(); + //Sec_Eng_Group0_Request_AES_Access(); + //Sec_Eng_Group0_Request_Trng_Access(); + //Sec_Eng_Trng_Enable(); + GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M); +} + +/****************************************************************************/ /** + * @brief system soft reset + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_sw_system_reset(void) +{ + GLB_SW_System_Reset(); +} + +/****************************************************************************/ /** + * @brief hal_boot2_set_psmode_status + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_set_psmode_status(uint32_t flag) +{ + HBN_Set_Status_Flag(flag); +} + +/****************************************************************************/ /** + * @brief hal_boot2_get_psmode_status + * + * @param None + * + * @return status flag + * +*******************************************************************************/ +uint32_t hal_boot2_get_psmode_status(void) +{ + return HBN_Get_Status_Flag(); +} + +/****************************************************************************/ /** + * @brief hal_boot2_get_user_fw + * + * @param None + * + * @return None + * +*******************************************************************************/ +uint32_t hal_boot2_get_user_fw(void) +{ + return BL_RD_WORD(HBN_BASE + HBN_RSV0_OFFSET); +} + +/****************************************************************************/ /** + * @brief hal_boot2_clr_user_fw + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_clr_user_fw(void) +{ + uint32_t *p = (uint32_t *)(HBN_BASE + HBN_RSV0_OFFSET); + *p = 0; +} + +/****************************************************************************/ /** + * @brief hal_boot2_sboot_finish + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION hal_boot2_sboot_finish(void) +{ + // uint32_t tmpVal; + // if (!g_efuse_cfg.keep_dbg_port_closed) { + // /* only after this, JTAG is really open */ + // tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, 0xf); + // BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal); + // } +} + +/****************************************************************************/ /** + * @brief uart gpio init + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_uart_gpio_init(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + + bflb_gpio_uart_init(gpio, GPIO_PIN_20, GPIO_UART_FUNC_UART0_TX); + bflb_gpio_uart_init(gpio, GPIO_PIN_21, GPIO_UART_FUNC_UART0_RX); +} + +/****************************************************************************/ /** + * @brief uart gpio init + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_debug_uart_gpio_init(void) +{ +} + +/****************************************************************************/ /** + * @brief usb init + * + * @param None + * + * @return None + * +*******************************************************************************/ +#if HAL_BOOT2_SUPPORT_USB_IAP +void hal_boot2_debug_usb_port_init(void) +{ +} +#endif + +/****************************************************************************/ /** + * @brief uart deinit + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_debug_uart_gpio_deinit(void) +{ +} + +/****************************************************************************/ /** + * @brief Check bootheader crc + * + * @param data: bootheader data pointer + * + * @return boot_error_code type + * +*******************************************************************************/ +static uint32_t hal_boot_check_bootheader(struct hal_bootheader_t *header) +{ + uint32_t crc_pass = 0; + uint32_t crc; + + if (header->basic_cfg.crc_ignore == 1 && header->crc32 == HAL_BOOT2_DEADBEEF_VAL) { + //MSG("Crc ignored\r\n"); + crc_pass = 1; + } else { + crc = BFLB_Soft_CRC32((uint8_t *)header, sizeof(struct hal_bootheader_t) - sizeof(header->crc32)); + + if (header->crc32 == crc) { + crc_pass = 1; + } + } + return crc_pass; +} + +/****************************************************************************/ /** + * @brief Check if the input public key is the same as burned in the efuse + * + * @param g_boot_img_cfg: Boot image config pointer + * @param data: Image data pointer + * + * @return boot_error_code type + * +*******************************************************************************/ +int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data) +{ + struct hal_bootheader_t *header = (struct hal_bootheader_t *)data; + uint32_t crc_pass = 0; + uint32_t i = 0; + uint32_t *phash = (uint32_t *)header->basic_cfg.hash; + + crc_pass = hal_boot_check_bootheader(header); + + if (!crc_pass) { + //MSG_ERR("bootheader crc error\r\n"); + //blsp_dump_data((uint8_t *)&crc, 4); + return 0x0204; + } + + if (header->basic_cfg.notload_in_bootrom) { + return 0x0202; + } + + /* Get which CPU's img it is*/ + for (i = 0; i < HAL_BOOT2_CPU_MAX; i++) { + if (0 == memcmp((void *)&header->magiccode, HAL_BOOT2_CPU0_MAGIC, + sizeof(header->magiccode))) { + break; + } else if (0 == memcmp((void *)&header->magiccode, HAL_BOOT2_CPU1_MAGIC, + sizeof(header->magiccode))) { + break; + } + } + + if (i == HAL_BOOT2_CPU_MAX) { + /* No cpu img magic match */ + //MSG_ERR("Magic code error\r\n"); + return 0x0203; + } + + if (boot_img_cfg == NULL) { + return 0; + } + + boot_img_cfg->pk_src = i; + boot_img_cfg->img_valid = 0; + + arch_memcpy_fast(&boot_img_cfg->basic_cfg, &header->basic_cfg, + sizeof(header->basic_cfg)); + + /* Check encrypt and sign match*/ + if (g_efuse_cfg.encrypted[i] != boot_img_cfg->basic_cfg.encrypt_type) { + if (boot_img_cfg->basic_cfg.xts_mode == 0) { + //("Encrypt not fit\r\n"); + return 0x0205; + } + } + + if (g_efuse_cfg.sign[i] != boot_img_cfg->basic_cfg.sign_type) { + //MSG_ERR("sign not fit\r\n"); + boot_img_cfg->basic_cfg.sign_type = g_efuse_cfg.sign[i]; + return 0x0206; + } + + if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) { + /* In HBN Mode, if user select to ignore hash and sign*/ + boot_img_cfg->basic_cfg.hash_ignore = 1; + } else if ((boot_img_cfg->basic_cfg.hash_ignore == 1 && *phash != HAL_BOOT2_DEADBEEF_VAL) || + g_efuse_cfg.sign[i] != 0) { + /* If signed or user not really want to ignore, hash can't be ignored*/ + boot_img_cfg->basic_cfg.hash_ignore = 0; + } + + if (g_user_hash_ignored) { + boot_img_cfg->basic_cfg.hash_ignore = 1; + } + + if (boot_img_cfg->basic_cfg.img_len_cnt == 0) { + return 0x0207; + } + + arch_memcpy_fast(&boot_img_cfg->cpu_cfg, &header->cpu_cfg, + sizeof(header->cpu_cfg)); + return 0; +} + +/****************************************************************************/ /** + * @brief clean cache + * + * @param + * + * @return cache set result + * +*******************************************************************************/ +void ATTR_TCM_SECTION hal_boot2_clean_cache(void) +{ + L1C_DCache_Clean_Invalid_All(); + L1C_ICache_Invalid_All(); +} + +/****************************************************************************/ /** + * @brief set cache + * + * @param cont_read: continue read mode + * boot_img_cfg: cache set param + * + * @return cache set result + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg) +{ + bflb_flash_set_cache(cont_read, boot_img_cfg->cpu_cfg[0].cache_enable, + boot_img_cfg->cpu_cfg[0].cache_way_dis, + boot_img_cfg->basic_cfg.group_image_offset); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get the ram image name and count + * + * @param img_name: ram image name in partition + * @param ram_img_cnt: ram image count that support boot from flash + * + * @return None + * +*******************************************************************************/ +void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt) +{ + *ram_img_cnt = 0; +} + +/****************************************************************************/ /** + * @brief get the ram image info + * + * @param data: bootheader information + * @param image_offset: ram image offset in flash(from of bootheader) + * @param img_len: ram image length + * @param hash: pointer to hash pointer + * + * @return None + * +*******************************************************************************/ +void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash) +{ + struct hal_bootheader_t *header = (struct hal_bootheader_t *)data; + uint32_t crc_pass = 0; + *img_len = 0; + uint8_t *phash = *hash; + uint8_t hash_ignore = 1; + + crc_pass = hal_boot_check_bootheader(header); + + if (!crc_pass) { + return; + } + if (0 != memcmp((void *)&header->magiccode, HAL_BOOT2_CPU0_MAGIC, sizeof(header->magiccode)) && + 0 != memcmp((void *)&header->magiccode, HAL_BOOT2_CPU1_MAGIC, sizeof(header->magiccode))) { + return; + } + + /* for ram image, it always download in iot tab, so + it share the same group with core 0 but use different image offset and + boot entry */ + *image_offset = 4096 * 1; //bootheader->basic_cfg.group_image_offset; + *img_len = header->basic_cfg.img_len_cnt; + + if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) { + /* In HBN Mode, if user select to ignore hash and sign*/ + hash_ignore = 1; + } else if ((header->basic_cfg.hash_ignore == 1 && header->basic_cfg.hash[0] != HAL_BOOT2_DEADBEEF_VAL) || + g_efuse_cfg.sign[0] != 0) { + /* If signed or user not really want to ignore, hash can't be ignored*/ + hash_ignore = 0; + } + + if (hash_ignore == 1) { + *hash = NULL; + } else { + memcpy(phash, header->basic_cfg.hash, sizeof(header->basic_cfg.hash)); + } +} + +/****************************************************************************/ /** + * @brief release other cpu to boot up + * + * @param core: core number + * @param boot_addr: boot address + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr) +{ + GLB_Set_CPU_Reset_Address(core, boot_addr); + GLB_Release_CPU(core); +} + +/****************************************************************************/ /** + * @brief get xip address according to flash addr + * + * @param flash_addr: flash address + * + * @return XIP Address + * +*******************************************************************************/ +uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr) +{ + uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0); + if (flash_addr >= img_offset) { + return BL606P_FLASH_XIP_BASE + (flash_addr - img_offset); + } else { + return 0; + } +} + +/****************************************************************************/ /** + * @brief get if multi-group + * + * @param None + * + * @return 1 for multi-group 0 for not + * +*******************************************************************************/ +uint32_t hal_boot2_get_grp_count(void) +{ + return 1; +} + +/****************************************************************************/ /** + * @brief get cpu count + * + * @param None + * + * @return 1 for multi-group 0 for not + * +*******************************************************************************/ +uint32_t hal_boot2_get_cpu_count(void) +{ + return 3; +} + +/****************************************************************************/ /** + * @brief get cpu count + * + * @param None + * + * @return 1 for multi-group 0 for not + * +*******************************************************************************/ +uint32_t ATTR_TCM_SECTION hal_boot2_get_feature_flag(void) +{ + return HAL_BOOT2_MP_FLAG; +} + +/****************************************************************************/ /** + * @brief get boot header offset + * + * @param None + * + * @return bootheader offset + * +*******************************************************************************/ +uint32_t hal_boot2_get_bootheader_offset(void) +{ + return 0x0; +} +/****************************************************************************/ /** + * @brief hal_reboot_config + * + * @param boot source + * + * @return bootheader offset + * +*******************************************************************************/ +void hal_reboot_config(hal_reboot_cfg_t rbot) +{ + switch(rbot){ + case HAL_REBOOT_AS_BOOTPIN: + HBN_Set_Hand_Off_Config(0); + break; + case HAL_REBOOT_FROM_INTERFACE: + HBN_Set_Hand_Off_Config(1); + break; + case HAL_REBOOT_FROM_MEDIA: + HBN_Set_Hand_Off_Config(2); + break; + default : + HBN_Set_Hand_Off_Config(0); + break; + } +} diff --git a/examples/boot2_isp/port/bl606p/bflb_port_boot2.h b/examples/boot2_isp/port/bl606p/bflb_port_boot2.h new file mode 100644 index 00000000..7d1c3811 --- /dev/null +++ b/examples/boot2_isp/port/bl606p/bflb_port_boot2.h @@ -0,0 +1,343 @@ +/** + * ***************************************************************************** + * @file bflb_port_boot2.h + * @version 0.1 + * @date 2021-07-17 + * @brief + * ***************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#ifndef __BFLB_PORT_BOOT2_H__ +#define __BFLB_PORT_BOOT2_H__ + +#include "bl606p_sflash.h" +#include "bl606p_glb.h" +#include "bl606p_pm.h" + +#define HAL_PLL_CFG_MAGICCODE "PCFG" + +#define HAL_BOOT2_PK_HASH_SIZE 256 / 8 +#define HAL_BOOT2_IMG_HASH_SIZE 256 / 8 +#define HAL_BOOT2_ECC_KEYXSIZE 256 / 8 +#define HAL_BOOT2_ECC_KEYYSIZE 256 / 8 +#define HAL_BOOT2_SIGN_MAXSIZE (2048 / 8) +#define HAL_BOOT2_DEADBEEF_VAL 0xdeadbeef +#define HAL_BOOT2_CPU0_MAGIC "BFNP" +#define HAL_BOOT2_CPU1_MAGIC "BFAP" +#define HAL_BOOT2_CP_FLAG 0x02 +#define HAL_BOOT2_MP_FLAG 0x01 +#define HAL_BOOT2_SP_FLAG 0x00 + +#define HAL_BOOT2_SUPPORT_DECOMPRESS 1 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_USB_IAP 0 /* 1 support IAP, 0 not support */ +#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM 0 /* 1 support eflash loader ram, 0 not support */ +#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 0 /* 1 support eflash loader flash, 0 not support */ +#define HAL_BOOT2_SUPPORT_SIGN_ENCRYPT 1 /* 1 support sign and encrypt, 0 not support */ + +#define HAL_BOOT2_CPU_GROUP_MAX 1 +#define HAL_BOOT2_CPU_MAX 3 +#define HAL_BOOT2_RAM_IMG_COUNT_MAX 0 + +#define HAL_BOOT2_FW_IMG_OFFSET_AFTER_HEADER 4 * 1024 + +#define HAL_BOOT2_MFG_START_REQUEST_OFFSET 8 * 1024 + +#define HAL_BOOT2_PSRAM_ID1_WINBOND_4MB (0x5f) +#define HAL_BOOT2_PSRAM_ID2_WINBOND_16MB (0xc96) +#define HAL_BOOT2_PSRAM_ID3_WINBOND_32MB (0xe86) + +#define HAL_BOOT2_PSRAM_INFO_MASK (0xff0000) +#define HAL_BOOT2_PSRAM_INFO_POS (16) + +typedef enum { + HAL_REBOOT_AS_BOOTPIN, /*!< reboot as bootpin level */ + HAL_REBOOT_FROM_INTERFACE, /*!< reboot from interface, download mode */ + HAL_REBOOT_FROM_MEDIA, /*!< reboot from media, running mode */ + HAL_REBOOT_MAX /*!< reboot max value */ +} hal_reboot_cfg_t; + +struct __attribute__((packed, aligned(4))) boot_efuse_sw_cfg0_t { + uint32_t bootrom_protect : 1; /* ef_sw_usage_0 bit [0] */ + uint32_t uart_log_disable : 1; /* ef_sw_usage_0 bit [1] */ + uint32_t boot_pin_cfg : 1; /* ef_sw_usage_0 bit [2] */ + //uint32_t dbg_pin_cfg : 1; /* ef_sw_usage_0 bit [3] */ + uint32_t uart_download_cfg : 1; /* ef_sw_usage_0 bit [3] */ + + uint32_t mediaboot_disable : 1; /* ef_sw_usage_0 bit [4] */ + uint32_t uartboot_disable : 1; /* ef_sw_usage_0 bit [5] */ + uint32_t usbboot_enable : 1; /* ef_sw_usage_0 bit [6] */ + uint32_t uart_log_reopen : 1; /* ef_sw_usage_1 bit [7] */ + + uint32_t sign_cfg : 1; /* ef_sw_usage_0 bit [8] */ + uint32_t dcache_disable : 1; /* ef_sw_usage_0 bit [9] */ + uint32_t jtag_cfg : 2; /* ef_sw_usage_0 bit [11:10] */ + + uint32_t fix_key_sel : 1; /* ef_sw_usage_0 bit [12] */ + + uint32_t sdh_en : 1; /* ef_sw_usage_1 bit [13] */ + uint32_t sf_pin_cfg : 5; /* ef_sw_usage_0 bit [18:14] */ + uint32_t boot_level_revert : 1; /* ef_sw_usage_0 bit [19] */ + + uint32_t boot_pin_dly : 2; /* ef_sw_usage_0 bit [21:20] */ + uint32_t ldo_trim_enable : 1; /* ef_sw_usage_0 bit [22] */ + uint32_t trim_enable : 1; /* ef_sw_usage_0 bit [23] */ + + uint32_t no_hd_boot_en : 1; /* ef_sw_usage_0 bit [24] */ + uint32_t flash_power_delay : 2; /* ef_sw_usage_0 bit [26:25] */ + uint32_t tz_boot : 1; /* ef_sw_usage_0 bit [27] */ + + uint32_t encrypted_tz_boot : 1; /* ef_sw_usage_0 bit [28] */ + uint32_t hbn_check_sign : 1; /* ef_sw_usage_0 bit [29] */ + uint32_t keep_dbg_port_closed : 1; /* ef_sw_usage_0 bit [30] */ + uint32_t hbn_jump_disable : 1; /* ef_sw_usage_0 bit [31] */ +}; + +struct __attribute__((packed, aligned(4))) boot_efuse_sw_cfg1_t { + uint32_t xtal_type : 3; /* ef_sw_usage_1 bit [2:0] */ + uint32_t wifipll_pu : 1; /* ef_sw_usage_1 bit [3] */ + + uint32_t aupll_pu : 1; /* ef_sw_usage_1 bit [4] */ + uint32_t cpupll_pu : 1; /* ef_sw_usage_1 bit [5] */ + uint32_t mipipll_pu : 1; /* ef_sw_usage_1 bit [6] */ + uint32_t uhspll_pu : 1; /* ef_sw_usage_1 bit [7] */ + + uint32_t mcu_clk : 3; /* ef_sw_usage_1 bit [10:8] */ + uint32_t mcu_clk_div : 1; /* ef_sw_usage_1 bit [11] */ + + uint32_t mcu_pbclk_div : 2; /* ef_sw_usage_1 bit [13:12] */ + uint32_t lp_div : 1; /* ef_sw_usage_1 bit [14] */ + uint32_t dsp_clk : 2; /* ef_sw_usage_1 bit [16:15] */ + uint32_t dsp_clk_div : 1; /* ef_sw_usage_1 bit [17] */ + uint32_t dsp_pbclk : 2; /* ef_sw_usage_1 bit [19:18] */ + + uint32_t emi_clk : 2; /* ef_sw_usage_1 bit [21:20] */ + uint32_t emi_clk_div : 1; /* ef_sw_usage_1 bit [22] */ + uint32_t flash_clk_type : 3; /* ef_sw_usage_1 bit [25:23] */ + uint32_t flash_clk_div : 1; /* ef_sw_usage_1 bit [26] */ + uint32_t ldo18flash_bypass_cfg : 1; /* ef_sw_usage_1 bit [27] */ + uint32_t bootlog_pin_cfg : 1; /* ef_sw_usage_1 bit [28] */ + + uint32_t abt_offset : 1; /* ef_sw_usage_1 bit [29] */ + uint32_t boot_pull_cfg : 1; /* ef_sw_usage_1 bit [30] */ + uint32_t usb_if_int_disable : 1; /* ef_sw_usage_1 bit [31] */ +}; + +typedef struct +{ + uint8_t encrypted[HAL_BOOT2_CPU_GROUP_MAX]; + uint8_t sign[HAL_BOOT2_CPU_GROUP_MAX]; + uint8_t hbn_check_sign; + uint8_t rsvd[3]; + uint8_t chip_id[8]; + uint8_t pk_hash_cpu0[HAL_BOOT2_PK_HASH_SIZE]; + uint8_t pk_hash_cpu1[HAL_BOOT2_PK_HASH_SIZE]; + uint8_t uart_download_cfg; + uint8_t sf_pin_cfg; + uint8_t keep_dbg_port_closed; + uint8_t boot_pin_cfg; + uint32_t psram_dqs_cfg; + uint32_t dev_info; +} boot2_efuse_hw_config; + +struct __attribute__((packed, aligned(4))) hal_flash_config { + uint32_t magicCode; /*'FCFG'*/ + SPI_Flash_Cfg_Type cfg; + uint32_t crc32; +}; + +struct hal_psram_config { + uint32_t magicCode; /*'FCFG'*/ + SPI_Flash_Cfg_Type cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) hal_sys_clk_config { + uint8_t xtal_type; + uint8_t mcu_clk; + uint8_t mcu_clk_div; + uint8_t mcu_bclk_div; + + uint8_t mcu_pbclk_div; + uint8_t lp_div; + uint8_t dsp_clk; + uint8_t dsp_clk_div; + + uint8_t dsp_bclk_div; + uint8_t dsp_pbclk; + uint8_t dsp_pbclk_div; + uint8_t emi_clk; + + uint8_t emi_clk_div; + uint8_t flash_clk_type; + uint8_t flash_clk_div; + uint8_t wifipll_pu; + + uint8_t aupll_pu; + uint8_t cpupll_pu; + uint8_t mipipll_pu; + uint8_t uhspll_pu; +}; + +typedef struct { + uint32_t magiccode; + struct hal_sys_clk_config cfg; + uint32_t crc32; +} hal_pll_config; + +struct __attribute__((packed, aligned(4))) hal_basic_cfg_t { + uint32_t sign_type : 2; /* [1: 0] for sign */ + uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ + uint32_t key_sel : 2; /* [5: 4] key slot */ + uint32_t xts_mode : 1; /* [6] for xts mode */ + uint32_t aes_region_lock : 1; /* [7] rsvd */ + uint32_t no_segment : 1; /* [8] no segment info */ + uint32_t boot2_enable : 1; /* [9] boot2 enable */ + uint32_t boot2_rollback : 1; /* [10] boot2 rollback */ + uint32_t cpu_master_id : 4; /* [14: 11] master id */ + uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */ + uint32_t crc_ignore : 1; /* [16] ignore crc */ + uint32_t hash_ignore : 1; /* [17] hash ignore */ + uint32_t power_on_mm : 1; /* [18] power on mm */ + uint32_t em_sel : 3; /* [21: 19] em_sel */ + uint32_t cmds_en : 1; /* [22] command spliter enable */ + uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */ + uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */ + uint32_t icache_invalid : 1; /* [29] icache invalid */ + uint32_t dcache_invalid : 1; /* [30] dcache invalid */ + uint32_t fpga_halt_release : 1; /* [31] FPGA halt release function */ + + uint32_t group_image_offset; /* flash controller offset */ + uint32_t aes_region_len; /* aes region length */ + + uint32_t img_len_cnt; /* image length or segment count */ + uint32_t hash[8]; /* hash of the image */ +}; + +struct __attribute__((packed, aligned(4))) hal_cpu_cfg_t { + uint8_t config_enable; /* coinfig this cpu */ + uint8_t halt_cpu; /* halt this cpu */ + uint8_t cache_enable : 1; /* cache setting */ + uint8_t cache_wa : 1; /* cache setting */ + uint8_t cache_wb : 1; /* cache setting */ + uint8_t cache_wt : 1; /* cache setting */ + uint8_t cache_way_dis : 4; /* cache setting */ + uint8_t rsvd; + + uint32_t cache_range_h; /* cache range high */ + uint32_t cache_range_l; /* cache range low */ + + uint32_t image_address_offset; /* image address on flash */ /*image_address_offset*/ + uint32_t boot_entry; /* entry point of the m0 image */ + uint32_t msp_val; /* msp value */ +}; + +struct __attribute__((packed, aligned(4))) hal_patch_cfg_t { + uint32_t addr; + uint32_t value; +}; + +struct __attribute__((packed, aligned(4))) hal_bootheader_t { + uint32_t magiccode; + uint32_t rivison; + + struct hal_flash_config flashCfg; + hal_pll_config clkCfg; + + struct hal_basic_cfg_t basic_cfg; + + struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX]; + + uint32_t boot2_pt_table_0; /* address of partition table 0 */ + uint32_t boot2_pt_table_1; /* address of partition table 1 */ + + uint32_t flashCfgTableAddr; /* address of flashcfg table list */ + uint32_t flashCfgTableLen; /* flashcfg table list len */ + + struct hal_patch_cfg_t patch_on_read[4]; /* do patch when read flash */ + struct hal_patch_cfg_t patch_on_jump[4]; /* do patch when jump */ + + uint32_t rsvd[5]; + + uint32_t crc32; +}; + +typedef struct +{ + uint8_t img_valid; + uint8_t pk_src; + uint8_t rsvd[2]; + + struct hal_basic_cfg_t basic_cfg; + + struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX]; + + uint8_t aes_iv[16 + 4]; //iv in boot header + + uint8_t eckye_x[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header + uint8_t eckey_y[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header + uint8_t eckey_x2[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header + uint8_t eckey_y2[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header + + uint8_t signature[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header + uint8_t signature2[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header + +} boot2_image_config; + +extern boot2_efuse_hw_config g_efuse_cfg; +extern uint8_t g_ps_mode; +extern uint32_t g_user_hash_ignored; +extern struct device *dev_check_hash; + +void hal_boot2_init_clock(void); +uint32_t hal_boot2_custom(void *custom_param); +void hal_boot2_reset_sec_eng(void); +void hal_boot2_sw_system_reset(void); +void hal_boot2_set_psmode_status(uint32_t flag); +uint32_t hal_boot2_get_psmode_status(void); +uint32_t hal_boot2_get_user_fw(void); +void hal_boot2_clr_user_fw(void); +void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg); +int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg); +void hal_boot2_sboot_finish(void); +void hal_boot2_uart_gpio_init(void); +void hal_boot2_debug_uart_gpio_init(void); +void hal_boot2_debug_uart_gpio_deinit(void); +int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data); +void hal_boot2_clean_cache(void); +BL_Err_Type hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg); +void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt); +void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash); +void hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr); +uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr); +uint32_t hal_boot2_get_grp_count(void); +uint32_t hal_boot2_get_cpu_count(void); +uint32_t hal_boot2_get_feature_flag(void); +uint32_t hal_boot2_get_bootheader_offset(void); +void hal_reboot_config(hal_reboot_cfg_t rbot); +#endif diff --git a/examples/boot2_isp/port/bl606p/blsp_boot2_iap_flash.ld b/examples/boot2_isp/port/bl606p/blsp_boot2_iap_flash.ld new file mode 100644 index 00000000..2e6b9db0 --- /dev/null +++ b/examples/boot2_isp/port/bl606p/blsp_boot2_iap_flash.ld @@ -0,0 +1,258 @@ +/**************************************************************************************** +* @file flash.ld +* +* @brief This file is the link script file (gnuarm or armgcc). +* +* Copyright (C) BouffaloLab 2021 +* +**************************************************************************************** +*/ + +/* configure the CPU type */ +OUTPUT_ARCH( "riscv" ) +/* link with the standard c library */ +INPUT(-lc) +/* link with the standard GCC library */ +INPUT(-lgcc) +/* configure the entry point */ +ENTRY(__start) + +StackSize = 0x0400; /* 1KB */ +HeapMinSize = 0x1000; /* 4KB */ +/* ToDo */ +PROVIDE(__boot2_pass_param_addr = 0x62047E00);/* 0x62030000+96*1024-512 */ +MEMORY +{ + xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 48K + itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 48K + dtcm_memory (rx) : ORIGIN = 0x6202C000, LENGTH = 4K + nocache_ram_memory (!rx) : ORIGIN = 0x2202D000, LENGTH = 84K + ram_memory (!rx) : ORIGIN = 0x62042000, LENGTH = 16K +} + +SECTIONS +{ + + .text : + { + . = ALIGN(4); + __text_code_start__ = .; + KEEP (*(SORT_NONE(.init))) + KEEP (*(SORT_NONE(.vector))) + KEEP(*(.text.init.*)) + + *(.text) + *(.text.*) + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for usb desc */ + . = ALIGN(4); + _usb_desc_start = .; + KEEP(*(usb_desc)) + . = ALIGN(4); + _usb_desc_end = .; + + /*put .rodata**/ + *(EXCLUDE_FILE( *bl606p_glb*.o* \ + *bl606p_glb_gpio*.o* \ + *bl606p_pds*.o* \ + *bl606p_aon*.o* \ + *bl606p_hbn*.o* \ + *bl606p_l1c*.o* \ + *bl606p_common*.o* \ + *bl606p_clock*.o* \ + *bl606p_ef_ctrl*.o* \ + *bl606p_sf_cfg*.o* \ + *bl606p_sf_ctrl*.o* \ + *bl606p_sflash*.o* \ + *bl606p_xip_sflash*.o* \ + *bl606p_romapi_patch*.o* ) .rodata*) + + *(.srodata) + *(.srodata.*) + + . = ALIGN(4); + __text_code_end__ = .; + } > xip_memory + + . = ALIGN(4); + __itcm_load_addr = .; + + .itcm_region : AT (__itcm_load_addr) + { + . = ALIGN(4); + __tcm_code_start__ = .; + + + *(.tcm_code.*) + *(.tcm_const.*) + *(.sclock_rlt_code.*) + *(.sclock_rlt_const.*) + + *bl606p_glb*.o*(.rodata*) + *bl606p_glb_gpio*.o*(.rodata*) + *bl606p_pds*.o*(.rodata*) + *bl606p_aon*.o*(.rodata*) + *bl606p_hbn*.o*(.rodata*) + *bl606p_l1c*.o*(.rodata*) + *bl606p_common*.o*(.rodata*) + *bl606p_clock*.o*(.rodata*) + *bl606p_ef_ctrl*.o*(.rodata*) + *bl606p_sf_cfg*.o*(.rodata*) + *bl606p_sf_ctrl*.o*(.rodata*) + *bl606p_sflash*.o*(.rodata*) + *bl606p_xip_sflash*.o*(.rodata*) + *bl606p_romapi_patch*.o*(.rodata*) + + . = ALIGN(4); + __tcm_code_end__ = .; + } > itcm_memory + + __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .dtcm_region : AT (__dtcm_load_addr) + { + . = ALIGN(4); + __tcm_data_start__ = .; + + *(.tcm_data) + /* *finger_print.o(.data*) */ + + . = ALIGN(4); + __tcm_data_end__ = .; + } > dtcm_memory + + /*************************************************************************/ + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + StackSize; + . = ALIGN(0x4); + } > dtcm_memory + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); + PROVIDE( __freertos_irq_stack_top = __StackTop); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + .nocache_ram_region (NOLOAD) : + { + . = ALIGN(4); + __nocache_ram_data_start__ = .; + + *(.nocache_ram) + + . = ALIGN(4); + __nocache_ram_data_end__ = .; + } > nocache_ram_memory + + __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + + .system_ram_data_region : AT (__system_ram_load_addr) + { + . = ALIGN(4); + __system_ram_data_start__ = .; + + *(.system_ram) + + . = ALIGN(4); + __system_ram_data_end__ = .; + } > ram_memory + + .system_ram_noinit_data_region (NOLOAD) : + { + . = ALIGN(4); + *(.system_ram_noinit) + + . = ALIGN(4); + } > ram_memory + + __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); + + /* Data section */ + RAM_DATA : AT (__ram_load_addr) + { + . = ALIGN(4); + __ram_data_start__ = .; + + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.sdata2) + *(.sdata2.*) + + . = ALIGN(4); + __ram_data_end__ = .; + } > ram_memory + + __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); + ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow") + + .bl_bss : AT (__bss_start__) + { + . = ALIGN(4); + __bss_start__ = .; + + *(.bss*) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > ram_memory + + .noinit_data (NOLOAD) : + { + . = ALIGN(4); + __noinit_data_start__ = .; + + *(.noinit_data*) + + . = ALIGN(4); + __noinit_data_end__ = .; + } > ram_memory + + .nocache_noinit_ram_region (NOLOAD) : + { + . = ALIGN(4); + __nocache_ram_data_start__ = .; + + *(.nocache_noinit_ram) + + . = ALIGN(4); + __nocache_ram_data_end__ = .; + } > nocache_ram_memory + + .heap (NOLOAD): + { + . = ALIGN(4); + __HeapBase = .; + + /*__end__ = .;*/ + /*end = __end__;*/ + KEEP(*(.heap*)) + + . = ALIGN(4); + __HeapLimit = .; + } > ram_memory + + __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); + ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") + +} + diff --git a/examples/boot2_isp/port/bl616/bflb_port_boot2.c b/examples/boot2_isp/port/bl616/bflb_port_boot2.c index cde31bb9..31182e6d 100644 --- a/examples/boot2_isp/port/bl616/bflb_port_boot2.c +++ b/examples/boot2_isp/port/bl616/bflb_port_boot2.c @@ -378,6 +378,14 @@ void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg) // /* get psram dqs delay info */ // EF_Ctrl_Read_Psram_Trim((Efuse_Psram_Trim_Type *)&efuse_cfg->psram_dqs_cfg); + bflb_ef_ctrl_com_trim_t trim; + efuse_cfg->psram_dqs_cfg = 0xffff; + bflb_ef_ctrl_read_common_trim(NULL, "psram", &trim, 1); + if (trim.en) { + if(trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value,trim.len)){ + efuse_cfg->psram_dqs_cfg = trim.value; + } + } /* get device info */ //EF_Ctrl_Read_Device_Info((Efuse_Device_Info_Type *)&efuse_cfg->dev_info); diff --git a/examples/boot2_isp/port/bl616/blsp_boot2_iap_flash.ld b/examples/boot2_isp/port/bl616/blsp_boot2_iap_flash.ld index 55bbc74b..521c6fdb 100644 --- a/examples/boot2_isp/port/bl616/blsp_boot2_iap_flash.ld +++ b/examples/boot2_isp/port/bl616/blsp_boot2_iap_flash.ld @@ -40,6 +40,7 @@ SECTIONS __text_code_start__ = .; KEEP (*(SORT_NONE(.init))) + KEEP (*(SORT_NONE(.vector))) *(.text) *(.text.*) diff --git a/examples/boot2_isp/port/bl702/bflb_port_boot2.c b/examples/boot2_isp/port/bl702/bflb_port_boot2.c new file mode 100644 index 00000000..e9810c89 --- /dev/null +++ b/examples/boot2_isp/port/bl702/bflb_port_boot2.c @@ -0,0 +1,553 @@ +#include "bflb_port_boot2.h" +#include "bflb_flash.h" +#include "bl702_ef_ctrl.h" +#include "bl702_hbn.h" +#include "bl702_glb.h" +#include "bl702_xip_sflash.h" +#include "bflb_gpio.h" +#include "softcrc.h" +#include "bl702_clock.h" +#include "bflb_efuse.h" + +/****************************************************************************/ /** + * @brief init clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +static void mtimer_clear_time() +{ + *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME) = 0; + *(volatile uint32_t *)(CLIC_CTRL_ADDR + CLIC_MTIME + 4) = 0; +} + +/****************************************************************************/ /** + * @brief init clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_init_clock(void) +{ + uint32_t tmpVal; + mtimer_clear_time(); + tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); + GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK) / 1000 / 1000 - 1); + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, 0); + BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); +} + +/****************************************************************************/ /** + * @brief hal_boot2_custom + * + * @param custom_param + * + * @return 0 + * +*******************************************************************************/ +uint32_t hal_boot2_custom(void *custom_param) +{ + return 0; +} + +/****************************************************************************/ /** + * @brief hal_boot2_get_efuse_cfg + * + * @param efuse_cfg + * + * @return None + * +*******************************************************************************/ +void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg) +{ + uint32_t tmp; + uint32_t rootClk; + uint8_t hdiv = 0, bdiv = 0; + + /* save bclk fclk div and root clock sel */ + bdiv = GLB_Get_BCLK_Div(); + hdiv = GLB_Get_HCLK_Div(); + rootClk = BL_RD_REG(HBN_BASE, HBN_GLB); + + /* change root clock to rc32m for efuse operation */ + HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M); + + /* Get sign and aes type*/ + //EF_Ctrl_Read_Secure_Boot((EF_Ctrl_Sign_Type *)efuse_cfg->sign, (EF_Ctrl_SF_AES_Type *)efuse_cfg->encrypted); + bflb_efuse_read_secure_boot((uint8_t *)efuse_cfg->sign, (uint8_t *)efuse_cfg->encrypted); + /* Get hash:aes key slot 0 and slot1*/ + //EF_Ctrl_Read_AES_Key(0, (uint32_t *)efuse_cfg->pk_hash_cpu0, 8); + bflb_efuse_read_aes_key(0, (uint8_t *)efuse_cfg->pk_hash_cpu0, 8); + //EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id); + bflb_efuse_get_chipid(efuse_cfg->chip_id); + /* Get HBN check sign config */ + //EF_Ctrl_Read_Sw_Usage(0, &tmp); + bflb_efuse_read_sw_usage(0, &tmp); + efuse_cfg->hbn_check_sign = (tmp >> 22) & 0x01; + + /* restore bclk fclk div and root clock sel */ + GLB_Set_System_CLK_Div(hdiv, bdiv); + BL_WR_REG(HBN_BASE, HBN_GLB, rootClk); + __NOP(); + __NOP(); + __NOP(); + __NOP(); +} + +/****************************************************************************/ /** + * @brief reset sec eng clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_reset_sec_eng(void) +{ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_SEC); + GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_DLL96M); +} + +/****************************************************************************/ /** + * @brief system soft reset + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_sw_system_reset(void) +{ + GLB_SW_System_Reset(); +} + +/****************************************************************************/ /** + * @brief hal_boot2_set_psmode_status + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_set_psmode_status(uint32_t flag) +{ + HBN_Set_Status_Flag(flag); +} + +/****************************************************************************/ /** + * @brief hal_boot2_get_psmode_status + * + * @param None + * + * @return status flag + * +*******************************************************************************/ +uint32_t hal_boot2_get_psmode_status(void) +{ + return HBN_Get_Status_Flag(); +} + +/****************************************************************************/ /** + * @brief hal_boot2_get_user_fw + * + * @param None + * + * @return None + * +*******************************************************************************/ +uint32_t hal_boot2_get_user_fw(void) +{ + return BL_RD_WORD(HBN_BASE + HBN_RSV0_OFFSET); +} + +/****************************************************************************/ /** + * @brief hal_boot2_clr_user_fw + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_clr_user_fw(void) +{ + uint32_t *p = (uint32_t *)(HBN_BASE + HBN_RSV0_OFFSET); + *p = 0; +} + +/****************************************************************************/ /** + * @brief hal_boot2_sboot_finish + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION hal_boot2_sboot_finish(void) +{ +#if 0 //FixZc + uint32_t tmp_val; + + tmp_val = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL); + + tmp_val = BL_SET_REG_BITS_VAL(tmp_val, TZC_SEC_TZC_SBOOT_DONE, 0xf); + + BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmp_val); +#endif +} + +/****************************************************************************/ /** + * @brief uart gpio init + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_uart_gpio_init(void) +{ + GLB_GPIO_Type gpios[] = { GPIO_PIN_14, GPIO_PIN_15 }; + + GLB_GPIO_Func_Init(GPIO_FUN_UART, gpios, 2); + + GLB_UART_Fun_Sel((GPIO_PIN_14 % 8), GLB_UART_SIG_FUN_UART0_TXD); // GPIO_FUN_UART1_TX + GLB_UART_Fun_Sel((GPIO_PIN_15 % 8), GLB_UART_SIG_FUN_UART0_RXD); +} + +/****************************************************************************/ /** + * @brief uart gpio init + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_debug_uart_gpio_init(void) +{ + GLB_GPIO_Type gpios[] = { GLB_GPIO_PIN_17 }; + + GLB_GPIO_Func_Init(GPIO_FUN_UART, gpios, 1); + + GLB_UART_Fun_Sel((GLB_GPIO_PIN_17 % 8), GLB_UART_SIG_FUN_UART1_TXD); +} + +/****************************************************************************/ /** + * @brief usb init + * + * @param None + * + * @return None + * +*******************************************************************************/ +#if HAL_BOOT2_SUPPORT_USB_IAP +void hal_boot2_debug_usb_port_init(void) +{ + /* must do this , or usb can not be recognized */ + cpu_global_irq_disable(); + cpu_global_irq_enable(); + + GLB_GPIO_Type gpios[] = { GLB_GPIO_PIN_7, GLB_GPIO_PIN_8 }; + GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, gpios, 2); +} +#endif + +/****************************************************************************/ /** + * @brief uart deinit + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_debug_uart_gpio_deinit(void) +{ + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART0); + GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_UART1); + GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); +} + +/****************************************************************************/ /** + * @brief Check bootheader crc + * + * @param data: bootheader data pointer + * + * @return boot_error_code type + * +*******************************************************************************/ +static uint32_t hal_boot_check_bootheader(struct hal_bootheader_t *header) +{ + uint32_t crc_pass = 0; + uint32_t crc; + + if (header->bootCfg.bval.crcIgnore == 1 && header->crc32 == HAL_BOOT2_DEADBEEF_VAL) { + //MSG("Crc ignored\r\n"); + crc_pass = 1; + } else { + crc = BFLB_Soft_CRC32((uint8_t *)header, sizeof(struct hal_bootheader_t) - sizeof(header->crc32)); + + if (header->crc32 == crc) { + crc_pass = 1; + } + } + return crc_pass; +} + +/****************************************************************************/ /** + * @brief Check if the input public key is the same as burned in the efuse + * + * @param g_boot_img_cfg: Boot image config pointer + * @param data: Image data pointer + * + * @return boot_error_code type + * +*******************************************************************************/ +int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data) +{ + struct hal_bootheader_t *header = (struct hal_bootheader_t *)data; + uint32_t crc_pass = 0; + uint32_t i = 0; + uint32_t *phash = (uint32_t *)header->hash; + + crc_pass = hal_boot_check_bootheader(header); + + if (!crc_pass) { + //MSG_ERR("bootheader crc error\r\n"); + //blsp_dump_data((uint8_t *)&crc, 4); + return 0x0204; + } + + if (header->bootCfg.bval.notLoadInBoot) { + return 0x0202; + } + + /* Get which CPU's img it is*/ + for (i = 0; i < HAL_BOOT2_CPU_MAX; i++) { + if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU0_MAGIC, + sizeof(header->magicCode))) { + break; + } else if (0 == memcmp((void *)&header->magicCode, HAL_BOOT2_CPU1_MAGIC, + sizeof(header->magicCode))) { + break; + } + } + + if (i == HAL_BOOT2_CPU_MAX) { + /* No cpu img magic match */ + //MSG_ERR("Magic code error\r\n"); + return 0x0203; + } + + if (boot_img_cfg == NULL) { + return 0; + } + + boot_img_cfg->pk_src = i; + boot_img_cfg->img_valid = 0; + + /* Deal with pll config */ + + /* Encrypt and sign */ + boot_img_cfg->basic_cfg.encrypt_type = header->bootCfg.bval.encrypt_type; + boot_img_cfg->basic_cfg.sign_type = header->bootCfg.bval.sign; + boot_img_cfg->basic_cfg.key_sel = header->bootCfg.bval.key_sel; + + /* Xip relative */ + boot_img_cfg->basic_cfg.no_segment = header->bootCfg.bval.no_segment; + boot_img_cfg->cpu_cfg[0].cache_enable = header->bootCfg.bval.cache_enable; + boot_img_cfg->basic_cfg.aes_region_lock = header->bootCfg.bval.aes_region_lock; + //boot_img_cfg->cpu_cfg[1].halt_cpu = header->bootCfg.bval.halt_cpu1; + boot_img_cfg->cpu_cfg[0].cache_way_dis = header->bootCfg.bval.cache_way_disable; + boot_img_cfg->basic_cfg.hash_ignore = header->bootCfg.bval.hash_ignore; + /* Firmware len*/ + boot_img_cfg->basic_cfg.img_len_cnt = header->img_segment_info.img_len; + + /* Boot entry and flash offset */ + boot_img_cfg->cpu_cfg[0].boot_entry = header->bootEntry; + boot_img_cfg->basic_cfg.group_image_offset = header->img_start.flash_offset; + + boot_img_cfg->cpu_cfg[0].config_enable = 1; + boot_img_cfg->cpu_cfg[0].halt_cpu = 0; + + //MSG("sign %d,encrypt:%d\r\n", boot_img_cfg->sign_type,boot_img_cfg->encrypt_type); + + /* Check encrypt and sign match*/ + if (g_efuse_cfg.encrypted[i] != 0) { + if (boot_img_cfg->basic_cfg.encrypt_type == 0) { + //MSG_ERR("Encrypt not fit\r\n"); + return 0x0205; + } + } + + if (g_efuse_cfg.sign[i] != boot_img_cfg->basic_cfg.sign_type) { + //MSG_ERR("sign not fit\r\n"); + boot_img_cfg->basic_cfg.sign_type = g_efuse_cfg.sign[i]; + return 0x0206; + } + + if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) { + /* In HBN Mode, if user select to ignore hash and sign*/ + boot_img_cfg->basic_cfg.hash_ignore = 1; + } else if ((boot_img_cfg->basic_cfg.hash_ignore == 1 && *phash != HAL_BOOT2_DEADBEEF_VAL) || + g_efuse_cfg.sign[i] != 0) { + /* If signed or user not really want to ignore, hash can't be ignored*/ + boot_img_cfg->basic_cfg.hash_ignore = 0; + } + + if (g_user_hash_ignored) { + boot_img_cfg->basic_cfg.hash_ignore = 1; + } + + arch_memcpy_fast(boot_img_cfg->basic_cfg.hash, header->hash, sizeof(header->hash)); + + if (boot_img_cfg->basic_cfg.img_len_cnt == 0) { + return 0x0207; + } + + return 0; +} + +/****************************************************************************/ /** + * @brief clean cache + * + * @param + * + * @return cache set result + * +*******************************************************************************/ +void ATTR_TCM_SECTION hal_boot2_clean_cache(void) +{ + /* no need clean again since hal_boot2_set_cache will also clean + unused way,and bl702 no data cache except psram */ +} + +/****************************************************************************/ /** + * @brief set cache + * + * @param cont_read: continue read mode + * boot_img_cfg: cache set param + * + * @return cache set result + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg) +{ + return bflb_flash_set_cache(cont_read, boot_img_cfg->cpu_cfg[0].cache_enable, + boot_img_cfg->cpu_cfg[0].cache_way_dis, + boot_img_cfg->basic_cfg.group_image_offset); +} + +/****************************************************************************/ /** + * @brief get the ram image name and count + * + * @param img_name: ram image name in partition + * @param ram_img_cnt: ram image count that support boot from flash + * + * @return None + * +*******************************************************************************/ +void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt) +{ + *ram_img_cnt = 0; +} + +/****************************************************************************/ /** + * @brief get the ram image info + * + * @param data: bootheader information + * @param image_offset: ram image offset in flash(from of bootheader) + * @param img_len: ram image length + * @param hash: pointer to hash pointer + * + * @return None + * +*******************************************************************************/ +void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash) +{ + *img_len = 0; +} + +/****************************************************************************/ /** + * @brief release other cpu to boot up + * + * @param core: core number + * @param boot_addr: boot address + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr) +{ +} + +/****************************************************************************/ /** + * @brief get xip address according to flash addr + * + * @param flash_addr: flash address + * + * @return XIP Address + * +*******************************************************************************/ +uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr) +{ + uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(); + if (flash_addr >= img_offset) { + return BL702_FLASH_XIP_BASE + (flash_addr - img_offset); + } else { + return 0; + } +} + +/****************************************************************************/ /** + * @brief get multi-group count + * + * @param None + * + * @return 1 for multi-group 0 for not + * +*******************************************************************************/ +uint32_t hal_boot2_get_grp_count(void) +{ + return 1; +} + +/****************************************************************************/ /** + * @brief get cpu count + * + * @param None + * + * @return 1 for multi-group 0 for not + * +*******************************************************************************/ +uint32_t hal_boot2_get_cpu_count(void) +{ + return 1; +} + +/****************************************************************************/ /** + * @brief get cpu count + * + * @param None + * + * @return 1 for multi-group 0 for not + * +*******************************************************************************/ +uint32_t ATTR_TCM_SECTION hal_boot2_get_feature_flag(void) +{ + return HAL_BOOT2_SP_FLAG; +} + +/****************************************************************************/ /** + * @brief get boot header offset + * + * @param None + * + * @return bootheader offset + * +*******************************************************************************/ +uint32_t hal_boot2_get_bootheader_offset(void) +{ + return 0x00; +} diff --git a/examples/boot2_isp/port/bl702/bflb_port_boot2.h b/examples/boot2_isp/port/bl702/bflb_port_boot2.h new file mode 100644 index 00000000..f70d37d8 --- /dev/null +++ b/examples/boot2_isp/port/bl702/bflb_port_boot2.h @@ -0,0 +1,284 @@ +/** + * ***************************************************************************** + * @file bflb_port_boot2.h + * @version 0.1 + * @date 2022-12-13 + * @brief + * ***************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#ifndef __BFLB_PORT_BOOT2_H__ +#define __BFLB_PORT_BOOT2_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +#include "bl702_sflash.h" +#include "bl702_glb.h" + +#define BL_TCM_BASE BL702_TCM_BASE +#define BL_SYS_CLK_PLL GLB_SYS_CLK_DLL144M +#define BL_SFLASH_CLK GLB_SFLASH_CLK_72M +#define HAL_PLL_CFG_MAGICCODE "PCFG" + +#define HAL_BOOT2_PK_HASH_SIZE 256 / 8 +#define HAL_BOOT2_IMG_HASH_SIZE 256 / 8 +#define HAL_BOOT2_ECC_KEYXSIZE 256 / 8 +#define HAL_BOOT2_ECC_KEYYSIZE 256 / 8 +#define HAL_BOOT2_SIGN_MAXSIZE (2048 / 8) +#define HAL_BOOT2_DEADBEEF_VAL 0xdeadbeef +#define HAL_BOOT2_CPU0_MAGIC "BFNP" +#define HAL_BOOT2_CPU1_MAGIC "BFAP" +#define HAL_BOOT2_CP_FLAG 0x02 +#define HAL_BOOT2_MP_FLAG 0x01 +#define HAL_BOOT2_SP_FLAG 0x00 + +#define HAL_BOOT2_SUPPORT_DECOMPRESS 1 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_USB_IAP 0 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM 1 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 1 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_SIGN_ENCRYPT 1 /* 1 support sign and encrypt, 0 not support */ + +#define HAL_BOOT2_CPU_GROUP_MAX 1 +#define HAL_BOOT2_CPU_MAX 1 +#define HAL_BOOT2_RAM_IMG_COUNT_MAX 0 + +#define HAL_BOOT2_FW_IMG_OFFSET_AFTER_HEADER 4 * 1024 +#define HAL_BOOT2_MFG_START_REQUEST_OFFSET 8 * 1024 + +#define CLIC_CTRL_ADDR 0x02000000UL +#define CLIC_HART0_ADDR 0x02800000UL + +#define CLIC_MSIP 0x0000 +#define CLIC_MSIP_size 0x4 +#define CLIC_MTIMECMP 0x4000 +#define CLIC_MTIMECMP_size 0x8 +#define CLIC_MTIME 0xBFF8 +#define CLIC_MTIME_size 0x8 + +#define CLIC_INTIP 0x000 +#define CLIC_INTIE 0x400 +#define CLIC_INTCFG 0x800 +#define CLIC_CFG 0xc00 + +typedef struct +{ + uint32_t encrypted[HAL_BOOT2_CPU_GROUP_MAX]; + uint32_t sign[HAL_BOOT2_CPU_GROUP_MAX]; + uint8_t hbn_check_sign; + uint8_t rsvd[1]; + uint8_t chip_id[8]; + uint32_t pk_hash_cpu0[HAL_BOOT2_PK_HASH_SIZE]; + uint32_t pk_hash_cpu1[HAL_BOOT2_PK_HASH_SIZE]; + uint8_t uart_download_cfg; + uint8_t sf_pin_cfg; + uint8_t keep_dbg_port_closed; + uint8_t boot_pin_cfg; +} boot2_efuse_hw_config; + +struct __attribute__((packed, aligned(4))) hal_flash_config { + uint32_t magicCode; /*'FCFG'*/ + SPI_Flash_Cfg_Type cfg; + uint32_t crc32; +}; + +typedef struct +{ + uint8_t xtal_type; + uint8_t pll_clk; + uint8_t hclk_div; + uint8_t bclk_div; + + uint8_t flash_clk_type; + uint8_t flash_clk_div; + uint8_t rsvd[2]; +} hal_sys_clk_config; + +typedef struct +{ + uint32_t magicCode; /*'PCFG'*/ + hal_sys_clk_config cfg; + uint32_t crc32; +} hal_pll_config; + +struct __attribute__((packed, aligned(4))) hal_basic_cfg_t { + uint32_t sign_type : 2; /* [1: 0] for sign */ + uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ + uint32_t key_sel : 2; /* [5: 4] key slot */ + uint32_t xts_mode : 1; /* [6] for xts mode */ + uint32_t aes_region_lock : 1; /* [7] rsvd */ + uint32_t no_segment : 1; /* [8] no segment info */ + uint32_t boot2_enable : 1; /* [9] boot2 enable */ + uint32_t boot2_rollback : 1; /* [10] boot2 rollback */ + uint32_t cpu_master_id : 4; /* [14: 11] master id */ + uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */ + uint32_t crc_ignore : 1; /* [16] ignore crc */ + uint32_t hash_ignore : 1; /* [17] hash ignore */ + uint32_t power_on_mm : 1; /* [18] power on mm */ + uint32_t em_sel : 3; /* [21: 19] em_sel */ + uint32_t cmds_en : 1; /* [22] command spliter enable */ + uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */ + uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */ + uint32_t icache_invalid : 1; /* [29] icache invalid */ + uint32_t dcache_invalid : 1; /* [30] dcache invalid */ + uint32_t fpga_halt_release : 1; /* [31] FPGA halt release function */ + + uint32_t group_image_offset; /* flash controller offset */ + uint32_t aes_region_len; /* aes region length */ + + uint32_t img_len_cnt; /* image length or segment count */ + uint32_t hash[8]; /* hash of the image */ +}; + +struct __attribute__((packed, aligned(4))) hal_cpu_cfg_t { + uint8_t config_enable; /* coinfig this cpu */ + uint8_t halt_cpu; /* halt this cpu */ + uint8_t cache_enable : 1; /* cache setting */ + uint8_t cache_wa : 1; /* cache setting */ + uint8_t cache_wb : 1; /* cache setting */ + uint8_t cache_wt : 1; /* cache setting */ + uint8_t cache_way_dis : 4; /* cache setting */ + uint8_t rsvd; + + uint32_t image_address_offset; /* image address on flash */ + uint32_t boot_entry; /* entry point of the m0 image */ + uint32_t msp_val; /* msp value */ +}; + +struct hal_bootheader_t { + uint32_t magicCode; /*'BFXP'*/ + uint32_t rivison; + struct hal_flash_config flash_cfg; + hal_pll_config clk_cfg; + __PACKED_UNION + { + __PACKED_STRUCT + { + uint32_t sign : 2; /* [1: 0] for sign*/ + uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ + uint32_t key_sel : 2; /* [5: 4] for key sel in boot interface*/ + uint32_t rsvd6_7 : 2; /* [7: 6] for encrypt*/ + uint32_t no_segment : 1; /* [8] no segment info */ + uint32_t cache_enable : 1; /* [9] for cache */ + uint32_t notLoadInBoot : 1; /* [10] not load this img in bootrom */ + uint32_t aes_region_lock : 1; /* [11] aes region lock */ + uint32_t cache_way_disable : 4; /* [15: 12] cache way disable info*/ + uint32_t crcIgnore : 1; /* [16] ignore crc */ + uint32_t hash_ignore : 1; /* [17] hash crc */ + uint32_t halt_cpu1 : 1; /* [18] halt ap */ + uint32_t rsvd19_31 : 13; /* [31:19] rsvd */ + } + bval; + uint32_t wval; + } + bootCfg; + + __PACKED_UNION + { + uint32_t segment_cnt; + uint32_t img_len; + } + img_segment_info; + + uint32_t bootEntry; /* entry point of the image*/ + __PACKED_UNION + { + uint32_t ram_addr; + uint32_t flash_offset; + } + img_start; + + uint8_t hash[HAL_BOOT2_IMG_HASH_SIZE]; /*hash of the image*/ + + uint32_t rsv1; + uint32_t rsv2; + uint32_t crc32; +}; + +typedef struct +{ + uint8_t img_valid; + uint8_t pk_src; + uint8_t rsvd[2]; + + struct hal_basic_cfg_t basic_cfg; + + struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX]; + + uint8_t aes_iv[16 + 4]; //iv in boot header + + uint8_t eckye_x[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header + uint8_t eckey_y[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header + uint8_t eckey_x2[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header + uint8_t eckey_y2[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header + + uint8_t signature[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header + uint8_t signature2[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header + +} boot2_image_config; + +extern boot2_efuse_hw_config g_efuse_cfg; +extern uint8_t g_ps_mode; +extern uint32_t g_user_hash_ignored; +extern struct device *dev_check_hash; + +void hal_boot2_init_clock(void); +uint32_t hal_boot2_custom(void *custom_param); +void hal_boot2_reset_sec_eng(void); +void hal_boot2_sw_system_reset(void); +void hal_boot2_set_psmode_status(uint32_t flag); +uint32_t hal_boot2_get_psmode_status(void); +uint32_t hal_boot2_get_user_fw(void); +void hal_boot2_clr_user_fw(void); +void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg); +int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg); +void hal_boot2_sboot_finish(void); +void hal_boot2_uart_gpio_init(void); +void hal_boot2_debug_uart_gpio_init(void); +#if HAL_BOOT2_SUPPORT_USB_IAP +void hal_boot2_debug_usb_port_init(void); +#endif + +void hal_boot2_debug_uart_gpio_deinit(void); +int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data); +void hal_boot2_clean_cache(void); +BL_Err_Type hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg); +void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt); +void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash); +void hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr); +uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr); +uint32_t hal_boot2_get_grp_count(void); +uint32_t hal_boot2_get_cpu_count(void); +uint32_t hal_boot2_get_feature_flag(void); +uint32_t hal_boot2_get_bootheader_offset(void); +#ifdef __cplusplus +} +#endif +#endif \ No newline at end of file diff --git a/examples/boot2_isp/port/bl702/blsp_boot2_iap_flash.ld b/examples/boot2_isp/port/bl702/blsp_boot2_iap_flash.ld new file mode 100644 index 00000000..4d3246b6 --- /dev/null +++ b/examples/boot2_isp/port/bl702/blsp_boot2_iap_flash.ld @@ -0,0 +1,209 @@ +/**************************************************************************************** +* @file map.txt +* +* @brief This file is the map file (gnuarm or armgcc). +* +* Copyright (C) BouffaloLab 2018 +* +**************************************************************************************** +*/ + +/* configure the CPU type */ +OUTPUT_ARCH( "riscv" ) +/* link with the standard c library */ +INPUT(-lc) +/* link with the standard GCC library */ +INPUT(-lgcc) +/* configure the entry point */ +ENTRY(__start) + +StackSize = 0x1000; /* 4KB */ +HeapSize = 0x0; /* 0KB */ +PROVIDE(__boot2_pass_param_addr = 0x4202DC00); + +MEMORY +{ + xip_memory (rx) : ORIGIN = 0x23000000, LENGTH = 64K + itcm_memory (rx) : ORIGIN = 0x22014000, LENGTH = 16K + dtcm_memory (rx) : ORIGIN = 0x42018000, LENGTH = 4K + ram_memory (!rx) : ORIGIN = 0x42019000/*0x42020000*/, LENGTH = 88K +} + +SECTIONS +{ + PROVIDE(__metal_chicken_bit = 0); + + .text : + { + . = ALIGN(4); + __text_code_start__ = .; + + KEEP (*(SORT_NONE(.init))) + KEEP (*(SORT_NONE(.vector))) + + KEEP (*(.text.metal.init.enter)) + + /* section information for usb desc */ + . = ALIGN(4); + _usb_desc_start = .; + KEEP(*(usb_desc)) + . = ALIGN(4); + _usb_desc_end = .; + + *(EXCLUDE_FILE ( *bl702_uart*.o* *hal_uart*.o* ) .text*) + + *(.rodata) + *(.rodata.*) + *(.srodata) + *(.srodata.*) + + . = ALIGN(4); + __text_code_end__ = .; + } > xip_memory + + . = ALIGN(4); + __itcm_load_addr = .; + + .itcm_region : AT (__itcm_load_addr) + { + . = ALIGN(4); + __tcm_code_start__ = .; + *(.tcm_code.*) + *(.tcm_const.*) + *(.sclock_rlt_code.*) + *(.sclock_rlt_const.*) + *bl702_romapi*.o*(.text) + *bl702_romapi*.o*(.text.*) + *bl702_romapi*.o*(.rodata) + *bl702_romapi*.o*(.rodata.*) + *bl702_romapi*.o*(.srodata) + *bl702_romapi*.o*(.srodata.*) + *bl702_uart*.o* (.text*) + *hal_uart*.o* (.text*) + . = ALIGN(4); + __tcm_code_end__ = .; + + } > itcm_memory + + __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .dtcm_region : AT (__dtcm_load_addr) + { + . = ALIGN(4); + __tcm_data_start__ = .; + + *(.tcm_data) + /* *finger_print.o(.data*) */ + + . = ALIGN(4); + __tcm_data_end__ = .; + } > dtcm_memory + + /* .heap_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of heap sections, and assign + * values to heap symbols later */ + .heap_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + HeapSize; + . = ALIGN(0x4); + } > dtcm_memory + + __HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize; + __HeapSize = HeapSize; + __HeapLimit = __HeapBase + __HeapSize; + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__HeapBase >= __tcm_data_end__, "region RAM overflowed with stack") + + /*************************************************************************/ + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + StackSize; + . = ALIGN(0x4); + } > dtcm_memory + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + + __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + + .system_ram_data_region : AT (__system_ram_load_addr) + { + . = ALIGN(4); + __system_ram_data_start__ = .; + + *(.system_ram) + + . = ALIGN(4); + __system_ram_data_end__ = .; + } > ram_memory + + __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); + + /* Data section */ + RAM_DATA : AT (__ram_load_addr) + { + . = ALIGN(4); + __ram_data_start__ = .; + + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.sdata2) + *(.sdata2.*) + + . = ALIGN(4); + __ram_data_end__ = .; + } > ram_memory + + .bss (NOLOAD) :AT(__bss_start__) + { + . = ALIGN(4); + __bss_start__ = .; + + *(.bss*) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > ram_memory + + .noinit_data (NOLOAD) :AT(__noinit_data_start__) + { + . = ALIGN(4); + __noinit_data_start__ = .; + + *(.noinit_data*) + + . = ALIGN(4); + __noinit_data_end__ = .; + } > ram_memory + + .nocache_noinit_ram_region (NOLOAD) : AT(__nocache_ram_data_start__) + { + . = ALIGN(4); + __nocache_ram_data_start__ = .; + + *(.nocache_noinit_ram) + + . = ALIGN(4); + __nocache_ram_data_end__ = .; + } > ram_memory + + +} + diff --git a/examples/boot2_isp/port/bl808/bflb_port_boot2.c b/examples/boot2_isp/port/bl808/bflb_port_boot2.c new file mode 100644 index 00000000..f97a2637 --- /dev/null +++ b/examples/boot2_isp/port/bl808/bflb_port_boot2.c @@ -0,0 +1,628 @@ +#include "bflb_port_boot2.h" +#include "bflb_flash.h" +#include "bl808_ef_ctrl.h" +#include "bl808_ef_cfg.h" +#include "bl808_hbn.h" +#include "bl808_glb.h" +#include "bl808_xip_sflash.h" +#include "bl808_tzc_sec.h" +#include "bflb_gpio.h" +#include "softcrc.h" +#include "bl808_psram_uhs.h" +#include "bflb_efuse.h" + +/****************************************************************************/ /** + * @brief init clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_init_clock(void) +{ + CPU_Reset_MTimer(); + /* set mtimer clock 1M */ + CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000000 - 1); + + GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0); +} + +/****************************************************************************/ /** + * @brief hal_boot2_custom + * + * @param custom_param + * + * @return 0 + * +*******************************************************************************/ +uint32_t hal_boot2_custom(void *custom_param) +{ + //EF_Ctrl_Trim_DCDC_And_LDO(); + AON_Trim_USB20_RCAL(); + //GLB_Readjust_LDO18IO_Vout(); + if (((g_efuse_cfg.dev_info & HAL_BOOT2_PSRAM_INFO_MASK) >> HAL_BOOT2_PSRAM_INFO_POS) != 0) { + GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M); + Psram_UHS_x16_Init(2000); + Tzc_Sec_PSRAMA_Access_Release(); + + /* Flush i-cache in case branch prediction logic is wrong when + psram is not inited by hal_boot2_custom but cpu has already prefetch psram */ + __ISB(); + } + return 0; +} + +/****************************************************************************/ /** + * @brief hal_boot2_get_efuse_cfg + * + * @param efuse_cfg + * + * @return None + * +*******************************************************************************/ +void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg) +{ + uint32_t timeout_cnt = 0; + uint32_t i = 0; + struct boot_efuse_sw_cfg0_t sw_cfg0; + + + /* get hw cfg (signature and aes type) */ + //EF_Ctrl_Read_Secure_Boot((EF_Ctrl_SF_AES_Type *)efuse_cfg->encrypted); + bflb_efuse_read_secure_boot((uint8_t *) efuse_cfg->encrypted, (uint8_t *) efuse_cfg->encrypted); + + for (i = 0; i < HAL_BOOT2_CPU_GROUP_MAX; i++) { + if (efuse_cfg->encrypted[i] == EF_CTRL_SF_AES_192) { + efuse_cfg->encrypted[i] = SF_CTRL_AES_192BITS + 1; + } else if (efuse_cfg->encrypted[i] == EF_CTRL_SF_AES_256) { + efuse_cfg->encrypted[i] = SF_CTRL_AES_256BITS + 1; + } + } + + /* get sw uasge 0 */ + //EF_Ctrl_Read_Sw_Usage(0, (uint32_t *)&sw_cfg0); + bflb_efuse_read_sw_usage(0, (uint32_t *) &sw_cfg0); + /* get sw uasge 1 */ + //EF_Ctrl_Read_Sw_Usage(1, &sw_cfg1); + + for (i = 0; i < HAL_BOOT2_CPU_GROUP_MAX; i++) { + efuse_cfg->sign[i] = ((struct boot_efuse_sw_cfg0_t)sw_cfg0).sign_cfg; + } + for (i = 1; i < HAL_BOOT2_CPU_GROUP_MAX; i++) { + efuse_cfg->encrypted[i] = EF_CTRL_SF_AES_NONE; + } + + efuse_cfg->hbn_check_sign = (uint8_t)(sw_cfg0.hbn_check_sign); + efuse_cfg->sf_pin_cfg = (uint8_t)(sw_cfg0.sf_pin_cfg); + efuse_cfg->uart_download_cfg = (uint8_t)(sw_cfg0.uart_download_cfg); + efuse_cfg->keep_dbg_port_closed = (uint8_t)(sw_cfg0.keep_dbg_port_closed); + efuse_cfg->boot_pin_cfg = (uint8_t)(sw_cfg0.boot_pin_cfg); + + /* get device info */ //FixZc + //EF_Ctrl_Get_Chip_Info((Efuse_Chip_Info_Type *)&efuse_cfg->dev_info); + + /* get chip id */ + //EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id); + bflb_efuse_get_chipid(efuse_cfg->chip_id); + + /* get public key hash */ + //EF_Ctrl_Read_AES_Key(0, (uint32_t *)efuse_cfg->pk_hash_cpu0, HAL_BOOT2_PK_HASH_SIZE / 4); + bflb_efuse_read_aes_key(0, (uint8_t *)efuse_cfg->pk_hash_cpu0, HAL_BOOT2_PK_HASH_SIZE / 4); + //EF_Ctrl_Read_AES_Key(8, (uint32_t *)efuse_cfg->pk_hash_cpu1, HAL_BOOT2_PK_HASH_SIZE / 4); + bflb_efuse_read_aes_key(8, (uint8_t *)efuse_cfg->pk_hash_cpu1, HAL_BOOT2_PK_HASH_SIZE / 4); +} + +/****************************************************************************/ /** + * @brief reset sec eng clock + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_reset_sec_eng(void) +{ + GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SEC_ENG); + //Sec_Eng_Group0_Request_SHA_Access(); + //Sec_Eng_Group0_Request_AES_Access(); + //Sec_Eng_Group0_Request_Trng_Access(); + //Sec_Eng_Trng_Enable(); + GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M); +} + +/****************************************************************************/ /** + * @brief system soft reset + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_sw_system_reset(void) +{ + GLB_SW_System_Reset(); +} + +/****************************************************************************/ /** + * @brief hal_boot2_set_psmode_status + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_set_psmode_status(uint32_t flag) +{ + HBN_Set_Status_Flag(flag); +} + +/****************************************************************************/ /** + * @brief hal_boot2_get_psmode_status + * + * @param None + * + * @return status flag + * +*******************************************************************************/ +uint32_t hal_boot2_get_psmode_status(void) +{ + return HBN_Get_Status_Flag(); +} + +/****************************************************************************/ /** + * @brief hal_boot2_get_user_fw + * + * @param None + * + * @return None + * +*******************************************************************************/ +uint32_t hal_boot2_get_user_fw(void) +{ + return BL_RD_WORD(HBN_BASE + HBN_RSV0_OFFSET); +} + +/****************************************************************************/ /** + * @brief hal_boot2_clr_user_fw + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_clr_user_fw(void) +{ + uint32_t *p = (uint32_t *)(HBN_BASE + HBN_RSV0_OFFSET); + *p = 0; +} + +/****************************************************************************/ /** + * @brief hal_boot2_sboot_finish + * + * @param None + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION hal_boot2_sboot_finish(void) +{ + // uint32_t tmpVal; + // if (!g_efuse_cfg.keep_dbg_port_closed) { + // /* only after this, JTAG is really open */ + // tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL); + // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, 0xf); + // BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal); + // } +} + +/** + * @brief hal_boot2_pll_init + * + * @return + */ +void hal_boot2_uart_gpio_init(void) +{ + struct bflb_device_s *gpio; + + gpio = bflb_device_get_by_name("gpio"); + + bflb_gpio_uart_init(gpio, GPIO_PIN_14, GPIO_UART_FUNC_UART0_TX); + bflb_gpio_uart_init(gpio, GPIO_PIN_15, GPIO_UART_FUNC_UART0_RX); +} + +/****************************************************************************/ /** + * @brief uart deinit + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_debug_uart_gpio_init(void) +{ + GLB_GPIO_Cfg_Type cfg; + + cfg.pullType = GPIO_PULL_NONE; + cfg.drive = 0; + cfg.smtCtrl = 1; + + /* OTP_BOOTLOG_PIN_CFG() */ + /* 0 -> GPIO39 -> qfn68 */ + /* 1 -> GPIO8 -> qfn88 */ + if (0 == g_efuse_cfg.boot_pin_cfg) { + cfg.gpioPin = GLB_GPIO_PIN_39; + cfg.gpioFun = GPIO_FUN_UART; + cfg.gpioMode = GPIO_MODE_OUTPUT; + GLB_GPIO_Init(&cfg); + + GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, 1); + GLB_UART_Fun_Sel(GLB_UART_SIG_9, GLB_UART_SIG_FUN_UART1_TXD); + GLB_UART_Fun_Sel((GLB_UART_SIG_Type)GLB_UART_SIG_FUN_UART1_TXD, (GLB_UART_SIG_FUN_Type)GLB_UART_SIG_9); + + } else { + cfg.gpioPin = GLB_GPIO_PIN_8; + cfg.gpioFun = GPIO_FUN_UART; + cfg.gpioMode = GPIO_MODE_OUTPUT; + GLB_GPIO_Init(&cfg); + + GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO0_GPIO11, 0); + GLB_UART_Fun_Sel(GLB_UART_SIG_8, GLB_UART_SIG_FUN_UART1_TXD); + GLB_UART_Fun_Sel((GLB_UART_SIG_Type)GLB_UART_SIG_FUN_UART1_TXD, (GLB_UART_SIG_FUN_Type)GLB_UART_SIG_8); + } +} + +/****************************************************************************/ /** + * @brief usb gpio init + * + * @param None + * + * @return None + * +*******************************************************************************/ +#if HAL_BOOT2_SUPPORT_USB_IAP +void hal_boot2_debug_usb_port_init(void) +{ +} +#endif + +/****************************************************************************/ /** + * @brief uart gpio deinit + * + * @param None + * + * @return None + * +*******************************************************************************/ +void hal_boot2_debug_uart_gpio_deinit(void) +{ +} + +/****************************************************************************/ /** + * @brief Check bootheader crc + * + * @param data: bootheader data pointer + * + * @return boot_error_code type + * +*******************************************************************************/ +static uint32_t hal_boot_check_bootheader(struct hal_bootheader_t *header) +{ + uint32_t crc_pass = 0; + uint32_t crc; + + if (header->basic_cfg.crc_ignore == 1 && header->crc32 == HAL_BOOT2_DEADBEEF_VAL) { + //MSG("Crc ignored\r\n"); + crc_pass = 1; + } else { + crc = BFLB_Soft_CRC32((uint8_t *)header, sizeof(struct hal_bootheader_t) - sizeof(header->crc32)); + + if (header->crc32 == crc) { + crc_pass = 1; + } + } + return crc_pass; +} + +/****************************************************************************/ /** + * @brief Check if the input public key is the same as burned in the efuse + * + * @param g_boot_img_cfg: Boot image config pointer + * @param data: Image data pointer + * + * @return boot_error_code type + * +*******************************************************************************/ +int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data) +{ + struct hal_bootheader_t *header = (struct hal_bootheader_t *)data; + uint32_t crc_pass = 0; + uint32_t i = 0; + uint32_t *phash = (uint32_t *)header->basic_cfg.hash; + + crc_pass = hal_boot_check_bootheader(header); + + if (!crc_pass) { + //MSG_ERR("bootheader crc error\r\n"); + //blsp_dump_data((uint8_t *)&crc, 4); + return 0x0204; + } + + if (header->basic_cfg.notload_in_bootrom) { + return 0x0202; + } + + /* Get which CPU's img it is*/ + for (i = 0; i < HAL_BOOT2_CPU_MAX; i++) { + if (0 == memcmp((void *)&header->magiccode, HAL_BOOT2_CPU0_MAGIC, + sizeof(header->magiccode))) { + break; + } else if (0 == memcmp((void *)&header->magiccode, HAL_BOOT2_CPU1_MAGIC, + sizeof(header->magiccode))) { + break; + } + } + + if (i == HAL_BOOT2_CPU_MAX) { + /* No cpu img magic match */ + //MSG_ERR("Magic code error\r\n"); + return 0x0203; + } + + if (boot_img_cfg == NULL) { + return 0; + } + + boot_img_cfg->pk_src = i; + boot_img_cfg->img_valid = 0; + + arch_memcpy_fast(&boot_img_cfg->basic_cfg, &header->basic_cfg, + sizeof(header->basic_cfg)); + + /* Check encrypt and sign match*/ + if (g_efuse_cfg.encrypted[i] != boot_img_cfg->basic_cfg.encrypt_type) { + if (boot_img_cfg->basic_cfg.xts_mode == 0) { + //("Encrypt not fit\r\n"); + return 0x0205; + } + } + + if (g_efuse_cfg.sign[i] != boot_img_cfg->basic_cfg.sign_type) { + //MSG_ERR("sign not fit\r\n"); + boot_img_cfg->basic_cfg.sign_type = g_efuse_cfg.sign[i]; + return 0x0206; + } + + if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) { + /* In HBN Mode, if user select to ignore hash and sign*/ + boot_img_cfg->basic_cfg.hash_ignore = 1; + } else if ((boot_img_cfg->basic_cfg.hash_ignore == 1 && *phash != HAL_BOOT2_DEADBEEF_VAL) || + g_efuse_cfg.sign[i] != 0) { + /* If signed or user not really want to ignore, hash can't be ignored*/ + boot_img_cfg->basic_cfg.hash_ignore = 0; + } + + if (g_user_hash_ignored) { + boot_img_cfg->basic_cfg.hash_ignore = 1; + } + + if (boot_img_cfg->basic_cfg.img_len_cnt == 0) { + return 0x0207; + } + + arch_memcpy_fast(&boot_img_cfg->cpu_cfg, &header->cpu_cfg, + sizeof(header->cpu_cfg)); + return 0; +} + +/****************************************************************************/ /** + * @brief clean cache + * + * @param + * + * @return cache set result + * +*******************************************************************************/ +void ATTR_TCM_SECTION hal_boot2_clean_cache(void) +{ + L1C_DCache_Clean_Invalid_All(); + L1C_ICache_Invalid_All(); +} + +/****************************************************************************/ /** + * @brief set cache + * + * @param cont_read: continue read mode + * boot_img_cfg: cache set param + * + * @return cache set result + * +*******************************************************************************/ +BL_Err_Type ATTR_TCM_SECTION hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg) +{ + bflb_flash_set_cache(cont_read, boot_img_cfg->cpu_cfg[0].cache_enable, + boot_img_cfg->cpu_cfg[0].cache_way_dis, + boot_img_cfg->basic_cfg.group_image_offset); + + return SUCCESS; +} + +/****************************************************************************/ /** + * @brief get the ram image name and count + * + * @param img_name: ram image name in partition + * @param ram_img_cnt: ram image count that support boot from flash + * + * @return None + * +*******************************************************************************/ +void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt) +{ + *ram_img_cnt = 5; + img_name[0] = "Imgload"; + img_name[1] = "SBI"; + img_name[2] = "Kernel"; + img_name[3] = "Rootfs"; + img_name[4] = "DTB"; +} + +/****************************************************************************/ /** + * @brief get the ram image info + * + * @param data: bootheader information + * @param image_offset: ram image offset in flash(from of bootheader) + * @param img_len: ram image length + * @param hash: pointer to hash pointer + * + * @return None + * +*******************************************************************************/ +void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash) +{ + struct hal_bootheader_t *header = (struct hal_bootheader_t *)data; + uint32_t crc_pass = 0; + *img_len = 0; + uint8_t *phash = *hash; + uint8_t hash_ignore = 1; + + crc_pass = hal_boot_check_bootheader(header); + + if (!crc_pass) { + return; + } + if (0 != arch_memcmp((void *)&header->magiccode, HAL_BOOT2_CPU0_MAGIC, sizeof(header->magiccode)) && + 0 != arch_memcmp((void *)&header->magiccode, HAL_BOOT2_CPU1_MAGIC, sizeof(header->magiccode))) { + return; + } + + /* for ram image, it always download in iot tab, so + it share the same group with core 0 but use different image offset and + boot entry */ + *image_offset = 4096 * 1; //bootheader->basic_cfg.group_image_offset; + *img_len = header->basic_cfg.img_len_cnt; + + if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) { + /* In HBN Mode, if user select to ignore hash and sign*/ + hash_ignore = 1; + } else if ((header->basic_cfg.hash_ignore == 1 && header->basic_cfg.hash[0] != HAL_BOOT2_DEADBEEF_VAL) || + g_efuse_cfg.sign[0] != 0) { + /* If signed or user not really want to ignore, hash can't be ignored*/ + hash_ignore = 0; + } + + if (hash_ignore == 1) { + *hash = NULL; + } else { + arch_memcpy(phash, header->basic_cfg.hash, sizeof(header->basic_cfg.hash)); + } +} + +/****************************************************************************/ /** + * @brief release other cpu to boot up + * + * @param core: core number + * @param boot_addr: boot address + * + * @return None + * +*******************************************************************************/ +void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr) +{ + GLB_Set_CPU_Reset_Address(core, boot_addr); + GLB_Release_CPU(core); +} + +/****************************************************************************/ /** + * @brief get xip address according to flash addr + * + * @param flash_addr: flash address + * + * @return XIP Address + * +*******************************************************************************/ +uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr) +{ + uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0); + if (flash_addr >= img_offset) { + return BL808_FLASH_XIP_BASE + (flash_addr - img_offset); + } else { + return 0; + } +} + +/****************************************************************************/ /** + * @brief get if multi-group + * + * @param None + * + * @return 1 for multi-group 0 for not + * +*******************************************************************************/ +uint32_t hal_boot2_get_grp_count(void) +{ + return 1; +} + +/****************************************************************************/ /** + * @brief get cpu count + * + * @param None + * + * @return 1 for multi-group 0 for not + * +*******************************************************************************/ +uint32_t hal_boot2_get_cpu_count(void) +{ + return 3; +} + +/****************************************************************************/ /** + * @brief get cpu count + * + * @param None + * + * @return 1 for multi-group 0 for not + * +*******************************************************************************/ +uint32_t ATTR_TCM_SECTION hal_boot2_get_feature_flag(void) +{ + return HAL_BOOT2_MP_FLAG; +} + +/****************************************************************************/ /** + * @brief get boot header offset + * + * @param None + * + * @return bootheader offset + * +*******************************************************************************/ +uint32_t hal_boot2_get_bootheader_offset(void) +{ + return 0x0; +} +/****************************************************************************/ /** + * @brief hal_reboot_config + * + * @param boot source + * + * @return bootheader offset + * +*******************************************************************************/ +void hal_reboot_config(hal_reboot_cfg_t rbot) +{ + switch(rbot){ + case HAL_REBOOT_AS_BOOTPIN: + HBN_Set_Hand_Off_Config(0); + break; + case HAL_REBOOT_FROM_INTERFACE: + HBN_Set_Hand_Off_Config(1); + break; + case HAL_REBOOT_FROM_MEDIA: + HBN_Set_Hand_Off_Config(2); + break; + default : + HBN_Set_Hand_Off_Config(0); + break; + } +} diff --git a/examples/boot2_isp/port/bl808/bflb_port_boot2.h b/examples/boot2_isp/port/bl808/bflb_port_boot2.h new file mode 100644 index 00000000..eadb683e --- /dev/null +++ b/examples/boot2_isp/port/bl808/bflb_port_boot2.h @@ -0,0 +1,330 @@ +/** + * ***************************************************************************** + * @file bflb_port_boot2.h + * @version 0.1 + * @date 2022-12-13 + * @brief + * ***************************************************************************** + * @attention + * + *

© COPYRIGHT(c) 2020 Bouffalo Lab

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of Bouffalo Lab nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * ***************************************************************************** + */ +#ifndef __BFLB_PORT_BOOT2_H__ +#define __BFLB_PORT_BOOT2_H__ + +#include "bl808_sflash.h" +#include "bl808_glb.h" + +#define HAL_PLL_CFG_MAGICCODE "PCFG" + +#define HAL_BOOT2_PK_HASH_SIZE 256 / 8 +#define HAL_BOOT2_IMG_HASH_SIZE 256 / 8 +#define HAL_BOOT2_ECC_KEYXSIZE 256 / 8 +#define HAL_BOOT2_ECC_KEYYSIZE 256 / 8 +#define HAL_BOOT2_SIGN_MAXSIZE (2048 / 8) +#define HAL_BOOT2_DEADBEEF_VAL 0xdeadbeef +#define HAL_BOOT2_CPU0_MAGIC "BFNP" +#define HAL_BOOT2_CPU1_MAGIC "BFAP" +#define HAL_BOOT2_CP_FLAG 0x02 +#define HAL_BOOT2_MP_FLAG 0x01 +#define HAL_BOOT2_SP_FLAG 0x00 + +#define HAL_BOOT2_SUPPORT_DECOMPRESS 1 /* 1 support decompress, 0 not support */ +#define HAL_BOOT2_SUPPORT_USB_IAP 0 /* 1 support IAP, 0 not support */ +#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM 0 /* 1 support eflash loader ram, 0 not support */ +#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 0 /* 1 support eflash loader flash, 0 not support */ +#define HAL_BOOT2_SUPPORT_SIGN_ENCRYPT 1 /* 1 support sign and encrypt, 0 not support */ + +#define HAL_BOOT2_CPU_GROUP_MAX 1 +#define HAL_BOOT2_CPU_MAX 3 +#define HAL_BOOT2_RAM_IMG_COUNT_MAX 0 + +#define HAL_BOOT2_FW_IMG_OFFSET_AFTER_HEADER 4 * 1024 +#define HAL_BOOT2_MFG_START_REQUEST_OFFSET 8 * 1024 + +#define HAL_BOOT2_PSRAM_INFO_MASK (0xff0000) +#define HAL_BOOT2_PSRAM_INFO_POS (16) + +typedef enum { + HAL_REBOOT_AS_BOOTPIN, /*!< reboot as bootpin level */ + HAL_REBOOT_FROM_INTERFACE, /*!< reboot from interface, download mode */ + HAL_REBOOT_FROM_MEDIA, /*!< reboot from media, running mode */ + HAL_REBOOT_MAX /*!< reboot max value */ +} hal_reboot_cfg_t; + +struct __attribute__((packed, aligned(4))) boot_efuse_sw_cfg0_t { + uint32_t bootrom_protect : 1; /* ef_sw_usage_0 bit [0] */ + uint32_t uart_log_disable : 1; /* ef_sw_usage_0 bit [1] */ + uint32_t boot_pin_cfg : 1; /* ef_sw_usage_0 bit [2] */ + //uint32_t dbg_pin_cfg : 1; /* ef_sw_usage_0 bit [3] */ + uint32_t uart_download_cfg : 1; /* ef_sw_usage_0 bit [3] */ + + uint32_t mediaboot_disable : 1; /* ef_sw_usage_0 bit [4] */ + uint32_t uartboot_disable : 1; /* ef_sw_usage_0 bit [5] */ + uint32_t usbboot_enable : 1; /* ef_sw_usage_0 bit [6] */ + uint32_t uart_log_reopen : 1; /* ef_sw_usage_1 bit [7] */ + + uint32_t sign_cfg : 1; /* ef_sw_usage_0 bit [8] */ + uint32_t dcache_disable : 1; /* ef_sw_usage_0 bit [9] */ + uint32_t jtag_cfg : 2; /* ef_sw_usage_0 bit [11:10] */ + + uint32_t fix_key_sel : 1; /* ef_sw_usage_0 bit [12] */ + + uint32_t sdh_en : 1; /* ef_sw_usage_1 bit [13] */ + uint32_t sf_pin_cfg : 5; /* ef_sw_usage_0 bit [18:14] */ + uint32_t boot_level_revert : 1; /* ef_sw_usage_0 bit [19] */ + + uint32_t boot_pin_dly : 2; /* ef_sw_usage_0 bit [21:20] */ + uint32_t ldo_trim_enable : 1; /* ef_sw_usage_0 bit [22] */ + uint32_t trim_enable : 1; /* ef_sw_usage_0 bit [23] */ + + uint32_t no_hd_boot_en : 1; /* ef_sw_usage_0 bit [24] */ + uint32_t flash_power_delay : 2; /* ef_sw_usage_0 bit [26:25] */ + uint32_t tz_boot : 1; /* ef_sw_usage_0 bit [27] */ + + uint32_t encrypted_tz_boot : 1; /* ef_sw_usage_0 bit [28] */ + uint32_t hbn_check_sign : 1; /* ef_sw_usage_0 bit [29] */ + uint32_t keep_dbg_port_closed : 1; /* ef_sw_usage_0 bit [30] */ + uint32_t hbn_jump_disable : 1; /* ef_sw_usage_0 bit [31] */ +}; + +struct __attribute__((packed, aligned(4))) boot_efuse_sw_cfg1_t { + uint32_t xtal_type : 3; /* ef_sw_usage_1 bit [2:0] */ + uint32_t wifipll_pu : 1; /* ef_sw_usage_1 bit [3] */ + + uint32_t aupll_pu : 1; /* ef_sw_usage_1 bit [4] */ + uint32_t cpupll_pu : 1; /* ef_sw_usage_1 bit [5] */ + uint32_t mipipll_pu : 1; /* ef_sw_usage_1 bit [6] */ + uint32_t uhspll_pu : 1; /* ef_sw_usage_1 bit [7] */ + + uint32_t mcu_clk : 3; /* ef_sw_usage_1 bit [10:8] */ + uint32_t mcu_clk_div : 1; /* ef_sw_usage_1 bit [11] */ + + uint32_t mcu_pbclk_div : 2; /* ef_sw_usage_1 bit [13:12] */ + uint32_t lp_div : 1; /* ef_sw_usage_1 bit [14] */ + uint32_t dsp_clk : 2; /* ef_sw_usage_1 bit [16:15] */ + uint32_t dsp_clk_div : 1; /* ef_sw_usage_1 bit [17] */ + uint32_t dsp_pbclk : 2; /* ef_sw_usage_1 bit [19:18] */ + + uint32_t emi_clk : 2; /* ef_sw_usage_1 bit [21:20] */ + uint32_t emi_clk_div : 1; /* ef_sw_usage_1 bit [22] */ + uint32_t flash_clk_type : 3; /* ef_sw_usage_1 bit [25:23] */ + uint32_t flash_clk_div : 1; /* ef_sw_usage_1 bit [26] */ + uint32_t ldo18flash_bypass_cfg : 1; /* ef_sw_usage_1 bit [27] */ + uint32_t bootlog_pin_cfg : 1; /* ef_sw_usage_1 bit [28] */ + + uint32_t abt_offset : 1; /* ef_sw_usage_1 bit [29] */ + uint32_t boot_pull_cfg : 1; /* ef_sw_usage_1 bit [30] */ + uint32_t usb_if_int_disable : 1; /* ef_sw_usage_1 bit [31] */ +}; + +typedef struct +{ + uint8_t encrypted[HAL_BOOT2_CPU_GROUP_MAX]; + uint8_t sign[HAL_BOOT2_CPU_GROUP_MAX]; + uint8_t hbn_check_sign; + uint8_t rsvd[3]; + uint8_t chip_id[8]; + uint8_t pk_hash_cpu0[HAL_BOOT2_PK_HASH_SIZE]; + uint8_t pk_hash_cpu1[HAL_BOOT2_PK_HASH_SIZE]; + uint8_t uart_download_cfg; + uint8_t sf_pin_cfg; + uint8_t keep_dbg_port_closed; + uint8_t boot_pin_cfg; + uint32_t dev_info; +} boot2_efuse_hw_config; + +struct __attribute__((packed, aligned(4))) hal_flash_config { + uint32_t magicCode; /*'FCFG'*/ + SPI_Flash_Cfg_Type cfg; + uint32_t crc32; +}; + +struct __attribute__((packed, aligned(4))) hal_sys_clk_config { + uint8_t xtal_type; + uint8_t mcu_clk; + uint8_t mcu_clk_div; + uint8_t mcu_bclk_div; + + uint8_t mcu_pbclk_div; + uint8_t lp_div; + uint8_t dsp_clk; + uint8_t dsp_clk_div; + + uint8_t dsp_bclk_div; + uint8_t dsp_pbclk; + uint8_t dsp_pbclk_div; + uint8_t emi_clk; + + uint8_t emi_clk_div; + uint8_t flash_clk_type; + uint8_t flash_clk_div; + uint8_t wifipll_pu; + + uint8_t aupll_pu; + uint8_t cpupll_pu; + uint8_t mipipll_pu; + uint8_t uhspll_pu; +}; + +typedef struct { + uint32_t magiccode; + struct hal_sys_clk_config cfg; + uint32_t crc32; +} hal_pll_config; + +struct __attribute__((packed, aligned(4))) hal_basic_cfg_t { + uint32_t sign_type : 2; /* [1: 0] for sign */ + uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ + uint32_t key_sel : 2; /* [5: 4] key slot */ + uint32_t xts_mode : 1; /* [6] for xts mode */ + uint32_t aes_region_lock : 1; /* [7] rsvd */ + uint32_t no_segment : 1; /* [8] no segment info */ + uint32_t boot2_enable : 1; /* [9] boot2 enable */ + uint32_t boot2_rollback : 1; /* [10] boot2 rollback */ + uint32_t cpu_master_id : 4; /* [14: 11] master id */ + uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */ + uint32_t crc_ignore : 1; /* [16] ignore crc */ + uint32_t hash_ignore : 1; /* [17] hash ignore */ + uint32_t power_on_mm : 1; /* [18] power on mm */ + uint32_t em_sel : 3; /* [21: 19] em_sel */ + uint32_t cmds_en : 1; /* [22] command spliter enable */ + uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */ + uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */ + uint32_t icache_invalid : 1; /* [29] icache invalid */ + uint32_t dcache_invalid : 1; /* [30] dcache invalid */ + uint32_t fpga_halt_release : 1; /* [31] FPGA halt release function */ + + uint32_t group_image_offset; /* flash controller offset */ + uint32_t aes_region_len; /* aes region length */ + + uint32_t img_len_cnt; /* image length or segment count */ + uint32_t hash[8]; /* hash of the image */ +}; + +struct __attribute__((packed, aligned(4))) hal_cpu_cfg_t { + uint8_t config_enable; /* coinfig this cpu */ + uint8_t halt_cpu; /* halt this cpu */ + uint8_t cache_enable : 1; /* cache setting */ + uint8_t cache_wa : 1; /* cache setting */ + uint8_t cache_wb : 1; /* cache setting */ + uint8_t cache_wt : 1; /* cache setting */ + uint8_t cache_way_dis : 4; /* cache setting */ + uint8_t rsvd; + + uint32_t cache_range_h; /* cache range high */ + uint32_t cache_range_l; /* cache range low */ + + uint32_t image_address_offset; /* image address on flash */ /*image_address_offset*/ + uint32_t boot_entry; /* entry point of the m0 image */ + uint32_t msp_val; /* msp value */ +}; + +struct __attribute__((packed, aligned(4))) hal_patch_cfg_t { + uint32_t addr; + uint32_t value; +}; + +struct __attribute__((packed, aligned(4))) hal_bootheader_t { + uint32_t magiccode; + uint32_t rivison; + + struct hal_flash_config flashCfg; + hal_pll_config clkCfg; + + struct hal_basic_cfg_t basic_cfg; + + struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX]; + + uint32_t boot2_pt_table_0; /* address of partition table 0 */ + uint32_t boot2_pt_table_1; /* address of partition table 1 */ + + uint32_t flashCfgTableAddr; /* address of flashcfg table list */ + uint32_t flashCfgTableLen; /* flashcfg table list len */ + + struct hal_patch_cfg_t patch_on_read[4]; /* do patch when read flash */ + struct hal_patch_cfg_t patch_on_jump[4]; /* do patch when jump */ + + uint32_t rsvd[5]; + + uint32_t crc32; +}; + +typedef struct +{ + uint8_t img_valid; + uint8_t pk_src; + uint8_t rsvd[2]; + + struct hal_basic_cfg_t basic_cfg; + + struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX]; + + uint8_t aes_iv[16 + 4]; //iv in boot header + + uint8_t eckye_x[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header + uint8_t eckey_y[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header + uint8_t eckey_x2[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header + uint8_t eckey_y2[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header + + uint8_t signature[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header + uint8_t signature2[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header + +} boot2_image_config; + +extern boot2_efuse_hw_config g_efuse_cfg; +extern uint8_t g_ps_mode; +extern uint32_t g_user_hash_ignored; +extern struct device *dev_check_hash; + +void hal_boot2_init_clock(void); +uint32_t hal_boot2_custom(void *custom_param); +void hal_boot2_reset_sec_eng(void); +void hal_boot2_sw_system_reset(void); +void hal_boot2_set_psmode_status(uint32_t flag); +uint32_t hal_boot2_get_psmode_status(void); +uint32_t hal_boot2_get_user_fw(void); +void hal_boot2_clr_user_fw(void); +void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg); +int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg); +void hal_boot2_sboot_finish(void); +void hal_boot2_uart_gpio_init(void); +void hal_boot2_debug_uart_gpio_init(void); +void hal_boot2_debug_uart_gpio_deinit(void); +int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data); +void hal_boot2_clean_cache(void); +BL_Err_Type hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg); +void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt); +void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash); +void hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr); +uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr); +uint32_t hal_boot2_get_grp_count(void); +uint32_t hal_boot2_get_cpu_count(void); +uint32_t hal_boot2_get_feature_flag(void); +uint32_t hal_boot2_get_bootheader_offset(void); +void hal_reboot_config(hal_reboot_cfg_t rbot); +#endif diff --git a/examples/boot2_isp/port/bl808/blsp_boot2_iap_flash.ld b/examples/boot2_isp/port/bl808/blsp_boot2_iap_flash.ld new file mode 100644 index 00000000..18d07ee3 --- /dev/null +++ b/examples/boot2_isp/port/bl808/blsp_boot2_iap_flash.ld @@ -0,0 +1,266 @@ +/**************************************************************************************** +* @file flash.ld +* +* @brief This file is the link script file (gnuarm or armgcc). +* +* Copyright (C) BouffaloLab 2021 +* +**************************************************************************************** +*/ + +/* configure the CPU type */ +OUTPUT_ARCH( "riscv" ) +/* link with the standard c library */ +INPUT(-lc) +/* link with the standard GCC library */ +INPUT(-lgcc) +/* configure the entry point */ +ENTRY(__start) + +StackSize = 0x0400; /* 1KB */ +HeapMinSize = 0x1000; /* 4KB */ +/* ToDo */ +PROVIDE(__boot2_pass_param_addr = 0x62057C00);/* 0x42030000+159*1024 */ +MEMORY +{ + xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 48K + itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 48K + dtcm_memory (rx) : ORIGIN = 0x6202C000, LENGTH = 4K + nocache_ram_memory (!rx) : ORIGIN = 0x2202D000, LENGTH = 84K + ram_memory (!rx) : ORIGIN = 0x62042000, LENGTH = 16K +} + +SECTIONS +{ + + .text : + { + . = ALIGN(4); + __text_code_start__ = .; + KEEP (*(SORT_NONE(.init))) + KEEP (*(SORT_NONE(.vector))) + KEEP(*startup*.*o(*.text*)) + KEEP (*(SORT_NONE(_start))) + KEEP (*(SORT_NONE(Reset_Handler))) + + *(.text) + *(.text.*) + + /* section information for shell */ + . = ALIGN(4); + __fsymtab_start = .; + KEEP(*(FSymTab)) + __fsymtab_end = .; + + . = ALIGN(4); + __vsymtab_start = .; + KEEP(*(VSymTab)) + __vsymtab_end = .; + + /* section information for usb desc */ + . = ALIGN(4); + _usb_desc_start = .; + KEEP(*(usb_desc)) + . = ALIGN(4); + _usb_desc_end = .; + + /*put .rodata**/ + *(EXCLUDE_FILE( *bl808_glb*.o* \ + *bl808_glb_gpio*.o* \ + *bl808_pds*.o* \ + *bl808_aon*.o* \ + *bl808_hbn*.o* \ + *bl808_l1c*.o* \ + *bl808_common*.o* \ + *bl808_clock*.o* \ + *bl808_ef_ctrl*.o* \ + *bl808_sf_cfg*.o* \ + *bl808_sf_ctrl*.o* \ + *bl808_sflash*.o* \ + *bl808_xip_sflash*.o* \ + *bl808_romapi_patch*.o* ) .rodata*) + + *(.srodata) + *(.srodata.*) + + . = ALIGN(4); + __text_code_end__ = .; + } > xip_memory + + . = ALIGN(4); + __itcm_load_addr = .; + + .itcm_region : AT (__itcm_load_addr) + { + . = ALIGN(4); + __tcm_code_start__ = .; + + *(.tcm_code.*) + *(.tcm_const.*) + *(.sclock_rlt_code.*) + *(.sclock_rlt_const.*) + + *bl808_glb*.o*(.rodata*) + *bl808_glb_gpio*.o*(.rodata*) + *bl808_pds*.o*(.rodata*) + *bl808_aon*.o*(.rodata*) + *bl808_hbn*.o*(.rodata*) + *bl808_l1c*.o*(.rodata*) + *bl808_common*.o*(.rodata*) + *bl808_clock*.o*(.rodata*) + *bl808_ef_ctrl*.o*(.rodata*) + *bl808_sf_cfg*.o*(.rodata*) + *bl808_sf_ctrl*.o*(.rodata*) + *bl808_sflash*.o*(.rodata*) + *bl808_xip_sflash*.o*(.rodata*) + *bl808_romapi_patch*.o*(.rodata*) + + . = ALIGN(4); + __tcm_code_end__ = .; + } > itcm_memory + + __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); + + .dtcm_region : AT (__dtcm_load_addr) + { + . = ALIGN(4); + __tcm_data_start__ = .; + + *(.tcm_data) + /* *finger_print.o(.data*) */ + + . = ALIGN(4); + __tcm_data_end__ = .; + } > dtcm_memory + + /*************************************************************************/ + /* .stack_dummy section doesn't contains any symbols. It is only + * used for linker to calculate size of stack sections, and assign + * values to stack symbols later */ + .stack_dummy (NOLOAD): + { + . = ALIGN(0x4); + . = . + StackSize; + . = ALIGN(0x4); + } > dtcm_memory + + /* Set stack top to end of RAM, and stack limit move down by + * size of stack_dummy section */ + __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); + PROVIDE( __freertos_irq_stack_top = __StackTop); + __StackLimit = __StackTop - SIZEOF(.stack_dummy); + + /* Check if data + heap + stack exceeds RAM limit */ + ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") + /*************************************************************************/ + __nocache_ram_load_addr = __dtcm_load_addr + LENGTH(dtcm_memory); + + .nocache_ram_region (NOLOAD) : + { + . = ALIGN(4); + __nocache_ram_data_start__ = .; + + *(.nocache_ram) + + . = ALIGN(4); + __nocache_ram_data_end__ = .; + } > nocache_ram_memory + + __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); + + .system_ram_data_region (NOLOAD) : + { + . = ALIGN(4); + __system_ram_data_start__ = .; + + *(.system_ram) + + . = ALIGN(4); + __system_ram_data_end__ = .; + } > ram_memory + + .system_ram_noinit_data_region (NOLOAD) : + { + . = ALIGN(4); + *(.system_ram_noinit) + + . = ALIGN(4); + } > ram_memory + + __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); + + /* Data section */ + RAM_DATA : AT (__ram_load_addr) + { + . = ALIGN(4); + __ram_data_start__ = .; + + PROVIDE( __global_pointer$ = . + 0x800 ); + + *(.data) + *(.data.*) + *(.sdata) + *(.sdata.*) + *(.sdata2) + *(.sdata2.*) + + . = ALIGN(4); + __ram_data_end__ = .; + } > ram_memory + + __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); + ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow") + + .bl_bss : AT (__bss_start__) + { + . = ALIGN(4); + __bss_start__ = .; + + *(.bss*) + *(.sbss*) + *(COMMON) + + . = ALIGN(4); + __bss_end__ = .; + } > ram_memory + + .noinit_data (NOLOAD) : + { + . = ALIGN(4); + __noinit_data_start__ = .; + + *(.noinit_data*) + + . = ALIGN(4); + __noinit_data_end__ = .; + } > ram_memory + + .nocache_noinit_ram_region (NOLOAD) : + { + . = ALIGN(4); + __nocache_ram_data_start__ = .; + + *(.nocache_noinit_ram) + + . = ALIGN(4); + __nocache_ram_data_end__ = .; + } > nocache_ram_memory + + .heap (NOLOAD): + { + . = ALIGN(4); + __HeapBase = .; + + /*__end__ = .;*/ + /*end = __end__;*/ + KEEP(*(.heap*)) + + . = ALIGN(4); + __HeapLimit = .; + } > ram_memory + + __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); + ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") + +} + diff --git a/examples/boot2_isp/proj.conf b/examples/boot2_isp/proj.conf index 28085a11..b00f9de4 100644 --- a/examples/boot2_isp/proj.conf +++ b/examples/boot2_isp/proj.conf @@ -1,8 +1,13 @@ set(CONFIG_VLIBC 0) set(CONFIG_BFLOG 0) set(CONFIG_XZ 1) -set(CONFIG_DEBUG 1) set(CONFIG_ROMAPI 1) set(CONFIG_VSNPRINTF_NANO 1) set(CONFIG_GCC_OPTIMISE_LEVEL -Os) +set(CONFIG_PM_PDS_FLASH_POWER_OFF 1) +set(CONFIG_PM_PDS_PLL_POWER_OFF 1) +set(CONFIG_PM_PDS_RF_POWER_OFF 1) +set(CONFIG_ERR_NOT_DUMP_ALL_REGS 1) +set(CONFIG_LOG_DISABLE 1) + diff --git a/examples/boot2_isp/softcrc.c b/examples/boot2_isp/softcrc.c index c72ddb90..d39f27c0 100644 --- a/examples/boot2_isp/softcrc.c +++ b/examples/boot2_isp/softcrc.c @@ -199,7 +199,6 @@ uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uin } #ifndef BFLB_USE_ROM_DRIVER -__WEAK__ uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32(void *dataIn, uint32_t len) { return BFLB_Soft_CRC32_Ex(0, dataIn, len);