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[feat][psram] enable 808 psram

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This commit is contained in:
jzlv 2022-10-21 20:12:06 +08:00
parent bea01b551b
commit 44a68b3adc
10 changed files with 7278 additions and 9 deletions
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8
bsp/board/bl808dk/board.c
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@ -5,10 +5,10 @@
#include "bflb_rtc.h"
#include "mmheap.h"
#include "bl808_glb.h"
// #include "bl808_psram_uhs.h"
// #include "bl808_tzc_sec.h"
// #include "bl808_ef_cfg.h"
// #include "bl808_uhs_phy.h"
#include "bl808_psram_uhs.h"
#include "bl808_tzc_sec.h"
#include "bl808_ef_cfg.h"
#include "bl808_uhs_phy.h"
#include "board.h"
#ifdef CONFIG_BSP_SDH_SDCARD

10
drivers/soc/bl808/CMakeLists.txt
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@ -15,11 +15,11 @@ sdk_library_add_sources(bl808_std/src/bl808_hbn.c)
sdk_library_add_sources(bl808_std/src/bl808_pds.c)
sdk_library_add_sources(bl808_std/src/bl808_sdh.c)
# sdk_library_add_sources(bl808_std/src/bl808_tzc_sec.c)
# sdk_library_add_sources(bl808_std/src/bl808_ef_ctrl.c)
# sdk_library_add_sources(bl808_std/src/bl808_ef_cfg.c)
# sdk_library_add_sources(bl808_std/src/bl808_psram_uhs.c)
# sdk_library_add_sources(bl808_std/src/bl808_uhs_phy.c)
sdk_library_add_sources(bl808_std/src/bl808_tzc_sec.c)
sdk_library_add_sources(bl808_std/src/bl808_ef_ctrl.c)
sdk_library_add_sources(bl808_std/src/bl808_ef_cfg.c)
sdk_library_add_sources(bl808_std/src/bl808_psram_uhs.c)
sdk_library_add_sources(bl808_std/src/bl808_uhs_phy.c)
sdk_library_add_sources(port/bl808_clock.c)
sdk_add_include_directories(

488
drivers/soc/bl808/bl808_std/include/bl808_psram.h Normal file
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@ -0,0 +1,488 @@
/**
******************************************************************************
* @file bl808_psram.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL808_PSRAM_CTRL_H__
#define __BL808_PSRAM_CTRL_H__
#include "psram_reg.h"
#include "bl808_common.h"
/** @addtogroup BL808_Peripheral_Driver
* @{
*/
/** @addtogroup PSRAM_CTRL
* @{
*/
/** @defgroup PSRAM_CTRL_Public_Types
* @{
*/
/**
* @brief PSRAM ID
*/
typedef enum {
PSRAM0_ID, /*!< PSRAM0 identifier */
} PSRAM_ID_Type;
/**
* @brief PSRAM Ctrl IO mode type definition
*/
typedef enum {
PSRAM_CTRL_X8_MODE, /*!< PSRAM X8 mode */
PSRAM_CTRL_X16_MODE, /*!< PSRAM X16 mode */
} PSRAM_Ctrl_Io_Mode_Type;
/**
* @brief PSRAM Ctrl PSRAM vendor type definition
*/
typedef enum {
PSRAM_CTRL_VENDOR_WINBOND = 0x1, /*!< Winbond psram */
PSRAM_CTRL_VENDOR_APMEM_EXCLUDE_4MB = 0x2, /*!< AP memory psram exclude 4MB size */
PSRAM_CTRL_VENDOR_APMEM_4MB = 0x4, /*!< AP memory psram 4MB size */
} PSRAM_Ctrl_Vendor_Type;
/**
* @brief PSRAM SIZE
*/
typedef enum {
PSRAM_SIZE_4MB = 0x3, /*!< PSRAM size is 4MB */
PSRAM_SIZE_8MB = 0x7, /*!< PSRAM size is 8MB */
PSRAM_SIZE_16MB = 0xf, /*!< PSRAM size is 16MB */
PSRAM_SIZE_32MB = 0x1f, /*!< PSRAM size is 32MB */
} PSRAM_Ctrl_Size_Type;
/**
* @brief Winbond PSRAM configuration register type definition
*/
typedef enum {
PSRAM_WINBOND_REG_ID0, /*!< Winbond register ID0 */
PSRAM_WINBOND_REG_ID1, /*!< Winbond register ID1 */
PSRAM_WINBOND_REG_CR0, /*!< Winbond register CR0 */
PSRAM_WINBOND_REG_CR1, /*!< Winbond register CR1 */
PSRAM_WINBOND_REG_CR2, /*!< Winbond register CR2 */
PSRAM_WINBOND_REG_CR3, /*!< Winbond register CR3 */
PSRAM_WINBOND_REG_CR4, /*!< Winbond register CR4 */
} PSRAM_Ctrl_Winbond_Cfg_Reg_Type;
/**
* @brief APMemory PSRAM configuration register type definition
*/
typedef enum {
PSRAM_APMEM_REG_0 = 0, /*!< APMemory register 0 */
PSRAM_APMEM_REG_1, /*!< APMemory register 1 */
PSRAM_APMEM_REG_2, /*!< APMemory register 2 */
PSRAM_APMEM_REG_3, /*!< APMemory register 3 */
PSRAM_APMEM_REG_4, /*!< APMemory register 4 */
PSRAM_APMEM_REG_5, /*!< APMemory register 5 */
PSRAM_APMEM_REG_6, /*!< APMemory register 6 */
PSRAM_APMEM_REG_8, /*!< APMemory register 8 */
} PSRAM_Ctrl_ApMem_Cfg_Reg_Type;
/**
* @brief PSRAM Latency Counter type definition
*/
typedef enum {
PSRAM_WINBOND_5_CLOCKS_LATENCY, /*!< PSRAM 5 clocks latency 133MHZ */
PSRAM_WINBOND_6_CLOCKS_LATENCY, /*!< PSRAM 6 clocks latency 166MHZ */
PSRAM_WINBOND_7_CLOCKS_LATENCY, /*!< PSRAM 7 clocks latency 200MHZ */
PSRAM_WINBOND_3_CLOCKS_LATENCY = 0xE, /*!< PSRAM 3 clocks latency 83MHZ */
PSRAM_WINBOND_4_CLOCKS_LATENCY = 0xF, /*!< PSRAM 4 clocks latency 100MHZ */
PSRAM_WINBOND_14_CLOCKS_LATENCY = 0x7, /*!< PSRAM 14 clocks latency only for Hyperbus3 400MHZ */
PSRAM_WINBOND_19_CLOCKS_LATENCY = 0x9, /*!< PSRAM 19 clocks latency only for Hyperbus3 533MHZ */
} PSRAM_Latency_Winbond_Type;
/**
* @brief PSRAM Burst Type
*/
typedef enum {
PSRAM_HYBRID_BURST, /*!< PSRAM use hybrid brust */
PSRAM_WRAPPED_BURST, /*!< PSRAM use warpped brust */
} PSRAM_Burst_Type;
/**
* @brief PSRAM Latency Counter type definition
*/
typedef enum {
PSRAM_APMEM_3_CLOCKS_LATENCY, /*!< PSRAM 3 clocks latency */
PSRAM_APMEM_4_CLOCKS_LATENCY = 0x4, /*!< PSRAM 4 clocks latency */
PSRAM_APMEM_5_CLOCKS_LATENCY = 0x2, /*!< PSRAM 5 clocks latency */
PSRAM_APMEM_6_CLOCKS_LATENCY = 0x6, /*!< PSRAM 6 clocks latency */
PSRAM_APMEM_7_CLOCKS_LATENCY = 0x1, /*!< PSRAM 7 clocks latency */
} PSRAM_Latency_ApMem_Type;
/**
* @brief PSRAM Drive Strength type definition for Winbon 4M
*/
typedef enum {
PSRAM_WINBOND_DRIVE_STRENGTH_50_OHMS_FOR_4M_34_OHMS_FOR_8M, /*!< drive strength 50 ohms for 4M size ,34 ohms for 8M size */
PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M, /*!< drive strength 35 ohms for 4M size ,115 ohms for 8M size */
PSRAM_WINBOND_DRIVE_STRENGTH_100_OHMS_FOR_4M_67_OHMS_FOR_8M, /*!< drive strength 100 ohms for 4M size ,67 ohms for 8M size */
PSRAM_WINBOND_DRIVE_STRENGTH_200_OHMS_FOR_4M_46_OHMS_FOR_8M, /*!< drive strength 200 ohms for 4M size ,46 ohms for 8M size */
PSRAM_DRIVE_STRENGTH_34_OHMS_ONLY_FOR_8M, /*!< drive strength 34 ohms only for 8M size */
PSRAM_DRIVE_STRENGTH_27_OHMS_ONLY_FOR_8M, /*!< drive strength 27 ohms only for 8M size */
PSRAM_DRIVE_STRENGTH_22_OHMS_ONLY_FOR_8M, /*!< drive strength 22 ohms only for 8M size */
PSRAM_DRIVE_STRENGTH_19_OHMS_ONLY_FOR_8M, /*!< drive strength 19 ohms only for 8M size */
} PSRAM_Winbond_Drive_Strength;
/**
* @brief PSRAM Drive Strength type definition for Winbon 8MB
*/
typedef enum {
PSRAM_APMEM_DRIVE_STRENGTH_25_OHMS, /*!< drive strength 25 ohms */
PSRAM_APMEM_DRIVE_STRENGTH_50_OHMS, /*!< drive strength 50 ohms */
PSRAM_APMEM_DRIVE_STRENGTH_100_OHMS, /*!< drive strength 100 ohms */
PSRAM_APMEM_DRIVE_STRENGTH_200_OHMS, /*!< drive strength 200 ohms */
} PSRAM_ApMem_Drive_Strength;
/**
* @brief PSRAM Burst Length type definition
*/
typedef enum {
PSRAM_WINBOND_BURST_LENGTH_128_BYTES = 0x4, /*!< Burst Length 128 bytes */
PSRAM_WINBOND_BURST_LENGTH_64_BYTES, /*!< Burst Length 64 bytes */
PSRAM_WINBOND_BURST_LENGTH_16_BYTES, /*!< Burst Length 16 bytes */
PSRAM_WINBOND_BURST_LENGTH_32_BYTES, /*!< Burst Length 32 bytes */
PSRAM_WINBOND_BURST_LENGTH_512_BYTES, /*!< Burst Length 512 only for HyperBus3 */
} PSRAM_Winbond_Burst_Length;
/**
* @brief PSRAM Burst Length type definition
*/
typedef enum {
PSRAM_APMEM_BURST_LENGTH_16_BYTES, /*!< Burst Length 16 bytes */
PSRAM_APMEM_BURST_LENGTH_32_BYTES, /*!< Burst Length 32 bytes */
PSRAM_APMEM_BURST_LENGTH_64_BYTES, /*!< Burst Length 64 bytes */
PSRAM_APMEM_BURST_LENGTH_1K_FOR_APS64_2K_FOR_APS256, /*!< Burst Length 1K bytes for APS6408L and 2Kbytes for APS256XXN */
} PSRAM_ApMem_Burst_Length;
/**
* @brief PSRAM Fixed Latency Enable type definition
*/
typedef enum {
PSRAM_VARIALBE_INITIAL_LATENCY, /*!< 1 or 2 times Initial Latency depending on RWDS during CA cycles */
PSRAM_FIXED_2_TIMES_INITIAL_LATENCY, /*!< Fixed 2 times Initial Latency (default) */
} PSRAM_Fixed_Latency_Enable;
/**
* @brief PSRAM Deep Power Down Enable type definition
*/
typedef enum {
PSRAM_DPD_ENTER, /*!< Writing 0 to CR0[15] causes the device to enter Deep Power Down */
PSRAM_DPD_NORMAL, /*!< Normal operation (default) */
} PSRAM_Deep_Power_Down;
/**
* @brief Partial Array Self Refresh definition
*/
typedef enum {
PSRAM_PARTIAL_REFRESH_FULL, /*!< PSRAM partial refresh full array (000000h - 1FFFFFh) */
PSRAM_PARTIAL_REFRESH_BOTTOM_1TO2, /*!< PSRAM partial refresh Bottom 1/2 array (000000h - 0FFFFFh) */
PSRAM_PARTIAL_REFRESH_BOTTOM_1TO4, /*!< PSRAM partial refresh Bottom 1/4 array (000000h - 07FFFFh) */
PSRAM_PARTIAL_REFRESH_BOTTOM_1TO8, /*!< PSRAM partial refresh Bottom 1/8 array (000000h - 03FFFFh) */
PSRAM_PARTIAL_REFRESH_NONE, /*!< PSRAM partial refresh None */
PSRAM_PARTIAL_REFRESH_TOP_1TO2, /*!< PSRAM partial refresh Top 1/2 array (100000h - 1FFFFFh) */
PSRAM_PARTIAL_REFRESH_TOP_1TO4, /*!< PSRAM partial refresh Top 1/4 array (180000h - 1FFFFFh) */
PSRAM_PARTIAL_REFRESH_TOP_1TO8, /*!< PSRAM partial refresh Top 1/8 array (1C0000h - 1FFFFFh) */
} PSRAM_Partial_Array_Refresh;
/**
* @brief PSRAM ApMem self-fresh freq
*/
typedef enum {
PSRAM_APMEM_FAST_REFRESH, /*!< Fast Refresh (default) */
PSRAM_APMEM_SLOW_REFRESH, /*!< Enables Slow Refresh when temperature allows */
} PSRAM_ApMem_Refresh_Speed;
/**
* @brief PSRAM Hybrid Sleep Mode type definition
*/
typedef enum {
PSRAM_HYBRID_SLEEP_DISABLE, /*!< not in Hybrid Sleep Mode */
PSRAM_HYBRID_SLEEP_ENABLE, /*!< entering Hybrid Sleep Mode */
} PSRAM_Hybrid_Sleep_Mode;
/**
* @brief PSRAM Master Clock type definition
*/
typedef enum {
PSRAM_CLOCK_DIFF, /*!< PSRAM Master Clock is differential */
PSRAM_CLOCK_SINGLE, /*!< PSRAM Master Clock is single end */
} PSRAM_Clock_Type;
/**
* @brief PSRAM delay chain configuration definition
*/
typedef struct
{
PSRAM_Ctrl_Vendor_Type vendor; /*!< PSRAM Vendor */
PSRAM_Ctrl_Io_Mode_Type ioMode; /*!< PSRAM interface mode */
PSRAM_Ctrl_Size_Type size; /*!< PSRAM size */
uint32_t dqs_delay; /*!< PSRAM dqs delay value */
} PSRAM_Ctrl_Cfg_Type;
/**
* @brief PSRAM Winbon configuration definition
*/
typedef struct
{
BL_Fun_Type rst; /*!< Winbond pSRAM CR1 - Software Reset */
PSRAM_Clock_Type clockType; /*!< Winbond pSRAM CR1 - Master Clock Type */
BL_Fun_Type inputPowerDownMode; /*!< Winbond pSRAM CR1 - Input Power Down */
BL_Fun_Type linear_dis; /*!< Winbond pSRAM linear burst disable */
BL_Fun_Type hybridSleepMode; /*!< Winbond pSRAM CR1 - Hybrid Sleep Mode configuration */
PSRAM_Partial_Array_Refresh PASR; /*!< Winbond pSRAM CR1 - Partial Array Refresh + Distributed Refresh Interval */
BL_Fun_Type disDeepPowerDownMode; /*!< Winbond pSRAM CR0 - Deep Power-Down Disable configuration */
BL_Fun_Type fixedLatency; /*!< Winbond pSRAM CR1 - Fix Latency configuration */
PSRAM_Winbond_Burst_Length brustLen; /*!< Winbond pSRAM CR0 - Burst Length configuration */
PSRAM_Burst_Type brustType; /*!< Winbond pSRAM CR0 - Hybrid Burst Enable */
PSRAM_Winbond_Drive_Strength driveStrength; /*!< Winbond pSRAM CR0 - Drive Strength configuration */
PSRAM_Latency_Winbond_Type latency; /*!< Winbond pSRAM CR0 - Latency Counter configuration */
} PSRAM_Winbond_Cfg_Type;
/**
* @brief PSRAM Winbon configuration definition
*/
typedef struct
{
BL_Fun_Type rst; /*!< AP Memory pSRAM configure global reset enable */
BL_Fun_Type fixedLatency; /*!< AP Memory pSRAM configure MR0 - read latency type */
PSRAM_Latency_ApMem_Type readLatency; /*!< AP Memory pSRAM configure MR0 - read latency code */
PSRAM_ApMem_Refresh_Speed refreshFreq; /*!< AP Memory pSRAM configure MR4 - refresh frequency */
PSRAM_ApMem_Drive_Strength driveStrength; /*!< AP Memory pSRAM configure MR0 - drive strength */
PSRAM_Latency_ApMem_Type writeLatency; /*!< AP Memory pSRAM configure MR4 - write latency code */
PSRAM_Partial_Array_Refresh PASR; /*!< AP Memory pSRAM configure MR4 - partial array refresh */
BL_Fun_Type halfSleepModeEnable; /*!< AP Memory pSRAM configure MR6 - Half Sleep enable */
BL_Fun_Type deepPowerDownModeEnable; /*!< AP Memory pSRAM configure MR6 - Deep Power Down enable */
BL_Fun_Type crossBoundaryEnable; /*!< AP Memory pSRAM configure MR8 - cross boundary enable 1'b0 - Read within 1K boundary 1'b1 -
Read cross 1K boundary */
PSRAM_Burst_Type brustType; /*!< AP Memory pSRAM configure MR8 - burst type */
PSRAM_ApMem_Burst_Length brustLen; /*!< AP Memory pSRAM configure MR8 - burst length */
} PSRAM_APMemory_Cfg_Type;
/*@} end of group PSRAM_CTRL_Public_Types */
/** @defgroup PSRAM_CTRL_Public_Constants
* @{
*/
/** @defgroup PSRAM_ID_TYPE
* @{
*/
#define IS_PSRAM_ID_TYPE(type) (((type) == PSRAM0_ID) || \
((type) == PSRAM1_ID))
/** @defgroup PSRAM_CTRL_IO_MODE_TYPE
* @{
*/
#define IS_PSRAM_CTRL_IO_MODE_TYPE(type) (((type) == PSRAM_CTRL_X8_MODE) || \
((type) == PSRAM_CTRL_X16_MODE))
/** @defgroup PSRAM_CTRL_VENDOR_TYPE
* @{
*/
#define IS_PSRAM_CTRL_VENDOR_TYPE(type) (((type) == PSRAM_CTRL_VENDOR_WINBOND) || \
((type) == PSRAM_CTRL_VENDOR_APMEM_EXCLUDE_4MB) || \
((type) == PSRAM_CTRL_VENDOR_APMEM_4MB))
/** @defgroup PSRAM_CTRL_SIZE_TYPE
* @{
*/
#define IS_PSRAM_CTRL_SIZE_TYPE(type) (((type) == PSRAM_SIZE_4MB) || \
((type) == PSRAM_SIZE_8MB) || \
((type) == PSRAM_SIZE_16MB) || \
((type) == PSRAM_SIZE_32MB))
/** @defgroup PSRAM_CTRL_WINBOND_CFG_REG_TYPE
* @{
*/
#define IS_PSRAM_CTRL_WINBOND_CFG_REG_TYPE(type) (((type) == PSRAM_WINBOND_REG_ID0) || \
((type) == PSRAM_WINBOND_REG_ID1) || \
((type) == PSRAM_WINBOND_REG_CR0) || \
((type) == PSRAM_WINBOND_REG_CR1) || \
((type) == PSRAM_WINBOND_REG_CR2) || \
((type) == PSRAM_WINBOND_REG_CR3) || \
((type) == PSRAM_WINBOND_REG_CR4))
/** @defgroup PSRAM_CTRL_APMEM_CFG_REG_TYPE
* @{
*/
#define IS_PSRAM_CTRL_APMEM_CFG_REG_TYPE(type) (((type) == PSRAM_APMEM_REG_0) || \
((type) == PSRAM_APMEM_REG_1) || \
((type) == PSRAM_APMEM_REG_2) || \
((type) == PSRAM_APMEM_REG_3) || \
((type) == PSRAM_APMEM_REG_4) || \
((type) == PSRAM_APMEM_REG_5) || \
((type) == PSRAM_APMEM_REG_6) || \
((type) == PSRAM_APMEM_REG_8))
/** @defgroup PSRAM_LATENCY_WINBOND_TYPE
* @{
*/
#define IS_PSRAM_LATENCY_WINBOND_TYPE(type) (((type) == PSRAM_WINBOND_5_CLOCKS_LATENCY) || \
((type) == PSRAM_WINBOND_6_CLOCKS_LATENCY) || \
((type) == PSRAM_WINBOND_7_CLOCKS_LATENCY) || \
((type) == PSRAM_WINBOND_3_CLOCKS_LATENCY) || \
((type) == PSRAM_WINBOND_4_CLOCKS_LATENCY) || \
((type) == PSRAM_WINBOND_14_CLOCKS_LATENCY) || \
((type) == PSRAM_WINBOND_19_CLOCKS_LATENCY))
/** @defgroup PSRAM_BURST_TYPE
* @{
*/
#define IS_PSRAM_BURST_TYPE(type) (((type) == PSRAM_HYBRID_BURST) || \
((type) == PSRAM_WRAPPED_BURST))
/** @defgroup PSRAM_LATENCY_APMEM_TYPE
* @{
*/
#define IS_PSRAM_LATENCY_APMEM_TYPE(type) (((type) == PSRAM_APMEM_3_CLOCKS_LATENCY) || \
((type) == PSRAM_APMEM_4_CLOCKS_LATENCY) || \
((type) == PSRAM_APMEM_5_CLOCKS_LATENCY) || \
((type) == PSRAM_APMEM_6_CLOCKS_LATENCY) || \
((type) == PSRAM_APMEM_7_CLOCKS_LATENCY))
/** @defgroup PSRAM_WINBOND_DRIVE_STRENGTH
* @{
*/
#define IS_PSRAM_WINBOND_DRIVE_STRENGTH(type) (((type) == PSRAM_WINBOND_DRIVE_STRENGTH_50_OHMS_FOR_4M_34_OHMS_FOR_8M) || \
((type) == PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M) || \
((type) == PSRAM_WINBOND_DRIVE_STRENGTH_100_OHMS_FOR_4M_67_OHMS_FOR_8M) || \
((type) == PSRAM_WINBOND_DRIVE_STRENGTH_200_OHMS_FOR_4M_46_OHMS_FOR_8M) || \
((type) == PSRAM_DRIVE_STRENGTH_34_OHMS_ONLY_FOR_8M) || \
((type) == PSRAM_DRIVE_STRENGTH_27_OHMS_ONLY_FOR_8M) || \
((type) == PSRAM_DRIVE_STRENGTH_22_OHMS_ONLY_FOR_8M) || \
((type) == PSRAM_DRIVE_STRENGTH_19_OHMS_ONLY_FOR_8M))
/** @defgroup PSRAM_APMEM_DRIVE_STRENGTH
* @{
*/
#define IS_PSRAM_APMEM_DRIVE_STRENGTH(type) (((type) == PSRAM_APMEM_DRIVE_STRENGTH_25_OHMS) || \
((type) == PSRAM_APMEM_DRIVE_STRENGTH_50_OHMS) || \
((type) == PSRAM_APMEM_DRIVE_STRENGTH_100_OHMS) || \
((type) == PSRAM_APMEM_DRIVE_STRENGTH_200_OHMS))
/** @defgroup PSRAM_WINBOND_BURST_LENGTH
* @{
*/
#define IS_PSRAM_WINBOND_BURST_LENGTH(type) (((type) == PSRAM_WINBOND_BURST_LENGTH_128_BYTES) || \
((type) == PSRAM_WINBOND_BURST_LENGTH_64_BYTES) || \
((type) == PSRAM_WINBOND_BURST_LENGTH_16_BYTES) || \
((type) == PSRAM_WINBOND_BURST_LENGTH_32_BYTES) || \
((type) == PSRAM_WINBOND_BURST_LENGTH_512_BYTES))
/** @defgroup PSRAM_APMEM_BURST_LENGTH
* @{
*/
#define IS_PSRAM_APMEM_BURST_LENGTH(type) (((type) == PSRAM_APMEM_BURST_LENGTH_16_BYTES) || \
((type) == PSRAM_APMEM_BURST_LENGTH_32_BYTES) || \
((type) == PSRAM_APMEM_BURST_LENGTH_64_BYTES) || \
((type) == PSRAM_APMEM_BURST_LENGTH_1K_FOR_APS64_2K_FOR_APS256))
/** @defgroup PSRAM_FIXED_LATENCY_ENABLE
* @{
*/
#define IS_PSRAM_FIXED_LATENCY_ENABLE(type) (((type) == PSRAM_VARIALBE_INITIAL_LATENCY) || \
((type) == PSRAM_FIXED_2_TIMES_INITIAL_LATENCY))
/** @defgroup PSRAM_DEEP_POWER_DOWN
* @{
*/
#define IS_PSRAM_DEEP_POWER_DOWN(type) (((type) == PSRAM_DPD_ENTER) || \
((type) == PSRAM_DPD_NORMAL))
/** @defgroup PSRAM_PARTIAL_ARRAY_REFRESH
* @{
*/
#define IS_PSRAM_PARTIAL_ARRAY_REFRESH(type) (((type) == PSRAM_PARTIAL_REFRESH_FULL) || \
((type) == PSRAM_PARTIAL_REFRESH_BOTTOM_1TO2) || \
((type) == PSRAM_PARTIAL_REFRESH_BOTTOM_1TO4) || \
((type) == PSRAM_PARTIAL_REFRESH_BOTTOM_1TO8) || \
((type) == PSRAM_PARTIAL_REFRESH_NONE) || \
((type) == PSRAM_PARTIAL_REFRESH_TOP_1TO2) || \
((type) == PSRAM_PARTIAL_REFRESH_TOP_1TO4) || \
((type) == PSRAM_PARTIAL_REFRESH_TOP_1TO8))
/** @defgroup PSRAM_APMEM_REFRESH_SPEED
* @{
*/
#define IS_PSRAM_APMEM_REFRESH_SPEED(type) (((type) == PSRAM_APMEM_FAST_REFRESH) || \
((type) == PSRAM_APMEM_SLOW_REFRESH))
/** @defgroup PSRAM_HYBRID_SLEEP_MODE
* @{
*/
#define IS_PSRAM_HYBRID_SLEEP_MODE(type) (((type) == PSRAM_HYBRID_SLEEP_DISABLE) || \
((type) == PSRAM_HYBRID_SLEEP_ENABLE))
/** @defgroup PSRAM_CLOCK_TYPE
* @{
*/
#define IS_PSRAM_CLOCK_TYPE(type) (((type) == PSRAM_CLOCK_DIFF) || \
((type) == PSRAM_CLOCK_SINGLE))
/*@} end of group PSRAM_CTRL_Public_Constants */
/** @defgroup PSRAM_CTRL_Public_Macros
* @{
*/
/*@} end of group PSRAM_CTRL_Public_Macros */
/** @defgroup PSRAM_CTRL_Public_Functions
* @{
*/
void PSram_Ctrl_Init(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Cfg_Type *psramCtrlCfg);
BL_Err_Type PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal);
BL_Err_Type PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr,
PSRAM_Winbond_Cfg_Type *reg_cfg);
BL_Err_Type PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal);
BL_Err_Type PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr,
PSRAM_APMemory_Cfg_Type *reg_cfg);
void PSram_Ctrl_ApMem_Reset(PSRAM_ID_Type PSRAM_ID);
void PSram_Ctrl_CK_Sel(PSRAM_ID_Type PSRAM_ID, PSRAM_Clock_Type clkSel);
void PSram_Ctrl_Winbond_Reset(PSRAM_ID_Type PSRAM_ID);
uint8_t PSram_Ctrl_Get_Timeout_Flag(PSRAM_ID_Type PSRAM_ID);
void PSram_Ctrl_Clear_Timout_Flag(PSRAM_ID_Type PSRAM_ID);
void PSram_Ctrl_Debug_Timout(PSRAM_ID_Type PSRAM_ID, uint8_t enable, uint32_t timeoutThr);
/*@} end of group PSRAM_CTRL_Public_Functions */
/*@} end of group PSRAM_CTRL */
/*@} end of group BL808_Peripheral_Driver */
#endif /* __BL808_PSRAM_CTRL_H__ */

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/**
******************************************************************************
* @file bl808_psram_uhs.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL808_PSRAM_UHS_H__
#define __BL808_PSRAM_UHS_H__
#include "psram_uhs_reg.h"
#include "bl808_common.h"
/** @addtogroup BL808_Peripheral_Driver
* @{
*/
/** @addtogroup PSRAM_UHS
* @{
*/
/** @defgroup PSRAM_UHS_Public_Types
* @{
*/
/**
* @brief Psram UHS Size
*/
typedef enum {
PSRAM_MEM_SIZE_4MB = 0x03, /*!< PSRAM Memory Size 4M */
PSRAM_MEM_SIZE_8MB = 0x07, /*!< PSRAM Memory Size 8M */
PSRAM_MEM_SIZE_16MB = 0x0f, /*!< PSRAM Memory Size 16M */
PSRAM_MEM_SIZE_32MB = 0x1f, /*!< PSRAM Memory Size 32M */
PSRAM_MEM_SIZE_64MB = 0x3f, /*!< PSRAM Memory Size 64M */
} PSRAM_UHS_Mem_Size_Type;
/**
* @brief Psram UHS Page Type
*/
typedef enum {
PSRAM_PAGE_SIZE_2KB = 0x0B, /*!< PSRAM Page Size 2KB */
PSRAM_PAGE_SIZE_4KB = 0x16, /*!< PSRAM Page Size 4KB */
} PSRAM_UHS_Page_Size_Type;
/**
* @brief Psram UHS Burst Size
*/
typedef enum {
PSRAM_UHS_WARP_BURST_64, /*!< PSRAM Warp Burst Size 64 */
PSRAM_UHS_WARP_BURST_32, /*!< PSRAM Warp Burst Size 32 */
PSRAM_UHS_WARP_BURST_16, /*!< PSRAM Warp Burst Size 16 */
PSRAM_UHS_WARP_BURST_NONE, /*!< PSRAM Warp Burst NONE */
PSRAM_UHS_WARP_BURST_NO_CHANGE, /*!< Not change this value */
} PSRAM_UHS_WARP_BURST_Type;
/**
* @brief Psram UHS Driver Strength
*/
typedef enum {
PSRAM_UHS_DRIVER_ST_34P3_PDPU = 0x1, /*!< 34.3 PD/PU */
PSRAM_UHS_DRIVER_ST_40_PDPU = 0x2, /*!< 40 PD/PU */
PSRAM_UHS_DRIVER_ST_48_PDPU = 0x3, /*!< 48 PD/PU */
PSRAM_UHS_DRIVER_ST_60_PDPU = 0x4, /*!< 60 PD/PU */
PSRAM_UHS_DRIVER_ST_80_PDPU = 0x6, /*!< 80 PD/PU */
PSRAM_UHS_DRIVER_ST_34P3_PD_40_PU = 0x9, /*!< 34.3 PD & 40 PU */
PSRAM_UHS_DRIVER_ST_40_PD_48_PU = 0xa, /*!< 40 PD & 48 PU */
PSRAM_UHS_DRIVER_ST_34P3_PD_48_PU = 0xb, /*!< 34.3 PD & 48 PU */
PSRAM_UHS_DRIVER_ST_NO_CHANGE = 0xf, /*!< Not change this value */
} PSRAM_UHS_DRIVER_ST_Type;
/**
* @brief Psram UHS LATENCY
*/
typedef enum {
PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ, /*!< MAX freq. = 533 MHz / Write LATENCY=10 / Read LATENCY=20 */
PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ, /*!< MAX freq. = 800 MHz / Write LATENCY=14 / Read LATENCY=29 */
PSRAM_UHS_LATENCY_W16_R33_MAX_FRE_933_MHZ, /*!< MAX freq. = 933 MHz / Write LATENCY=16 / Read LATENCY=33 */
PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ, /*!< MAX freq. = 1066 MHz / Write LATENCY=18 / Read LATENCY=37 */
PSRAM_UHS_LATENCY_RESERVED, /*!< Reserved */
PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ, /*!< MAX freq. = 400 MHz / Write LATENCY=6 / Read LATENCY=16 */
PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ, /*!< MAX freq. = 333 MHz / Write LATENCY=5 / Read LATENCY=13 */
PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ, /*!< MAX freq. = 200 MHz / Write LATENCY=5 / Read LATENCY=9 */
PSRAM_UHS_LATENCY_NO_CHANGE, /*!< Not change this value */
} PSRAM_UHS_LATENCY_Type;
/**
* @brief Psram UHS CMD Type
*/
typedef enum {
PSRAM_UHS_CMD_SELF_REFRESH_IN, /*!< pSRAM self-refresh in command */
PSRAM_UHS_CMD_SELF_REFRESH_EXIT, /*!< pSRAM self-refresh exit command */
PSRAM_UHS_CMD_GLOBAL_RESET, /*!< pSRAM global reset command */
PSRAM_UHS_CMD_ZQ_CAL_LONG, /*!<ZQ calibration, long> */
PSRAM_UHS_CMD_ZQ_CAL_SHORT, /*!<ZQ calibration, short>*/
PSRAM_UHS_CMD_ZQ_CAL_RESET, /*!<ZQ calibration,reset>*/
} PSRAM_UHS_CMD_Type;
/**
* @brief PSRAM UHS Temperature
*
*/
typedef enum {
PSRAM_UHS_NORMAL_TEMP,
PSRAM_UHS_HIGH_TEMP,
} PSRAM_UHS_TEMP_Type;
/**
* @brief PSRAM_UHS_Cfg_Type
*/
typedef struct {
uint32_t pck_freq; /*!< pck frequency unit is MHZ */
PSRAM_UHS_Mem_Size_Type psramMemSize; /*!< psram uhm memory size */
PSRAM_UHS_Page_Size_Type psramPageSize; /*!< psram uhm page size */
PSRAM_UHS_TEMP_Type isHighTem; /*!< auto refresh work temperature */
} PSRAM_UHS_Cfg_Type;
/**
* @brief PSRAM_UHS_Phy_Latency_Pra_Type
*/
typedef struct {
uint8_t phy_rl_ana; /*!< phy_rl_ana */
uint8_t phy_rl_dig; /*!< phy_rl_dig*/
uint8_t phy_wl_ana; /*!< phy_wl_ana */
uint8_t phy_wl_dig; /*!< phy_wl_dig*/
uint8_t phy_wl_dq_ana; /*!< phy_wl_dq_ana */
uint8_t phy_wl_dq_dig; /*!< phy_wl_dq_dig */
uint8_t reg_timer_array_read; /*!< reg_timer_array_read */
uint8_t reg_timer_array_write; /*!< reg_timer_array_write */
uint8_t reg_timer_dqs_array_stop; /*!< reg_timer_dqs_array_stop */
uint8_t reg_timer_dqs_start; /*!< reg_timer_dqs_start */
uint8_t reg_timer_dqs_stop; /*!< reg_timer_dqs_stop */
uint8_t reg_timer_reg_read; /*!< reg_timer_reg_read */
uint8_t reg_timer_reg_write; /*!< reg_timer_reg_write */
uint8_t reg_timer_auto_refresh; /*!< reg_timer_auto_refresh */
uint16_t reg_timer_global_rst; /*!< reg_timer_global_rst */
uint8_t reg_timer_self_refresh1_in; /*!< reg_timer_self_refresh1_in */
uint8_t reg_timer_self_refresh1_exit; /*!< reg_timer_self_refresh1_exit */
uint8_t reg_timer_reg_write_busy; /*!< reg_timer_reg_write_busy */
uint8_t reg_timer_reg_read_busy; /*!< reg_timer_reg_read_busy */
uint8_t reg_timer_arrary_write_busy; /*!< reg_timer_arrary_write_busy */
uint8_t reg_timer_arrary_read_busy; /*!< reg_timer_arrary_read_busy */
uint8_t en_rx_fe_dly; /*!< en_rx_fe_dly */
uint8_t odt_sel_dly; /*!< odt_sel_dly */
uint8_t reg_trc_cycle; /*!< reg_trc_cycle */
uint8_t reg_trfc_cycle; /*!< reg_trfc_cycle */
uint8_t reg_tcphr_cycle; /*!< reg_tcphr_cycle */
uint8_t reg_tcphw_cycle; /*!< reg_tcphw_cycle */
} PSRAM_UHS_Phy_Latency_Pra_Type;
/**
* @brief PSRAM_UHS_Write_Reg_Cfg_Type
*/
typedef struct {
PSRAM_UHS_DRIVER_ST_Type driver_st; /*!< driver strength */
PSRAM_UHS_WARP_BURST_Type burst_size; /*!< burst size */
PSRAM_UHS_LATENCY_Type lentency; /*!< lentency */
} PSRAM_UHS_Write_Reg_Cfg_Type;
/*@} end of group PSRAM_UHS_Public_Types */
/** @defgroup PSRAM_UHS_Public_Constants
* @{
*/
/** @defgroup PSRAM_UHS_MEM_SIZE_TYPE
* @{
*/
#define IS_PSRAM_UHS_MEM_SIZE_TYPE(type) (((type) == PSRAM_MEM_SIZE_4MB) || \
((type) == PSRAM_MEM_SIZE_8MB) || \
((type) == PSRAM_MEM_SIZE_16MB) || \
((type) == PSRAM_MEM_SIZE_32MB))
/** @defgroup PSRAM_UHS_PAGE_SIZE_TYPE
* @{
*/
#define IS_PSRAM_UHS_PAGE_SIZE_TYPE(type) (((type) == PSRAM_PAGE_SIZE_2KB) || \
((type) == PSRAM_PAGE_SIZE_4KB))
/** @defgroup PSRAM_UHS_WARP_BURST_TYPE
* @{
*/
#define IS_PSRAM_UHS_WARP_BURST_TYPE(type) (((type) == PSRAM_UHS_WARP_BURST_64) || \
((type) == PSRAM_UHS_WARP_BURST_32) || \
((type) == PSRAM_UHS_WARP_BURST_16))
/** @defgroup PSRAM_UHS_DRIVER_ST_TYPE
* @{
*/
#define IS_PSRAM_UHS_DRIVER_ST_TYPE(type) (((type) == PSRAM_UHS_DRIVER_ST_34P3_PUPU) || \
((type) == PSRAM_UHS_DRIVER_ST_40_PUPU) || \
((type) == PSRAM_UHS_DRIVER_ST_48_PUPU) || \
((type) == PSRAM_UHS_DRIVER_ST_60_PUPU) || \
((type) == PSRAM_UHS_DRIVER_ST_80_PUPU) || \
((type) == PSRAM_UHS_DRIVER_ST_34P3_PD_40_PU) || \
((type) == PSRAM_UHS_DRIVER_ST_40_PD_48_PU) || \
((type) == PSRAM_UHS_DRIVER_ST_34P3_PD_48_PU))
/** @defgroup PSRAM_UHS_LATENCY_TYPE
* @{
*/
#define IS_PSRAM_UHS_LATENCY_TYPE(type) (((type) == PSRAM_UHS_LATENCY_W10_R20_MAX_FRE_533_MHZ) || \
((type) == PSRAM_UHS_LATENCY_W14_R29_MAX_FRE_800_MHZ) || \
((type) == PSRAM_UHS_LATENCY_W16_R33_MAX_FRE_933_MHZ) || \
((type) == PSRAM_UHS_LATENCY_W18_R37_MAX_FRE_1066_MHZ) || \
((type) == PSRAM_UHS_LATENCY_W6_R16_MAX_FRE_400_MHZ) || \
((type) == PSRAM_UHS_LATENCY_W5_R13_MAX_FRE_333_MHZ) || \
((type) == PSRAM_UHS_LATENCY_W5_R9_MAX_FRE_200_MHZ))
/** @defgroup PSRAM_UHS_CMD_Type
* @{
*/
#define IS_PSRAM_UHS_CMD_TYPE(type) (((type) == PSRAM_UHS_CMD_SELF_REFRESH_IN) || \
((type) == PSRAM_UHS_CMD_SELF_REFRESH_EXIT) || \
((type) == PSRAM_UHS_CMD_GLOBAL_RESET)
/*@} end of group PSRAM_UHS_Public_Constants */
/** @defgroup PSRAM_UHS_Public_Macros
* @{
*/
/*@} end of group PSRAM_UHS_Public_Macros */
/** @defgroup PSRAM_UHS_Public_Functions
* @{
*/
void Psram_UHS_Init(PSRAM_UHS_Cfg_Type *cfg);
int PSram_UHS_Read_Reg(uint32_t reg_addr, uint8_t *regVal);
int PSram_UHS_Write_Reg(PSRAM_UHS_Write_Reg_Cfg_Type *regCfg);
int PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_Type cmd);
void Psram_UHS_x16_Init(uint32_t uhs_pll_clk);
void Psram_UHS_x16_Init_Override(PSRAM_UHS_Cfg_Type *cfg);
/*@} end of group PSRAM_UHS_Public_Functions */
/*@} end of group PSRAM_UHS */
/*@} end of group BL808_Peripheral_Driver */
#endif /* __BL808_PSRAM_UHS_H__ */

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/**
******************************************************************************
* @file bl808_tzc_sec.h
* @version V1.0
* @date
* @brief This file is the standard driver header file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#ifndef __BL808_TZC_SEC_H__
#define __BL808_TZC_SEC_H__
#include "tzc_sec_reg.h"
#include "bl808_common.h"
/** @addtogroup BL808_Peripheral_Driver
* @{
*/
/** @addtogroup TZC_SEC
* @{
*/
/** @defgroup TZC_SEC_Public_Types
* @{
*/
/**
* @brief TZC_SEC master type definition
*/
typedef enum {
TZC_SEC_MASTER_LP, /*!< TZC Master:LP CPU */
TZC_SEC_MASTER_MM_BUS, /*!< TZC Master:MM Bus */
TZC_SEC_MASTER_USB, /*!< TZC Master:USB */
TZC_SEC_MASTER_WIFI, /*!< TZC Master:WIFI */
TZC_SEC_MASTER_CCI, /*!< TZC Master:CCI */
TZC_SEC_MASTER_SDH, /*!< TZC Master:SDH */
TZC_SEC_MASTER_EMAC, /*!< TZC Master:EMAC */
TZC_SEC_MASTER_M0, /*!< TZC Master:M0 CPU */
TZC_SEC_MASTER_DMA0, /*!< TZC Master:DMA0 */
TZC_SEC_MASTER_DMA1, /*!< TZC Master:DMA1 */
TZC_SEC_MASTER_LZ4, /*!< TZC Master:LZ4 */
TZC_SEC_MASTER_D0, /*!< TZC Master:D0 */
TZC_SEC_MASTER_BLAI, /*!< TZC Master:BLAI */
TZC_SEC_MASTER_CODEC, /*!< TZC Master:CODEC */
TZC_SEC_MASTER_ISP, /*!< TZC Master:ISP */
TZC_SEC_MASTER_2DDMA, /*!< TZC Master:2D DMA */
TZC_SEC_MASTER_DMA2, /*!< TZC Master:DMA2 */
TZC_SEC_MASTER_MAX, /*!< TZC Master max */
} TZC_SEC_Master_Type;
/**
* @brief TZC_SEC slave type definition
*/
typedef enum {
TZC_SEC_SLAVE_GLB = 0, /*!< TZC Slave:GLB */
TZC_SEC_SLAVE_MIX, /*!< TZC Slave:MIX */
TZC_SEC_SLAVE_GPIP, /*!< TZC Slave:GPIP */
TZC_SEC_SLAVE_DBG, /*!< TZC Slave:DBG */
TZC_SEC_SLAVE_RSVD, /*!< TZC Slave:Reserved */
TZC_SEC_SLAVE_TZC1, /*!< TZC Slave:TZC1 */
TZC_SEC_SLAVE_TZC2, /*!< TZC Slave:TZC2 */
TZC_SEC_SLAVE_RSVD2, /*!< TZC Slave:Reserved */
TZC_SEC_SLAVE_CCI, /*!< TZC Slave:CCI */
TZC_SEC_SLAVE_MCU_MISC, /*!< TZC Slave:MCU_MISC */
TZC_SEC_SLAVE_PERIPHERAL, /*!< TZC Slave:Peripheral */
TZC_SEC_SLAVE_EMI_MISC = 16, /*!< TZC Slave:emi misc */
TZC_SEC_SLAVE_PSRAMA, /*!< TZC Slave:PSRAMA */
TZC_SEC_SLAVE_PSRAMB, /*!< TZC Slave:PSRAMB */
TZC_SEC_SLAVE_USB, /*!< TZC Slave:USB */
TZC_SEC_SLAVE_RF2, /*!< TZC Slave:RF2 */
TZC_SEC_SLAVE_AUDIO, /*!< TZC Slave:Audio */
TZC_SEC_SLAVE_EF_CTRL, /*!< TZC Slave:efuse control*/
TZC_SEC_SLAVE_MM = 32, /*!< TZC Slave:MM */
TZC_SEC_SLAVE_DMA0, /*!< TZC Slave:DMA0 */
TZC_SEC_SLAVE_DMA1, /*!< TZC Slave:DMA1 */
TZC_SEC_SLAVE_PWR, /*!< TZC Slave:Power */
TZC_SEC_SLAVE_MAX, /*!< TZC slave max*/
} TZC_SEC_Slave_Type;
/**
* @brief TZC_SEC MM slave type definition
*/
typedef enum {
TZC_SEC_MM_SLAVE_MISC, /*!< TZC MM Slave:MISC */
TZC_SEC_MM_SLAVE_DMA, /*!< TZC MM Slave:DMA */
TZC_SEC_MM_SLAVE_UART, /*!< TZC MM Slave:UART */
TZC_SEC_MM_SLAVE_I2C0, /*!< TZC MM Slave:I2C0 */
TZC_SEC_MM_SLAVE_I2C1, /*!< TZC MM Slave:I2C1 */
TZC_SEC_MM_SLAVE_IPC, /*!< TZC MM Slave:IPC */
TZC_SEC_MM_SLAVE_2DDMA, /*!< TZC MM Slave:2DDMA */
TZC_SEC_MM_SLAVE_CLKRST, /*!< TZC MM Slave:Clock and reset */
TZC_SEC_MM_SLAVE_SPI, /*!< TZC MM Slave:SPI */
TZC_SEC_MM_SLAVE_TIMER, /*!< TZC MM Slave:Timer */
TZC_SEC_MM_SLAVE_RSVD1, /*!< TZC MM Slave:reserved1 */
TZC_SEC_MM_SLAVE_RSVD2, /*!< TZC MM Slave:reserved2 */
TZC_SEC_MM_SLAVE_RSVD3, /*!< TZC MM Slave:reserved3 */
TZC_SEC_MM_SLAVE_RSVD4, /*!< TZC MM Slave:reserved4 */
TZC_SEC_MM_SLAVE_RSVD5, /*!< TZC MM Slave:reserved5 */
TZC_SEC_MM_SLAVE_UHS_PSRAM, /*!< TZC MM Slave:uhs psram */
TZC_SEC_MM_SLAVE_ISP_MISC = 16, /*!< TZC MM Slave:ISP MISC */
TZC_SEC_MM_SLAVE_ISP_TOP, /*!< TZC MM Slave:ISP TOP */
TZC_SEC_MM_SLAVE_DVP_MISC, /*!< TZC MM Slave:DVP MISC */
TZC_SEC_MM_SLAVE_OSD_A, /*!< TZC MM Slave:OSD_A */
TZC_SEC_MM_SLAVE_OSD_B, /*!< TZC MM Slave:OSD_B */
TZC_SEC_MM_SLAVE_OSD_DP, /*!< TZC MM Slave:OSD_DP */
TZC_SEC_MM_SLAVE_AWB3_CORE, /*!< TZC MM Slave:AWB3 core */
TZC_SEC_MM_SLAVE_AWB3_SRAM, /*!< TZC MM Slave:AWB3 SRAM */
TZC_SEC_MM_SLAVE_RSVD6, /*!< TZC MM Slave:Reserved */
TZC_SEC_MM_SLAVE_ISP_AE_SRAM, /*!< TZC MM Slave:ISP AE SRAM */
TZC_SEC_MM_SLAVE_MIPI, /*!< TZC MM Slave:MIPI(DSI & CSI )*/
TZC_SEC_MM_SLAVE_DBI, /*!< TZC MM Slave:DBI */
TZC_SEC_MM_SLAVE_ISP_AWB_SRAM, /*!< TZC MM Slave:ISP AWB SRAM */
TZC_SEC_MM_SLAVE_CODEC_MISC = 32, /*!< TZC MM Slave:Codec misc */
TZC_SEC_MM_SLAVE_MJPEG, /*!< TZC MM Slave:MJPEG */
TZC_SEC_MM_SLAVE_VIDEO, /*!< TZC MM Slave:Video */
TZC_SEC_MM_SLAVE_MJPEG_DEC, /*!< TZC MM Slave:MJPEG Decoder */
TZC_SEC_MM_SLAVE_BLAI, /*!< TZC MM Slave:BLAI */
TZC_SEC_MM_SLAVE_MAX, /*!< TZC MM slave max*/
} TZC_SEC_MM_Slave_Type;
/**
* @brief TZC_SEC GLB Ctrl type definition
*/
typedef enum {
TZC_SEC_GLB_CTRL_POR_RESET, /*!< TZC GLB Ctrl: Power on reset */
TZC_SEC_GLB_CTRL_CPU_RESET, /*!< TZC GLB Ctrl: CPU reset */
TZC_SEC_GLB_CTRL_SYS_RESET, /*!< TZC GLB Ctrl: System reset */
TZC_SEC_GLB_CTRL_CCPU_RESET, /*!< TZC GLB Ctrl: Coupled CPU reset */
TZC_SEC_GLB_CTRL_MISC, /*!< TZC GLB Ctrl: MISC */
TZC_SEC_GLB_CTRL_SRAM, /*!< TZC GLB Ctrl: SRAM */
TZC_SEC_GLB_CTRL_SWRESET, /*!< TZC GLB Ctrl: Software reset */
TZC_SEC_GLB_CTRL_BMX, /*!< TZC GLB Ctrl: BMX */
TZC_SEC_GLB_CTRL_DBG, /*!< TZC GLB Ctrl: DBG */
TZC_SEC_GLB_CTRL_MBIST, /*!< TZC GLB Ctrl: MBIST */
TZC_SEC_GLB_CTRL_CLK, /*!< TZC GLB Ctrl: CLK */
TZC_SEC_GLB_CTRL_INT, /*!< TZC GLB Ctrl: Interrupt */
TZC_SEC_GLB_CTRL_PWR, /*!< TZC GLB Ctrl: Power */
TZC_SEC_GLB_CTRL_MAX,
} TZC_SEC_GLB_Ctrl_Type;
/**
* @brief TZC_SEC MM GLB Ctrl type definition
*/
typedef enum {
TZC_SEC_MM_GLB_CTRL_POR_RESET, /*!< TZC MM GLB Ctrl: Power on reset */
TZC_SEC_MM_GLB_CTRL_CPU_RESET, /*!< TZC MM GLB Ctrl: CPU reset */
TZC_SEC_MM_GLB_CTRL_SYS_RESET, /*!< TZC MM GLB Ctrl: System reset */
TZC_SEC_MM_GLB_CTRL_CCPU_RESET, /*!< TZC MM GLB Ctrl: Coupled CPU reset */
TZC_SEC_MM_GLB_CTRL_RSVD1, /*!< TZC MM GLB Ctrl: Reserved */
TZC_SEC_MM_GLB_CTRL_SRAM, /*!< TZC MM GLB Ctrl: SRAM */
TZC_SEC_MM_GLB_CTRL_SWRESET, /*!< TZC MM GLB Ctrl: Software reset */
TZC_SEC_MM_GLB_CTRL_RSVD2, /*!< TZC MM GLB Ctrl: Reserved */
TZC_SEC_MM_GLB_CTRL_RSVD3, /*!< TZC MM GLB Ctrl: Reserved */
TZC_SEC_MM_GLB_CTRL_RSVD4, /*!< TZC MM GLB Ctrl: Reserved */
TZC_SEC_MM_GLB_CTRL_CLK, /*!< TZC MM GLB Ctrl: CLK */
TZC_SEC_MM_GLB_CTRL_MAX,
} TZC_SEC_MM_GLB_Ctrl_Type;
/**
* @brief TZC_SEC SE Ctrl type definition
*/
typedef enum {
TZC_SEC_SE_CTRL_SHA, /*!< TZC SE Ctrl: SHA */
TZC_SEC_SE_CTRL_AES, /*!< TZC SE Ctrl: AES */
TZC_SEC_SE_CTRL_TRNG, /*!< TZC SE Ctrl: TRNG */
TZC_SEC_SE_CTRL_PKA, /*!< TZC SE Ctrl: PKA */
TZC_SEC_SE_CTRL_CDET, /*!< TZC SE Ctrl: CEDT */
TZC_SEC_SE_CTRL_GMAC, /*!< TZC SE Ctrl: GMAC */
TZC_SEC_SE_CTRL_MAX,
} TZC_SEC_SE_Ctrl_Type;
/**
* @brief TZC_SEC SF Ctrl type definition
*/
typedef enum {
TZC_SEC_SF_CTRL_CR, /*!< TZC SF Ctrl: control register */
TZC_SEC_SF_CTRL_SEC, /*!< TZC SF Ctrl: security register */
TZC_SEC_SF_CTRL_MAX,
} TZC_SEC_SF_Ctrl_Type;
/**
* @brief TZC_SEC SE Ctrl mode definition
*/
typedef enum {
TZC_SEC_SE_MODE_ARB, /*!< TZC SE Ctrl mode: cpus arbitrate */
TZC_SEC_SE_MODE_TZC, /*!< TZC SE Ctrl: TZC control as group */
} TZC_SEC_SE_Ctrl_Mode;
/**
* @brief TZC_SEC SF Ctrl mode definition
*/
typedef enum {
TZC_SEC_SF_MODE_ARB, /*!< TZC SF Ctrl mode: cpus arbitrate */
TZC_SEC_SF_MODE_TZC, /*!< TZC SF Ctrl: TZC control as group */
} TZC_SEC_SF_Ctrl_Mode;
/**
* @brief TZC_SEC Auth group
*/
typedef enum {
TZC_SEC_AUTH_GRP_0, /*!< TZC auth group 0 */
TZC_SEC_AUTH_GRP_1, /*!< TZC auth group 1 */
} TZC_SEC_Auth_Group;
/**
* @brief TZC_SEC Advance Auth group
*/
typedef enum {
TZC_SEC_ADV_AUTH_GRP_0_IBUS = 0x01, /*!< TZC advance auth group 0 IBUS */
TZC_SEC_ADV_AUTH_GRP_0_DBUS = 0x02, /*!< TZC advance auth group 0 DBUS */
TZC_SEC_ADV_AUTH_GRP_1_IBUS = 0x04, /*!< TZC advance auth group 1 IBUS */
TZC_SEC_ADV_AUTH_GRP_1_DBUS = 0x08, /*!< TZC advance auth group 1 DBUS */
} TZC_SEC_Advance_Auth_Group;
/*@} end of group TZC_SEC_Public_Types */
/** @defgroup TZC_SEC_Public_Constants
* @{
*/
/*@} end of group TZC_SEC_Public_Constants */
/** @defgroup TZC_SEC_Public_Macros
* @{
*/
#define TZC_SEC_MAX_AUTH_GRP 3
/*@} end of group TZC_SEC_Public_Macros */
/** @defgroup TZC_SEC_Public_Functions
* @{
*/
void Tzc_Sec_Set_Sboot_Done(void);
void Tzc_Sec_Set_Master_Group(TZC_SEC_Master_Type masterType, uint8_t group);
void Tzc_Sec_Set_CPU_Group(uint8_t cpu, uint8_t group);
void Tzc_Sec_Set_Slave_Group(TZC_SEC_Slave_Type slaveType, uint8_t group);
void Tzc_Sec_Set_Glb_Ctrl_Group(TZC_SEC_GLB_Ctrl_Type slaveType, uint8_t group);
void Tzc_Sec_ROM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
void Tzc_Sec_OCRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
void Tzc_Sec_OCRAM_Access_Set_Regionx(uint8_t group);
void Tzc_Sec_WRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
void Tzc_Sec_WRAM_Access_Set_Regionx(uint8_t group);
void Tzc_Sec_Flash_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
void Tzc_Sec_Flash_Access_Set_Regionx(uint8_t group);
void Tzc_Sec_L2SRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
void Tzc_Sec_VRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
void Tzc_Sec_PSRAMA_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
void Tzc_Sec_PSRAMA_Access_Release(void);
void Tzc_Sec_PSRAMB_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
void Tzc_Sec_PSRAMB_Access_Release(void);
void Tzc_Sec_XRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
void Tzc_Sec_Set_Se_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode);
void Tzc_Sec_Set_Sf_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode);
void Tzc_Sec_Set_Se_Group(TZC_SEC_SE_Ctrl_Type slaveType, uint8_t group);
void Tzc_Sec_Set_Sf_Group(TZC_SEC_SF_Ctrl_Type slaveType, uint8_t group);
void Tzc_Sec_Set_WTD_Rst_Delay(uint16_t delayValue);
/*@} end of group TZC_SEC_Public_Functions */
/*@} end of group TZC_SEC */
/*@} end of group BL808_Peripheral_Driver */
#endif /* __BL808_TZC_SEC_H__ */

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drivers/soc/bl808/bl808_std/include/bl808_uhs_phy.h Normal file
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#ifndef __UHS_PHY_H__
#define __UHS_PHY_H__
#include "bl808_common.h"
#include "bl808_psram_uhs.h"
#include "bl808_glb.h"
#ifndef CAL_MODE
#define CAL_MODE (0) // 0 is for sw call, 1 is for phy test, 2 is for ate cal
#endif
enum {
UHS_LATENCY_CODE_533 = 3, // "0"
UHS_LATENCY_CODE_800 = 3, // "1"
UHS_LATENCY_CODE_933 = 3, // "2"
UHS_LATENCY_CODE_1066 = 3,
UHS_LATENCY_CODE_RESERVED = 3, //"4"
UHS_LATENCY_CODE_400 = 3, //"5"
UHS_LATENCY_CODE_333 = 3, //"6"
UHS_LATENCY_CODE_200 = 3, //"7"
};
enum{
UHS_REGR_GNT_ERR = 1,
UHS_REGR_DONE_ERR,
UHS_REGW_GNT_ERR,
UHS_REGW_DONE_ERR,
UHS_LATENCY_CODE_WRITE_ERR,
UHS_INIT_ARRAY_WRITE_ERR,
UHS_REG_READ_CAL_ERR,
UHS_REG_WRITE_CAL_ERR,
UHS_ARRAY_READ_LAT_ERR,
UHS_ARRAY_WRITE_CK_ERR,
UHS_ARRAY_READ_CAL_ERR,
UHS_ARRAY_WRITE_CAL_ERR,
UHS_CACHE_ENABLE_ERR,
UHS_CACHE_DISABLE_ERR,
UHS_CACHE_RECOVER_ERR,
UHS_REG_WRITE_2kM_ERR,
UHS_BAD_DIE_ERR,
UHS_DIAGONAL_TEST_ERR,
UHS_ALL_ADDR_TEST_ERR,
};
#if CAL_MODE != 2
typedef struct
{
uint8_t rl :6;
uint8_t rdqs :4;
uint8_t rdq :4;
uint8_t wl :5;
uint8_t wdqs :4;
uint8_t wdq :4;
uint8_t ck :4;
uint8_t err_type;
uint8_t err_sub_type;
uint8_t cal_mode;
uint16_t datarate;
uint8_t rwindow;
uint8_t rwindow_begin;
uint8_t rwindow_end;
uint8_t wwindow;
uint8_t wwindow_begin;
uint8_t wwindow_end;
uint8_t cal_done;
uint32_t crc_res;
} uhs_phy_cal_res_struct;
#else
typedef struct
{
uint32_t rl;
uint32_t rdqs;
uint32_t rdq;
uint32_t wl;
uint32_t wdqs;
uint32_t wdq;
uint32_t ck;
uint32_t err_type;
uint32_t err_sub_type;
uint32_t cal_mode;
uint32_t datarate;
uint32_t rwindow;
uint32_t rwindow_begin;
uint32_t rwindow_end;
uint32_t wwindow;
uint32_t wwindow_begin;
uint32_t wwindow_end;
uint32_t cal_done;
uint32_t crc_res;
} uhs_phy_cal_res_struct;
#endif
extern uhs_phy_cal_res_struct* uhs_phy_cal_res;
// function call
void uhs_phy_init(PSRAM_UHS_Cfg_Type *cfg);
void uhs_phy_pwr_down(void);
uint8_t mr_read_back(void);
void set_odt_en(void);
// for htol test api
uint8_t uhs_all_addr_test(void);
// for test or debug in example main.c
void soft_reset(void);
void uhs_reset(uint8_t ma_rb);
void array_write_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1);
uint8_t array_read_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1);
BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL_Freq(GLB_XTAL_Type xtalType, uint32_t pllFreq);
//
void set_uhs_latency_r(uint32_t uhs_latency);
void set_uhs_latency_w(uint32_t uhs_latency);
void cfg_dq_drv(uint32_t dq);
void cfg_dqs_drv(uint32_t dqs);
void cfg_ck_cen_drv(uint8_t array_ck_dly_drv,uint8_t array_cen_dly_drv);
void cfg_dq_rx(uint8_t dq);
void cfg_dqs_rx(uint8_t dqs);
#endif // __UHS_PHY_H__

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drivers/soc/bl808/bl808_std/src/bl808_ef_cfg.c Normal file
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/**
******************************************************************************
* @file bl808_ef_cfg.c
* @version V1.0
* @date
* @brief This file is the standard driver c file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "string.h"
#include "bl808_ef_ctrl.h"
#include "bl808_ef_cfg.h"
#include "ef_data_0_reg.h"
#include "ef_data_1_reg.h"
/** @addtogroup BL808_Peripheral_Driver
* @{
*/
/** @addtogroup SEC_EF_CTRL
* @{
*/
/** @defgroup SEC_EF_CTRL_Private_Macros
* @{
*/
#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0()
#define EF_CTRL_LOAD_BEFORE_READ_R1 EF_Ctrl_Load_Efuse_R1()
/*@} end of group SEC_EF_CTRL_Private_Macros */
/** @defgroup SEC_EF_CTRL_Private_Types
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Types */
/** @defgroup SEC_EF_CTRL_Private_Variables
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Variables */
/** @defgroup SEC_EF_CTRL_Global_Variables
* @{
*/
/*@} end of group SEC_EF_CTRL_Global_Variables */
/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration
* @{
*/
/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */
/** @defgroup SEC_EF_CTRL_Private_Functions
* @{
*/
/****************************************************************************/ /**
* @brief Efuse get zero bit count
*
* @param val: Value to count
*
* @return Zero bit count
*
*******************************************************************************/
static uint32_t EF_Cfg_Get_Byte_Zero_Cnt(uint8_t val)
{
uint32_t cnt = 0;
uint32_t i = 0;
for (i = 0; i < 8; i++) {
if ((val & (1 << i)) == 0) {
cnt += 1;
}
}
return cnt;
}
/****************************************************************************/ /**
* @brief Efuse get chip info
*
* @param chipInfo: info pointer
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Get_Chip_Info(Efuse_Chip_Info_Type *chipInfo)
{
uint32_t tmpVal;
/* Trigger read data from efuse */
EF_CTRL_LOAD_BEFORE_READ_R0;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
chipInfo->chipInfo = (tmpVal>>29)&0x7;
chipInfo->memoryInfo = (tmpVal>>27)&0x3;
chipInfo->psramInfo = (tmpVal>>25)&0x3;
chipInfo->deviceInfo = (tmpVal>>22)&0x7;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0);
chipInfo->psramInfo |= ((tmpVal>>20)&0x1) << 2;
}
/****************************************************************************/ /**
* @brief Efuse read xtal trim rc32m configuration
*
* @param trim: Trim data pointer
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Read_LDO15RF_Vout_Sel(Efuse_Ana_LDO15RF_Vout_Sel_Type *trim)
{
uint32_t tmpVal;
/* Trigger read data from efuse */
EF_CTRL_LOAD_BEFORE_READ_R0;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3);
trim->trimLDO15RFVoutAon = (tmpVal >> 27) & 0x07;
trim->trimLDO15RFVoutAonParity = (tmpVal >> 30) & 0x01;
trim->trimLDO15RFVoutAonEn = (tmpVal >> 31) & 0x01;
}
/****************************************************************************/ /**
* @brief Efuse read rcal iptat code configuration
*
* @param trim: Trim data pointer
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Read_Rcal_Iptat_Code(Efuse_Ana_Rcal_Iptat_Code_Type *trim)
{
uint32_t tmpVal;
/* Trigger read data from efuse */
EF_CTRL_LOAD_BEFORE_READ_R0;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3);
trim->trimRcalIptatCode = (tmpVal >> 22) & 0x1f;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2);
trim->trimRcalIptatCodeParity = (tmpVal >> 30) & 0x01;
trim->trimRcalIptatCodeEn = (tmpVal >> 31) & 0x01;
}
/****************************************************************************/ /**
* @brief Efuse read rcal icx code configuration
*
* @param trim: Trim data pointer
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Read_Rcal_Icx_Code(Efuse_Ana_Rcal_Icx_Code_Type *trim)
{
uint32_t tmpVal;
/* Trigger read data from efuse */
EF_CTRL_LOAD_BEFORE_READ_R0;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2);
trim->trimRcalIcxCode = (tmpVal >> 22) & 0x3f;
trim->trimRcalIcxCodeParity = (tmpVal >> 28) & 0x01;
trim->trimRcalIcxCodeEn = (tmpVal >> 29) & 0x01;
}
/****************************************************************************/ /**
* @brief Efuse read LDO28CIS vout trim configuration
*
* @param trim: Trim data pointer
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Read_LDO28CIS_Vout_Trim(Efuse_Ana_LDO28CIS_Vout_Trim_Type *trim)
{
uint32_t tmpVal;
/* Trigger read data from efuse */
EF_CTRL_LOAD_BEFORE_READ_R0;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3);
trim->trimLDO28CISVout = (tmpVal >> 8) & 0xf;
trim->trimLDO28CISVoutParity = (tmpVal >> 12) & 0x01;
trim->trimLDO28CISVoutEn = (tmpVal >> 13) & 0x01;
}
/****************************************************************************/ /**
* @brief Efuse read LDO15CIS vout trim configuration
*
* @param trim: Trim data pointer
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Read_LDO15CIS_Vout_Trim(Efuse_Ana_LDO15CIS_Vout_Trim_Type *trim)
{
uint32_t tmpVal;
/* Trigger read data from efuse */
EF_CTRL_LOAD_BEFORE_READ_R0;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3);
trim->trimLDO15CISVout = (tmpVal >> 8) & 0xf;
trim->trimLDO15CISVoutParity = (tmpVal >> 12) & 0x01;
trim->trimLDO15CISVoutEn = (tmpVal >> 13) & 0x01;
}
/****************************************************************************/ /**
* @brief Efuse read LDO12UHS vout trim configuration
*
* @param trim: Trim data pointer
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Read_LDO12UHS_Vout_Trim(Efuse_Ana_LDO12UHS_Vout_Trim_Type *trim)
{
uint32_t tmpVal;
/* Trigger read data from efuse */
EF_CTRL_LOAD_BEFORE_READ_R1;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3);
trim->trimLDO12UHSVout = (tmpVal >> 20) & 0xf;
trim->trimLDO12UHSVoutParity = (tmpVal >> 24) & 0x01;
trim->trimLDO12UHSVoutEn = (tmpVal >> 25) & 0x01;
}
/****************************************************************************/ /**
* @brief Efuse read xtal capcode 1 inout configuration
*
* @param trim: Trim data pointer
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Read_Xtal_Capcode1_Inout(Efuse_Ana_Xtal_Capcode_1_Type *trim)
{
uint32_t tmpVal;
/* Trigger read data from efuse */
EF_CTRL_LOAD_BEFORE_READ_R1;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3);
trim->trimXtalCapcode1 = (tmpVal >> 0) & 0x3f;
trim->trimXtalCapcode1Parity = (tmpVal >> 6) & 0x01;
trim->trimXtalCapcode1En = (tmpVal >> 7) & 0x01;
}
/****************************************************************************/ /**
* @brief Efuse read xtal capcode 2 inout configuration
*
* @param trim: Trim data pointer
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Read_Xtal_Capcode2_Inout(Efuse_Ana_Xtal_Capcode_2_Type *trim)
{
uint32_t tmpVal;
/* Trigger read data from efuse */
EF_CTRL_LOAD_BEFORE_READ_R1;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1);
trim->trimXtalCapcode2 = (tmpVal >> 26) & 0x3f;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_0);
trim->trimXtalCapcode2Parity = (tmpVal >> 30) & 0x01;
trim->trimXtalCapcode2En = (tmpVal >> 31) & 0x01;
}
/****************************************************************************/ /**
* @brief Efuse read xtal capcode 3 inout configuration
*
* @param trim: Trim data pointer
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Read_Xtal_Capcode3_Inout(Efuse_Ana_Xtal_Capcode_3_Type *trim)
{
uint32_t tmpVal;
/* Trigger read data from efuse */
EF_CTRL_LOAD_BEFORE_READ_R1;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1);
trim->trimXtalCapcode3 = (tmpVal >> 20) & 0x3f;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_0);
trim->trimXtalCapcode3Parity = (tmpVal >> 28) & 0x01;
trim->trimXtalCapcode3En = (tmpVal >> 29) & 0x01;
}
/****************************************************************************/ /**
* @brief Efuse read gauge vpack offset configuration
*
* @param trim: Trim data pointer
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Read_Gauge_Vpack_Offset(Efuse_Ana_Gauge_Vpack_Offset_Type *trim)
{
uint32_t tmpVal;
/* Trigger read data from efuse */
EF_CTRL_LOAD_BEFORE_READ_R1;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1);
trim->trimGaugeVpackOffset = (tmpVal >> 2) & 0xffff;
trim->trimGaugeVpackOffsetParity = (tmpVal >> 18) & 0x01;
trim->trimGaugeVpackOffsetEn = (tmpVal >> 19) & 0x01;
}
/****************************************************************************/ /**
* @brief Efuse read gauge vtemp offset configuration
*
* @param trim: Trim data pointer
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Read_Gauge_Vtemp_Offset(Efuse_Ana_Gauge_Vtemp_Offset_Type *trim)
{
uint32_t tmpVal;
/* Trigger read data from efuse */
EF_CTRL_LOAD_BEFORE_READ_R1;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_2);
trim->trimGaugeVtempOffset = (tmpVal >> 16) & 0xffff;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1);
trim->trimGaugeVtempOffsetParity = (tmpVal >> 0) & 0x01;
trim->trimGaugeVtempOffsetEn = (tmpVal >> 1) & 0x01;
}
/****************************************************************************/ /**
* @brief Efuse read psram trim configuration
*
* @param trim: Trim data pointer
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Read_Psram_Trim(Efuse_Psram_Trim_Type *trim)
{
uint32_t tmpVal;
/* Trigger read data from efuse */
EF_CTRL_LOAD_BEFORE_READ_R1;
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W2);
trim->psramTrim = (tmpVal >> 0) & 0x7ff;
trim->psramTrimParity = (tmpVal >> 11) & 0x01;
trim->psramTrimEn = (tmpVal >> 12) & 0x01;
}
/****************************************************************************/ /**
* @brief Efuse write psram trim configuration
*
* @param trim: Trim data pointer
* @param program: program to efuse entity or not
*
* @return None
*
*******************************************************************************/
void EF_Ctrl_Write_Psram_Trim(Efuse_Psram_Trim_Type *trim, uint8_t program)
{
uint32_t tmpVal;
/* Switch to AHB clock */
EF_Ctrl_Sw_AHB_Clk_1();
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W2);
tmpVal |= (trim->psramTrim<<0);
tmpVal |= (trim->psramTrimParity<<11);
tmpVal |= (trim->psramTrimEn<<12);
BL_WR_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W2, tmpVal);
if (program) {
EF_Ctrl_Program_Efuse_1();
}
}
/****************************************************************************/ /**
* @brief Whether MAC address slot is empty
*
* @param slot: MAC address slot
* @param reload: whether reload to check
*
* @return 0 for all slots full,1 for others
*
*******************************************************************************/
uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload)
{
uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff;
uint32_t part1Empty = 0, part2Empty = 0;
if (slot == 0) {
/* Switch to AHB clock */
EF_Ctrl_Sw_AHB_Clk_0();
if (reload) {
EF_CTRL_LOAD_BEFORE_READ_R0;
}
tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);
tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
} else if (slot == 1) {
/* Switch to AHB clock */
EF_Ctrl_Sw_AHB_Clk_0();
if (reload) {
EF_CTRL_LOAD_BEFORE_READ_R0;
}
tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2);
tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3);
} else if (slot == 2) {
/* Switch to AHB clock */
EF_Ctrl_Sw_AHB_Clk_0();
if (reload) {
EF_CTRL_LOAD_BEFORE_READ_R0;
}
tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W1);
tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2);
}
part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 32));
part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp2, 0, 22));
return (part1Empty && part2Empty);
}
/****************************************************************************/ /**
* @brief Efuse write optional MAC address
*
* @param slot: MAC address slot
* @param mac[6]: MAC address buffer
* @param program: Whether program
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program)
{
uint8_t *maclow = (uint8_t *)mac;
uint8_t *machigh = (uint8_t *)(mac + 4);
uint32_t tmpVal;
uint32_t i = 0, cnt;
if (slot >= 3) {
return ERROR;
}
/* Change to local order */
for (i = 0; i < 3; i++) {
tmpVal = mac[i];
mac[i] = mac[5 - i];
mac[5 - i] = tmpVal;
}
/* Switch to AHB clock */
EF_Ctrl_Sw_AHB_Clk_0();
/* The low 32 bits */
if (slot == 0) {
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow));
} else if (slot == 1) {
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2, BL_RDWD_FRM_BYTEP(maclow));
} else if (slot == 2) {
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W1, BL_RDWD_FRM_BYTEP(maclow));
}
/* The high 16 bits */
tmpVal = machigh[0] + (machigh[1] << 8);
cnt = 0;
for (i = 0; i < 6; i++) {
cnt += EF_Cfg_Get_Byte_Zero_Cnt(mac[i]);
}
tmpVal |= ((cnt & 0x3f) << 16);
if (slot == 0) {
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal);
} else if (slot == 1) {
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3, tmpVal);
} else if (slot == 2) {
BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2, tmpVal);
}
if (program) {
EF_Ctrl_Program_Efuse_0();
}
return SUCCESS;
}
/****************************************************************************/ /**
* @brief Efuse read optional MAC address
*
* @param slot: MAC address slot
* @param mac[6]: MAC address buffer
* @param reload: Whether reload
*
* @return SUCCESS or ERROR
*
*******************************************************************************/
BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
{
uint8_t *maclow = (uint8_t *)mac;
uint8_t *machigh = (uint8_t *)(mac + 4);
uint32_t tmpVal = 0;
uint32_t i = 0;
uint32_t cnt = 0;
if (slot >= 3) {
return ERROR;
}
/* Trigger read data from efuse */
if (reload) {
EF_CTRL_LOAD_BEFORE_READ_R0;
}
if (slot == 0) {
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW);
} else if (slot == 1) {
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2);
} else if (slot == 2) {
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W1);
}
BL_WRWD_TO_BYTEP(maclow, tmpVal);
if (slot == 0) {
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
} else if (slot == 1) {
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3);
} else if (slot == 2) {
tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2);
}
machigh[0] = tmpVal & 0xff;
machigh[1] = (tmpVal >> 8) & 0xff;
/* Check parity */
for (i = 0; i < 6; i++) {
cnt += EF_Cfg_Get_Byte_Zero_Cnt(mac[i]);
}
if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) {
/* Change to network order */
for (i = 0; i < 3; i++) {
tmpVal = mac[i];
mac[i] = mac[5 - i];
mac[5 - i] = tmpVal;
}
return SUCCESS;
} else {
return ERROR;
}
}
/*@} end of group SEC_EF_CTRL_Public_Functions */
/*@} end of group SEC_EF_CTRL */
/*@} end of group BL808_Peripheral_Driver */

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drivers/soc/bl808/bl808_std/src/bl808_tzc_sec.c Normal file
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/**
******************************************************************************
* @file bl808_tzc_sec.c
* @version V1.0
* @date
* @brief This file is the standard driver c file
******************************************************************************
* @attention
*
* <h2><center>&copy; COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of Bouffalo Lab nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
#include "string.h"
#include "bl808_tzc_sec.h"
#include "bl808_glb.h"
/** @addtogroup BL808_Peripheral_Driver
* @{
*/
/** @addtogroup TZC_ENG
* @{
*/
/** @defgroup TZC_ENG_Private_Macros
* @{
*/
/*@} end of group TZC_ENG_Private_Macros */
/** @defgroup TZC_ENG_Private_Types
* @{
*/
/*@} end of group TZC_ENG_Private_Types */
/** @defgroup TZC_ENG_Private_Variables
* @{
*/
/*@} end of group TZC_ENG_Private_Variables */
/** @defgroup TZC_ENG_Global_Variables
* @{
*/
/*@} end of group TZC_ENG_Global_Variables */
/** @defgroup TZC_ENG_Private_Fun_Declaration
* @{
*/
/*@} end of group TZC_ENG_Private_Fun_Declaration */
/** @defgroup TZC_ENG_Private_Functions
* @{
*/
/*@} end of group TZC_ENG_Private_Functions */
/** @defgroup TZC_ENG_Public_Functions
* @{
*/
/****************************************************************************/ /**
* @brief None
*
* @param None
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_Set_Sboot_Done(void)
{
uint32_t tmpVal;
/* Set Sboot done */
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, 0xf);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
}
void Tzc_Sec_Set_Master_Group(TZC_SEC_Master_Type masterType, uint8_t group)
{
uint32_t tmpVal;
uint32_t tmpVal2;
if (masterType < TZC_SEC_MASTER_D0) {
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID);
tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK);
if (group == 0) {
tmpVal &= (~(1 << masterType));
} else {
tmpVal |= (1 << masterType);
}
tmpVal |= (1 << (masterType + 16));
tmpVal2 |= (1 << masterType);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID, tmpVal);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK, tmpVal2);
} else {
masterType -= TZC_SEC_MASTER_D0;
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID);
tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK);
if (group == 0) {
tmpVal &= (~(1 << masterType));
} else {
tmpVal |= (1 << masterType);
}
tmpVal |= (1 << (masterType + 16));
tmpVal2 |= (1 << masterType);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID, tmpVal);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK, tmpVal2);
}
}
void Tzc_Sec_Set_Slave_Group(TZC_SEC_Slave_Type slaveType, uint8_t group)
{
uint32_t tmpVal;
if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_SLAVE_MAX) {
return;
}
group = 1 << (group);
if (slaveType >= TZC_SEC_SLAVE_MM) {
slaveType -= TZC_SEC_SLAVE_MM;
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S0);
/* set group */
tmpVal &= (~(3 << (slaveType * 2)));
tmpVal |= (group << (slaveType * 2));
/* set lock*/
tmpVal |= (1 << (slaveType + 16));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S0, tmpVal);
} else if (slaveType < TZC_SEC_SLAVE_EMI_MISC) {
slaveType -= TZC_SEC_SLAVE_GLB;
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1);
/* set group */
tmpVal &= (~(3 << (slaveType * 2)));
tmpVal |= (group << (slaveType * 2));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1, tmpVal);
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK);
/* set lock */
tmpVal |= (1 << slaveType);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK, tmpVal);
} else {
slaveType -= TZC_SEC_SLAVE_EMI_MISC;
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S2);
/* set group */
tmpVal &= (~(3 << (slaveType * 2)));
tmpVal |= (group << (slaveType * 2));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S2, tmpVal);
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK);
/* set lock */
tmpVal |= (1 << (slaveType + TZC_SEC_SLAVE_EMI_MISC));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK, tmpVal);
}
}
void Tzc_Sec_Set_MM_Slave_Group(TZC_SEC_MM_Slave_Type slaveType, uint8_t group)
{
uint32_t tmpVal;
if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_MM_SLAVE_MAX) {
return;
}
group = 1 << (group);
if (slaveType < TZC_SEC_MM_SLAVE_ISP_MISC) {
/* set group */
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S0);
tmpVal &= (~(3 << (slaveType * 2)));
tmpVal |= (group << (slaveType * 2));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S0, tmpVal);
/* set lock */
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK0);
tmpVal |= (1 << slaveType);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK0, tmpVal);
} else if (slaveType < TZC_SEC_MM_SLAVE_CODEC_MISC) {
slaveType -= TZC_SEC_MM_SLAVE_ISP_MISC;
/* set group */
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S1);
tmpVal &= (~(3 << (slaveType * 2)));
tmpVal |= (group << (slaveType * 2));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S1, tmpVal);
/* set lock */
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK1);
tmpVal |= (1 << (slaveType + 16));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK1, tmpVal);
} else {
slaveType -= TZC_SEC_MM_SLAVE_CODEC_MISC;
/* set group */
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S2);
tmpVal &= (~(3 << (slaveType * 2)));
tmpVal |= (group << (slaveType * 2));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S2, tmpVal);
/* set lock */
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK1);
tmpVal |= (1 << slaveType);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK1, tmpVal);
}
}
void Tzc_Sec_Set_Glb_Ctrl_Group(TZC_SEC_GLB_Ctrl_Type slaveType, uint8_t group)
{
uint32_t tmpVal;
if (slaveType >= TZC_SEC_GLB_CTRL_MAX || group > TZC_SEC_MAX_AUTH_GRP) {
return;
}
group = 1 << (group);
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_0);
/* set group */
tmpVal &= (~(3 << (slaveType * 2)));
tmpVal |= (group << (slaveType * 2));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_0, tmpVal);
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_2);
/* set lock */
tmpVal |= (1 << slaveType);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_2, tmpVal);
}
void Tzc_Sec_Set_MM_Glb_Ctrl_Group(TZC_SEC_MM_GLB_Ctrl_Type slaveType, uint8_t group)
{
uint32_t tmpVal;
if (slaveType >= TZC_SEC_MM_GLB_CTRL_MAX || group > TZC_SEC_MAX_AUTH_GRP) {
return;
}
group = 1 << (group);
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_0);
/* set group */
tmpVal &= (~(3 << (slaveType * 2)));
tmpVal |= (group << (slaveType * 2));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_0, tmpVal);
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_2);
/* set lock */
tmpVal |= (1 << slaveType);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_CTRL_2, tmpVal);
}
void Tzc_Sec_Set_CPU_Group(uint8_t cpu, uint8_t group)
{
uint32_t tmpVal;
uint32_t tmpVal2;
if (cpu == GLB_CORE_ID_M0) {
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID);
tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_CPU_TZMID, group);
tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, TZC_SEC_TZC_CPU_TZMID_LOCK, 1);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID, tmpVal);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK, tmpVal2);
} else if (cpu == GLB_CORE_ID_D0) {
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID);
tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_MMCPU_TZMID, group);
tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, TZC_SEC_TZC_MMCPU_TZMID, 1);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID, tmpVal);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK, tmpVal2);
} else if (cpu == GLB_CORE_ID_LP) {
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID);
tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_PICO_TZMID, group);
tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, TZC_SEC_TZC_PICO_TZMID_LOCK, 1);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID, tmpVal);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK, tmpVal2);
}
}
/****************************************************************************/ /**
* @brief TrustZone Security set ROM region access configuration
*
* @param region: ROM region index 0-2
* @param startAddr: ROM region start address
* @param length: ROM region length
* @param group: ROM region auth group type
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_ROM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
return;
}
group = 1 << (group);
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
tmpVal &= (~(3 << (region * 2)));
tmpVal |= (group << (region * 2));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_ROM_TZSRG_R0_OFFSET + region * 4, tmpVal);
/* set enable and lock */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
tmpVal |= 1 << (region + 16);
tmpVal |= 1 << (region + 24);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set OCRAM region access configuration
*
* @param region: OCRAM region index 0-2
* @param startAddr: OCRAM region start address
* @param length: OCRAM region length
* @param group: OCRAM region auth group type
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_OCRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
if (region >= 3) {
return;
}
group = group & 0xf;
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);
tmpVal &= (~(0xf << (region * 4)));
tmpVal |= (group << (region * 4));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);
tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_OCRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);
/* set enable and lock */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);
tmpVal |= 1 << (region + 16);
tmpVal |= 1 << (region + 20);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set OCRAM regionx access configuration
*
* @param group: OCRAM region auth group type
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_OCRAM_Access_Set_Regionx(uint8_t group)
{
uint32_t tmpVal = 0;
uint8_t region = 3;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
if (group > TZC_SEC_MAX_AUTH_GRP) {
return;
}
group = 1 << (group);
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);
tmpVal &= (~(3 << (region * 4)));
tmpVal |= (group << (region * 4));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);
/* set enable and lock */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);
tmpVal |= 1 << (region + 16);
tmpVal |= 1 << (region + 20);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set WRAM region access configuration
*
* @param region: WRAM region index 0-2
* @param startAddr: WRAM region start address
* @param length: WRAM region length
* @param group: WRAM region auth group type
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_WRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
if (region >= 3) {
return;
}
group = group & 0xf;
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);
tmpVal &= (~(0xf << (region * 4)));
tmpVal |= (group << (region * 4));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);
tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_WRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);
/* set enable and lock */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);
tmpVal |= 1 << (region + 16);
tmpVal |= 1 << (region + 20);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set WRAM regionx access configuration
*
* @param group: WRAM region auth group type
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_WRAM_Access_Set_Regionx(uint8_t group)
{
uint32_t tmpVal = 0;
uint8_t region = 3;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
if (group > TZC_SEC_MAX_AUTH_GRP) {
return;
}
group = 1 << (group);
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);
tmpVal &= (~(3 << (region * 4)));
tmpVal |= (group << (region * 4));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);
/* set enable and lock */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);
tmpVal |= 1 << (region + 16);
tmpVal |= 1 << (region + 20);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set Flash region access configuration
*
* @param region: Flash region index 0-2
* @param startAddr: Flash region start address
* @param length: Flash region length
* @param group: Flash region auth group type
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_Flash_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t tmpVal2 = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
if (region >= 4 || group > TZC_SEC_MAX_AUTH_GRP) {
return;
}
group = 0xf & (group);
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
tmpVal &= (~(0xf << (region * 4)));
tmpVal |= (group << (region * 4));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
/* Set range */
tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_R0_OFFSET + region * 4, tmpVal);
/* Set range MSB */
tmpVal = BL_RD_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_MSB_OFFSET);
tmpVal = tmpVal & (0xff << (8 * region));
tmpVal2 = ((alignEnd >> 26) & 0x7) | (((startAddr >> 26) & 0x7) << 3);
tmpVal2 = tmpVal2 << (8 * region);
BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_MSB_OFFSET, tmpVal | tmpVal2);
/* set enable and lock */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
tmpVal |= 1 << (region + 20);
tmpVal |= 1 << (region + 25);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set Flash regionx access configuration
*
* @param group: Flash region auth group type
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_Flash_Access_Set_Regionx(uint8_t group)
{
uint32_t tmpVal = 0;
uint8_t region = 4;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
if (group > TZC_SEC_MAX_AUTH_GRP) {
return;
}
group = 1 << (group);
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
tmpVal &= (~(3 << (region * 4)));
tmpVal |= (group << (region * 4));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
/* set enable and lock */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
tmpVal |= 1 << (region + 20);
tmpVal |= 1 << (region + 25);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set L2SRAM region access configuration
*
* @param region: L2SRAM region index 0-2
* @param startAddr: L2SRAM region start address
* @param length: L2SRAM region length
* @param group: L2SRAM region auth group type
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_L2SRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
return;
}
group = 1 << (group);
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_L2SRAM_TZSRG_CTRL);
tmpVal &= (~(3 << (region * 2)));
tmpVal |= (group << (region * 2));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_L2SRAM_TZSRG_CTRL, tmpVal);
tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_L2SRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);
/* set enable and lock */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_L2SRAM_TZSRG_CTRL);
tmpVal |= 1 << (region + 16);
tmpVal |= 1 << (region + 24);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_L2SRAM_TZSRG_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set VRAM region access configuration
*
* @param region: VRAM region index 0-2
* @param startAddr: VRAM region start address
* @param length: VRAM region length
* @param group: VRAM region auth group type
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_VRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
return;
}
group = 1 << (group);
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_VRAM_TZSRG_CTRL);
tmpVal &= (~(3 << (region * 2)));
tmpVal |= (group << (region * 2));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_VRAM_TZSRG_CTRL, tmpVal);
tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_VRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);
/* set enable lock */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_VRAM_TZSRG_CTRL);
tmpVal |= 1 << (region + 16);
tmpVal |= 1 << (region + 24);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_VRAM_TZSRG_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set PSRAMA region access configuration
*
* @param region: PSRAMA region index 0-2
* @param startAddr: PSRAMA region start address
* @param length: PSRAMA region length
* @param group: PSRAMA region auth group type
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_PSRAMA_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
return;
}
group = 1 << (group);
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL);
tmpVal &= (~(3 << (region * 2)));
tmpVal |= (group << (region * 2));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL, tmpVal);
tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMA_TZSRG_R0_OFFSET + region * 4, tmpVal);
/* set enable and lock */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL);
tmpVal |= 1 << (region + 16);
tmpVal |= 1 << (region + 24);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL, tmpVal);
}
/**
* @brief TrustZone Security set Release PSRAMA region access
*
*/
void Tzc_Sec_PSRAMA_Access_Release(void)
{
uint32_t tmpVal = 0;
uint32_t region = 0;
/* set disable */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL);
tmpVal &= (~(1 << (region + 16)));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMA_TZSRG_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set PSRAMB region access configuration
*
* @param region: PSRAMB region index 0-2
* @param startAddr: PSRAMB region start address
* @param length: PSRAMB region length
* @param group: PSRAMB region auth group type
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_PSRAMB_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
return;
}
group = 1 << (group);
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
tmpVal &= (~(3 << (region * 2)));
tmpVal |= (group << (region * 2));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMB_TZSRG_R0_OFFSET + region * 4, tmpVal);
/* set enable and lock */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
tmpVal |= 1 << (region + 16);
tmpVal |= 1 << (region + 24);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
}
/**
* @brief TrustZone Security set Release PSRAMB region access
*
*/
void Tzc_Sec_PSRAMB_Access_Release(void)
{
uint32_t tmpVal = 0;
uint32_t region = 0;
/* set disable */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
tmpVal &= (~(1 << (region + 16)));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set XRAM region access configuration
*
* @param region: XRAM region index 0-2
* @param startAddr: XRAM region start address
* @param length: XRAM region length
* @param group: XRAM region auth group type
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_XRAM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
{
uint32_t tmpVal = 0;
uint32_t alignEnd = (startAddr+length+1023)&~0x3FF;
/* check the parameter */
CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
return;
}
group = 1 << (group);
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_XRAM_TZSRG_CTRL);
tmpVal &= (~(3 << (region * 2)));
tmpVal |= (group << (region * 2));
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_XRAM_TZSRG_CTRL, tmpVal);
tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_XRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);
/* set enable and lock */
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_XRAM_TZSRG_CTRL);
tmpVal |= 1 << (region + 16);
tmpVal |= 1 << (region + 24);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_XRAM_TZSRG_CTRL, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set sec_eng module config
*
* @param mode: sec_eng control mode
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_Set_Se_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode)
{
uint32_t tmpVal = 0;
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SE_TZSID_CRMD, mode);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0, tmpVal);
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);
/* set lock */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SE_TZSID_CRMD_LOCK, 1);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set sf_ctrl module config
*
* @param mode: sf_ctrl control mode
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_Set_Sf_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode)
{
uint32_t tmpVal = 0;
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_1);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SF_TZSID_CRMD, mode);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_1, tmpVal);
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);
/* set lock */
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SF_TZSID_CRMD_LOCK, 1);
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);
}
void Tzc_Sec_Set_Se_Group(TZC_SEC_SE_Ctrl_Type slaveType, uint8_t group)
{
uint32_t tmpVal;
if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_SE_CTRL_MAX) {
return;
}
group = 1 << (group);
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_0);
/* set group */
tmpVal &= (~(3 << (slaveType * 2)));
tmpVal |= (group << (slaveType * 2));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_0, tmpVal);
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);
/* set lock */
tmpVal |= (1 << (slaveType));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);
}
void Tzc_Sec_Set_Sf_Group(TZC_SEC_SF_Ctrl_Type slaveType, uint8_t group)
{
uint32_t tmpVal;
if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_SF_CTRL_MAX) {
return;
}
group = 1 << (group);
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_1);
/* set group */
tmpVal &= (~(3 << (slaveType * 2)));
tmpVal |= (group << (slaveType * 2));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_1, tmpVal);
tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);
/* set lock */
tmpVal |= (1 << (slaveType + 16));
BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);
}
/****************************************************************************/ /**
* @brief TrustZone Security set watchdog reset delay value
*
* @param mode: sec_eng control mode
*
* @return None
*
*******************************************************************************/
void Tzc_Sec_Set_WTD_Rst_Delay(uint16_t delayValue)
{
uint32_t tmpVal = 0;
tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0);
tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SE_WDT_DLY, delayValue);
BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0, tmpVal);
}
/*@} end of group TZC_ENG_Public_Functions */
/*@} end of group TZC_ENG */
/*@} end of group BL808_Peripheral_Driver */

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drivers/soc/bl808/bl808_std/src/bl808_uhs_phy.c Normal file
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