diff --git a/drivers/lhal/bouffalo.mk b/drivers/lhal/bouffalo.mk
index 04a42989..09d039a2 100644
--- a/drivers/lhal/bouffalo.mk
+++ b/drivers/lhal/bouffalo.mk
@@ -10,37 +10,32 @@ COMPONENT_ADD_INCLUDEDIRS += include/arch/risc-v/t-head/Core/Include
 COMPONENT_PRIV_INCLUDEDIRS :=
 
 ## This component's src
-COMPONENT_SRCS := src/bflb_uart.c  \
-				  src/bflb_gpio.c  \
+COMPONENT_SRCS := src/bflb_gpio.c    \
+				  src/bflb_irq.c     \
+				  src/bflb_l1c.c     \
+				  src/bflb_mtimer.c  \
+				  src/bflb_sec_aes.c \
+				  src/bflb_uart.c    \
 
-ifeq ($(CONFIG_CHIP_NAME),BL602)
-CFLAGS   += -DBL602
-endif
+CHIP_NAME = $(shell echo $(CONFIG_CHIP_NAME) | tr A-Z a-z)
+
+COMPONENT_SRCS += config/$(CHIP_NAME)/device_table.c
+COMPONENT_ADD_INCLUDEDIRS += config/$(CHIP_NAME)
+
+CFLAGS += -D$(CONFIG_CHIP_NAME)
+CFLAGS += -DCONFIG_IRQ_NUM=80
+CFLAGS += -DBL_IOT_SDK
 
 ifeq ($(CONFIG_CHIP_NAME),BL616)
-CFLAGS   += -DBL616
 COMPONENT_SRCS += include/arch/risc-v/t-head/rv_hart.c
 COMPONENT_SRCS += include/arch/risc-v/t-head/rv_pmp.c
-COMPONENT_SRCS += config/bl616/device_table.c
+
+ifeq ($(CONFIG_CHERRYUSB),1)
+COMPONENT_SRCS += src/bflb_usb_v2.c
 endif
 
-ifeq ($(CONFIG_CHIP_NAME),BL702)
-CFLAGS   += -DBL702
-COMPONENT_SRCS += config/bl702/device_table.c
-endif
-
-ifeq ($(CONFIG_CHIP_NAME),BL702L)
-CFLAGS   += -DBL702L
-endif
-
-ifeq ($(CONFIG_CHIP_NAME),BL808)
-CFLAGS   += -DBL808
-endif
-
-ifeq ($(CONFIG_CHIP_NAME),BL606P)
-CFLAGS   += -DBL606P
 endif
 
 COMPONENT_OBJS := $(patsubst %.c,%.o, $(COMPONENT_SRCS))
 
-COMPONENT_SRCDIRS := src include/arch/risc-v/t-head config/bl616
+COMPONENT_SRCDIRS := src include/arch/risc-v/t-head config/$(CHIP_NAME)
\ No newline at end of file
diff --git a/drivers/lhal/include/bflb_core.h b/drivers/lhal/include/bflb_core.h
index 8f896ed1..c563cd50 100644
--- a/drivers/lhal/include/bflb_core.h
+++ b/drivers/lhal/include/bflb_core.h
@@ -63,12 +63,9 @@ void assert_func(uint8_t *file, uint32_t line, uint8_t *function, uint8_t *strin
 #define BFLB_DEVICE_TYPE_PKA      32
 #define BFLB_DEVICE_TYPE_CKS      33
 #define BFLB_DEVICE_TYPE_MJPEG    34
-#define BFLB_DEVICE_TYPE_KYS      35
 #define BFLB_DEVICE_TYPE_DBI      36
-#define BFLB_DEVICE_TYPE_PEC      37
 #define BFLB_DEVICE_TYPE_WDT      38
 #define BFLB_DEVICE_TYPE_EF_CTRL  39
-#define BFLB_DEVICE_TYPE_SDIO3    40
 
 struct bflb_device_s {
     const char *name;
diff --git a/drivers/lhal/include/bflb_dma.h b/drivers/lhal/include/bflb_dma.h
index 00ee8b10..5b7f717f 100644
--- a/drivers/lhal/include/bflb_dma.h
+++ b/drivers/lhal/include/bflb_dma.h
@@ -54,20 +54,20 @@
 #define DMA_ADDR_UART1_TDR (0x4000A100 + 0x88)
 #define DMA_ADDR_UART1_RDR (0x4000A100 + 0x8C)
 #endif
-#define DMA_ADDR_I2C0_TDR  (0x4000A300 + 0x88)
-#define DMA_ADDR_I2C0_RDR  (0x4000A300 + 0x8C)
-#define DMA_ADDR_SPI0_TDR  (0x4000A200 + 0x88)
-#define DMA_ADDR_SPI0_RDR  (0x4000A200 + 0x8C)
+#define DMA_ADDR_I2C0_TDR (0x4000A300 + 0x88)
+#define DMA_ADDR_I2C0_RDR (0x4000A300 + 0x8C)
+#define DMA_ADDR_SPI0_TDR (0x4000A200 + 0x88)
+#define DMA_ADDR_SPI0_RDR (0x4000A200 + 0x8C)
 #if !defined(BL702L)
-#define DMA_ADDR_I2S_TDR   (0x4000AA00 + 0x88)
-#define DMA_ADDR_I2S_RDR   (0x4000AA00 + 0x8C)
+#define DMA_ADDR_I2S_TDR (0x4000AA00 + 0x88)
+#define DMA_ADDR_I2S_RDR (0x4000AA00 + 0x8C)
 #endif
-#define DMA_ADDR_ADC_RDR   (0x40002000 + 0x04)
+#define DMA_ADDR_ADC_RDR (0x40002000 + 0x04)
 #if !defined(BL702L)
-#define DMA_ADDR_DAC_TDR   (0x40002000 + 0x48)
+#define DMA_ADDR_DAC_TDR (0x40002000 + 0x48)
 #endif
 #if defined(BL702L)
-#define DMA_ADDR_IR_TDR    (0x4000A600 + 0x88)
+#define DMA_ADDR_IR_TDR (0x4000A600 + 0x88)
 #endif
 /**
   * @}
@@ -83,20 +83,20 @@
 #define DMA_REQUEST_UART1_RX 0x00000002
 #define DMA_REQUEST_UART1_TX 0x00000003
 #endif
-#define DMA_REQUEST_I2C0_RX  0x00000006
-#define DMA_REQUEST_I2C0_TX  0x00000007
+#define DMA_REQUEST_I2C0_RX 0x00000006
+#define DMA_REQUEST_I2C0_TX 0x00000007
 #if defined(BL702L)
-#define DMA_REQUEST_IR_TX    0x00000008
+#define DMA_REQUEST_IR_TX 0x00000008
 #endif
-#define DMA_REQUEST_SPI0_RX  0x0000000A
-#define DMA_REQUEST_SPI0_TX  0x0000000B
+#define DMA_REQUEST_SPI0_RX 0x0000000A
+#define DMA_REQUEST_SPI0_TX 0x0000000B
 #if !defined(BL702L)
-#define DMA_REQUEST_I2S_RX   0x00000014
-#define DMA_REQUEST_I2S_TX   0x00000015
+#define DMA_REQUEST_I2S_RX 0x00000014
+#define DMA_REQUEST_I2S_TX 0x00000015
 #endif
-#define DMA_REQUEST_ADC      0x00000016
+#define DMA_REQUEST_ADC 0x00000016
 #if !defined(BL702L)
-#define DMA_REQUEST_DAC      0x00000017
+#define DMA_REQUEST_DAC 0x00000017
 #endif
 /**
   * @}
@@ -269,8 +269,8 @@
 #define DMA_CMD_SET_SRCADDR_INCREMENT (0x01)
 #define DMA_CMD_SET_DSTADDR_INCREMENT (0x02)
 #if !defined(BL602)
-#define DMA_CMD_SET_ADD_MODE          (0x03)
-#define DMA_CMD_SET_REDUCE_MODE       (0x04)
+#define DMA_CMD_SET_ADD_MODE    (0x03)
+#define DMA_CMD_SET_REDUCE_MODE (0x04)
 #endif
 /**
   * @}
@@ -364,6 +364,9 @@ void bflb_dma_channel_irq_detach(struct bflb_device_s *dev);
 int bflb_dma_channel_lli_reload(struct bflb_device_s *dev,
                                 struct bflb_dma_channel_lli_pool_s *lli_pool, uint32_t max_lli_count,
                                 struct bflb_dma_channel_lli_transfer_s *transfer, uint32_t count);
+void bflb_dma_channel_lli_link_head(struct bflb_device_s *dev,
+                                    struct bflb_dma_channel_lli_pool_s *lli_pool,
+                                    uint32_t used_lli_count);
 
 int bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
 
diff --git a/drivers/lhal/include/bflb_flash.h b/drivers/lhal/include/bflb_flash.h
index 6ff8d75e..91a70245 100644
--- a/drivers/lhal/include/bflb_flash.h
+++ b/drivers/lhal/include/bflb_flash.h
@@ -45,6 +45,7 @@ uint32_t bflb_flash_get_image_offset(void);
 int bflb_flash_erase(uint32_t addr, uint32_t len);
 int bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len);
 int bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len);
+int bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset);
 
 void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config);
 void bflb_flash_aes_enable(void);
diff --git a/drivers/lhal/include/bflb_ir.h b/drivers/lhal/include/bflb_ir.h
index ae319f31..acb9968e 100644
--- a/drivers/lhal/include/bflb_ir.h
+++ b/drivers/lhal/include/bflb_ir.h
@@ -18,9 +18,11 @@
 /** @defgroup IR TX FIFO valid width definition
   * @{
   */
+#if !defined(BL602) && !defined(BL702)
 #define IR_TX_FIFO_WIDTH_8BIT  0
 #define IR_TX_FIFO_WIDTH_16BIT 1
 #define IR_TX_FIFO_WIDTH_24BIT 2
+#endif
 #define IR_TX_FIFO_WIDTH_32BIT 3
 /**
   * @}
@@ -30,8 +32,10 @@
   * @{
   */
 #define IR_TX_INT_END  (1 << 0)
+#if !defined(BL602) && !defined(BL702)
 #define IR_TX_INT_FIFO (1 << 1)
 #define IR_TX_INT_FER  (1 << 2)
+#endif
 /**
   * @}
   */
@@ -52,22 +56,15 @@
   * @{
   */
 #define IR_RX_INT_END  (1 << 0)
+#if !defined(BL602) && !defined(BL702)
 #define IR_RX_INT_FIFO (1 << 1)
 #define IR_RX_INT_FER  (1 << 2)
+#endif
 /**
   * @}
   */
 #endif
 
-/** @defgroup IR word definition
-  * @{
-  */
-#define IR_WORD_0 0
-#define IR_WORD_1 1
-/**
-  * @}
-  */
-
 #if !defined(BL616)
 /**
  * @brief IR TX configuration structure
@@ -166,10 +163,12 @@ void bflb_ir_tx_enable(struct bflb_device_s *dev, bool enable);
 void bflb_ir_txint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask);
 void bflb_ir_txint_clear(struct bflb_device_s *dev);
 uint32_t bflb_ir_txint_status(struct bflb_device_s *dev);
+#if !defined(BL602) && !defined(BL702)
 void bflb_ir_link_txdma(struct bflb_device_s *dev, bool enable);
 uint8_t bflb_ir_txfifo_cnt(struct bflb_device_s *dev);
 void bflb_ir_txfifo_clear(struct bflb_device_s *dev);
 #endif
+#endif
 
 #if !defined(BL702L)
 void bflb_ir_rx_init(struct bflb_device_s *dev, const struct bflb_ir_rx_config_s *config);
diff --git a/drivers/lhal/src/bflb_adc.c b/drivers/lhal/src/bflb_adc.c
index 42a25288..dfb09e25 100644
--- a/drivers/lhal/src/bflb_adc.c
+++ b/drivers/lhal/src/bflb_adc.c
@@ -45,6 +45,23 @@ void bflb_adc_init(struct bflb_device_s *dev, const struct bflb_adc_config_s *co
     regval &= ~AON_GPADC_SOFT_RST;
     putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
 
+    /* disable int and clear status */
+    regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+    regval |= (GPIP_GPADC_FIFO_UNDERRUN_MASK | GPIP_GPADC_FIFO_OVERRUN_MASK | GPIP_GPADC_RDY_MASK |
+               GPIP_GPADC_FIFO_UNDERRUN_CLR | GPIP_GPADC_FIFO_OVERRUN_CLR | GPIP_GPADC_RDY_CLR);
+
+#if defined(BL702) || defined(BL702L)
+    regval |= (GPIP_GPADC_FIFO_RDY_MASK | GPIP_GPADC_FIFO_RDY);
+#endif
+    regval |= GPIP_GPADC_FIFO_CLR;
+    regval &= ~GPIP_GPADC_FIFO_THL_MASK;
+    regval &= ~GPIP_GPADC_DMA_EN;
+    putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+    bflb_adc_start_conversion(dev);
+    bflb_mtimer_delay_ms(1);
+    bflb_adc_stop_conversion(dev);
+
     regval = 0;
     regval |= (2 << AON_GPADC_V18_SEL_SHIFT);                     /* V18 select 1.82V */
     regval |= (1 << AON_GPADC_V11_SEL_SHIFT);                     /* V11 select 1.1V */
@@ -112,6 +129,7 @@ void bflb_adc_init(struct bflb_device_s *dev, const struct bflb_adc_config_s *co
 #endif
     regval |= GPIP_GPADC_FIFO_CLR;
     regval &= ~GPIP_GPADC_FIFO_THL_MASK;
+    regval &= ~GPIP_GPADC_DMA_EN;
     putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
 
     regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
@@ -119,8 +137,8 @@ void bflb_adc_init(struct bflb_device_s *dev, const struct bflb_adc_config_s *co
     regval |= AON_GPADC_POS_SATUR_MASK;
     putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
 
-    coe = bflb_efuse_get_adc_trim();              /* read from efuse */
-    tsen_offset = bflb_efuse_get_adc_tsen_trim(); /* read from efuse */
+    //coe = bflb_efuse_get_adc_trim();              /* read from efuse */
+    //tsen_offset = bflb_efuse_get_adc_tsen_trim(); /* read from efuse */
 }
 
 void bflb_adc_deinit(struct bflb_device_s *dev)
@@ -154,6 +172,7 @@ void bflb_adc_deinit(struct bflb_device_s *dev)
     putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
 
     putreg32(0, reg_base + AON_GPADC_REG_CONFIG1_OFFSET);
+    putreg32(0, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
 }
 
 void bflb_adc_link_rxdma(struct bflb_device_s *dev, bool enable)
diff --git a/drivers/lhal/src/bflb_dma.c b/drivers/lhal/src/bflb_dma.c
index f77650c1..103a101e 100644
--- a/drivers/lhal/src/bflb_dma.c
+++ b/drivers/lhal/src/bflb_dma.c
@@ -270,7 +270,24 @@ int bflb_dma_channel_lli_reload(struct bflb_device_s *dev, struct bflb_dma_chann
     /* clean cache, DMA does not pass through the cache */
     bflb_l1c_dcache_clean_range((uint32_t *)(uintptr_t)lli_pool, sizeof(struct bflb_dma_channel_lli_pool_s) * lli_count_used_offset);
 #endif
-    return 0;
+    return lli_count_used_offset;
+}
+
+void bflb_dma_channel_lli_link_head(struct bflb_device_s *dev,
+                                    struct bflb_dma_channel_lli_pool_s *lli_pool,
+                                    uint32_t used_lli_count)
+{
+    uint32_t channel_base;
+
+    channel_base = dev->reg_base;
+
+    lli_pool[used_lli_count - 1].nextlli = (uint32_t)(uintptr_t)&lli_pool[0];
+
+    putreg32(lli_pool[0].nextlli, channel_base + DMA_CxLLI_OFFSET);
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+    /* clean cache, DMA does not pass through the cache */
+    bflb_l1c_dcache_clean_range((uint32_t *)(uintptr_t)lli_pool, sizeof(struct bflb_dma_channel_lli_pool_s) * used_lli_count);
+#endif
 }
 
 int bflb_dma_channel_start(struct bflb_device_s *dev)
diff --git a/drivers/lhal/src/bflb_emac.c b/drivers/lhal/src/bflb_emac.c
index 12bd5ef2..4e034cb7 100644
--- a/drivers/lhal/src/bflb_emac.c
+++ b/drivers/lhal/src/bflb_emac.c
@@ -187,6 +187,8 @@ int emac_bd_fragment_support(void)
     return 1;
 #elif defined(BL702)
     return 0;
+#elif defined(BL628)
+    return 1;
 #endif
 }
 /**
@@ -215,7 +217,7 @@ int bflb_emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in
         //printf(TAG"%s:%d\n", __func__, __LINE__);
     } else {
 #if defined(BL616)
-        __DSB();
+        __ASM volatile("fence");
 #endif
         // printf("tx q flags:%d,len:%d,data:0x%x\r\n", flags, len, data_in);
         if (flags & EMAC_NOCOPY_PACKET) {
diff --git a/drivers/lhal/src/bflb_ir.c b/drivers/lhal/src/bflb_ir.c
index 5cccaae5..2a4288b4 100644
--- a/drivers/lhal/src/bflb_ir.c
+++ b/drivers/lhal/src/bflb_ir.c
@@ -12,7 +12,11 @@ void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s
     uint32_t ir_clock;
     struct bflb_ir_tx_config_s *tx_config = (struct bflb_ir_tx_config_s *)config;
     
+#if defined(BL602) || defined(BL702)
+    *(uint32_t *)0x40000224 |= 1 << 31;
+#else
     *(uint32_t *)0x20000144 |= 1 << 31;
+#endif
     
     if (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_IR, 0)) {
         ir_clock = bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_IR, 0);
@@ -97,13 +101,19 @@ void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s
     regval = (tx_config->pulse_width_unit & 0xfff) | tx_config->modu_width_1 << 16 | tx_config->modu_width_0 << 24;
     putreg32(regval, reg_base + IRTX_PULSE_WIDTH_OFFSET);
     
+#if !defined(BL602) && !defined(BL702)
     regval = getreg32(reg_base + IR_FIFO_CONFIG_1_OFFSET);
     regval &= ~IR_TX_FIFO_TH_MASK;
     regval |= tx_config->fifo_threshold << IR_TX_FIFO_TH_SHIFT;
     putreg32(regval, reg_base + IR_FIFO_CONFIG_1_OFFSET);
+#endif
     
     regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
+#if defined(BL602) || defined(BL702)
+    regval &= ~(IR_CR_IRTX_SWM_EN | IR_CR_IRTX_MOD_EN | IR_CR_IRTX_OUT_INV);
+#else
     regval &= ~(IR_CR_IRTX_SWM_EN | IR_CR_IRTX_MOD_EN | IR_CR_IRTX_OUT_INV | IR_CR_IRTX_FRM_FRAME_SIZE_MASK);
+#endif
     if (tx_config->swm_enable) {
         regval |= IR_CR_IRTX_SWM_EN;
     }
@@ -113,12 +123,18 @@ void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s
     if (tx_config->output_inverse) {
         regval |= IR_CR_IRTX_OUT_INV;
     }
+#if !defined(BL602) && !defined(BL702)
     regval |= (tx_config->fifo_width & 0x3) << IR_CR_IRTX_FRM_FRAME_SIZE_SHIFT;
+#endif
     if (tx_config->tx_mode == IR_TX_SWM) {
         putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
         return;
     }
+#if defined(BL602) || defined(BL702)
+    regval &= IR_CR_IRTX_SWM_EN | IR_CR_IRTX_MOD_EN | IR_CR_IRTX_OUT_INV;
+#else
     regval &= IR_CR_IRTX_SWM_EN | IR_CR_IRTX_MOD_EN | IR_CR_IRTX_OUT_INV | IR_CR_IRTX_FRM_FRAME_SIZE_MASK;
+#endif
     regval |= (tx_config->data_bits - 1) << IR_CR_IRTX_DATA_NUM_SHIFT;
     if (tx_config->tail_inverse) {
         regval |= IR_CR_IRTX_TAIL_HL_INV;
@@ -141,38 +157,60 @@ void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s
     if (tx_config->data_enable) {
         regval |= IR_CR_IRTX_DATA_EN;
     }
+#if !defined(BL602) && !defined(BL702)
     if (tx_config->freerun_enable) {
         regval |= IR_CR_IRTX_FRM_EN;
     }
     if (tx_config->continue_enable) {
         regval |= IR_CR_IRTX_FRM_CONT_EN;
     }
+#endif
     putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
     
-    regval = getreg32(reg_base + IRTX_PW_0_OFFSET);
+#if defined(BL602) || defined(BL702)
+    regval = (tx_config->tail_pulse_width_1 & 0xf) << 28 | \
+             (tx_config->tail_pulse_width_0 & 0xf) << 24 | \
+             (tx_config->head_pulse_width_1 & 0xf) << 20 | \
+             (tx_config->head_pulse_width_0 & 0xf) << 16 | \
+             (tx_config->logic1_pulse_width_1 & 0xf) << 12 | \
+             (tx_config->logic1_pulse_width_0 & 0xf) << 8 | \
+             (tx_config->logic0_pulse_width_1 & 0xf) << 4 | \
+             (tx_config->logic0_pulse_width_0 & 0xf);
+    putreg32(regval, reg_base + IRTX_PW_OFFSET);
+#else
     regval = tx_config->logic0_pulse_width_0 | tx_config->logic0_pulse_width_1 << 8 | \
              tx_config->logic1_pulse_width_0 << 16 | tx_config->logic1_pulse_width_1 << 24;
     putreg32(regval, reg_base + IRTX_PW_0_OFFSET);
     
-    regval = getreg32(reg_base + IRTX_PW_1_OFFSET);
     regval = tx_config->head_pulse_width_0 | tx_config->head_pulse_width_1 << 8 | \
              tx_config->tail_pulse_width_0 << 16 | tx_config->tail_pulse_width_1 << 24;
     putreg32(regval, reg_base + IRTX_PW_1_OFFSET);
+#endif
 }
 
 void bflb_ir_send(struct bflb_device_s *dev, uint32_t *data, uint32_t length)
 {
     uint32_t reg_base;
     uint32_t regval;
+#if !defined(BL602) && !defined(BL702)
     uint32_t i = 0;
+#endif
     
     bflb_ir_txint_clear(dev);
     
     reg_base = dev->reg_base;
+#if defined(BL602) || defined(BL702)
+    putreg32(data[0], reg_base + IRTX_DATA_WORD0_OFFSET);
+    if (length > 1) {
+        putreg32(data[1], reg_base + IRTX_DATA_WORD1_OFFSET);
+    }
+#endif
+    
     regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
     regval |= IR_CR_IRTX_EN;
     putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
     
+#if !defined(BL602) && !defined(BL702)
     if ((regval & IR_CR_IRTX_FRM_EN) == 0) {
         length = length < 4 ? length : 4;
     }
@@ -192,6 +230,11 @@ void bflb_ir_send(struct bflb_device_s *dev, uint32_t *data, uint32_t length)
             /* Waiting for sending */
         }
     }
+#else
+    while((bflb_ir_txint_status(dev) & IR_TX_INT_END) == 0){
+        /* Waiting for sending */
+    }
+#endif
 
     regval &= ~IR_CR_IRTX_EN;
     putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
@@ -204,7 +247,11 @@ void bflb_ir_swm_send(struct bflb_device_s *dev, uint16_t *data, uint8_t length)
     uint32_t reg_base;
     uint32_t regval;
     uint16_t min_data = data[0];
+#if defined(BL602) || defined(BL702)
+    uint32_t count = (length + 7) / 8;
+#else
     uint32_t count = (length + 3) / 4;
+#endif
     uint32_t pwval = 0;
     uint32_t i, j;
     
@@ -228,12 +275,36 @@ void bflb_ir_swm_send(struct bflb_device_s *dev, uint16_t *data, uint8_t length)
     regval |= min_data << IR_CR_IRTX_PW_UNIT_SHIFT;
     putreg32(regval, reg_base + IRTX_PULSE_WIDTH_OFFSET);
 
+#if defined(BL602) || defined(BL702)
+    /* Set tx SWM pulse width data as multiples of pulse width unit */
+    for (i = 0; i < count; i++) {
+        pwval = 0;
+
+        if (i < count - 1) {
+            for (j = 0; j < 8; j++) {
+                regval = ((2 * data[j + i * 8] + min_data) / (2 * min_data) - 1) & 0xf;
+                pwval |= regval << (4 * j);
+            }
+
+            putreg32(pwval, reg_base + IRTX_SWM_PW_0_OFFSET + i * 4);
+        } else {
+            for (j = 0; j < length % 8; j++) {
+                regval = ((2 * data[j + i * 8] + min_data) / (2 * min_data) - 1) & 0xf;
+                pwval |= regval << (4 * j);
+            }
+
+            putreg32(pwval, reg_base + IRTX_SWM_PW_0_OFFSET + i * 4);
+        }
+    }
+#endif
+
     regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
     regval &= ~IR_CR_IRTX_DATA_NUM_MASK;
     regval |= (length - 1) << IR_CR_IRTX_DATA_NUM_SHIFT;
     regval |= IR_CR_IRTX_EN;
     putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
 
+#if !defined(BL602) && !defined(BL702)
     /* Calculate tx SWM pulse width data as multiples of pulse width unit */
     for (i = 0; i < count; i++) {
         pwval = 0;
@@ -258,11 +329,13 @@ void bflb_ir_swm_send(struct bflb_device_s *dev, uint16_t *data, uint8_t length)
         while(bflb_ir_txfifo_cnt(dev) == 0){}
         putreg32(pwval, reg_base + IR_FIFO_WDATA_OFFSET);
     }
+#endif
     
     while((bflb_ir_txint_status(dev) & IR_TX_INT_END) == 0){
         /* Waiting for sending */
     }
     
+    regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
     regval &= ~IR_CR_IRTX_EN;
     putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
     
@@ -318,6 +391,7 @@ uint32_t bflb_ir_txint_status(struct bflb_device_s *dev)
     return (getreg32(reg_base + IRTX_INT_STS_OFFSET) & 0x7);
 }
 
+#if !defined(BL602) && !defined(BL702)
 void bflb_ir_link_txdma(struct bflb_device_s *dev, bool enable)
 {
     uint32_t reg_base;
@@ -352,6 +426,7 @@ void bflb_ir_txfifo_clear(struct bflb_device_s *dev)
     putreg32(regval, reg_base + IR_FIFO_CONFIG_0_OFFSET);
 }
 #endif
+#endif
 
 #if !defined(BL702L)
 void bflb_ir_rx_init(struct bflb_device_s *dev, const struct bflb_ir_rx_config_s *config)
@@ -399,10 +474,12 @@ void bflb_ir_rx_init(struct bflb_device_s *dev, const struct bflb_ir_rx_config_s
     regval = end_threshold << IR_CR_IRRX_END_TH_SHIFT | data_threshold;
     putreg32(regval, reg_base + IRRX_PW_CONFIG_OFFSET);
     
+#if !defined(BL602) && !defined(BL702)
     regval = getreg32(reg_base + IR_FIFO_CONFIG_1_OFFSET);
     regval &= ~IR_RX_FIFO_TH_MASK;
     regval |= config->fifo_threshold << IR_RX_FIFO_TH_SHIFT;
     putreg32(regval, reg_base + IR_FIFO_CONFIG_1_OFFSET);
+#endif
 }
 
 uint8_t bflb_ir_receive(struct bflb_device_s *dev, uint64_t *data)
@@ -451,7 +528,11 @@ uint8_t bflb_ir_swm_receive(struct bflb_device_s *dev, uint16_t *data, uint8_t l
     
     while((bflb_ir_rxint_status(dev) & IR_RX_INT_END) == 0){
         if (bflb_ir_rxfifo_cnt(dev) != 0 && i < length) {
+#if defined(BL602) || defined(BL702)
+            data[i] = getreg32(reg_base + IRRX_SWM_FIFO_RDATA_OFFSET);
+#else
             data[i] = getreg32(reg_base + IR_FIFO_RDATA_OFFSET);
+#endif
             i++;
         }
     }
@@ -519,7 +600,11 @@ uint8_t bflb_ir_rxfifo_cnt(struct bflb_device_s *dev)
     uint32_t reg_base;
     
     reg_base = dev->reg_base;
+#if defined(BL602) || defined(BL702)
+    return ((getreg32(reg_base + IRRX_SWM_FIFO_CONFIG_0_OFFSET) & IR_RX_FIFO_CNT_MASK) >> IR_RX_FIFO_CNT_SHIFT);
+#else
     return ((getreg32(reg_base + IR_FIFO_CONFIG_1_OFFSET) & IR_RX_FIFO_CNT_MASK) >> IR_RX_FIFO_CNT_SHIFT);
+#endif
 }
 
 void bflb_ir_rxfifo_clear(struct bflb_device_s *dev)
@@ -528,8 +613,14 @@ void bflb_ir_rxfifo_clear(struct bflb_device_s *dev)
     uint32_t regval;
     
     reg_base = dev->reg_base;
+#if defined(BL602) || defined(BL702)
+    regval = getreg32(reg_base + IRRX_SWM_FIFO_CONFIG_0_OFFSET);
+    regval |= IR_RX_FIFO_CLR;
+    putreg32(regval, reg_base + IRRX_SWM_FIFO_CONFIG_0_OFFSET);
+#else
     regval = getreg32(reg_base + IR_FIFO_CONFIG_0_OFFSET);
     regval |= IR_RX_FIFO_CLR;
     putreg32(regval, reg_base + IR_FIFO_CONFIG_0_OFFSET);
+#endif
 }
 #endif
diff --git a/drivers/lhal/src/bflb_l1c.c b/drivers/lhal/src/bflb_l1c.c
index b7fd6e35..0b8af078 100644
--- a/drivers/lhal/src/bflb_l1c.c
+++ b/drivers/lhal/src/bflb_l1c.c
@@ -58,8 +58,10 @@ ATTR_TCM_SECTION void bflb_l1c_dcache_clean_invalidate_range(void *addr, uint32_
 }
 #else
 
+#if defined(BL702) || defined(BL702L)
 extern void L1C_Cache_Enable_Set(uint8_t wayDisable);
 extern void L1C_Cache_Flush(void);
+#endif
 
 void bflb_l1c_icache_enable(void)
 {
@@ -67,7 +69,9 @@ void bflb_l1c_icache_enable(void)
 
 void bflb_l1c_icache_disable(void)
 {
+#if defined(BL702) || defined(BL702L)
     L1C_Cache_Enable_Set(0x0f);
+#endif
 }
 
 void bflb_l1c_icache_invalid_all(void)
@@ -88,12 +92,16 @@ void bflb_l1c_dcache_clean_all(void)
 
 void bflb_l1c_dcache_invalidate_all(void)
 {
+#if defined(BL702) || defined(BL702L)
     L1C_Cache_Flush();
+#endif
 }
 
 void bflb_l1c_dcache_clean_invalidate_all(void)
 {
+#if defined(BL702) || defined(BL702L)
     L1C_Cache_Flush();
+#endif
 }
 
 void bflb_l1c_dcache_clean_range(void *addr, uint32_t size)
@@ -102,7 +110,9 @@ void bflb_l1c_dcache_clean_range(void *addr, uint32_t size)
 
 ATTR_TCM_SECTION void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size)
 {
+#if defined(BL702) || defined(BL702L)
     L1C_Cache_Flush();
+#endif
 }
 
 #endif
\ No newline at end of file
diff --git a/drivers/lhal/src/bflb_mtimer.c b/drivers/lhal/src/bflb_mtimer.c
index 5ef4f570..e9154756 100644
--- a/drivers/lhal/src/bflb_mtimer.c
+++ b/drivers/lhal/src/bflb_mtimer.c
@@ -35,12 +35,12 @@ void bflb_mtimer_config(uint64_t ticks, void (*interruptfun)(void))
     bflb_irq_enable(7);
 }
 
-__WEAK uint32_t bflb_mtimer_get_freq(void)
+__WEAK uint32_t ATTR_TCM_SECTION bflb_mtimer_get_freq(void)
 {
     return 1 * 1000 * 1000;
 }
 
-uint64_t bflb_mtimer_get_time_us()
+uint64_t ATTR_TCM_SECTION bflb_mtimer_get_time_us()
 {
     volatile uint64_t tmp_low, tmp_high, tmp_low1, tmp_high1;
 
@@ -64,12 +64,12 @@ uint64_t bflb_mtimer_get_time_us()
 #endif
 }
 
-uint64_t bflb_mtimer_get_time_ms()
+uint64_t ATTR_TCM_SECTION bflb_mtimer_get_time_ms()
 {
     return bflb_mtimer_get_time_us() / 1000;
 }
 
-void bflb_mtimer_delay_us(uint32_t time)
+void ATTR_TCM_SECTION bflb_mtimer_delay_us(uint32_t time)
 {
     uint64_t start_time = bflb_mtimer_get_time_us();
 
@@ -77,7 +77,7 @@ void bflb_mtimer_delay_us(uint32_t time)
     }
 }
 
-void bflb_mtimer_delay_ms(uint32_t time)
+void ATTR_TCM_SECTION bflb_mtimer_delay_ms(uint32_t time)
 {
     uint64_t start_time = bflb_mtimer_get_time_ms();
 
diff --git a/drivers/lhal/src/bflb_timer.c b/drivers/lhal/src/bflb_timer.c
index 9ac5af8b..697aa4c0 100644
--- a/drivers/lhal/src/bflb_timer.c
+++ b/drivers/lhal/src/bflb_timer.c
@@ -90,6 +90,14 @@ void bflb_timer_init(struct bflb_device_s *dev, const struct bflb_timer_config_s
 
 void bflb_timer_deinit(struct bflb_device_s *dev)
 {
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + TIMER_TCER_OFFSET);
+    regval &= ~(1 << (dev->idx + 1));
+    putreg32(regval, reg_base + TIMER_TCER_OFFSET);
 }
 
 void bflb_timer_start(struct bflb_device_s *dev)
diff --git a/drivers/lhal/src/bflb_usb_v1.c b/drivers/lhal/src/bflb_usb_v1.c
index e0ee6cd9..88d90c9d 100644
--- a/drivers/lhal/src/bflb_usb_v1.c
+++ b/drivers/lhal/src/bflb_usb_v1.c
@@ -305,6 +305,11 @@ int usbd_set_address(const uint8_t addr)
     return 0;
 }
 
+uint8_t usbd_get_port_speed(const uint8_t port)
+{
+    return USB_SPEED_FULL;
+}
+
 int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
 {
     uint8_t ep;
diff --git a/drivers/lhal/src/bflb_usb_v2.c b/drivers/lhal/src/bflb_usb_v2.c
index b376c00b..7a664758 100644
--- a/drivers/lhal/src/bflb_usb_v2.c
+++ b/drivers/lhal/src/bflb_usb_v2.c
@@ -601,6 +601,22 @@ int usbd_set_address(const uint8_t addr)
     return 0;
 }
 
+uint8_t usbd_get_port_speed(const uint8_t port)
+{
+    uint8_t speed = 3;
+
+    speed = (getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET) & USB_SPD_TYP_HOV_POV_MASK) >> USB_SPD_TYP_HOV_POV_SHIFT;
+
+    if (speed == 0) {
+        return USB_SPEED_FULL;
+    } else if (speed == 1) {
+        return USB_SPEED_LOW;
+    } else if (speed == 2) {
+        return USB_SPEED_HIGH;
+    }
+    return USB_SPEED_HIGH;
+}
+
 int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
 {
     uint8_t ep;
diff --git a/drivers/soc/bl602/port/bl602_flash.c b/drivers/soc/bl602/port/bl602_flash.c
index 9ab4f837..0361e306 100644
--- a/drivers/soc/bl602/port/bl602_flash.c
+++ b/drivers/soc/bl602/port/bl602_flash.c
@@ -193,6 +193,43 @@ int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len)
     return ret;
 }
 
+int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset)
+{
+    uint8_t isAesEnable = 0;
+    uint32_t tmp[1];
+    int stat;
+
+    SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
+
+    XIP_SFlash_Opt_Enter(&isAesEnable);
+    /* To make it simple, exit cont read anyway */
+    SFlash_Reset_Continue_Read(&g_flash_cfg);
+
+    if (g_flash_cfg.cReadSupport == 0) {
+        cont_read = 0;
+    }
+
+    if (cont_read == 1) {
+        stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
+
+        if (0 != stat) {
+            XIP_SFlash_Opt_Exit(isAesEnable);
+            return -1;
+        }
+    }
+
+    /* Set default value */
+    SFlash_Cache_Enable_Set(0xf);
+
+    if (cache_enable) {
+        SF_Ctrl_Set_Flash_Image_Offset(flash_offset);
+        SFlash_Cache_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, cache_way_disable);
+    }
+    XIP_SFlash_Opt_Exit(isAesEnable);
+
+    return 0;
+}
+
 void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config)
 {
     uint8_t hw_key_enable = 0;
diff --git a/drivers/soc/bl616/port/bl616_flash.c b/drivers/soc/bl616/port/bl616_flash.c
index 8e5499d0..9eb7e8e1 100644
--- a/drivers/soc/bl616/port/bl616_flash.c
+++ b/drivers/soc/bl616/port/bl616_flash.c
@@ -11,7 +11,7 @@ static uint32_t g_jedec_id2 = 0;
 static SPI_Flash_Cfg_Type g_flash_cfg;
 static SPI_Flash_Cfg_Type g_flash2_cfg;
 
-uint32_t flash2_get_jedecid(void)
+uint32_t bflb_flash2_get_jedec_id(void)
 {
     uint32_t jid = 0;
 
@@ -19,14 +19,6 @@ uint32_t flash2_get_jedecid(void)
     return jid;
 }
 
-uint32_t flash_get_size(SF_Ctrl_Bank_Select bank)
-{
-    if (bank == SF_CTRL_FLASH_BANK1) {
-        return flash2_size;
-    }
-    return flash1_size;
-}
-
 static void flash_get_clock_delay(SPI_Flash_Cfg_Type *cfg)
 {
     uint32_t tmpVal = 0;
@@ -120,7 +112,7 @@ static int ATTR_TCM_SECTION flash2_init(void)
     int stat = -1;
     uint32_t ret = 0;
     uint32_t jid = 0;
-    Efuse_Device_Info_Type deviceInfo;
+    bflb_efuse_device_info_type deviceInfo;
     SF_Ctrl_Bank2_Cfg sfBank2Cfg = {
         .sbus2Select = ENABLE,
         .bank2RxClkInvertSrc = DISABLE,
@@ -141,7 +133,7 @@ static int ATTR_TCM_SECTION flash2_init(void)
         .cmdsWrapLen = SF_CTRL_WRAP_LEN_4096,
     };
 
-    EF_Ctrl_Read_Device_Info(&deviceInfo);
+    bflb_ef_ctrl_get_device_info(&deviceInfo);
     if (deviceInfo.memoryInfo == 0) {
         /* memoryInfo==0, external flash */
         flash1_size = 64 * 1024 * 1024;
@@ -376,6 +368,40 @@ int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len)
     return stat;
 }
 
+int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset)
+{
+    uint8_t isAesEnable = 0;
+    uint32_t tmp[1];
+    int stat;
+
+    SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
+
+    XIP_SFlash_Opt_Enter(&isAesEnable);
+    /* To make it simple, exit cont read anyway */
+    SFlash_Reset_Continue_Read(&g_flash_cfg);
+
+    if (g_flash_cfg.cReadSupport == 0) {
+        cont_read = 0;
+    }
+
+    if (cont_read == 1) {
+        stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
+
+        if (0 != stat) {
+            XIP_SFlash_Opt_Exit(isAesEnable);
+            return -1;
+        }
+    }
+
+    /* TODO: Set default value */
+    SF_Ctrl_Set_Flash_Image_Offset(flash_offset, 0, 0);
+    SFlash_IDbus_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, 0);
+
+    XIP_SFlash_Opt_Exit(isAesEnable);
+
+    return 0;
+}
+
 void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config)
 {
     uint8_t hw_key_enable = 0;
diff --git a/drivers/soc/bl702/port/bl702_flash.c b/drivers/soc/bl702/port/bl702_flash.c
index 08b202d1..9e411ae1 100644
--- a/drivers/soc/bl702/port/bl702_flash.c
+++ b/drivers/soc/bl702/port/bl702_flash.c
@@ -3,7 +3,7 @@
 #include "bl702_xip_sflash_ext.h"
 #include "bl702_sf_cfg.h"
 #include "bl702_sf_cfg_ext.h"
-#include "bl702_ef_ctrl.h"
+#include "bl702_ef_cfg.h"
 #include "bflb_flash.h"
 
 static uint32_t g_jedec_id = 0;
@@ -31,9 +31,10 @@ static void ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg)
 static void ATTR_TCM_SECTION flash_sf2_gpio_init(void)
 {
     uint32_t tmpVal;
-    Efuse_Device_Info_Type devInfo;
+    bflb_efuse_device_info_type devInfo;
+
+    bflb_ef_ctrl_get_device_info(&devInfo);
 
-    EF_Ctrl_Read_Device_Info(&devInfo);
     /* flash_cfg != BFLB_FLASH_CFG_SF1_EXT_17_22, flash pad use SF2 */
     if (devInfo.flash_cfg != BFLB_FLASH_CFG_SF1_EXT_17_22) {
         tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
@@ -179,6 +180,42 @@ int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len)
     return ret;
 }
 
+int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset)
+{
+    uint32_t tmp[1];
+    int stat;
+
+    SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
+
+    XIP_SFlash_Opt_Enter();
+    /* To make it simple, exit cont read anyway */
+    SFlash_Reset_Continue_Read(&g_flash_cfg);
+
+    if (g_flash_cfg.cReadSupport == 0) {
+        cont_read = 0;
+    }
+
+    if (cont_read == 1) {
+        stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
+
+        if (0 != stat) {
+            XIP_SFlash_Opt_Exit();
+            return -1;
+        }
+    }
+
+    /* Set default value */
+    L1C_Cache_Enable_Set(0xf);
+
+    if (cache_enable) {
+        SF_Ctrl_Set_Flash_Image_Offset(flash_offset);
+        SFlash_Cache_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, cache_way_disable);
+    }
+    XIP_SFlash_Opt_Exit();
+
+    return 0;
+}
+
 void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config)
 {
     uint8_t hw_key_enable = 0;
diff --git a/drivers/soc/bl808/port/bl808_flash.c b/drivers/soc/bl808/port/bl808_flash.c
index 003ce35b..3f8be629 100644
--- a/drivers/soc/bl808/port/bl808_flash.c
+++ b/drivers/soc/bl808/port/bl808_flash.c
@@ -224,6 +224,41 @@ int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len)
     return stat;
 }
 
+int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset)
+{
+    uint8_t isAesEnable = 0;
+    uint32_t tmp[1];
+    int stat;
+
+    SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
+
+    XIP_SFlash_Opt_Enter(&isAesEnable);
+    /* To make it simple, exit cont read anyway */
+    SFlash_Reset_Continue_Read(&g_flash_cfg);
+
+    if (g_flash_cfg.cReadSupport == 0) {
+        cont_read = 0;
+    }
+
+    if (cont_read == 1) {
+        stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
+
+        if (0 != stat) {
+            XIP_SFlash_Opt_Exit(isAesEnable);
+            return -1;
+        }
+    }
+
+    /* TODO: Set default value */
+
+    SF_Ctrl_Set_Flash_Image_Offset(flash_offset, 0, 0);
+    SFlash_IDbus_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, SF_CTRL_FLASH_BANK0);
+
+    XIP_SFlash_Opt_Exit(isAesEnable);
+
+    return 0;
+}
+
 void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config)
 {
     uint8_t hw_key_enable = 0;