93 lines
4.2 KiB
C
93 lines
4.2 KiB
C
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/**
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******************************************************************************
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* @file rtc_reg.h
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* @version V1.0
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* @date 2022-08-05
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2020 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __HARDWARE_RTC_H__
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#define __HARDWARE_RTC_H__
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Register offsets *********************************************************/
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#define HBN_CTL_OFFSET (0x0) /* HBN_CTL */
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#define HBN_TIME_L_OFFSET (0x4) /* HBN_TIME_L */
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#define HBN_TIME_H_OFFSET (0x8) /* HBN_TIME_H */
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#define HBN_RTC_TIME_L_OFFSET (0xC) /* RTC_TIME_L */
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#define HBN_RTC_TIME_H_OFFSET (0x10) /* RTC_TIME_H */
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/* Register Bitfield definitions *****************************************************/
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/* 0x0 : HBN_CTL */
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#define HBN_RTC_CTL_SHIFT (0U)
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#define HBN_RTC_CTL_MASK (0x7f << HBN_RTC_CTL_SHIFT)
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#define HBN_MODE (1 << 7U)
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#define HBN_TRAP_MODE (1 << 8U)
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#define HBN_PWRDN_HBN_CORE (1 << 9U)
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#define HBN_PWRDN_HBN_RTC (1 << 11U)
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#define HBN_SW_RST (1 << 12U)
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#define HBN_DIS_PWR_OFF_LDO11 (1 << 13U)
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#define HBN_DIS_PWR_OFF_LDO11_RT (1 << 14U)
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#define HBN_LDO11_RT_VOUT_SEL_SHIFT (15U)
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#define HBN_LDO11_RT_VOUT_SEL_MASK (0xf << HBN_LDO11_RT_VOUT_SEL_SHIFT)
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#define HBN_LDO11_AON_VOUT_SEL_SHIFT (19U)
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#define HBN_LDO11_AON_VOUT_SEL_MASK (0xf << HBN_LDO11_AON_VOUT_SEL_SHIFT)
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#define HBN_PU_DCDC18_AON (1 << 23U)
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#define HBN_RTC_DLY_OPTION (1 << 24U)
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#define HBN_PWR_ON_OPTION (1 << 25U)
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#define HBN_SRAM_SLP_OPTION (1 << 26U)
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#define HBN_SRAM_SLP (1 << 27U)
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#define HBN_STATE_SHIFT (28U)
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#define HBN_STATE_MASK (0xf << HBN_STATE_SHIFT)
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/* 0x4 : HBN_TIME_L */
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#define HBN_TIME_L_SHIFT (0U)
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#define HBN_TIME_L_MASK (0xffffffff << HBN_TIME_L_SHIFT)
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/* 0x8 : HBN_TIME_H */
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#define HBN_TIME_H_SHIFT (0U)
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#define HBN_TIME_H_MASK (0xff << HBN_TIME_H_SHIFT)
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/* 0xC : RTC_TIME_L */
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#define HBN_RTC_TIME_LATCH_L_SHIFT (0U)
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#define HBN_RTC_TIME_LATCH_L_MASK (0xffffffff << HBN_RTC_TIME_LATCH_L_SHIFT)
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/* 0x10 : RTC_TIME_H */
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#define HBN_RTC_TIME_LATCH_H_SHIFT (0U)
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#define HBN_RTC_TIME_LATCH_H_MASK (0xff << HBN_RTC_TIME_LATCH_H_SHIFT)
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#define HBN_RTC_TIME_LATCH (1 << 31U)
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#endif /* __HARDWARE_RTC_H__ */
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