514 lines
36 KiB
C
514 lines
36 KiB
C
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/**
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******************************************************************************
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* @file spi_reg.h
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* @version V1.2
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* @date 2019-10-21
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* @brief This file is the description of.IP register
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******************************************************************************
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* @attention
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*
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* <h2><center>© COPYRIGHT(c) 2019 Bouffalo Lab</center></h2>
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1. Redistributions of source code must retain the above copyright notice,
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* this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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* 3. Neither the name of Bouffalo Lab nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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******************************************************************************
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*/
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#ifndef __SPI_REG_H__
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#define __SPI_REG_H__
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#include "bl602.h"
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/* 0x0 : spi_config */
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#define SPI_CONFIG_OFFSET (0x0)
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#define SPI_CR_SPI_M_EN SPI_CR_SPI_M_EN
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#define SPI_CR_SPI_M_EN_POS (0U)
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#define SPI_CR_SPI_M_EN_LEN (1U)
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#define SPI_CR_SPI_M_EN_MSK (((1U<<SPI_CR_SPI_M_EN_LEN)-1)<<SPI_CR_SPI_M_EN_POS)
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#define SPI_CR_SPI_M_EN_UMSK (~(((1U<<SPI_CR_SPI_M_EN_LEN)-1)<<SPI_CR_SPI_M_EN_POS))
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#define SPI_CR_SPI_S_EN SPI_CR_SPI_S_EN
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#define SPI_CR_SPI_S_EN_POS (1U)
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#define SPI_CR_SPI_S_EN_LEN (1U)
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#define SPI_CR_SPI_S_EN_MSK (((1U<<SPI_CR_SPI_S_EN_LEN)-1)<<SPI_CR_SPI_S_EN_POS)
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#define SPI_CR_SPI_S_EN_UMSK (~(((1U<<SPI_CR_SPI_S_EN_LEN)-1)<<SPI_CR_SPI_S_EN_POS))
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#define SPI_CR_SPI_FRAME_SIZE SPI_CR_SPI_FRAME_SIZE
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#define SPI_CR_SPI_FRAME_SIZE_POS (2U)
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#define SPI_CR_SPI_FRAME_SIZE_LEN (2U)
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#define SPI_CR_SPI_FRAME_SIZE_MSK (((1U<<SPI_CR_SPI_FRAME_SIZE_LEN)-1)<<SPI_CR_SPI_FRAME_SIZE_POS)
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#define SPI_CR_SPI_FRAME_SIZE_UMSK (~(((1U<<SPI_CR_SPI_FRAME_SIZE_LEN)-1)<<SPI_CR_SPI_FRAME_SIZE_POS))
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#define SPI_CR_SPI_SCLK_POL SPI_CR_SPI_SCLK_POL
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#define SPI_CR_SPI_SCLK_POL_POS (4U)
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#define SPI_CR_SPI_SCLK_POL_LEN (1U)
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#define SPI_CR_SPI_SCLK_POL_MSK (((1U<<SPI_CR_SPI_SCLK_POL_LEN)-1)<<SPI_CR_SPI_SCLK_POL_POS)
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#define SPI_CR_SPI_SCLK_POL_UMSK (~(((1U<<SPI_CR_SPI_SCLK_POL_LEN)-1)<<SPI_CR_SPI_SCLK_POL_POS))
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#define SPI_CR_SPI_SCLK_PH SPI_CR_SPI_SCLK_PH
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#define SPI_CR_SPI_SCLK_PH_POS (5U)
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#define SPI_CR_SPI_SCLK_PH_LEN (1U)
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#define SPI_CR_SPI_SCLK_PH_MSK (((1U<<SPI_CR_SPI_SCLK_PH_LEN)-1)<<SPI_CR_SPI_SCLK_PH_POS)
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#define SPI_CR_SPI_SCLK_PH_UMSK (~(((1U<<SPI_CR_SPI_SCLK_PH_LEN)-1)<<SPI_CR_SPI_SCLK_PH_POS))
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#define SPI_CR_SPI_BIT_INV SPI_CR_SPI_BIT_INV
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#define SPI_CR_SPI_BIT_INV_POS (6U)
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#define SPI_CR_SPI_BIT_INV_LEN (1U)
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#define SPI_CR_SPI_BIT_INV_MSK (((1U<<SPI_CR_SPI_BIT_INV_LEN)-1)<<SPI_CR_SPI_BIT_INV_POS)
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#define SPI_CR_SPI_BIT_INV_UMSK (~(((1U<<SPI_CR_SPI_BIT_INV_LEN)-1)<<SPI_CR_SPI_BIT_INV_POS))
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#define SPI_CR_SPI_BYTE_INV SPI_CR_SPI_BYTE_INV
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#define SPI_CR_SPI_BYTE_INV_POS (7U)
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#define SPI_CR_SPI_BYTE_INV_LEN (1U)
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#define SPI_CR_SPI_BYTE_INV_MSK (((1U<<SPI_CR_SPI_BYTE_INV_LEN)-1)<<SPI_CR_SPI_BYTE_INV_POS)
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#define SPI_CR_SPI_BYTE_INV_UMSK (~(((1U<<SPI_CR_SPI_BYTE_INV_LEN)-1)<<SPI_CR_SPI_BYTE_INV_POS))
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#define SPI_CR_SPI_RXD_IGNR_EN SPI_CR_SPI_RXD_IGNR_EN
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#define SPI_CR_SPI_RXD_IGNR_EN_POS (8U)
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#define SPI_CR_SPI_RXD_IGNR_EN_LEN (1U)
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#define SPI_CR_SPI_RXD_IGNR_EN_MSK (((1U<<SPI_CR_SPI_RXD_IGNR_EN_LEN)-1)<<SPI_CR_SPI_RXD_IGNR_EN_POS)
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#define SPI_CR_SPI_RXD_IGNR_EN_UMSK (~(((1U<<SPI_CR_SPI_RXD_IGNR_EN_LEN)-1)<<SPI_CR_SPI_RXD_IGNR_EN_POS))
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#define SPI_CR_SPI_M_CONT_EN SPI_CR_SPI_M_CONT_EN
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#define SPI_CR_SPI_M_CONT_EN_POS (9U)
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#define SPI_CR_SPI_M_CONT_EN_LEN (1U)
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#define SPI_CR_SPI_M_CONT_EN_MSK (((1U<<SPI_CR_SPI_M_CONT_EN_LEN)-1)<<SPI_CR_SPI_M_CONT_EN_POS)
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#define SPI_CR_SPI_M_CONT_EN_UMSK (~(((1U<<SPI_CR_SPI_M_CONT_EN_LEN)-1)<<SPI_CR_SPI_M_CONT_EN_POS))
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#define SPI_CR_SPI_DEG_EN SPI_CR_SPI_DEG_EN
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#define SPI_CR_SPI_DEG_EN_POS (11U)
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#define SPI_CR_SPI_DEG_EN_LEN (1U)
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#define SPI_CR_SPI_DEG_EN_MSK (((1U<<SPI_CR_SPI_DEG_EN_LEN)-1)<<SPI_CR_SPI_DEG_EN_POS)
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#define SPI_CR_SPI_DEG_EN_UMSK (~(((1U<<SPI_CR_SPI_DEG_EN_LEN)-1)<<SPI_CR_SPI_DEG_EN_POS))
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#define SPI_CR_SPI_DEG_CNT SPI_CR_SPI_DEG_CNT
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#define SPI_CR_SPI_DEG_CNT_POS (12U)
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#define SPI_CR_SPI_DEG_CNT_LEN (4U)
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#define SPI_CR_SPI_DEG_CNT_MSK (((1U<<SPI_CR_SPI_DEG_CNT_LEN)-1)<<SPI_CR_SPI_DEG_CNT_POS)
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#define SPI_CR_SPI_DEG_CNT_UMSK (~(((1U<<SPI_CR_SPI_DEG_CNT_LEN)-1)<<SPI_CR_SPI_DEG_CNT_POS))
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/* 0x4 : spi_int_sts */
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#define SPI_INT_STS_OFFSET (0x4)
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#define SPI_END_INT SPI_END_INT
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#define SPI_END_INT_POS (0U)
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#define SPI_END_INT_LEN (1U)
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#define SPI_END_INT_MSK (((1U<<SPI_END_INT_LEN)-1)<<SPI_END_INT_POS)
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#define SPI_END_INT_UMSK (~(((1U<<SPI_END_INT_LEN)-1)<<SPI_END_INT_POS))
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#define SPI_TXF_INT SPI_TXF_INT
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#define SPI_TXF_INT_POS (1U)
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#define SPI_TXF_INT_LEN (1U)
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#define SPI_TXF_INT_MSK (((1U<<SPI_TXF_INT_LEN)-1)<<SPI_TXF_INT_POS)
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#define SPI_TXF_INT_UMSK (~(((1U<<SPI_TXF_INT_LEN)-1)<<SPI_TXF_INT_POS))
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#define SPI_RXF_INT SPI_RXF_INT
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#define SPI_RXF_INT_POS (2U)
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#define SPI_RXF_INT_LEN (1U)
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#define SPI_RXF_INT_MSK (((1U<<SPI_RXF_INT_LEN)-1)<<SPI_RXF_INT_POS)
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#define SPI_RXF_INT_UMSK (~(((1U<<SPI_RXF_INT_LEN)-1)<<SPI_RXF_INT_POS))
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#define SPI_STO_INT SPI_STO_INT
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#define SPI_STO_INT_POS (3U)
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#define SPI_STO_INT_LEN (1U)
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#define SPI_STO_INT_MSK (((1U<<SPI_STO_INT_LEN)-1)<<SPI_STO_INT_POS)
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#define SPI_STO_INT_UMSK (~(((1U<<SPI_STO_INT_LEN)-1)<<SPI_STO_INT_POS))
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#define SPI_TXU_INT SPI_TXU_INT
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#define SPI_TXU_INT_POS (4U)
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#define SPI_TXU_INT_LEN (1U)
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#define SPI_TXU_INT_MSK (((1U<<SPI_TXU_INT_LEN)-1)<<SPI_TXU_INT_POS)
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#define SPI_TXU_INT_UMSK (~(((1U<<SPI_TXU_INT_LEN)-1)<<SPI_TXU_INT_POS))
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#define SPI_FER_INT SPI_FER_INT
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#define SPI_FER_INT_POS (5U)
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#define SPI_FER_INT_LEN (1U)
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#define SPI_FER_INT_MSK (((1U<<SPI_FER_INT_LEN)-1)<<SPI_FER_INT_POS)
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#define SPI_FER_INT_UMSK (~(((1U<<SPI_FER_INT_LEN)-1)<<SPI_FER_INT_POS))
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#define SPI_CR_SPI_END_MASK SPI_CR_SPI_END_MASK
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#define SPI_CR_SPI_END_MASK_POS (8U)
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#define SPI_CR_SPI_END_MASK_LEN (1U)
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#define SPI_CR_SPI_END_MASK_MSK (((1U<<SPI_CR_SPI_END_MASK_LEN)-1)<<SPI_CR_SPI_END_MASK_POS)
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#define SPI_CR_SPI_END_MASK_UMSK (~(((1U<<SPI_CR_SPI_END_MASK_LEN)-1)<<SPI_CR_SPI_END_MASK_POS))
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#define SPI_CR_SPI_TXF_MASK SPI_CR_SPI_TXF_MASK
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#define SPI_CR_SPI_TXF_MASK_POS (9U)
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#define SPI_CR_SPI_TXF_MASK_LEN (1U)
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#define SPI_CR_SPI_TXF_MASK_MSK (((1U<<SPI_CR_SPI_TXF_MASK_LEN)-1)<<SPI_CR_SPI_TXF_MASK_POS)
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#define SPI_CR_SPI_TXF_MASK_UMSK (~(((1U<<SPI_CR_SPI_TXF_MASK_LEN)-1)<<SPI_CR_SPI_TXF_MASK_POS))
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#define SPI_CR_SPI_RXF_MASK SPI_CR_SPI_RXF_MASK
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#define SPI_CR_SPI_RXF_MASK_POS (10U)
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#define SPI_CR_SPI_RXF_MASK_LEN (1U)
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#define SPI_CR_SPI_RXF_MASK_MSK (((1U<<SPI_CR_SPI_RXF_MASK_LEN)-1)<<SPI_CR_SPI_RXF_MASK_POS)
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#define SPI_CR_SPI_RXF_MASK_UMSK (~(((1U<<SPI_CR_SPI_RXF_MASK_LEN)-1)<<SPI_CR_SPI_RXF_MASK_POS))
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#define SPI_CR_SPI_STO_MASK SPI_CR_SPI_STO_MASK
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#define SPI_CR_SPI_STO_MASK_POS (11U)
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#define SPI_CR_SPI_STO_MASK_LEN (1U)
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#define SPI_CR_SPI_STO_MASK_MSK (((1U<<SPI_CR_SPI_STO_MASK_LEN)-1)<<SPI_CR_SPI_STO_MASK_POS)
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#define SPI_CR_SPI_STO_MASK_UMSK (~(((1U<<SPI_CR_SPI_STO_MASK_LEN)-1)<<SPI_CR_SPI_STO_MASK_POS))
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#define SPI_CR_SPI_TXU_MASK SPI_CR_SPI_TXU_MASK
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#define SPI_CR_SPI_TXU_MASK_POS (12U)
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#define SPI_CR_SPI_TXU_MASK_LEN (1U)
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#define SPI_CR_SPI_TXU_MASK_MSK (((1U<<SPI_CR_SPI_TXU_MASK_LEN)-1)<<SPI_CR_SPI_TXU_MASK_POS)
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#define SPI_CR_SPI_TXU_MASK_UMSK (~(((1U<<SPI_CR_SPI_TXU_MASK_LEN)-1)<<SPI_CR_SPI_TXU_MASK_POS))
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#define SPI_CR_SPI_FER_MASK SPI_CR_SPI_FER_MASK
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#define SPI_CR_SPI_FER_MASK_POS (13U)
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#define SPI_CR_SPI_FER_MASK_LEN (1U)
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#define SPI_CR_SPI_FER_MASK_MSK (((1U<<SPI_CR_SPI_FER_MASK_LEN)-1)<<SPI_CR_SPI_FER_MASK_POS)
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#define SPI_CR_SPI_FER_MASK_UMSK (~(((1U<<SPI_CR_SPI_FER_MASK_LEN)-1)<<SPI_CR_SPI_FER_MASK_POS))
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#define SPI_CR_SPI_END_CLR SPI_CR_SPI_END_CLR
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#define SPI_CR_SPI_END_CLR_POS (16U)
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#define SPI_CR_SPI_END_CLR_LEN (1U)
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#define SPI_CR_SPI_END_CLR_MSK (((1U<<SPI_CR_SPI_END_CLR_LEN)-1)<<SPI_CR_SPI_END_CLR_POS)
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#define SPI_CR_SPI_END_CLR_UMSK (~(((1U<<SPI_CR_SPI_END_CLR_LEN)-1)<<SPI_CR_SPI_END_CLR_POS))
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#define SPI_CR_SPI_STO_CLR SPI_CR_SPI_STO_CLR
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#define SPI_CR_SPI_STO_CLR_POS (19U)
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#define SPI_CR_SPI_STO_CLR_LEN (1U)
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#define SPI_CR_SPI_STO_CLR_MSK (((1U<<SPI_CR_SPI_STO_CLR_LEN)-1)<<SPI_CR_SPI_STO_CLR_POS)
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#define SPI_CR_SPI_STO_CLR_UMSK (~(((1U<<SPI_CR_SPI_STO_CLR_LEN)-1)<<SPI_CR_SPI_STO_CLR_POS))
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#define SPI_CR_SPI_TXU_CLR SPI_CR_SPI_TXU_CLR
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#define SPI_CR_SPI_TXU_CLR_POS (20U)
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#define SPI_CR_SPI_TXU_CLR_LEN (1U)
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#define SPI_CR_SPI_TXU_CLR_MSK (((1U<<SPI_CR_SPI_TXU_CLR_LEN)-1)<<SPI_CR_SPI_TXU_CLR_POS)
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#define SPI_CR_SPI_TXU_CLR_UMSK (~(((1U<<SPI_CR_SPI_TXU_CLR_LEN)-1)<<SPI_CR_SPI_TXU_CLR_POS))
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#define SPI_CR_SPI_END_EN SPI_CR_SPI_END_EN
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#define SPI_CR_SPI_END_EN_POS (24U)
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#define SPI_CR_SPI_END_EN_LEN (1U)
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#define SPI_CR_SPI_END_EN_MSK (((1U<<SPI_CR_SPI_END_EN_LEN)-1)<<SPI_CR_SPI_END_EN_POS)
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#define SPI_CR_SPI_END_EN_UMSK (~(((1U<<SPI_CR_SPI_END_EN_LEN)-1)<<SPI_CR_SPI_END_EN_POS))
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#define SPI_CR_SPI_TXF_EN SPI_CR_SPI_TXF_EN
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#define SPI_CR_SPI_TXF_EN_POS (25U)
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#define SPI_CR_SPI_TXF_EN_LEN (1U)
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#define SPI_CR_SPI_TXF_EN_MSK (((1U<<SPI_CR_SPI_TXF_EN_LEN)-1)<<SPI_CR_SPI_TXF_EN_POS)
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#define SPI_CR_SPI_TXF_EN_UMSK (~(((1U<<SPI_CR_SPI_TXF_EN_LEN)-1)<<SPI_CR_SPI_TXF_EN_POS))
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#define SPI_CR_SPI_RXF_EN SPI_CR_SPI_RXF_EN
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#define SPI_CR_SPI_RXF_EN_POS (26U)
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#define SPI_CR_SPI_RXF_EN_LEN (1U)
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#define SPI_CR_SPI_RXF_EN_MSK (((1U<<SPI_CR_SPI_RXF_EN_LEN)-1)<<SPI_CR_SPI_RXF_EN_POS)
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#define SPI_CR_SPI_RXF_EN_UMSK (~(((1U<<SPI_CR_SPI_RXF_EN_LEN)-1)<<SPI_CR_SPI_RXF_EN_POS))
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#define SPI_CR_SPI_STO_EN SPI_CR_SPI_STO_EN
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#define SPI_CR_SPI_STO_EN_POS (27U)
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#define SPI_CR_SPI_STO_EN_LEN (1U)
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#define SPI_CR_SPI_STO_EN_MSK (((1U<<SPI_CR_SPI_STO_EN_LEN)-1)<<SPI_CR_SPI_STO_EN_POS)
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#define SPI_CR_SPI_STO_EN_UMSK (~(((1U<<SPI_CR_SPI_STO_EN_LEN)-1)<<SPI_CR_SPI_STO_EN_POS))
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#define SPI_CR_SPI_TXU_EN SPI_CR_SPI_TXU_EN
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#define SPI_CR_SPI_TXU_EN_POS (28U)
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#define SPI_CR_SPI_TXU_EN_LEN (1U)
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#define SPI_CR_SPI_TXU_EN_MSK (((1U<<SPI_CR_SPI_TXU_EN_LEN)-1)<<SPI_CR_SPI_TXU_EN_POS)
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#define SPI_CR_SPI_TXU_EN_UMSK (~(((1U<<SPI_CR_SPI_TXU_EN_LEN)-1)<<SPI_CR_SPI_TXU_EN_POS))
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#define SPI_CR_SPI_FER_EN SPI_CR_SPI_FER_EN
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#define SPI_CR_SPI_FER_EN_POS (29U)
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#define SPI_CR_SPI_FER_EN_LEN (1U)
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#define SPI_CR_SPI_FER_EN_MSK (((1U<<SPI_CR_SPI_FER_EN_LEN)-1)<<SPI_CR_SPI_FER_EN_POS)
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#define SPI_CR_SPI_FER_EN_UMSK (~(((1U<<SPI_CR_SPI_FER_EN_LEN)-1)<<SPI_CR_SPI_FER_EN_POS))
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/* 0x8 : spi_bus_busy */
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#define SPI_BUS_BUSY_OFFSET (0x8)
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#define SPI_STS_SPI_BUS_BUSY SPI_STS_SPI_BUS_BUSY
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#define SPI_STS_SPI_BUS_BUSY_POS (0U)
|
||
|
|
#define SPI_STS_SPI_BUS_BUSY_LEN (1U)
|
||
|
|
#define SPI_STS_SPI_BUS_BUSY_MSK (((1U<<SPI_STS_SPI_BUS_BUSY_LEN)-1)<<SPI_STS_SPI_BUS_BUSY_POS)
|
||
|
|
#define SPI_STS_SPI_BUS_BUSY_UMSK (~(((1U<<SPI_STS_SPI_BUS_BUSY_LEN)-1)<<SPI_STS_SPI_BUS_BUSY_POS))
|
||
|
|
|
||
|
|
/* 0x10 : spi_prd_0 */
|
||
|
|
#define SPI_PRD_0_OFFSET (0x10)
|
||
|
|
#define SPI_CR_SPI_PRD_S SPI_CR_SPI_PRD_S
|
||
|
|
#define SPI_CR_SPI_PRD_S_POS (0U)
|
||
|
|
#define SPI_CR_SPI_PRD_S_LEN (8U)
|
||
|
|
#define SPI_CR_SPI_PRD_S_MSK (((1U<<SPI_CR_SPI_PRD_S_LEN)-1)<<SPI_CR_SPI_PRD_S_POS)
|
||
|
|
#define SPI_CR_SPI_PRD_S_UMSK (~(((1U<<SPI_CR_SPI_PRD_S_LEN)-1)<<SPI_CR_SPI_PRD_S_POS))
|
||
|
|
#define SPI_CR_SPI_PRD_P SPI_CR_SPI_PRD_P
|
||
|
|
#define SPI_CR_SPI_PRD_P_POS (8U)
|
||
|
|
#define SPI_CR_SPI_PRD_P_LEN (8U)
|
||
|
|
#define SPI_CR_SPI_PRD_P_MSK (((1U<<SPI_CR_SPI_PRD_P_LEN)-1)<<SPI_CR_SPI_PRD_P_POS)
|
||
|
|
#define SPI_CR_SPI_PRD_P_UMSK (~(((1U<<SPI_CR_SPI_PRD_P_LEN)-1)<<SPI_CR_SPI_PRD_P_POS))
|
||
|
|
#define SPI_CR_SPI_PRD_D_PH_0 SPI_CR_SPI_PRD_D_PH_0
|
||
|
|
#define SPI_CR_SPI_PRD_D_PH_0_POS (16U)
|
||
|
|
#define SPI_CR_SPI_PRD_D_PH_0_LEN (8U)
|
||
|
|
#define SPI_CR_SPI_PRD_D_PH_0_MSK (((1U<<SPI_CR_SPI_PRD_D_PH_0_LEN)-1)<<SPI_CR_SPI_PRD_D_PH_0_POS)
|
||
|
|
#define SPI_CR_SPI_PRD_D_PH_0_UMSK (~(((1U<<SPI_CR_SPI_PRD_D_PH_0_LEN)-1)<<SPI_CR_SPI_PRD_D_PH_0_POS))
|
||
|
|
#define SPI_CR_SPI_PRD_D_PH_1 SPI_CR_SPI_PRD_D_PH_1
|
||
|
|
#define SPI_CR_SPI_PRD_D_PH_1_POS (24U)
|
||
|
|
#define SPI_CR_SPI_PRD_D_PH_1_LEN (8U)
|
||
|
|
#define SPI_CR_SPI_PRD_D_PH_1_MSK (((1U<<SPI_CR_SPI_PRD_D_PH_1_LEN)-1)<<SPI_CR_SPI_PRD_D_PH_1_POS)
|
||
|
|
#define SPI_CR_SPI_PRD_D_PH_1_UMSK (~(((1U<<SPI_CR_SPI_PRD_D_PH_1_LEN)-1)<<SPI_CR_SPI_PRD_D_PH_1_POS))
|
||
|
|
|
||
|
|
/* 0x14 : spi_prd_1 */
|
||
|
|
#define SPI_PRD_1_OFFSET (0x14)
|
||
|
|
#define SPI_CR_SPI_PRD_I SPI_CR_SPI_PRD_I
|
||
|
|
#define SPI_CR_SPI_PRD_I_POS (0U)
|
||
|
|
#define SPI_CR_SPI_PRD_I_LEN (8U)
|
||
|
|
#define SPI_CR_SPI_PRD_I_MSK (((1U<<SPI_CR_SPI_PRD_I_LEN)-1)<<SPI_CR_SPI_PRD_I_POS)
|
||
|
|
#define SPI_CR_SPI_PRD_I_UMSK (~(((1U<<SPI_CR_SPI_PRD_I_LEN)-1)<<SPI_CR_SPI_PRD_I_POS))
|
||
|
|
|
||
|
|
/* 0x18 : spi_rxd_ignr */
|
||
|
|
#define SPI_RXD_IGNR_OFFSET (0x18)
|
||
|
|
#define SPI_CR_SPI_RXD_IGNR_P SPI_CR_SPI_RXD_IGNR_P
|
||
|
|
#define SPI_CR_SPI_RXD_IGNR_P_POS (0U)
|
||
|
|
#define SPI_CR_SPI_RXD_IGNR_P_LEN (5U)
|
||
|
|
#define SPI_CR_SPI_RXD_IGNR_P_MSK (((1U<<SPI_CR_SPI_RXD_IGNR_P_LEN)-1)<<SPI_CR_SPI_RXD_IGNR_P_POS)
|
||
|
|
#define SPI_CR_SPI_RXD_IGNR_P_UMSK (~(((1U<<SPI_CR_SPI_RXD_IGNR_P_LEN)-1)<<SPI_CR_SPI_RXD_IGNR_P_POS))
|
||
|
|
#define SPI_CR_SPI_RXD_IGNR_S SPI_CR_SPI_RXD_IGNR_S
|
||
|
|
#define SPI_CR_SPI_RXD_IGNR_S_POS (16U)
|
||
|
|
#define SPI_CR_SPI_RXD_IGNR_S_LEN (5U)
|
||
|
|
#define SPI_CR_SPI_RXD_IGNR_S_MSK (((1U<<SPI_CR_SPI_RXD_IGNR_S_LEN)-1)<<SPI_CR_SPI_RXD_IGNR_S_POS)
|
||
|
|
#define SPI_CR_SPI_RXD_IGNR_S_UMSK (~(((1U<<SPI_CR_SPI_RXD_IGNR_S_LEN)-1)<<SPI_CR_SPI_RXD_IGNR_S_POS))
|
||
|
|
|
||
|
|
/* 0x1C : spi_sto_value */
|
||
|
|
#define SPI_STO_VALUE_OFFSET (0x1C)
|
||
|
|
#define SPI_CR_SPI_STO_VALUE SPI_CR_SPI_STO_VALUE
|
||
|
|
#define SPI_CR_SPI_STO_VALUE_POS (0U)
|
||
|
|
#define SPI_CR_SPI_STO_VALUE_LEN (12U)
|
||
|
|
#define SPI_CR_SPI_STO_VALUE_MSK (((1U<<SPI_CR_SPI_STO_VALUE_LEN)-1)<<SPI_CR_SPI_STO_VALUE_POS)
|
||
|
|
#define SPI_CR_SPI_STO_VALUE_UMSK (~(((1U<<SPI_CR_SPI_STO_VALUE_LEN)-1)<<SPI_CR_SPI_STO_VALUE_POS))
|
||
|
|
|
||
|
|
/* 0x80 : spi_fifo_config_0 */
|
||
|
|
#define SPI_FIFO_CONFIG_0_OFFSET (0x80)
|
||
|
|
#define SPI_DMA_TX_EN SPI_DMA_TX_EN
|
||
|
|
#define SPI_DMA_TX_EN_POS (0U)
|
||
|
|
#define SPI_DMA_TX_EN_LEN (1U)
|
||
|
|
#define SPI_DMA_TX_EN_MSK (((1U<<SPI_DMA_TX_EN_LEN)-1)<<SPI_DMA_TX_EN_POS)
|
||
|
|
#define SPI_DMA_TX_EN_UMSK (~(((1U<<SPI_DMA_TX_EN_LEN)-1)<<SPI_DMA_TX_EN_POS))
|
||
|
|
#define SPI_DMA_RX_EN SPI_DMA_RX_EN
|
||
|
|
#define SPI_DMA_RX_EN_POS (1U)
|
||
|
|
#define SPI_DMA_RX_EN_LEN (1U)
|
||
|
|
#define SPI_DMA_RX_EN_MSK (((1U<<SPI_DMA_RX_EN_LEN)-1)<<SPI_DMA_RX_EN_POS)
|
||
|
|
#define SPI_DMA_RX_EN_UMSK (~(((1U<<SPI_DMA_RX_EN_LEN)-1)<<SPI_DMA_RX_EN_POS))
|
||
|
|
#define SPI_TX_FIFO_CLR SPI_TX_FIFO_CLR
|
||
|
|
#define SPI_TX_FIFO_CLR_POS (2U)
|
||
|
|
#define SPI_TX_FIFO_CLR_LEN (1U)
|
||
|
|
#define SPI_TX_FIFO_CLR_MSK (((1U<<SPI_TX_FIFO_CLR_LEN)-1)<<SPI_TX_FIFO_CLR_POS)
|
||
|
|
#define SPI_TX_FIFO_CLR_UMSK (~(((1U<<SPI_TX_FIFO_CLR_LEN)-1)<<SPI_TX_FIFO_CLR_POS))
|
||
|
|
#define SPI_RX_FIFO_CLR SPI_RX_FIFO_CLR
|
||
|
|
#define SPI_RX_FIFO_CLR_POS (3U)
|
||
|
|
#define SPI_RX_FIFO_CLR_LEN (1U)
|
||
|
|
#define SPI_RX_FIFO_CLR_MSK (((1U<<SPI_RX_FIFO_CLR_LEN)-1)<<SPI_RX_FIFO_CLR_POS)
|
||
|
|
#define SPI_RX_FIFO_CLR_UMSK (~(((1U<<SPI_RX_FIFO_CLR_LEN)-1)<<SPI_RX_FIFO_CLR_POS))
|
||
|
|
#define SPI_TX_FIFO_OVERFLOW SPI_TX_FIFO_OVERFLOW
|
||
|
|
#define SPI_TX_FIFO_OVERFLOW_POS (4U)
|
||
|
|
#define SPI_TX_FIFO_OVERFLOW_LEN (1U)
|
||
|
|
#define SPI_TX_FIFO_OVERFLOW_MSK (((1U<<SPI_TX_FIFO_OVERFLOW_LEN)-1)<<SPI_TX_FIFO_OVERFLOW_POS)
|
||
|
|
#define SPI_TX_FIFO_OVERFLOW_UMSK (~(((1U<<SPI_TX_FIFO_OVERFLOW_LEN)-1)<<SPI_TX_FIFO_OVERFLOW_POS))
|
||
|
|
#define SPI_TX_FIFO_UNDERFLOW SPI_TX_FIFO_UNDERFLOW
|
||
|
|
#define SPI_TX_FIFO_UNDERFLOW_POS (5U)
|
||
|
|
#define SPI_TX_FIFO_UNDERFLOW_LEN (1U)
|
||
|
|
#define SPI_TX_FIFO_UNDERFLOW_MSK (((1U<<SPI_TX_FIFO_UNDERFLOW_LEN)-1)<<SPI_TX_FIFO_UNDERFLOW_POS)
|
||
|
|
#define SPI_TX_FIFO_UNDERFLOW_UMSK (~(((1U<<SPI_TX_FIFO_UNDERFLOW_LEN)-1)<<SPI_TX_FIFO_UNDERFLOW_POS))
|
||
|
|
#define SPI_RX_FIFO_OVERFLOW SPI_RX_FIFO_OVERFLOW
|
||
|
|
#define SPI_RX_FIFO_OVERFLOW_POS (6U)
|
||
|
|
#define SPI_RX_FIFO_OVERFLOW_LEN (1U)
|
||
|
|
#define SPI_RX_FIFO_OVERFLOW_MSK (((1U<<SPI_RX_FIFO_OVERFLOW_LEN)-1)<<SPI_RX_FIFO_OVERFLOW_POS)
|
||
|
|
#define SPI_RX_FIFO_OVERFLOW_UMSK (~(((1U<<SPI_RX_FIFO_OVERFLOW_LEN)-1)<<SPI_RX_FIFO_OVERFLOW_POS))
|
||
|
|
#define SPI_RX_FIFO_UNDERFLOW SPI_RX_FIFO_UNDERFLOW
|
||
|
|
#define SPI_RX_FIFO_UNDERFLOW_POS (7U)
|
||
|
|
#define SPI_RX_FIFO_UNDERFLOW_LEN (1U)
|
||
|
|
#define SPI_RX_FIFO_UNDERFLOW_MSK (((1U<<SPI_RX_FIFO_UNDERFLOW_LEN)-1)<<SPI_RX_FIFO_UNDERFLOW_POS)
|
||
|
|
#define SPI_RX_FIFO_UNDERFLOW_UMSK (~(((1U<<SPI_RX_FIFO_UNDERFLOW_LEN)-1)<<SPI_RX_FIFO_UNDERFLOW_POS))
|
||
|
|
|
||
|
|
/* 0x84 : spi_fifo_config_1 */
|
||
|
|
#define SPI_FIFO_CONFIG_1_OFFSET (0x84)
|
||
|
|
#define SPI_TX_FIFO_CNT SPI_TX_FIFO_CNT
|
||
|
|
#define SPI_TX_FIFO_CNT_POS (0U)
|
||
|
|
#define SPI_TX_FIFO_CNT_LEN (3U)
|
||
|
|
#define SPI_TX_FIFO_CNT_MSK (((1U<<SPI_TX_FIFO_CNT_LEN)-1)<<SPI_TX_FIFO_CNT_POS)
|
||
|
|
#define SPI_TX_FIFO_CNT_UMSK (~(((1U<<SPI_TX_FIFO_CNT_LEN)-1)<<SPI_TX_FIFO_CNT_POS))
|
||
|
|
#define SPI_RX_FIFO_CNT SPI_RX_FIFO_CNT
|
||
|
|
#define SPI_RX_FIFO_CNT_POS (8U)
|
||
|
|
#define SPI_RX_FIFO_CNT_LEN (3U)
|
||
|
|
#define SPI_RX_FIFO_CNT_MSK (((1U<<SPI_RX_FIFO_CNT_LEN)-1)<<SPI_RX_FIFO_CNT_POS)
|
||
|
|
#define SPI_RX_FIFO_CNT_UMSK (~(((1U<<SPI_RX_FIFO_CNT_LEN)-1)<<SPI_RX_FIFO_CNT_POS))
|
||
|
|
#define SPI_TX_FIFO_TH SPI_TX_FIFO_TH
|
||
|
|
#define SPI_TX_FIFO_TH_POS (16U)
|
||
|
|
#define SPI_TX_FIFO_TH_LEN (2U)
|
||
|
|
#define SPI_TX_FIFO_TH_MSK (((1U<<SPI_TX_FIFO_TH_LEN)-1)<<SPI_TX_FIFO_TH_POS)
|
||
|
|
#define SPI_TX_FIFO_TH_UMSK (~(((1U<<SPI_TX_FIFO_TH_LEN)-1)<<SPI_TX_FIFO_TH_POS))
|
||
|
|
#define SPI_RX_FIFO_TH SPI_RX_FIFO_TH
|
||
|
|
#define SPI_RX_FIFO_TH_POS (24U)
|
||
|
|
#define SPI_RX_FIFO_TH_LEN (2U)
|
||
|
|
#define SPI_RX_FIFO_TH_MSK (((1U<<SPI_RX_FIFO_TH_LEN)-1)<<SPI_RX_FIFO_TH_POS)
|
||
|
|
#define SPI_RX_FIFO_TH_UMSK (~(((1U<<SPI_RX_FIFO_TH_LEN)-1)<<SPI_RX_FIFO_TH_POS))
|
||
|
|
|
||
|
|
/* 0x88 : spi_fifo_wdata */
|
||
|
|
#define SPI_FIFO_WDATA_OFFSET (0x88)
|
||
|
|
#define SPI_FIFO_WDATA SPI_FIFO_WDATA
|
||
|
|
#define SPI_FIFO_WDATA_POS (0U)
|
||
|
|
#define SPI_FIFO_WDATA_LEN (32U)
|
||
|
|
#define SPI_FIFO_WDATA_MSK (((1U<<SPI_FIFO_WDATA_LEN)-1)<<SPI_FIFO_WDATA_POS)
|
||
|
|
#define SPI_FIFO_WDATA_UMSK (~(((1U<<SPI_FIFO_WDATA_LEN)-1)<<SPI_FIFO_WDATA_POS))
|
||
|
|
|
||
|
|
/* 0x8C : spi_fifo_rdata */
|
||
|
|
#define SPI_FIFO_RDATA_OFFSET (0x8C)
|
||
|
|
#define SPI_FIFO_RDATA SPI_FIFO_RDATA
|
||
|
|
#define SPI_FIFO_RDATA_POS (0U)
|
||
|
|
#define SPI_FIFO_RDATA_LEN (32U)
|
||
|
|
#define SPI_FIFO_RDATA_MSK (((1U<<SPI_FIFO_RDATA_LEN)-1)<<SPI_FIFO_RDATA_POS)
|
||
|
|
#define SPI_FIFO_RDATA_UMSK (~(((1U<<SPI_FIFO_RDATA_LEN)-1)<<SPI_FIFO_RDATA_POS))
|
||
|
|
|
||
|
|
|
||
|
|
struct spi_reg {
|
||
|
|
/* 0x0 : spi_config */
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
uint32_t cr_spi_m_en : 1; /* [ 0], r/w, 0x0 */
|
||
|
|
uint32_t cr_spi_s_en : 1; /* [ 1], r/w, 0x0 */
|
||
|
|
uint32_t cr_spi_frame_size : 2; /* [ 3: 2], r/w, 0x0 */
|
||
|
|
uint32_t cr_spi_sclk_pol : 1; /* [ 4], r/w, 0x0 */
|
||
|
|
uint32_t cr_spi_sclk_ph : 1; /* [ 5], r/w, 0x0 */
|
||
|
|
uint32_t cr_spi_bit_inv : 1; /* [ 6], r/w, 0x0 */
|
||
|
|
uint32_t cr_spi_byte_inv : 1; /* [ 7], r/w, 0x0 */
|
||
|
|
uint32_t cr_spi_rxd_ignr_en : 1; /* [ 8], r/w, 0x0 */
|
||
|
|
uint32_t cr_spi_m_cont_en : 1; /* [ 9], r/w, 0x0 */
|
||
|
|
uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */
|
||
|
|
uint32_t cr_spi_deg_en : 1; /* [ 11], r/w, 0x0 */
|
||
|
|
uint32_t cr_spi_deg_cnt : 4; /* [15:12], r/w, 0x0 */
|
||
|
|
uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */
|
||
|
|
}BF;
|
||
|
|
uint32_t WORD;
|
||
|
|
} spi_config;
|
||
|
|
|
||
|
|
/* 0x4 : spi_int_sts */
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
uint32_t spi_end_int : 1; /* [ 0], r, 0x0 */
|
||
|
|
uint32_t spi_txf_int : 1; /* [ 1], r, 0x0 */
|
||
|
|
uint32_t spi_rxf_int : 1; /* [ 2], r, 0x0 */
|
||
|
|
uint32_t spi_sto_int : 1; /* [ 3], r, 0x0 */
|
||
|
|
uint32_t spi_txu_int : 1; /* [ 4], r, 0x0 */
|
||
|
|
uint32_t spi_fer_int : 1; /* [ 5], r, 0x0 */
|
||
|
|
uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */
|
||
|
|
uint32_t cr_spi_end_mask : 1; /* [ 8], r/w, 0x1 */
|
||
|
|
uint32_t cr_spi_txf_mask : 1; /* [ 9], r/w, 0x1 */
|
||
|
|
uint32_t cr_spi_rxf_mask : 1; /* [ 10], r/w, 0x1 */
|
||
|
|
uint32_t cr_spi_sto_mask : 1; /* [ 11], r/w, 0x1 */
|
||
|
|
uint32_t cr_spi_txu_mask : 1; /* [ 12], r/w, 0x1 */
|
||
|
|
uint32_t cr_spi_fer_mask : 1; /* [ 13], r/w, 0x1 */
|
||
|
|
uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */
|
||
|
|
uint32_t cr_spi_end_clr : 1; /* [ 16], w1c, 0x0 */
|
||
|
|
uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */
|
||
|
|
uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */
|
||
|
|
uint32_t cr_spi_sto_clr : 1; /* [ 19], w1c, 0x0 */
|
||
|
|
uint32_t cr_spi_txu_clr : 1; /* [ 20], w1c, 0x0 */
|
||
|
|
uint32_t rsvd_21 : 1; /* [ 21], rsvd, 0x0 */
|
||
|
|
uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */
|
||
|
|
uint32_t cr_spi_end_en : 1; /* [ 24], r/w, 0x1 */
|
||
|
|
uint32_t cr_spi_txf_en : 1; /* [ 25], r/w, 0x1 */
|
||
|
|
uint32_t cr_spi_rxf_en : 1; /* [ 26], r/w, 0x1 */
|
||
|
|
uint32_t cr_spi_sto_en : 1; /* [ 27], r/w, 0x1 */
|
||
|
|
uint32_t cr_spi_txu_en : 1; /* [ 28], r/w, 0x1 */
|
||
|
|
uint32_t cr_spi_fer_en : 1; /* [ 29], r/w, 0x1 */
|
||
|
|
uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */
|
||
|
|
}BF;
|
||
|
|
uint32_t WORD;
|
||
|
|
} spi_int_sts;
|
||
|
|
|
||
|
|
/* 0x8 : spi_bus_busy */
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
uint32_t sts_spi_bus_busy : 1; /* [ 0], r, 0x0 */
|
||
|
|
uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */
|
||
|
|
}BF;
|
||
|
|
uint32_t WORD;
|
||
|
|
} spi_bus_busy;
|
||
|
|
|
||
|
|
/* 0xc reserved */
|
||
|
|
uint8_t RESERVED0xc[4];
|
||
|
|
|
||
|
|
/* 0x10 : spi_prd_0 */
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
uint32_t cr_spi_prd_s : 8; /* [ 7: 0], r/w, 0xf */
|
||
|
|
uint32_t cr_spi_prd_p : 8; /* [15: 8], r/w, 0xf */
|
||
|
|
uint32_t cr_spi_prd_d_ph_0 : 8; /* [23:16], r/w, 0xf */
|
||
|
|
uint32_t cr_spi_prd_d_ph_1 : 8; /* [31:24], r/w, 0xf */
|
||
|
|
}BF;
|
||
|
|
uint32_t WORD;
|
||
|
|
} spi_prd_0;
|
||
|
|
|
||
|
|
/* 0x14 : spi_prd_1 */
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
uint32_t cr_spi_prd_i : 8; /* [ 7: 0], r/w, 0xf */
|
||
|
|
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
|
||
|
|
}BF;
|
||
|
|
uint32_t WORD;
|
||
|
|
} spi_prd_1;
|
||
|
|
|
||
|
|
/* 0x18 : spi_rxd_ignr */
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
uint32_t cr_spi_rxd_ignr_p : 5; /* [ 4: 0], r/w, 0x0 */
|
||
|
|
uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */
|
||
|
|
uint32_t cr_spi_rxd_ignr_s : 5; /* [20:16], r/w, 0x0 */
|
||
|
|
uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */
|
||
|
|
}BF;
|
||
|
|
uint32_t WORD;
|
||
|
|
} spi_rxd_ignr;
|
||
|
|
|
||
|
|
/* 0x1C : spi_sto_value */
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
uint32_t cr_spi_sto_value : 12; /* [11: 0], r/w, 0xfff */
|
||
|
|
uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */
|
||
|
|
}BF;
|
||
|
|
uint32_t WORD;
|
||
|
|
} spi_sto_value;
|
||
|
|
|
||
|
|
/* 0x20 reserved */
|
||
|
|
uint8_t RESERVED0x20[96];
|
||
|
|
|
||
|
|
/* 0x80 : spi_fifo_config_0 */
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
uint32_t spi_dma_tx_en : 1; /* [ 0], r/w, 0x0 */
|
||
|
|
uint32_t spi_dma_rx_en : 1; /* [ 1], r/w, 0x0 */
|
||
|
|
uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */
|
||
|
|
uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */
|
||
|
|
uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */
|
||
|
|
uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */
|
||
|
|
uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */
|
||
|
|
uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */
|
||
|
|
uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */
|
||
|
|
}BF;
|
||
|
|
uint32_t WORD;
|
||
|
|
} spi_fifo_config_0;
|
||
|
|
|
||
|
|
/* 0x84 : spi_fifo_config_1 */
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
uint32_t tx_fifo_cnt : 3; /* [ 2: 0], r, 0x4 */
|
||
|
|
uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */
|
||
|
|
uint32_t rx_fifo_cnt : 3; /* [10: 8], r, 0x0 */
|
||
|
|
uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */
|
||
|
|
uint32_t tx_fifo_th : 2; /* [17:16], r/w, 0x0 */
|
||
|
|
uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */
|
||
|
|
uint32_t rx_fifo_th : 2; /* [25:24], r/w, 0x0 */
|
||
|
|
uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */
|
||
|
|
}BF;
|
||
|
|
uint32_t WORD;
|
||
|
|
} spi_fifo_config_1;
|
||
|
|
|
||
|
|
/* 0x88 : spi_fifo_wdata */
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
uint32_t spi_fifo_wdata : 32; /* [31: 0], w, x */
|
||
|
|
}BF;
|
||
|
|
uint32_t WORD;
|
||
|
|
} spi_fifo_wdata;
|
||
|
|
|
||
|
|
/* 0x8C : spi_fifo_rdata */
|
||
|
|
union {
|
||
|
|
struct {
|
||
|
|
uint32_t spi_fifo_rdata : 32; /* [31: 0], r, 0x0 */
|
||
|
|
}BF;
|
||
|
|
uint32_t WORD;
|
||
|
|
} spi_fifo_rdata;
|
||
|
|
|
||
|
|
};
|
||
|
|
|
||
|
|
typedef volatile struct spi_reg spi_reg_t;
|
||
|
|
|
||
|
|
|
||
|
|
#endif /* __SPI_REG_H__ */
|