diff --git a/FreeRTOS/Source/event_groups.c b/FreeRTOS/Source/event_groups.c deleted file mode 100755 index 65a5ff2..0000000 --- a/FreeRTOS/Source/event_groups.c +++ /dev/null @@ -1,753 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* Standard includes. */ -#include - -/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining -all the API functions to use the MPU wrappers. That should only be done when -task.h is included from an application file. */ -#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE - -/* FreeRTOS includes. */ -#include "FreeRTOS.h" -#include "task.h" -#include "timers.h" -#include "event_groups.h" - -/* Lint e961, e750 and e9021 are suppressed as a MISRA exception justified -because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined -for the header files above, but not in this file, in order to generate the -correct privileged Vs unprivileged linkage and placement. */ -#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021 See comment above. */ - -/* The following bit fields convey control information in a task's event list -item value. It is important they don't clash with the -taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */ -#if configUSE_16_BIT_TICKS == 1 - #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x0100U - #define eventUNBLOCKED_DUE_TO_BIT_SET 0x0200U - #define eventWAIT_FOR_ALL_BITS 0x0400U - #define eventEVENT_BITS_CONTROL_BYTES 0xff00U -#else - #define eventCLEAR_EVENTS_ON_EXIT_BIT 0x01000000UL - #define eventUNBLOCKED_DUE_TO_BIT_SET 0x02000000UL - #define eventWAIT_FOR_ALL_BITS 0x04000000UL - #define eventEVENT_BITS_CONTROL_BYTES 0xff000000UL -#endif - -typedef struct EventGroupDef_t -{ - EventBits_t uxEventBits; - List_t xTasksWaitingForBits; /*< List of tasks waiting for a bit to be set. */ - - #if( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxEventGroupNumber; - #endif - - #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) - uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */ - #endif -} EventGroup_t; - -/*-----------------------------------------------------------*/ - -/* - * Test the bits set in uxCurrentEventBits to see if the wait condition is met. - * The wait condition is defined by xWaitForAllBits. If xWaitForAllBits is - * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor - * are also set in uxCurrentEventBits. If xWaitForAllBits is pdFALSE then the - * wait condition is met if any of the bits set in uxBitsToWait for are also set - * in uxCurrentEventBits. - */ -static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION; - -/*-----------------------------------------------------------*/ - -#if( configSUPPORT_STATIC_ALLOCATION == 1 ) - - EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) - { - EventGroup_t *pxEventBits; - - /* A StaticEventGroup_t object must be provided. */ - configASSERT( pxEventGroupBuffer ); - - #if( configASSERT_DEFINED == 1 ) - { - /* Sanity check that the size of the structure used to declare a - variable of type StaticEventGroup_t equals the size of the real - event group structure. */ - volatile size_t xSize = sizeof( StaticEventGroup_t ); - configASSERT( xSize == sizeof( EventGroup_t ) ); - } /*lint !e529 xSize is referenced if configASSERT() is defined. */ - #endif /* configASSERT_DEFINED */ - - /* The user has provided a statically allocated event group - use it. */ - pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 !e9087 EventGroup_t and StaticEventGroup_t are deliberately aliased for data hiding purposes and guaranteed to have the same size and alignment requirement - checked by configASSERT(). */ - - if( pxEventBits != NULL ) - { - pxEventBits->uxEventBits = 0; - vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); - - #if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - { - /* Both static and dynamic allocation can be used, so note that - this event group was created statically in case the event group - is later deleted. */ - pxEventBits->ucStaticallyAllocated = pdTRUE; - } - #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ - - traceEVENT_GROUP_CREATE( pxEventBits ); - } - else - { - /* xEventGroupCreateStatic should only ever be called with - pxEventGroupBuffer pointing to a pre-allocated (compile time - allocated) StaticEventGroup_t variable. */ - traceEVENT_GROUP_CREATE_FAILED(); - } - - return pxEventBits; - } - -#endif /* configSUPPORT_STATIC_ALLOCATION */ -/*-----------------------------------------------------------*/ - -#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - - EventGroupHandle_t xEventGroupCreate( void ) - { - EventGroup_t *pxEventBits; - - /* Allocate the event group. Justification for MISRA deviation as - follows: pvPortMalloc() always ensures returned memory blocks are - aligned per the requirements of the MCU stack. In this case - pvPortMalloc() must return a pointer that is guaranteed to meet the - alignment requirements of the EventGroup_t structure - which (if you - follow it through) is the alignment requirements of the TickType_t type - (EventBits_t being of TickType_t itself). Therefore, whenever the - stack alignment requirements are greater than or equal to the - TickType_t alignment requirements the cast is safe. In other cases, - where the natural word size of the architecture is less than - sizeof( TickType_t ), the TickType_t variables will be accessed in two - or more reads operations, and the alignment requirements is only that - of each individual read. */ - pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) ); /*lint !e9087 !e9079 see comment above. */ - - if( pxEventBits != NULL ) - { - pxEventBits->uxEventBits = 0; - vListInitialise( &( pxEventBits->xTasksWaitingForBits ) ); - - #if( configSUPPORT_STATIC_ALLOCATION == 1 ) - { - /* Both static and dynamic allocation can be used, so note this - event group was allocated statically in case the event group is - later deleted. */ - pxEventBits->ucStaticallyAllocated = pdFALSE; - } - #endif /* configSUPPORT_STATIC_ALLOCATION */ - - traceEVENT_GROUP_CREATE( pxEventBits ); - } - else - { - traceEVENT_GROUP_CREATE_FAILED(); /*lint !e9063 Else branch only exists to allow tracing and does not generate code if trace macros are not defined. */ - } - - return pxEventBits; - } - -#endif /* configSUPPORT_DYNAMIC_ALLOCATION */ -/*-----------------------------------------------------------*/ - -EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) -{ -EventBits_t uxOriginalBitValue, uxReturn; -EventGroup_t *pxEventBits = xEventGroup; -BaseType_t xAlreadyYielded; -BaseType_t xTimeoutOccurred = pdFALSE; - - configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); - configASSERT( uxBitsToWaitFor != 0 ); - #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) - { - configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); - } - #endif - - vTaskSuspendAll(); - { - uxOriginalBitValue = pxEventBits->uxEventBits; - - ( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet ); - - if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor ) - { - /* All the rendezvous bits are now set - no need to block. */ - uxReturn = ( uxOriginalBitValue | uxBitsToSet ); - - /* Rendezvous always clear the bits. They will have been cleared - already unless this is the only task in the rendezvous. */ - pxEventBits->uxEventBits &= ~uxBitsToWaitFor; - - xTicksToWait = 0; - } - else - { - if( xTicksToWait != ( TickType_t ) 0 ) - { - traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ); - - /* Store the bits that the calling task is waiting for in the - task's event list item so the kernel knows when a match is - found. Then enter the blocked state. */ - vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait ); - - /* This assignment is obsolete as uxReturn will get set after - the task unblocks, but some compilers mistakenly generate a - warning about uxReturn being returned without being set if the - assignment is omitted. */ - uxReturn = 0; - } - else - { - /* The rendezvous bits were not set, but no block time was - specified - just return the current event bit value. */ - uxReturn = pxEventBits->uxEventBits; - xTimeoutOccurred = pdTRUE; - } - } - } - xAlreadyYielded = xTaskResumeAll(); - - if( xTicksToWait != ( TickType_t ) 0 ) - { - if( xAlreadyYielded == pdFALSE ) - { - portYIELD_WITHIN_API(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - - /* The task blocked to wait for its required bits to be set - at this - point either the required bits were set or the block time expired. If - the required bits were set they will have been stored in the task's - event list item, and they should now be retrieved then cleared. */ - uxReturn = uxTaskResetEventItemValue(); - - if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) - { - /* The task timed out, just return the current event bit value. */ - taskENTER_CRITICAL(); - { - uxReturn = pxEventBits->uxEventBits; - - /* Although the task got here because it timed out before the - bits it was waiting for were set, it is possible that since it - unblocked another task has set the bits. If this is the case - then it needs to clear the bits before exiting. */ - if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor ) - { - pxEventBits->uxEventBits &= ~uxBitsToWaitFor; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - taskEXIT_CRITICAL(); - - xTimeoutOccurred = pdTRUE; - } - else - { - /* The task unblocked because the bits were set. */ - } - - /* Control bits might be set as the task had blocked should not be - returned. */ - uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; - } - - traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ); - - /* Prevent compiler warnings when trace macros are not used. */ - ( void ) xTimeoutOccurred; - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) -{ -EventGroup_t *pxEventBits = xEventGroup; -EventBits_t uxReturn, uxControlBits = 0; -BaseType_t xWaitConditionMet, xAlreadyYielded; -BaseType_t xTimeoutOccurred = pdFALSE; - - /* Check the user is not attempting to wait on the bits used by the kernel - itself, and that at least one bit is being requested. */ - configASSERT( xEventGroup ); - configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); - configASSERT( uxBitsToWaitFor != 0 ); - #if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) - { - configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) ); - } - #endif - - vTaskSuspendAll(); - { - const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits; - - /* Check to see if the wait condition is already met or not. */ - xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits ); - - if( xWaitConditionMet != pdFALSE ) - { - /* The wait condition has already been met so there is no need to - block. */ - uxReturn = uxCurrentEventBits; - xTicksToWait = ( TickType_t ) 0; - - /* Clear the wait bits if requested to do so. */ - if( xClearOnExit != pdFALSE ) - { - pxEventBits->uxEventBits &= ~uxBitsToWaitFor; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - else if( xTicksToWait == ( TickType_t ) 0 ) - { - /* The wait condition has not been met, but no block time was - specified, so just return the current value. */ - uxReturn = uxCurrentEventBits; - xTimeoutOccurred = pdTRUE; - } - else - { - /* The task is going to block to wait for its required bits to be - set. uxControlBits are used to remember the specified behaviour of - this call to xEventGroupWaitBits() - for use when the event bits - unblock the task. */ - if( xClearOnExit != pdFALSE ) - { - uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - - if( xWaitForAllBits != pdFALSE ) - { - uxControlBits |= eventWAIT_FOR_ALL_BITS; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - - /* Store the bits that the calling task is waiting for in the - task's event list item so the kernel knows when a match is - found. Then enter the blocked state. */ - vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait ); - - /* This is obsolete as it will get set after the task unblocks, but - some compilers mistakenly generate a warning about the variable - being returned without being set if it is not done. */ - uxReturn = 0; - - traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ); - } - } - xAlreadyYielded = xTaskResumeAll(); - - if( xTicksToWait != ( TickType_t ) 0 ) - { - if( xAlreadyYielded == pdFALSE ) - { - portYIELD_WITHIN_API(); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - - /* The task blocked to wait for its required bits to be set - at this - point either the required bits were set or the block time expired. If - the required bits were set they will have been stored in the task's - event list item, and they should now be retrieved then cleared. */ - uxReturn = uxTaskResetEventItemValue(); - - if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 ) - { - taskENTER_CRITICAL(); - { - /* The task timed out, just return the current event bit value. */ - uxReturn = pxEventBits->uxEventBits; - - /* It is possible that the event bits were updated between this - task leaving the Blocked state and running again. */ - if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE ) - { - if( xClearOnExit != pdFALSE ) - { - pxEventBits->uxEventBits &= ~uxBitsToWaitFor; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - xTimeoutOccurred = pdTRUE; - } - taskEXIT_CRITICAL(); - } - else - { - /* The task unblocked because the bits were set. */ - } - - /* The task blocked so control bits may have been set. */ - uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES; - } - traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ); - - /* Prevent compiler warnings when trace macros are not used. */ - ( void ) xTimeoutOccurred; - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) -{ -EventGroup_t *pxEventBits = xEventGroup; -EventBits_t uxReturn; - - /* Check the user is not attempting to clear the bits used by the kernel - itself. */ - configASSERT( xEventGroup ); - configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); - - taskENTER_CRITICAL(); - { - traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ); - - /* The value returned is the event group value prior to the bits being - cleared. */ - uxReturn = pxEventBits->uxEventBits; - - /* Clear the bits. */ - pxEventBits->uxEventBits &= ~uxBitsToClear; - } - taskEXIT_CRITICAL(); - - return uxReturn; -} -/*-----------------------------------------------------------*/ - -#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) - - BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) - { - BaseType_t xReturn; - - traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ); - xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ - - return xReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) -{ -UBaseType_t uxSavedInterruptStatus; -EventGroup_t const * const pxEventBits = xEventGroup; -EventBits_t uxReturn; - - uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR(); - { - uxReturn = pxEventBits->uxEventBits; - } - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ); - - return uxReturn; -} /*lint !e818 EventGroupHandle_t is a typedef used in other functions to so can't be pointer to const. */ -/*-----------------------------------------------------------*/ - -EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) -{ -ListItem_t *pxListItem, *pxNext; -ListItem_t const *pxListEnd; -List_t const * pxList; -EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits; -EventGroup_t *pxEventBits = xEventGroup; -BaseType_t xMatchFound = pdFALSE; - - /* Check the user is not attempting to set the bits used by the kernel - itself. */ - configASSERT( xEventGroup ); - configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 ); - - pxList = &( pxEventBits->xTasksWaitingForBits ); - pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM. This is checked and valid. */ - vTaskSuspendAll(); - { - traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ); - - pxListItem = listGET_HEAD_ENTRY( pxList ); - - /* Set the bits. */ - pxEventBits->uxEventBits |= uxBitsToSet; - - /* See if the new bit value should unblock any tasks. */ - while( pxListItem != pxListEnd ) - { - pxNext = listGET_NEXT( pxListItem ); - uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem ); - xMatchFound = pdFALSE; - - /* Split the bits waited for from the control bits. */ - uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES; - uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES; - - if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 ) - { - /* Just looking for single bit being set. */ - if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 ) - { - xMatchFound = pdTRUE; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor ) - { - /* All bits are set. */ - xMatchFound = pdTRUE; - } - else - { - /* Need all bits to be set, but not all the bits were set. */ - } - - if( xMatchFound != pdFALSE ) - { - /* The bits match. Should the bits be cleared on exit? */ - if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 ) - { - uxBitsToClear |= uxBitsWaitedFor; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - - /* Store the actual event flag value in the task's event list - item before removing the task from the event list. The - eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows - that is was unblocked due to its required bits matching, rather - than because it timed out. */ - vTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET ); - } - - /* Move onto the next list item. Note pxListItem->pxNext is not - used here as the list item may have been removed from the event list - and inserted into the ready/pending reading list. */ - pxListItem = pxNext; - } - - /* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT - bit was set in the control word. */ - pxEventBits->uxEventBits &= ~uxBitsToClear; - } - ( void ) xTaskResumeAll(); - - return pxEventBits->uxEventBits; -} -/*-----------------------------------------------------------*/ - -void vEventGroupDelete( EventGroupHandle_t xEventGroup ) -{ -EventGroup_t *pxEventBits = xEventGroup; -const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits ); - - vTaskSuspendAll(); - { - traceEVENT_GROUP_DELETE( xEventGroup ); - - while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 ) - { - /* Unblock the task, returning 0 as the event list is being deleted - and cannot therefore have any bits set. */ - configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( const ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) ); - vTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET ); - } - - #if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) ) - { - /* The event group can only have been allocated dynamically - free - it again. */ - vPortFree( pxEventBits ); - } - #elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) - { - /* The event group could have been allocated statically or - dynamically, so check before attempting to free the memory. */ - if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE ) - { - vPortFree( pxEventBits ); - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - #endif /* configSUPPORT_DYNAMIC_ALLOCATION */ - } - ( void ) xTaskResumeAll(); -} -/*-----------------------------------------------------------*/ - -/* For internal use only - execute a 'set bits' command that was pended from -an interrupt. */ -void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) -{ - ( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ -} -/*-----------------------------------------------------------*/ - -/* For internal use only - execute a 'clear bits' command that was pended from -an interrupt. */ -void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) -{ - ( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear ); /*lint !e9079 Can't avoid cast to void* as a generic timer callback prototype. Callback casts back to original type so safe. */ -} -/*-----------------------------------------------------------*/ - -static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) -{ -BaseType_t xWaitConditionMet = pdFALSE; - - if( xWaitForAllBits == pdFALSE ) - { - /* Task only has to wait for one bit within uxBitsToWaitFor to be - set. Is one already set? */ - if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 ) - { - xWaitConditionMet = pdTRUE; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - else - { - /* Task has to wait for all the bits in uxBitsToWaitFor to be set. - Are they set already? */ - if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor ) - { - xWaitConditionMet = pdTRUE; - } - else - { - mtCOVERAGE_TEST_MARKER(); - } - } - - return xWaitConditionMet; -} -/*-----------------------------------------------------------*/ - -#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) ) - - BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) - { - BaseType_t xReturn; - - traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ); - xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ); /*lint !e9087 Can't avoid cast to void* as a generic callback function not specific to this use case. Callback casts back to original type so safe. */ - - return xReturn; - } - -#endif -/*-----------------------------------------------------------*/ - -#if (configUSE_TRACE_FACILITY == 1) - - UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) - { - UBaseType_t xReturn; - EventGroup_t const *pxEventBits = ( EventGroup_t * ) xEventGroup; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ - - if( xEventGroup == NULL ) - { - xReturn = 0; - } - else - { - xReturn = pxEventBits->uxEventGroupNumber; - } - - return xReturn; - } - -#endif /* configUSE_TRACE_FACILITY */ -/*-----------------------------------------------------------*/ - -#if ( configUSE_TRACE_FACILITY == 1 ) - - void vEventGroupSetNumber( void * xEventGroup, UBaseType_t uxEventGroupNumber ) - { - ( ( EventGroup_t * ) xEventGroup )->uxEventGroupNumber = uxEventGroupNumber; /*lint !e9087 !e9079 EventGroupHandle_t is a pointer to an EventGroup_t, but EventGroupHandle_t is kept opaque outside of this file for data hiding purposes. */ - } - -#endif /* configUSE_TRACE_FACILITY */ -/*-----------------------------------------------------------*/ - - diff --git a/FreeRTOS/Source/include/FreeRTOS.h b/FreeRTOS/Source/include/FreeRTOS.h deleted file mode 100755 index c68d5ac..0000000 --- a/FreeRTOS/Source/include/FreeRTOS.h +++ /dev/null @@ -1,1290 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef INC_FREERTOS_H -#define INC_FREERTOS_H - -/* - * Include the generic headers required for the FreeRTOS port being used. - */ -#include - -/* - * If stdint.h cannot be located then: - * + If using GCC ensure the -nostdint options is *not* being used. - * + Ensure the project's include path includes the directory in which your - * compiler stores stdint.h. - * + Set any compiler options necessary for it to support C99, as technically - * stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any - * other way). - * + The FreeRTOS download includes a simple stdint.h definition that can be - * used in cases where none is provided by the compiler. The files only - * contains the typedefs required to build FreeRTOS. Read the instructions - * in FreeRTOS/source/stdint.readme for more information. - */ -#include /* READ COMMENT ABOVE. */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Application specific configuration options. */ -#include "FreeRTOSConfig.h" - -/* Basic FreeRTOS definitions. */ -#include "projdefs.h" - -/* Definitions specific to the port being used. */ -#include "portable.h" - -/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */ -#ifndef configUSE_NEWLIB_REENTRANT - #define configUSE_NEWLIB_REENTRANT 0 -#endif - -/* Required if struct _reent is used. */ -#if ( configUSE_NEWLIB_REENTRANT == 1 ) - #include -#endif -/* - * Check all the required application specific macros have been defined. - * These macros are application specific and (as downloaded) are defined - * within FreeRTOSConfig.h. - */ - -#ifndef configMINIMAL_STACK_SIZE - #error Missing definition: configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h. configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task. Refer to the demo project provided for your port for a suitable value. -#endif - -#ifndef configMAX_PRIORITIES - #error Missing definition: configMAX_PRIORITIES must be defined in FreeRTOSConfig.h. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#if configMAX_PRIORITIES < 1 - #error configMAX_PRIORITIES must be defined to be greater than or equal to 1. -#endif - -#ifndef configUSE_PREEMPTION - #error Missing definition: configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_IDLE_HOOK - #error Missing definition: configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_TICK_HOOK - #error Missing definition: configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_16_BIT_TICKS - #error Missing definition: configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0. See the Configuration section of the FreeRTOS API documentation for details. -#endif - -#ifndef configUSE_CO_ROUTINES - #define configUSE_CO_ROUTINES 0 -#endif - -#ifndef INCLUDE_vTaskPrioritySet - #define INCLUDE_vTaskPrioritySet 0 -#endif - -#ifndef INCLUDE_uxTaskPriorityGet - #define INCLUDE_uxTaskPriorityGet 0 -#endif - -#ifndef INCLUDE_vTaskDelete - #define INCLUDE_vTaskDelete 0 -#endif - -#ifndef INCLUDE_vTaskSuspend - #define INCLUDE_vTaskSuspend 0 -#endif - -#ifndef INCLUDE_vTaskDelayUntil - #define INCLUDE_vTaskDelayUntil 0 -#endif - -#ifndef INCLUDE_vTaskDelay - #define INCLUDE_vTaskDelay 0 -#endif - -#ifndef INCLUDE_xTaskGetIdleTaskHandle - #define INCLUDE_xTaskGetIdleTaskHandle 0 -#endif - -#ifndef INCLUDE_xTaskAbortDelay - #define INCLUDE_xTaskAbortDelay 0 -#endif - -#ifndef INCLUDE_xQueueGetMutexHolder - #define INCLUDE_xQueueGetMutexHolder 0 -#endif - -#ifndef INCLUDE_xSemaphoreGetMutexHolder - #define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder -#endif - -#ifndef INCLUDE_xTaskGetHandle - #define INCLUDE_xTaskGetHandle 0 -#endif - -#ifndef INCLUDE_uxTaskGetStackHighWaterMark - #define INCLUDE_uxTaskGetStackHighWaterMark 0 -#endif - -#ifndef INCLUDE_uxTaskGetStackHighWaterMark2 - #define INCLUDE_uxTaskGetStackHighWaterMark2 0 -#endif - -#ifndef INCLUDE_eTaskGetState - #define INCLUDE_eTaskGetState 0 -#endif - -#ifndef INCLUDE_xTaskResumeFromISR - #define INCLUDE_xTaskResumeFromISR 1 -#endif - -#ifndef INCLUDE_xTimerPendFunctionCall - #define INCLUDE_xTimerPendFunctionCall 0 -#endif - -#ifndef INCLUDE_xTaskGetSchedulerState - #define INCLUDE_xTaskGetSchedulerState 0 -#endif - -#ifndef INCLUDE_xTaskGetCurrentTaskHandle - #define INCLUDE_xTaskGetCurrentTaskHandle 0 -#endif - -#if configUSE_CO_ROUTINES != 0 - #ifndef configMAX_CO_ROUTINE_PRIORITIES - #error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1. - #endif -#endif - -#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK - #define configUSE_DAEMON_TASK_STARTUP_HOOK 0 -#endif - -#ifndef configUSE_APPLICATION_TASK_TAG - #define configUSE_APPLICATION_TASK_TAG 0 -#endif - -#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS - #define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0 -#endif - -#ifndef configUSE_RECURSIVE_MUTEXES - #define configUSE_RECURSIVE_MUTEXES 0 -#endif - -#ifndef configUSE_MUTEXES - #define configUSE_MUTEXES 0 -#endif - -#ifndef configUSE_TIMERS - #define configUSE_TIMERS 0 -#endif - -#ifndef configUSE_COUNTING_SEMAPHORES - #define configUSE_COUNTING_SEMAPHORES 0 -#endif - -#ifndef configUSE_ALTERNATIVE_API - #define configUSE_ALTERNATIVE_API 0 -#endif - -#ifndef portCRITICAL_NESTING_IN_TCB - #define portCRITICAL_NESTING_IN_TCB 0 -#endif - -#ifndef configMAX_TASK_NAME_LEN - #define configMAX_TASK_NAME_LEN 16 -#endif - -#ifndef configIDLE_SHOULD_YIELD - #define configIDLE_SHOULD_YIELD 1 -#endif - -#if configMAX_TASK_NAME_LEN < 1 - #error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h -#endif - -#ifndef configASSERT - #define configASSERT( x ) - #define configASSERT_DEFINED 0 -#else - #define configASSERT_DEFINED 1 -#endif - -/* configPRECONDITION should be resolve to configASSERT. - The CBMC proofs need a way to track assumptions and assertions. - A configPRECONDITION statement should express an implicit invariant or assumption made. - A configASSERT statement should express an invariant that must hold explicit before calling - the code. */ -#ifndef configPRECONDITION - #define configPRECONDITION( X ) configASSERT(X) - #define configPRECONDITION_DEFINED 0 -#else - #define configPRECONDITION_DEFINED 1 -#endif - -#ifndef portMEMORY_BARRIER - #define portMEMORY_BARRIER() -#endif - -/* The timers module relies on xTaskGetSchedulerState(). */ -#if configUSE_TIMERS == 1 - - #ifndef configTIMER_TASK_PRIORITY - #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined. - #endif /* configTIMER_TASK_PRIORITY */ - - #ifndef configTIMER_QUEUE_LENGTH - #error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined. - #endif /* configTIMER_QUEUE_LENGTH */ - - #ifndef configTIMER_TASK_STACK_DEPTH - #error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined. - #endif /* configTIMER_TASK_STACK_DEPTH */ - -#endif /* configUSE_TIMERS */ - -#ifndef portSET_INTERRUPT_MASK_FROM_ISR - #define portSET_INTERRUPT_MASK_FROM_ISR() 0 -#endif - -#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR - #define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue -#endif - -#ifndef portCLEAN_UP_TCB - #define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB -#endif - -#ifndef portPRE_TASK_DELETE_HOOK - #define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending ) -#endif - -#ifndef portSETUP_TCB - #define portSETUP_TCB( pxTCB ) ( void ) pxTCB -#endif - -#ifndef configQUEUE_REGISTRY_SIZE - #define configQUEUE_REGISTRY_SIZE 0U -#endif - -#if ( configQUEUE_REGISTRY_SIZE < 1 ) - #define vQueueAddToRegistry( xQueue, pcName ) - #define vQueueUnregisterQueue( xQueue ) - #define pcQueueGetName( xQueue ) -#endif - -#ifndef portPOINTER_SIZE_TYPE - #define portPOINTER_SIZE_TYPE uint32_t -#endif - -/* Remove any unused trace macros. */ -#ifndef traceSTART - /* Used to perform any necessary initialisation - for example, open a file - into which trace is to be written. */ - #define traceSTART() -#endif - -#ifndef traceEND - /* Use to close a trace, for example close a file into which trace has been - written. */ - #define traceEND() -#endif - -#ifndef traceTASK_SWITCHED_IN - /* Called after a task has been selected to run. pxCurrentTCB holds a pointer - to the task control block of the selected task. */ - #define traceTASK_SWITCHED_IN() -#endif - -#ifndef traceINCREASE_TICK_COUNT - /* Called before stepping the tick count after waking from tickless idle - sleep. */ - #define traceINCREASE_TICK_COUNT( x ) -#endif - -#ifndef traceLOW_POWER_IDLE_BEGIN - /* Called immediately before entering tickless idle. */ - #define traceLOW_POWER_IDLE_BEGIN() -#endif - -#ifndef traceLOW_POWER_IDLE_END - /* Called when returning to the Idle task after a tickless idle. */ - #define traceLOW_POWER_IDLE_END() -#endif - -#ifndef traceTASK_SWITCHED_OUT - /* Called before a task has been selected to run. pxCurrentTCB holds a pointer - to the task control block of the task being switched out. */ - #define traceTASK_SWITCHED_OUT() -#endif - -#ifndef traceTASK_PRIORITY_INHERIT - /* Called when a task attempts to take a mutex that is already held by a - lower priority task. pxTCBOfMutexHolder is a pointer to the TCB of the task - that holds the mutex. uxInheritedPriority is the priority the mutex holder - will inherit (the priority of the task that is attempting to obtain the - muted. */ - #define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority ) -#endif - -#ifndef traceTASK_PRIORITY_DISINHERIT - /* Called when a task releases a mutex, the holding of which had resulted in - the task inheriting the priority of a higher priority task. - pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the - mutex. uxOriginalPriority is the task's configured (base) priority. */ - #define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority ) -#endif - -#ifndef traceBLOCKING_ON_QUEUE_RECEIVE - /* Task is about to block because it cannot read from a - queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore - upon which the read was attempted. pxCurrentTCB points to the TCB of the - task that attempted the read. */ - #define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue ) -#endif - -#ifndef traceBLOCKING_ON_QUEUE_PEEK - /* Task is about to block because it cannot read from a - queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore - upon which the read was attempted. pxCurrentTCB points to the TCB of the - task that attempted the read. */ - #define traceBLOCKING_ON_QUEUE_PEEK( pxQueue ) -#endif - -#ifndef traceBLOCKING_ON_QUEUE_SEND - /* Task is about to block because it cannot write to a - queue/mutex/semaphore. pxQueue is a pointer to the queue/mutex/semaphore - upon which the write was attempted. pxCurrentTCB points to the TCB of the - task that attempted the write. */ - #define traceBLOCKING_ON_QUEUE_SEND( pxQueue ) -#endif - -#ifndef configCHECK_FOR_STACK_OVERFLOW - #define configCHECK_FOR_STACK_OVERFLOW 0 -#endif - -#ifndef configRECORD_STACK_HIGH_ADDRESS - #define configRECORD_STACK_HIGH_ADDRESS 0 -#endif - -#ifndef configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H - #define configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H 0 -#endif - -/* The following event macros are embedded in the kernel API calls. */ - -#ifndef traceMOVED_TASK_TO_READY_STATE - #define traceMOVED_TASK_TO_READY_STATE( pxTCB ) -#endif - -#ifndef tracePOST_MOVED_TASK_TO_READY_STATE - #define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB ) -#endif - -#ifndef traceQUEUE_CREATE - #define traceQUEUE_CREATE( pxNewQueue ) -#endif - -#ifndef traceQUEUE_CREATE_FAILED - #define traceQUEUE_CREATE_FAILED( ucQueueType ) -#endif - -#ifndef traceCREATE_MUTEX - #define traceCREATE_MUTEX( pxNewQueue ) -#endif - -#ifndef traceCREATE_MUTEX_FAILED - #define traceCREATE_MUTEX_FAILED() -#endif - -#ifndef traceGIVE_MUTEX_RECURSIVE - #define traceGIVE_MUTEX_RECURSIVE( pxMutex ) -#endif - -#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED - #define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex ) -#endif - -#ifndef traceTAKE_MUTEX_RECURSIVE - #define traceTAKE_MUTEX_RECURSIVE( pxMutex ) -#endif - -#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED - #define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex ) -#endif - -#ifndef traceCREATE_COUNTING_SEMAPHORE - #define traceCREATE_COUNTING_SEMAPHORE() -#endif - -#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED - #define traceCREATE_COUNTING_SEMAPHORE_FAILED() -#endif - -#ifndef traceQUEUE_SEND - #define traceQUEUE_SEND( pxQueue ) -#endif - -#ifndef traceQUEUE_SEND_FAILED - #define traceQUEUE_SEND_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_RECEIVE - #define traceQUEUE_RECEIVE( pxQueue ) -#endif - -#ifndef traceQUEUE_PEEK - #define traceQUEUE_PEEK( pxQueue ) -#endif - -#ifndef traceQUEUE_PEEK_FAILED - #define traceQUEUE_PEEK_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_PEEK_FROM_ISR - #define traceQUEUE_PEEK_FROM_ISR( pxQueue ) -#endif - -#ifndef traceQUEUE_RECEIVE_FAILED - #define traceQUEUE_RECEIVE_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_SEND_FROM_ISR - #define traceQUEUE_SEND_FROM_ISR( pxQueue ) -#endif - -#ifndef traceQUEUE_SEND_FROM_ISR_FAILED - #define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_RECEIVE_FROM_ISR - #define traceQUEUE_RECEIVE_FROM_ISR( pxQueue ) -#endif - -#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED - #define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED - #define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue ) -#endif - -#ifndef traceQUEUE_DELETE - #define traceQUEUE_DELETE( pxQueue ) -#endif - -#ifndef traceTASK_CREATE - #define traceTASK_CREATE( pxNewTCB ) -#endif - -#ifndef traceTASK_CREATE_FAILED - #define traceTASK_CREATE_FAILED() -#endif - -#ifndef traceTASK_DELETE - #define traceTASK_DELETE( pxTaskToDelete ) -#endif - -#ifndef traceTASK_DELAY_UNTIL - #define traceTASK_DELAY_UNTIL( x ) -#endif - -#ifndef traceTASK_DELAY - #define traceTASK_DELAY() -#endif - -#ifndef traceTASK_PRIORITY_SET - #define traceTASK_PRIORITY_SET( pxTask, uxNewPriority ) -#endif - -#ifndef traceTASK_SUSPEND - #define traceTASK_SUSPEND( pxTaskToSuspend ) -#endif - -#ifndef traceTASK_RESUME - #define traceTASK_RESUME( pxTaskToResume ) -#endif - -#ifndef traceTASK_RESUME_FROM_ISR - #define traceTASK_RESUME_FROM_ISR( pxTaskToResume ) -#endif - -#ifndef traceTASK_INCREMENT_TICK - #define traceTASK_INCREMENT_TICK( xTickCount ) -#endif - -#ifndef traceTIMER_CREATE - #define traceTIMER_CREATE( pxNewTimer ) -#endif - -#ifndef traceTIMER_CREATE_FAILED - #define traceTIMER_CREATE_FAILED() -#endif - -#ifndef traceTIMER_COMMAND_SEND - #define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn ) -#endif - -#ifndef traceTIMER_EXPIRED - #define traceTIMER_EXPIRED( pxTimer ) -#endif - -#ifndef traceTIMER_COMMAND_RECEIVED - #define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue ) -#endif - -#ifndef traceMALLOC - #define traceMALLOC( pvAddress, uiSize ) -#endif - -#ifndef traceFREE - #define traceFREE( pvAddress, uiSize ) -#endif - -#ifndef traceEVENT_GROUP_CREATE - #define traceEVENT_GROUP_CREATE( xEventGroup ) -#endif - -#ifndef traceEVENT_GROUP_CREATE_FAILED - #define traceEVENT_GROUP_CREATE_FAILED() -#endif - -#ifndef traceEVENT_GROUP_SYNC_BLOCK - #define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor ) -#endif - -#ifndef traceEVENT_GROUP_SYNC_END - #define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred -#endif - -#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK - #define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor ) -#endif - -#ifndef traceEVENT_GROUP_WAIT_BITS_END - #define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred -#endif - -#ifndef traceEVENT_GROUP_CLEAR_BITS - #define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear ) -#endif - -#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR - #define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear ) -#endif - -#ifndef traceEVENT_GROUP_SET_BITS - #define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet ) -#endif - -#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR - #define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet ) -#endif - -#ifndef traceEVENT_GROUP_DELETE - #define traceEVENT_GROUP_DELETE( xEventGroup ) -#endif - -#ifndef tracePEND_FUNC_CALL - #define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret) -#endif - -#ifndef tracePEND_FUNC_CALL_FROM_ISR - #define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret) -#endif - -#ifndef traceQUEUE_REGISTRY_ADD - #define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName) -#endif - -#ifndef traceTASK_NOTIFY_TAKE_BLOCK - #define traceTASK_NOTIFY_TAKE_BLOCK() -#endif - -#ifndef traceTASK_NOTIFY_TAKE - #define traceTASK_NOTIFY_TAKE() -#endif - -#ifndef traceTASK_NOTIFY_WAIT_BLOCK - #define traceTASK_NOTIFY_WAIT_BLOCK() -#endif - -#ifndef traceTASK_NOTIFY_WAIT - #define traceTASK_NOTIFY_WAIT() -#endif - -#ifndef traceTASK_NOTIFY - #define traceTASK_NOTIFY() -#endif - -#ifndef traceTASK_NOTIFY_FROM_ISR - #define traceTASK_NOTIFY_FROM_ISR() -#endif - -#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR - #define traceTASK_NOTIFY_GIVE_FROM_ISR() -#endif - -#ifndef traceSTREAM_BUFFER_CREATE_FAILED - #define traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_CREATE_STATIC_FAILED - #define traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_CREATE - #define traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_DELETE - #define traceSTREAM_BUFFER_DELETE( xStreamBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_RESET - #define traceSTREAM_BUFFER_RESET( xStreamBuffer ) -#endif - -#ifndef traceBLOCKING_ON_STREAM_BUFFER_SEND - #define traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_SEND - #define traceSTREAM_BUFFER_SEND( xStreamBuffer, xBytesSent ) -#endif - -#ifndef traceSTREAM_BUFFER_SEND_FAILED - #define traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_SEND_FROM_ISR - #define traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xBytesSent ) -#endif - -#ifndef traceBLOCKING_ON_STREAM_BUFFER_RECEIVE - #define traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_RECEIVE - #define traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength ) -#endif - -#ifndef traceSTREAM_BUFFER_RECEIVE_FAILED - #define traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer ) -#endif - -#ifndef traceSTREAM_BUFFER_RECEIVE_FROM_ISR - #define traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength ) -#endif - -#ifndef configGENERATE_RUN_TIME_STATS - #define configGENERATE_RUN_TIME_STATS 0 -#endif - -#if ( configGENERATE_RUN_TIME_STATS == 1 ) - - #ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS - #error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined. portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base. - #endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */ - - #ifndef portGET_RUN_TIME_COUNTER_VALUE - #ifndef portALT_GET_RUN_TIME_COUNTER_VALUE - #error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined. See the examples provided and the FreeRTOS web site for more information. - #endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */ - #endif /* portGET_RUN_TIME_COUNTER_VALUE */ - -#endif /* configGENERATE_RUN_TIME_STATS */ - -#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS - #define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() -#endif - -#ifndef configUSE_MALLOC_FAILED_HOOK - #define configUSE_MALLOC_FAILED_HOOK 0 -#endif - -#ifndef portPRIVILEGE_BIT - #define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 ) -#endif - -#ifndef portYIELD_WITHIN_API - #define portYIELD_WITHIN_API portYIELD -#endif - -#ifndef portSUPPRESS_TICKS_AND_SLEEP - #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) -#endif - -#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP - #define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2 -#endif - -#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2 - #error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2 -#endif - -#ifndef configUSE_TICKLESS_IDLE - #define configUSE_TICKLESS_IDLE 0 -#endif - -#ifndef configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING - #define configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( x ) -#endif - -#ifndef configPRE_SLEEP_PROCESSING - #define configPRE_SLEEP_PROCESSING( x ) -#endif - -#ifndef configPOST_SLEEP_PROCESSING - #define configPOST_SLEEP_PROCESSING( x ) -#endif - -#ifndef configUSE_QUEUE_SETS - #define configUSE_QUEUE_SETS 0 -#endif - -#ifndef portTASK_USES_FLOATING_POINT - #define portTASK_USES_FLOATING_POINT() -#endif - -#ifndef portALLOCATE_SECURE_CONTEXT - #define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize ) -#endif - -#ifndef portDONT_DISCARD - #define portDONT_DISCARD -#endif - -#ifndef configUSE_TIME_SLICING - #define configUSE_TIME_SLICING 1 -#endif - -#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS - #define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0 -#endif - -#ifndef configUSE_STATS_FORMATTING_FUNCTIONS - #define configUSE_STATS_FORMATTING_FUNCTIONS 0 -#endif - -#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID - #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() -#endif - -#ifndef configUSE_TRACE_FACILITY - #define configUSE_TRACE_FACILITY 0 -#endif - -#ifndef mtCOVERAGE_TEST_MARKER - #define mtCOVERAGE_TEST_MARKER() -#endif - -#ifndef mtCOVERAGE_TEST_DELAY - #define mtCOVERAGE_TEST_DELAY() -#endif - -#ifndef portASSERT_IF_IN_ISR - #define portASSERT_IF_IN_ISR() -#endif - -#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION - #define configUSE_PORT_OPTIMISED_TASK_SELECTION 0 -#endif - -#ifndef configAPPLICATION_ALLOCATED_HEAP - #define configAPPLICATION_ALLOCATED_HEAP 0 -#endif - -#ifndef configUSE_TASK_NOTIFICATIONS - #define configUSE_TASK_NOTIFICATIONS 1 -#endif - -#ifndef configUSE_POSIX_ERRNO - #define configUSE_POSIX_ERRNO 0 -#endif - -#ifndef portTICK_TYPE_IS_ATOMIC - #define portTICK_TYPE_IS_ATOMIC 0 -#endif - -#ifndef configSUPPORT_STATIC_ALLOCATION - /* Defaults to 0 for backward compatibility. */ - #define configSUPPORT_STATIC_ALLOCATION 0 -#endif - -#ifndef configSUPPORT_DYNAMIC_ALLOCATION - /* Defaults to 1 for backward compatibility. */ - #define configSUPPORT_DYNAMIC_ALLOCATION 1 -#endif - -#ifndef configSTACK_DEPTH_TYPE - /* Defaults to uint16_t for backward compatibility, but can be overridden - in FreeRTOSConfig.h if uint16_t is too restrictive. */ - #define configSTACK_DEPTH_TYPE uint16_t -#endif - -#ifndef configMESSAGE_BUFFER_LENGTH_TYPE - /* Defaults to size_t for backward compatibility, but can be overridden - in FreeRTOSConfig.h if lengths will always be less than the number of bytes - in a size_t. */ - #define configMESSAGE_BUFFER_LENGTH_TYPE size_t -#endif - -/* Sanity check the configuration. */ -#if( configUSE_TICKLESS_IDLE != 0 ) - #if( INCLUDE_vTaskSuspend != 1 ) - #error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0 - #endif /* INCLUDE_vTaskSuspend */ -#endif /* configUSE_TICKLESS_IDLE */ - -#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) ) - #error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1. -#endif - -#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) ) - #error configUSE_MUTEXES must be set to 1 to use recursive mutexes -#endif - -#ifndef configINITIAL_TICK_COUNT - #define configINITIAL_TICK_COUNT 0 -#endif - -#if( portTICK_TYPE_IS_ATOMIC == 0 ) - /* Either variables of tick type cannot be read atomically, or - portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when - the tick count is returned to the standard critical section macros. */ - #define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL() - #define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL() - #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR() - #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) ) -#else - /* The tick type can be read atomically, so critical sections used when the - tick count is returned can be defined away. */ - #define portTICK_TYPE_ENTER_CRITICAL() - #define portTICK_TYPE_EXIT_CRITICAL() - #define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0 - #define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x -#endif - -/* Definitions to allow backward compatibility with FreeRTOS versions prior to -V8 if desired. */ -#ifndef configENABLE_BACKWARD_COMPATIBILITY - #define configENABLE_BACKWARD_COMPATIBILITY 1 -#endif - -#ifndef configPRINTF - /* configPRINTF() was not defined, so define it away to nothing. To use - configPRINTF() then define it as follows (where MyPrintFunction() is - provided by the application writer): - - void MyPrintFunction(const char *pcFormat, ... ); - #define configPRINTF( X ) MyPrintFunction X - - Then call like a standard printf() function, but placing brackets around - all parameters so they are passed as a single parameter. For example: - configPRINTF( ("Value = %d", MyVariable) ); */ - #define configPRINTF( X ) -#endif - -#ifndef configMAX - /* The application writer has not provided their own MAX macro, so define - the following generic implementation. */ - #define configMAX( a, b ) ( ( ( a ) > ( b ) ) ? ( a ) : ( b ) ) -#endif - -#ifndef configMIN - /* The application writer has not provided their own MAX macro, so define - the following generic implementation. */ - #define configMIN( a, b ) ( ( ( a ) < ( b ) ) ? ( a ) : ( b ) ) -#endif - -#if configENABLE_BACKWARD_COMPATIBILITY == 1 - #define eTaskStateGet eTaskGetState - #define portTickType TickType_t - #define xTaskHandle TaskHandle_t - #define xQueueHandle QueueHandle_t - #define xSemaphoreHandle SemaphoreHandle_t - #define xQueueSetHandle QueueSetHandle_t - #define xQueueSetMemberHandle QueueSetMemberHandle_t - #define xTimeOutType TimeOut_t - #define xMemoryRegion MemoryRegion_t - #define xTaskParameters TaskParameters_t - #define xTaskStatusType TaskStatus_t - #define xTimerHandle TimerHandle_t - #define xCoRoutineHandle CoRoutineHandle_t - #define pdTASK_HOOK_CODE TaskHookFunction_t - #define portTICK_RATE_MS portTICK_PERIOD_MS - #define pcTaskGetTaskName pcTaskGetName - #define pcTimerGetTimerName pcTimerGetName - #define pcQueueGetQueueName pcQueueGetName - #define vTaskGetTaskInfo vTaskGetInfo - - /* Backward compatibility within the scheduler code only - these definitions - are not really required but are included for completeness. */ - #define tmrTIMER_CALLBACK TimerCallbackFunction_t - #define pdTASK_CODE TaskFunction_t - #define xListItem ListItem_t - #define xList List_t - - /* For libraries that break the list data hiding, and access list structure - members directly (which is not supposed to be done). */ - #define pxContainer pvContainer -#endif /* configENABLE_BACKWARD_COMPATIBILITY */ - -#if( configUSE_ALTERNATIVE_API != 0 ) - #error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0 -#endif - -/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even -if floating point hardware is otherwise supported by the FreeRTOS port in use. -This constant is not supported by all FreeRTOS ports that include floating -point support. */ -#ifndef configUSE_TASK_FPU_SUPPORT - #define configUSE_TASK_FPU_SUPPORT 1 -#endif - -/* Set configENABLE_MPU to 1 to enable MPU support and 0 to disable it. This is -currently used in ARMv8M ports. */ -#ifndef configENABLE_MPU - #define configENABLE_MPU 0 -#endif - -/* Set configENABLE_FPU to 1 to enable FPU support and 0 to disable it. This is -currently used in ARMv8M ports. */ -#ifndef configENABLE_FPU - #define configENABLE_FPU 1 -#endif - -/* Set configENABLE_TRUSTZONE to 1 enable TrustZone support and 0 to disable it. -This is currently used in ARMv8M ports. */ -#ifndef configENABLE_TRUSTZONE - #define configENABLE_TRUSTZONE 1 -#endif - -/* Set configRUN_FREERTOS_SECURE_ONLY to 1 to run the FreeRTOS ARMv8M port on -the Secure Side only. */ -#ifndef configRUN_FREERTOS_SECURE_ONLY - #define configRUN_FREERTOS_SECURE_ONLY 0 -#endif - -/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using - * dynamically allocated RAM, in which case when any task is deleted it is known - * that both the task's stack and TCB need to be freed. Sometimes the - * FreeRTOSConfig.h settings only allow a task to be created using statically - * allocated RAM, in which case when any task is deleted it is known that neither - * the task's stack or TCB should be freed. Sometimes the FreeRTOSConfig.h - * settings allow a task to be created using either statically or dynamically - * allocated RAM, in which case a member of the TCB is used to record whether the - * stack and/or TCB were allocated statically or dynamically, so when a task is - * deleted the RAM that was allocated dynamically is freed again and no attempt is - * made to free the RAM that was allocated statically. - * tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a - * task to be created using either statically or dynamically allocated RAM. Note - * that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with - * a statically allocated stack and a dynamically allocated TCB. - * - * The following table lists various combinations of portUSING_MPU_WRAPPERS, - * configSUPPORT_DYNAMIC_ALLOCATION and configSUPPORT_STATIC_ALLOCATION and - * when it is possible to have both static and dynamic allocation: - * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ - * | MPU | Dynamic | Static | Available Functions | Possible Allocations | Both Dynamic and | Need Free | - * | | | | | | Static Possible | | - * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ - * | 0 | 0 | 1 | xTaskCreateStatic | TCB - Static, Stack - Static | No | No | - * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| - * | 0 | 1 | 0 | xTaskCreate | TCB - Dynamic, Stack - Dynamic | No | Yes | - * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| - * | 0 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | - * | | | | xTaskCreateStatic | 2. TCB - Static, Stack - Static | | | - * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| - * | 1 | 0 | 1 | xTaskCreateStatic, | TCB - Static, Stack - Static | No | No | - * | | | | xTaskCreateRestrictedStatic | | | | - * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| - * | 1 | 1 | 0 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | - * | | | | xTaskCreateRestricted | 2. TCB - Dynamic, Stack - Static | | | - * +-----|---------|--------|-----------------------------|-----------------------------------|------------------|-----------| - * | 1 | 1 | 1 | xTaskCreate, | 1. TCB - Dynamic, Stack - Dynamic | Yes | Yes | - * | | | | xTaskCreateStatic, | 2. TCB - Dynamic, Stack - Static | | | - * | | | | xTaskCreateRestricted, | 3. TCB - Static, Stack - Static | | | - * | | | | xTaskCreateRestrictedStatic | | | | - * +-----+---------+--------+-----------------------------+-----------------------------------+------------------+-----------+ - */ -#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( portUSING_MPU_WRAPPERS == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) || \ - ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) ) - -/* - * In line with software engineering best practice, FreeRTOS implements a strict - * data hiding policy, so the real structures used by FreeRTOS to maintain the - * state of tasks, queues, semaphores, etc. are not accessible to the application - * code. However, if the application writer wants to statically allocate such - * an object then the size of the object needs to be know. Dummy structures - * that are guaranteed to have the same size and alignment requirements of the - * real objects are used for this purpose. The dummy list and list item - * structures below are used for inclusion in such a dummy structure. - */ -struct xSTATIC_LIST_ITEM -{ - #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) - TickType_t xDummy1; - #endif - TickType_t xDummy2; - void *pvDummy3[ 4 ]; - #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) - TickType_t xDummy4; - #endif -}; -typedef struct xSTATIC_LIST_ITEM StaticListItem_t; - -/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ -struct xSTATIC_MINI_LIST_ITEM -{ - #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) - TickType_t xDummy1; - #endif - TickType_t xDummy2; - void *pvDummy3[ 2 ]; -}; -typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t; - -/* See the comments above the struct xSTATIC_LIST_ITEM definition. */ -typedef struct xSTATIC_LIST -{ - #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) - TickType_t xDummy1; - #endif - UBaseType_t uxDummy2; - void *pvDummy3; - StaticMiniListItem_t xDummy4; - #if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 1 ) - TickType_t xDummy5; - #endif -} StaticList_t; - -/* - * In line with software engineering best practice, especially when supplying a - * library that is likely to change in future versions, FreeRTOS implements a - * strict data hiding policy. This means the Task structure used internally by - * FreeRTOS is not accessible to application code. However, if the application - * writer wants to statically allocate the memory required to create a task then - * the size of the task object needs to be know. The StaticTask_t structure - * below is provided for this purpose. Its sizes and alignment requirements are - * guaranteed to match those of the genuine structure, no matter which - * architecture is being used, and no matter how the values in FreeRTOSConfig.h - * are set. Its contents are somewhat obfuscated in the hope users will - * recognise that it would be unwise to make direct use of the structure members. - */ -typedef struct xSTATIC_TCB -{ - void *pxDummy1; - #if ( portUSING_MPU_WRAPPERS == 1 ) - xMPU_SETTINGS xDummy2; - #endif - StaticListItem_t xDummy3[ 2 ]; - UBaseType_t uxDummy5; - void *pxDummy6; - uint8_t ucDummy7[ configMAX_TASK_NAME_LEN ]; - #if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) ) - void *pxDummy8; - #endif - #if ( portCRITICAL_NESTING_IN_TCB == 1 ) - UBaseType_t uxDummy9; - #endif - #if ( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxDummy10[ 2 ]; - #endif - #if ( configUSE_MUTEXES == 1 ) - UBaseType_t uxDummy12[ 2 ]; - #endif - #if ( configUSE_APPLICATION_TASK_TAG == 1 ) - void *pxDummy14; - #endif - #if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 ) - void *pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ]; - #endif - #if ( configGENERATE_RUN_TIME_STATS == 1 ) - uint32_t ulDummy16; - #endif - #if ( configUSE_NEWLIB_REENTRANT == 1 ) - struct _reent xDummy17; - #endif - #if ( configUSE_TASK_NOTIFICATIONS == 1 ) - uint32_t ulDummy18; - uint8_t ucDummy19; - #endif - #if ( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) - uint8_t uxDummy20; - #endif - - #if( INCLUDE_xTaskAbortDelay == 1 ) - uint8_t ucDummy21; - #endif - #if ( configUSE_POSIX_ERRNO == 1 ) - int iDummy22; - #endif -} StaticTask_t; - -/* - * In line with software engineering best practice, especially when supplying a - * library that is likely to change in future versions, FreeRTOS implements a - * strict data hiding policy. This means the Queue structure used internally by - * FreeRTOS is not accessible to application code. However, if the application - * writer wants to statically allocate the memory required to create a queue - * then the size of the queue object needs to be know. The StaticQueue_t - * structure below is provided for this purpose. Its sizes and alignment - * requirements are guaranteed to match those of the genuine structure, no - * matter which architecture is being used, and no matter how the values in - * FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in the hope - * users will recognise that it would be unwise to make direct use of the - * structure members. - */ -typedef struct xSTATIC_QUEUE -{ - void *pvDummy1[ 3 ]; - - union - { - void *pvDummy2; - UBaseType_t uxDummy2; - } u; - - StaticList_t xDummy3[ 2 ]; - UBaseType_t uxDummy4[ 3 ]; - uint8_t ucDummy5[ 2 ]; - - #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) - uint8_t ucDummy6; - #endif - - #if ( configUSE_QUEUE_SETS == 1 ) - void *pvDummy7; - #endif - - #if ( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxDummy8; - uint8_t ucDummy9; - #endif - -} StaticQueue_t; -typedef StaticQueue_t StaticSemaphore_t; - -/* - * In line with software engineering best practice, especially when supplying a - * library that is likely to change in future versions, FreeRTOS implements a - * strict data hiding policy. This means the event group structure used - * internally by FreeRTOS is not accessible to application code. However, if - * the application writer wants to statically allocate the memory required to - * create an event group then the size of the event group object needs to be - * know. The StaticEventGroup_t structure below is provided for this purpose. - * Its sizes and alignment requirements are guaranteed to match those of the - * genuine structure, no matter which architecture is being used, and no matter - * how the values in FreeRTOSConfig.h are set. Its contents are somewhat - * obfuscated in the hope users will recognise that it would be unwise to make - * direct use of the structure members. - */ -typedef struct xSTATIC_EVENT_GROUP -{ - TickType_t xDummy1; - StaticList_t xDummy2; - - #if( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxDummy3; - #endif - - #if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) - uint8_t ucDummy4; - #endif - -} StaticEventGroup_t; - -/* - * In line with software engineering best practice, especially when supplying a - * library that is likely to change in future versions, FreeRTOS implements a - * strict data hiding policy. This means the software timer structure used - * internally by FreeRTOS is not accessible to application code. However, if - * the application writer wants to statically allocate the memory required to - * create a software timer then the size of the queue object needs to be know. - * The StaticTimer_t structure below is provided for this purpose. Its sizes - * and alignment requirements are guaranteed to match those of the genuine - * structure, no matter which architecture is being used, and no matter how the - * values in FreeRTOSConfig.h are set. Its contents are somewhat obfuscated in - * the hope users will recognise that it would be unwise to make direct use of - * the structure members. - */ -typedef struct xSTATIC_TIMER -{ - void *pvDummy1; - StaticListItem_t xDummy2; - TickType_t xDummy3; - void *pvDummy5; - TaskFunction_t pvDummy6; - #if( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxDummy7; - #endif - uint8_t ucDummy8; - -} StaticTimer_t; - -/* -* In line with software engineering best practice, especially when supplying a -* library that is likely to change in future versions, FreeRTOS implements a -* strict data hiding policy. This means the stream buffer structure used -* internally by FreeRTOS is not accessible to application code. However, if -* the application writer wants to statically allocate the memory required to -* create a stream buffer then the size of the stream buffer object needs to be -* know. The StaticStreamBuffer_t structure below is provided for this purpose. -* Its size and alignment requirements are guaranteed to match those of the -* genuine structure, no matter which architecture is being used, and no matter -* how the values in FreeRTOSConfig.h are set. Its contents are somewhat -* obfuscated in the hope users will recognise that it would be unwise to make -* direct use of the structure members. -*/ -typedef struct xSTATIC_STREAM_BUFFER -{ - size_t uxDummy1[ 4 ]; - void * pvDummy2[ 3 ]; - uint8_t ucDummy3; - #if ( configUSE_TRACE_FACILITY == 1 ) - UBaseType_t uxDummy4; - #endif -} StaticStreamBuffer_t; - -/* Message buffers are built on stream buffers. */ -typedef StaticStreamBuffer_t StaticMessageBuffer_t; - -#ifdef __cplusplus -} -#endif - -#endif /* INC_FREERTOS_H */ - diff --git a/FreeRTOS/Source/include/atomic.h b/FreeRTOS/Source/include/atomic.h deleted file mode 100755 index 3d23ca4..0000000 --- a/FreeRTOS/Source/include/atomic.h +++ /dev/null @@ -1,547 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/** - * @file atomic.h - * @brief FreeRTOS atomic operation support. - * - * Two implementations of atomic are given in this header file: - * 1. Disabling interrupt globally. - * 2. ISA native atomic support. - * The former is available to all ports (compiler-architecture combination), - * while the latter is only available to ports compiling with GCC (version at - * least 4.7.0), which also have ISA atomic support. - * - * User can select which implementation to use by: - * setting/clearing configUSE_ATOMIC_INSTRUCTION in FreeRTOSConfig.h. - * Define AND set configUSE_ATOMIC_INSTRUCTION to 1 for ISA native atomic support. - * Undefine OR clear configUSE_ATOMIC_INSTRUCTION for disabling global interrupt - * implementation. - * - * @see GCC Built-in Functions for Memory Model Aware Atomic Operations - * https://gcc.gnu.org/onlinedocs/gcc/_005f_005fatomic-Builtins.html - */ - -#ifndef ATOMIC_H -#define ATOMIC_H - -#ifndef INC_FREERTOS_H - #error "include FreeRTOS.h must appear in source files before include atomic.h" -#endif - -/* Standard includes. */ -#include - -#ifdef __cplusplus -extern "C" { -#endif - -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - /* Needed for __atomic_compare_exchange() weak=false. */ - #include - - /* This branch is for GCC compiler and GCC compiler only. */ - #ifndef portFORCE_INLINE - #define portFORCE_INLINE inline __attribute__((always_inline)) - #endif - -#else - - /* Port specific definitions -- entering/exiting critical section. - * Refer template -- ./lib/FreeRTOS/portable/Compiler/Arch/portmacro.h - * - * Every call to ATOMIC_EXIT_CRITICAL() must be closely paired with - * ATOMIC_ENTER_CRITICAL(). - */ - #if defined( portSET_INTERRUPT_MASK_FROM_ISR ) - - /* Nested interrupt scheme is supported in this port. */ - #define ATOMIC_ENTER_CRITICAL() \ - UBaseType_t uxCriticalSectionType = portSET_INTERRUPT_MASK_FROM_ISR() - - #define ATOMIC_EXIT_CRITICAL() \ - portCLEAR_INTERRUPT_MASK_FROM_ISR( uxCriticalSectionType ) - - #else - - /* Nested interrupt scheme is NOT supported in this port. */ - #define ATOMIC_ENTER_CRITICAL() portENTER_CRITICAL() - #define ATOMIC_EXIT_CRITICAL() portEXIT_CRITICAL() - - #endif /* portSET_INTERRUPT_MASK_FROM_ISR() */ - - /* Port specific definition -- "always inline". - * Inline is compiler specific, and may not always get inlined depending on your optimization level. - * Also, inline is considerred as performance optimization for atomic. - * Thus, if portFORCE_INLINE is not provided by portmacro.h, instead of resulting error, - * simply define it. - */ - #ifndef portFORCE_INLINE - #define portFORCE_INLINE - #endif - -#endif /* configUSE_GCC_BUILTIN_ATOMICS */ - -#define ATOMIC_COMPARE_AND_SWAP_SUCCESS 0x1U /**< Compare and swap succeeded, swapped. */ -#define ATOMIC_COMPARE_AND_SWAP_FAILURE 0x0U /**< Compare and swap failed, did not swap. */ - -/*----------------------------- Swap && CAS ------------------------------*/ - -/** - * Atomic compare-and-swap - * - * @brief Performs an atomic compare-and-swap operation on the specified values. - * - * @param[in, out] pDestination Pointer to memory location from where value is - * to be loaded and checked. - * @param[in] ulExchange If condition meets, write this value to memory. - * @param[in] ulComparand Swap condition. - * - * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. - * - * @note This function only swaps *pDestination with ulExchange, if previous - * *pDestination value equals ulComparand. - */ -static portFORCE_INLINE uint32_t Atomic_CompareAndSwap_u32( - uint32_t volatile * pDestination, - uint32_t ulExchange, - uint32_t ulComparand ) -{ - - uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; - -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - if ( __atomic_compare_exchange( pDestination, - &ulComparand, - &ulExchange, - false, - __ATOMIC_SEQ_CST, - __ATOMIC_SEQ_CST ) ) - { - ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; - } - -#else - - ATOMIC_ENTER_CRITICAL(); - - if ( *pDestination == ulComparand ) - { - *pDestination = ulExchange; - ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; - } - - ATOMIC_EXIT_CRITICAL(); - -#endif - - return ulReturnValue; - -} - -/** - * Atomic swap (pointers) - * - * @brief Atomically sets the address pointed to by *ppDestination to the value - * of *pExchange. - * - * @param[in, out] ppDestination Pointer to memory location from where a pointer - * value is to be loaded and written back to. - * @param[in] pExchange Pointer value to be written to *ppDestination. - * - * @return The initial value of *ppDestination. - */ -static portFORCE_INLINE void * Atomic_SwapPointers_p32( - void * volatile * ppDestination, - void * pExchange ) -{ - void * pReturnValue; - -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - __atomic_exchange( ppDestination, &pExchange, &pReturnValue, __ATOMIC_SEQ_CST ); - -#else - - ATOMIC_ENTER_CRITICAL(); - - pReturnValue = *ppDestination; - - *ppDestination = pExchange; - - ATOMIC_EXIT_CRITICAL(); - -#endif - - return pReturnValue; -} - -/** - * Atomic compare-and-swap (pointers) - * - * @brief Performs an atomic compare-and-swap operation on the specified pointer - * values. - * - * @param[in, out] ppDestination Pointer to memory location from where a pointer - * value is to be loaded and checked. - * @param[in] pExchange If condition meets, write this value to memory. - * @param[in] pComparand Swap condition. - * - * @return Unsigned integer of value 1 or 0. 1 for swapped, 0 for not swapped. - * - * @note This function only swaps *ppDestination with pExchange, if previous - * *ppDestination value equals pComparand. - */ -static portFORCE_INLINE uint32_t Atomic_CompareAndSwapPointers_p32( - void * volatile * ppDestination, - void * pExchange, void * pComparand ) -{ - uint32_t ulReturnValue = ATOMIC_COMPARE_AND_SWAP_FAILURE; - -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - if ( __atomic_compare_exchange( ppDestination, - &pComparand, - &pExchange, - false, - __ATOMIC_SEQ_CST, - __ATOMIC_SEQ_CST ) ) - { - ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; - } - -#else - - ATOMIC_ENTER_CRITICAL(); - - if ( *ppDestination == pComparand ) - { - *ppDestination = pExchange; - ulReturnValue = ATOMIC_COMPARE_AND_SWAP_SUCCESS; - } - - ATOMIC_EXIT_CRITICAL(); - -#endif - - return ulReturnValue; -} - - -/*----------------------------- Arithmetic ------------------------------*/ - -/** - * Atomic add - * - * @brief Atomically adds count to the value of the specified pointer points to. - * - * @param[in,out] pAddend Pointer to memory location from where value is to be - * loaded and written back to. - * @param[in] ulCount Value to be added to *pAddend. - * - * @return previous *pAddend value. - */ -static portFORCE_INLINE uint32_t Atomic_Add_u32( - uint32_t volatile * pAddend, - uint32_t ulCount ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_add(pAddend, ulCount, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pAddend; - - *pAddend += ulCount; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/** - * Atomic subtract - * - * @brief Atomically subtracts count from the value of the specified pointer - * pointers to. - * - * @param[in,out] pAddend Pointer to memory location from where value is to be - * loaded and written back to. - * @param[in] ulCount Value to be subtract from *pAddend. - * - * @return previous *pAddend value. - */ -static portFORCE_INLINE uint32_t Atomic_Subtract_u32( - uint32_t volatile * pAddend, - uint32_t ulCount ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_sub(pAddend, ulCount, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pAddend; - - *pAddend -= ulCount; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/** - * Atomic increment - * - * @brief Atomically increments the value of the specified pointer points to. - * - * @param[in,out] pAddend Pointer to memory location from where value is to be - * loaded and written back to. - * - * @return *pAddend value before increment. - */ -static portFORCE_INLINE uint32_t Atomic_Increment_u32( uint32_t volatile * pAddend ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_add(pAddend, 1, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pAddend; - - *pAddend += 1; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/** - * Atomic decrement - * - * @brief Atomically decrements the value of the specified pointer points to - * - * @param[in,out] pAddend Pointer to memory location from where value is to be - * loaded and written back to. - * - * @return *pAddend value before decrement. - */ -static portFORCE_INLINE uint32_t Atomic_Decrement_u32( uint32_t volatile * pAddend ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_sub(pAddend, 1, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pAddend; - - *pAddend -= 1; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/*----------------------------- Bitwise Logical ------------------------------*/ - -/** - * Atomic OR - * - * @brief Performs an atomic OR operation on the specified values. - * - * @param [in, out] pDestination Pointer to memory location from where value is - * to be loaded and written back to. - * @param [in] ulValue Value to be ORed with *pDestination. - * - * @return The original value of *pDestination. - */ -static portFORCE_INLINE uint32_t Atomic_OR_u32( - uint32_t volatile * pDestination, - uint32_t ulValue ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_or(pDestination, ulValue, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pDestination; - - *pDestination |= ulValue; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/** - * Atomic AND - * - * @brief Performs an atomic AND operation on the specified values. - * - * @param [in, out] pDestination Pointer to memory location from where value is - * to be loaded and written back to. - * @param [in] ulValue Value to be ANDed with *pDestination. - * - * @return The original value of *pDestination. - */ -static portFORCE_INLINE uint32_t Atomic_AND_u32( - uint32_t volatile * pDestination, - uint32_t ulValue ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_and(pDestination, ulValue, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pDestination; - - *pDestination &= ulValue; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/** - * Atomic NAND - * - * @brief Performs an atomic NAND operation on the specified values. - * - * @param [in, out] pDestination Pointer to memory location from where value is - * to be loaded and written back to. - * @param [in] ulValue Value to be NANDed with *pDestination. - * - * @return The original value of *pDestination. - */ -static portFORCE_INLINE uint32_t Atomic_NAND_u32( - uint32_t volatile * pDestination, - uint32_t ulValue ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_nand(pDestination, ulValue, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pDestination; - - *pDestination = ~(ulCurrent & ulValue); - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -/** - * Atomic XOR - * - * @brief Performs an atomic XOR operation on the specified values. - * - * @param [in, out] pDestination Pointer to memory location from where value is - * to be loaded and written back to. - * @param [in] ulValue Value to be XORed with *pDestination. - * - * @return The original value of *pDestination. - */ -static portFORCE_INLINE uint32_t Atomic_XOR_u32( - uint32_t volatile * pDestination, - uint32_t ulValue ) -{ -#if defined ( configUSE_GCC_BUILTIN_ATOMICS ) && ( configUSE_GCC_BUILTIN_ATOMICS == 1 ) - - return __atomic_fetch_xor(pDestination, ulValue, __ATOMIC_SEQ_CST); - -#else - - uint32_t ulCurrent; - - ATOMIC_ENTER_CRITICAL(); - - ulCurrent = *pDestination; - - *pDestination ^= ulValue; - - ATOMIC_EXIT_CRITICAL(); - - return ulCurrent; - -#endif -} - -#ifdef __cplusplus -} -#endif - -#endif /* ATOMIC_H */ diff --git a/FreeRTOS/Source/include/deprecated_definitions.h b/FreeRTOS/Source/include/deprecated_definitions.h deleted file mode 100755 index 9cece98..0000000 --- a/FreeRTOS/Source/include/deprecated_definitions.h +++ /dev/null @@ -1,279 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef DEPRECATED_DEFINITIONS_H -#define DEPRECATED_DEFINITIONS_H - - -/* Each FreeRTOS port has a unique portmacro.h header file. Originally a -pre-processor definition was used to ensure the pre-processor found the correct -portmacro.h file for the port being used. That scheme was deprecated in favour -of setting the compiler's include path such that it found the correct -portmacro.h file - removing the need for the constant and allowing the -portmacro.h file to be located anywhere in relation to the port being used. The -definitions below remain in the code for backward compatibility only. New -projects should not use them. */ - -#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT - #include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT - #include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef GCC_MEGA_AVR - #include "../portable/GCC/ATMega323/portmacro.h" -#endif - -#ifdef IAR_MEGA_AVR - #include "../portable/IAR/ATMega323/portmacro.h" -#endif - -#ifdef MPLAB_PIC24_PORT - #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" -#endif - -#ifdef MPLAB_DSPIC_PORT - #include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h" -#endif - -#ifdef MPLAB_PIC18F_PORT - #include "../../Source/portable/MPLAB/PIC18F/portmacro.h" -#endif - -#ifdef MPLAB_PIC32MX_PORT - #include "../../Source/portable/MPLAB/PIC32MX/portmacro.h" -#endif - -#ifdef _FEDPICC - #include "libFreeRTOS/Include/portmacro.h" -#endif - -#ifdef SDCC_CYGNAL - #include "../../Source/portable/SDCC/Cygnal/portmacro.h" -#endif - -#ifdef GCC_ARM7 - #include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h" -#endif - -#ifdef GCC_ARM7_ECLIPSE - #include "portmacro.h" -#endif - -#ifdef ROWLEY_LPC23xx - #include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h" -#endif - -#ifdef IAR_MSP430 - #include "..\..\Source\portable\IAR\MSP430\portmacro.h" -#endif - -#ifdef GCC_MSP430 - #include "../../Source/portable/GCC/MSP430F449/portmacro.h" -#endif - -#ifdef ROWLEY_MSP430 - #include "../../Source/portable/Rowley/MSP430F449/portmacro.h" -#endif - -#ifdef ARM7_LPC21xx_KEIL_RVDS - #include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h" -#endif - -#ifdef SAM7_GCC - #include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h" -#endif - -#ifdef SAM7_IAR - #include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h" -#endif - -#ifdef SAM9XE_IAR - #include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h" -#endif - -#ifdef LPC2000_IAR - #include "..\..\Source\portable\IAR\LPC2000\portmacro.h" -#endif - -#ifdef STR71X_IAR - #include "..\..\Source\portable\IAR\STR71x\portmacro.h" -#endif - -#ifdef STR75X_IAR - #include "..\..\Source\portable\IAR\STR75x\portmacro.h" -#endif - -#ifdef STR75X_GCC - #include "..\..\Source\portable\GCC\STR75x\portmacro.h" -#endif - -#ifdef STR91X_IAR - #include "..\..\Source\portable\IAR\STR91x\portmacro.h" -#endif - -#ifdef GCC_H8S - #include "../../Source/portable/GCC/H8S2329/portmacro.h" -#endif - -#ifdef GCC_AT91FR40008 - #include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h" -#endif - -#ifdef RVDS_ARMCM3_LM3S102 - #include "../../Source/portable/RVDS/ARM_CM3/portmacro.h" -#endif - -#ifdef GCC_ARMCM3_LM3S102 - #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" -#endif - -#ifdef GCC_ARMCM3 - #include "../../Source/portable/GCC/ARM_CM3/portmacro.h" -#endif - -#ifdef IAR_ARM_CM3 - #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" -#endif - -#ifdef IAR_ARMCM3_LM - #include "../../Source/portable/IAR/ARM_CM3/portmacro.h" -#endif - -#ifdef HCS12_CODE_WARRIOR - #include "../../Source/portable/CodeWarrior/HCS12/portmacro.h" -#endif - -#ifdef MICROBLAZE_GCC - #include "../../Source/portable/GCC/MicroBlaze/portmacro.h" -#endif - -#ifdef TERN_EE - #include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h" -#endif - -#ifdef GCC_HCS12 - #include "../../Source/portable/GCC/HCS12/portmacro.h" -#endif - -#ifdef GCC_MCF5235 - #include "../../Source/portable/GCC/MCF5235/portmacro.h" -#endif - -#ifdef COLDFIRE_V2_GCC - #include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h" -#endif - -#ifdef COLDFIRE_V2_CODEWARRIOR - #include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h" -#endif - -#ifdef GCC_PPC405 - #include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h" -#endif - -#ifdef GCC_PPC440 - #include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h" -#endif - -#ifdef _16FX_SOFTUNE - #include "..\..\Source\portable\Softune\MB96340\portmacro.h" -#endif - -#ifdef BCC_INDUSTRIAL_PC_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\PC\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef BCC_FLASH_LITE_186_PORT - /* A short file name has to be used in place of the normal - FreeRTOSConfig.h when using the Borland compiler. */ - #include "frconfig.h" - #include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h" - typedef void ( __interrupt __far *pxISR )(); -#endif - -#ifdef __GNUC__ - #ifdef __AVR32_AVR32A__ - #include "portmacro.h" - #endif -#endif - -#ifdef __ICCAVR32__ - #ifdef __CORE__ - #if __CORE__ == __AVR32A__ - #include "portmacro.h" - #endif - #endif -#endif - -#ifdef __91467D - #include "portmacro.h" -#endif - -#ifdef __96340 - #include "portmacro.h" -#endif - - -#ifdef __IAR_V850ES_Fx3__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_V850ES_Jx3__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_V850ES_Jx3_L__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_V850ES_Jx2__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_V850ES_Hx2__ - #include "../../Source/portable/IAR/V850ES/portmacro.h" -#endif - -#ifdef __IAR_78K0R_Kx3__ - #include "../../Source/portable/IAR/78K0R/portmacro.h" -#endif - -#ifdef __IAR_78K0R_Kx3L__ - #include "../../Source/portable/IAR/78K0R/portmacro.h" -#endif - -#endif /* DEPRECATED_DEFINITIONS_H */ - diff --git a/FreeRTOS/Source/include/event_groups.h b/FreeRTOS/Source/include/event_groups.h deleted file mode 100755 index 1f38bdb..0000000 --- a/FreeRTOS/Source/include/event_groups.h +++ /dev/null @@ -1,757 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -#ifndef EVENT_GROUPS_H -#define EVENT_GROUPS_H - -#ifndef INC_FREERTOS_H - #error "include FreeRTOS.h" must appear in source files before "include event_groups.h" -#endif - -/* FreeRTOS includes. */ -#include "timers.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * An event group is a collection of bits to which an application can assign a - * meaning. For example, an application may create an event group to convey - * the status of various CAN bus related events in which bit 0 might mean "A CAN - * message has been received and is ready for processing", bit 1 might mean "The - * application has queued a message that is ready for sending onto the CAN - * network", and bit 2 might mean "It is time to send a SYNC message onto the - * CAN network" etc. A task can then test the bit values to see which events - * are active, and optionally enter the Blocked state to wait for a specified - * bit or a group of specified bits to be active. To continue the CAN bus - * example, a CAN controlling task can enter the Blocked state (and therefore - * not consume any processing time) until either bit 0, bit 1 or bit 2 are - * active, at which time the bit that was actually active would inform the task - * which action it had to take (process a received message, send a message, or - * send a SYNC). - * - * The event groups implementation contains intelligence to avoid race - * conditions that would otherwise occur were an application to use a simple - * variable for the same purpose. This is particularly important with respect - * to when a bit within an event group is to be cleared, and when bits have to - * be set and then tested atomically - as is the case where event groups are - * used to create a synchronisation point between multiple tasks (a - * 'rendezvous'). - * - * \defgroup EventGroup - */ - - - -/** - * event_groups.h - * - * Type by which event groups are referenced. For example, a call to - * xEventGroupCreate() returns an EventGroupHandle_t variable that can then - * be used as a parameter to other event group functions. - * - * \defgroup EventGroupHandle_t EventGroupHandle_t - * \ingroup EventGroup - */ -struct EventGroupDef_t; -typedef struct EventGroupDef_t * EventGroupHandle_t; - -/* - * The type that holds event bits always matches TickType_t - therefore the - * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1, - * 32 bits if set to 0. - * - * \defgroup EventBits_t EventBits_t - * \ingroup EventGroup - */ -typedef TickType_t EventBits_t; - -/** - * event_groups.h - *
- EventGroupHandle_t xEventGroupCreate( void );
-
- * - * Create a new event group. - * - * Internally, within the FreeRTOS implementation, event groups use a [small] - * block of memory, in which the event group's structure is stored. If an event - * groups is created using xEventGropuCreate() then the required memory is - * automatically dynamically allocated inside the xEventGroupCreate() function. - * (see http://www.freertos.org/a00111.html). If an event group is created - * using xEventGropuCreateStatic() then the application writer must instead - * provide the memory that will get used by the event group. - * xEventGroupCreateStatic() therefore allows an event group to be created - * without using any dynamic memory allocation. - * - * Although event groups are not related to ticks, for internal implementation - * reasons the number of bits available for use in an event group is dependent - * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If - * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit - * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has - * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store - * event bits within an event group. - * - * @return If the event group was created then a handle to the event group is - * returned. If there was insufficient FreeRTOS heap available to create the - * event group then NULL is returned. See http://www.freertos.org/a00111.html - * - * Example usage: - 
-	// Declare a variable to hold the created event group.
-	EventGroupHandle_t xCreatedEventGroup;
-
-	// Attempt to create the event group.
-	xCreatedEventGroup = xEventGroupCreate();
-
-	// Was the event group created successfully?
-	if( xCreatedEventGroup == NULL )
-	{
-		// The event group was not created because there was insufficient
-		// FreeRTOS heap available.
-	}
-	else
-	{
-		// The event group was created.
-	}
-
- * \defgroup xEventGroupCreate xEventGroupCreate - * \ingroup EventGroup - */ -#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) - EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION; -#endif - -/** - * event_groups.h - *
- EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
-
- * - * Create a new event group. - * - * Internally, within the FreeRTOS implementation, event groups use a [small] - * block of memory, in which the event group's structure is stored. If an event - * groups is created using xEventGropuCreate() then the required memory is - * automatically dynamically allocated inside the xEventGroupCreate() function. - * (see http://www.freertos.org/a00111.html). If an event group is created - * using xEventGropuCreateStatic() then the application writer must instead - * provide the memory that will get used by the event group. - * xEventGroupCreateStatic() therefore allows an event group to be created - * without using any dynamic memory allocation. - * - * Although event groups are not related to ticks, for internal implementation - * reasons the number of bits available for use in an event group is dependent - * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h. If - * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit - * 0 to bit 7). If configUSE_16_BIT_TICKS is set to 0 then each event group has - * 24 usable bits (bit 0 to bit 23). The EventBits_t type is used to store - * event bits within an event group. - * - * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type - * StaticEventGroup_t, which will be then be used to hold the event group's data - * structures, removing the need for the memory to be allocated dynamically. - * - * @return If the event group was created then a handle to the event group is - * returned. If pxEventGroupBuffer was NULL then NULL is returned. - * - * Example usage: - 
-	// StaticEventGroup_t is a publicly accessible structure that has the same
-	// size and alignment requirements as the real event group structure.  It is
-	// provided as a mechanism for applications to know the size of the event
-	// group (which is dependent on the architecture and configuration file
-	// settings) without breaking the strict data hiding policy by exposing the
-	// real event group internals.  This StaticEventGroup_t variable is passed
-	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
-	// the event group's data structures
-	StaticEventGroup_t xEventGroupBuffer;
-
-	// Create the event group without dynamically allocating any memory.
-	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
-
- */ -#if( configSUPPORT_STATIC_ALLOCATION == 1 ) - EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION; -#endif - -/** - * event_groups.h - *
-	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
-										const EventBits_t uxBitsToWaitFor,
-										const BaseType_t xClearOnExit,
-										const BaseType_t xWaitForAllBits,
-										const TickType_t xTicksToWait );
-
- * - * [Potentially] block to wait for one or more bits to be set within a - * previously created event group. - * - * This function cannot be called from an interrupt. - * - * @param xEventGroup The event group in which the bits are being tested. The - * event group must have previously been created using a call to - * xEventGroupCreate(). - * - * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test - * inside the event group. For example, to wait for bit 0 and/or bit 2 set - * uxBitsToWaitFor to 0x05. To wait for bits 0 and/or bit 1 and/or bit 2 set - * uxBitsToWaitFor to 0x07. Etc. - * - * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within - * uxBitsToWaitFor that are set within the event group will be cleared before - * xEventGroupWaitBits() returns if the wait condition was met (if the function - * returns for a reason other than a timeout). If xClearOnExit is set to - * pdFALSE then the bits set in the event group are not altered when the call to - * xEventGroupWaitBits() returns. - * - * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then - * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor - * are set or the specified block time expires. If xWaitForAllBits is set to - * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set - * in uxBitsToWaitFor is set or the specified block time expires. The block - * time is specified by the xTicksToWait parameter. - * - * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait - * for one/all (depending on the xWaitForAllBits value) of the bits specified by - * uxBitsToWaitFor to become set. - * - * @return The value of the event group at the time either the bits being waited - * for became set, or the block time expired. Test the return value to know - * which bits were set. If xEventGroupWaitBits() returned because its timeout - * expired then not all the bits being waited for will be set. If - * xEventGroupWaitBits() returned because the bits it was waiting for were set - * then the returned value is the event group value before any bits were - * automatically cleared in the case that xClearOnExit parameter was set to - * pdTRUE. - * - * Example usage: - 
-   #define BIT_0	( 1 << 0 )
-   #define BIT_4	( 1 << 4 )
-
-   void aFunction( EventGroupHandle_t xEventGroup )
-   {
-   EventBits_t uxBits;
-   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
-
-		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
-		// the event group.  Clear the bits before exiting.
-		uxBits = xEventGroupWaitBits(
-					xEventGroup,	// The event group being tested.
-					BIT_0 | BIT_4,	// The bits within the event group to wait for.
-					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
-					pdFALSE,		// Don't wait for both bits, either bit will do.
-					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
-
-		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
-		{
-			// xEventGroupWaitBits() returned because both bits were set.
-		}
-		else if( ( uxBits & BIT_0 ) != 0 )
-		{
-			// xEventGroupWaitBits() returned because just BIT_0 was set.
-		}
-		else if( ( uxBits & BIT_4 ) != 0 )
-		{
-			// xEventGroupWaitBits() returned because just BIT_4 was set.
-		}
-		else
-		{
-			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
-			// without either BIT_0 or BIT_4 becoming set.
-		}
-   }
-
- * \defgroup xEventGroupWaitBits xEventGroupWaitBits - * \ingroup EventGroup - */ -EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; - -/** - * event_groups.h - *
-	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
-
- * - * Clear bits within an event group. This function cannot be called from an - * interrupt. - * - * @param xEventGroup The event group in which the bits are to be cleared. - * - * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear - * in the event group. For example, to clear bit 3 only, set uxBitsToClear to - * 0x08. To clear bit 3 and bit 0 set uxBitsToClear to 0x09. - * - * @return The value of the event group before the specified bits were cleared. - * - * Example usage: - 
-   #define BIT_0	( 1 << 0 )
-   #define BIT_4	( 1 << 4 )
-
-   void aFunction( EventGroupHandle_t xEventGroup )
-   {
-   EventBits_t uxBits;
-
-		// Clear bit 0 and bit 4 in xEventGroup.
-		uxBits = xEventGroupClearBits(
-								xEventGroup,	// The event group being updated.
-								BIT_0 | BIT_4 );// The bits being cleared.
-
-		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
-		{
-			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
-			// called.  Both will now be clear (not set).
-		}
-		else if( ( uxBits & BIT_0 ) != 0 )
-		{
-			// Bit 0 was set before xEventGroupClearBits() was called.  It will
-			// now be clear.
-		}
-		else if( ( uxBits & BIT_4 ) != 0 )
-		{
-			// Bit 4 was set before xEventGroupClearBits() was called.  It will
-			// now be clear.
-		}
-		else
-		{
-			// Neither bit 0 nor bit 4 were set in the first place.
-		}
-   }
-
- * \defgroup xEventGroupClearBits xEventGroupClearBits - * \ingroup EventGroup - */ -EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; - -/** - * event_groups.h - *
-	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
-
- * - * A version of xEventGroupClearBits() that can be called from an interrupt. - * - * Setting bits in an event group is not a deterministic operation because there - * are an unknown number of tasks that may be waiting for the bit or bits being - * set. FreeRTOS does not allow nondeterministic operations to be performed - * while interrupts are disabled, so protects event groups that are accessed - * from tasks by suspending the scheduler rather than disabling interrupts. As - * a result event groups cannot be accessed directly from an interrupt service - * routine. Therefore xEventGroupClearBitsFromISR() sends a message to the - * timer task to have the clear operation performed in the context of the timer - * task. - * - * @param xEventGroup The event group in which the bits are to be cleared. - * - * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear. - * For example, to clear bit 3 only, set uxBitsToClear to 0x08. To clear bit 3 - * and bit 0 set uxBitsToClear to 0x09. - * - * @return If the request to execute the function was posted successfully then - * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned - * if the timer service queue was full. - * - * Example usage: - 
-   #define BIT_0	( 1 << 0 )
-   #define BIT_4	( 1 << 4 )
-
-   // An event group which it is assumed has already been created by a call to
-   // xEventGroupCreate().
-   EventGroupHandle_t xEventGroup;
-
-   void anInterruptHandler( void )
-   {
-		// Clear bit 0 and bit 4 in xEventGroup.
-		xResult = xEventGroupClearBitsFromISR(
-							xEventGroup,	 // The event group being updated.
-							BIT_0 | BIT_4 ); // The bits being set.
-
-		if( xResult == pdPASS )
-		{
-			// The message was posted successfully.
-		}
-  }
-
- * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR - * \ingroup EventGroup - */ -#if( configUSE_TRACE_FACILITY == 1 ) - BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION; -#else - #define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL ) -#endif - -/** - * event_groups.h - *
-	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
-
- * - * Set bits within an event group. - * This function cannot be called from an interrupt. xEventGroupSetBitsFromISR() - * is a version that can be called from an interrupt. - * - * Setting bits in an event group will automatically unblock tasks that are - * blocked waiting for the bits. - * - * @param xEventGroup The event group in which the bits are to be set. - * - * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. - * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 - * and bit 0 set uxBitsToSet to 0x09. - * - * @return The value of the event group at the time the call to - * xEventGroupSetBits() returns. There are two reasons why the returned value - * might have the bits specified by the uxBitsToSet parameter cleared. First, - * if setting a bit results in a task that was waiting for the bit leaving the - * blocked state then it is possible the bit will be cleared automatically - * (see the xClearBitOnExit parameter of xEventGroupWaitBits()). Second, any - * unblocked (or otherwise Ready state) task that has a priority above that of - * the task that called xEventGroupSetBits() will execute and may change the - * event group value before the call to xEventGroupSetBits() returns. - * - * Example usage: - 
-   #define BIT_0	( 1 << 0 )
-   #define BIT_4	( 1 << 4 )
-
-   void aFunction( EventGroupHandle_t xEventGroup )
-   {
-   EventBits_t uxBits;
-
-		// Set bit 0 and bit 4 in xEventGroup.
-		uxBits = xEventGroupSetBits(
-							xEventGroup,	// The event group being updated.
-							BIT_0 | BIT_4 );// The bits being set.
-
-		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
-		{
-			// Both bit 0 and bit 4 remained set when the function returned.
-		}
-		else if( ( uxBits & BIT_0 ) != 0 )
-		{
-			// Bit 0 remained set when the function returned, but bit 4 was
-			// cleared.  It might be that bit 4 was cleared automatically as a
-			// task that was waiting for bit 4 was removed from the Blocked
-			// state.
-		}
-		else if( ( uxBits & BIT_4 ) != 0 )
-		{
-			// Bit 4 remained set when the function returned, but bit 0 was
-			// cleared.  It might be that bit 0 was cleared automatically as a
-			// task that was waiting for bit 0 was removed from the Blocked
-			// state.
-		}
-		else
-		{
-			// Neither bit 0 nor bit 4 remained set.  It might be that a task
-			// was waiting for both of the bits to be set, and the bits were
-			// cleared as the task left the Blocked state.
-		}
-   }
-
- * \defgroup xEventGroupSetBits xEventGroupSetBits - * \ingroup EventGroup - */ -EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION; - -/** - * event_groups.h - *
-	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
-
- * - * A version of xEventGroupSetBits() that can be called from an interrupt. - * - * Setting bits in an event group is not a deterministic operation because there - * are an unknown number of tasks that may be waiting for the bit or bits being - * set. FreeRTOS does not allow nondeterministic operations to be performed in - * interrupts or from critical sections. Therefore xEventGroupSetBitsFromISR() - * sends a message to the timer task to have the set operation performed in the - * context of the timer task - where a scheduler lock is used in place of a - * critical section. - * - * @param xEventGroup The event group in which the bits are to be set. - * - * @param uxBitsToSet A bitwise value that indicates the bit or bits to set. - * For example, to set bit 3 only, set uxBitsToSet to 0x08. To set bit 3 - * and bit 0 set uxBitsToSet to 0x09. - * - * @param pxHigherPriorityTaskWoken As mentioned above, calling this function - * will result in a message being sent to the timer daemon task. If the - * priority of the timer daemon task is higher than the priority of the - * currently running task (the task the interrupt interrupted) then - * *pxHigherPriorityTaskWoken will be set to pdTRUE by - * xEventGroupSetBitsFromISR(), indicating that a context switch should be - * requested before the interrupt exits. For that reason - * *pxHigherPriorityTaskWoken must be initialised to pdFALSE. See the - * example code below. - * - * @return If the request to execute the function was posted successfully then - * pdPASS is returned, otherwise pdFALSE is returned. pdFALSE will be returned - * if the timer service queue was full. - * - * Example usage: - 
-   #define BIT_0	( 1 << 0 )
-   #define BIT_4	( 1 << 4 )
-
-   // An event group which it is assumed has already been created by a call to
-   // xEventGroupCreate().
-   EventGroupHandle_t xEventGroup;
-
-   void anInterruptHandler( void )
-   {
-   BaseType_t xHigherPriorityTaskWoken, xResult;
-
-		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
-		xHigherPriorityTaskWoken = pdFALSE;
-
-		// Set bit 0 and bit 4 in xEventGroup.
-		xResult = xEventGroupSetBitsFromISR(
-							xEventGroup,	// The event group being updated.
-							BIT_0 | BIT_4   // The bits being set.
-							&xHigherPriorityTaskWoken );
-
-		// Was the message posted successfully?
-		if( xResult == pdPASS )
-		{
-			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
-			// switch should be requested.  The macro used is port specific and
-			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
-			// refer to the documentation page for the port being used.
-			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-		}
-  }
-
- * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR - * \ingroup EventGroup - */ -#if( configUSE_TRACE_FACILITY == 1 ) - BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION; -#else - #define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken ) -#endif - -/** - * event_groups.h - *
-	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
-									const EventBits_t uxBitsToSet,
-									const EventBits_t uxBitsToWaitFor,
-									TickType_t xTicksToWait );
-
- * - * Atomically set bits within an event group, then wait for a combination of - * bits to be set within the same event group. This functionality is typically - * used to synchronise multiple tasks, where each task has to wait for the other - * tasks to reach a synchronisation point before proceeding. - * - * This function cannot be used from an interrupt. - * - * The function will return before its block time expires if the bits specified - * by the uxBitsToWait parameter are set, or become set within that time. In - * this case all the bits specified by uxBitsToWait will be automatically - * cleared before the function returns. - * - * @param xEventGroup The event group in which the bits are being tested. The - * event group must have previously been created using a call to - * xEventGroupCreate(). - * - * @param uxBitsToSet The bits to set in the event group before determining - * if, and possibly waiting for, all the bits specified by the uxBitsToWait - * parameter are set. - * - * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test - * inside the event group. For example, to wait for bit 0 and bit 2 set - * uxBitsToWaitFor to 0x05. To wait for bits 0 and bit 1 and bit 2 set - * uxBitsToWaitFor to 0x07. Etc. - * - * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait - * for all of the bits specified by uxBitsToWaitFor to become set. - * - * @return The value of the event group at the time either the bits being waited - * for became set, or the block time expired. Test the return value to know - * which bits were set. If xEventGroupSync() returned because its timeout - * expired then not all the bits being waited for will be set. If - * xEventGroupSync() returned because all the bits it was waiting for were - * set then the returned value is the event group value before any bits were - * automatically cleared. - * - * Example usage: - 
- // Bits used by the three tasks.
- #define TASK_0_BIT		( 1 << 0 )
- #define TASK_1_BIT		( 1 << 1 )
- #define TASK_2_BIT		( 1 << 2 )
-
- #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
-
- // Use an event group to synchronise three tasks.  It is assumed this event
- // group has already been created elsewhere.
- EventGroupHandle_t xEventBits;
-
- void vTask0( void *pvParameters )
- {
- EventBits_t uxReturn;
- TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
-
-	 for( ;; )
-	 {
-		// Perform task functionality here.
-
-		// Set bit 0 in the event flag to note this task has reached the
-		// sync point.  The other two tasks will set the other two bits defined
-		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
-		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
-		// for this to happen.
-		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
-
-		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
-		{
-			// All three tasks reached the synchronisation point before the call
-			// to xEventGroupSync() timed out.
-		}
-	}
- }
-
- void vTask1( void *pvParameters )
- {
-	 for( ;; )
-	 {
-		// Perform task functionality here.
-
-		// Set bit 1 in the event flag to note this task has reached the
-		// synchronisation point.  The other two tasks will set the other two
-		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
-		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
-		// indefinitely for this to happen.
-		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
-
-		// xEventGroupSync() was called with an indefinite block time, so
-		// this task will only reach here if the syncrhonisation was made by all
-		// three tasks, so there is no need to test the return value.
-	 }
- }
-
- void vTask2( void *pvParameters )
- {
-	 for( ;; )
-	 {
-		// Perform task functionality here.
-
-		// Set bit 2 in the event flag to note this task has reached the
-		// synchronisation point.  The other two tasks will set the other two
-		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
-		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
-		// indefinitely for this to happen.
-		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
-
-		// xEventGroupSync() was called with an indefinite block time, so
-		// this task will only reach here if the syncrhonisation was made by all
-		// three tasks, so there is no need to test the return value.
-	}
- }
-
-
- * \defgroup xEventGroupSync xEventGroupSync - * \ingroup EventGroup - */ -EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION; - - -/** - * event_groups.h - *
-	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
-
- * - * Returns the current value of the bits in an event group. This function - * cannot be used from an interrupt. - * - * @param xEventGroup The event group being queried. - * - * @return The event group bits at the time xEventGroupGetBits() was called. - * - * \defgroup xEventGroupGetBits xEventGroupGetBits - * \ingroup EventGroup - */ -#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 ) - -/** - * event_groups.h - *
-	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
-
- * - * A version of xEventGroupGetBits() that can be called from an ISR. - * - * @param xEventGroup The event group being queried. - * - * @return The event group bits at the time xEventGroupGetBitsFromISR() was called. - * - * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR - * \ingroup EventGroup - */ -EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; - -/** - * event_groups.h - *
-	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
-
- * - * Delete an event group that was previously created by a call to - * xEventGroupCreate(). Tasks that are blocked on the event group will be - * unblocked and obtain 0 as the event group's value. - * - * @param xEventGroup The event group being deleted. - */ -void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION; - -/* For internal use only. */ -void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION; -void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION; - - -#if (configUSE_TRACE_FACILITY == 1) - UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION; - void vEventGroupSetNumber( void* xEventGroup, UBaseType_t uxEventGroupNumber ) PRIVILEGED_FUNCTION; -#endif - -#ifdef __cplusplus -} -#endif - -#endif /* EVENT_GROUPS_H */ - - diff --git a/FreeRTOS/Source/include/list.h b/FreeRTOS/Source/include/list.h deleted file mode 100755 index 2fb6775..0000000 --- a/FreeRTOS/Source/include/list.h +++ /dev/null @@ -1,412 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - -/* - * This is the list implementation used by the scheduler. While it is tailored - * heavily for the schedulers needs, it is also available for use by - * application code. - * - * list_ts can only store pointers to list_item_ts. Each ListItem_t contains a - * numeric value (xItemValue). Most of the time the lists are sorted in - * descending item value order. - * - * Lists are created already containing one list item. The value of this - * item is the maximum possible that can be stored, it is therefore always at - * the end of the list and acts as a marker. The list member pxHead always - * points to this marker - even though it is at the tail of the list. This - * is because the tail contains a wrap back pointer to the true head of - * the list. - * - * In addition to it's value, each list item contains a pointer to the next - * item in the list (pxNext), a pointer to the list it is in (pxContainer) - * and a pointer to back to the object that contains it. These later two - * pointers are included for efficiency of list manipulation. There is - * effectively a two way link between the object containing the list item and - * the list item itself. - * - * - * \page ListIntroduction List Implementation - * \ingroup FreeRTOSIntro - */ - -#ifndef INC_FREERTOS_H - #error FreeRTOS.h must be included before list.h -#endif - -#ifndef LIST_H -#define LIST_H - -/* - * The list structure members are modified from within interrupts, and therefore - * by rights should be declared volatile. However, they are only modified in a - * functionally atomic way (within critical sections of with the scheduler - * suspended) and are either passed by reference into a function or indexed via - * a volatile variable. Therefore, in all use cases tested so far, the volatile - * qualifier can be omitted in order to provide a moderate performance - * improvement without adversely affecting functional behaviour. The assembly - * instructions generated by the IAR, ARM and GCC compilers when the respective - * compiler's options were set for maximum optimisation has been inspected and - * deemed to be as intended. That said, as compiler technology advances, and - * especially if aggressive cross module optimisation is used (a use case that - * has not been exercised to any great extend) then it is feasible that the - * volatile qualifier will be needed for correct optimisation. It is expected - * that a compiler removing essential code because, without the volatile - * qualifier on the list structure members and with aggressive cross module - * optimisation, the compiler deemed the code unnecessary will result in - * complete and obvious failure of the scheduler. If this is ever experienced - * then the volatile qualifier can be inserted in the relevant places within the - * list structures by simply defining configLIST_VOLATILE to volatile in - * FreeRTOSConfig.h (as per the example at the bottom of this comment block). - * If configLIST_VOLATILE is not defined then the preprocessor directives below - * will simply #define configLIST_VOLATILE away completely. - * - * To use volatile list structure members then add the following line to - * FreeRTOSConfig.h (without the quotes): - * "#define configLIST_VOLATILE volatile" - */ -#ifndef configLIST_VOLATILE - #define configLIST_VOLATILE -#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */ - -#ifdef __cplusplus -extern "C" { -#endif - -/* Macros that can be used to place known values within the list structures, -then check that the known values do not get corrupted during the execution of -the application. These may catch the list data structures being overwritten in -memory. They will not catch data errors caused by incorrect configuration or -use of FreeRTOS.*/ -#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 ) - /* Define the macros to do nothing. */ - #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE - #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE - #define listFIRST_LIST_INTEGRITY_CHECK_VALUE - #define listSECOND_LIST_INTEGRITY_CHECK_VALUE - #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) - #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) - #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) - #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) - #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) - #define listTEST_LIST_INTEGRITY( pxList ) -#else - /* Define macros that add new members into the list structures. */ - #define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue1; - #define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE TickType_t xListItemIntegrityValue2; - #define listFIRST_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue1; - #define listSECOND_LIST_INTEGRITY_CHECK_VALUE TickType_t xListIntegrityValue2; - - /* Define macros that set the new structure members to known values. */ - #define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE - #define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem ) ( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE - #define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList ) ( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE - #define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList ) ( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE - - /* Define macros that will assert if one of the structure members does not - contain its expected value. */ - #define listTEST_LIST_ITEM_INTEGRITY( pxItem ) configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) - #define listTEST_LIST_INTEGRITY( pxList ) configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) ) -#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */ - - -/* - * Definition of the only type of object that a list can contain. - */ -struct xLIST; -struct xLIST_ITEM -{ - listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ - configLIST_VOLATILE TickType_t xItemValue; /*< The value being listed. In most cases this is used to sort the list in descending order. */ - struct xLIST_ITEM * configLIST_VOLATILE pxNext; /*< Pointer to the next ListItem_t in the list. */ - struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; /*< Pointer to the previous ListItem_t in the list. */ - void * pvOwner; /*< Pointer to the object (normally a TCB) that contains the list item. There is therefore a two way link between the object containing the list item and the list item itself. */ - struct xLIST * configLIST_VOLATILE pxContainer; /*< Pointer to the list in which this list item is placed (if any). */ - listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ -}; -typedef struct xLIST_ITEM ListItem_t; /* For some reason lint wants this as two separate definitions. */ - -struct xMINI_LIST_ITEM -{ - listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ - configLIST_VOLATILE TickType_t xItemValue; - struct xLIST_ITEM * configLIST_VOLATILE pxNext; - struct xLIST_ITEM * configLIST_VOLATILE pxPrevious; -}; -typedef struct xMINI_LIST_ITEM MiniListItem_t; - -/* - * Definition of the type of queue used by the scheduler. - */ -typedef struct xLIST -{ - listFIRST_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ - volatile UBaseType_t uxNumberOfItems; - ListItem_t * configLIST_VOLATILE pxIndex; /*< Used to walk through the list. Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */ - MiniListItem_t xListEnd; /*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */ - listSECOND_LIST_INTEGRITY_CHECK_VALUE /*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */ -} List_t; - -/* - * Access macro to set the owner of a list item. The owner of a list item - * is the object (usually a TCB) that contains the list item. - * - * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner ) ( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) ) - -/* - * Access macro to get the owner of a list item. The owner of a list item - * is the object (usually a TCB) that contains the list item. - * - * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER - * \ingroup LinkedList - */ -#define listGET_LIST_ITEM_OWNER( pxListItem ) ( ( pxListItem )->pvOwner ) - -/* - * Access macro to set the value of the list item. In most cases the value is - * used to sort the list in descending order. - * - * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listSET_LIST_ITEM_VALUE( pxListItem, xValue ) ( ( pxListItem )->xItemValue = ( xValue ) ) - -/* - * Access macro to retrieve the value of the list item. The value can - * represent anything - for example the priority of a task, or the time at - * which a task should be unblocked. - * - * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listGET_LIST_ITEM_VALUE( pxListItem ) ( ( pxListItem )->xItemValue ) - -/* - * Access macro to retrieve the value of the list item at the head of a given - * list. - * - * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE - * \ingroup LinkedList - */ -#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext->xItemValue ) - -/* - * Return the list item at the head of the list. - * - * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY - * \ingroup LinkedList - */ -#define listGET_HEAD_ENTRY( pxList ) ( ( ( pxList )->xListEnd ).pxNext ) - -/* - * Return the list item at the head of the list. - * - * \page listGET_NEXT listGET_NEXT - * \ingroup LinkedList - */ -#define listGET_NEXT( pxListItem ) ( ( pxListItem )->pxNext ) - -/* - * Return the list item that marks the end of the list - * - * \page listGET_END_MARKER listGET_END_MARKER - * \ingroup LinkedList - */ -#define listGET_END_MARKER( pxList ) ( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) ) - -/* - * Access macro to determine if a list contains any items. The macro will - * only have the value true if the list is empty. - * - * \page listLIST_IS_EMPTY listLIST_IS_EMPTY - * \ingroup LinkedList - */ -#define listLIST_IS_EMPTY( pxList ) ( ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) ? pdTRUE : pdFALSE ) - -/* - * Access macro to return the number of items in the list. - */ -#define listCURRENT_LIST_LENGTH( pxList ) ( ( pxList )->uxNumberOfItems ) - -/* - * Access function to obtain the owner of the next entry in a list. - * - * The list member pxIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list - * and returns that entry's pxOwner parameter. Using multiple calls to this - * function it is therefore possible to move through every item contained in - * a list. - * - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxTCB pxTCB is set to the address of the owner of the next list item. - * @param pxList The list from which the next item owner is to be returned. - * - * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList ) \ -{ \ -List_t * const pxConstList = ( pxList ); \ - /* Increment the index to the next item and return the item, ensuring */ \ - /* we don't return the marker used at the end of the list. */ \ - ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ - if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) ) \ - { \ - ( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext; \ - } \ - ( pxTCB ) = ( pxConstList )->pxIndex->pvOwner; \ -} - - -/* - * Access function to obtain the owner of the first entry in a list. Lists - * are normally sorted in ascending item value order. - * - * This function returns the pxOwner member of the first item in the list. - * The pxOwner parameter of a list item is a pointer to the object that owns - * the list item. In the scheduler this is normally a task control block. - * The pxOwner parameter effectively creates a two way link between the list - * item and its owner. - * - * @param pxList The list from which the owner of the head item is to be - * returned. - * - * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY - * \ingroup LinkedList - */ -#define listGET_OWNER_OF_HEAD_ENTRY( pxList ) ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner ) - -/* - * Check to see if a list item is within a list. The list item maintains a - * "container" pointer that points to the list it is in. All this macro does - * is check to see if the container and the list match. - * - * @param pxList The list we want to know if the list item is within. - * @param pxListItem The list item we want to know if is in the list. - * @return pdTRUE if the list item is in the list, otherwise pdFALSE. - */ -#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( ( pxListItem )->pxContainer == ( pxList ) ) ? ( pdTRUE ) : ( pdFALSE ) ) - -/* - * Return the list a list item is contained within (referenced from). - * - * @param pxListItem The list item being queried. - * @return A pointer to the List_t object that references the pxListItem - */ -#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pxContainer ) - -/* - * This provides a crude means of knowing if a list has been initialised, as - * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise() - * function. - */ -#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY ) - -/* - * Must be called before a list is used! This initialises all the members - * of the list structure and inserts the xListEnd item into the list as a - * marker to the back of the list. - * - * @param pxList Pointer to the list being initialised. - * - * \page vListInitialise vListInitialise - * \ingroup LinkedList - */ -void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION; - -/* - * Must be called before a list item is used. This sets the list container to - * null so the item does not think that it is already contained in a list. - * - * @param pxItem Pointer to the list item being initialised. - * - * \page vListInitialiseItem vListInitialiseItem - * \ingroup LinkedList - */ -void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION; - -/* - * Insert a list item into a list. The item will be inserted into the list in - * a position determined by its item value (descending item value order). - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The item that is to be placed in the list. - * - * \page vListInsert vListInsert - * \ingroup LinkedList - */ -void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; - -/* - * Insert a list item into a list. The item will be inserted in a position - * such that it will be the last item within the list returned by multiple - * calls to listGET_OWNER_OF_NEXT_ENTRY. - * - * The list member pxIndex is used to walk through a list. Calling - * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list. - * Placing an item in a list using vListInsertEnd effectively places the item - * in the list position pointed to by pxIndex. This means that every other - * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before - * the pxIndex parameter again points to the item being inserted. - * - * @param pxList The list into which the item is to be inserted. - * - * @param pxNewListItem The list item to be inserted into the list. - * - * \page vListInsertEnd vListInsertEnd - * \ingroup LinkedList - */ -void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION; - -/* - * Remove an item from a list. The list item has a pointer to the list that - * it is in, so only the list item need be passed into the function. - * - * @param uxListRemove The item to be removed. The item will remove itself from - * the list pointed to by it's pxContainer parameter. - * - * @return The number of items that remain in the list after the list item has - * been removed. - * - * \page uxListRemove uxListRemove - * \ingroup LinkedList - */ -UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION; - -#ifdef __cplusplus -} -#endif - -#endif - diff --git a/FreeRTOS/Source/include/message_buffer.h b/FreeRTOS/Source/include/message_buffer.h deleted file mode 100755 index cfa08cb..0000000 --- a/FreeRTOS/Source/include/message_buffer.h +++ /dev/null @@ -1,799 +0,0 @@ -/* - * FreeRTOS Kernel V10.2.1 - * Copyright (C) 2019 Amazon.com, Inc. or its affiliates. All Rights Reserved. - * - * Permission is hereby granted, free of charge, to any person obtaining a copy of - * this software and associated documentation files (the "Software"), to deal in - * the Software without restriction, including without limitation the rights to - * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of - * the Software, and to permit persons to whom the Software is furnished to do so, - * subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in all - * copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS - * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR - * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER - * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN - * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. - * - * http://www.FreeRTOS.org - * http://aws.amazon.com/freertos - * - * 1 tab == 4 spaces! - */ - - -/* - * Message buffers build functionality on top of FreeRTOS stream buffers. - * Whereas stream buffers are used to send a continuous stream of data from one - * task or interrupt to another, message buffers are used to send variable - * length discrete messages from one task or interrupt to another. Their - * implementation is light weight, making them particularly suited for interrupt - * to task and core to core communication scenarios. - * - * ***NOTE***: Uniquely among FreeRTOS objects, the stream buffer - * implementation (so also the message buffer implementation, as message buffers - * are built on top of stream buffers) assumes there is only one task or - * interrupt that will write to the buffer (the writer), and only one task or - * interrupt that will read from the buffer (the reader). It is safe for the - * writer and reader to be different tasks or interrupts, but, unlike other - * FreeRTOS objects, it is not safe to have multiple different writers or - * multiple different readers. If there are to be multiple different writers - * then the application writer must place each call to a writing API function - * (such as xMessageBufferSend()) inside a critical section and set the send - * block time to 0. Likewise, if there are to be multiple different readers - * then the application writer must place each call to a reading API function - * (such as xMessageBufferRead()) inside a critical section and set the receive - * timeout to 0. - * - * Message buffers hold variable length messages. To enable that, when a - * message is written to the message buffer an additional sizeof( size_t ) bytes - * are also written to store the message's length (that happens internally, with - * the API function). sizeof( size_t ) is typically 4 bytes on a 32-bit - * architecture, so writing a 10 byte message to a message buffer on a 32-bit - * architecture will actually reduce the available space in the message buffer - * by 14 bytes (10 byte are used by the message, and 4 bytes to hold the length - * of the message). - */ - -#ifndef FREERTOS_MESSAGE_BUFFER_H -#define FREERTOS_MESSAGE_BUFFER_H - -/* Message buffers are built onto of stream buffers. */ -#include "stream_buffer.h" - -#if defined( __cplusplus ) -extern "C" { -#endif - -/** - * Type by which message buffers are referenced. For example, a call to - * xMessageBufferCreate() returns an MessageBufferHandle_t variable that can - * then be used as a parameter to xMessageBufferSend(), xMessageBufferReceive(), - * etc. - */ -typedef void * MessageBufferHandle_t; - -/*-----------------------------------------------------------*/ - -/** - * message_buffer.h - * -
-MessageBufferHandle_t xMessageBufferCreate( size_t xBufferSizeBytes );
-
- * - * Creates a new message buffer using dynamically allocated memory. See - * xMessageBufferCreateStatic() for a version that uses statically allocated - * memory (memory that is allocated at compile time). - * - * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in - * FreeRTOSConfig.h for xMessageBufferCreate() to be available. - * - * @param xBufferSizeBytes The total number of bytes (not messages) the message - * buffer will be able to hold at any one time. When a message is written to - * the message buffer an additional sizeof( size_t ) bytes are also written to - * store the message's length. sizeof( size_t ) is typically 4 bytes on a - * 32-bit architecture, so on most 32-bit architectures a 10 byte message will - * take up 14 bytes of message buffer space. - * - * @return If NULL is returned, then the message buffer cannot be created - * because there is insufficient heap memory available for FreeRTOS to allocate - * the message buffer data structures and storage area. A non-NULL value being - * returned indicates that the message buffer has been created successfully - - * the returned value should be stored as the handle to the created message - * buffer. - * - * Example use: -
-
-void vAFunction( void )
-{
-MessageBufferHandle_t xMessageBuffer;
-const size_t xMessageBufferSizeBytes = 100;
-
-    // Create a message buffer that can hold 100 bytes.  The memory used to hold
-    // both the message buffer structure and the messages themselves is allocated
-    // dynamically.  Each message added to the buffer consumes an additional 4
-    // bytes which are used to hold the lengh of the message.
-    xMessageBuffer = xMessageBufferCreate( xMessageBufferSizeBytes );
-
-    if( xMessageBuffer == NULL )
-    {
-        // There was not enough heap memory space available to create the
-        // message buffer.
-    }
-    else
-    {
-        // The message buffer was created successfully and can now be used.
-    }
-
-
- * \defgroup xMessageBufferCreate xMessageBufferCreate - * \ingroup MessageBufferManagement - */ -#define xMessageBufferCreate( xBufferSizeBytes ) ( MessageBufferHandle_t ) xStreamBufferGenericCreate( xBufferSizeBytes, ( size_t ) 0, pdTRUE ) - -/** - * message_buffer.h - * -
-MessageBufferHandle_t xMessageBufferCreateStatic( size_t xBufferSizeBytes,
-                                                  uint8_t *pucMessageBufferStorageArea,
-                                                  StaticMessageBuffer_t *pxStaticMessageBuffer );
-
- * Creates a new message buffer using statically allocated memory. See - * xMessageBufferCreate() for a version that uses dynamically allocated memory. - * - * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the - * pucMessageBufferStorageArea parameter. When a message is written to the - * message buffer an additional sizeof( size_t ) bytes are also written to store - * the message's length. sizeof( size_t ) is typically 4 bytes on a 32-bit - * architecture, so on most 32-bit architecture a 10 byte message will take up - * 14 bytes of message buffer space. The maximum number of bytes that can be - * stored in the message buffer is actually (xBufferSizeBytes - 1). - * - * @param pucMessageBufferStorageArea Must point to a uint8_t array that is at - * least xBufferSizeBytes + 1 big. This is the array to which messages are - * copied when they are written to the message buffer. - * - * @param pxStaticMessageBuffer Must point to a variable of type - * StaticMessageBuffer_t, which will be used to hold the message buffer's data - * structure. - * - * @return If the message buffer is created successfully then a handle to the - * created message buffer is returned. If either pucMessageBufferStorageArea or - * pxStaticmessageBuffer are NULL then NULL is returned. - * - * Example use: -
-
-// Used to dimension the array used to hold the messages.  The available space
-// will actually be one less than this, so 999.
-#define STORAGE_SIZE_BYTES 1000
-
-// Defines the memory that will actually hold the messages within the message
-// buffer.
-static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
-
-// The variable used to hold the message buffer structure.
-StaticMessageBuffer_t xMessageBufferStruct;
-
-void MyFunction( void )
-{
-MessageBufferHandle_t xMessageBuffer;
-
-    xMessageBuffer = xMessageBufferCreateStatic( sizeof( ucBufferStorage ),
-                                                 ucBufferStorage,
-                                                 &xMessageBufferStruct );
-
-    // As neither the pucMessageBufferStorageArea or pxStaticMessageBuffer
-    // parameters were NULL, xMessageBuffer will not be NULL, and can be used to
-    // reference the created message buffer in other message buffer API calls.
-
-    // Other code that uses the message buffer can go here.
-}
-
-
- * \defgroup xMessageBufferCreateStatic xMessageBufferCreateStatic - * \ingroup MessageBufferManagement - */ -#define xMessageBufferCreateStatic( xBufferSizeBytes, pucMessageBufferStorageArea, pxStaticMessageBuffer ) ( MessageBufferHandle_t ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, 0, pdTRUE, pucMessageBufferStorageArea, pxStaticMessageBuffer ) - -/** - * message_buffer.h - * -
-size_t xMessageBufferSend( MessageBufferHandle_t xMessageBuffer,
-                           const void *pvTxData,
-                           size_t xDataLengthBytes,
-                           TickType_t xTicksToWait );
-
- *
- * Sends a discrete message to the message buffer.  The message can be any
- * length that fits within the buffer's free space, and is copied into the
- * buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xMessageBufferSend() to write to a message buffer from a task.  Use
- * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
- * service routine (ISR).
- *
- * @param xMessageBuffer The handle of the message buffer to which a message is
- * being sent.
- *
- * @param pvTxData A pointer to the message that is to be copied into the
- * message buffer.
- *
- * @param xDataLengthBytes The length of the message.  That is, the number of
- * bytes to copy from pvTxData into the message buffer.  When a message is
- * written to the message buffer an additional sizeof( size_t ) bytes are also
- * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
- * on a 32-bit architecture, so on most 32-bit architecture setting
- * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
- * bytes (20 bytes of message data and 4 bytes to hold the message length).
- *
- * @param xTicksToWait The maximum amount of time the calling task should remain
- * in the Blocked state to wait for enough space to become available in the
- * message buffer, should the message buffer have insufficient space when
- * xMessageBufferSend() is called.  The calling task will never block if
- * xTicksToWait is zero.  The block time is specified in tick periods, so the
- * absolute time it represents is dependent on the tick frequency.  The macro
- * pdMS_TO_TICKS() can be used to convert a time specified in milliseconds into
- * a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will cause
- * the task to wait indefinitely (without timing out), provided
- * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
- * CPU time when they are in the Blocked state.
- *
- * @return The number of bytes written to the message buffer.  If the call to
- * xMessageBufferSend() times out before there was enough space to write the
- * message into the message buffer then zero is returned.  If the call did not
- * time out then xDataLengthBytes is returned.
- *
- * Example use:
-
-void vAFunction( MessageBufferHandle_t xMessageBuffer )
-{
-size_t xBytesSent;
-uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
-char *pcStringToSend = "String to send";
-const TickType_t x100ms = pdMS_TO_TICKS( 100 );
-
-    // Send an array to the message buffer, blocking for a maximum of 100ms to
-    // wait for enough space to be available in the message buffer.
-    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
-
-    if( xBytesSent != sizeof( ucArrayToSend ) )
-    {
-        // The call to xMessageBufferSend() times out before there was enough
-        // space in the buffer for the data to be written.
-    }
-
-    // Send the string to the message buffer.  Return immediately if there is
-    // not enough space in the buffer.
-    xBytesSent = xMessageBufferSend( xMessageBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
-
-    if( xBytesSent != strlen( pcStringToSend ) )
-    {
-        // The string could not be added to the message buffer because there was
-        // not enough free space in the buffer.
-    }
-}
-

- * \defgroup xMessageBufferSend xMessageBufferSend
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferSend( xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait ) xStreamBufferSend( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, xTicksToWait )
-
-/**
- * message_buffer.h
- *
-
-size_t xMessageBufferSendFromISR( MessageBufferHandle_t xMessageBuffer,
-                                  const void *pvTxData,
-                                  size_t xDataLengthBytes,
-                                  BaseType_t *pxHigherPriorityTaskWoken );
-
- *
- * Interrupt safe version of the API function that sends a discrete message to
- * the message buffer.  The message can be any length that fits within the
- * buffer's free space, and is copied into the buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xMessageBufferSend() to write to a message buffer from a task.  Use
- * xMessageBufferSendFromISR() to write to a message buffer from an interrupt
- * service routine (ISR).
- *
- * @param xMessageBuffer The handle of the message buffer to which a message is
- * being sent.
- *
- * @param pvTxData A pointer to the message that is to be copied into the
- * message buffer.
- *
- * @param xDataLengthBytes The length of the message.  That is, the number of
- * bytes to copy from pvTxData into the message buffer.  When a message is
- * written to the message buffer an additional sizeof( size_t ) bytes are also
- * written to store the message's length.  sizeof( size_t ) is typically 4 bytes
- * on a 32-bit architecture, so on most 32-bit architecture setting
- * xDataLengthBytes to 20 will reduce the free space in the message buffer by 24
- * bytes (20 bytes of message data and 4 bytes to hold the message length).
- *
- * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
- * have a task blocked on it waiting for data.  Calling
- * xMessageBufferSendFromISR() can make data available, and so cause a task that
- * was waiting for data to leave the Blocked state.  If calling
- * xMessageBufferSendFromISR() causes a task to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently executing task (the
- * task that was interrupted), then, internally, xMessageBufferSendFromISR()
- * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
- * xMessageBufferSendFromISR() sets this value to pdTRUE, then normally a
- * context switch should be performed before the interrupt is exited.  This will
- * ensure that the interrupt returns directly to the highest priority Ready
- * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
- * is passed into the function.  See the code example below for an example.
- *
- * @return The number of bytes actually written to the message buffer.  If the
- * message buffer didn't have enough free space for the message to be stored
- * then 0 is returned, otherwise xDataLengthBytes is returned.
- *
- * Example use:
-
-// A message buffer that has already been created.
-MessageBufferHandle_t xMessageBuffer;
-
-void vAnInterruptServiceRoutine( void )
-{
-size_t xBytesSent;
-char *pcStringToSend = "String to send";
-BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
-
-    // Attempt to send the string to the message buffer.
-    xBytesSent = xMessageBufferSendFromISR( xMessageBuffer,
-                                            ( void * ) pcStringToSend,
-                                            strlen( pcStringToSend ),
-                                            &xHigherPriorityTaskWoken );
-
-    if( xBytesSent != strlen( pcStringToSend ) )
-    {
-        // The string could not be added to the message buffer because there was
-        // not enough free space in the buffer.
-    }
-
-    // If xHigherPriorityTaskWoken was set to pdTRUE inside
-    // xMessageBufferSendFromISR() then a task that has a priority above the
-    // priority of the currently executing task was unblocked and a context
-    // switch should be performed to ensure the ISR returns to the unblocked
-    // task.  In most FreeRTOS ports this is done by simply passing
-    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
-    // variables value, and perform the context switch if necessary.  Check the
-    // documentation for the port in use for port specific instructions.
-    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-}
-

- * \defgroup xMessageBufferSendFromISR xMessageBufferSendFromISR
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferSendFromISR( xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferSendFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvTxData, xDataLengthBytes, pxHigherPriorityTaskWoken )
-
-/**
- * message_buffer.h
- *
-
-size_t xMessageBufferReceive( MessageBufferHandle_t xMessageBuffer,
-                              void *pvRxData,
-                              size_t xBufferLengthBytes,
-                              TickType_t xTicksToWait );
-

- *
- * Receives a discrete message from a message buffer.  Messages can be of
- * variable length and are copied out of the buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
- * xMessageBufferReceiveFromISR() to read from a message buffer from an
- * interrupt service routine (ISR).
- *
- * @param xMessageBuffer The handle of the message buffer from which a message
- * is being received.
- *
- * @param pvRxData A pointer to the buffer into which the received message is
- * to be copied.
- *
- * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
- * parameter.  This sets the maximum length of the message that can be received.
- * If xBufferLengthBytes is too small to hold the next message then the message
- * will be left in the message buffer and 0 will be returned.
- *
- * @param xTicksToWait The maximum amount of time the task should remain in the
- * Blocked state to wait for a message, should the message buffer be empty.
- * xMessageBufferReceive() will return immediately if xTicksToWait is zero and
- * the message buffer is empty.  The block time is specified in tick periods, so
- * the absolute time it represents is dependent on the tick frequency.  The
- * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
- * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
- * cause the task to wait indefinitely (without timing out), provided
- * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  Tasks do not use any
- * CPU time when they are in the Blocked state.
- *
- * @return The length, in bytes, of the message read from the message buffer, if
- * any.  If xMessageBufferReceive() times out before a message became available
- * then zero is returned.  If the length of the message is greater than
- * xBufferLengthBytes then the message will be left in the message buffer and
- * zero is returned.
- *
- * Example use:
-
-void vAFunction( MessageBuffer_t xMessageBuffer )
-{
-uint8_t ucRxData[ 20 ];
-size_t xReceivedBytes;
-const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
-
-    // Receive the next message from the message buffer.  Wait in the Blocked
-    // state (so not using any CPU processing time) for a maximum of 100ms for
-    // a message to become available.
-    xReceivedBytes = xMessageBufferReceive( xMessageBuffer,
-                                            ( void * ) ucRxData,
-                                            sizeof( ucRxData ),
-                                            xBlockTime );
-
-    if( xReceivedBytes > 0 )
-    {
-        // A ucRxData contains a message that is xReceivedBytes long.  Process
-        // the message here....
-    }
-}
-

- * \defgroup xMessageBufferReceive xMessageBufferReceive
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferReceive( xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait ) xStreamBufferReceive( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, xTicksToWait )
-
-
-/**
- * message_buffer.h
- *
-
-size_t xMessageBufferReceiveFromISR( MessageBufferHandle_t xMessageBuffer,
-                                     void *pvRxData,
-                                     size_t xBufferLengthBytes,
-                                     BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * An interrupt safe version of the API function that receives a discrete
- * message from a message buffer.  Messages can be of variable length and are
- * copied out of the buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xMessageBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xMessageBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xMessageBufferReceive() to read from a message buffer from a task.  Use
- * xMessageBufferReceiveFromISR() to read from a message buffer from an
- * interrupt service routine (ISR).
- *
- * @param xMessageBuffer The handle of the message buffer from which a message
- * is being received.
- *
- * @param pvRxData A pointer to the buffer into which the received message is
- * to be copied.
- *
- * @param xBufferLengthBytes The length of the buffer pointed to by the pvRxData
- * parameter.  This sets the maximum length of the message that can be received.
- * If xBufferLengthBytes is too small to hold the next message then the message
- * will be left in the message buffer and 0 will be returned.
- *
- * @param pxHigherPriorityTaskWoken  It is possible that a message buffer will
- * have a task blocked on it waiting for space to become available.  Calling
- * xMessageBufferReceiveFromISR() can make space available, and so cause a task
- * that is waiting for space to leave the Blocked state.  If calling
- * xMessageBufferReceiveFromISR() causes a task to leave the Blocked state, and
- * the unblocked task has a priority higher than the currently executing task
- * (the task that was interrupted), then, internally,
- * xMessageBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
- * If xMessageBufferReceiveFromISR() sets this value to pdTRUE, then normally a
- * context switch should be performed before the interrupt is exited.  That will
- * ensure the interrupt returns directly to the highest priority Ready state
- * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
- * passed into the function.  See the code example below for an example.
- *
- * @return The length, in bytes, of the message read from the message buffer, if
- * any.
- *
- * Example use:
-
-// A message buffer that has already been created.
-MessageBuffer_t xMessageBuffer;
-
-void vAnInterruptServiceRoutine( void )
-{
-uint8_t ucRxData[ 20 ];
-size_t xReceivedBytes;
-BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
-
-    // Receive the next message from the message buffer.
-    xReceivedBytes = xMessageBufferReceiveFromISR( xMessageBuffer,
-                                                  ( void * ) ucRxData,
-                                                  sizeof( ucRxData ),
-                                                  &xHigherPriorityTaskWoken );
-
-    if( xReceivedBytes > 0 )
-    {
-        // A ucRxData contains a message that is xReceivedBytes long.  Process
-        // the message here....
-    }
-
-    // If xHigherPriorityTaskWoken was set to pdTRUE inside
-    // xMessageBufferReceiveFromISR() then a task that has a priority above the
-    // priority of the currently executing task was unblocked and a context
-    // switch should be performed to ensure the ISR returns to the unblocked
-    // task.  In most FreeRTOS ports this is done by simply passing
-    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
-    // variables value, and perform the context switch if necessary.  Check the
-    // documentation for the port in use for port specific instructions.
-    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-}
-

- * \defgroup xMessageBufferReceiveFromISR xMessageBufferReceiveFromISR
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferReceiveFromISR( xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken ) xStreamBufferReceiveFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pvRxData, xBufferLengthBytes, pxHigherPriorityTaskWoken )
-
-/**
- * message_buffer.h
- *
-
-void vMessageBufferDelete( MessageBufferHandle_t xMessageBuffer );
-

- *
- * Deletes a message buffer that was previously created using a call to
- * xMessageBufferCreate() or xMessageBufferCreateStatic().  If the message
- * buffer was created using dynamic memory (that is, by xMessageBufferCreate()),
- * then the allocated memory is freed.
- *
- * A message buffer handle must not be used after the message buffer has been
- * deleted.
- *
- * @param xMessageBuffer The handle of the message buffer to be deleted.
- *
- */
-#define vMessageBufferDelete( xMessageBuffer ) vStreamBufferDelete( ( StreamBufferHandle_t ) xMessageBuffer )
-
-/**
- * message_buffer.h
-
-BaseType_t xMessageBufferIsFull( MessageBufferHandle_t xMessageBuffer ) );
-

- *
- * Tests to see if a message buffer is full.  A message buffer is full if it
- * cannot accept any more messages, of any size, until space is made available
- * by a message being removed from the message buffer.
- *
- * @param xMessageBuffer The handle of the message buffer being queried.
- *
- * @return If the message buffer referenced by xMessageBuffer is full then
- * pdTRUE is returned.  Otherwise pdFALSE is returned.
- */
-#define xMessageBufferIsFull( xMessageBuffer ) xStreamBufferIsFull( ( StreamBufferHandle_t ) xMessageBuffer )
-
-/**
- * message_buffer.h
-
-BaseType_t xMessageBufferIsEmpty( MessageBufferHandle_t xMessageBuffer ) );
-

- *
- * Tests to see if a message buffer is empty (does not contain any messages).
- *
- * @param xMessageBuffer The handle of the message buffer being queried.
- *
- * @return If the message buffer referenced by xMessageBuffer is empty then
- * pdTRUE is returned.  Otherwise pdFALSE is returned.
- *
- */
-#define xMessageBufferIsEmpty( xMessageBuffer ) xStreamBufferIsEmpty( ( StreamBufferHandle_t ) xMessageBuffer )
-
-/**
- * message_buffer.h
-
-BaseType_t xMessageBufferReset( MessageBufferHandle_t xMessageBuffer );
-

- *
- * Resets a message buffer to its initial empty state, discarding any message it
- * contained.
- *
- * A message buffer can only be reset if there are no tasks blocked on it.
- *
- * @param xMessageBuffer The handle of the message buffer being reset.
- *
- * @return If the message buffer was reset then pdPASS is returned.  If the
- * message buffer could not be reset because either there was a task blocked on
- * the message queue to wait for space to become available, or to wait for a
- * a message to be available, then pdFAIL is returned.
- *
- * \defgroup xMessageBufferReset xMessageBufferReset
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferReset( xMessageBuffer ) xStreamBufferReset( ( StreamBufferHandle_t ) xMessageBuffer )
-
-
-/**
- * message_buffer.h
-
-size_t xMessageBufferSpaceAvailable( MessageBufferHandle_t xMessageBuffer ) );
-

- * Returns the number of bytes of free space in the message buffer.
- *
- * @param xMessageBuffer The handle of the message buffer being queried.
- *
- * @return The number of bytes that can be written to the message buffer before
- * the message buffer would be full.  When a message is written to the message
- * buffer an additional sizeof( size_t ) bytes are also written to store the
- * message's length.  sizeof( size_t ) is typically 4 bytes on a 32-bit
- * architecture, so if xMessageBufferSpacesAvailable() returns 10, then the size
- * of the largest message that can be written to the message buffer is 6 bytes.
- *
- * \defgroup xMessageBufferSpaceAvailable xMessageBufferSpaceAvailable
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferSpaceAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer )
-#define xMessageBufferSpacesAvailable( xMessageBuffer ) xStreamBufferSpacesAvailable( ( StreamBufferHandle_t ) xMessageBuffer ) /* Corrects typo in original macro name. */
-
-/**
- * message_buffer.h
- 
- size_t xMessageBufferNextLengthBytes( MessageBufferHandle_t xMessageBuffer ) );
- 

- * Returns the length (in bytes) of the next message in a message buffer.
- * Useful if xMessageBufferReceive() returned 0 because the size of the buffer
- * passed into xMessageBufferReceive() was too small to hold the next message.
- *
- * @param xMessageBuffer The handle of the message buffer being queried.
- *
- * @return The length (in bytes) of the next message in the message buffer, or 0
- * if the message buffer is empty.
- *
- * \defgroup xMessageBufferNextLengthBytes xMessageBufferNextLengthBytes
- * \ingroup MessageBufferManagement
- */
-#define xMessageBufferNextLengthBytes( xMessageBuffer ) xStreamBufferNextMessageLengthBytes( ( StreamBufferHandle_t ) xMessageBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * message_buffer.h
- *
-
-BaseType_t xMessageBufferSendCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * For advanced users only.
- *
- * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
- * data is sent to a message buffer or stream buffer.  If there was a task that
- * was blocked on the message or stream buffer waiting for data to arrive then
- * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
- * from the Blocked state.  xMessageBufferSendCompletedFromISR() does the same
- * thing.  It is provided to enable application writers to implement their own
- * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
- *
- * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
- * additional information.
- *
- * @param xStreamBuffer The handle of the stream buffer to which data was
- * written.
- *
- * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
- * initialised to pdFALSE before it is passed into
- * xMessageBufferSendCompletedFromISR().  If calling
- * xMessageBufferSendCompletedFromISR() removes a task from the Blocked state,
- * and the task has a priority above the priority of the currently running task,
- * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
- * context switch should be performed before exiting the ISR.
- *
- * @return If a task was removed from the Blocked state then pdTRUE is returned.
- * Otherwise pdFALSE is returned.
- *
- * \defgroup xMessageBufferSendCompletedFromISR xMessageBufferSendCompletedFromISR
- * \ingroup StreamBufferManagement
- */
-#define xMessageBufferSendCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferSendCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
-
-/**
- * message_buffer.h
- *
-
-BaseType_t xMessageBufferReceiveCompletedFromISR( MessageBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * For advanced users only.
- *
- * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
- * data is read out of a message buffer or stream buffer.  If there was a task
- * that was blocked on the message or stream buffer waiting for data to arrive
- * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
- * remove it from the Blocked state.  xMessageBufferReceiveCompletedFromISR()
- * does the same thing.  It is provided to enable application writers to
- * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
- * ANY OTHER TIME.
- *
- * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
- * additional information.
- *
- * @param xStreamBuffer The handle of the stream buffer from which data was
- * read.
- *
- * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
- * initialised to pdFALSE before it is passed into
- * xMessageBufferReceiveCompletedFromISR().  If calling
- * xMessageBufferReceiveCompletedFromISR() removes a task from the Blocked state,
- * and the task has a priority above the priority of the currently running task,
- * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
- * context switch should be performed before exiting the ISR.
- *
- * @return If a task was removed from the Blocked state then pdTRUE is returned.
- * Otherwise pdFALSE is returned.
- *
- * \defgroup xMessageBufferReceiveCompletedFromISR xMessageBufferReceiveCompletedFromISR
- * \ingroup StreamBufferManagement
- */
-#define xMessageBufferReceiveCompletedFromISR( xMessageBuffer, pxHigherPriorityTaskWoken ) xStreamBufferReceiveCompletedFromISR( ( StreamBufferHandle_t ) xMessageBuffer, pxHigherPriorityTaskWoken )
-
-#if defined( __cplusplus )
-} /* extern "C" */
-#endif
-
-#endif	/* !defined( FREERTOS_MESSAGE_BUFFER_H ) */
diff --git a/FreeRTOS/Source/include/mpu_prototypes.h b/FreeRTOS/Source/include/mpu_prototypes.h
deleted file mode 100755
index 5d74907..0000000
--- a/FreeRTOS/Source/include/mpu_prototypes.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * When the MPU is used the standard (non MPU) API functions are mapped to
- * equivalents that start "MPU_", the prototypes for which are defined in this
- * header files.  This will cause the application code to call the MPU_ version
- * which wraps the non-MPU version with privilege promoting then demoting code,
- * so the kernel code always runs will full privileges.
- */
-
-
-#ifndef MPU_PROTOTYPES_H
-#define MPU_PROTOTYPES_H
-
-/* MPU versions of tasks.h API functions. */
-BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskDelete( TaskHandle_t xTaskToDelete ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskDelay( const TickType_t xTicksToDelay ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-eTaskState MPU_eTaskGetState( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskResume( TaskHandle_t xTaskToResume ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskStartScheduler( void ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSuspendAll( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskResumeAll( void ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTaskGetTickCount( void ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) FREERTOS_SYSTEM_CALL;
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) FREERTOS_SYSTEM_CALL;
-TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) FREERTOS_SYSTEM_CALL;
-void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskList( char * pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskIncrementTick( void ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) FREERTOS_SYSTEM_CALL;
-void MPU_vTaskMissedYield( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTaskGetSchedulerState( void ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of queue.h API functions. */
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueDelete( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-const char * MPU_pcQueueGetName( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) FREERTOS_SYSTEM_CALL;
-QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) FREERTOS_SYSTEM_CALL;
-QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) FREERTOS_SYSTEM_CALL;
-void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of timers.h API functions. */
-TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) FREERTOS_SYSTEM_CALL;
-TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) FREERTOS_SYSTEM_CALL;
-void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerCreateTimerTask( void ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of event_group.h API functions. */
-EventGroupHandle_t MPU_xEventGroupCreate( void ) FREERTOS_SYSTEM_CALL;
-EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) FREERTOS_SYSTEM_CALL;
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) FREERTOS_SYSTEM_CALL;
-UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup ) FREERTOS_SYSTEM_CALL;
-
-/* MPU versions of message/stream_buffer.h API functions. */
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) FREERTOS_SYSTEM_CALL;
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) FREERTOS_SYSTEM_CALL;
-StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) FREERTOS_SYSTEM_CALL;
-StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) FREERTOS_SYSTEM_CALL;
-
-
-
-#endif /* MPU_PROTOTYPES_H */
-
diff --git a/FreeRTOS/Source/include/mpu_wrappers.h b/FreeRTOS/Source/include/mpu_wrappers.h
deleted file mode 100755
index 711393f..0000000
--- a/FreeRTOS/Source/include/mpu_wrappers.h
+++ /dev/null
@@ -1,186 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef MPU_WRAPPERS_H
-#define MPU_WRAPPERS_H
-
-/* This file redefines API functions to be called through a wrapper macro, but
-only for ports that are using the MPU. */
-#ifdef portUSING_MPU_WRAPPERS
-
-	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
-	included from queue.c or task.c to prevent it from having an effect within
-	those files. */
-	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-		/*
-		 * Map standard (non MPU) API functions to equivalents that start
-		 * "MPU_".  This will cause the application code to call the MPU_
-		 * version, which wraps the non-MPU version with privilege promoting
-		 * then demoting code, so the kernel code always runs will full
-		 * privileges.
-		 */
-
-		/* Map standard tasks.h API functions to the MPU equivalents. */
-		#define xTaskCreate								MPU_xTaskCreate
-		#define xTaskCreateStatic						MPU_xTaskCreateStatic
-		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
-		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
-		#define vTaskDelete								MPU_vTaskDelete
-		#define vTaskDelay								MPU_vTaskDelay
-		#define vTaskDelayUntil							MPU_vTaskDelayUntil
-		#define xTaskAbortDelay							MPU_xTaskAbortDelay
-		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
-		#define eTaskGetState							MPU_eTaskGetState
-		#define vTaskGetInfo							MPU_vTaskGetInfo
-		#define vTaskPrioritySet						MPU_vTaskPrioritySet
-		#define vTaskSuspend							MPU_vTaskSuspend
-		#define vTaskResume								MPU_vTaskResume
-		#define vTaskSuspendAll							MPU_vTaskSuspendAll
-		#define xTaskResumeAll							MPU_xTaskResumeAll
-		#define xTaskGetTickCount						MPU_xTaskGetTickCount
-		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
-		#define pcTaskGetName							MPU_pcTaskGetName
-		#define xTaskGetHandle							MPU_xTaskGetHandle
-		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
-		#define uxTaskGetStackHighWaterMark2			MPU_uxTaskGetStackHighWaterMark2
-		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
-		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
-		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
-		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
-		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
-		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
-		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
-		#define vTaskList								MPU_vTaskList
-		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
-		#define xTaskGetIdleRunTimeCounter				MPU_xTaskGetIdleRunTimeCounter
-		#define xTaskGenericNotify						MPU_xTaskGenericNotify
-		#define xTaskNotifyWait							MPU_xTaskNotifyWait
-		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
-		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
-
-		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
-		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
-		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
-		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
-
-		/* Map standard queue.h API functions to the MPU equivalents. */
-		#define xQueueGenericSend						MPU_xQueueGenericSend
-		#define xQueueReceive							MPU_xQueueReceive
-		#define xQueuePeek								MPU_xQueuePeek
-		#define xQueueSemaphoreTake						MPU_xQueueSemaphoreTake
-		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
-		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
-		#define vQueueDelete							MPU_vQueueDelete
-		#define xQueueCreateMutex						MPU_xQueueCreateMutex
-		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
-		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
-		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
-		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
-		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
-		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
-		#define xQueueGenericCreate						MPU_xQueueGenericCreate
-		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
-		#define xQueueCreateSet							MPU_xQueueCreateSet
-		#define xQueueAddToSet							MPU_xQueueAddToSet
-		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
-		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
-		#define xQueueGenericReset						MPU_xQueueGenericReset
-
-		#if( configQUEUE_REGISTRY_SIZE > 0 )
-			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
-			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
-			#define pcQueueGetName							MPU_pcQueueGetName
-		#endif
-
-		/* Map standard timer.h API functions to the MPU equivalents. */
-		#define xTimerCreate							MPU_xTimerCreate
-		#define xTimerCreateStatic						MPU_xTimerCreateStatic
-		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
-		#define vTimerSetTimerID						MPU_vTimerSetTimerID
-		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
-		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
-		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
-		#define pcTimerGetName							MPU_pcTimerGetName
-		#define vTimerSetReloadMode						MPU_vTimerSetReloadMode
-		#define xTimerGetPeriod							MPU_xTimerGetPeriod
-		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
-		#define xTimerGenericCommand					MPU_xTimerGenericCommand
-
-		/* Map standard event_group.h API functions to the MPU equivalents. */
-		#define xEventGroupCreate						MPU_xEventGroupCreate
-		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
-		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
-		#define xEventGroupClearBits					MPU_xEventGroupClearBits
-		#define xEventGroupSetBits						MPU_xEventGroupSetBits
-		#define xEventGroupSync							MPU_xEventGroupSync
-		#define vEventGroupDelete						MPU_vEventGroupDelete
-
-		/* Map standard message/stream_buffer.h API functions to the MPU
-		equivalents. */
-		#define xStreamBufferSend						MPU_xStreamBufferSend
-		#define xStreamBufferReceive					MPU_xStreamBufferReceive
-		#define xStreamBufferNextMessageLengthBytes		MPU_xStreamBufferNextMessageLengthBytes
-		#define vStreamBufferDelete						MPU_vStreamBufferDelete
-		#define xStreamBufferIsFull						MPU_xStreamBufferIsFull
-		#define xStreamBufferIsEmpty					MPU_xStreamBufferIsEmpty
-		#define xStreamBufferReset						MPU_xStreamBufferReset
-		#define xStreamBufferSpacesAvailable			MPU_xStreamBufferSpacesAvailable
-		#define xStreamBufferBytesAvailable				MPU_xStreamBufferBytesAvailable
-		#define xStreamBufferSetTriggerLevel			MPU_xStreamBufferSetTriggerLevel
-		#define xStreamBufferGenericCreate				MPU_xStreamBufferGenericCreate
-		#define xStreamBufferGenericCreateStatic		MPU_xStreamBufferGenericCreateStatic
-
-
-		/* Remove the privileged function macro, but keep the PRIVILEGED_DATA
-		macro so applications can place data in privileged access sections
-		(useful when using statically allocated objects). */
-		#define PRIVILEGED_FUNCTION
-		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
-		#define FREERTOS_SYSTEM_CALL
-
-	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
-
-		/* Ensure API functions go in the privileged execution section. */
-		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
-		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
-		#define FREERTOS_SYSTEM_CALL __attribute__((section( "freertos_system_calls")))
-
-	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
-
-#else /* portUSING_MPU_WRAPPERS */
-
-	#define PRIVILEGED_FUNCTION
-	#define PRIVILEGED_DATA
-	#define FREERTOS_SYSTEM_CALL
-	#define portUSING_MPU_WRAPPERS 0
-
-#endif /* portUSING_MPU_WRAPPERS */
-
-
-#endif /* MPU_WRAPPERS_H */
-
diff --git a/FreeRTOS/Source/include/portable.h b/FreeRTOS/Source/include/portable.h
deleted file mode 100755
index 59e8169..0000000
--- a/FreeRTOS/Source/include/portable.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Portable layer API.  Each function must be defined for each port.
- *----------------------------------------------------------*/
-
-#ifndef PORTABLE_H
-#define PORTABLE_H
-
-/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
-pre-processor definition was used to ensure the pre-processor found the correct
-portmacro.h file for the port being used.  That scheme was deprecated in favour
-of setting the compiler's include path such that it found the correct
-portmacro.h file - removing the need for the constant and allowing the
-portmacro.h file to be located anywhere in relation to the port being used.
-Purely for reasons of backward compatibility the old method is still valid, but
-to make it clear that new projects should not use it, support for the port
-specific constants has been moved into the deprecated_definitions.h header
-file. */
-#include "deprecated_definitions.h"
-
-/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
-did not result in a portmacro.h header file being included - and it should be
-included here.  In this case the path to the correct portmacro.h header file
-must be set in the compiler's include path. */
-#ifndef portENTER_CRITICAL
-	#include "portmacro.h"
-#endif
-
-#if portBYTE_ALIGNMENT == 32
-	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
-#endif
-
-#if portBYTE_ALIGNMENT == 16
-	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
-#endif
-
-#if portBYTE_ALIGNMENT == 8
-	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
-#endif
-
-#if portBYTE_ALIGNMENT == 4
-	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
-#endif
-
-#if portBYTE_ALIGNMENT == 2
-	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
-#endif
-
-#if portBYTE_ALIGNMENT == 1
-	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
-#endif
-
-#ifndef portBYTE_ALIGNMENT_MASK
-	#error "Invalid portBYTE_ALIGNMENT definition"
-#endif
-
-#ifndef portNUM_CONFIGURABLE_REGIONS
-	#define portNUM_CONFIGURABLE_REGIONS 1
-#endif
-
-#ifndef portHAS_STACK_OVERFLOW_CHECKING
-	#define portHAS_STACK_OVERFLOW_CHECKING 0
-#endif
-
-#ifndef portARCH_NAME
-	#define portARCH_NAME NULL
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "mpu_wrappers.h"
-
-/*
- * Setup the stack of a new task so it is ready to be placed under the
- * scheduler control.  The registers have to be placed on the stack in
- * the order that the port expects to find them.
- *
- */
-#if( portUSING_MPU_WRAPPERS == 1 )
-	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
-	#else
-		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
-	#endif
-#else
-	#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
-	#else
-		StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
-	#endif
-#endif
-
-/* Used by heap_5.c. */
-typedef struct HeapRegion
-{
-	uint8_t *pucStartAddress;
-	size_t xSizeInBytes;
-} HeapRegion_t;
-
-/*
- * Used to define multiple heap regions for use by heap_5.c.  This function
- * must be called before any calls to pvPortMalloc() - not creating a task,
- * queue, semaphore, mutex, software timer, event group, etc. will result in
- * pvPortMalloc being called.
- *
- * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
- * defines a region of memory that can be used as the heap.  The array is
- * terminated by a HeapRegions_t structure that has a size of 0.  The region
- * with the lowest start address must appear first in the array.
- */
-void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
-
-
-/*
- * Map to the memory management routines required for the port.
- */
-void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
-void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
-void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
-size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
-size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Setup the hardware ready for the scheduler to take control.  This generally
- * sets up a tick interrupt and sets timers for the correct tick frequency.
- */
-BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
- * the hardware is left in its original condition after the scheduler stops
- * executing.
- */
-void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
-
-/*
- * The structures and methods of manipulating the MPU are contained within the
- * port layer.
- *
- * Fills the xMPUSettings structure with the memory region information
- * contained in xRegions.
- */
-#if( portUSING_MPU_WRAPPERS == 1 )
-	struct xMEMORY_REGION;
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTABLE_H */
-
diff --git a/FreeRTOS/Source/include/projdefs.h b/FreeRTOS/Source/include/projdefs.h
deleted file mode 100755
index e045861..0000000
--- a/FreeRTOS/Source/include/projdefs.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PROJDEFS_H
-#define PROJDEFS_H
-
-/*
- * Defines the prototype to which task functions must conform.  Defined in this
- * file to ensure the type is known before portable.h is included.
- */
-typedef void (*TaskFunction_t)( void * );
-
-/* Converts a time in milliseconds to a time in ticks.  This macro can be
-overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
-definition here is not suitable for your application. */
-#ifndef pdMS_TO_TICKS
-	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
-#endif
-
-#define pdFALSE			( ( BaseType_t ) 0 )
-#define pdTRUE			( ( BaseType_t ) 1 )
-
-#define pdPASS			( pdTRUE )
-#define pdFAIL			( pdFALSE )
-#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
-#define errQUEUE_FULL	( ( BaseType_t ) 0 )
-
-/* FreeRTOS error definitions. */
-#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
-#define errQUEUE_BLOCKED						( -4 )
-#define errQUEUE_YIELD							( -5 )
-
-/* Macros used for basic data corruption checks. */
-#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
-	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
-#endif
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
-#else
-	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
-#endif
-
-/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
-itself. */
-#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
-#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
-#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
-#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
-#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
-#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
-#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
-#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
-#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
-#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
-#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
-#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
-#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
-#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
-#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
-#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
-#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
-#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
-#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
-#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
-#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
-#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
-#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
-#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
-#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
-#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
-#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
-#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
-#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
-#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
-#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
-#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
-#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
-#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
-#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
-#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
-#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
-#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
-#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
-#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
-
-/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
-itself. */
-#define pdFREERTOS_LITTLE_ENDIAN		0
-#define pdFREERTOS_BIG_ENDIAN			1
-
-/* Re-defining endian values for generic naming. */
-#define pdLITTLE_ENDIAN					pdFREERTOS_LITTLE_ENDIAN
-#define pdBIG_ENDIAN					pdFREERTOS_BIG_ENDIAN
-
-
-#endif /* PROJDEFS_H */
-
-
-
diff --git a/FreeRTOS/Source/include/queue.h b/FreeRTOS/Source/include/queue.h
deleted file mode 100755
index 3b9da93..0000000
--- a/FreeRTOS/Source/include/queue.h
+++ /dev/null
@@ -1,1655 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef QUEUE_H
-#define QUEUE_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "task.h"
-
-/**
- * Type by which queues are referenced.  For example, a call to xQueueCreate()
- * returns an QueueHandle_t variable that can then be used as a parameter to
- * xQueueSend(), xQueueReceive(), etc.
- */
-struct QueueDefinition; /* Using old naming convention so as not to break kernel aware debuggers. */
-typedef struct QueueDefinition * QueueHandle_t;
-
-/**
- * Type by which queue sets are referenced.  For example, a call to
- * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
- * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
- */
-typedef struct QueueDefinition * QueueSetHandle_t;
-
-/**
- * Queue sets can contain both queues and semaphores, so the
- * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
- * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
- */
-typedef struct QueueDefinition * QueueSetMemberHandle_t;
-
-/* For internal use only. */
-#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
-#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
-#define queueOVERWRITE			( ( BaseType_t ) 2 )
-
-/* For internal use only.  These definitions *must* match those in queue.c. */
-#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
-#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
-#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
-#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
-#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
-#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
-
-/**
- * queue. h
- * 
- QueueHandle_t xQueueCreate(
-							  UBaseType_t uxQueueLength,
-							  UBaseType_t uxItemSize
-						  );
- * 

- *
- * Creates a new queue instance, and returns a handle by which the new queue
- * can be referenced.
- *
- * Internally, within the FreeRTOS implementation, queues use two blocks of
- * memory.  The first block is used to hold the queue's data structures.  The
- * second block is used to hold items placed into the queue.  If a queue is
- * created using xQueueCreate() then both blocks of memory are automatically
- * dynamically allocated inside the xQueueCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a queue is created using
- * xQueueCreateStatic() then the application writer must provide the memory that
- * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
- * be created without using any dynamic memory allocation.
- *
- * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
- *
- * @param uxQueueLength The maximum number of items that the queue can contain.
- *
- * @param uxItemSize The number of bytes each item in the queue will require.
- * Items are queued by copy, not by reference, so this is the number of bytes
- * that will be copied for each posted item.  Each item on the queue must be
- * the same size.
- *
- * @return If the queue is successfully create then a handle to the newly
- * created queue is returned.  If the queue cannot be created then 0 is
- * returned.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- };
-
- void vATask( void *pvParameters )
- {
- QueueHandle_t xQueue1, xQueue2;
-
-	// Create a queue capable of containing 10 uint32_t values.
-	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
-	if( xQueue1 == 0 )
-	{
-		// Queue was not created and must not be used.
-	}
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-	if( xQueue2 == 0 )
-	{
-		// Queue was not created and must not be used.
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueCreate xQueueCreate
- * \ingroup QueueManagement
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
-#endif
-
-/**
- * queue. h
- * 
- QueueHandle_t xQueueCreateStatic(
-							  UBaseType_t uxQueueLength,
-							  UBaseType_t uxItemSize,
-							  uint8_t *pucQueueStorageBuffer,
-							  StaticQueue_t *pxQueueBuffer
-						  );
- * 

- *
- * Creates a new queue instance, and returns a handle by which the new queue
- * can be referenced.
- *
- * Internally, within the FreeRTOS implementation, queues use two blocks of
- * memory.  The first block is used to hold the queue's data structures.  The
- * second block is used to hold items placed into the queue.  If a queue is
- * created using xQueueCreate() then both blocks of memory are automatically
- * dynamically allocated inside the xQueueCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a queue is created using
- * xQueueCreateStatic() then the application writer must provide the memory that
- * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
- * be created without using any dynamic memory allocation.
- *
- * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
- *
- * @param uxQueueLength The maximum number of items that the queue can contain.
- *
- * @param uxItemSize The number of bytes each item in the queue will require.
- * Items are queued by copy, not by reference, so this is the number of bytes
- * that will be copied for each posted item.  Each item on the queue must be
- * the same size.
- *
- * @param pucQueueStorageBuffer If uxItemSize is not zero then
- * pucQueueStorageBuffer must point to a uint8_t array that is at least large
- * enough to hold the maximum number of items that can be in the queue at any
- * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
- * zero then pucQueueStorageBuffer can be NULL.
- *
- * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
- * will be used to hold the queue's data structure.
- *
- * @return If the queue is created then a handle to the created queue is
- * returned.  If pxQueueBuffer is NULL then NULL is returned.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- };
-
- #define QUEUE_LENGTH 10
- #define ITEM_SIZE sizeof( uint32_t )
-
- // xQueueBuffer will hold the queue structure.
- StaticQueue_t xQueueBuffer;
-
- // ucQueueStorage will hold the items posted to the queue.  Must be at least
- // [(queue length) * ( queue item size)] bytes long.
- uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
-
- void vATask( void *pvParameters )
- {
- QueueHandle_t xQueue1;
-
-	// Create a queue capable of containing 10 uint32_t values.
-	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
-							ITEM_SIZE	  // The size of each item in the queue
-							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
-							&xQueueBuffer ); // The buffer that will hold the queue structure.
-
-	// The queue is guaranteed to be created successfully as no dynamic memory
-	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueCreateStatic xQueueCreateStatic
- * \ingroup QueueManagement
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * queue. h
- * 
- BaseType_t xQueueSendToToFront(
-								   QueueHandle_t	xQueue,
-								   const void		*pvItemToQueue,
-								   TickType_t		xTicksToWait
-							   );
- * 

- *
- * Post an item to the front of a queue.  The item is queued by copy, not by
- * reference.  This function must not be called from an interrupt service
- * routine.  See xQueueSendFromISR () for an alternative which may be used
- * in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the
- * queue is full.  The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- uint32_t ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- QueueHandle_t xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 uint32_t values.
-	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-	// ...
-
-	if( xQueue1 != 0 )
-	{
-		// Send an uint32_t.  Wait for 10 ticks for space to become
-		// available if necessary.
-		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
-		{
-			// Failed to post the message, even after 10 ticks.
-		}
-	}
-
-	if( xQueue2 != 0 )
-	{
-		// Send a pointer to a struct AMessage object.  Don't block if the
-		// queue is already full.
-		pxMessage = & xMessage;
-		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueSend xQueueSend
- * \ingroup QueueManagement
- */
-#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
-
-/**
- * queue. h
- * 
- BaseType_t xQueueSendToBack(
-								   QueueHandle_t	xQueue,
-								   const void		*pvItemToQueue,
-								   TickType_t		xTicksToWait
-							   );
- * 

- *
- * This is a macro that calls xQueueGenericSend().
- *
- * Post an item to the back of a queue.  The item is queued by copy, not by
- * reference.  This function must not be called from an interrupt service
- * routine.  See xQueueSendFromISR () for an alternative which may be used
- * in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the queue
- * is full.  The  time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- uint32_t ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- QueueHandle_t xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 uint32_t values.
-	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-	// ...
-
-	if( xQueue1 != 0 )
-	{
-		// Send an uint32_t.  Wait for 10 ticks for space to become
-		// available if necessary.
-		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
-		{
-			// Failed to post the message, even after 10 ticks.
-		}
-	}
-
-	if( xQueue2 != 0 )
-	{
-		// Send a pointer to a struct AMessage object.  Don't block if the
-		// queue is already full.
-		pxMessage = & xMessage;
-		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueSend xQueueSend
- * \ingroup QueueManagement
- */
-#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
-
-/**
- * queue. h
- * 
- BaseType_t xQueueSend(
-							  QueueHandle_t xQueue,
-							  const void * pvItemToQueue,
-							  TickType_t xTicksToWait
-						 );
- * 

- *
- * This is a macro that calls xQueueGenericSend().  It is included for
- * backward compatibility with versions of FreeRTOS.org that did not
- * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
- * equivalent to xQueueSendToBack().
- *
- * Post an item on a queue.  The item is queued by copy, not by reference.
- * This function must not be called from an interrupt service routine.
- * See xQueueSendFromISR () for an alternative which may be used in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the
- * queue is full.  The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- uint32_t ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- QueueHandle_t xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 uint32_t values.
-	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-	// ...
-
-	if( xQueue1 != 0 )
-	{
-		// Send an uint32_t.  Wait for 10 ticks for space to become
-		// available if necessary.
-		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
-		{
-			// Failed to post the message, even after 10 ticks.
-		}
-	}
-
-	if( xQueue2 != 0 )
-	{
-		// Send a pointer to a struct AMessage object.  Don't block if the
-		// queue is already full.
-		pxMessage = & xMessage;
-		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueSend xQueueSend
- * \ingroup QueueManagement
- */
-#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
-
-/**
- * queue. h
- * 
- BaseType_t xQueueOverwrite(
-							  QueueHandle_t xQueue,
-							  const void * pvItemToQueue
-						 );
- * 

- *
- * Only for use with queues that have a length of one - so the queue is either
- * empty or full.
- *
- * Post an item on a queue.  If the queue is already full then overwrite the
- * value held in the queue.  The item is queued by copy, not by reference.
- *
- * This function must not be called from an interrupt service routine.
- * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
- *
- * @param xQueue The handle of the queue to which the data is being sent.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
- * therefore has the same return values as xQueueSendToFront().  However, pdPASS
- * is the only value that can be returned because xQueueOverwrite() will write
- * to the queue even when the queue is already full.
- *
- * Example usage:
-   
-
- void vFunction( void *pvParameters )
- {
- QueueHandle_t xQueue;
- uint32_t ulVarToSend, ulValReceived;
-
-	// Create a queue to hold one uint32_t value.  It is strongly
-	// recommended *not* to use xQueueOverwrite() on queues that can
-	// contain more than one value, and doing so will trigger an assertion
-	// if configASSERT() is defined.
-	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
-
-	// Write the value 10 to the queue using xQueueOverwrite().
-	ulVarToSend = 10;
-	xQueueOverwrite( xQueue, &ulVarToSend );
-
-	// Peeking the queue should now return 10, but leave the value 10 in
-	// the queue.  A block time of zero is used as it is known that the
-	// queue holds a value.
-	ulValReceived = 0;
-	xQueuePeek( xQueue, &ulValReceived, 0 );
-
-	if( ulValReceived != 10 )
-	{
-		// Error unless the item was removed by a different task.
-	}
-
-	// The queue is still full.  Use xQueueOverwrite() to overwrite the
-	// value held in the queue with 100.
-	ulVarToSend = 100;
-	xQueueOverwrite( xQueue, &ulVarToSend );
-
-	// This time read from the queue, leaving the queue empty once more.
-	// A block time of 0 is used again.
-	xQueueReceive( xQueue, &ulValReceived, 0 );
-
-	// The value read should be the last value written, even though the
-	// queue was already full when the value was written.
-	if( ulValReceived != 100 )
-	{
-		// Error!
-	}
-
-	// ...
-}
- 

- * \defgroup xQueueOverwrite xQueueOverwrite
- * \ingroup QueueManagement
- */
-#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
-
-
-/**
- * queue. h
- * 
- BaseType_t xQueueGenericSend(
-									QueueHandle_t xQueue,
-									const void * pvItemToQueue,
-									TickType_t xTicksToWait
-									BaseType_t xCopyPosition
-								);
- * 

- *
- * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
- * xQueueSendToBack() are used in place of calling this function directly.
- *
- * Post an item on a queue.  The item is queued by copy, not by reference.
- * This function must not be called from an interrupt service routine.
- * See xQueueSendFromISR () for an alternative which may be used in an ISR.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for space to become available on the queue, should it already
- * be full.  The call will return immediately if this is set to 0 and the
- * queue is full.  The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- *
- * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
- * item at the back of the queue, or queueSEND_TO_FRONT to place the item
- * at the front of the queue (for high priority messages).
- *
- * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- uint32_t ulVar = 10UL;
-
- void vATask( void *pvParameters )
- {
- QueueHandle_t xQueue1, xQueue2;
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 uint32_t values.
-	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
-
-	// ...
-
-	if( xQueue1 != 0 )
-	{
-		// Send an uint32_t.  Wait for 10 ticks for space to become
-		// available if necessary.
-		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
-		{
-			// Failed to post the message, even after 10 ticks.
-		}
-	}
-
-	if( xQueue2 != 0 )
-	{
-		// Send a pointer to a struct AMessage object.  Don't block if the
-		// queue is already full.
-		pxMessage = & xMessage;
-		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueSend xQueueSend
- * \ingroup QueueManagement
- */
-BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- BaseType_t xQueuePeek(
-							 QueueHandle_t xQueue,
-							 void * const pvBuffer,
-							 TickType_t xTicksToWait
-						 );

- *
- * Receive an item from a queue without removing the item from the queue.
- * The item is received by copy so a buffer of adequate size must be
- * provided.  The number of bytes copied into the buffer was defined when
- * the queue was created.
- *
- * Successfully received items remain on the queue so will be returned again
- * by the next call, or a call to xQueueReceive().
- *
- * This macro must not be used in an interrupt service routine.  See
- * xQueuePeekFromISR() for an alternative that can be called from an interrupt
- * service routine.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for an item to receive should the queue be empty at the time
- * of the call.	 The time is defined in tick periods so the constant
- * portTICK_PERIOD_MS should be used to convert to real time if this is required.
- * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
- * is empty.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- QueueHandle_t xQueue;
-
- // Task to create a queue and post a value.
- void vATask( void *pvParameters )
- {
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
-	if( xQueue == 0 )
-	{
-		// Failed to create the queue.
-	}
-
-	// ...
-
-	// Send a pointer to a struct AMessage object.  Don't block if the
-	// queue is already full.
-	pxMessage = & xMessage;
-	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
-
-	// ... Rest of task code.
- }
-
- // Task to peek the data from the queue.
- void vADifferentTask( void *pvParameters )
- {
- struct AMessage *pxRxedMessage;
-
-	if( xQueue != 0 )
-	{
-		// Peek a message on the created queue.  Block for 10 ticks if a
-		// message is not immediately available.
-		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
-		{
-			// pcRxedMessage now points to the struct AMessage variable posted
-			// by vATask, but the item still remains on the queue.
-		}
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueuePeek xQueuePeek
- * \ingroup QueueManagement
- */
-BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- BaseType_t xQueuePeekFromISR(
-									QueueHandle_t xQueue,
-									void *pvBuffer,
-								);

- *
- * A version of xQueuePeek() that can be called from an interrupt service
- * routine (ISR).
- *
- * Receive an item from a queue without removing the item from the queue.
- * The item is received by copy so a buffer of adequate size must be
- * provided.  The number of bytes copied into the buffer was defined when
- * the queue was created.
- *
- * Successfully received items remain on the queue so will be returned again
- * by the next call, or a call to xQueueReceive().
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * \defgroup xQueuePeekFromISR xQueuePeekFromISR
- * \ingroup QueueManagement
- */
-BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- BaseType_t xQueueReceive(
-								 QueueHandle_t xQueue,
-								 void *pvBuffer,
-								 TickType_t xTicksToWait
-							);

- *
- * Receive an item from a queue.  The item is received by copy so a buffer of
- * adequate size must be provided.  The number of bytes copied into the buffer
- * was defined when the queue was created.
- *
- * Successfully received items are removed from the queue.
- *
- * This function must not be used in an interrupt service routine.  See
- * xQueueReceiveFromISR for an alternative that can.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param xTicksToWait The maximum amount of time the task should block
- * waiting for an item to receive should the queue be empty at the time
- * of the call.	 xQueueReceive() will return immediately if xTicksToWait
- * is zero and the queue is empty.  The time is defined in tick periods so the
- * constant portTICK_PERIOD_MS should be used to convert to real time if this is
- * required.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
-   
- struct AMessage
- {
-	char ucMessageID;
-	char ucData[ 20 ];
- } xMessage;
-
- QueueHandle_t xQueue;
-
- // Task to create a queue and post a value.
- void vATask( void *pvParameters )
- {
- struct AMessage *pxMessage;
-
-	// Create a queue capable of containing 10 pointers to AMessage structures.
-	// These should be passed by pointer as they contain a lot of data.
-	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
-	if( xQueue == 0 )
-	{
-		// Failed to create the queue.
-	}
-
-	// ...
-
-	// Send a pointer to a struct AMessage object.  Don't block if the
-	// queue is already full.
-	pxMessage = & xMessage;
-	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
-
-	// ... Rest of task code.
- }
-
- // Task to receive from the queue.
- void vADifferentTask( void *pvParameters )
- {
- struct AMessage *pxRxedMessage;
-
-	if( xQueue != 0 )
-	{
-		// Receive a message on the created queue.  Block for 10 ticks if a
-		// message is not immediately available.
-		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
-		{
-			// pcRxedMessage now points to the struct AMessage variable posted
-			// by vATask.
-		}
-	}
-
-	// ... Rest of task code.
- }
- 

- * \defgroup xQueueReceive xQueueReceive
- * \ingroup QueueManagement
- */
-BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );

- *
- * Return the number of messages stored in a queue.
- *
- * @param xQueue A handle to the queue being queried.
- *
- * @return The number of messages available in the queue.
- *
- * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
- * \ingroup QueueManagement
- */
-UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );

- *
- * Return the number of free spaces available in a queue.  This is equal to the
- * number of items that can be sent to the queue before the queue becomes full
- * if no items are removed.
- *
- * @param xQueue A handle to the queue being queried.
- *
- * @return The number of spaces available in the queue.
- *
- * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
- * \ingroup QueueManagement
- */
-UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
void vQueueDelete( QueueHandle_t xQueue );

- *
- * Delete a queue - freeing all the memory allocated for storing of items
- * placed on the queue.
- *
- * @param xQueue A handle to the queue to be deleted.
- *
- * \defgroup vQueueDelete vQueueDelete
- * \ingroup QueueManagement
- */
-void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- BaseType_t xQueueSendToFrontFromISR(
-										 QueueHandle_t xQueue,
-										 const void *pvItemToQueue,
-										 BaseType_t *pxHigherPriorityTaskWoken
-									  );
- 

- *
- * This is a macro that calls xQueueGenericSendFromISR().
- *
- * Post an item to the front of a queue.  It is safe to use this macro from
- * within an interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
-   
- void vBufferISR( void )
- {
- char cIn;
- BaseType_t xHigherPrioritTaskWoken;
-
-	// We have not woken a task at the start of the ISR.
-	xHigherPriorityTaskWoken = pdFALSE;
-
-	// Loop until the buffer is empty.
-	do
-	{
-		// Obtain a byte from the buffer.
-		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
-
-		// Post the byte.
-		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
-
-	} while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-	// Now the buffer is empty we can switch context if necessary.
-	if( xHigherPriorityTaskWoken )
-	{
-		taskYIELD ();
-	}
- }
- 

- *
- * \defgroup xQueueSendFromISR xQueueSendFromISR
- * \ingroup QueueManagement
- */
-#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
-
-
-/**
- * queue. h
- * 
- BaseType_t xQueueSendToBackFromISR(
-										 QueueHandle_t xQueue,
-										 const void *pvItemToQueue,
-										 BaseType_t *pxHigherPriorityTaskWoken
-									  );
- 

- *
- * This is a macro that calls xQueueGenericSendFromISR().
- *
- * Post an item to the back of a queue.  It is safe to use this macro from
- * within an interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
-   
- void vBufferISR( void )
- {
- char cIn;
- BaseType_t xHigherPriorityTaskWoken;
-
-	// We have not woken a task at the start of the ISR.
-	xHigherPriorityTaskWoken = pdFALSE;
-
-	// Loop until the buffer is empty.
-	do
-	{
-		// Obtain a byte from the buffer.
-		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
-
-		// Post the byte.
-		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
-
-	} while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-	// Now the buffer is empty we can switch context if necessary.
-	if( xHigherPriorityTaskWoken )
-	{
-		taskYIELD ();
-	}
- }
- 

- *
- * \defgroup xQueueSendFromISR xQueueSendFromISR
- * \ingroup QueueManagement
- */
-#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
-
-/**
- * queue. h
- * 
- BaseType_t xQueueOverwriteFromISR(
-							  QueueHandle_t xQueue,
-							  const void * pvItemToQueue,
-							  BaseType_t *pxHigherPriorityTaskWoken
-						 );
- * 

- *
- * A version of xQueueOverwrite() that can be used in an interrupt service
- * routine (ISR).
- *
- * Only for use with queues that can hold a single item - so the queue is either
- * empty or full.
- *
- * Post an item on a queue.  If the queue is already full then overwrite the
- * value held in the queue.  The item is queued by copy, not by reference.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return xQueueOverwriteFromISR() is a macro that calls
- * xQueueGenericSendFromISR(), and therefore has the same return values as
- * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
- * returned because xQueueOverwriteFromISR() will write to the queue even when
- * the queue is already full.
- *
- * Example usage:
-   
-
- QueueHandle_t xQueue;
-
- void vFunction( void *pvParameters )
- {
- 	// Create a queue to hold one uint32_t value.  It is strongly
-	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
-	// contain more than one value, and doing so will trigger an assertion
-	// if configASSERT() is defined.
-	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
-}
-
-void vAnInterruptHandler( void )
-{
-// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
-BaseType_t xHigherPriorityTaskWoken = pdFALSE;
-uint32_t ulVarToSend, ulValReceived;
-
-	// Write the value 10 to the queue using xQueueOverwriteFromISR().
-	ulVarToSend = 10;
-	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
-
-	// The queue is full, but calling xQueueOverwriteFromISR() again will still
-	// pass because the value held in the queue will be overwritten with the
-	// new value.
-	ulVarToSend = 100;
-	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
-
-	// Reading from the queue will now return 100.
-
-	// ...
-
-	if( xHigherPrioritytaskWoken == pdTRUE )
-	{
-		// Writing to the queue caused a task to unblock and the unblocked task
-		// has a priority higher than or equal to the priority of the currently
-		// executing task (the task this interrupt interrupted).  Perform a context
-		// switch so this interrupt returns directly to the unblocked task.
-		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
-	}
-}
- 

- * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
- * \ingroup QueueManagement
- */
-#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
-
-/**
- * queue. h
- * 
- BaseType_t xQueueSendFromISR(
-									 QueueHandle_t xQueue,
-									 const void *pvItemToQueue,
-									 BaseType_t *pxHigherPriorityTaskWoken
-								);
- 

- *
- * This is a macro that calls xQueueGenericSendFromISR().  It is included
- * for backward compatibility with versions of FreeRTOS.org that did not
- * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
- * macros.
- *
- * Post an item to the back of a queue.  It is safe to use this function from
- * within an interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
-   
- void vBufferISR( void )
- {
- char cIn;
- BaseType_t xHigherPriorityTaskWoken;
-
-	// We have not woken a task at the start of the ISR.
-	xHigherPriorityTaskWoken = pdFALSE;
-
-	// Loop until the buffer is empty.
-	do
-	{
-		// Obtain a byte from the buffer.
-		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
-
-		// Post the byte.
-		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
-
-	} while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-	// Now the buffer is empty we can switch context if necessary.
-	if( xHigherPriorityTaskWoken )
-	{
-		// Actual macro used here is port specific.
-		portYIELD_FROM_ISR ();
-	}
- }
- 

- *
- * \defgroup xQueueSendFromISR xQueueSendFromISR
- * \ingroup QueueManagement
- */
-#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
-
-/**
- * queue. h
- * 
- BaseType_t xQueueGenericSendFromISR(
-										   QueueHandle_t		xQueue,
-										   const	void	*pvItemToQueue,
-										   BaseType_t	*pxHigherPriorityTaskWoken,
-										   BaseType_t	xCopyPosition
-									   );
- 

- *
- * It is preferred that the macros xQueueSendFromISR(),
- * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
- * of calling this function directly.  xQueueGiveFromISR() is an
- * equivalent for use by semaphores that don't actually copy any data.
- *
- * Post an item on a queue.  It is safe to use this function from within an
- * interrupt service routine.
- *
- * Items are queued by copy not reference so it is preferable to only
- * queue small items, especially when called from an ISR.  In most cases
- * it would be preferable to store a pointer to the item being queued.
- *
- * @param xQueue The handle to the queue on which the item is to be posted.
- *
- * @param pvItemToQueue A pointer to the item that is to be placed on the
- * queue.  The size of the items the queue will hold was defined when the
- * queue was created, so this many bytes will be copied from pvItemToQueue
- * into the queue storage area.
- *
- * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
- * item at the back of the queue, or queueSEND_TO_FRONT to place the item
- * at the front of the queue (for high priority messages).
- *
- * @return pdTRUE if the data was successfully sent to the queue, otherwise
- * errQUEUE_FULL.
- *
- * Example usage for buffered IO (where the ISR can obtain more than one value
- * per call):
-   
- void vBufferISR( void )
- {
- char cIn;
- BaseType_t xHigherPriorityTaskWokenByPost;
-
-	// We have not woken a task at the start of the ISR.
-	xHigherPriorityTaskWokenByPost = pdFALSE;
-
-	// Loop until the buffer is empty.
-	do
-	{
-		// Obtain a byte from the buffer.
-		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
-
-		// Post each byte.
-		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
-
-	} while( portINPUT_BYTE( BUFFER_COUNT ) );
-
-	// Now the buffer is empty we can switch context if necessary.  Note that the
-	// name of the yield function required is port specific.
-	if( xHigherPriorityTaskWokenByPost )
-	{
-		taskYIELD_YIELD_FROM_ISR();
-	}
- }
- 

- *
- * \defgroup xQueueSendFromISR xQueueSendFromISR
- * \ingroup QueueManagement
- */
-BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * queue. h
- * 
- BaseType_t xQueueReceiveFromISR(
-									   QueueHandle_t	xQueue,
-									   void	*pvBuffer,
-									   BaseType_t *pxTaskWoken
-								   );
- * 

- *
- * Receive an item from a queue.  It is safe to use this function from within an
- * interrupt service routine.
- *
- * @param xQueue The handle to the queue from which the item is to be
- * received.
- *
- * @param pvBuffer Pointer to the buffer into which the received item will
- * be copied.
- *
- * @param pxTaskWoken A task may be blocked waiting for space to become
- * available on the queue.  If xQueueReceiveFromISR causes such a task to
- * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
- * remain unchanged.
- *
- * @return pdTRUE if an item was successfully received from the queue,
- * otherwise pdFALSE.
- *
- * Example usage:
-   
-
- QueueHandle_t xQueue;
-
- // Function to create a queue and post some values.
- void vAFunction( void *pvParameters )
- {
- char cValueToPost;
- const TickType_t xTicksToWait = ( TickType_t )0xff;
-
-	// Create a queue capable of containing 10 characters.
-	xQueue = xQueueCreate( 10, sizeof( char ) );
-	if( xQueue == 0 )
-	{
-		// Failed to create the queue.
-	}
-
-	// ...
-
-	// Post some characters that will be used within an ISR.  If the queue
-	// is full then this task will block for xTicksToWait ticks.
-	cValueToPost = 'a';
-	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
-	cValueToPost = 'b';
-	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
-
-	// ... keep posting characters ... this task may block when the queue
-	// becomes full.
-
-	cValueToPost = 'c';
-	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
- }
-
- // ISR that outputs all the characters received on the queue.
- void vISR_Routine( void )
- {
- BaseType_t xTaskWokenByReceive = pdFALSE;
- char cRxedChar;
-
-	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
-	{
-		// A character was received.  Output the character now.
-		vOutputCharacter( cRxedChar );
-
-		// If removing the character from the queue woke the task that was
-		// posting onto the queue cTaskWokenByReceive will have been set to
-		// pdTRUE.  No matter how many times this loop iterates only one
-		// task will be woken.
-	}
-
-	if( cTaskWokenByPost != ( char ) pdFALSE;
-	{
-		taskYIELD ();
-	}
- }
- 

- * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
- * \ingroup QueueManagement
- */
-BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/*
- * Utilities to query queues that are safe to use from an ISR.  These utilities
- * should be used only from witin an ISR, or within a critical section.
- */
-BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * The functions defined above are for passing data to and from tasks.  The
- * functions below are the equivalents for passing data to and from
- * co-routines.
- *
- * These functions are called from the co-routine macro implementation and
- * should not be called directly from application code.  Instead use the macro
- * wrappers defined within croutine.h.
- */
-BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
-BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
-BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
-BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
-
-/*
- * For internal use only.  Use xSemaphoreCreateMutex(),
- * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
- * these functions directly.
- */
-QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
-QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
-TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
-
-/*
- * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
- * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
- */
-BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex ) PRIVILEGED_FUNCTION;
-
-/*
- * Reset a queue back to its original empty state.  The return value is now
- * obsolete and is always set to pdPASS.
- */
-#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
-
-/*
- * The registry is provided as a means for kernel aware debuggers to
- * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
- * a queue, semaphore or mutex handle to the registry if you want the handle
- * to be available to a kernel aware debugger.  If you are not using a kernel
- * aware debugger then this function can be ignored.
- *
- * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
- * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
- * within FreeRTOSConfig.h for the registry to be available.  Its value
- * does not effect the number of queues, semaphores and mutexes that can be
- * created - just the number that the registry can hold.
- *
- * @param xQueue The handle of the queue being added to the registry.  This
- * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
- * handles can also be passed in here.
- *
- * @param pcName The name to be associated with the handle.  This is the
- * name that the kernel aware debugger will display.  The queue registry only
- * stores a pointer to the string - so the string must be persistent (global or
- * preferably in ROM/Flash), not on the stack.
- */
-#if( configQUEUE_REGISTRY_SIZE > 0 )
-	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-#endif
-
-/*
- * The registry is provided as a means for kernel aware debuggers to
- * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
- * a queue, semaphore or mutex handle to the registry if you want the handle
- * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
- * remove the queue, semaphore or mutex from the register.  If you are not using
- * a kernel aware debugger then this function can be ignored.
- *
- * @param xQueue The handle of the queue being removed from the registry.
- */
-#if( configQUEUE_REGISTRY_SIZE > 0 )
-	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-#endif
-
-/*
- * The queue registry is provided as a means for kernel aware debuggers to
- * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
- * up and return the name of a queue in the queue registry from the queue's
- * handle.
- *
- * @param xQueue The handle of the queue the name of which will be returned.
- * @return If the queue is in the registry then a pointer to the name of the
- * queue is returned.  If the queue is not in the registry then NULL is
- * returned.
- */
-#if( configQUEUE_REGISTRY_SIZE > 0 )
-	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-#endif
-
-/*
- * Generic version of the function used to creaet a queue using dynamic memory
- * allocation.  This is called by other functions and macros that create other
- * RTOS objects that use the queue structure as their base.
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-#endif
-
-/*
- * Generic version of the function used to creaet a queue using dynamic memory
- * allocation.  This is called by other functions and macros that create other
- * RTOS objects that use the queue structure as their base.
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
-#endif
-
-/*
- * Queue sets provide a mechanism to allow a task to block (pend) on a read
- * operation from multiple queues or semaphores simultaneously.
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * A queue set must be explicitly created using a call to xQueueCreateSet()
- * before it can be used.  Once created, standard FreeRTOS queues and semaphores
- * can be added to the set using calls to xQueueAddToSet().
- * xQueueSelectFromSet() is then used to determine which, if any, of the queues
- * or semaphores contained in the set is in a state where a queue read or
- * semaphore take operation would be successful.
- *
- * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
- * for reasons why queue sets are very rarely needed in practice as there are
- * simpler methods of blocking on multiple objects.
- *
- * Note 2:  Blocking on a queue set that contains a mutex will not cause the
- * mutex holder to inherit the priority of the blocked task.
- *
- * Note 3:  An additional 4 bytes of RAM is required for each space in a every
- * queue added to a queue set.  Therefore counting semaphores that have a high
- * maximum count value should not be added to a queue set.
- *
- * Note 4:  A receive (in the case of a queue) or take (in the case of a
- * semaphore) operation must not be performed on a member of a queue set unless
- * a call to xQueueSelectFromSet() has first returned a handle to that set member.
- *
- * @param uxEventQueueLength Queue sets store events that occur on
- * the queues and semaphores contained in the set.  uxEventQueueLength specifies
- * the maximum number of events that can be queued at once.  To be absolutely
- * certain that events are not lost uxEventQueueLength should be set to the
- * total sum of the length of the queues added to the set, where binary
- * semaphores and mutexes have a length of 1, and counting semaphores have a
- * length set by their maximum count value.  Examples:
- *  + If a queue set is to hold a queue of length 5, another queue of length 12,
- *    and a binary semaphore, then uxEventQueueLength should be set to
- *    (5 + 12 + 1), or 18.
- *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
- *    should be set to (1 + 1 + 1 ), or 3.
- *  + If a queue set is to hold a counting semaphore that has a maximum count of
- *    5, and a counting semaphore that has a maximum count of 3, then
- *    uxEventQueueLength should be set to (5 + 3), or 8.
- *
- * @return If the queue set is created successfully then a handle to the created
- * queue set is returned.  Otherwise NULL is returned.
- */
-QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
-
-/*
- * Adds a queue or semaphore to a queue set that was previously created by a
- * call to xQueueCreateSet().
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * Note 1:  A receive (in the case of a queue) or take (in the case of a
- * semaphore) operation must not be performed on a member of a queue set unless
- * a call to xQueueSelectFromSet() has first returned a handle to that set member.
- *
- * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
- * the queue set (cast to an QueueSetMemberHandle_t type).
- *
- * @param xQueueSet The handle of the queue set to which the queue or semaphore
- * is being added.
- *
- * @return If the queue or semaphore was successfully added to the queue set
- * then pdPASS is returned.  If the queue could not be successfully added to the
- * queue set because it is already a member of a different queue set then pdFAIL
- * is returned.
- */
-BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-
-/*
- * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
- * be removed from a set if the queue or semaphore is empty.
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
- * from the queue set (cast to an QueueSetMemberHandle_t type).
- *
- * @param xQueueSet The handle of the queue set in which the queue or semaphore
- * is included.
- *
- * @return If the queue or semaphore was successfully removed from the queue set
- * then pdPASS is returned.  If the queue was not in the queue set, or the
- * queue (or semaphore) was not empty, then pdFAIL is returned.
- */
-BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-
-/*
- * xQueueSelectFromSet() selects from the members of a queue set a queue or
- * semaphore that either contains data (in the case of a queue) or is available
- * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
- * allows a task to block (pend) on a read operation on all the queues and
- * semaphores in a queue set simultaneously.
- *
- * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
- * function.
- *
- * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
- * for reasons why queue sets are very rarely needed in practice as there are
- * simpler methods of blocking on multiple objects.
- *
- * Note 2:  Blocking on a queue set that contains a mutex will not cause the
- * mutex holder to inherit the priority of the blocked task.
- *
- * Note 3:  A receive (in the case of a queue) or take (in the case of a
- * semaphore) operation must not be performed on a member of a queue set unless
- * a call to xQueueSelectFromSet() has first returned a handle to that set member.
- *
- * @param xQueueSet The queue set on which the task will (potentially) block.
- *
- * @param xTicksToWait The maximum time, in ticks, that the calling task will
- * remain in the Blocked state (with other tasks executing) to wait for a member
- * of the queue set to be ready for a successful queue read or semaphore take
- * operation.
- *
- * @return xQueueSelectFromSet() will return the handle of a queue (cast to
- * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
- * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
- * in the queue set that is available, or NULL if no such queue or semaphore
- * exists before before the specified block time expires.
- */
-QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/*
- * A version of xQueueSelectFromSet() that can be used from an ISR.
- */
-QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
-
-/* Not public API functions. */
-void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
-BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
-void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
-UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* QUEUE_H */
-
diff --git a/FreeRTOS/Source/include/semphr.h b/FreeRTOS/Source/include/semphr.h
deleted file mode 100755
index 2c106ea..0000000
--- a/FreeRTOS/Source/include/semphr.h
+++ /dev/null
@@ -1,1140 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef SEMAPHORE_H
-#define SEMAPHORE_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
-#endif
-
-#include "queue.h"
-
-typedef QueueHandle_t SemaphoreHandle_t;
-
-#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
-#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
-#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
-
-
-/**
- * semphr. h
- * 
vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )

- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a binary semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
- * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
- * the vSemaphoreCreateBinary() macro are created in a state such that the
- * first call to 'take' the semaphore would pass, whereas binary semaphores
- * created using xSemaphoreCreateBinary() are created in a state such that the
- * the semaphore must first be 'given' before it can be 'taken'.
- *
- * Macro that implements a semaphore by using the existing queue mechanism.
- * The queue length is 1 as this is a binary semaphore.  The data size is 0
- * as we don't want to actually store any data - we just want to know if the
- * queue is empty or full.
- *
- * This type of semaphore can be used for pure synchronisation between tasks or
- * between an interrupt and a task.  The semaphore need not be given back once
- * obtained, so one task/interrupt can continuously 'give' the semaphore while
- * another continuously 'takes' the semaphore.  For this reason this type of
- * semaphore does not use a priority inheritance mechanism.  For an alternative
- * that does use priority inheritance see xSemaphoreCreateMutex().
- *
- * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore = NULL;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
-    // This is a macro so pass the variable in directly.
-    vSemaphoreCreateBinary( xSemaphore );
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.
-    }
- }
- 

- * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
- * \ingroup Semaphores
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define vSemaphoreCreateBinary( xSemaphore )																							\
-		{																																	\
-			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
-			if( ( xSemaphore ) != NULL )																									\
-			{																																\
-				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
-			}																																\
-		}
-#endif
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateBinary( void )

- *
- * Creates a new binary semaphore instance, and returns a handle by which the
- * new semaphore can be referenced.
- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a binary semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, binary semaphores use a block
- * of memory, in which the semaphore structure is stored.  If a binary semaphore
- * is created using xSemaphoreCreateBinary() then the required memory is
- * automatically dynamically allocated inside the xSemaphoreCreateBinary()
- * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
- * is created using xSemaphoreCreateBinaryStatic() then the application writer
- * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
- * binary semaphore to be created without using any dynamic memory allocation.
- *
- * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
- * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
- * the vSemaphoreCreateBinary() macro are created in a state such that the
- * first call to 'take' the semaphore would pass, whereas binary semaphores
- * created using xSemaphoreCreateBinary() are created in a state such that the
- * the semaphore must first be 'given' before it can be 'taken'.
- *
- * This type of semaphore can be used for pure synchronisation between tasks or
- * between an interrupt and a task.  The semaphore need not be given back once
- * obtained, so one task/interrupt can continuously 'give' the semaphore while
- * another continuously 'takes' the semaphore.  For this reason this type of
- * semaphore does not use a priority inheritance mechanism.  For an alternative
- * that does use priority inheritance see xSemaphoreCreateMutex().
- *
- * @return Handle to the created semaphore, or NULL if the memory required to
- * hold the semaphore's data structures could not be allocated.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore = NULL;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
-    // This is a macro so pass the variable in directly.
-    xSemaphore = xSemaphoreCreateBinary();
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.
-    }
- }
- 

- * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
- * \ingroup Semaphores
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
-#endif
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )

- *
- * Creates a new binary semaphore instance, and returns a handle by which the
- * new semaphore can be referenced.
- *
- * NOTE: In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a binary semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, binary semaphores use a block
- * of memory, in which the semaphore structure is stored.  If a binary semaphore
- * is created using xSemaphoreCreateBinary() then the required memory is
- * automatically dynamically allocated inside the xSemaphoreCreateBinary()
- * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
- * is created using xSemaphoreCreateBinaryStatic() then the application writer
- * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
- * binary semaphore to be created without using any dynamic memory allocation.
- *
- * This type of semaphore can be used for pure synchronisation between tasks or
- * between an interrupt and a task.  The semaphore need not be given back once
- * obtained, so one task/interrupt can continuously 'give' the semaphore while
- * another continuously 'takes' the semaphore.  For this reason this type of
- * semaphore does not use a priority inheritance mechanism.  For an alternative
- * that does use priority inheritance see xSemaphoreCreateMutex().
- *
- * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
- * which will then be used to hold the semaphore's data structure, removing the
- * need for the memory to be allocated dynamically.
- *
- * @return If the semaphore is created then a handle to the created semaphore is
- * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore = NULL;
- StaticSemaphore_t xSemaphoreBuffer;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
-    // The semaphore's data structures will be placed in the xSemaphoreBuffer
-    // variable, the address of which is passed into the function.  The
-    // function's parameter is not NULL, so the function will not attempt any
-    // dynamic memory allocation, and therefore the function will not return
-    // return NULL.
-    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
-
-    // Rest of task code goes here.
- }
- 

- * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
- * \ingroup Semaphores
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * semphr. h
- * 
xSemaphoreTake(
- *                   SemaphoreHandle_t xSemaphore,
- *                   TickType_t xBlockTime
- *               )

- *
- * Macro to obtain a semaphore.  The semaphore must have previously been
- * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
- * xSemaphoreCreateCounting().
- *
- * @param xSemaphore A handle to the semaphore being taken - obtained when
- * the semaphore was created.
- *
- * @param xBlockTime The time in ticks to wait for the semaphore to become
- * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
- * real time.  A block time of zero can be used to poll the semaphore.  A block
- * time of portMAX_DELAY can be used to block indefinitely (provided
- * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
- *
- * @return pdTRUE if the semaphore was obtained.  pdFALSE
- * if xBlockTime expired without the semaphore becoming available.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore = NULL;
-
- // A task that creates a semaphore.
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    xSemaphore = xSemaphoreCreateBinary();
- }
-
- // A task that uses the semaphore.
- void vAnotherTask( void * pvParameters )
- {
-    // ... Do other things.
-
-    if( xSemaphore != NULL )
-    {
-        // See if we can obtain the semaphore.  If the semaphore is not available
-        // wait 10 ticks to see if it becomes free.
-        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
-        {
-            // We were able to obtain the semaphore and can now access the
-            // shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource.  Release the
-            // semaphore.
-            xSemaphoreGive( xSemaphore );
-        }
-        else
-        {
-            // We could not obtain the semaphore and can therefore not access
-            // the shared resource safely.
-        }
-    }
- }
- 

- * \defgroup xSemaphoreTake xSemaphoreTake
- * \ingroup Semaphores
- */
-#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueSemaphoreTake( ( xSemaphore ), ( xBlockTime ) )
-
-/**
- * semphr. h
- * xSemaphoreTakeRecursive(
- *                          SemaphoreHandle_t xMutex,
- *                          TickType_t xBlockTime
- *                        )
- *
- * Macro to recursively obtain, or 'take', a mutex type semaphore.
- * The mutex must have previously been created using a call to
- * xSemaphoreCreateRecursiveMutex();
- *
- * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
- * macro to be available.
- *
- * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * @param xMutex A handle to the mutex being obtained.  This is the
- * handle returned by xSemaphoreCreateRecursiveMutex();
- *
- * @param xBlockTime The time in ticks to wait for the semaphore to become
- * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
- * real time.  A block time of zero can be used to poll the semaphore.  If
- * the task already owns the semaphore then xSemaphoreTakeRecursive() will
- * return immediately no matter what the value of xBlockTime.
- *
- * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
- * expired without the semaphore becoming available.
- *
- * Example usage:
- 
- SemaphoreHandle_t xMutex = NULL;
-
- // A task that creates a mutex.
- void vATask( void * pvParameters )
- {
-    // Create the mutex to guard a shared resource.
-    xMutex = xSemaphoreCreateRecursiveMutex();
- }
-
- // A task that uses the mutex.
- void vAnotherTask( void * pvParameters )
- {
-    // ... Do other things.
-
-    if( xMutex != NULL )
-    {
-        // See if we can obtain the mutex.  If the mutex is not available
-        // wait 10 ticks to see if it becomes free.
-        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
-        {
-            // We were able to obtain the mutex and can now access the
-            // shared resource.
-
-            // ...
-            // For some reason due to the nature of the code further calls to
-            // xSemaphoreTakeRecursive() are made on the same mutex.  In real
-            // code these would not be just sequential calls as this would make
-            // no sense.  Instead the calls are likely to be buried inside
-            // a more complex call structure.
-            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
-            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
-
-            // The mutex has now been 'taken' three times, so will not be
-            // available to another task until it has also been given back
-            // three times.  Again it is unlikely that real code would have
-            // these calls sequentially, but instead buried in a more complex
-            // call structure.  This is just for illustrative purposes.
-            xSemaphoreGiveRecursive( xMutex );
-            xSemaphoreGiveRecursive( xMutex );
-            xSemaphoreGiveRecursive( xMutex );
-
-            // Now the mutex can be taken by other tasks.
-        }
-        else
-        {
-            // We could not obtain the mutex and can therefore not access
-            // the shared resource safely.
-        }
-    }
- }
- 

- * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
- * \ingroup Semaphores
- */
-#if( configUSE_RECURSIVE_MUTEXES == 1 )
-	#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
-#endif
-
-/**
- * semphr. h
- * 
xSemaphoreGive( SemaphoreHandle_t xSemaphore )

- *
- * Macro to release a semaphore.  The semaphore must have previously been
- * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
- * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
- *
- * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
- * an alternative which can be used from an ISR.
- *
- * This macro must also not be used on semaphores created using
- * xSemaphoreCreateRecursiveMutex().
- *
- * @param xSemaphore A handle to the semaphore being released.  This is the
- * handle returned when the semaphore was created.
- *
- * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
- * Semaphores are implemented using queues.  An error can occur if there is
- * no space on the queue to post a message - indicating that the
- * semaphore was not first obtained correctly.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore = NULL;
-
- void vATask( void * pvParameters )
- {
-    // Create the semaphore to guard a shared resource.
-    xSemaphore = vSemaphoreCreateBinary();
-
-    if( xSemaphore != NULL )
-    {
-        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-        {
-            // We would expect this call to fail because we cannot give
-            // a semaphore without first "taking" it!
-        }
-
-        // Obtain the semaphore - don't block if the semaphore is not
-        // immediately available.
-        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
-        {
-            // We now have the semaphore and can access the shared resource.
-
-            // ...
-
-            // We have finished accessing the shared resource so can free the
-            // semaphore.
-            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
-            {
-                // We would not expect this call to fail because we must have
-                // obtained the semaphore to get here.
-            }
-        }
-    }
- }
- 

- * \defgroup xSemaphoreGive xSemaphoreGive
- * \ingroup Semaphores
- */
-#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
-
-/**
- * semphr. h
- * 
xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )

- *
- * Macro to recursively release, or 'give', a mutex type semaphore.
- * The mutex must have previously been created using a call to
- * xSemaphoreCreateRecursiveMutex();
- *
- * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
- * macro to be available.
- *
- * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * @param xMutex A handle to the mutex being released, or 'given'.  This is the
- * handle returned by xSemaphoreCreateMutex();
- *
- * @return pdTRUE if the semaphore was given.
- *
- * Example usage:
- 
- SemaphoreHandle_t xMutex = NULL;
-
- // A task that creates a mutex.
- void vATask( void * pvParameters )
- {
-    // Create the mutex to guard a shared resource.
-    xMutex = xSemaphoreCreateRecursiveMutex();
- }
-
- // A task that uses the mutex.
- void vAnotherTask( void * pvParameters )
- {
-    // ... Do other things.
-
-    if( xMutex != NULL )
-    {
-        // See if we can obtain the mutex.  If the mutex is not available
-        // wait 10 ticks to see if it becomes free.
-        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
-        {
-            // We were able to obtain the mutex and can now access the
-            // shared resource.
-
-            // ...
-            // For some reason due to the nature of the code further calls to
-			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
-			// code these would not be just sequential calls as this would make
-			// no sense.  Instead the calls are likely to be buried inside
-			// a more complex call structure.
-            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
-            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
-
-            // The mutex has now been 'taken' three times, so will not be
-			// available to another task until it has also been given back
-			// three times.  Again it is unlikely that real code would have
-			// these calls sequentially, it would be more likely that the calls
-			// to xSemaphoreGiveRecursive() would be called as a call stack
-			// unwound.  This is just for demonstrative purposes.
-            xSemaphoreGiveRecursive( xMutex );
-			xSemaphoreGiveRecursive( xMutex );
-			xSemaphoreGiveRecursive( xMutex );
-
-			// Now the mutex can be taken by other tasks.
-        }
-        else
-        {
-            // We could not obtain the mutex and can therefore not access
-            // the shared resource safely.
-        }
-    }
- }
- 

- * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
- * \ingroup Semaphores
- */
-#if( configUSE_RECURSIVE_MUTEXES == 1 )
-	#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
-#endif
-
-/**
- * semphr. h
- * 
- xSemaphoreGiveFromISR(
-                          SemaphoreHandle_t xSemaphore,
-                          BaseType_t *pxHigherPriorityTaskWoken
-                      )

- *
- * Macro to  release a semaphore.  The semaphore must have previously been
- * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
- *
- * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
- * must not be used with this macro.
- *
- * This macro can be used from an ISR.
- *
- * @param xSemaphore A handle to the semaphore being released.  This is the
- * handle returned when the semaphore was created.
- *
- * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
- *
- * Example usage:
- 
- \#define LONG_TIME 0xffff
- \#define TICKS_TO_WAIT	10
- SemaphoreHandle_t xSemaphore = NULL;
-
- // Repetitive task.
- void vATask( void * pvParameters )
- {
-    for( ;; )
-    {
-        // We want this task to run every 10 ticks of a timer.  The semaphore
-        // was created before this task was started.
-
-        // Block waiting for the semaphore to become available.
-        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
-        {
-            // It is time to execute.
-
-            // ...
-
-            // We have finished our task.  Return to the top of the loop where
-            // we will block on the semaphore until it is time to execute
-            // again.  Note when using the semaphore for synchronisation with an
-			// ISR in this manner there is no need to 'give' the semaphore back.
-        }
-    }
- }
-
- // Timer ISR
- void vTimerISR( void * pvParameters )
- {
- static uint8_t ucLocalTickCount = 0;
- static BaseType_t xHigherPriorityTaskWoken;
-
-    // A timer tick has occurred.
-
-    // ... Do other time functions.
-
-    // Is it time for vATask () to run?
-	xHigherPriorityTaskWoken = pdFALSE;
-    ucLocalTickCount++;
-    if( ucLocalTickCount >= TICKS_TO_WAIT )
-    {
-        // Unblock the task by releasing the semaphore.
-        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
-
-        // Reset the count so we release the semaphore again in 10 ticks time.
-        ucLocalTickCount = 0;
-    }
-
-    if( xHigherPriorityTaskWoken != pdFALSE )
-    {
-        // We can force a context switch here.  Context switching from an
-        // ISR uses port specific syntax.  Check the demo task for your port
-        // to find the syntax required.
-    }
- }
- 

- * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
- * \ingroup Semaphores
- */
-#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
-
-/**
- * semphr. h
- * 
- xSemaphoreTakeFromISR(
-                          SemaphoreHandle_t xSemaphore,
-                          BaseType_t *pxHigherPriorityTaskWoken
-                      )

- *
- * Macro to  take a semaphore from an ISR.  The semaphore must have
- * previously been created with a call to xSemaphoreCreateBinary() or
- * xSemaphoreCreateCounting().
- *
- * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
- * must not be used with this macro.
- *
- * This macro can be used from an ISR, however taking a semaphore from an ISR
- * is not a common operation.  It is likely to only be useful when taking a
- * counting semaphore when an interrupt is obtaining an object from a resource
- * pool (when the semaphore count indicates the number of resources available).
- *
- * @param xSemaphore A handle to the semaphore being taken.  This is the
- * handle returned when the semaphore was created.
- *
- * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
- * to unblock, and the unblocked task has a priority higher than the currently
- * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
- * a context switch should be requested before the interrupt is exited.
- *
- * @return pdTRUE if the semaphore was successfully taken, otherwise
- * pdFALSE
- */
-#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateMutex( void )

- *
- * Creates a new mutex type semaphore instance, and returns a handle by which
- * the new mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, mutex semaphores use a block
- * of memory, in which the mutex structure is stored.  If a mutex is created
- * using xSemaphoreCreateMutex() then the required memory is automatically
- * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
- * http://www.freertos.org/a00111.html).  If a mutex is created using
- * xSemaphoreCreateMutexStatic() then the application writer must provided the
- * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
- * without using any dynamic memory allocation.
- *
- * Mutexes created using this function can be accessed using the xSemaphoreTake()
- * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
- * xSemaphoreGiveRecursive() macros must not be used.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @return If the mutex was successfully created then a handle to the created
- * semaphore is returned.  If there was not enough heap to allocate the mutex
- * data structures then NULL is returned.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
-    // This is a macro so pass the variable in directly.
-    xSemaphore = xSemaphoreCreateMutex();
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.
-    }
- }
- 

- * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
- * \ingroup Semaphores
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
-#endif
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )

- *
- * Creates a new mutex type semaphore instance, and returns a handle by which
- * the new mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, mutex semaphores use a block
- * of memory, in which the mutex structure is stored.  If a mutex is created
- * using xSemaphoreCreateMutex() then the required memory is automatically
- * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
- * http://www.freertos.org/a00111.html).  If a mutex is created using
- * xSemaphoreCreateMutexStatic() then the application writer must provided the
- * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
- * without using any dynamic memory allocation.
- *
- * Mutexes created using this function can be accessed using the xSemaphoreTake()
- * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
- * xSemaphoreGiveRecursive() macros must not be used.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
- * which will be used to hold the mutex's data structure, removing the need for
- * the memory to be allocated dynamically.
- *
- * @return If the mutex was successfully created then a handle to the created
- * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore;
- StaticSemaphore_t xMutexBuffer;
-
- void vATask( void * pvParameters )
- {
-    // A mutex cannot be used before it has been created.  xMutexBuffer is
-    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
-    // attempted.
-    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
-
-    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
-    // so there is no need to check it.
- }
- 

- * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
- * \ingroup Semaphores
- */
- #if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )

- *
- * Creates a new recursive mutex type semaphore instance, and returns a handle
- * by which the new recursive mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, recursive mutexs use a block
- * of memory, in which the mutex structure is stored.  If a recursive mutex is
- * created using xSemaphoreCreateRecursiveMutex() then the required memory is
- * automatically dynamically allocated inside the
- * xSemaphoreCreateRecursiveMutex() function.  (see
- * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
- * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
- * provide the memory that will get used by the mutex.
- * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
- * be created without using any dynamic memory allocation.
- *
- * Mutexes created using this macro can be accessed using the
- * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
- * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
- * SemaphoreHandle_t.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore;
-
- void vATask( void * pvParameters )
- {
-    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
-    // This is a macro so pass the variable in directly.
-    xSemaphore = xSemaphoreCreateRecursiveMutex();
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.
-    }
- }
- 

- * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
- * \ingroup Semaphores
- */
-#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
-	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
-#endif
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )

- *
- * Creates a new recursive mutex type semaphore instance, and returns a handle
- * by which the new recursive mutex can be referenced.
- *
- * Internally, within the FreeRTOS implementation, recursive mutexs use a block
- * of memory, in which the mutex structure is stored.  If a recursive mutex is
- * created using xSemaphoreCreateRecursiveMutex() then the required memory is
- * automatically dynamically allocated inside the
- * xSemaphoreCreateRecursiveMutex() function.  (see
- * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
- * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
- * provide the memory that will get used by the mutex.
- * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
- * be created without using any dynamic memory allocation.
- *
- * Mutexes created using this macro can be accessed using the
- * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
- * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
- *
- * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
- * doesn't become available again until the owner has called
- * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
- * if a task successfully 'takes' the same mutex 5 times then the mutex will
- * not be available to any other task until it has also  'given' the mutex back
- * exactly five times.
- *
- * This type of semaphore uses a priority inheritance mechanism so a task
- * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
- * semaphore it is no longer required.
- *
- * Mutex type semaphores cannot be used from within interrupt service routines.
- *
- * See xSemaphoreCreateBinary() for an alternative implementation that can be
- * used for pure synchronisation (where one task or interrupt always 'gives' the
- * semaphore and another always 'takes' the semaphore) and from within interrupt
- * service routines.
- *
- * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
- * which will then be used to hold the recursive mutex's data structure,
- * removing the need for the memory to be allocated dynamically.
- *
- * @return If the recursive mutex was successfully created then a handle to the
- * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
- * returned.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore;
- StaticSemaphore_t xMutexBuffer;
-
- void vATask( void * pvParameters )
- {
-    // A recursive semaphore cannot be used before it is created.  Here a
-    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
-    // The address of xMutexBuffer is passed into the function, and will hold
-    // the mutexes data structures - so no dynamic memory allocation will be
-    // attempted.
-    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
-
-    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
-    // so there is no need to check it.
- }
- 

- * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
- * \ingroup Semaphores
- */
-#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
-	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )

- *
- * Creates a new counting semaphore instance, and returns a handle by which the
- * new counting semaphore can be referenced.
- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a counting semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, counting semaphores use a
- * block of memory, in which the counting semaphore structure is stored.  If a
- * counting semaphore is created using xSemaphoreCreateCounting() then the
- * required memory is automatically dynamically allocated inside the
- * xSemaphoreCreateCounting() function.  (see
- * http://www.freertos.org/a00111.html).  If a counting semaphore is created
- * using xSemaphoreCreateCountingStatic() then the application writer can
- * instead optionally provide the memory that will get used by the counting
- * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
- * semaphore to be created without using any dynamic memory allocation.
- *
- * Counting semaphores are typically used for two things:
- *
- * 1) Counting events.
- *
- *    In this usage scenario an event handler will 'give' a semaphore each time
- *    an event occurs (incrementing the semaphore count value), and a handler
- *    task will 'take' a semaphore each time it processes an event
- *    (decrementing the semaphore count value).  The count value is therefore
- *    the difference between the number of events that have occurred and the
- *    number that have been processed.  In this case it is desirable for the
- *    initial count value to be zero.
- *
- * 2) Resource management.
- *
- *    In this usage scenario the count value indicates the number of resources
- *    available.  To obtain control of a resource a task must first obtain a
- *    semaphore - decrementing the semaphore count value.  When the count value
- *    reaches zero there are no free resources.  When a task finishes with the
- *    resource it 'gives' the semaphore back - incrementing the semaphore count
- *    value.  In this case it is desirable for the initial count value to be
- *    equal to the maximum count value, indicating that all resources are free.
- *
- * @param uxMaxCount The maximum count value that can be reached.  When the
- *        semaphore reaches this value it can no longer be 'given'.
- *
- * @param uxInitialCount The count value assigned to the semaphore when it is
- *        created.
- *
- * @return Handle to the created semaphore.  Null if the semaphore could not be
- *         created.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore;
-
- void vATask( void * pvParameters )
- {
- SemaphoreHandle_t xSemaphore = NULL;
-
-    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
-    // The max value to which the semaphore can count should be 10, and the
-    // initial value assigned to the count should be 0.
-    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
-
-    if( xSemaphore != NULL )
-    {
-        // The semaphore was created successfully.
-        // The semaphore can now be used.
-    }
- }
- 

- * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
- * \ingroup Semaphores
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
-#endif
-
-/**
- * semphr. h
- * 
SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )

- *
- * Creates a new counting semaphore instance, and returns a handle by which the
- * new counting semaphore can be referenced.
- *
- * In many usage scenarios it is faster and more memory efficient to use a
- * direct to task notification in place of a counting semaphore!
- * http://www.freertos.org/RTOS-task-notifications.html
- *
- * Internally, within the FreeRTOS implementation, counting semaphores use a
- * block of memory, in which the counting semaphore structure is stored.  If a
- * counting semaphore is created using xSemaphoreCreateCounting() then the
- * required memory is automatically dynamically allocated inside the
- * xSemaphoreCreateCounting() function.  (see
- * http://www.freertos.org/a00111.html).  If a counting semaphore is created
- * using xSemaphoreCreateCountingStatic() then the application writer must
- * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
- * counting semaphore to be created without using any dynamic memory allocation.
- *
- * Counting semaphores are typically used for two things:
- *
- * 1) Counting events.
- *
- *    In this usage scenario an event handler will 'give' a semaphore each time
- *    an event occurs (incrementing the semaphore count value), and a handler
- *    task will 'take' a semaphore each time it processes an event
- *    (decrementing the semaphore count value).  The count value is therefore
- *    the difference between the number of events that have occurred and the
- *    number that have been processed.  In this case it is desirable for the
- *    initial count value to be zero.
- *
- * 2) Resource management.
- *
- *    In this usage scenario the count value indicates the number of resources
- *    available.  To obtain control of a resource a task must first obtain a
- *    semaphore - decrementing the semaphore count value.  When the count value
- *    reaches zero there are no free resources.  When a task finishes with the
- *    resource it 'gives' the semaphore back - incrementing the semaphore count
- *    value.  In this case it is desirable for the initial count value to be
- *    equal to the maximum count value, indicating that all resources are free.
- *
- * @param uxMaxCount The maximum count value that can be reached.  When the
- *        semaphore reaches this value it can no longer be 'given'.
- *
- * @param uxInitialCount The count value assigned to the semaphore when it is
- *        created.
- *
- * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
- * which will then be used to hold the semaphore's data structure, removing the
- * need for the memory to be allocated dynamically.
- *
- * @return If the counting semaphore was successfully created then a handle to
- * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
- * then NULL is returned.
- *
- * Example usage:
- 
- SemaphoreHandle_t xSemaphore;
- StaticSemaphore_t xSemaphoreBuffer;
-
- void vATask( void * pvParameters )
- {
- SemaphoreHandle_t xSemaphore = NULL;
-
-    // Counting semaphore cannot be used before they have been created.  Create
-    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
-    // value to which the semaphore can count is 10, and the initial value
-    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
-    // passed in and will be used to hold the semaphore structure, so no dynamic
-    // memory allocation will be used.
-    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
-
-    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
-    // is no need to check its value.
- }
- 

- * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
- * \ingroup Semaphores
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * semphr. h
- * 
void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );

- *
- * Delete a semaphore.  This function must be used with care.  For example,
- * do not delete a mutex type semaphore if the mutex is held by a task.
- *
- * @param xSemaphore A handle to the semaphore to be deleted.
- *
- * \defgroup vSemaphoreDelete vSemaphoreDelete
- * \ingroup Semaphores
- */
-#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
-
-/**
- * semphr.h
- * 
TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );

- *
- * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
- * If xMutex is not a mutex type semaphore, or the mutex is available (not held
- * by a task), return NULL.
- *
- * Note: This is a good way of determining if the calling task is the mutex
- * holder, but not a good way of determining the identity of the mutex holder as
- * the holder may change between the function exiting and the returned value
- * being tested.
- */
-#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
-
-/**
- * semphr.h
- * 
TaskHandle_t xSemaphoreGetMutexHolderFromISR( SemaphoreHandle_t xMutex );

- *
- * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
- * If xMutex is not a mutex type semaphore, or the mutex is available (not held
- * by a task), return NULL.
- *
- */
-#define xSemaphoreGetMutexHolderFromISR( xSemaphore ) xQueueGetMutexHolderFromISR( ( xSemaphore ) )
-
-/**
- * semphr.h
- * 
UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );

- *
- * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
- * its current count value.  If the semaphore is a binary semaphore then
- * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
- * semaphore is not available.
- *
- */
-#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
-
-#endif /* SEMAPHORE_H */
-
-
diff --git a/FreeRTOS/Source/include/stack_macros.h b/FreeRTOS/Source/include/stack_macros.h
deleted file mode 100755
index 18406bb..0000000
--- a/FreeRTOS/Source/include/stack_macros.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef STACK_MACROS_H
-#define STACK_MACROS_H
-
-/*
- * Call the stack overflow hook function if the stack of the task being swapped
- * out is currently overflowed, or looks like it might have overflowed in the
- * past.
- *
- * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
- * the current stack state only - comparing the current top of stack value to
- * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
- * will also cause the last few stack bytes to be checked to ensure the value
- * to which the bytes were set when the task was created have not been
- * overwritten.  Note this second test does not guarantee that an overflowed
- * stack will always be recognised.
- */
-
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
-
-	/* Only the current stack state is to be checked. */
-	#define taskCHECK_FOR_STACK_OVERFLOW()																\
-	{																									\
-		/* Is the currently saved stack pointer within the stack limit? */								\
-		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
-		}																								\
-	}
-
-#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
-
-	/* Only the current stack state is to be checked. */
-	#define taskCHECK_FOR_STACK_OVERFLOW()																\
-	{																									\
-																										\
-		/* Is the currently saved stack pointer within the stack limit? */								\
-		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
-		}																								\
-	}
-
-#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
-
-	#define taskCHECK_FOR_STACK_OVERFLOW()																\
-	{																									\
-		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
-		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
-																										\
-		if( ( pulStack[ 0 ] != ulCheckValue ) ||														\
-			( pulStack[ 1 ] != ulCheckValue ) ||														\
-			( pulStack[ 2 ] != ulCheckValue ) ||														\
-			( pulStack[ 3 ] != ulCheckValue ) )															\
-		{																								\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
-		}																								\
-	}
-
-#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
-/*-----------------------------------------------------------*/
-
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
-
-	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
-	{																																	\
-	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
-	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
-													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
-																																		\
-																																		\
-		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
-																																		\
-		/* Has the extremity of the task stack ever been written over? */																\
-		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
-		{																																\
-			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
-		}																																\
-	}
-
-#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
-/*-----------------------------------------------------------*/
-
-/* Remove stack overflow macro if not being used. */
-#ifndef taskCHECK_FOR_STACK_OVERFLOW
-	#define taskCHECK_FOR_STACK_OVERFLOW()
-#endif
-
-
-
-#endif /* STACK_MACROS_H */
-
diff --git a/FreeRTOS/Source/include/stream_buffer.h b/FreeRTOS/Source/include/stream_buffer.h
deleted file mode 100755
index 0f00119..0000000
--- a/FreeRTOS/Source/include/stream_buffer.h
+++ /dev/null
@@ -1,855 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * Stream buffers are used to send a continuous stream of data from one task or
- * interrupt to another.  Their implementation is light weight, making them
- * particularly suited for interrupt to task and core to core communication
- * scenarios.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferRead()) inside a critical section section and set the
- * receive block time to 0.
- *
- */
-
-#ifndef STREAM_BUFFER_H
-#define STREAM_BUFFER_H
-
-#if defined( __cplusplus )
-extern "C" {
-#endif
-
-/**
- * Type by which stream buffers are referenced.  For example, a call to
- * xStreamBufferCreate() returns an StreamBufferHandle_t variable that can
- * then be used as a parameter to xStreamBufferSend(), xStreamBufferReceive(),
- * etc.
- */
-struct StreamBufferDef_t;
-typedef struct StreamBufferDef_t * StreamBufferHandle_t;
-
-
-/**
- * message_buffer.h
- *
-
-StreamBufferHandle_t xStreamBufferCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes );
-

- *
- * Creates a new stream buffer using dynamically allocated memory.  See
- * xStreamBufferCreateStatic() for a version that uses statically allocated
- * memory (memory that is allocated at compile time).
- *
- * configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 or left undefined in
- * FreeRTOSConfig.h for xStreamBufferCreate() to be available.
- *
- * @param xBufferSizeBytes The total number of bytes the stream buffer will be
- * able to hold at any one time.
- *
- * @param xTriggerLevelBytes The number of bytes that must be in the stream
- * buffer before a task that is blocked on the stream buffer to wait for data is
- * moved out of the blocked state.  For example, if a task is blocked on a read
- * of an empty stream buffer that has a trigger level of 1 then the task will be
- * unblocked when a single byte is written to the buffer or the task's block
- * time expires.  As another example, if a task is blocked on a read of an empty
- * stream buffer that has a trigger level of 10 then the task will not be
- * unblocked until the stream buffer contains at least 10 bytes or the task's
- * block time expires.  If a reading task's block time expires before the
- * trigger level is reached then the task will still receive however many bytes
- * are actually available.  Setting a trigger level of 0 will result in a
- * trigger level of 1 being used.  It is not valid to specify a trigger level
- * that is greater than the buffer size.
- *
- * @return If NULL is returned, then the stream buffer cannot be created
- * because there is insufficient heap memory available for FreeRTOS to allocate
- * the stream buffer data structures and storage area.  A non-NULL value being
- * returned indicates that the stream buffer has been created successfully -
- * the returned value should be stored as the handle to the created stream
- * buffer.
- *
- * Example use:
-
-
-void vAFunction( void )
-{
-StreamBufferHandle_t xStreamBuffer;
-const size_t xStreamBufferSizeBytes = 100, xTriggerLevel = 10;
-
-    // Create a stream buffer that can hold 100 bytes.  The memory used to hold
-    // both the stream buffer structure and the data in the stream buffer is
-    // allocated dynamically.
-    xStreamBuffer = xStreamBufferCreate( xStreamBufferSizeBytes, xTriggerLevel );
-
-    if( xStreamBuffer == NULL )
-    {
-        // There was not enough heap memory space available to create the
-        // stream buffer.
-    }
-    else
-    {
-        // The stream buffer was created successfully and can now be used.
-    }
-}
-

- * \defgroup xStreamBufferCreate xStreamBufferCreate
- * \ingroup StreamBufferManagement
- */
-#define xStreamBufferCreate( xBufferSizeBytes, xTriggerLevelBytes ) xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE )
-
-/**
- * stream_buffer.h
- *
-
-StreamBufferHandle_t xStreamBufferCreateStatic( size_t xBufferSizeBytes,
-                                                size_t xTriggerLevelBytes,
-                                                uint8_t *pucStreamBufferStorageArea,
-                                                StaticStreamBuffer_t *pxStaticStreamBuffer );
-

- * Creates a new stream buffer using statically allocated memory.  See
- * xStreamBufferCreate() for a version that uses dynamically allocated memory.
- *
- * configSUPPORT_STATIC_ALLOCATION must be set to 1 in FreeRTOSConfig.h for
- * xStreamBufferCreateStatic() to be available.
- *
- * @param xBufferSizeBytes The size, in bytes, of the buffer pointed to by the
- * pucStreamBufferStorageArea parameter.
- *
- * @param xTriggerLevelBytes The number of bytes that must be in the stream
- * buffer before a task that is blocked on the stream buffer to wait for data is
- * moved out of the blocked state.  For example, if a task is blocked on a read
- * of an empty stream buffer that has a trigger level of 1 then the task will be
- * unblocked when a single byte is written to the buffer or the task's block
- * time expires.  As another example, if a task is blocked on a read of an empty
- * stream buffer that has a trigger level of 10 then the task will not be
- * unblocked until the stream buffer contains at least 10 bytes or the task's
- * block time expires.  If a reading task's block time expires before the
- * trigger level is reached then the task will still receive however many bytes
- * are actually available.  Setting a trigger level of 0 will result in a
- * trigger level of 1 being used.  It is not valid to specify a trigger level
- * that is greater than the buffer size.
- *
- * @param pucStreamBufferStorageArea Must point to a uint8_t array that is at
- * least xBufferSizeBytes + 1 big.  This is the array to which streams are
- * copied when they are written to the stream buffer.
- *
- * @param pxStaticStreamBuffer Must point to a variable of type
- * StaticStreamBuffer_t, which will be used to hold the stream buffer's data
- * structure.
- *
- * @return If the stream buffer is created successfully then a handle to the
- * created stream buffer is returned. If either pucStreamBufferStorageArea or
- * pxStaticstreamBuffer are NULL then NULL is returned.
- *
- * Example use:
-
-
-// Used to dimension the array used to hold the streams.  The available space
-// will actually be one less than this, so 999.
-#define STORAGE_SIZE_BYTES 1000
-
-// Defines the memory that will actually hold the streams within the stream
-// buffer.
-static uint8_t ucStorageBuffer[ STORAGE_SIZE_BYTES ];
-
-// The variable used to hold the stream buffer structure.
-StaticStreamBuffer_t xStreamBufferStruct;
-
-void MyFunction( void )
-{
-StreamBufferHandle_t xStreamBuffer;
-const size_t xTriggerLevel = 1;
-
-    xStreamBuffer = xStreamBufferCreateStatic( sizeof( ucBufferStorage ),
-                                               xTriggerLevel,
-                                               ucBufferStorage,
-                                               &xStreamBufferStruct );
-
-    // As neither the pucStreamBufferStorageArea or pxStaticStreamBuffer
-    // parameters were NULL, xStreamBuffer will not be NULL, and can be used to
-    // reference the created stream buffer in other stream buffer API calls.
-
-    // Other code that uses the stream buffer can go here.
-}
-
-

- * \defgroup xStreamBufferCreateStatic xStreamBufferCreateStatic
- * \ingroup StreamBufferManagement
- */
-#define xStreamBufferCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pucStreamBufferStorageArea, pxStaticStreamBuffer ) xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, pdFALSE, pucStreamBufferStorageArea, pxStaticStreamBuffer )
-
-/**
- * stream_buffer.h
- *
-
-size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-                          const void *pvTxData,
-                          size_t xDataLengthBytes,
-                          TickType_t xTicksToWait );
-

- *
- * Sends bytes to a stream buffer.  The bytes are copied into the stream buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
- * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
- * service routine (ISR).
- *
- * @param xStreamBuffer The handle of the stream buffer to which a stream is
- * being sent.
- *
- * @param pvTxData A pointer to the buffer that holds the bytes to be copied
- * into the stream buffer.
- *
- * @param xDataLengthBytes   The maximum number of bytes to copy from pvTxData
- * into the stream buffer.
- *
- * @param xTicksToWait The maximum amount of time the task should remain in the
- * Blocked state to wait for enough space to become available in the stream
- * buffer, should the stream buffer contain too little space to hold the
- * another xDataLengthBytes bytes.  The block time is specified in tick periods,
- * so the absolute time it represents is dependent on the tick frequency.  The
- * macro pdMS_TO_TICKS() can be used to convert a time specified in milliseconds
- * into a time specified in ticks.  Setting xTicksToWait to portMAX_DELAY will
- * cause the task to wait indefinitely (without timing out), provided
- * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h.  If a task times out
- * before it can write all xDataLengthBytes into the buffer it will still write
- * as many bytes as possible.  A task does not use any CPU time when it is in
- * the blocked state.
- *
- * @return The number of bytes written to the stream buffer.  If a task times
- * out before it can write all xDataLengthBytes into the buffer it will still
- * write as many bytes as possible.
- *
- * Example use:
-
-void vAFunction( StreamBufferHandle_t xStreamBuffer )
-{
-size_t xBytesSent;
-uint8_t ucArrayToSend[] = { 0, 1, 2, 3 };
-char *pcStringToSend = "String to send";
-const TickType_t x100ms = pdMS_TO_TICKS( 100 );
-
-    // Send an array to the stream buffer, blocking for a maximum of 100ms to
-    // wait for enough space to be available in the stream buffer.
-    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) ucArrayToSend, sizeof( ucArrayToSend ), x100ms );
-
-    if( xBytesSent != sizeof( ucArrayToSend ) )
-    {
-        // The call to xStreamBufferSend() times out before there was enough
-        // space in the buffer for the data to be written, but it did
-        // successfully write xBytesSent bytes.
-    }
-
-    // Send the string to the stream buffer.  Return immediately if there is not
-    // enough space in the buffer.
-    xBytesSent = xStreamBufferSend( xStreamBuffer, ( void * ) pcStringToSend, strlen( pcStringToSend ), 0 );
-
-    if( xBytesSent != strlen( pcStringToSend ) )
-    {
-        // The entire string could not be added to the stream buffer because
-        // there was not enough free space in the buffer, but xBytesSent bytes
-        // were sent.  Could try again to send the remaining bytes.
-    }
-}
-

- * \defgroup xStreamBufferSend xStreamBufferSend
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-						  const void *pvTxData,
-						  size_t xDataLengthBytes,
-						  TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
-                                 const void *pvTxData,
-                                 size_t xDataLengthBytes,
-                                 BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * Interrupt safe version of the API function that sends a stream of bytes to
- * the stream buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xStreamBufferSend() to write to a stream buffer from a task.  Use
- * xStreamBufferSendFromISR() to write to a stream buffer from an interrupt
- * service routine (ISR).
- *
- * @param xStreamBuffer The handle of the stream buffer to which a stream is
- * being sent.
- *
- * @param pvTxData A pointer to the data that is to be copied into the stream
- * buffer.
- *
- * @param xDataLengthBytes The maximum number of bytes to copy from pvTxData
- * into the stream buffer.
- *
- * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
- * have a task blocked on it waiting for data.  Calling
- * xStreamBufferSendFromISR() can make data available, and so cause a task that
- * was waiting for data to leave the Blocked state.  If calling
- * xStreamBufferSendFromISR() causes a task to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently executing task (the
- * task that was interrupted), then, internally, xStreamBufferSendFromISR()
- * will set *pxHigherPriorityTaskWoken to pdTRUE.  If
- * xStreamBufferSendFromISR() sets this value to pdTRUE, then normally a
- * context switch should be performed before the interrupt is exited.  This will
- * ensure that the interrupt returns directly to the highest priority Ready
- * state task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it
- * is passed into the function.  See the example code below for an example.
- *
- * @return The number of bytes actually written to the stream buffer, which will
- * be less than xDataLengthBytes if the stream buffer didn't have enough free
- * space for all the bytes to be written.
- *
- * Example use:
-
-// A stream buffer that has already been created.
-StreamBufferHandle_t xStreamBuffer;
-
-void vAnInterruptServiceRoutine( void )
-{
-size_t xBytesSent;
-char *pcStringToSend = "String to send";
-BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialised to pdFALSE.
-
-    // Attempt to send the string to the stream buffer.
-    xBytesSent = xStreamBufferSendFromISR( xStreamBuffer,
-                                           ( void * ) pcStringToSend,
-                                           strlen( pcStringToSend ),
-                                           &xHigherPriorityTaskWoken );
-
-    if( xBytesSent != strlen( pcStringToSend ) )
-    {
-        // There was not enough free space in the stream buffer for the entire
-        // string to be written, ut xBytesSent bytes were written.
-    }
-
-    // If xHigherPriorityTaskWoken was set to pdTRUE inside
-    // xStreamBufferSendFromISR() then a task that has a priority above the
-    // priority of the currently executing task was unblocked and a context
-    // switch should be performed to ensure the ISR returns to the unblocked
-    // task.  In most FreeRTOS ports this is done by simply passing
-    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
-    // variables value, and perform the context switch if necessary.  Check the
-    // documentation for the port in use for port specific instructions.
-    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-}
-

- * \defgroup xStreamBufferSendFromISR xStreamBufferSendFromISR
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
-								 const void *pvTxData,
-								 size_t xDataLengthBytes,
-								 BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-                             void *pvRxData,
-                             size_t xBufferLengthBytes,
-                             TickType_t xTicksToWait );
-

- *
- * Receives bytes from a stream buffer.
- *
- * ***NOTE***:  Uniquely among FreeRTOS objects, the stream buffer
- * implementation (so also the message buffer implementation, as message buffers
- * are built on top of stream buffers) assumes there is only one task or
- * interrupt that will write to the buffer (the writer), and only one task or
- * interrupt that will read from the buffer (the reader).  It is safe for the
- * writer and reader to be different tasks or interrupts, but, unlike other
- * FreeRTOS objects, it is not safe to have multiple different writers or
- * multiple different readers.  If there are to be multiple different writers
- * then the application writer must place each call to a writing API function
- * (such as xStreamBufferSend()) inside a critical section and set the send
- * block time to 0.  Likewise, if there are to be multiple different readers
- * then the application writer must place each call to a reading API function
- * (such as xStreamBufferRead()) inside a critical section and set the receive
- * block time to 0.
- *
- * Use xStreamBufferReceive() to read from a stream buffer from a task.  Use
- * xStreamBufferReceiveFromISR() to read from a stream buffer from an
- * interrupt service routine (ISR).
- *
- * @param xStreamBuffer The handle of the stream buffer from which bytes are to
- * be received.
- *
- * @param pvRxData A pointer to the buffer into which the received bytes will be
- * copied.
- *
- * @param xBufferLengthBytes The length of the buffer pointed to by the
- * pvRxData parameter.  This sets the maximum number of bytes to receive in one
- * call.  xStreamBufferReceive will return as many bytes as possible up to a
- * maximum set by xBufferLengthBytes.
- *
- * @param xTicksToWait The maximum amount of time the task should remain in the
- * Blocked state to wait for data to become available if the stream buffer is
- * empty.  xStreamBufferReceive() will return immediately if xTicksToWait is
- * zero.  The block time is specified in tick periods, so the absolute time it
- * represents is dependent on the tick frequency.  The macro pdMS_TO_TICKS() can
- * be used to convert a time specified in milliseconds into a time specified in
- * ticks.  Setting xTicksToWait to portMAX_DELAY will cause the task to wait
- * indefinitely (without timing out), provided INCLUDE_vTaskSuspend is set to 1
- * in FreeRTOSConfig.h.  A task does not use any CPU time when it is in the
- * Blocked state.
- *
- * @return The number of bytes actually read from the stream buffer, which will
- * be less than xBufferLengthBytes if the call to xStreamBufferReceive() timed
- * out before xBufferLengthBytes were available.
- *
- * Example use:
-
-void vAFunction( StreamBuffer_t xStreamBuffer )
-{
-uint8_t ucRxData[ 20 ];
-size_t xReceivedBytes;
-const TickType_t xBlockTime = pdMS_TO_TICKS( 20 );
-
-    // Receive up to another sizeof( ucRxData ) bytes from the stream buffer.
-    // Wait in the Blocked state (so not using any CPU processing time) for a
-    // maximum of 100ms for the full sizeof( ucRxData ) number of bytes to be
-    // available.
-    xReceivedBytes = xStreamBufferReceive( xStreamBuffer,
-                                           ( void * ) ucRxData,
-                                           sizeof( ucRxData ),
-                                           xBlockTime );
-
-    if( xReceivedBytes > 0 )
-    {
-        // A ucRxData contains another xRecievedBytes bytes of data, which can
-        // be processed here....
-    }
-}
-

- * \defgroup xStreamBufferReceive xStreamBufferReceive
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-							 void *pvRxData,
-							 size_t xBufferLengthBytes,
-							 TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
-                                    void *pvRxData,
-                                    size_t xBufferLengthBytes,
-                                    BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * An interrupt safe version of the API function that receives bytes from a
- * stream buffer.
- *
- * Use xStreamBufferReceive() to read bytes from a stream buffer from a task.
- * Use xStreamBufferReceiveFromISR() to read bytes from a stream buffer from an
- * interrupt service routine (ISR).
- *
- * @param xStreamBuffer The handle of the stream buffer from which a stream
- * is being received.
- *
- * @param pvRxData A pointer to the buffer into which the received bytes are
- * copied.
- *
- * @param xBufferLengthBytes The length of the buffer pointed to by the
- * pvRxData parameter.  This sets the maximum number of bytes to receive in one
- * call.  xStreamBufferReceive will return as many bytes as possible up to a
- * maximum set by xBufferLengthBytes.
- *
- * @param pxHigherPriorityTaskWoken  It is possible that a stream buffer will
- * have a task blocked on it waiting for space to become available.  Calling
- * xStreamBufferReceiveFromISR() can make space available, and so cause a task
- * that is waiting for space to leave the Blocked state.  If calling
- * xStreamBufferReceiveFromISR() causes a task to leave the Blocked state, and
- * the unblocked task has a priority higher than the currently executing task
- * (the task that was interrupted), then, internally,
- * xStreamBufferReceiveFromISR() will set *pxHigherPriorityTaskWoken to pdTRUE.
- * If xStreamBufferReceiveFromISR() sets this value to pdTRUE, then normally a
- * context switch should be performed before the interrupt is exited.  That will
- * ensure the interrupt returns directly to the highest priority Ready state
- * task.  *pxHigherPriorityTaskWoken should be set to pdFALSE before it is
- * passed into the function.  See the code example below for an example.
- *
- * @return The number of bytes read from the stream buffer, if any.
- *
- * Example use:
-
-// A stream buffer that has already been created.
-StreamBuffer_t xStreamBuffer;
-
-void vAnInterruptServiceRoutine( void )
-{
-uint8_t ucRxData[ 20 ];
-size_t xReceivedBytes;
-BaseType_t xHigherPriorityTaskWoken = pdFALSE;  // Initialised to pdFALSE.
-
-    // Receive the next stream from the stream buffer.
-    xReceivedBytes = xStreamBufferReceiveFromISR( xStreamBuffer,
-                                                  ( void * ) ucRxData,
-                                                  sizeof( ucRxData ),
-                                                  &xHigherPriorityTaskWoken );
-
-    if( xReceivedBytes > 0 )
-    {
-        // ucRxData contains xReceivedBytes read from the stream buffer.
-        // Process the stream here....
-    }
-
-    // If xHigherPriorityTaskWoken was set to pdTRUE inside
-    // xStreamBufferReceiveFromISR() then a task that has a priority above the
-    // priority of the currently executing task was unblocked and a context
-    // switch should be performed to ensure the ISR returns to the unblocked
-    // task.  In most FreeRTOS ports this is done by simply passing
-    // xHigherPriorityTaskWoken into taskYIELD_FROM_ISR(), which will test the
-    // variables value, and perform the context switch if necessary.  Check the
-    // documentation for the port in use for port specific instructions.
-    taskYIELD_FROM_ISR( xHigherPriorityTaskWoken );
-}
-

- * \defgroup xStreamBufferReceiveFromISR xStreamBufferReceiveFromISR
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
-									void *pvRxData,
-									size_t xBufferLengthBytes,
-									BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer );
-

- *
- * Deletes a stream buffer that was previously created using a call to
- * xStreamBufferCreate() or xStreamBufferCreateStatic().  If the stream
- * buffer was created using dynamic memory (that is, by xStreamBufferCreate()),
- * then the allocated memory is freed.
- *
- * A stream buffer handle must not be used after the stream buffer has been
- * deleted.
- *
- * @param xStreamBuffer The handle of the stream buffer to be deleted.
- *
- * \defgroup vStreamBufferDelete vStreamBufferDelete
- * \ingroup StreamBufferManagement
- */
-void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer );
-

- *
- * Queries a stream buffer to see if it is full.  A stream buffer is full if it
- * does not have any free space, and therefore cannot accept any more data.
- *
- * @param xStreamBuffer The handle of the stream buffer being queried.
- *
- * @return If the stream buffer is full then pdTRUE is returned.  Otherwise
- * pdFALSE is returned.
- *
- * \defgroup xStreamBufferIsFull xStreamBufferIsFull
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer );
-

- *
- * Queries a stream buffer to see if it is empty.  A stream buffer is empty if
- * it does not contain any data.
- *
- * @param xStreamBuffer The handle of the stream buffer being queried.
- *
- * @return If the stream buffer is empty then pdTRUE is returned.  Otherwise
- * pdFALSE is returned.
- *
- * \defgroup xStreamBufferIsEmpty xStreamBufferIsEmpty
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer );
-

- *
- * Resets a stream buffer to its initial, empty, state.  Any data that was in
- * the stream buffer is discarded.  A stream buffer can only be reset if there
- * are no tasks blocked waiting to either send to or receive from the stream
- * buffer.
- *
- * @param xStreamBuffer The handle of the stream buffer being reset.
- *
- * @return If the stream buffer is reset then pdPASS is returned.  If there was
- * a task blocked waiting to send to or read from the stream buffer then the
- * stream buffer is not reset and pdFAIL is returned.
- *
- * \defgroup xStreamBufferReset xStreamBufferReset
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer );
-

- *
- * Queries a stream buffer to see how much free space it contains, which is
- * equal to the amount of data that can be sent to the stream buffer before it
- * is full.
- *
- * @param xStreamBuffer The handle of the stream buffer being queried.
- *
- * @return The number of bytes that can be written to the stream buffer before
- * the stream buffer would be full.
- *
- * \defgroup xStreamBufferSpacesAvailable xStreamBufferSpacesAvailable
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer );
-

- *
- * Queries a stream buffer to see how much data it contains, which is equal to
- * the number of bytes that can be read from the stream buffer before the stream
- * buffer would be empty.
- *
- * @param xStreamBuffer The handle of the stream buffer being queried.
- *
- * @return The number of bytes that can be read from the stream buffer before
- * the stream buffer would be empty.
- *
- * \defgroup xStreamBufferBytesAvailable xStreamBufferBytesAvailable
- * \ingroup StreamBufferManagement
- */
-size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel );
-

- *
- * A stream buffer's trigger level is the number of bytes that must be in the
- * stream buffer before a task that is blocked on the stream buffer to
- * wait for data is moved out of the blocked state.  For example, if a task is
- * blocked on a read of an empty stream buffer that has a trigger level of 1
- * then the task will be unblocked when a single byte is written to the buffer
- * or the task's block time expires.  As another example, if a task is blocked
- * on a read of an empty stream buffer that has a trigger level of 10 then the
- * task will not be unblocked until the stream buffer contains at least 10 bytes
- * or the task's block time expires.  If a reading task's block time expires
- * before the trigger level is reached then the task will still receive however
- * many bytes are actually available.  Setting a trigger level of 0 will result
- * in a trigger level of 1 being used.  It is not valid to specify a trigger
- * level that is greater than the buffer size.
- *
- * A trigger level is set when the stream buffer is created, and can be modified
- * using xStreamBufferSetTriggerLevel().
- *
- * @param xStreamBuffer The handle of the stream buffer being updated.
- *
- * @param xTriggerLevel The new trigger level for the stream buffer.
- *
- * @return If xTriggerLevel was less than or equal to the stream buffer's length
- * then the trigger level will be updated and pdTRUE is returned.  Otherwise
- * pdFALSE is returned.
- *
- * \defgroup xStreamBufferSetTriggerLevel xStreamBufferSetTriggerLevel
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * For advanced users only.
- *
- * The sbSEND_COMPLETED() macro is called from within the FreeRTOS APIs when
- * data is sent to a message buffer or stream buffer.  If there was a task that
- * was blocked on the message or stream buffer waiting for data to arrive then
- * the sbSEND_COMPLETED() macro sends a notification to the task to remove it
- * from the Blocked state.  xStreamBufferSendCompletedFromISR() does the same
- * thing.  It is provided to enable application writers to implement their own
- * version of sbSEND_COMPLETED(), and MUST NOT BE USED AT ANY OTHER TIME.
- *
- * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
- * additional information.
- *
- * @param xStreamBuffer The handle of the stream buffer to which data was
- * written.
- *
- * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
- * initialised to pdFALSE before it is passed into
- * xStreamBufferSendCompletedFromISR().  If calling
- * xStreamBufferSendCompletedFromISR() removes a task from the Blocked state,
- * and the task has a priority above the priority of the currently running task,
- * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
- * context switch should be performed before exiting the ISR.
- *
- * @return If a task was removed from the Blocked state then pdTRUE is returned.
- * Otherwise pdFALSE is returned.
- *
- * \defgroup xStreamBufferSendCompletedFromISR xStreamBufferSendCompletedFromISR
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * stream_buffer.h
- *
-
-BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken );
-

- *
- * For advanced users only.
- *
- * The sbRECEIVE_COMPLETED() macro is called from within the FreeRTOS APIs when
- * data is read out of a message buffer or stream buffer.  If there was a task
- * that was blocked on the message or stream buffer waiting for data to arrive
- * then the sbRECEIVE_COMPLETED() macro sends a notification to the task to
- * remove it from the Blocked state.  xStreamBufferReceiveCompletedFromISR()
- * does the same thing.  It is provided to enable application writers to
- * implement their own version of sbRECEIVE_COMPLETED(), and MUST NOT BE USED AT
- * ANY OTHER TIME.
- *
- * See the example implemented in FreeRTOS/Demo/Minimal/MessageBufferAMP.c for
- * additional information.
- *
- * @param xStreamBuffer The handle of the stream buffer from which data was
- * read.
- *
- * @param pxHigherPriorityTaskWoken *pxHigherPriorityTaskWoken should be
- * initialised to pdFALSE before it is passed into
- * xStreamBufferReceiveCompletedFromISR().  If calling
- * xStreamBufferReceiveCompletedFromISR() removes a task from the Blocked state,
- * and the task has a priority above the priority of the currently running task,
- * then *pxHigherPriorityTaskWoken will get set to pdTRUE indicating that a
- * context switch should be performed before exiting the ISR.
- *
- * @return If a task was removed from the Blocked state then pdTRUE is returned.
- * Otherwise pdFALSE is returned.
- *
- * \defgroup xStreamBufferReceiveCompletedFromISR xStreamBufferReceiveCompletedFromISR
- * \ingroup StreamBufferManagement
- */
-BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/* Functions below here are not part of the public API. */
-StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes,
-												 size_t xTriggerLevelBytes,
-												 BaseType_t xIsMessageBuffer ) PRIVILEGED_FUNCTION;
-
-StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
-													   size_t xTriggerLevelBytes,
-													   BaseType_t xIsMessageBuffer,
-													   uint8_t * const pucStreamBufferStorageArea,
-													   StaticStreamBuffer_t * const pxStaticStreamBuffer ) PRIVILEGED_FUNCTION;
-
-size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-
-#if( configUSE_TRACE_FACILITY == 1 )
-	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber ) PRIVILEGED_FUNCTION;
-	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer ) PRIVILEGED_FUNCTION;
-#endif
-
-#if defined( __cplusplus )
-}
-#endif
-
-#endif	/* !defined( STREAM_BUFFER_H ) */
diff --git a/FreeRTOS/Source/include/task.h b/FreeRTOS/Source/include/task.h
deleted file mode 100755
index 4174cbb..0000000
--- a/FreeRTOS/Source/include/task.h
+++ /dev/null
@@ -1,2421 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef INC_TASK_H
-#define INC_TASK_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h must appear in source files before include task.h"
-#endif
-
-#include "list.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * MACROS AND DEFINITIONS
- *----------------------------------------------------------*/
-
-#define tskKERNEL_VERSION_NUMBER "V10.2.1"
-#define tskKERNEL_VERSION_MAJOR 10
-#define tskKERNEL_VERSION_MINOR 2
-#define tskKERNEL_VERSION_BUILD 1
-
-/* MPU region parameters passed in ulParameters
- * of MemoryRegion_t struct. */
-#define tskMPU_REGION_READ_ONLY			( 1UL << 0UL )
-#define tskMPU_REGION_READ_WRITE		( 1UL << 1UL )
-#define tskMPU_REGION_EXECUTE_NEVER		( 1UL << 2UL )
-#define tskMPU_REGION_NORMAL_MEMORY		( 1UL << 3UL )
-#define tskMPU_REGION_DEVICE_MEMORY		( 1UL << 4UL )
-
-/**
- * task. h
- *
- * Type by which tasks are referenced.  For example, a call to xTaskCreate
- * returns (via a pointer parameter) an TaskHandle_t variable that can then
- * be used as a parameter to vTaskDelete to delete the task.
- *
- * \defgroup TaskHandle_t TaskHandle_t
- * \ingroup Tasks
- */
-struct tskTaskControlBlock; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
-typedef struct tskTaskControlBlock* TaskHandle_t;
-
-/*
- * Defines the prototype to which the application task hook function must
- * conform.
- */
-typedef BaseType_t (*TaskHookFunction_t)( void * );
-
-/* Task states returned by eTaskGetState. */
-typedef enum
-{
-	eRunning = 0,	/* A task is querying the state of itself, so must be running. */
-	eReady,			/* The task being queried is in a read or pending ready list. */
-	eBlocked,		/* The task being queried is in the Blocked state. */
-	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
-	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
-	eInvalid		/* Used as an 'invalid state' value. */
-} eTaskState;
-
-/* Actions that can be performed when vTaskNotify() is called. */
-typedef enum
-{
-	eNoAction = 0,				/* Notify the task without updating its notify value. */
-	eSetBits,					/* Set bits in the task's notification value. */
-	eIncrement,					/* Increment the task's notification value. */
-	eSetValueWithOverwrite,		/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
-	eSetValueWithoutOverwrite	/* Set the task's notification value if the previous value has been read by the task. */
-} eNotifyAction;
-
-/*
- * Used internally only.
- */
-typedef struct xTIME_OUT
-{
-	BaseType_t xOverflowCount;
-	TickType_t xTimeOnEntering;
-} TimeOut_t;
-
-/*
- * Defines the memory ranges allocated to the task when an MPU is used.
- */
-typedef struct xMEMORY_REGION
-{
-	void *pvBaseAddress;
-	uint32_t ulLengthInBytes;
-	uint32_t ulParameters;
-} MemoryRegion_t;
-
-/*
- * Parameters required to create an MPU protected task.
- */
-typedef struct xTASK_PARAMETERS
-{
-	TaskFunction_t pvTaskCode;
-	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	configSTACK_DEPTH_TYPE usStackDepth;
-	void *pvParameters;
-	UBaseType_t uxPriority;
-	StackType_t *puxStackBuffer;
-	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
-	#if ( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-		StaticTask_t * const pxTaskBuffer;
-	#endif
-} TaskParameters_t;
-
-/* Used with the uxTaskGetSystemState() function to return the state of each task
-in the system. */
-typedef struct xTASK_STATUS
-{
-	TaskHandle_t xHandle;			/* The handle of the task to which the rest of the information in the structure relates. */
-	const char *pcTaskName;			/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	UBaseType_t xTaskNumber;		/* A number unique to the task. */
-	eTaskState eCurrentState;		/* The state in which the task existed when the structure was populated. */
-	UBaseType_t uxCurrentPriority;	/* The priority at which the task was running (may be inherited) when the structure was populated. */
-	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
-	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
-	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
-	configSTACK_DEPTH_TYPE usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
-} TaskStatus_t;
-
-/* Possible return values for eTaskConfirmSleepModeStatus(). */
-typedef enum
-{
-	eAbortSleep = 0,		/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
-	eStandardSleep,			/* Enter a sleep mode that will not last any longer than the expected idle time. */
-	eNoTasksWaitingTimeout	/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
-} eSleepModeStatus;
-
-/**
- * Defines the priority used by the idle task.  This must not be modified.
- *
- * \ingroup TaskUtils
- */
-#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
-
-/**
- * task. h
- *
- * Macro for forcing a context switch.
- *
- * \defgroup taskYIELD taskYIELD
- * \ingroup SchedulerControl
- */
-#define taskYIELD()					portYIELD()
-
-/**
- * task. h
- *
- * Macro to mark the start of a critical code region.  Preemptive context
- * switches cannot occur when in a critical region.
- *
- * NOTE: This may alter the stack (depending on the portable implementation)
- * so must be used with care!
- *
- * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
- * \ingroup SchedulerControl
- */
-#define taskENTER_CRITICAL()		portENTER_CRITICAL()
-#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
-
-/**
- * task. h
- *
- * Macro to mark the end of a critical code region.  Preemptive context
- * switches cannot occur when in a critical region.
- *
- * NOTE: This may alter the stack (depending on the portable implementation)
- * so must be used with care!
- *
- * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
- * \ingroup SchedulerControl
- */
-#define taskEXIT_CRITICAL()			portEXIT_CRITICAL()
-#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
-/**
- * task. h
- *
- * Macro to disable all maskable interrupts.
- *
- * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
- * \ingroup SchedulerControl
- */
-#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
-
-/**
- * task. h
- *
- * Macro to enable microcontroller interrupts.
- *
- * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
- * \ingroup SchedulerControl
- */
-#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
-
-/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
-0 to generate more optimal code when configASSERT() is defined as the constant
-is used in assert() statements. */
-#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
-#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
-#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
-
-
-/*-----------------------------------------------------------
- * TASK CREATION API
- *----------------------------------------------------------*/
-
-/**
- * task. h
- *
- BaseType_t xTaskCreate(
-							  TaskFunction_t pvTaskCode,
-							  const char * const pcName,
-							  configSTACK_DEPTH_TYPE usStackDepth,
-							  void *pvParameters,
-							  UBaseType_t uxPriority,
-							  TaskHandle_t *pvCreatedTask
-						  );

- *
- * Create a new task and add it to the list of tasks that are ready to run.
- *
- * Internally, within the FreeRTOS implementation, tasks use two blocks of
- * memory.  The first block is used to hold the task's data structures.  The
- * second block is used by the task as its stack.  If a task is created using
- * xTaskCreate() then both blocks of memory are automatically dynamically
- * allocated inside the xTaskCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a task is created using
- * xTaskCreateStatic() then the application writer must provide the required
- * memory.  xTaskCreateStatic() therefore allows a task to be created without
- * using any dynamic memory allocation.
- *
- * See xTaskCreateStatic() for a version that does not use any dynamic memory
- * allocation.
- *
- * xTaskCreate() can only be used to create a task that has unrestricted
- * access to the entire microcontroller memory map.  Systems that include MPU
- * support can alternatively create an MPU constrained task using
- * xTaskCreateRestricted().
- *
- * @param pvTaskCode Pointer to the task entry function.  Tasks
- * must be implemented to never return (i.e. continuous loop).
- *
- * @param pcName A descriptive name for the task.  This is mainly used to
- * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
- * is 16.
- *
- * @param usStackDepth The size of the task stack specified as the number of
- * variables the stack can hold - not the number of bytes.  For example, if
- * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
- * will be allocated for stack storage.
- *
- * @param pvParameters Pointer that will be used as the parameter for the task
- * being created.
- *
- * @param uxPriority The priority at which the task should run.  Systems that
- * include MPU support can optionally create tasks in a privileged (system)
- * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
- * example, to create a privileged task at priority 2 the uxPriority parameter
- * should be set to ( 2 | portPRIVILEGE_BIT ).
- *
- * @param pvCreatedTask Used to pass back a handle by which the created task
- * can be referenced.
- *
- * @return pdPASS if the task was successfully created and added to a ready
- * list, otherwise an error code defined in the file projdefs.h
- *
- * Example usage:
-   
- // Task to be created.
- void vTaskCode( void * pvParameters )
- {
-	 for( ;; )
-	 {
-		 // Task code goes here.
-	 }
- }
-
- // Function that creates a task.
- void vOtherFunction( void )
- {
- static uint8_t ucParameterToPass;
- TaskHandle_t xHandle = NULL;
-
-	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
-	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
-	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
-	 // the new task attempts to access it.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
-     configASSERT( xHandle );
-
-	 // Use the handle to delete the task.
-     if( xHandle != NULL )
-     {
-	     vTaskDelete( xHandle );
-     }
- }
-   

- * \defgroup xTaskCreate xTaskCreate
- * \ingroup Tasks
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
-							const char * const pcName,	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-							const configSTACK_DEPTH_TYPE usStackDepth,
-							void * const pvParameters,
-							UBaseType_t uxPriority,
-							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * task. h
- *
- TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
-								 const char * const pcName,
-								 uint32_t ulStackDepth,
-								 void *pvParameters,
-								 UBaseType_t uxPriority,
-								 StackType_t *pxStackBuffer,
-								 StaticTask_t *pxTaskBuffer );

- *
- * Create a new task and add it to the list of tasks that are ready to run.
- *
- * Internally, within the FreeRTOS implementation, tasks use two blocks of
- * memory.  The first block is used to hold the task's data structures.  The
- * second block is used by the task as its stack.  If a task is created using
- * xTaskCreate() then both blocks of memory are automatically dynamically
- * allocated inside the xTaskCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a task is created using
- * xTaskCreateStatic() then the application writer must provide the required
- * memory.  xTaskCreateStatic() therefore allows a task to be created without
- * using any dynamic memory allocation.
- *
- * @param pvTaskCode Pointer to the task entry function.  Tasks
- * must be implemented to never return (i.e. continuous loop).
- *
- * @param pcName A descriptive name for the task.  This is mainly used to
- * facilitate debugging.  The maximum length of the string is defined by
- * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
- *
- * @param ulStackDepth The size of the task stack specified as the number of
- * variables the stack can hold - not the number of bytes.  For example, if
- * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
- * will be allocated for stack storage.
- *
- * @param pvParameters Pointer that will be used as the parameter for the task
- * being created.
- *
- * @param uxPriority The priority at which the task will run.
- *
- * @param pxStackBuffer Must point to a StackType_t array that has at least
- * ulStackDepth indexes - the array will then be used as the task's stack,
- * removing the need for the stack to be allocated dynamically.
- *
- * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
- * then be used to hold the task's data structures, removing the need for the
- * memory to be allocated dynamically.
- *
- * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
- * be created and a handle to the created task is returned.  If either
- * pxStackBuffer or pxTaskBuffer are NULL then the task will not be created and
- * NULL is returned.
- *
- * Example usage:
-   
-
-    // Dimensions the buffer that the task being created will use as its stack.
-    // NOTE:  This is the number of words the stack will hold, not the number of
-    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
-    // then 400 bytes (100 * 32-bits) will be allocated.
-    #define STACK_SIZE 200
-
-    // Structure that will hold the TCB of the task being created.
-    StaticTask_t xTaskBuffer;
-
-    // Buffer that the task being created will use as its stack.  Note this is
-    // an array of StackType_t variables.  The size of StackType_t is dependent on
-    // the RTOS port.
-    StackType_t xStack[ STACK_SIZE ];
-
-    // Function that implements the task being created.
-    void vTaskCode( void * pvParameters )
-    {
-        // The parameter value is expected to be 1 as 1 is passed in the
-        // pvParameters value in the call to xTaskCreateStatic().
-        configASSERT( ( uint32_t ) pvParameters == 1UL );
-
-        for( ;; )
-        {
-            // Task code goes here.
-        }
-    }
-
-    // Function that creates a task.
-    void vOtherFunction( void )
-    {
-        TaskHandle_t xHandle = NULL;
-
-        // Create the task without using any dynamic memory allocation.
-        xHandle = xTaskCreateStatic(
-                      vTaskCode,       // Function that implements the task.
-                      "NAME",          // Text name for the task.
-                      STACK_SIZE,      // Stack size in words, not bytes.
-                      ( void * ) 1,    // Parameter passed into the task.
-                      tskIDLE_PRIORITY,// Priority at which the task is created.
-                      xStack,          // Array to use as the task's stack.
-                      &xTaskBuffer );  // Variable to hold the task's data structure.
-
-        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
-        // been created, and xHandle will be the task's handle.  Use the handle
-        // to suspend the task.
-        vTaskSuspend( xHandle );
-    }
-   

- * \defgroup xTaskCreateStatic xTaskCreateStatic
- * \ingroup Tasks
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
-									const char * const pcName, /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-									const uint32_t ulStackDepth,
-									void * const pvParameters,
-									UBaseType_t uxPriority,
-									StackType_t * const puxStackBuffer,
-									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION;
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * task. h
- *
- BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

- *
- * Only available when configSUPPORT_DYNAMIC_ALLOCATION is set to 1.
- *
- * xTaskCreateRestricted() should only be used in systems that include an MPU
- * implementation.
- *
- * Create a new task and add it to the list of tasks that are ready to run.
- * The function parameters define the memory regions and associated access
- * permissions allocated to the task.
- *
- * See xTaskCreateRestrictedStatic() for a version that does not use any
- * dynamic memory allocation.
- *
- * @param pxTaskDefinition Pointer to a structure that contains a member
- * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
- * documentation) plus an optional stack buffer and the memory region
- * definitions.
- *
- * @param pxCreatedTask Used to pass back a handle by which the created task
- * can be referenced.
- *
- * @return pdPASS if the task was successfully created and added to a ready
- * list, otherwise an error code defined in the file projdefs.h
- *
- * Example usage:
-   
-// Create an TaskParameters_t structure that defines the task to be created.
-static const TaskParameters_t xCheckTaskParameters =
-{
-	vATask,		// pvTaskCode - the function that implements the task.
-	"ATask",	// pcName - just a text name for the task to assist debugging.
-	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
-	NULL,		// pvParameters - passed into the task function as the function parameters.
-	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
-	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
-
-	// xRegions - Allocate up to three separate memory regions for access by
-	// the task, with appropriate access permissions.  Different processors have
-	// different memory alignment requirements - refer to the FreeRTOS documentation
-	// for full information.
-	{
-		// Base address					Length	Parameters
-        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
-        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
-        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
-	}
-};
-
-int main( void )
-{
-TaskHandle_t xHandle;
-
-	// Create a task from the const structure defined above.  The task handle
-	// is requested (the second parameter is not NULL) but in this case just for
-	// demonstration purposes as its not actually used.
-	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
-
-	// Start the scheduler.
-	vTaskStartScheduler();
-
-	// Will only get here if there was insufficient memory to create the idle
-	// and/or timer task.
-	for( ;; );
-}
-   

- * \defgroup xTaskCreateRestricted xTaskCreateRestricted
- * \ingroup Tasks
- */
-#if( portUSING_MPU_WRAPPERS == 1 )
-	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * task. h
- *
- BaseType_t xTaskCreateRestrictedStatic( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );

- *
- * Only available when configSUPPORT_STATIC_ALLOCATION is set to 1.
- *
- * xTaskCreateRestrictedStatic() should only be used in systems that include an
- * MPU implementation.
- *
- * Internally, within the FreeRTOS implementation, tasks use two blocks of
- * memory.  The first block is used to hold the task's data structures.  The
- * second block is used by the task as its stack.  If a task is created using
- * xTaskCreateRestricted() then the stack is provided by the application writer,
- * and the memory used to hold the task's data structure is automatically
- * dynamically allocated inside the xTaskCreateRestricted() function.  If a task
- * is created using xTaskCreateRestrictedStatic() then the application writer
- * must provide the memory used to hold the task's data structures too.
- * xTaskCreateRestrictedStatic() therefore allows a memory protected task to be
- * created without using any dynamic memory allocation.
- *
- * @param pxTaskDefinition Pointer to a structure that contains a member
- * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
- * documentation) plus an optional stack buffer and the memory region
- * definitions.  If configSUPPORT_STATIC_ALLOCATION is set to 1 the structure
- * contains an additional member, which is used to point to a variable of type
- * StaticTask_t - which is then used to hold the task's data structure.
- *
- * @param pxCreatedTask Used to pass back a handle by which the created task
- * can be referenced.
- *
- * @return pdPASS if the task was successfully created and added to a ready
- * list, otherwise an error code defined in the file projdefs.h
- *
- * Example usage:
-   
-// Create an TaskParameters_t structure that defines the task to be created.
-// The StaticTask_t variable is only included in the structure when
-// configSUPPORT_STATIC_ALLOCATION is set to 1.  The PRIVILEGED_DATA macro can
-// be used to force the variable into the RTOS kernel's privileged data area.
-static PRIVILEGED_DATA StaticTask_t xTaskBuffer;
-static const TaskParameters_t xCheckTaskParameters =
-{
-	vATask,		// pvTaskCode - the function that implements the task.
-	"ATask",	// pcName - just a text name for the task to assist debugging.
-	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
-	NULL,		// pvParameters - passed into the task function as the function parameters.
-	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
-	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
-
-	// xRegions - Allocate up to three separate memory regions for access by
-	// the task, with appropriate access permissions.  Different processors have
-	// different memory alignment requirements - refer to the FreeRTOS documentation
-	// for full information.
-	{
-		// Base address					Length	Parameters
-        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
-        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
-        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
-	}
-
-	&xTaskBuffer; // Holds the task's data structure.
-};
-
-int main( void )
-{
-TaskHandle_t xHandle;
-
-	// Create a task from the const structure defined above.  The task handle
-	// is requested (the second parameter is not NULL) but in this case just for
-	// demonstration purposes as its not actually used.
-	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
-
-	// Start the scheduler.
-	vTaskStartScheduler();
-
-	// Will only get here if there was insufficient memory to create the idle
-	// and/or timer task.
-	for( ;; );
-}
-   

- * \defgroup xTaskCreateRestrictedStatic xTaskCreateRestrictedStatic
- * \ingroup Tasks
- */
-#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * task. h
- *
- void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );

- *
- * Memory regions are assigned to a restricted task when the task is created by
- * a call to xTaskCreateRestricted().  These regions can be redefined using
- * vTaskAllocateMPURegions().
- *
- * @param xTask The handle of the task being updated.
- *
- * @param xRegions A pointer to an MemoryRegion_t structure that contains the
- * new memory region definitions.
- *
- * Example usage:
-   
-// Define an array of MemoryRegion_t structures that configures an MPU region
-// allowing read/write access for 1024 bytes starting at the beginning of the
-// ucOneKByte array.  The other two of the maximum 3 definable regions are
-// unused so set to zero.
-static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
-{
-	// Base address		Length		Parameters
-	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
-	{ 0,				0,			0 },
-	{ 0,				0,			0 }
-};
-
-void vATask( void *pvParameters )
-{
-	// This task was created such that it has access to certain regions of
-	// memory as defined by the MPU configuration.  At some point it is
-	// desired that these MPU regions are replaced with that defined in the
-	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
-	// for this purpose.  NULL is used as the task handle to indicate that this
-	// function should modify the MPU regions of the calling task.
-	vTaskAllocateMPURegions( NULL, xAltRegions );
-
-	// Now the task can continue its function, but from this point on can only
-	// access its stack and the ucOneKByte array (unless any other statically
-	// defined or shared regions have been declared elsewhere).
-}
-   

- * \defgroup xTaskCreateRestricted xTaskCreateRestricted
- * \ingroup Tasks
- */
-void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskDelete( TaskHandle_t xTask );

- *
- * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Remove a task from the RTOS real time kernel's management.  The task being
- * deleted will be removed from all ready, blocked, suspended and event lists.
- *
- * NOTE:  The idle task is responsible for freeing the kernel allocated
- * memory from tasks that have been deleted.  It is therefore important that
- * the idle task is not starved of microcontroller processing time if your
- * application makes any calls to vTaskDelete ().  Memory allocated by the
- * task code is not automatically freed, and should be freed before the task
- * is deleted.
- *
- * See the demo application file death.c for sample code that utilises
- * vTaskDelete ().
- *
- * @param xTask The handle of the task to be deleted.  Passing NULL will
- * cause the calling task to be deleted.
- *
- * Example usage:
-   
- void vOtherFunction( void )
- {
- TaskHandle_t xHandle;
-
-	 // Create the task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // Use the handle to delete the task.
-	 vTaskDelete( xHandle );
- }
-   

- * \defgroup vTaskDelete vTaskDelete
- * \ingroup Tasks
- */
-void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------
- * TASK CONTROL API
- *----------------------------------------------------------*/
-
-/**
- * task. h
- * 
void vTaskDelay( const TickType_t xTicksToDelay );

- *
- * Delay a task for a given number of ticks.  The actual time that the
- * task remains blocked depends on the tick rate.  The constant
- * portTICK_PERIOD_MS can be used to calculate real time from the tick
- * rate - with the resolution of one tick period.
- *
- * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- *
- * vTaskDelay() specifies a time at which the task wishes to unblock relative to
- * the time at which vTaskDelay() is called.  For example, specifying a block
- * period of 100 ticks will cause the task to unblock 100 ticks after
- * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
- * of controlling the frequency of a periodic task as the path taken through the
- * code, as well as other task and interrupt activity, will effect the frequency
- * at which vTaskDelay() gets called and therefore the time at which the task
- * next executes.  See vTaskDelayUntil() for an alternative API function designed
- * to facilitate fixed frequency execution.  It does this by specifying an
- * absolute time (rather than a relative time) at which the calling task should
- * unblock.
- *
- * @param xTicksToDelay The amount of time, in tick periods, that
- * the calling task should block.
- *
- * Example usage:
-
- void vTaskFunction( void * pvParameters )
- {
- // Block for 500ms.
- const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
-
-	 for( ;; )
-	 {
-		 // Simply toggle the LED every 500ms, blocking between each toggle.
-		 vToggleLED();
-		 vTaskDelay( xDelay );
-	 }
- }
-
- * \defgroup vTaskDelay vTaskDelay
- * \ingroup TaskCtrl
- */
-void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );

- *
- * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Delay a task until a specified time.  This function can be used by periodic
- * tasks to ensure a constant execution frequency.
- *
- * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
- * cause a task to block for the specified number of ticks from the time vTaskDelay () is
- * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
- * execution frequency as the time between a task starting to execute and that task
- * calling vTaskDelay () may not be fixed [the task may take a different path though the
- * code between calls, or may get interrupted or preempted a different number of times
- * each time it executes].
- *
- * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
- * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
- * unblock.
- *
- * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
- * rate - with the resolution of one tick period.
- *
- * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
- * task was last unblocked.  The variable must be initialised with the current time
- * prior to its first use (see the example below).  Following this the variable is
- * automatically updated within vTaskDelayUntil ().
- *
- * @param xTimeIncrement The cycle time period.  The task will be unblocked at
- * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
- * same xTimeIncrement parameter value will cause the task to execute with
- * a fixed interface period.
- *
- * Example usage:
-   
- // Perform an action every 10 ticks.
- void vTaskFunction( void * pvParameters )
- {
- TickType_t xLastWakeTime;
- const TickType_t xFrequency = 10;
-
-	 // Initialise the xLastWakeTime variable with the current time.
-	 xLastWakeTime = xTaskGetTickCount ();
-	 for( ;; )
-	 {
-		 // Wait for the next cycle.
-		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
-
-		 // Perform action here.
-	 }
- }
-   

- * \defgroup vTaskDelayUntil vTaskDelayUntil
- * \ingroup TaskCtrl
- */
-void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
BaseType_t xTaskAbortDelay( TaskHandle_t xTask );

- *
- * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
- * function to be available.
- *
- * A task will enter the Blocked state when it is waiting for an event.  The
- * event it is waiting for can be a temporal event (waiting for a time), such
- * as when vTaskDelay() is called, or an event on an object, such as when
- * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
- * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
- * task will leave the Blocked state, and return from whichever function call
- * placed the task into the Blocked state.
- *
- * @param xTask The handle of the task to remove from the Blocked state.
- *
- * @return If the task referenced by xTask was not in the Blocked state then
- * pdFAIL is returned.  Otherwise pdPASS is returned.
- *
- * \defgroup xTaskAbortDelay xTaskAbortDelay
- * \ingroup TaskCtrl
- */
-BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask );

- *
- * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Obtain the priority of any task.
- *
- * @param xTask Handle of the task to be queried.  Passing a NULL
- * handle results in the priority of the calling task being returned.
- *
- * @return The priority of xTask.
- *
- * Example usage:
-   
- void vAFunction( void )
- {
- TaskHandle_t xHandle;
-
-	 // Create a task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // ...
-
-	 // Use the handle to obtain the priority of the created task.
-	 // It was created with tskIDLE_PRIORITY, but may have changed
-	 // it itself.
-	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
-	 {
-		 // The task has changed it's priority.
-	 }
-
-	 // ...
-
-	 // Is our priority higher than the created task?
-	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
-	 {
-		 // Our priority (obtained using NULL handle) is higher.
-	 }
- }
-   

- * \defgroup uxTaskPriorityGet uxTaskPriorityGet
- * \ingroup TaskCtrl
- */
-UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask );

- *
- * A version of uxTaskPriorityGet() that can be used from an ISR.
- */
-UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
eTaskState eTaskGetState( TaskHandle_t xTask );

- *
- * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Obtain the state of any task.  States are encoded by the eTaskState
- * enumerated type.
- *
- * @param xTask Handle of the task to be queried.
- *
- * @return The state of xTask at the time the function was called.  Note the
- * state of the task might change between the function being called, and the
- * functions return value being tested by the calling task.
- */
-eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );

- *
- * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
- * available.  See the configuration section for more information.
- *
- * Populates a TaskStatus_t structure with information about a task.
- *
- * @param xTask Handle of the task being queried.  If xTask is NULL then
- * information will be returned about the calling task.
- *
- * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
- * filled with information about the task referenced by the handle passed using
- * the xTask parameter.
- *
- * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
- * the stack high water mark of the task being queried.  Calculating the stack
- * high water mark takes a relatively long time, and can make the system
- * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
- * allow the high water mark checking to be skipped.  The high watermark value
- * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
- * not set to pdFALSE;
- *
- * @param eState The TaskStatus_t structure contains a member to report the
- * state of the task being queried.  Obtaining the task state is not as fast as
- * a simple assignment - so the eState parameter is provided to allow the state
- * information to be omitted from the TaskStatus_t structure.  To obtain state
- * information then set eState to eInvalid - otherwise the value passed in
- * eState will be reported as the task state in the TaskStatus_t structure.
- *
- * Example usage:
-   
- void vAFunction( void )
- {
- TaskHandle_t xHandle;
- TaskStatus_t xTaskDetails;
-
-    // Obtain the handle of a task from its name.
-    xHandle = xTaskGetHandle( "Task_Name" );
-
-    // Check the handle is not NULL.
-    configASSERT( xHandle );
-
-    // Use the handle to obtain further information about the task.
-    vTaskGetInfo( xHandle,
-                  &xTaskDetails,
-                  pdTRUE, // Include the high water mark in xTaskDetails.
-                  eInvalid ); // Include the task state in xTaskDetails.
- }
-   

- * \defgroup vTaskGetInfo vTaskGetInfo
- * \ingroup TaskCtrl
- */
-void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );

- *
- * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Set the priority of any task.
- *
- * A context switch will occur before the function returns if the priority
- * being set is higher than the currently executing task.
- *
- * @param xTask Handle to the task for which the priority is being set.
- * Passing a NULL handle results in the priority of the calling task being set.
- *
- * @param uxNewPriority The priority to which the task will be set.
- *
- * Example usage:
-   
- void vAFunction( void )
- {
- TaskHandle_t xHandle;
-
-	 // Create a task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // ...
-
-	 // Use the handle to raise the priority of the created task.
-	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
-
-	 // ...
-
-	 // Use a NULL handle to raise our priority to the same value.
-	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
- }
-   

- * \defgroup vTaskPrioritySet vTaskPrioritySet
- * \ingroup TaskCtrl
- */
-void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskSuspend( TaskHandle_t xTaskToSuspend );

- *
- * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Suspend any task.  When suspended a task will never get any microcontroller
- * processing time, no matter what its priority.
- *
- * Calls to vTaskSuspend are not accumulative -
- * i.e. calling vTaskSuspend () twice on the same task still only requires one
- * call to vTaskResume () to ready the suspended task.
- *
- * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
- * handle will cause the calling task to be suspended.
- *
- * Example usage:
-   
- void vAFunction( void )
- {
- TaskHandle_t xHandle;
-
-	 // Create a task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // ...
-
-	 // Use the handle to suspend the created task.
-	 vTaskSuspend( xHandle );
-
-	 // ...
-
-	 // The created task will not run during this period, unless
-	 // another task calls vTaskResume( xHandle ).
-
-	 //...
-
-
-	 // Suspend ourselves.
-	 vTaskSuspend( NULL );
-
-	 // We cannot get here unless another task calls vTaskResume
-	 // with our handle as the parameter.
- }
-   

- * \defgroup vTaskSuspend vTaskSuspend
- * \ingroup TaskCtrl
- */
-void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskResume( TaskHandle_t xTaskToResume );

- *
- * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
- * See the configuration section for more information.
- *
- * Resumes a suspended task.
- *
- * A task that has been suspended by one or more calls to vTaskSuspend ()
- * will be made available for running again by a single call to
- * vTaskResume ().
- *
- * @param xTaskToResume Handle to the task being readied.
- *
- * Example usage:
-   
- void vAFunction( void )
- {
- TaskHandle_t xHandle;
-
-	 // Create a task, storing the handle.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
-
-	 // ...
-
-	 // Use the handle to suspend the created task.
-	 vTaskSuspend( xHandle );
-
-	 // ...
-
-	 // The created task will not run during this period, unless
-	 // another task calls vTaskResume( xHandle ).
-
-	 //...
-
-
-	 // Resume the suspended task ourselves.
-	 vTaskResume( xHandle );
-
-	 // The created task will once again get microcontroller processing
-	 // time in accordance with its priority within the system.
- }
-   

- * \defgroup vTaskResume vTaskResume
- * \ingroup TaskCtrl
- */
-void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void xTaskResumeFromISR( TaskHandle_t xTaskToResume );

- *
- * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
- * available.  See the configuration section for more information.
- *
- * An implementation of vTaskResume() that can be called from within an ISR.
- *
- * A task that has been suspended by one or more calls to vTaskSuspend ()
- * will be made available for running again by a single call to
- * xTaskResumeFromISR ().
- *
- * xTaskResumeFromISR() should not be used to synchronise a task with an
- * interrupt if there is a chance that the interrupt could arrive prior to the
- * task being suspended - as this can lead to interrupts being missed. Use of a
- * semaphore as a synchronisation mechanism would avoid this eventuality.
- *
- * @param xTaskToResume Handle to the task being readied.
- *
- * @return pdTRUE if resuming the task should result in a context switch,
- * otherwise pdFALSE. This is used by the ISR to determine if a context switch
- * may be required following the ISR.
- *
- * \defgroup vTaskResumeFromISR vTaskResumeFromISR
- * \ingroup TaskCtrl
- */
-BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------
- * SCHEDULER CONTROL
- *----------------------------------------------------------*/
-
-/**
- * task. h
- * 
void vTaskStartScheduler( void );

- *
- * Starts the real time kernel tick processing.  After calling the kernel
- * has control over which tasks are executed and when.
- *
- * See the demo application file main.c for an example of creating
- * tasks and starting the kernel.
- *
- * Example usage:
-   
- void vAFunction( void )
- {
-	 // Create at least one task before starting the kernel.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-	 // Start the real time kernel with preemption.
-	 vTaskStartScheduler ();
-
-	 // Will not get here unless a task calls vTaskEndScheduler ()
- }
-   

- *
- * \defgroup vTaskStartScheduler vTaskStartScheduler
- * \ingroup SchedulerControl
- */
-void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskEndScheduler( void );

- *
- * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
- * in place of DOS, implements this function.
- *
- * Stops the real time kernel tick.  All created tasks will be automatically
- * deleted and multitasking (either preemptive or cooperative) will
- * stop.  Execution then resumes from the point where vTaskStartScheduler ()
- * was called, as if vTaskStartScheduler () had just returned.
- *
- * See the demo application file main. c in the demo/PC directory for an
- * example that uses vTaskEndScheduler ().
- *
- * vTaskEndScheduler () requires an exit function to be defined within the
- * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
- * performs hardware specific operations such as stopping the kernel tick.
- *
- * vTaskEndScheduler () will cause all of the resources allocated by the
- * kernel to be freed - but will not free resources allocated by application
- * tasks.
- *
- * Example usage:
-   
- void vTaskCode( void * pvParameters )
- {
-	 for( ;; )
-	 {
-		 // Task code goes here.
-
-		 // At some point we want to end the real time kernel processing
-		 // so call ...
-		 vTaskEndScheduler ();
-	 }
- }
-
- void vAFunction( void )
- {
-	 // Create at least one task before starting the kernel.
-	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
-
-	 // Start the real time kernel with preemption.
-	 vTaskStartScheduler ();
-
-	 // Will only get here when the vTaskCode () task has called
-	 // vTaskEndScheduler ().  When we get here we are back to single task
-	 // execution.
- }
-   

- *
- * \defgroup vTaskEndScheduler vTaskEndScheduler
- * \ingroup SchedulerControl
- */
-void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskSuspendAll( void );

- *
- * Suspends the scheduler without disabling interrupts.  Context switches will
- * not occur while the scheduler is suspended.
- *
- * After calling vTaskSuspendAll () the calling task will continue to execute
- * without risk of being swapped out until a call to xTaskResumeAll () has been
- * made.
- *
- * API functions that have the potential to cause a context switch (for example,
- * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
- * is suspended.
- *
- * Example usage:
-   
- void vTask1( void * pvParameters )
- {
-	 for( ;; )
-	 {
-		 // Task code goes here.
-
-		 // ...
-
-		 // At some point the task wants to perform a long operation during
-		 // which it does not want to get swapped out.  It cannot use
-		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-		 // operation may cause interrupts to be missed - including the
-		 // ticks.
-
-		 // Prevent the real time kernel swapping out the task.
-		 vTaskSuspendAll ();
-
-		 // Perform the operation here.  There is no need to use critical
-		 // sections as we have all the microcontroller processing time.
-		 // During this time interrupts will still operate and the kernel
-		 // tick count will be maintained.
-
-		 // ...
-
-		 // The operation is complete.  Restart the kernel.
-		 xTaskResumeAll ();
-	 }
- }
-   

- * \defgroup vTaskSuspendAll vTaskSuspendAll
- * \ingroup SchedulerControl
- */
-void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
BaseType_t xTaskResumeAll( void );

- *
- * Resumes scheduler activity after it was suspended by a call to
- * vTaskSuspendAll().
- *
- * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
- * that were previously suspended by a call to vTaskSuspend().
- *
- * @return If resuming the scheduler caused a context switch then pdTRUE is
- *		  returned, otherwise pdFALSE is returned.
- *
- * Example usage:
-   
- void vTask1( void * pvParameters )
- {
-	 for( ;; )
-	 {
-		 // Task code goes here.
-
-		 // ...
-
-		 // At some point the task wants to perform a long operation during
-		 // which it does not want to get swapped out.  It cannot use
-		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
-		 // operation may cause interrupts to be missed - including the
-		 // ticks.
-
-		 // Prevent the real time kernel swapping out the task.
-		 vTaskSuspendAll ();
-
-		 // Perform the operation here.  There is no need to use critical
-		 // sections as we have all the microcontroller processing time.
-		 // During this time interrupts will still operate and the real
-		 // time kernel tick count will be maintained.
-
-		 // ...
-
-		 // The operation is complete.  Restart the kernel.  We want to force
-		 // a context switch - but there is no point if resuming the scheduler
-		 // caused a context switch already.
-		 if( !xTaskResumeAll () )
-		 {
-			  taskYIELD ();
-		 }
-	 }
- }
-   

- * \defgroup xTaskResumeAll xTaskResumeAll
- * \ingroup SchedulerControl
- */
-BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------
- * TASK UTILITIES
- *----------------------------------------------------------*/
-
-/**
- * task. h
- * 
TickType_t xTaskGetTickCount( void );

- *
- * @return The count of ticks since vTaskStartScheduler was called.
- *
- * \defgroup xTaskGetTickCount xTaskGetTickCount
- * \ingroup TaskUtils
- */
-TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
TickType_t xTaskGetTickCountFromISR( void );

- *
- * @return The count of ticks since vTaskStartScheduler was called.
- *
- * This is a version of xTaskGetTickCount() that is safe to be called from an
- * ISR - provided that TickType_t is the natural word size of the
- * microcontroller being used or interrupt nesting is either not supported or
- * not being used.
- *
- * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
- * \ingroup TaskUtils
- */
-TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
uint16_t uxTaskGetNumberOfTasks( void );

- *
- * @return The number of tasks that the real time kernel is currently managing.
- * This includes all ready, blocked and suspended tasks.  A task that
- * has been deleted but not yet freed by the idle task will also be
- * included in the count.
- *
- * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
- * \ingroup TaskUtils
- */
-UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
char *pcTaskGetName( TaskHandle_t xTaskToQuery );

- *
- * @return The text (human readable) name of the task referenced by the handle
- * xTaskToQuery.  A task can query its own name by either passing in its own
- * handle, or by setting xTaskToQuery to NULL.
- *
- * \defgroup pcTaskGetName pcTaskGetName
- * \ingroup TaskUtils
- */
-char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * task. h
- * 
TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );

- *
- * NOTE:  This function takes a relatively long time to complete and should be
- * used sparingly.
- *
- * @return The handle of the task that has the human readable name pcNameToQuery.
- * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
- * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
- *
- * \defgroup pcTaskGetHandle pcTaskGetHandle
- * \ingroup TaskUtils
- */
-TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * task.h
- * 
UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );

- *
- * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
- * this function to be available.
- *
- * Returns the high water mark of the stack associated with xTask.  That is,
- * the minimum free stack space there has been (in words, so on a 32 bit machine
- * a value of 1 means 4 bytes) since the task started.  The smaller the returned
- * number the closer the task has come to overflowing its stack.
- *
- * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
- * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
- * user to determine the return type.  It gets around the problem of the value
- * overflowing on 8-bit types without breaking backward compatibility for
- * applications that expect an 8-bit return type.
- *
- * @param xTask Handle of the task associated with the stack to be checked.
- * Set xTask to NULL to check the stack of the calling task.
- *
- * @return The smallest amount of free stack space there has been (in words, so
- * actual spaces on the stack rather than bytes) since the task referenced by
- * xTask was created.
- */
-UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/**
- * task.h
- * 
configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask );

- *
- * INCLUDE_uxTaskGetStackHighWaterMark2 must be set to 1 in FreeRTOSConfig.h for
- * this function to be available.
- *
- * Returns the high water mark of the stack associated with xTask.  That is,
- * the minimum free stack space there has been (in words, so on a 32 bit machine
- * a value of 1 means 4 bytes) since the task started.  The smaller the returned
- * number the closer the task has come to overflowing its stack.
- *
- * uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
- * same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
- * user to determine the return type.  It gets around the problem of the value
- * overflowing on 8-bit types without breaking backward compatibility for
- * applications that expect an 8-bit return type.
- *
- * @param xTask Handle of the task associated with the stack to be checked.
- * Set xTask to NULL to check the stack of the calling task.
- *
- * @return The smallest amount of free stack space there has been (in words, so
- * actual spaces on the stack rather than bytes) since the task referenced by
- * xTask was created.
- */
-configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/* When using trace macros it is sometimes necessary to include task.h before
-FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
-so the following two prototypes will cause a compilation error.  This can be
-fixed by simply guarding against the inclusion of these two prototypes unless
-they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
-constant. */
-#ifdef configUSE_APPLICATION_TASK_TAG
-	#if configUSE_APPLICATION_TASK_TAG == 1
-		/**
-		 * task.h
-		 * 
void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );

-		 *
-		 * Sets pxHookFunction to be the task hook function used by the task xTask.
-		 * Passing xTask as NULL has the effect of setting the calling tasks hook
-		 * function.
-		 */
-		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
-
-		/**
-		 * task.h
-		 * 
void xTaskGetApplicationTaskTag( TaskHandle_t xTask );

-		 *
-		 * Returns the pxHookFunction value assigned to the task xTask.  Do not
-		 * call from an interrupt service routine - call
-		 * xTaskGetApplicationTaskTagFromISR() instead.
-		 */
-		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-		/**
-		 * task.h
-		 * 
void xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask );

-		 *
-		 * Returns the pxHookFunction value assigned to the task xTask.  Can
-		 * be called from an interrupt service routine.
-		 */
-		TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
-#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
-
-#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
-
-	/* Each task contains an array of pointers that is dimensioned by the
-	configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
-	kernel does not use the pointers itself, so the application writer can use
-	the pointers for any purpose they wish.  The following two functions are
-	used to set and query a pointer respectively. */
-	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
-	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/**
- * task.h
- * 
BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );

- *
- * Calls the hook function associated with xTask.  Passing xTask as NULL has
- * the effect of calling the Running tasks (the calling task) hook function.
- *
- * pvParameter is passed to the hook function for the task to interpret as it
- * wants.  The return value is the value returned by the task hook function
- * registered by the user.
- */
-BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
-
-/**
- * xTaskGetIdleTaskHandle() is only available if
- * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
- *
- * Simply returns the handle of the idle task.  It is not valid to call
- * xTaskGetIdleTaskHandle() before the scheduler has been started.
- */
-TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
-
-/**
- * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
- * uxTaskGetSystemState() to be available.
- *
- * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
- * the system.  TaskStatus_t structures contain, among other things, members
- * for the task handle, task name, task priority, task state, and total amount
- * of run time consumed by the task.  See the TaskStatus_t structure
- * definition in this file for the full member list.
- *
- * NOTE:  This function is intended for debugging use only as its use results in
- * the scheduler remaining suspended for an extended period.
- *
- * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
- * The array must contain at least one TaskStatus_t structure for each task
- * that is under the control of the RTOS.  The number of tasks under the control
- * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
- *
- * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
- * parameter.  The size is specified as the number of indexes in the array, or
- * the number of TaskStatus_t structures contained in the array, not by the
- * number of bytes in the array.
- *
- * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
- * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
- * total run time (as defined by the run time stats clock, see
- * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
- * pulTotalRunTime can be set to NULL to omit the total run time information.
- *
- * @return The number of TaskStatus_t structures that were populated by
- * uxTaskGetSystemState().  This should equal the number returned by the
- * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
- * in the uxArraySize parameter was too small.
- *
- * Example usage:
-   
-    // This example demonstrates how a human readable table of run time stats
-	// information is generated from raw data provided by uxTaskGetSystemState().
-	// The human readable table is written to pcWriteBuffer
-	void vTaskGetRunTimeStats( char *pcWriteBuffer )
-	{
-	TaskStatus_t *pxTaskStatusArray;
-	volatile UBaseType_t uxArraySize, x;
-	uint32_t ulTotalRunTime, ulStatsAsPercentage;
-
-		// Make sure the write buffer does not contain a string.
-		*pcWriteBuffer = 0x00;
-
-		// Take a snapshot of the number of tasks in case it changes while this
-		// function is executing.
-		uxArraySize = uxTaskGetNumberOfTasks();
-
-		// Allocate a TaskStatus_t structure for each task.  An array could be
-		// allocated statically at compile time.
-		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
-
-		if( pxTaskStatusArray != NULL )
-		{
-			// Generate raw status information about each task.
-			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
-
-			// For percentage calculations.
-			ulTotalRunTime /= 100UL;
-
-			// Avoid divide by zero errors.
-			if( ulTotalRunTime > 0 )
-			{
-				// For each populated position in the pxTaskStatusArray array,
-				// format the raw data as human readable ASCII data
-				for( x = 0; x < uxArraySize; x++ )
-				{
-					// What percentage of the total run time has the task used?
-					// This will always be rounded down to the nearest integer.
-					// ulTotalRunTimeDiv100 has already been divided by 100.
-					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
-
-					if( ulStatsAsPercentage > 0UL )
-					{
-						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
-					}
-					else
-					{
-						// If the percentage is zero here then the task has
-						// consumed less than 1% of the total run time.
-						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
-					}
-
-					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
-				}
-			}
-
-			// The array is no longer needed, free the memory it consumes.
-			vPortFree( pxTaskStatusArray );
-		}
-	}
-	

- */
-UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
void vTaskList( char *pcWriteBuffer );

- *
- * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
- * both be defined as 1 for this function to be available.  See the
- * configuration section of the FreeRTOS.org website for more information.
- *
- * NOTE 1: This function will disable interrupts for its duration.  It is
- * not intended for normal application runtime use but as a debug aid.
- *
- * Lists all the current tasks, along with their current state and stack
- * usage high water mark.
- *
- * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
- * suspended ('S').
- *
- * PLEASE NOTE:
- *
- * This function is provided for convenience only, and is used by many of the
- * demo applications.  Do not consider it to be part of the scheduler.
- *
- * vTaskList() calls uxTaskGetSystemState(), then formats part of the
- * uxTaskGetSystemState() output into a human readable table that displays task
- * names, states and stack usage.
- *
- * vTaskList() has a dependency on the sprintf() C library function that might
- * bloat the code size, use a lot of stack, and provide different results on
- * different platforms.  An alternative, tiny, third party, and limited
- * functionality implementation of sprintf() is provided in many of the
- * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
- * printf-stdarg.c does not provide a full snprintf() implementation!).
- *
- * It is recommended that production systems call uxTaskGetSystemState()
- * directly to get access to raw stats data, rather than indirectly through a
- * call to vTaskList().
- *
- * @param pcWriteBuffer A buffer into which the above mentioned details
- * will be written, in ASCII form.  This buffer is assumed to be large
- * enough to contain the generated report.  Approximately 40 bytes per
- * task should be sufficient.
- *
- * \defgroup vTaskList vTaskList
- * \ingroup TaskUtils
- */
-void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * task. h
- * 
void vTaskGetRunTimeStats( char *pcWriteBuffer );

- *
- * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
- * must both be defined as 1 for this function to be available.  The application
- * must also then provide definitions for
- * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
- * to configure a peripheral timer/counter and return the timers current count
- * value respectively.  The counter should be at least 10 times the frequency of
- * the tick count.
- *
- * NOTE 1: This function will disable interrupts for its duration.  It is
- * not intended for normal application runtime use but as a debug aid.
- *
- * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
- * accumulated execution time being stored for each task.  The resolution
- * of the accumulated time value depends on the frequency of the timer
- * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
- * Calling vTaskGetRunTimeStats() writes the total execution time of each
- * task into a buffer, both as an absolute count value and as a percentage
- * of the total system execution time.
- *
- * NOTE 2:
- *
- * This function is provided for convenience only, and is used by many of the
- * demo applications.  Do not consider it to be part of the scheduler.
- *
- * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
- * uxTaskGetSystemState() output into a human readable table that displays the
- * amount of time each task has spent in the Running state in both absolute and
- * percentage terms.
- *
- * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
- * that might bloat the code size, use a lot of stack, and provide different
- * results on different platforms.  An alternative, tiny, third party, and
- * limited functionality implementation of sprintf() is provided in many of the
- * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
- * printf-stdarg.c does not provide a full snprintf() implementation!).
- *
- * It is recommended that production systems call uxTaskGetSystemState() directly
- * to get access to raw stats data, rather than indirectly through a call to
- * vTaskGetRunTimeStats().
- *
- * @param pcWriteBuffer A buffer into which the execution times will be
- * written, in ASCII form.  This buffer is assumed to be large enough to
- * contain the generated report.  Approximately 40 bytes per task should
- * be sufficient.
- *
- * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
- * \ingroup TaskUtils
- */
-void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
-* task. h
-* 
TickType_t xTaskGetIdleRunTimeCounter( void );

-*
-* configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
-* must both be defined as 1 for this function to be available.  The application
-* must also then provide definitions for
-* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
-* to configure a peripheral timer/counter and return the timers current count
-* value respectively.  The counter should be at least 10 times the frequency of
-* the tick count.
-*
-* Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
-* accumulated execution time being stored for each task.  The resolution
-* of the accumulated time value depends on the frequency of the timer
-* configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
-* While uxTaskGetSystemState() and vTaskGetRunTimeStats() writes the total
-* execution time of each task into a buffer, xTaskGetIdleRunTimeCounter()
-* returns the total execution time of just the idle task.
-*
-* @return The total run time of the idle task.  This is the amount of time the
-* idle task has actually been executing.  The unit of time is dependent on the
-* frequency configured using the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and
-* portGET_RUN_TIME_COUNTER_VALUE() macros.
-*
-* \defgroup xTaskGetIdleRunTimeCounter xTaskGetIdleRunTimeCounter
-* \ingroup TaskUtils
-*/
-TickType_t xTaskGetIdleRunTimeCounter( void ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );

- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * A notification sent to a task will remain pending until it is cleared by the
- * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
- * already in the Blocked state to wait for a notification when the notification
- * arrives then the task will automatically be removed from the Blocked state
- * (unblocked) and the notification cleared.
- *
- * A task can use xTaskNotifyWait() to [optionally] block to wait for a
- * notification to be pending, or ulTaskNotifyTake() to [optionally] block
- * to wait for its notification value to have a non-zero value.  The task does
- * not consume any CPU time while it is in the Blocked state.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @param ulValue Data that can be sent with the notification.  How the data is
- * used depends on the value of the eAction parameter.
- *
- * @param eAction Specifies how the notification updates the task's notification
- * value, if at all.  Valid values for eAction are as follows:
- *
- * eSetBits -
- * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
- * always returns pdPASS in this case.
- *
- * eIncrement -
- * The task's notification value is incremented.  ulValue is not used and
- * xTaskNotify() always returns pdPASS in this case.
- *
- * eSetValueWithOverwrite -
- * The task's notification value is set to the value of ulValue, even if the
- * task being notified had not yet processed the previous notification (the
- * task already had a notification pending).  xTaskNotify() always returns
- * pdPASS in this case.
- *
- * eSetValueWithoutOverwrite -
- * If the task being notified did not already have a notification pending then
- * the task's notification value is set to ulValue and xTaskNotify() will
- * return pdPASS.  If the task being notified already had a notification
- * pending then no action is performed and pdFAIL is returned.
- *
- * eNoAction -
- * The task receives a notification without its notification value being
- * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
- * this case.
- *
- *  pulPreviousNotificationValue -
- *  Can be used to pass out the subject task's notification value before any
- *  bits are modified by the notify function.
- *
- * @return Dependent on the value of eAction.  See the description of the
- * eAction parameter.
- *
- * \defgroup xTaskNotify xTaskNotify
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
-#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
-#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
-
-/**
- * task. h
- * 
BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );

- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * A version of xTaskNotify() that can be used from an interrupt service routine
- * (ISR).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * A notification sent to a task will remain pending until it is cleared by the
- * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
- * already in the Blocked state to wait for a notification when the notification
- * arrives then the task will automatically be removed from the Blocked state
- * (unblocked) and the notification cleared.
- *
- * A task can use xTaskNotifyWait() to [optionally] block to wait for a
- * notification to be pending, or ulTaskNotifyTake() to [optionally] block
- * to wait for its notification value to have a non-zero value.  The task does
- * not consume any CPU time while it is in the Blocked state.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @param ulValue Data that can be sent with the notification.  How the data is
- * used depends on the value of the eAction parameter.
- *
- * @param eAction Specifies how the notification updates the task's notification
- * value, if at all.  Valid values for eAction are as follows:
- *
- * eSetBits -
- * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
- * always returns pdPASS in this case.
- *
- * eIncrement -
- * The task's notification value is incremented.  ulValue is not used and
- * xTaskNotify() always returns pdPASS in this case.
- *
- * eSetValueWithOverwrite -
- * The task's notification value is set to the value of ulValue, even if the
- * task being notified had not yet processed the previous notification (the
- * task already had a notification pending).  xTaskNotify() always returns
- * pdPASS in this case.
- *
- * eSetValueWithoutOverwrite -
- * If the task being notified did not already have a notification pending then
- * the task's notification value is set to ulValue and xTaskNotify() will
- * return pdPASS.  If the task being notified already had a notification
- * pending then no action is performed and pdFAIL is returned.
- *
- * eNoAction -
- * The task receives a notification without its notification value being
- * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
- * this case.
- *
- * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
- * task to which the notification was sent to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently running task.  If
- * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
- * be requested before the interrupt is exited.  How a context switch is
- * requested from an ISR is dependent on the port - see the documentation page
- * for the port in use.
- *
- * @return Dependent on the value of eAction.  See the description of the
- * eAction parameter.
- *
- * \defgroup xTaskNotify xTaskNotify
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
-#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
-
-/**
- * task. h
- * 
BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );

- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * A notification sent to a task will remain pending until it is cleared by the
- * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
- * already in the Blocked state to wait for a notification when the notification
- * arrives then the task will automatically be removed from the Blocked state
- * (unblocked) and the notification cleared.
- *
- * A task can use xTaskNotifyWait() to [optionally] block to wait for a
- * notification to be pending, or ulTaskNotifyTake() to [optionally] block
- * to wait for its notification value to have a non-zero value.  The task does
- * not consume any CPU time while it is in the Blocked state.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
- * will be cleared in the calling task's notification value before the task
- * checks to see if any notifications are pending, and optionally blocks if no
- * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
- * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
- * the effect of resetting the task's notification value to 0.  Setting
- * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
- *
- * @param ulBitsToClearOnExit If a notification is pending or received before
- * the calling task exits the xTaskNotifyWait() function then the task's
- * notification value (see the xTaskNotify() API function) is passed out using
- * the pulNotificationValue parameter.  Then any bits that are set in
- * ulBitsToClearOnExit will be cleared in the task's notification value (note
- * *pulNotificationValue is set before any bits are cleared).  Setting
- * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
- * (if limits.h is not included) will have the effect of resetting the task's
- * notification value to 0 before the function exits.  Setting
- * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
- * when the function exits (in which case the value passed out in
- * pulNotificationValue will match the task's notification value).
- *
- * @param pulNotificationValue Used to pass the task's notification value out
- * of the function.  Note the value passed out will not be effected by the
- * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
- *
- * @param xTicksToWait The maximum amount of time that the task should wait in
- * the Blocked state for a notification to be received, should a notification
- * not already be pending when xTaskNotifyWait() was called.  The task
- * will not consume any processing time while it is in the Blocked state.  This
- * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
- * used to convert a time specified in milliseconds to a time specified in
- * ticks.
- *
- * @return If a notification was received (including notifications that were
- * already pending when xTaskNotifyWait was called) then pdPASS is
- * returned.  Otherwise pdFAIL is returned.
- *
- * \defgroup xTaskNotifyWait xTaskNotifyWait
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );

- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
- * to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * xTaskNotifyGive() is a helper macro intended for use when task notifications
- * are used as light weight and faster binary or counting semaphore equivalents.
- * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
- * the equivalent action that instead uses a task notification is
- * xTaskNotifyGive().
- *
- * When task notifications are being used as a binary or counting semaphore
- * equivalent then the task being notified should wait for the notification
- * using the ulTaskNotificationTake() API function rather than the
- * xTaskNotifyWait() API function.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
- * eAction parameter set to eIncrement - so pdPASS is always returned.
- *
- * \defgroup xTaskNotifyGive xTaskNotifyGive
- * \ingroup TaskNotifications
- */
-#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
-
-/**
- * task. h
- * 
void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
- * to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * A version of xTaskNotifyGive() that can be called from an interrupt service
- * routine (ISR).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * vTaskNotifyGiveFromISR() is intended for use when task notifications are
- * used as light weight and faster binary or counting semaphore equivalents.
- * Actual FreeRTOS semaphores are given from an ISR using the
- * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
- * a task notification is vTaskNotifyGiveFromISR().
- *
- * When task notifications are being used as a binary or counting semaphore
- * equivalent then the task being notified should wait for the notification
- * using the ulTaskNotificationTake() API function rather than the
- * xTaskNotifyWait() API function.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
- *
- * @param xTaskToNotify The handle of the task being notified.  The handle to a
- * task can be returned from the xTaskCreate() API function used to create the
- * task, and the handle of the currently running task can be obtained by calling
- * xTaskGetCurrentTaskHandle().
- *
- * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
- * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
- * task to which the notification was sent to leave the Blocked state, and the
- * unblocked task has a priority higher than the currently running task.  If
- * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
- * should be requested before the interrupt is exited.  How a context switch is
- * requested from an ISR is dependent on the port - see the documentation page
- * for the port in use.
- *
- * \defgroup xTaskNotifyWait xTaskNotifyWait
- * \ingroup TaskNotifications
- */
-void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );

- *
- * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
- * function to be available.
- *
- * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
- * "notification value", which is a 32-bit unsigned integer (uint32_t).
- *
- * Events can be sent to a task using an intermediary object.  Examples of such
- * objects are queues, semaphores, mutexes and event groups.  Task notifications
- * are a method of sending an event directly to a task without the need for such
- * an intermediary object.
- *
- * A notification sent to a task can optionally perform an action, such as
- * update, overwrite or increment the task's notification value.  In that way
- * task notifications can be used to send data to a task, or be used as light
- * weight and fast binary or counting semaphores.
- *
- * ulTaskNotifyTake() is intended for use when a task notification is used as a
- * faster and lighter weight binary or counting semaphore alternative.  Actual
- * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
- * equivalent action that instead uses a task notification is
- * ulTaskNotifyTake().
- *
- * When a task is using its notification value as a binary or counting semaphore
- * other tasks should send notifications to it using the xTaskNotifyGive()
- * macro, or xTaskNotify() function with the eAction parameter set to
- * eIncrement.
- *
- * ulTaskNotifyTake() can either clear the task's notification value to
- * zero on exit, in which case the notification value acts like a binary
- * semaphore, or decrement the task's notification value on exit, in which case
- * the notification value acts like a counting semaphore.
- *
- * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
- * the task's notification value to be non-zero.  The task does not consume any
- * CPU time while it is in the Blocked state.
- *
- * Where as xTaskNotifyWait() will return when a notification is pending,
- * ulTaskNotifyTake() will return when the task's notification value is
- * not zero.
- *
- * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
- *
- * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
- * notification value is decremented when the function exits.  In this way the
- * notification value acts like a counting semaphore.  If xClearCountOnExit is
- * not pdFALSE then the task's notification value is cleared to zero when the
- * function exits.  In this way the notification value acts like a binary
- * semaphore.
- *
- * @param xTicksToWait The maximum amount of time that the task should wait in
- * the Blocked state for the task's notification value to be greater than zero,
- * should the count not already be greater than zero when
- * ulTaskNotifyTake() was called.  The task will not consume any processing
- * time while it is in the Blocked state.  This is specified in kernel ticks,
- * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
- * specified in milliseconds to a time specified in ticks.
- *
- * @return The task's notification count before it is either cleared to zero or
- * decremented (see the xClearCountOnExit parameter).
- *
- * \defgroup ulTaskNotifyTake ulTaskNotifyTake
- * \ingroup TaskNotifications
- */
-uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * task. h
- * 
BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );

- *
- * If the notification state of the task referenced by the handle xTask is
- * eNotified, then set the task's notification state to eNotWaitingNotification.
- * The task's notification value is not altered.  Set xTask to NULL to clear the
- * notification state of the calling task.
- *
- * @return pdTRUE if the task's notification state was set to
- * eNotWaitingNotification, otherwise pdFALSE.
- * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
- * \ingroup TaskNotifications
- */
-BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
-
-/*-----------------------------------------------------------
- * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
- *----------------------------------------------------------*/
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
- * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
- * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * Called from the real time kernel tick (either preemptive or cooperative),
- * this increments the tick count and checks if any tasks that are blocked
- * for a finite period required removing from a blocked list and placing on
- * a ready list.  If a non-zero value is returned then a context switch is
- * required because either:
- *   + A task was removed from a blocked list because its timeout had expired,
- *     or
- *   + Time slicing is in use and there is a task of equal priority to the
- *     currently running task.
- */
-BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * Removes the calling task from the ready list and places it both
- * on the list of tasks waiting for a particular event, and the
- * list of delayed tasks.  The task will be removed from both lists
- * and replaced on the ready list should either the event occur (and
- * there be no higher priority tasks waiting on the same event) or
- * the delay period expires.
- *
- * The 'unordered' version replaces the event list item value with the
- * xItemValue value, and inserts the list item at the end of the list.
- *
- * The 'ordered' version uses the existing event list item value (which is the
- * owning tasks priority) to insert the list item into the event list is task
- * priority order.
- *
- * @param pxEventList The list containing tasks that are blocked waiting
- * for the event to occur.
- *
- * @param xItemValue The item value to use for the event list item when the
- * event list is not ordered by task priority.
- *
- * @param xTicksToWait The maximum amount of time that the task should wait
- * for the event to occur.  This is specified in kernel ticks,the constant
- * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
- * period.
- */
-void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * This function performs nearly the same function as vTaskPlaceOnEventList().
- * The difference being that this function does not permit tasks to block
- * indefinitely, whereas vTaskPlaceOnEventList() does.
- *
- */
-void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
- * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
- *
- * Removes a task from both the specified event list and the list of blocked
- * tasks, and places it on a ready queue.
- *
- * xTaskRemoveFromEventList()/vTaskRemoveFromUnorderedEventList() will be called
- * if either an event occurs to unblock a task, or the block timeout period
- * expires.
- *
- * xTaskRemoveFromEventList() is used when the event list is in task priority
- * order.  It removes the list item from the head of the event list as that will
- * have the highest priority owning task of all the tasks on the event list.
- * vTaskRemoveFromUnorderedEventList() is used when the event list is not
- * ordered and the event list items hold something other than the owning tasks
- * priority.  In this case the event list item value is updated to the value
- * passed in the xItemValue parameter.
- *
- * @return pdTRUE if the task being removed has a higher priority than the task
- * making the call, otherwise pdFALSE.
- */
-BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
-void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
-
-/*
- * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
- * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
- * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
- *
- * Sets the pointer to the current TCB to the TCB of the highest priority task
- * that is ready to run.
- */
-portDONT_DISCARD void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
-
-/*
- * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
- * THE EVENT BITS MODULE.
- */
-TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Return the handle of the calling task.
- */
-TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Capture the current time status for future reference.
- */
-void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
-
-/*
- * Compare the time status now with that previously captured to see if the
- * timeout has expired.
- */
-BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
-
-/*
- * Shortcut used by the queue implementation to prevent unnecessary call to
- * taskYIELD();
- */
-void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Returns the scheduler state as taskSCHEDULER_RUNNING,
- * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
- */
-BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Raises the priority of the mutex holder to that of the calling task should
- * the mutex holder have a priority less than the calling task.
- */
-BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
-
-/*
- * Set the priority of a task back to its proper priority in the case that it
- * inherited a higher priority while it was holding a semaphore.
- */
-BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
-
-/*
- * If a higher priority task attempting to obtain a mutex caused a lower
- * priority task to inherit the higher priority task's priority - but the higher
- * priority task then timed out without obtaining the mutex, then the lower
- * priority task will disinherit the priority again - but only down as far as
- * the highest priority task that is still waiting for the mutex (if there were
- * more than one task waiting for the mutex).
- */
-void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask ) PRIVILEGED_FUNCTION;
-
-/*
- * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
- */
-UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-/*
- * Set the uxTaskNumber of the task referenced by the xTask parameter to
- * uxHandle.
- */
-void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
-
-/*
- * Only available when configUSE_TICKLESS_IDLE is set to 1.
- * If tickless mode is being used, or a low power mode is implemented, then
- * the tick interrupt will not execute during idle periods.  When this is the
- * case, the tick count value maintained by the scheduler needs to be kept up
- * to date with the actual execution time by being skipped forward by a time
- * equal to the idle period.
- */
-void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
-
-/*
- * Only available when configUSE_TICKLESS_IDLE is set to 1.
- * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
- * specific sleep function to determine if it is ok to proceed with the sleep,
- * and if it is ok to proceed, if it is ok to sleep indefinitely.
- *
- * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
- * called with the scheduler suspended, not from within a critical section.  It
- * is therefore possible for an interrupt to request a context switch between
- * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
- * entered.  eTaskConfirmSleepModeStatus() should be called from a short
- * critical section between the timer being stopped and the sleep mode being
- * entered to ensure it is ok to proceed into the sleep mode.
- */
-eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
-
-/*
- * For internal use only.  Increment the mutex held count when a mutex is
- * taken and return the handle of the task that has taken the mutex.
- */
-TaskHandle_t pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
-
-/*
- * For internal use only.  Same as vTaskSetTimeOutState(), but without a critial
- * section.
- */
-void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
-
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* INC_TASK_H */
-
-
-
diff --git a/FreeRTOS/Source/include/timers.h b/FreeRTOS/Source/include/timers.h
deleted file mode 100755
index cb72179..0000000
--- a/FreeRTOS/Source/include/timers.h
+++ /dev/null
@@ -1,1295 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef TIMERS_H
-#define TIMERS_H
-
-#ifndef INC_FREERTOS_H
-	#error "include FreeRTOS.h must appear in source files before include timers.h"
-#endif
-
-/*lint -save -e537 This headers are only multiply included if the application code
-happens to also be including task.h. */
-#include "task.h"
-/*lint -restore */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * MACROS AND DEFINITIONS
- *----------------------------------------------------------*/
-
-/* IDs for commands that can be sent/received on the timer queue.  These are to
-be used solely through the macros that make up the public software timer API,
-as defined below.  The commands that are sent from interrupts must use the
-highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
-or interrupt version of the queue send function should be used. */
-#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
-#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
-#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
-#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
-#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
-#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
-#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
-#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
-
-#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
-#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
-#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
-#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
-#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
-
-
-/**
- * Type by which software timers are referenced.  For example, a call to
- * xTimerCreate() returns an TimerHandle_t variable that can then be used to
- * reference the subject timer in calls to other software timer API functions
- * (for example, xTimerStart(), xTimerReset(), etc.).
- */
-struct tmrTimerControl; /* The old naming convention is used to prevent breaking kernel aware debuggers. */
-typedef struct tmrTimerControl * TimerHandle_t;
-
-/*
- * Defines the prototype to which timer callback functions must conform.
- */
-typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
-
-/*
- * Defines the prototype to which functions used with the
- * xTimerPendFunctionCallFromISR() function must conform.
- */
-typedef void (*PendedFunction_t)( void *, uint32_t );
-
-/**
- * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
- * 								TickType_t xTimerPeriodInTicks,
- * 								UBaseType_t uxAutoReload,
- * 								void * pvTimerID,
- * 								TimerCallbackFunction_t pxCallbackFunction );
- *
- * Creates a new software timer instance, and returns a handle by which the
- * created software timer can be referenced.
- *
- * Internally, within the FreeRTOS implementation, software timers use a block
- * of memory, in which the timer data structure is stored.  If a software timer
- * is created using xTimerCreate() then the required memory is automatically
- * dynamically allocated inside the xTimerCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a software timer is created using
- * xTimerCreateStatic() then the application writer must provide the memory that
- * will get used by the software timer.  xTimerCreateStatic() therefore allows a
- * software timer to be created without using any dynamic memory allocation.
- *
- * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
- * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
- * xTimerChangePeriodFromISR() API functions can all be used to transition a
- * timer into the active state.
- *
- * @param pcTimerName A text name that is assigned to the timer.  This is done
- * purely to assist debugging.  The kernel itself only ever references a timer
- * by its handle, and never by its name.
- *
- * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
- * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
- * has been specified in milliseconds.  For example, if the timer must expire
- * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
- * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
- * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
- * equal to 1000.
- *
- * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
- * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
- * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
- * enter the dormant state after it expires.
- *
- * @param pvTimerID An identifier that is assigned to the timer being created.
- * Typically this would be used in the timer callback function to identify which
- * timer expired when the same callback function is assigned to more than one
- * timer.
- *
- * @param pxCallbackFunction The function to call when the timer expires.
- * Callback functions must have the prototype defined by TimerCallbackFunction_t,
- * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
- *
- * @return If the timer is successfully created then a handle to the newly
- * created timer is returned.  If the timer cannot be created (because either
- * there is insufficient FreeRTOS heap remaining to allocate the timer
- * structures, or the timer period was set to 0) then NULL is returned.
- *
- * Example usage:
- * @verbatim
- * #define NUM_TIMERS 5
- *
- * // An array to hold handles to the created timers.
- * TimerHandle_t xTimers[ NUM_TIMERS ];
- *
- * // An array to hold a count of the number of times each timer expires.
- * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
- *
- * // Define a callback function that will be used by multiple timer instances.
- * // The callback function does nothing but count the number of times the
- * // associated timer expires, and stop the timer once the timer has expired
- * // 10 times.
- * void vTimerCallback( TimerHandle_t pxTimer )
- * {
- * int32_t lArrayIndex;
- * const int32_t xMaxExpiryCountBeforeStopping = 10;
- *
- * 	   // Optionally do something if the pxTimer parameter is NULL.
- * 	   configASSERT( pxTimer );
- *
- *     // Which timer expired?
- *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
- *
- *     // Increment the number of times that pxTimer has expired.
- *     lExpireCounters[ lArrayIndex ] += 1;
- *
- *     // If the timer has expired 10 times then stop it from running.
- *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
- *     {
- *         // Do not use a block time if calling a timer API function from a
- *         // timer callback function, as doing so could cause a deadlock!
- *         xTimerStop( pxTimer, 0 );
- *     }
- * }
- *
- * void main( void )
- * {
- * int32_t x;
- *
- *     // Create then start some timers.  Starting the timers before the scheduler
- *     // has been started means the timers will start running immediately that
- *     // the scheduler starts.
- *     for( x = 0; x < NUM_TIMERS; x++ )
- *     {
- *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
- *                                         ( 100 * x ),   // The timer period in ticks.
- *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
- *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
- *                                         vTimerCallback // Each timer calls the same callback when it expires.
- *                                     );
- *
- *         if( xTimers[ x ] == NULL )
- *         {
- *             // The timer was not created.
- *         }
- *         else
- *         {
- *             // Start the timer.  No block time is specified, and even if one was
- *             // it would be ignored because the scheduler has not yet been
- *             // started.
- *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
- *             {
- *                 // The timer could not be set into the Active state.
- *             }
- *         }
- *     }
- *
- *     // ...
- *     // Create tasks here.
- *     // ...
- *
- *     // Starting the scheduler will start the timers running as they have already
- *     // been set into the active state.
- *     vTaskStartScheduler();
- *
- *     // Should not reach here.
- *     for( ;; );
- * }
- * @endverbatim
- */
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-								const TickType_t xTimerPeriodInTicks,
-								const UBaseType_t uxAutoReload,
-								void * const pvTimerID,
-								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION;
-#endif
-
-/**
- * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
- * 									TickType_t xTimerPeriodInTicks,
- * 									UBaseType_t uxAutoReload,
- * 									void * pvTimerID,
- * 									TimerCallbackFunction_t pxCallbackFunction,
- *									StaticTimer_t *pxTimerBuffer );
- *
- * Creates a new software timer instance, and returns a handle by which the
- * created software timer can be referenced.
- *
- * Internally, within the FreeRTOS implementation, software timers use a block
- * of memory, in which the timer data structure is stored.  If a software timer
- * is created using xTimerCreate() then the required memory is automatically
- * dynamically allocated inside the xTimerCreate() function.  (see
- * http://www.freertos.org/a00111.html).  If a software timer is created using
- * xTimerCreateStatic() then the application writer must provide the memory that
- * will get used by the software timer.  xTimerCreateStatic() therefore allows a
- * software timer to be created without using any dynamic memory allocation.
- *
- * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
- * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
- * xTimerChangePeriodFromISR() API functions can all be used to transition a
- * timer into the active state.
- *
- * @param pcTimerName A text name that is assigned to the timer.  This is done
- * purely to assist debugging.  The kernel itself only ever references a timer
- * by its handle, and never by its name.
- *
- * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
- * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
- * has been specified in milliseconds.  For example, if the timer must expire
- * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
- * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
- * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
- * equal to 1000.
- *
- * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
- * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
- * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
- * enter the dormant state after it expires.
- *
- * @param pvTimerID An identifier that is assigned to the timer being created.
- * Typically this would be used in the timer callback function to identify which
- * timer expired when the same callback function is assigned to more than one
- * timer.
- *
- * @param pxCallbackFunction The function to call when the timer expires.
- * Callback functions must have the prototype defined by TimerCallbackFunction_t,
- * which is "void vCallbackFunction( TimerHandle_t xTimer );".
- *
- * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
- * will be then be used to hold the software timer's data structures, removing
- * the need for the memory to be allocated dynamically.
- *
- * @return If the timer is created then a handle to the created timer is
- * returned.  If pxTimerBuffer was NULL then NULL is returned.
- *
- * Example usage:
- * @verbatim
- *
- * // The buffer used to hold the software timer's data structure.
- * static StaticTimer_t xTimerBuffer;
- *
- * // A variable that will be incremented by the software timer's callback
- * // function.
- * UBaseType_t uxVariableToIncrement = 0;
- *
- * // A software timer callback function that increments a variable passed to
- * // it when the software timer was created.  After the 5th increment the
- * // callback function stops the software timer.
- * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
- * {
- * UBaseType_t *puxVariableToIncrement;
- * BaseType_t xReturned;
- *
- *     // Obtain the address of the variable to increment from the timer ID.
- *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
- *
- *     // Increment the variable to show the timer callback has executed.
- *     ( *puxVariableToIncrement )++;
- *
- *     // If this callback has executed the required number of times, stop the
- *     // timer.
- *     if( *puxVariableToIncrement == 5 )
- *     {
- *         // This is called from a timer callback so must not block.
- *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
- *     }
- * }
- *
- *
- * void main( void )
- * {
- *     // Create the software time.  xTimerCreateStatic() has an extra parameter
- *     // than the normal xTimerCreate() API function.  The parameter is a pointer
- *     // to the StaticTimer_t structure that will hold the software timer
- *     // structure.  If the parameter is passed as NULL then the structure will be
- *     // allocated dynamically, just as if xTimerCreate() had been called.
- *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
- *                                  xTimerPeriod,     // The period of the timer in ticks.
- *                                  pdTRUE,           // This is an auto-reload timer.
- *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
- *                                  prvTimerCallback, // The function to execute when the timer expires.
- *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
- *
- *     // The scheduler has not started yet so a block time is not used.
- *     xReturned = xTimerStart( xTimer, 0 );
- *
- *     // ...
- *     // Create tasks here.
- *     // ...
- *
- *     // Starting the scheduler will start the timers running as they have already
- *     // been set into the active state.
- *     vTaskStartScheduler();
- *
- *     // Should not reach here.
- *     for( ;; );
- * }
- * @endverbatim
- */
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-										const TickType_t xTimerPeriodInTicks,
-										const UBaseType_t uxAutoReload,
-										void * const pvTimerID,
-										TimerCallbackFunction_t pxCallbackFunction,
-										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION;
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/**
- * void *pvTimerGetTimerID( TimerHandle_t xTimer );
- *
- * Returns the ID assigned to the timer.
- *
- * IDs are assigned to timers using the pvTimerID parameter of the call to
- * xTimerCreated() that was used to create the timer, and by calling the
- * vTimerSetTimerID() API function.
- *
- * If the same callback function is assigned to multiple timers then the timer
- * ID can be used as time specific (timer local) storage.
- *
- * @param xTimer The timer being queried.
- *
- * @return The ID assigned to the timer being queried.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- */
-void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
- * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
- *
- * Sets the ID assigned to the timer.
- *
- * IDs are assigned to timers using the pvTimerID parameter of the call to
- * xTimerCreated() that was used to create the timer.
- *
- * If the same callback function is assigned to multiple timers then the timer
- * ID can be used as time specific (timer local) storage.
- *
- * @param xTimer The timer being updated.
- *
- * @param pvNewID The ID to assign to the timer.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- */
-void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
-
-/**
- * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
- *
- * Queries a timer to see if it is active or dormant.
- *
- * A timer will be dormant if:
- *     1) It has been created but not started, or
- *     2) It is an expired one-shot timer that has not been restarted.
- *
- * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
- * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
- * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
- * active state.
- *
- * @param xTimer The timer being queried.
- *
- * @return pdFALSE will be returned if the timer is dormant.  A value other than
- * pdFALSE will be returned if the timer is active.
- *
- * Example usage:
- * @verbatim
- * // This function assumes xTimer has already been created.
- * void vAFunction( TimerHandle_t xTimer )
- * {
- *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
- *     {
- *         // xTimer is active, do something.
- *     }
- *     else
- *     {
- *         // xTimer is not active, do something else.
- *     }
- * }
- * @endverbatim
- */
-BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
- * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
- *
- * Simply returns the handle of the timer service/daemon task.  It it not valid
- * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
- */
-TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
-
-/**
- * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerStart() starts a timer that was previously created using the
- * xTimerCreate() API function.  If the timer had already been started and was
- * already in the active state, then xTimerStart() has equivalent functionality
- * to the xTimerReset() API function.
- *
- * Starting a timer ensures the timer is in the active state.  If the timer
- * is not stopped, deleted, or reset in the mean time, the callback function
- * associated with the timer will get called 'n' ticks after xTimerStart() was
- * called, where 'n' is the timers defined period.
- *
- * It is valid to call xTimerStart() before the scheduler has been started, but
- * when this is done the timer will not actually start until the scheduler is
- * started, and the timers expiry time will be relative to when the scheduler is
- * started, not relative to when xTimerStart() was called.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
- * to be available.
- *
- * @param xTimer The handle of the timer being started/restarted.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the start command to be successfully
- * sent to the timer command queue, should the queue already be full when
- * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
- * before the scheduler is started.
- *
- * @return pdFAIL will be returned if the start command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system, although the
- * timers expiry time is relative to when xTimerStart() is actually called.  The
- * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- *
- */
-#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerStop() stops a timer that was previously started using either of the
- * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
- * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
- *
- * Stopping a timer ensures the timer is not in the active state.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
- * to be available.
- *
- * @param xTimer The handle of the timer being stopped.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the stop command to be successfully
- * sent to the timer command queue, should the queue already be full when
- * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
- * before the scheduler is started.
- *
- * @return pdFAIL will be returned if the stop command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system.  The timer
- * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- *
- * See the xTimerCreate() API function example usage scenario.
- *
- */
-#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
- *										TickType_t xNewPeriod,
- *										TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerChangePeriod() changes the period of a timer that was previously
- * created using the xTimerCreate() API function.
- *
- * xTimerChangePeriod() can be called to change the period of an active or
- * dormant state timer.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for
- * xTimerChangePeriod() to be available.
- *
- * @param xTimer The handle of the timer that is having its period changed.
- *
- * @param xNewPeriod The new period for xTimer. Timer periods are specified in
- * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
- * that has been specified in milliseconds.  For example, if the timer must
- * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
- * if the timer must expire after 500ms, then xNewPeriod can be set to
- * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
- * or equal to 1000.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the change period command to be
- * successfully sent to the timer command queue, should the queue already be
- * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
- * xTimerChangePeriod() is called before the scheduler is started.
- *
- * @return pdFAIL will be returned if the change period command could not be
- * sent to the timer command queue even after xTicksToWait ticks had passed.
- * pdPASS will be returned if the command was successfully sent to the timer
- * command queue.  When the command is actually processed will depend on the
- * priority of the timer service/daemon task relative to other tasks in the
- * system.  The timer service/daemon task priority is set by the
- * configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This function assumes xTimer has already been created.  If the timer
- * // referenced by xTimer is already active when it is called, then the timer
- * // is deleted.  If the timer referenced by xTimer is not active when it is
- * // called, then the period of the timer is set to 500ms and the timer is
- * // started.
- * void vAFunction( TimerHandle_t xTimer )
- * {
- *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
- *     {
- *         // xTimer is already active - delete it.
- *         xTimerDelete( xTimer );
- *     }
- *     else
- *     {
- *         // xTimer is not active, change its period to 500ms.  This will also
- *         // cause the timer to start.  Block for a maximum of 100 ticks if the
- *         // change period command cannot immediately be sent to the timer
- *         // command queue.
- *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
- *         {
- *             // The command was successfully sent.
- *         }
- *         else
- *         {
- *             // The command could not be sent, even after waiting for 100 ticks
- *             // to pass.  Take appropriate action here.
- *         }
- *     }
- * }
- * @endverbatim
- */
- #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerDelete() deletes a timer that was previously created using the
- * xTimerCreate() API function.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for
- * xTimerDelete() to be available.
- *
- * @param xTimer The handle of the timer being deleted.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the delete command to be
- * successfully sent to the timer command queue, should the queue already be
- * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
- * is called before the scheduler is started.
- *
- * @return pdFAIL will be returned if the delete command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system.  The timer
- * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- *
- * See the xTimerChangePeriod() API function example usage scenario.
- */
-#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
- *
- * Timer functionality is provided by a timer service/daemon task.  Many of the
- * public FreeRTOS timer API functions send commands to the timer service task
- * through a queue called the timer command queue.  The timer command queue is
- * private to the kernel itself and is not directly accessible to application
- * code.  The length of the timer command queue is set by the
- * configTIMER_QUEUE_LENGTH configuration constant.
- *
- * xTimerReset() re-starts a timer that was previously created using the
- * xTimerCreate() API function.  If the timer had already been started and was
- * already in the active state, then xTimerReset() will cause the timer to
- * re-evaluate its expiry time so that it is relative to when xTimerReset() was
- * called.  If the timer was in the dormant state then xTimerReset() has
- * equivalent functionality to the xTimerStart() API function.
- *
- * Resetting a timer ensures the timer is in the active state.  If the timer
- * is not stopped, deleted, or reset in the mean time, the callback function
- * associated with the timer will get called 'n' ticks after xTimerReset() was
- * called, where 'n' is the timers defined period.
- *
- * It is valid to call xTimerReset() before the scheduler has been started, but
- * when this is done the timer will not actually start until the scheduler is
- * started, and the timers expiry time will be relative to when the scheduler is
- * started, not relative to when xTimerReset() was called.
- *
- * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
- * to be available.
- *
- * @param xTimer The handle of the timer being reset/started/restarted.
- *
- * @param xTicksToWait Specifies the time, in ticks, that the calling task should
- * be held in the Blocked state to wait for the reset command to be successfully
- * sent to the timer command queue, should the queue already be full when
- * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
- * before the scheduler is started.
- *
- * @return pdFAIL will be returned if the reset command could not be sent to
- * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
- * be returned if the command was successfully sent to the timer command queue.
- * When the command is actually processed will depend on the priority of the
- * timer service/daemon task relative to other tasks in the system, although the
- * timers expiry time is relative to when xTimerStart() is actually called.  The
- * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- * @verbatim
- * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
- * // without a key being pressed, then the LCD back-light is switched off.  In
- * // this case, the timer is a one-shot timer.
- *
- * TimerHandle_t xBacklightTimer = NULL;
- *
- * // The callback function assigned to the one-shot timer.  In this case the
- * // parameter is not used.
- * void vBacklightTimerCallback( TimerHandle_t pxTimer )
- * {
- *     // The timer expired, therefore 5 seconds must have passed since a key
- *     // was pressed.  Switch off the LCD back-light.
- *     vSetBacklightState( BACKLIGHT_OFF );
- * }
- *
- * // The key press event handler.
- * void vKeyPressEventHandler( char cKey )
- * {
- *     // Ensure the LCD back-light is on, then reset the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
- *     // if it cannot be sent immediately.
- *     vSetBacklightState( BACKLIGHT_ON );
- *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
- *     {
- *         // The reset command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // Perform the rest of the key processing here.
- * }
- *
- * void main( void )
- * {
- * int32_t x;
- *
- *     // Create then start the one-shot timer that is responsible for turning
- *     // the back-light off if no keys are pressed within a 5 second period.
- *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
- *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
- *                                     pdFALSE,                    // The timer is a one-shot timer.
- *                                     0,                          // The id is not used by the callback so can take any value.
- *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
- *                                   );
- *
- *     if( xBacklightTimer == NULL )
- *     {
- *         // The timer was not created.
- *     }
- *     else
- *     {
- *         // Start the timer.  No block time is specified, and even if one was
- *         // it would be ignored because the scheduler has not yet been
- *         // started.
- *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
- *         {
- *             // The timer could not be set into the Active state.
- *         }
- *     }
- *
- *     // ...
- *     // Create tasks here.
- *     // ...
- *
- *     // Starting the scheduler will start the timer running as it has already
- *     // been set into the active state.
- *     vTaskStartScheduler();
- *
- *     // Should not reach here.
- *     for( ;; );
- * }
- * @endverbatim
- */
-#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
-
-/**
- * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
- *									BaseType_t *pxHigherPriorityTaskWoken );
- *
- * A version of xTimerStart() that can be called from an interrupt service
- * routine.
- *
- * @param xTimer The handle of the timer being started/restarted.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerStartFromISR() writes a message to the timer
- * command queue, so has the potential to transition the timer service/daemon
- * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
- * timer service/daemon task to leave the Blocked state, and the timer service/
- * daemon task has a priority equal to or greater than the currently executing
- * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
- * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
- * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
- * be performed before the interrupt exits.
- *
- * @return pdFAIL will be returned if the start command could not be sent to
- * the timer command queue.  pdPASS will be returned if the command was
- * successfully sent to the timer command queue.  When the command is actually
- * processed will depend on the priority of the timer service/daemon task
- * relative to other tasks in the system, although the timers expiry time is
- * relative to when xTimerStartFromISR() is actually called.  The timer
- * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
- * configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This scenario assumes xBacklightTimer has already been created.  When a
- * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
- * // without a key being pressed, then the LCD back-light is switched off.  In
- * // this case, the timer is a one-shot timer, and unlike the example given for
- * // the xTimerReset() function, the key press event handler is an interrupt
- * // service routine.
- *
- * // The callback function assigned to the one-shot timer.  In this case the
- * // parameter is not used.
- * void vBacklightTimerCallback( TimerHandle_t pxTimer )
- * {
- *     // The timer expired, therefore 5 seconds must have passed since a key
- *     // was pressed.  Switch off the LCD back-light.
- *     vSetBacklightState( BACKLIGHT_OFF );
- * }
- *
- * // The key press interrupt service routine.
- * void vKeyPressEventInterruptHandler( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // Ensure the LCD back-light is on, then restart the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  This is an interrupt service routine so can only
- *     // call FreeRTOS API functions that end in "FromISR".
- *     vSetBacklightState( BACKLIGHT_ON );
- *
- *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
- *     // as both cause the timer to re-calculate its expiry time.
- *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
- *     // declared (in this function).
- *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The start command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // Perform the rest of the key processing here.
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endverbatim
- */
-#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
-
-/**
- * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
- *									BaseType_t *pxHigherPriorityTaskWoken );
- *
- * A version of xTimerStop() that can be called from an interrupt service
- * routine.
- *
- * @param xTimer The handle of the timer being stopped.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerStopFromISR() writes a message to the timer
- * command queue, so has the potential to transition the timer service/daemon
- * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
- * timer service/daemon task to leave the Blocked state, and the timer service/
- * daemon task has a priority equal to or greater than the currently executing
- * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
- * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
- * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
- * be performed before the interrupt exits.
- *
- * @return pdFAIL will be returned if the stop command could not be sent to
- * the timer command queue.  pdPASS will be returned if the command was
- * successfully sent to the timer command queue.  When the command is actually
- * processed will depend on the priority of the timer service/daemon task
- * relative to other tasks in the system.  The timer service/daemon task
- * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This scenario assumes xTimer has already been created and started.  When
- * // an interrupt occurs, the timer should be simply stopped.
- *
- * // The interrupt service routine that stops the timer.
- * void vAnExampleInterruptServiceRoutine( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // The interrupt has occurred - simply stop the timer.
- *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
- *     // (within this function).  As this is an interrupt service routine, only
- *     // FreeRTOS API functions that end in "FromISR" can be used.
- *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The stop command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endverbatim
- */
-#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
-
-/**
- * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
- *										 TickType_t xNewPeriod,
- *										 BaseType_t *pxHigherPriorityTaskWoken );
- *
- * A version of xTimerChangePeriod() that can be called from an interrupt
- * service routine.
- *
- * @param xTimer The handle of the timer that is having its period changed.
- *
- * @param xNewPeriod The new period for xTimer. Timer periods are specified in
- * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
- * that has been specified in milliseconds.  For example, if the timer must
- * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
- * if the timer must expire after 500ms, then xNewPeriod can be set to
- * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
- * or equal to 1000.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
- * timer command queue, so has the potential to transition the timer service/
- * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
- * causes the timer service/daemon task to leave the Blocked state, and the
- * timer service/daemon task has a priority equal to or greater than the
- * currently executing task (the task that was interrupted), then
- * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
- * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
- * this value to pdTRUE then a context switch should be performed before the
- * interrupt exits.
- *
- * @return pdFAIL will be returned if the command to change the timers period
- * could not be sent to the timer command queue.  pdPASS will be returned if the
- * command was successfully sent to the timer command queue.  When the command
- * is actually processed will depend on the priority of the timer service/daemon
- * task relative to other tasks in the system.  The timer service/daemon task
- * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This scenario assumes xTimer has already been created and started.  When
- * // an interrupt occurs, the period of xTimer should be changed to 500ms.
- *
- * // The interrupt service routine that changes the period of xTimer.
- * void vAnExampleInterruptServiceRoutine( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // The interrupt has occurred - change the period of xTimer to 500ms.
- *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
- *     // (within this function).  As this is an interrupt service routine, only
- *     // FreeRTOS API functions that end in "FromISR" can be used.
- *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The command to change the timers period was not executed
- *         // successfully.  Take appropriate action here.
- *     }
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endverbatim
- */
-#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
-
-/**
- * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
- *									BaseType_t *pxHigherPriorityTaskWoken );
- *
- * A version of xTimerReset() that can be called from an interrupt service
- * routine.
- *
- * @param xTimer The handle of the timer that is to be started, reset, or
- * restarted.
- *
- * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
- * of its time in the Blocked state, waiting for messages to arrive on the timer
- * command queue.  Calling xTimerResetFromISR() writes a message to the timer
- * command queue, so has the potential to transition the timer service/daemon
- * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
- * timer service/daemon task to leave the Blocked state, and the timer service/
- * daemon task has a priority equal to or greater than the currently executing
- * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
- * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
- * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
- * be performed before the interrupt exits.
- *
- * @return pdFAIL will be returned if the reset command could not be sent to
- * the timer command queue.  pdPASS will be returned if the command was
- * successfully sent to the timer command queue.  When the command is actually
- * processed will depend on the priority of the timer service/daemon task
- * relative to other tasks in the system, although the timers expiry time is
- * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
- * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
- *
- * Example usage:
- * @verbatim
- * // This scenario assumes xBacklightTimer has already been created.  When a
- * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
- * // without a key being pressed, then the LCD back-light is switched off.  In
- * // this case, the timer is a one-shot timer, and unlike the example given for
- * // the xTimerReset() function, the key press event handler is an interrupt
- * // service routine.
- *
- * // The callback function assigned to the one-shot timer.  In this case the
- * // parameter is not used.
- * void vBacklightTimerCallback( TimerHandle_t pxTimer )
- * {
- *     // The timer expired, therefore 5 seconds must have passed since a key
- *     // was pressed.  Switch off the LCD back-light.
- *     vSetBacklightState( BACKLIGHT_OFF );
- * }
- *
- * // The key press interrupt service routine.
- * void vKeyPressEventInterruptHandler( void )
- * {
- * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
- *
- *     // Ensure the LCD back-light is on, then reset the timer that is
- *     // responsible for turning the back-light off after 5 seconds of
- *     // key inactivity.  This is an interrupt service routine so can only
- *     // call FreeRTOS API functions that end in "FromISR".
- *     vSetBacklightState( BACKLIGHT_ON );
- *
- *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
- *     // as both cause the timer to re-calculate its expiry time.
- *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
- *     // declared (in this function).
- *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
- *     {
- *         // The reset command was not executed successfully.  Take appropriate
- *         // action here.
- *     }
- *
- *     // Perform the rest of the key processing here.
- *
- *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
- *     // should be performed.  The syntax required to perform a context switch
- *     // from inside an ISR varies from port to port, and from compiler to
- *     // compiler.  Inspect the demos for the port you are using to find the
- *     // actual syntax required.
- *     if( xHigherPriorityTaskWoken != pdFALSE )
- *     {
- *         // Call the interrupt safe yield function here (actual function
- *         // depends on the FreeRTOS port being used).
- *     }
- * }
- * @endverbatim
- */
-#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
-
-
-/**
- * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
- *                                          void *pvParameter1,
- *                                          uint32_t ulParameter2,
- *                                          BaseType_t *pxHigherPriorityTaskWoken );
- *
- *
- * Used from application interrupt service routines to defer the execution of a
- * function to the RTOS daemon task (the timer service task, hence this function
- * is implemented in timers.c and is prefixed with 'Timer').
- *
- * Ideally an interrupt service routine (ISR) is kept as short as possible, but
- * sometimes an ISR either has a lot of processing to do, or needs to perform
- * processing that is not deterministic.  In these cases
- * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
- * to the RTOS daemon task.
- *
- * A mechanism is provided that allows the interrupt to return directly to the
- * task that will subsequently execute the pended callback function.  This
- * allows the callback function to execute contiguously in time with the
- * interrupt - just as if the callback had executed in the interrupt itself.
- *
- * @param xFunctionToPend The function to execute from the timer service/
- * daemon task.  The function must conform to the PendedFunction_t
- * prototype.
- *
- * @param pvParameter1 The value of the callback function's first parameter.
- * The parameter has a void * type to allow it to be used to pass any type.
- * For example, unsigned longs can be cast to a void *, or the void * can be
- * used to point to a structure.
- *
- * @param ulParameter2 The value of the callback function's second parameter.
- *
- * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
- * will result in a message being sent to the timer daemon task.  If the
- * priority of the timer daemon task (which is set using
- * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
- * the currently running task (the task the interrupt interrupted) then
- * *pxHigherPriorityTaskWoken will be set to pdTRUE within
- * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
- * requested before the interrupt exits.  For that reason
- * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
- * example code below.
- *
- * @return pdPASS is returned if the message was successfully sent to the
- * timer daemon task, otherwise pdFALSE is returned.
- *
- * Example usage:
- * @verbatim
- *
- *	// The callback function that will execute in the context of the daemon task.
- *  // Note callback functions must all use this same prototype.
- *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
- *	{
- *		BaseType_t xInterfaceToService;
- *
- *		// The interface that requires servicing is passed in the second
- *      // parameter.  The first parameter is not used in this case.
- *		xInterfaceToService = ( BaseType_t ) ulParameter2;
- *
- *		// ...Perform the processing here...
- *	}
- *
- *	// An ISR that receives data packets from multiple interfaces
- *  void vAnISR( void )
- *	{
- *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
- *
- *		// Query the hardware to determine which interface needs processing.
- *		xInterfaceToService = prvCheckInterfaces();
- *
- *      // The actual processing is to be deferred to a task.  Request the
- *      // vProcessInterface() callback function is executed, passing in the
- *		// number of the interface that needs processing.  The interface to
- *		// service is passed in the second parameter.  The first parameter is
- *		// not used in this case.
- *		xHigherPriorityTaskWoken = pdFALSE;
- *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
- *
- *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
- *		// switch should be requested.  The macro used is port specific and will
- *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
- *		// the documentation page for the port being used.
- *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
- *
- *	}
- * @endverbatim
- */
-BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
-
- /**
-  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
-  *                                    void *pvParameter1,
-  *                                    uint32_t ulParameter2,
-  *                                    TickType_t xTicksToWait );
-  *
-  *
-  * Used to defer the execution of a function to the RTOS daemon task (the timer
-  * service task, hence this function is implemented in timers.c and is prefixed
-  * with 'Timer').
-  *
-  * @param xFunctionToPend The function to execute from the timer service/
-  * daemon task.  The function must conform to the PendedFunction_t
-  * prototype.
-  *
-  * @param pvParameter1 The value of the callback function's first parameter.
-  * The parameter has a void * type to allow it to be used to pass any type.
-  * For example, unsigned longs can be cast to a void *, or the void * can be
-  * used to point to a structure.
-  *
-  * @param ulParameter2 The value of the callback function's second parameter.
-  *
-  * @param xTicksToWait Calling this function will result in a message being
-  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
-  * time the calling task should remain in the Blocked state (so not using any
-  * processing time) for space to become available on the timer queue if the
-  * queue is found to be full.
-  *
-  * @return pdPASS is returned if the message was successfully sent to the
-  * timer daemon task, otherwise pdFALSE is returned.
-  *
-  */
-BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-/**
- * const char * const pcTimerGetName( TimerHandle_t xTimer );
- *
- * Returns the name that was assigned to a timer when the timer was created.
- *
- * @param xTimer The handle of the timer being queried.
- *
- * @return The name assigned to the timer specified by the xTimer parameter.
- */
-const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-/**
- * void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload );
- *
- * Updates a timer to be either an autoreload timer, in which case the timer
- * automatically resets itself each time it expires, or a one shot timer, in
- * which case the timer will only expire once unless it is manually restarted.
- *
- * @param xTimer The handle of the timer being updated.
- *
- * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
- * expire repeatedly with a frequency set by the timer's period (see the
- * xTimerPeriodInTicks parameter of the xTimerCreate() API function).  If
- * uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
- * enter the dormant state after it expires.
- */
-void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) PRIVILEGED_FUNCTION;
-
-/**
- * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
- *
- * Returns the period of a timer.
- *
- * @param xTimer The handle of the timer being queried.
- *
- * @return The period of the timer in ticks.
- */
-TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/**
-* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
-*
-* Returns the time in ticks at which the timer will expire.  If this is less
-* than the current tick count then the expiry time has overflowed from the
-* current time.
-*
-* @param xTimer The handle of the timer being queried.
-*
-* @return If the timer is running then the time in ticks at which the timer
-* will next expire is returned.  If the timer is not running then the return
-* value is undefined.
-*/
-TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-
-/*
- * Functions beyond this part are not part of the public API and are intended
- * for use by the kernel only.
- */
-BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
-BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
-
-#if( configUSE_TRACE_FACILITY == 1 )
-	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber ) PRIVILEGED_FUNCTION;
-	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-#endif /* TIMERS_H */
-
-
-
diff --git a/FreeRTOS/Source/list.c b/FreeRTOS/Source/list.c
deleted file mode 100755
index 21dabde..0000000
--- a/FreeRTOS/Source/list.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#include 
-#include "FreeRTOS.h"
-#include "list.h"
-
-/*-----------------------------------------------------------
- * PUBLIC LIST API documented in list.h
- *----------------------------------------------------------*/
-
-void vListInitialise( List_t * const pxList )
-{
-	/* The list structure contains a list item which is used to mark the
-	end of the list.  To initialise the list the list end is inserted
-	as the only list entry. */
-	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-
-	/* The list end value is the highest possible value in the list to
-	ensure it remains at the end of the list. */
-	pxList->xListEnd.xItemValue = portMAX_DELAY;
-
-	/* The list end next and previous pointers point to itself so we know
-	when the list is empty. */
-	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
-
-	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
-
-	/* Write known values into the list if
-	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
-	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
-}
-/*-----------------------------------------------------------*/
-
-void vListInitialiseItem( ListItem_t * const pxItem )
-{
-	/* Make sure the list item is not recorded as being on a list. */
-	pxItem->pxContainer = NULL;
-
-	/* Write known values into the list item if
-	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
-	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
-	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
-}
-/*-----------------------------------------------------------*/
-
-void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
-{
-ListItem_t * const pxIndex = pxList->pxIndex;
-
-	/* Only effective when configASSERT() is also defined, these tests may catch
-	the list data structures being overwritten in memory.  They will not catch
-	data errors caused by incorrect configuration or use of FreeRTOS. */
-	listTEST_LIST_INTEGRITY( pxList );
-	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
-
-	/* Insert a new list item into pxList, but rather than sort the list,
-	makes the new list item the last item to be removed by a call to
-	listGET_OWNER_OF_NEXT_ENTRY(). */
-	pxNewListItem->pxNext = pxIndex;
-	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
-
-	/* Only used during decision coverage testing. */
-	mtCOVERAGE_TEST_DELAY();
-
-	pxIndex->pxPrevious->pxNext = pxNewListItem;
-	pxIndex->pxPrevious = pxNewListItem;
-
-	/* Remember which list the item is in. */
-	pxNewListItem->pxContainer = pxList;
-
-	( pxList->uxNumberOfItems )++;
-}
-/*-----------------------------------------------------------*/
-
-void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
-{
-ListItem_t *pxIterator;
-const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
-
-	/* Only effective when configASSERT() is also defined, these tests may catch
-	the list data structures being overwritten in memory.  They will not catch
-	data errors caused by incorrect configuration or use of FreeRTOS. */
-	listTEST_LIST_INTEGRITY( pxList );
-	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
-
-	/* Insert the new list item into the list, sorted in xItemValue order.
-
-	If the list already contains a list item with the same item value then the
-	new list item should be placed after it.  This ensures that TCBs which are
-	stored in ready lists (all of which have the same xItemValue value) get a
-	share of the CPU.  However, if the xItemValue is the same as the back marker
-	the iteration loop below will not end.  Therefore the value is checked
-	first, and the algorithm slightly modified if necessary. */
-	if( xValueOfInsertion == portMAX_DELAY )
-	{
-		pxIterator = pxList->xListEnd.pxPrevious;
-	}
-	else
-	{
-		/* *** NOTE ***********************************************************
-		If you find your application is crashing here then likely causes are
-		listed below.  In addition see https://www.freertos.org/FAQHelp.html for
-		more tips, and ensure configASSERT() is defined!
-		https://www.freertos.org/a00110.html#configASSERT
-
-			1) Stack overflow -
-			   see https://www.freertos.org/Stacks-and-stack-overflow-checking.html
-			2) Incorrect interrupt priority assignment, especially on Cortex-M
-			   parts where numerically high priority values denote low actual
-			   interrupt priorities, which can seem counter intuitive.  See
-			   https://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
-			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
-			   https://www.freertos.org/a00110.html
-			3) Calling an API function from within a critical section or when
-			   the scheduler is suspended, or calling an API function that does
-			   not end in "FromISR" from an interrupt.
-			4) Using a queue or semaphore before it has been initialised or
-			   before the scheduler has been started (are interrupts firing
-			   before vTaskStartScheduler() has been called?).
-		**********************************************************************/
-
-		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 !e9087 The mini list structure is used as the list end to save RAM.  This is checked and valid. *//*lint !e440 The iterator moves to a different value, not xValueOfInsertion. */
-		{
-			/* There is nothing to do here, just iterating to the wanted
-			insertion position. */
-		}
-	}
-
-	pxNewListItem->pxNext = pxIterator->pxNext;
-	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
-	pxNewListItem->pxPrevious = pxIterator;
-	pxIterator->pxNext = pxNewListItem;
-
-	/* Remember which list the item is in.  This allows fast removal of the
-	item later. */
-	pxNewListItem->pxContainer = pxList;
-
-	( pxList->uxNumberOfItems )++;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
-{
-/* The list item knows which list it is in.  Obtain the list from the list
-item. */
-List_t * const pxList = pxItemToRemove->pxContainer;
-
-	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
-	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
-
-	/* Only used during decision coverage testing. */
-	mtCOVERAGE_TEST_DELAY();
-
-	/* Make sure the index is left pointing to a valid item. */
-	if( pxList->pxIndex == pxItemToRemove )
-	{
-		pxList->pxIndex = pxItemToRemove->pxPrevious;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	pxItemToRemove->pxContainer = NULL;
-	( pxList->uxNumberOfItems )--;
-
-	return pxList->uxNumberOfItems;
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/ARMv8M/ReadMe.txt b/FreeRTOS/Source/portable/ARMv8M/ReadMe.txt
deleted file mode 100755
index 9b12e54..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/ReadMe.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
-Do not use the files located here!  These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
-FreeRTOS release.
-
-If your Cortex-M33 application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
-
-If your Cortex-M33 application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
diff --git a/FreeRTOS/Source/portable/ARMv8M/copy_files.py b/FreeRTOS/Source/portable/ARMv8M/copy_files.py
deleted file mode 100755
index 88fce0b..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/copy_files.py
+++ /dev/null
@@ -1,103 +0,0 @@
-#/*
-# * FreeRTOS Kernel V10.2.1
-# * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-# *
-# * Permission is hereby granted, free of charge, to any person obtaining a copy of
-# * this software and associated documentation files (the "Software"), to deal in
-# * the Software without restriction, including without limitation the rights to
-# * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-# * the Software, and to permit persons to whom the Software is furnished to do so,
-# * subject to the following conditions:
-# *
-# * The above copyright notice and this permission notice shall be included in all
-# * copies or substantial portions of the Software.
-# *
-# * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-# * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-# * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-# * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-# * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-# * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-# *
-# * http://www.FreeRTOS.org
-# * http://aws.amazon.com/freertos
-# *
-# * 1 tab == 4 spaces!
-# */
-
-import os
-import shutil
-
-_THIS_FILE_DIRECTORY_ = os.path.dirname(os.path.realpath(__file__))
-_FREERTOS_PORTABLE_DIRECTORY_ = os.path.dirname(_THIS_FILE_DIRECTORY_)
-
-_COMPILERS_ = ['GCC', 'IAR']
-_ARCH_NS_ = ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
-_ARCH_S_ = ['ARM_CM33', 'ARM_CM23']
-
-_SUPPORTED_CONFIGS_ =   {
-                            'GCC' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ'],
-                            'IAR' : ['ARM_CM33', 'ARM_CM33_NTZ', 'ARM_CM23', 'ARM_CM23_NTZ']
-                        }
-
-# Files to be complied in the Secure Project
-_SECURE_FILE_PATHS_ = [
-    os.path.join('secure', 'context'),
-    os.path.join('secure', 'context', 'portable', '_COMPILER_ARCH_'),
-    os.path.join('secure', 'heap'),
-    os.path.join('secure', 'init'),
-    os.path.join('secure', 'macros')
-]
-
-# Files to be complied in the Non-Secure Project
-_NONSECURE_FILE_PATHS_ = [
-    'non_secure',
-    os.path.join('non_secure', 'portable', '_COMPILER_ARCH_')
-]
-
-
-def is_supported_config(compiler, arch):
-    return arch in _SUPPORTED_CONFIGS_[compiler]
-
-
-def copy_files_in_dir(src_abs_path, dst_abs_path):
-    for src_file in os.listdir(src_abs_path):
-        src_file_abs_path = os.path.join(src_abs_path, src_file)
-        if os.path.isfile(src_file_abs_path) and src_file != 'ReadMe.txt':
-            if not os.path.exists(dst_abs_path):
-                os.makedirs(dst_abs_path)
-            print('Copying {}...'.format(os.path.basename(src_file_abs_path)))
-            shutil.copy2(src_file_abs_path, dst_abs_path)
-
-
-def copy_files_for_compiler_and_arch(compiler, arch, src_paths, dst_path):
-    _COMPILER_ARCH_ = os.path.join(compiler, arch)
-    for src_path in src_paths:
-        src_path_sanitized = src_path.replace('_COMPILER_ARCH_', _COMPILER_ARCH_ )
-
-        src_abs_path = os.path.join(_THIS_FILE_DIRECTORY_, src_path_sanitized)
-        dst_abs_path = os.path.join(_FREERTOS_PORTABLE_DIRECTORY_, _COMPILER_ARCH_, dst_path)
-
-        copy_files_in_dir(src_abs_path, dst_abs_path)
-
-
-def copy_files():
-    # Copy Secure Files
-    for compiler in _COMPILERS_:
-        for arch in _ARCH_S_:
-            if is_supported_config(compiler, arch):
-                copy_files_for_compiler_and_arch(compiler, arch, _SECURE_FILE_PATHS_, 'secure')
-
-    # Copy Non-Secure Files
-    for compiler in _COMPILERS_:
-        for arch in _ARCH_NS_:
-            if is_supported_config(compiler, arch):
-                copy_files_for_compiler_and_arch(compiler, arch, _NONSECURE_FILE_PATHS_, 'non_secure')
-
-
-def main():
-    copy_files()
-
-
-if __name__ == '__main__':
-    main()
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/ReadMe.txt b/FreeRTOS/Source/portable/ARMv8M/non_secure/ReadMe.txt
deleted file mode 100755
index c74a534..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/ReadMe.txt
+++ /dev/null
@@ -1,11 +0,0 @@
-This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
-Do not use the files located here!  These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
-FreeRTOS release.
-
-If your Cortex-M33 application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
-
-If your Cortex-M33 application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
-
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/port.c b/FreeRTOS/Source/portable/ARMv8M/non_secure/port.c
deleted file mode 100755
index bd85a6f..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
deleted file mode 100755
index c8345c7..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portasm.c
+++ /dev/null
@@ -1,468 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r5, #1										\n" /* r5 = 1. */
-	"	bics r4, r5										\n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	movs r5, #4										\n" /* r5 = 4. */
-	"	str  r5, [r2]									\n" /* Program RNR = 4. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read first set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write first set of RBAR/RLAR registers. */
-	"	movs r5, #5										\n" /* r5 = 5. */
-	"	str  r5, [r2]									\n" /* Program RNR = 5. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read second set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write second set of RBAR/RLAR registers. */
-	"	movs r5, #6										\n" /* r5 = 6. */
-	"	str  r5, [r2]									\n" /* Program RNR = 6. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read third set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write third set of RBAR/RLAR registers. */
-	"	movs r5, #7										\n" /* r5 = 7. */
-	"	str  r5, [r2]									\n" /* Program RNR = 7. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write fourth set of RBAR/RLAR registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r5, #1										\n" /* r5 = 1. */
-	"	orrs r4, r5										\n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	"	ldr  r5, xSecureContextConst2					\n"
-	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	"	ldr  r4, xSecureContextConst2					\n"
-	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	"xSecureContextConst2: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	tst r0, r1										\n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-	"	beq running_privileged							\n" /* If the result of previous AND operation was 0, branch. */
-	"	movs r0, #0										\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	bx lr											\n" /* Return. */
-	" running_privileged:								\n"
-	"	movs r0, #1										\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs r0, control									\n" /* Read the CONTROL register. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	bics r0, r1										\n" /* Clear the bit 0. */
-	"	msr control, r0									\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	orrs r0, r1										\n" /* r0 = r0 | r1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* To avoid compiler warnings.  The return statement will never be reached,
-	 * but some compilers warn if it is not included, while others won't compile
-	 * if it is. */
-	return 0;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* Just to avoid compiler warning.  ulMask is used from the asm code but
-	 * the compiler can't see that.  Some compilers generate warnings without
-	 * the following line, while others generate warnings if the line is
-	 * included. */
-	( void ) ulMask;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"	.extern SecureContext_SaveContext				\n"
-	"	.extern SecureContext_LoadContext				\n"
-	"													\n"
-	"	mrs r1, psp										\n" /* Read PSP in r1. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-	"													\n"
-	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
-	"	push {r0-r2, r14}								\n"
-	"	bl SecureContext_SaveContext					\n"
-	"	pop {r0-r3}										\n" /* LR is now in r3. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"	b select_next_task								\n"
-	"													\n"
-	" save_ns_context:									\n"
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
-	"	stmia r1!, {r4-r7}								\n" /* Store the low registers that are not saved automatically. */
-	"	mov r4, r8										\n" /* r4 = r8. */
-	"	mov r5, r9										\n" /* r5 = r9. */
-	"	mov r6, r10										\n" /* r6 = r10. */
-	"	mov r7, r11										\n" /* r7 = r11. */
-	"	stmia r1!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	subs r1, r1, #48								\n" /* r1 = r1 - 48. */
-	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r7}							\n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
-	"	mov r4, r8										\n" /* r4 = r8. */
-	"	mov r5, r9										\n" /* r5 = r9. */
-	"	mov r6, r10										\n" /* r6 = r10. */
-	"	mov r7, r11										\n" /* r7 = r11. */
-	"	stmia r1!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" select_next_task:									\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r5, #1										\n" /* r5 = 1. */
-	"	bics r4, r5										\n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	movs r5, #4										\n" /* r5 = 4. */
-	"	str  r5, [r2]									\n" /* Program RNR = 4. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read first set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write first set of RBAR/RLAR registers. */
-	"	movs r5, #5										\n" /* r5 = 5. */
-	"	str  r5, [r2]									\n" /* Program RNR = 5. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read second set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write second set of RBAR/RLAR registers. */
-	"	movs r5, #6										\n" /* r5 = 6. */
-	"	str  r5, [r2]									\n" /* Program RNR = 6. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read third set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write third set of RBAR/RLAR registers. */
-	"	movs r5, #7										\n" /* r5 = 7. */
-	"	str  r5, [r2]									\n" /* Program RNR = 7. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write fourth set of RBAR/RLAR registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r5, #1										\n" /* r5 = 1. */
-	"	orrs r4, r5										\n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r4}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r4}										\n"
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#else /* configENABLE_MPU */
-	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r3}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r3}										\n"
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" restore_ns_context:								\n"
-	"	adds r1, r1, #16								\n" /* Move to the high registers. */
-	"	ldmia r1!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
-	"	mov r8, r4										\n" /* r8 = r4. */
-	"	mov r9, r5										\n" /* r9 = r5. */
-	"	mov r10, r6										\n" /* r10 = r6. */
-	"	mov r11, r7										\n" /* r11 = r7. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	subs r1, r1, #32								\n" /* Go back to the low registers. */
-	"	ldmia r1!, {r4-r7}								\n" /* Restore the low registers that are not automatically restored. */
-	"	bx lr											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	"xSecureContextConst: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	movs r0, #4										\n"
-	"	mov r1, lr										\n"
-	"	tst r0, r1										\n"
-	"	beq stacking_used_msp							\n"
-	"	mrs r0, psp										\n"
-	"	ldr r2, svchandler_address_const				\n"
-	"	bx r2											\n"
-	" stacking_used_msp:								\n"
-	"	mrs r0, msp										\n"
-	"	ldr r2, svchandler_address_const				\n"
-	"	bx r2											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
-	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
-	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
-	"	beq free_secure_context							\n"
-	"	bx lr											\n" /* There is no secure context (xSecureContext is NULL). */
-	" free_secure_context:								\n"
-	"	svc %0											\n" /* Secure context is freed in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
deleted file mode 100755
index bbab1b7..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M23"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
deleted file mode 100755
index 5b8e604..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portasm.c
+++ /dev/null
@@ -1,381 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r4, #1										\n" /* r4 = 1. */
-	"	bics r3, r4										\n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
-	"	str r3, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r1]									\n" /* r4 = *r1 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str  r4, [r2]									\n" /* Program RNR = 4. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read first set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write first set of RBAR/RLAR registers. */
-	"	movs r4, #5										\n" /* r4 = 5. */
-	"	str  r4, [r2]									\n" /* Program RNR = 5. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read second set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write second set of RBAR/RLAR registers. */
-	"	movs r4, #6										\n" /* r4 = 6. */
-	"	str  r4, [r2]									\n" /* Program RNR = 6. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read third set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write third set of RBAR/RLAR registers. */
-	"	movs r4, #7										\n" /* r4 = 7. */
-	"	str  r4, [r2]									\n" /* Program RNR = 7. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write fourth set of RBAR/RLAR registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r4, #1										\n" /* r4 = 1. */
-	"	orrs r3, r4										\n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
-	"	str r3, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	tst r0, r1										\n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-	"	beq running_privileged							\n" /* If the result of previous AND operation was 0, branch. */
-	"	movs r0, #0										\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	bx lr											\n" /* Return. */
-	" running_privileged:								\n"
-	"	movs r0, #1										\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs  r0, control								\n" /* Read the CONTROL register. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	bics r0, r1										\n" /* Clear the bit 0. */
-	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	orrs r0, r1										\n" /* r0 = r0 | r1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* To avoid compiler warnings.  The return statement will never be reached,
-	 * but some compilers warn if it is not included, while others won't compile
-	 * if it is. */
-	return 0;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* Just to avoid compiler warning.  ulMask is used from the asm code but
-	 * the compiler can't see that.  Some compilers generate warnings without
-	 * the following line, while others generate warnings if the line is
-	 * included. */
-	( void ) ulMask;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	mrs r0, psp										\n" /* Read PSP in r0. */
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r0, r0, #44								\n" /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
-	"	mrs r2, control									\n" /* r2 = CONTROL. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r0!, {r1-r7}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
-	"	mov r4, r8										\n" /* r4 = r8. */
-	"	mov r5, r9										\n" /* r5 = r9. */
-	"	mov r6, r10										\n" /* r6 = r10. */
-	"	mov r7, r11										\n" /* r7 = r11. */
-	"	stmia r0!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
-	#else /* configENABLE_MPU */
-	"	subs r0, r0, #40								\n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
-	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r0!, {r2-r7}								\n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
-	"	mov r4, r8										\n" /* r4 = r8. */
-	"	mov r5, r9										\n" /* r5 = r9. */
-	"	mov r6, r10										\n" /* r6 = r10. */
-	"	mov r7, r11										\n" /* r7 = r11. */
-	"	stmia r0!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r4, #1										\n" /* r4 = 1. */
-	"	bics r3, r4										\n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
-	"	str r3, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r1]									\n" /* r4 = *r1 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str  r4, [r2]									\n" /* Program RNR = 4. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read first set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write first set of RBAR/RLAR registers. */
-	"	movs r4, #5										\n" /* r4 = 5. */
-	"	str  r4, [r2]									\n" /* Program RNR = 5. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read second set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write second set of RBAR/RLAR registers. */
-	"	movs r4, #6										\n" /* r4 = 6. */
-	"	str  r4, [r2]									\n" /* Program RNR = 6. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read third set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write third set of RBAR/RLAR registers. */
-	"	movs r4, #7										\n" /* r4 = 7. */
-	"	str  r4, [r2]									\n" /* Program RNR = 7. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write fourth set of RBAR/RLAR registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r4, #1										\n" /* r4 = 1. */
-	"	orrs r3, r4										\n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
-	"	str r3, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	adds r0, r0, #28								\n" /* Move to the high registers. */
-	"	ldmia r0!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
-	"	mov r8, r4										\n" /* r8 = r4. */
-	"	mov r9, r5										\n" /* r9 = r5. */
-	"	mov r10, r6										\n" /* r10 = r6. */
-	"	mov r11, r7										\n" /* r11 = r7. */
-	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
-	"	subs r0, r0, #44								\n" /* Move to the starting of the saved context. */
-	"	ldmia r0!, {r1-r7}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
-	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
-	"	bx r3											\n"
-	#else /* configENABLE_MPU */
-	"	adds r0, r0, #24								\n" /* Move to the high registers. */
-	"	ldmia r0!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
-	"	mov r8, r4										\n" /* r8 = r4. */
-	"	mov r9, r5										\n" /* r9 = r5. */
-	"	mov r10, r6										\n" /* r10 = r6. */
-	"	mov r11, r7										\n" /* r11 = r7. */
-	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
-	"	subs r0, r0, #40								\n" /* Move to the starting of the saved context. */
-	"	ldmia r0!, {r2-r7}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	bx r3											\n"
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	movs r0, #4										\n"
-	"	mov r1, lr										\n"
-	"	tst r0, r1										\n"
-	"	beq stacking_used_msp							\n"
-	"	mrs r0, psp										\n"
-	"	ldr r2, svchandler_address_const				\n"
-	"	bx r2											\n"
-	" stacking_used_msp:								\n"
-	"	mrs r0, msp										\n"
-	"	ldr r2, svchandler_address_const				\n"
-	"	bx r2											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
deleted file mode 100755
index bbab1b7..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM23_NTZ/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M23"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
deleted file mode 100755
index 3a24f3a..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portasm.c
+++ /dev/null
@@ -1,415 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str  r4, [r2]									\n" /* Program RNR = 4. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r3!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	"	ldr  r5, xSecureContextConst2					\n"
-	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	"	ldr  r4, xSecureContextConst2					\n"
-	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	"xSecureContextConst2: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne											\n"
-	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs r0, control									\n" /* Read the CONTROL register. */
-	"	bic r0, #1										\n" /* Clear the bit 0. */
-	"	msr control, r0									\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	orr r0, #1										\n" /* r0 = r0 | 1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	cpsie f											\n"
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* To avoid compiler warnings.  The return statement will never be reached,
-	 * but some compilers warn if it is not included, while others won't compile
-	 * if it is. */
-	return 0;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* Just to avoid compiler warning.  ulMask is used from the asm code but
-	 * the compiler can't see that.  Some compilers generate warnings without
-	 * the following line, while others generate warnings if the line is
-	 * included. */
-	( void ) ulMask;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"	.extern SecureContext_SaveContext				\n"
-	"	.extern SecureContext_LoadContext				\n"
-	"													\n"
-	"	mrs r1, psp										\n" /* Read PSP in r1. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-	"													\n"
-	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
-	"	push {r0-r2, r14}								\n"
-	"	bl SecureContext_SaveContext					\n"
-	"	pop {r0-r3}										\n" /* LR is now in r3. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"	b select_next_task								\n"
-	"													\n"
-	" save_ns_context:									\n"
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vstmdbeq r1!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
-	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	subs r1, r1, #16								\n" /* r1 = r1 - 16. */
-	"	stm r1, {r0, r2-r4}								\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #12								\n" /* r1 = r1 + 12. */
-	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	subs r1, r1, #12								\n" /* r1 = r1 - 12. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" select_next_task:									\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str r4, [r2]									\n" /* Program RNR = 4. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r3!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r4}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r4}										\n"
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#else /* configENABLE_MPU */
-	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r3}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r3}										\n"
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" restore_ns_context:								\n"
-	"	ldmia r1!, {r4-r11}								\n" /* Restore the registers that are not automatically restored. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vldmiaeq r1!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	"xSecureContextConst: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	tst lr, #4										\n"
-	"	ite eq											\n"
-	"	mrseq r0, msp									\n"
-	"	mrsne r0, psp									\n"
-	"	ldr r1, svchandler_address_const				\n"
-	"	bx r1											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
-	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
-	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
-	"	it ne											\n"
-	"	svcne %0										\n" /* Secure context is freed in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
deleted file mode 100755
index d051ddc..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
deleted file mode 100755
index ba4a69c..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portasm.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr  r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r3, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r3, #4										\n" /* r3 = 4. */
-	"	str  r3, [r2]									\n" /* Program RNR = 4. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r1!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne											\n"
-	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs  r0, control								\n" /* Read the CONTROL register. */
-	"	bic r0, #1										\n" /* Clear the bit 0. */
-	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	orr r0, #1										\n" /* r0 = r0 | 1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	cpsie f											\n"
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* To avoid compiler warnings.  The return statement will never be reached,
-	 * but some compilers warn if it is not included, while others won't compile
-	 * if it is. */
-	return 0;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* Just to avoid compiler warning.  ulMask is used from the asm code but
-	 * the compiler can't see that.  Some compilers generate warnings without
-	 * the following line, while others generate warnings if the line is
-	 * included. */
-	( void ) ulMask;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	mrs r0, psp										\n" /* Read PSP in r0. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vstmdbeq r0!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
-	"	mrs r2, control									\n" /* r2 = CONTROL. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmdb r0!, {r1-r11}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
-	#else /* configENABLE_MPU */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmdb r0!, {r2-r11}								\n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
-	"													\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r3, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r3, #4										\n" /* r3 = 4. */
-	"	str r3, [r2]									\n" /* Program RNR = 4. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	ldr r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r1!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r0!, {r1-r11}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
-	#else /* configENABLE_MPU */
-	"	ldmia r0!, {r2-r11}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_FPU == 1 )
-	"	tst r3, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vldmiaeq r0!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
-	#else /* configENABLE_MPU */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	#endif /* configENABLE_MPU */
-	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
-	"	bx r3											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	tst lr, #4										\n"
-	"	ite eq											\n"
-	"	mrseq r0, msp									\n"
-	"	mrsne r0, psp									\n"
-	"	ldr r1, svchandler_address_const				\n"
-	"	bx r1											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
deleted file mode 100755
index d051ddc..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/GCC/ARM_CM33_NTZ/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
deleted file mode 100755
index b1a543a..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portasm.s
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	EXTERN pxCurrentTCB
-	EXTERN xSecureContext
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-	EXTERN SecureContext_SaveContext
-	EXTERN SecureContext_LoadContext
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vPortAllocateSecureContext
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMaskFromISR
-	PUBLIC vClearInterruptMaskFromISR
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-	PUBLIC vPortFreeSecureContext
-
-#if ( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	movs r1, #1								/* r1 = 1. */
-	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
-	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-	running_privileged:
-		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-		bx lr								/* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	movs r1, #1								/* r1 = 1. */
-	orrs r0, r1								/* r0 = r0 | r1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vPortAllocateSecureContext:
-	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r3, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	movs r5, #1								/* r5 = 1. */
-	bics r4, r5								/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
-	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str  r4, [r2]							/* Program MAIR0. */
-	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	movs r5, #4								/* r5 = 4. */
-	str  r5, [r2]							/* Program RNR = 4. */
-	ldmia r3!, {r6,r7}						/* Read first set of RBAR/RLAR from TCB. */
-	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
-	stmia r4!, {r6,r7}						/* Write first set of RBAR/RLAR registers. */
-	movs r5, #5								/* r5 = 5. */
-	str  r5, [r2]							/* Program RNR = 5. */
-	ldmia r3!, {r6,r7}						/* Read second set of RBAR/RLAR from TCB. */
-	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
-	stmia r4!, {r6,r7}						/* Write second set of RBAR/RLAR registers. */
-	movs r5, #6								/* r5 = 6. */
-	str  r5, [r2]							/* Program RNR = 6. */
-	ldmia r3!, {r6,r7}						/* Read third set of RBAR/RLAR from TCB. */
-	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
-	stmia r4!, {r6,r7}						/* Write third set of RBAR/RLAR registers. */
-	movs r5, #7								/* r5 = 7. */
-	str  r5, [r2]							/* Program RNR = 7. */
-	ldmia r3!, {r6,r7}						/* Read fourth set of RBAR/RLAR from TCB. */
-	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
-	stmia r4!, {r6,r7}						/* Write fourth set of RBAR/RLAR registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	movs r5, #1								/* r5 = 1. */
-	orrs r4, r5								/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	ldr  r5, =xSecureContext
-	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	msr  control, r3						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r4									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	ldr  r4, =xSecureContext
-	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs r0, control							/* Read the CONTROL register. */
-	movs r1, #1								/* r1 = 1. */
-	bics r0, r1								/* Clear the bit 0. */
-	msr control, r0							/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMaskFromISR:
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-/*-----------------------------------------------------------*/
-
-vClearInterruptMaskFromISR:
-	msr PRIMASK, r0
-	bx lr
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	mrs r1, psp								/* Read PSP in r1. */
-	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-
-	cbz r0, save_ns_context					/* No secure context to save. */
-	push {r0-r2, r14}
-	bl SecureContext_SaveContext
-	pop {r0-r3}								/* LR is now in r3. */
-	mov lr, r3								/* LR = r3. */
-	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r2, [r3]							/* Read pxCurrentTCB. */
-#if ( configENABLE_MPU == 1 )
-	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mrs r3, control							/* r3 = CONTROL. */
-	mov r4, lr								/* r4 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-#else /* configENABLE_MPU */
-	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
-#endif /* configENABLE_MPU */
-	b select_next_task
-
-	save_ns_context:
-		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r2, [r3]						/* Read pxCurrentTCB. */
-	#if ( configENABLE_MPU == 1 )
-		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #16					/* r1 = r1 + 16. */
-		stmia r1!, {r4-r7}					/* Store the low registers that are not saved automatically. */
-		mov r4, r8							/* r4 = r8. */
-		mov r5, r9							/* r5 = r9. */
-		mov r6, r10							/* r6 = r10. */
-		mov r7, r11							/* r7 = r11. */
-		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
-		mrs r3, control						/* r3 = CONTROL. */
-		mov r4, lr							/* r4 = LR/EXC_RETURN. */
-		subs r1, r1, #48					/* r1 = r1 - 48. */
-		stmia r1!, {r0, r2-r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
-		mov r3, lr							/* r3 = LR/EXC_RETURN. */
-		stmia r1!, {r0, r2-r7}				/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
-		mov r4, r8							/* r4 = r8. */
-		mov r5, r9							/* r5 = r9. */
-		mov r6, r10							/* r6 = r10. */
-		mov r7, r11							/* r7 = r11. */
-		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
-	#endif /* configENABLE_MPU */
-
-	select_next_task:
-		cpsid i
-		bl vTaskSwitchContext
-		cpsie i
-
-		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r3, [r2]						/* Read pxCurrentTCB. */
-		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-
-	#if ( configENABLE_MPU == 1 )
-		dmb									/* Complete outstanding transfers before disabling MPU. */
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
-		movs r5, #1							/* r5 = 1. */
-		bics r4, r5							/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
-		str r4, [r2]						/* Disable MPU. */
-
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
-		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-		str r4, [r2]						/* Program MAIR0. */
-		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-		movs r5, #4							/* r5 = 4. */
-		str  r5, [r2]						/* Program RNR = 4. */
-		ldmia r3!, {r6,r7}					/* Read first set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write first set of RBAR/RLAR registers. */
-		movs r5, #5							/* r5 = 5. */
-		str  r5, [r2]						/* Program RNR = 5. */
-		ldmia r3!, {r6,r7}					/* Read second set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write second set of RBAR/RLAR registers. */
-		movs r5, #6							/* r5 = 6. */
-		str  r5, [r2]						/* Program RNR = 6. */
-		ldmia r3!, {r6,r7}					/* Read third set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write third set of RBAR/RLAR registers. */
-		movs r5, #7							/* r5 = 7. */
-		str  r5, [r2]						/* Program RNR = 7. */
-		ldmia r3!, {r6,r7}					/* Read fourth set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write fourth set of RBAR/RLAR registers. */
-
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
-		movs r5, #1							/* r5 = 1. */
-		orrs r4, r5							/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
-		str r4, [r2]						/* Enable MPU. */
-		dsb									/* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-
-	#if ( configENABLE_MPU == 1 )
-		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		msr control, r3						/* Restore the CONTROL register value for the task. */
-		mov lr, r4							/* LR = r4. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r4}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r4}
-		mov lr, r4							/* LR = r4. */
-		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-	#else /* configENABLE_MPU */
-		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		mov lr, r3							/* LR = r3. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r3}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r3}
-		mov lr, r3							/* LR = r3. */
-		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-	#endif /* configENABLE_MPU */
-
-	restore_ns_context:
-		adds r1, r1, #16					/* Move to the high registers. */
-		ldmia r1!, {r4-r7}					/* Restore the high registers that are not automatically restored. */
-		mov r8, r4							/* r8 = r4. */
-		mov r9, r5							/* r9 = r5. */
-		mov r10, r6							/* r10 = r6. */
-		mov r11, r7							/* r11 = r7. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		subs r1, r1, #32					/* Go back to the low registers. */
-		ldmia r1!, {r4-r7}					/* Restore the low registers that are not automatically restored. */
-		bx lr
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	movs r0, #4
-	mov r1, lr
-	tst r0, r1
-	beq stacking_used_msp
-	mrs r0, psp
-	b vPortSVCHandler_C
-	stacking_used_msp:
-		mrs r0, msp
-		b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-vPortFreeSecureContext:
-	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
-	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
-	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
-	beq free_secure_context
-	bx lr									/* There is no secure context (xSecureContext is NULL). */
-	free_secure_context:
-		svc 1								/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
-		bx lr								/* Return. */
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
deleted file mode 100755
index 48b0e0b..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M23"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
deleted file mode 100755
index 3121df6..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portasm.s
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	EXTERN pxCurrentTCB
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMaskFromISR
-	PUBLIC vClearInterruptMaskFromISR
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-
-#if ( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	movs r1, #1								/* r1 = 1. */
-	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
-	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-	running_privileged:
-		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-		bx lr								/* Return. */
-
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	movs r1, #1								/* r1 = 1. */
-	orrs r0, r1								/* r0 = r0 | r1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r1, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
-	movs r4, #1								/* r4 = 1. */
-	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
-	str r3, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
-	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str  r4, [r2]							/* Program MAIR0. */
-	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	movs r4, #4								/* r4 = 4. */
-	str  r4, [r2]							/* Program RNR = 4. */
-	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
-	movs r4, #5								/* r4 = 5. */
-	str  r4, [r2]							/* Program RNR = 5. */
-	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
-	movs r4, #6								/* r4 = 6. */
-	str  r4, [r2]							/* Program RNR = 6. */
-	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
-	movs r4, #7								/* r4 = 7. */
-	str  r4, [r2]							/* Program RNR = 7. */
-	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
-	movs r4, #1								/* r4 = 1. */
-	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
-	str r3, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	msr  control, r2						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r2									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs  r0, control						/* Read the CONTROL register. */
-	movs r1, #1								/* r1 = 1. */
-	bics r0, r1								/* Clear the bit 0. */
-	msr  control, r0						/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-	nop
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMaskFromISR:
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-/*-----------------------------------------------------------*/
-
-vClearInterruptMaskFromISR:
-	msr PRIMASK, r0
-	bx lr
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	mrs r0, psp								/* Read PSP in r0. */
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-#if ( configENABLE_MPU == 1 )
-	subs r0, r0, #44						/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	str r0, [r1]							/* Save the new top of stack in TCB. */
-	mrs r1, psplim							/* r1 = PSPLIM. */
-	mrs r2, control							/* r2 = CONTROL. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r0!, {r1-r7}						/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
-	mov r4, r8								/* r4 = r8. */
-	mov r5, r9								/* r5 = r9. */
-	mov r6, r10								/* r6 = r10. */
-	mov r7, r11								/* r7 = r11. */
-	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
-#else /* configENABLE_MPU */
-	subs r0, r0, #40						/* Make space for PSPLIM, LR and the remaining registers on the stack. */
-	str r0, [r1]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r0!, {r2-r7}						/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
-	mov r4, r8								/* r4 = r8. */
-	mov r5, r9								/* r5 = r9. */
-	mov r6, r10								/* r6 = r10. */
-	mov r7, r11								/* r7 = r11. */
-	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
-#endif /* configENABLE_MPU */
-
-	cpsid i
-	bl vTaskSwitchContext
-	cpsie i
-
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
-	movs r4, #1								/* r4 = 1. */
-	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
-	str r3, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
-	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str  r4, [r2]							/* Program MAIR0. */
-	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	movs r4, #4								/* r4 = 4. */
-	str  r4, [r2]							/* Program RNR = 4. */
-	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
-	movs r4, #5								/* r4 = 5. */
-	str  r4, [r2]							/* Program RNR = 5. */
-	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
-	movs r4, #6								/* r4 = 6. */
-	str  r4, [r2]							/* Program RNR = 6. */
-	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
-	movs r4, #7								/* r4 = 7. */
-	str  r4, [r2]							/* Program RNR = 7. */
-	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
-	movs r4, #1								/* r4 = 1. */
-	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
-	str r3, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	adds r0, r0, #28						/* Move to the high registers. */
-	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
-	mov r8, r4								/* r8 = r4. */
-	mov r9, r5								/* r9 = r5. */
-	mov r10, r6								/* r10 = r6. */
-	mov r11, r7								/* r11 = r7. */
-	msr psp, r0								/* Remember the new top of stack for the task. */
-	subs r0, r0, #44						/* Move to the starting of the saved context. */
-	ldmia r0!, {r1-r7}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
-	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
-	msr control, r2							/* Restore the CONTROL register value for the task. */
-	bx r3
-#else /* configENABLE_MPU */
-	adds r0, r0, #24						/* Move to the high registers. */
-	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
-	mov r8, r4								/* r8 = r4. */
-	mov r9, r5								/* r9 = r5. */
-	mov r10, r6								/* r10 = r6. */
-	mov r11, r7								/* r11 = r7. */
-	msr psp, r0								/* Remember the new top of stack for the task. */
-	subs r0, r0, #40						/* Move to the starting of the saved context. */
-	ldmia r0!, {r2-r7}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
-	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
-	bx r3
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	movs r0, #4
-	mov r1, lr
-	tst r0, r1
-	beq stacking_used_msp
-	mrs r0, psp
-	b vPortSVCHandler_C
-	stacking_used_msp:
-		mrs r0, msp
-		b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
deleted file mode 100755
index 48b0e0b..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM23_NTZ/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M23"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
deleted file mode 100755
index e38104c..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portasm.s
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	EXTERN pxCurrentTCB
-	EXTERN xSecureContext
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-	EXTERN SecureContext_SaveContext
-	EXTERN SecureContext_LoadContext
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vPortAllocateSecureContext
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMaskFromISR
-	PUBLIC vClearInterruptMaskFromISR
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-	PUBLIC vPortFreeSecureContext
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	ite ne
-	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	orr r0, r0, #1							/* r0 = r0 | 1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vPortAllocateSecureContext:
-	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r3, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
-	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str  r4, [r2]							/* Program MAIR0. */
-	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r4, #4								/* r4 = 4. */
-	str  r4, [r2]							/* Program RNR = 4. */
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	ldr  r2, =0xe000ed9c					/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r3!, {r4-r11}						/* Read 4 set of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	ldr  r5, =xSecureContext
-	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	msr  control, r3						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r4									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	ldr  r4, =xSecureContext
-	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs  r0, control						/* Read the CONTROL register. */
-	bic r0, r0, #1							/* Clear the bit 0. */
-	msr  control, r0						/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	cpsie f
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMaskFromISR:
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-/*-----------------------------------------------------------*/
-
-vClearInterruptMaskFromISR:
-	msr PRIMASK, r0
-	bx lr
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	mrs r1, psp								/* Read PSP in r1. */
-	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-
-	cbz r0, save_ns_context					/* No secure context to save. */
-	push {r0-r2, r14}
-	bl SecureContext_SaveContext
-	pop {r0-r3}								/* LR is now in r3. */
-	mov lr, r3								/* LR = r3. */
-	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r2, [r3]							/* Read pxCurrentTCB. */
-#if ( configENABLE_MPU == 1 )
-	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mrs r3, control							/* r3 = CONTROL. */
-	mov r4, lr								/* r4 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-#else /* configENABLE_MPU */
-	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
-#endif /* configENABLE_MPU */
-	b select_next_task
-
-	save_ns_context:
-		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r2, [r3]						/* Read pxCurrentTCB. */
-	#if ( configENABLE_FPU == 1 )
-		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-		it eq
-		vstmdbeq r1!, {s16-s31}				/* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if ( configENABLE_MPU == 1 )
-		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #16					/* r1 = r1 + 16. */
-		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
-		mrs r3, control						/* r3 = CONTROL. */
-		mov r4, lr							/* r4 = LR/EXC_RETURN. */
-		subs r1, r1, #16					/* r1 = r1 - 16. */
-		stm r1, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #12					/* r1 = r1 + 12. */
-		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
-		mov r3, lr							/* r3 = LR/EXC_RETURN. */
-		subs r1, r1, #12					/* r1 = r1 - 12. */
-		stmia r1!, {r0, r2-r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-
-	select_next_task:
-		cpsid i
-		bl vTaskSwitchContext
-		cpsie i
-
-		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r3, [r2]						/* Read pxCurrentTCB. */
-		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-
-	#if ( configENABLE_MPU == 1 )
-		dmb									/* Complete outstanding transfers before disabling MPU. */
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
-		bic r4, r4, #1						/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-		str r4, [r2]						/* Disable MPU. */
-
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
-		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-		str r4, [r2]						/* Program MAIR0. */
-		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-		movs r4, #4							/* r4 = 4. */
-		str r4, [r2]						/* Program RNR = 4. */
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-		ldr  r2, =0xe000ed9c				/* r2 = 0xe000ed9c [Location of RBAR]. */
-		ldmia r3!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
-		stmia r2!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
-		orr r4, r4, #1						/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-		str r4, [r2]						/* Enable MPU. */
-		dsb									/* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-
-	#if ( configENABLE_MPU == 1 )
-		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		msr control, r3						/* Restore the CONTROL register value for the task. */
-		mov lr, r4							/* LR = r4. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r4}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r4}
-		mov lr, r4							/* LR = r4. */
-		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-	#else /* configENABLE_MPU */
-		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		mov lr, r3							/* LR = r3. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r3}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r3}
-		mov lr, r3							/* LR = r3. */
-		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-	#endif /* configENABLE_MPU */
-
-	restore_ns_context:
-		ldmia r1!, {r4-r11}					/* Restore the registers that are not automatically restored. */
-	#if ( configENABLE_FPU == 1 )
-		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-		it eq
-		vldmiaeq r1!, {s16-s31}				/* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	tst lr, #4
-	ite eq
-	mrseq r0, msp
-	mrsne r0, psp
-	b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-vPortFreeSecureContext:
-	/* r0 = uint32_t *pulTCB. */
-	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
-	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
-	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
-	it ne
-	svcne 1									/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
deleted file mode 100755
index aba3daf..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
deleted file mode 100755
index 400755b..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portasm.s
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	EXTERN pxCurrentTCB
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMaskFromISR
-	PUBLIC vClearInterruptMaskFromISR
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	ite ne
-	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	orr r0, r0, #1							/* r0 = r0 | 1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r1, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
-	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str r3, [r2]							/* Program MAIR0. */
-	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r3, #4								/* r3 = 4. */
-	str r3, [r2]							/* Program RNR = 4. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	msr  control, r2						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r2									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs  r0, control						/* Read the CONTROL register. */
-	bic r0, r0, #1							/* Clear the bit 0. */
-	msr  control, r0						/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	cpsie f
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMaskFromISR:
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-/*-----------------------------------------------------------*/
-
-vClearInterruptMaskFromISR:
-	msr PRIMASK, r0
-	bx lr
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	mrs r0, psp								/* Read PSP in r0. */
-#if ( configENABLE_FPU == 1 )
-	tst lr, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	it eq
-	vstmdbeq r0!, {s16-s31}					/* Store the FPU registers which are not saved automatically. */
-#endif /* configENABLE_FPU */
-#if ( configENABLE_MPU == 1 )
-	mrs r1, psplim							/* r1 = PSPLIM. */
-	mrs r2, control							/* r2 = CONTROL. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmdb r0!, {r1-r11}						/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
-#else /* configENABLE_MPU */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmdb r0!, {r2-r11}						/* Store on the stack - PSPLIM, LR and registers that are not automatically. */
-#endif /* configENABLE_MPU */
-
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-	str r0, [r1]							/* Save the new top of stack in TCB. */
-
-	cpsid i
-	bl vTaskSwitchContext
-	cpsie i
-
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
-	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str r3, [r2]							/* Program MAIR0. */
-	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r3, #4								/* r3 = 4. */
-	str r3, [r2]							/* Program RNR = 4. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldmia r0!, {r1-r11}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
-#else /* configENABLE_MPU */
-	ldmia r0!, {r2-r11}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_FPU == 1 )
-	tst r3, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	it eq
-	vldmiaeq r0!, {s16-s31}					/* Restore the FPU registers which are not restored automatically. */
-#endif /* configENABLE_FPU */
-
- #if ( configENABLE_MPU == 1 )
-	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
-	msr control, r2							/* Restore the CONTROL register value for the task. */
-#else /* configENABLE_MPU */
-	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
-#endif /* configENABLE_MPU */
-	msr psp, r0								/* Remember the new top of stack for the task. */
-	bx r3
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	tst lr, #4
-	ite eq
-	mrseq r0, msp
-	mrsne r0, psp
-	b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h b/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
deleted file mode 100755
index aba3daf..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portable/IAR/ARM_CM33_NTZ/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portasm.h b/FreeRTOS/Source/portable/ARMv8M/non_secure/portasm.h
deleted file mode 100755
index 2ecf04e..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOS/Source/portable/ARMv8M/non_secure/portmacro.h b/FreeRTOS/Source/portable/ARMv8M/non_secure/portmacro.h
deleted file mode 100755
index 2d02a1f..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/non_secure/portmacro.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.0
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize );
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portPRIVILEGED_RAM_REGION							( 2UL )
-#define portUNPRIVILEGED_DEVICE_REGION						( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Devices Region. */
-#define portDEVICE_REGION_START_ADDRESS						( 0x50000000 )
-#define portDEVICE_REGION_END_ADDRESS						( 0x5FFFFFFF )
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/ReadMe.txt b/FreeRTOS/Source/portable/ARMv8M/secure/ReadMe.txt
deleted file mode 100755
index 9b12e54..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/ReadMe.txt
+++ /dev/null
@@ -1,10 +0,0 @@
-This directory tree contains the master copy of the FreeeRTOS Cortex-M33 port.
-Do not use the files located here!  These file are copied into separate
-FreeRTOS/Source/portable/[compiler]/ARM_CM33_NNN directories prior to each
-FreeRTOS release.
-
-If your Cortex-M33 application uses TrustZone then use the files from the
-FreeRTOS/Source/portable/[compiler]/ARM_CM33 directories.
-
-If your Cortex-M33 application does not use TrustZone then use the files from
-the FreeRTOS/Source/portable/[compiler]/ARM_CM33_NTZ directories.
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c b/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c
deleted file mode 100755
index e703498..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM23/secure_context_port.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-#if( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	"	msr control, r3							\n" /* CONTROL = r3. */
-	#endif /* configENABLE_MPU */
-	"	msr psplim, r2							\n" /* PSPLIM = r2. */
-	"	msr psp, r1								\n" /* PSP = r1. */
-	"											\n"
-	" load_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:::"r0", "r1", "r2"
-	);
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	mrs r1, psp								\n" /* r1 = PSP. */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r2, control							\n" /* r2 = CONTROL. */
-	"	subs r1, r1, #4							\n" /* Make space for the CONTROL value on the stack. */
-	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	"	stmia r1!, {r2}							\n" /* Store CONTROL value on the stack. */
-	#else /* configENABLE_MPU */
-	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	#endif /* configENABLE_MPU */
-	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
-	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
-	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-	"											\n"
-	" save_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c b/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
deleted file mode 100755
index 7c556f5..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/GCC/ARM_CM33/secure_context_port.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	"	msr control, r3							\n" /* CONTROL = r3. */
-	#endif /* configENABLE_MPU */
-	"	msr psplim, r2							\n" /* PSPLIM = r2. */
-	"	msr psp, r1								\n" /* PSP = r1. */
-	"											\n"
-	" load_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:::"r0", "r1", "r2"
-	);
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	mrs r1, psp								\n" /* r1 = PSP. */
-	#if( configENABLE_FPU == 1 )
-	"	vstmdb r1!, {s0}						\n" /* Trigger the defferred stacking of FPU registers. */
-	"	vldmia r1!, {s0}						\n" /* Nullify the effect of the pervious statement. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r2, control							\n" /* r2 = CONTROL. */
-	"	stmdb r1!, {r2}							\n" /* Store CONTROL value on the stack. */
-	#endif /* configENABLE_MPU */
-	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
-	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
-	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-	"											\n"
-	" save_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port.c b/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port.c
deleted file mode 100755
index 619db1e..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/* Functions implemented in assembler file. */
-extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
-extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
-{
-	SecureContext_LoadContextAsm( xSecureContextHandle );
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
-{
-	SecureContext_SaveContextAsm( xSecureContextHandle );
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s b/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s
deleted file mode 100755
index 65cee0c..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM23/secure_context_port_asm.s
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-
-	PUBLIC SecureContext_LoadContextAsm
-	PUBLIC SecureContext_SaveContextAsm
-
-#if ( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-/*-----------------------------------------------------------*/
-
-SecureContext_LoadContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-#if ( configENABLE_MPU == 1 )
-	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	msr control, r3							/* CONTROL = r3. */
-#endif /* configENABLE_MPU */
-	msr psplim, r2							/* PSPLIM = r2. */
-	msr psp, r1								/* PSP = r1. */
-
-	load_ctx_therad_mode:
-		bx lr
-/*-----------------------------------------------------------*/
-
-SecureContext_SaveContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	mrs r1, psp								/* r1 = PSP. */
-#if ( configENABLE_MPU == 1 )
-	mrs r2, control							/* r2 = CONTROL. */
-	subs r1, r1, #4							/* Make space for the CONTROL value on the stack. */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	stmia r1!, {r2}							/* Store CONTROL value on the stack. */
-#else /* configENABLE_MPU */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-#endif /* configENABLE_MPU */
-	movs r1, #0								/* r1 = securecontextNO_STACK. */
-	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
-	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-
-	save_ctx_therad_mode:
-		bx lr
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c b/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c
deleted file mode 100755
index 619db1e..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/* Functions implemented in assembler file. */
-extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
-extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
-{
-	SecureContext_LoadContextAsm( xSecureContextHandle );
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
-{
-	SecureContext_SaveContextAsm( xSecureContextHandle );
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s b/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
deleted file mode 100755
index 0cbfe6e..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/context/portable/IAR/ARM_CM33/secure_context_port_asm.s
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-
-	PUBLIC SecureContext_LoadContextAsm
-	PUBLIC SecureContext_SaveContextAsm
-/*-----------------------------------------------------------*/
-
-SecureContext_LoadContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-#if ( configENABLE_MPU == 1 )
-	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	msr control, r3							/* CONTROL = r3. */
-#endif /* configENABLE_MPU */
-	msr psplim, r2							/* PSPLIM = r2. */
-	msr psp, r1								/* PSP = r1. */
-
-	load_ctx_therad_mode:
-		bx lr
-/*-----------------------------------------------------------*/
-
-SecureContext_SaveContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	mrs r1, psp								/* r1 = PSP. */
-#if ( configENABLE_FPU == 1 )
-	vstmdb r1!, {s0}						/* Trigger the defferred stacking of FPU registers. */
-	vldmia r1!, {s0}						/* Nullify the effect of the pervious statement. */
-#endif /* configENABLE_FPU */
-#if ( configENABLE_MPU == 1 )
-	mrs r2, control							/* r2 = CONTROL. */
-	stmdb r1!, {r2}							/* Store CONTROL value on the stack. */
-#endif /* configENABLE_MPU */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	movs r1, #0								/* r1 = securecontextNO_STACK. */
-	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
-	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-
-	save_ctx_therad_mode:
-		bx lr
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.c b/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.c
deleted file mode 100755
index 53535cd..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief CONTROL value for privileged tasks.
- *
- * Bit[0] - 0 --> Thread mode is privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
-
-/**
- * @brief CONTROL value for un-privileged tasks.
- *
- * Bit[0] - 1 --> Thread mode is un-privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Structure to represent secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first addess of the allocated memory.
- */
-typedef struct SecureContext
-{
-	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
-	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
-	uint8_t *pucStackStart;				/**< First location of the stack memory. */
-} SecureContext_t;
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* No stack for thread mode until a task's context is loaded. */
-		secureportSET_PSPLIM( securecontextNO_STACK );
-		secureportSET_PSP( securecontextNO_STACK );
-
-		#if( configENABLE_MPU == 1 )
-		{
-			/* Configure thread mode to use PSP and to be unprivileged. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-		}
-		#else /* configENABLE_MPU */
-		{
-			/* Configure thread mode to use PSP and to be privileged.. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-		}
-		#endif /* configENABLE_MPU */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
-#else /* configENABLE_MPU */
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
-#endif /* configENABLE_MPU */
-{
-	uint8_t *pucStackMemory = NULL;
-	uint32_t ulIPSR;
-	SecureContextHandle_t xSecureContextHandle = NULL;
-	#if( configENABLE_MPU == 1 )
-		uint32_t *pulCurrentStackPointer = NULL;
-	#endif /* configENABLE_MPU */
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Allocate the context structure. */
-		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
-
-		if( xSecureContextHandle != NULL )
-		{
-			/* Allocate the stack space. */
-			pucStackMemory = pvPortMalloc( ulSecureStackSize );
-
-			if( pucStackMemory != NULL )
-			{
-				/* Since stack grows down, the starting point will be the last
-				 * location. Note that this location is next to the last
-				 * allocated byte because the hardware decrements the stack
-				 * pointer before writing i.e. if stack pointer is 0x2, a push
-				 * operation will decrement the stack pointer to 0x1 and then
-				 * write at 0x1. */
-				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
-
-				/* The stack cannot go beyond this location. This value is
-				 * programmed in the PSPLIM register on context switch.*/
-				xSecureContextHandle->pucStackLimit = pucStackMemory;
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Store the correct CONTROL value for the task on the stack.
-					 * This value is programmed in the CONTROL register on
-					 * context switch. */
-					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
-					pulCurrentStackPointer--;
-					if( ulIsTaskPrivileged )
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-					}
-					else
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-					}
-
-					/* Store the current stack pointer. This value is programmed in
-					 * the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
-				}
-				#else /* configENABLE_MPU */
-				{
-					/* Current SP is set to the starting of the stack. This
-					 * value programmed in the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
-
-				}
-				#endif /* configENABLE_MPU */
-			}
-			else
-			{
-				/* Free the context to avoid memory leak and make sure to return
-				 * NULL to indicate failure. */
-				vPortFree( xSecureContextHandle );
-				xSecureContextHandle = NULL;
-			}
-		}
-	}
-
-	return xSecureContextHandle;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Ensure that valid parameters are passed. */
-		secureportASSERT( xSecureContextHandle != NULL );
-
-		/* Free the stack space. */
-		vPortFree( xSecureContextHandle->pucStackLimit );
-
-		/* Free the context itself. */
-		vPortFree( xSecureContextHandle );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.h b/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.h
deleted file mode 100755
index e148bff..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/context/secure_context.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_CONTEXT_H__
-#define __SECURE_CONTEXT_H__
-
-/* Standard includes. */
-#include 
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/**
- * @brief PSP value when no task's context is loaded.
- */
-#define securecontextNO_STACK	0x0
-
-/**
- * @brief Opaque handle.
- */
-struct SecureContext;
-typedef struct SecureContext*	SecureContextHandle_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Initializes the secure context management system.
- *
- * PSP is set to NULL and therefore a task must allocate and load a context
- * before calling any secure side function in the thread mode.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureContext_Init( void );
-
-/**
- * @brief Allocates a context on the secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
- * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
- *
- * @return Opaque context handle if context is successfully allocated, NULL
- * otherwise.
- */
-#if( configENABLE_MPU == 1 )
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
-#else /* configENABLE_MPU */
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
-#endif /* configENABLE_MPU */
-
-/**
- * @brief Frees the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the
- * context to be freed.
- */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Loads the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be loaded.
- */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Saves the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be saved.
- */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
-
-#endif /* __SECURE_CONTEXT_H__ */
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.c b/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.c
deleted file mode 100755
index 60fce5c..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure context heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Total heap size.
- */
-#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
-
-/* No test marker by default. */
-#ifndef mtCOVERAGE_TEST_MARKER
-	#define mtCOVERAGE_TEST_MARKER()
-#endif
-
-/* No tracing by default. */
-#ifndef traceMALLOC
-	#define traceMALLOC( pvReturn, xWantedSize )
-#endif
-
-/* No tracing by default. */
-#ifndef traceFREE
-	#define traceFREE( pv, xBlockSize )
-#endif
-
-/* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
-/*-----------------------------------------------------------*/
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	 * heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#else /* configAPPLICATION_ALLOCATED_HEAP */
-	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/**
- * @brief The linked list structure.
- *
- * This is used to link free blocks in order of their memory address.
- */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
-	size_t xBlockSize;						/**< The size of the free block. */
-} BlockLink_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Called automatically to setup the required heap structures the first
- * time pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/**
- * @brief Inserts a block of memory that is being freed into the correct
- * position in the list of free memory blocks.
- *
- * The block being freed will be merged with the block in front it and/or the
- * block behind it if the memory blocks are adjacent to each other.
- *
- * @param[in] pxBlockToInsert The block being freed.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The size of the structure placed at the beginning of each allocated
- * memory block must by correctly byte aligned.
- */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-
-/**
- * @brief Create a couple of list links to mark the start and end of the list.
- */
-static BlockLink_t xStart, *pxEnd = NULL;
-
-/**
- * @brief Keeps track of the number of free bytes remaining, but says nothing
- * about fragmentation.
- */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-size_t uxAddress;
-size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
-
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	uxAddress = ( size_t ) ucHeap;
-
-	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
-	{
-		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
-		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-	}
-
-	pucAlignedHeap = ( uint8_t * ) uxAddress;
-
-	/* xStart is used to hold a pointer to the first item in the list of free
-	 * blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
-
-	/* pxEnd is used to mark the end of the list of free blocks and is inserted
-	 * at the end of the heap space. */
-	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-	uxAddress -= xHeapStructSize;
-	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-	pxEnd = ( void * ) uxAddress;
-	pxEnd->xBlockSize = 0;
-	pxEnd->pxNextFreeBlock = NULL;
-
-	/* To start with there is a single free block that is sized to take up the
-	 * entire heap space, minus the space taken by pxEnd. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
-	/* Only one block exists - and it covers the entire usable heap space. */
-	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
-{
-BlockLink_t *pxIterator;
-uint8_t *puc;
-
-	/* Iterate through the list until a block is found that has a higher address
-	 * than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
-
-	/* Do the block being inserted, and the block it is being inserted after
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Do the block being inserted, and the block it is being inserted before
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
-
-	/* If the block being inserted plugged a gab, so was merged with the block
-	 * before and the block after, then it's pxNextFreeBlock pointer will have
-	 * already been set, and should not be set here as that would make it point
-	 * to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
-
-	/* If this is the first call to malloc then the heap will require
-	 * initialisation to setup the list of free blocks. */
-	if( pxEnd == NULL )
-	{
-		prvHeapInit();
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Check the requested block size is not so large that the top bit is set.
-	 * The top bit of the block size member of the BlockLink_t structure is used
-	 * to determine who owns the block - the application or the kernel, so it
-	 * must be free. */
-	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-	{
-		/* The wanted size is increased so it can contain a BlockLink_t
-		 * structure in addition to the requested amount of bytes. */
-		if( xWantedSize > 0 )
-		{
-			xWantedSize += xHeapStructSize;
-
-			/* Ensure that blocks are always aligned to the required number of
-			 * bytes. */
-			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
-			{
-				/* Byte alignment required. */
-				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-		{
-			/* Traverse the list from the start (lowest address) block until
-			 * one of adequate size is found. */
-			pxPreviousBlock = &xStart;
-			pxBlock = xStart.pxNextFreeBlock;
-			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-			{
-				pxPreviousBlock = pxBlock;
-				pxBlock = pxBlock->pxNextFreeBlock;
-			}
-
-			/* If the end marker was reached then a block of adequate size was
-			 * not found. */
-			if( pxBlock != pxEnd )
-			{
-				/* Return the memory space pointed to - jumping over the
-				 * BlockLink_t structure at its start. */
-				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-				/* This block is being returned for use so must be taken out
-				 * of the list of free blocks. */
-				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-				/* If the block is larger than required it can be split into
-				 * two. */
-				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
-				{
-					/* This block is to be split into two.  Create a new
-					 * block following the number of bytes requested. The void
-					 * cast is used to prevent byte alignment warnings from the
-					 * compiler. */
-					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-
-					/* Calculate the sizes of two blocks split from the single
-					 * block. */
-					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-					pxBlock->xBlockSize = xWantedSize;
-
-					/* Insert the new block into the list of free blocks. */
-					prvInsertBlockIntoFreeList( pxNewBlockLink );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-				{
-					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* The block is being returned - it is allocated and owned by
-				 * the application and has no "next" block. */
-				pxBlock->xBlockSize |= xBlockAllocatedBit;
-				pxBlock->pxNextFreeBlock = NULL;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	traceMALLOC( pvReturn, xWantedSize );
-
-	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
-
-	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		 * before it. */
-		puc -= xHeapStructSize;
-
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
-
-		/* Check the block is actually allocated. */
-		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
-
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				 * allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-				secureportDISABLE_NON_SECURE_INTERRUPTS();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				secureportENABLE_NON_SECURE_INTERRUPTS();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.h b/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.h
deleted file mode 100755
index 69e4f2a..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/heap/secure_heap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_HEAP_H__
-#define __SECURE_HEAP_H__
-
-/* Standard includes. */
-#include 
-
-/**
- * @brief Allocates memory from heap.
- *
- * @param[in] xWantedSize The size of the memory to be allocated.
- *
- * @return Pointer to the memory region if the allocation is successful, NULL
- * otherwise.
- */
-void *pvPortMalloc( size_t xWantedSize );
-
-/**
- * @brief Frees the previously allocated memory.
- *
- * @param[in] pv Pointer to the memory to be freed.
- */
-void vPortFree( void *pv );
-
-#endif /* __SECURE_HEAP_H__ */
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c b/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c
deleted file mode 100755
index c6525f7..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure init includes. */
-#include "secure_init.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS			( 29UL )
-#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS				( 26UL )
-#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
-
-#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS			( 10UL )
-#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS			( 11UL )
-#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
-									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
-									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
-		 * permitted. CP11 should be programmed to the same value as CP10. */
-		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
-
-		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
-		 * that we can enable/disable lazy stacking in port.c file. */
-		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
-
-		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
-		 * registers (S16-S31) are also pushed to stack on exception entry and
-		 * restored on exception return. */
-		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.h b/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.h
deleted file mode 100755
index 6c5bc71..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/init/secure_init.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_INIT_H__
-#define __SECURE_INIT_H__
-
-/**
- * @brief De-prioritizes the non-secure exceptions.
- *
- * This is needed to ensure that the non-secure PendSV runs at the lowest
- * priority. Context switch is done in the non-secure PendSV handler.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_DePrioritizeNSExceptions( void );
-
-/**
- * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
- *
- * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
- * Registers are not leaked to the non-secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_EnableNSFPUAccess( void );
-
-#endif /* __SECURE_INIT_H__ */
diff --git a/FreeRTOS/Source/portable/ARMv8M/secure/macros/secure_port_macros.h b/FreeRTOS/Source/portable/ARMv8M/secure/macros/secure_port_macros.h
deleted file mode 100755
index 760edab..0000000
--- a/FreeRTOS/Source/portable/ARMv8M/secure/macros/secure_port_macros.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_PORT_MACROS_H__
-#define __SECURE_PORT_MACROS_H__
-
-/**
- * @brief Byte alignment requirements.
- */
-#define secureportBYTE_ALIGNMENT					8
-#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
-
-/**
- * @brief Macro to declare a function as non-secure callable.
- */
-#if defined( __IAR_SYSTEMS_ICC__ )
-	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
-#else
-	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
-#endif
-
-/**
- * @brief Set the secure PRIMASK value.
- */
-#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Set the non-secure PRIMASK value.
- */
-#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Read the PSP value in the given variable.
- */
-#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
-	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
-
-/**
- * @brief Set the PSP to the given value.
- */
-#define secureportSET_PSP( pucCurrentStackPointer ) \
-	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
-
-/**
- * @brief Set the PSPLIM to the given value.
- */
-#define secureportSET_PSPLIM( pucStackLimit ) \
-	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
-
-/**
- * @brief Set the NonSecure MSP to the given value.
- */
-#define secureportSET_MSP_NS( pucMainStackPointer ) \
-	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
-
-/**
- * @brief Set the CONTROL register to the given value.
- */
-#define secureportSET_CONTROL( ulControl ) \
-	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
-
-/**
- * @brief Read the Interrupt Program Status Register (IPSR) value in the given
- * variable.
- */
-#define secureportREAD_IPSR( ulIPSR ) \
-	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
-
-/**
- * @brief PRIMASK value to enable interrupts.
- */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
-
-/**
- * @brief PRIMASK value to disable interrupts.
- */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
-
-/**
- * @brief Disable secure interrupts.
- */
-#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Disable non-secure interrupts.
- *
- * This effectively disables context switches.
- */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Enable non-secure interrupts.
- */
-#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Assert definition.
- */
-#define secureportASSERT( x )						\
-	if( ( x ) == 0 )								\
-	{												\
-		secureportDISABLE_SECURE_INTERRUPTS();		\
-		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
-		for( ;; );									\
-	}
-
-#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/port.c b/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/port.c
deleted file mode 100755
index 9d43e12..0000000
--- a/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/port.c
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-Changes from V1.00:
-
-	+ Call to taskYIELD() from within tick ISR has been replaced by the more
-	  efficient portSWITCH_CONTEXT().
-	+ ISR function definitions renamed to include the prv prefix.
-
-Changes from V2.6.1
-
-	+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
-	  macro to be consistent with the later ports.
-*/
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Flashlite 186
- * port.
- *----------------------------------------------------------*/
-
-#include 
-#include 
-#include 
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "portasm.h"
-
-/*lint -e950 Non ANSI reserved words okay in this file only. */
-
-#define portTIMER_EOI_TYPE		( 8 )
-#define portRESET_PIC()			portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
-#define portTIMER_INT_NUMBER	0x12
-
-#define portTIMER_1_CONTROL_REGISTER	( ( uint16_t ) 0xff5e )
-#define portTIMER_0_CONTROL_REGISTER	( ( uint16_t ) 0xff56 )
-#define portTIMER_INTERRUPT_ENABLE		( ( uint16_t ) 0x2000 )
-
-/* Setup the hardware to generate the required tick frequency. */
-static void prvSetTickFrequency( uint32_t ulTickRateHz );
-
-/* Set the hardware back to the state as per before the scheduler started. */
-static void prvExitFunction( void );
-
-/* The ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if( configUSE_PREEMPTION == 1 )
-	/* Tick service routine used by the scheduler when preemptive scheduling is
-	being used. */
-	static void __interrupt __far prvPreemptiveTick( void );
-#else
-	/* Tick service routine used by the scheduler when cooperative scheduling is
-	being used. */
-	static void __interrupt __far prvNonPreemptiveTick( void );
-#endif
-
-/* Trap routine used by taskYIELD() to manually cause a context switch. */
-static void __interrupt __far prvYieldProcessor( void );
-
-/*lint -e956 File scopes necessary here. */
-
-/* Set true when the vectors are set so the scheduler will service the tick. */
-static BaseType_t xSchedulerRunning = pdFALSE;
-
-/* Points to the original routine installed on the vector we use for manual
-context switches.  This is then used to restore the original routine during
-prvExitFunction(). */
-static void ( __interrupt __far *pxOldSwitchISR )();
-
-/* Used to restore the original DOS context when the scheduler is ended. */
-static jmp_buf xJumpBuf;
-
-/*lint +e956 */
-
-/*-----------------------------------------------------------*/
-BaseType_t xPortStartScheduler( void )
-{
-	/* This is called with interrupts already disabled. */
-
-	/* Remember what was on the interrupts we are going to use
-	so we can put them back later if required. */
-	pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
-
-	/* Put our manual switch (yield) function on a known
-	vector. */
-	_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
-
-	#if( configUSE_PREEMPTION == 1 )
-	{
-		/* Put our tick switch function on the timer interrupt. */
-		_dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
-	}
-	#else
-	{
-		/* We want the timer interrupt to just increment the tick count. */
-		_dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
-	}
-	#endif
-
-	prvSetTickFrequency( configTICK_RATE_HZ );
-
-	/* Clean up function if we want to return to DOS. */
-	if( setjmp( xJumpBuf ) != 0 )
-	{
-		prvExitFunction();
-		xSchedulerRunning = pdFALSE;
-	}
-	else
-	{
-		xSchedulerRunning = pdTRUE;
-
-		/* Kick off the scheduler by setting up the context of the first task. */
-		portFIRST_CONTEXT();
-	}
-
-	return xSchedulerRunning;
-}
-/*-----------------------------------------------------------*/
-
-/* The ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if( configUSE_PREEMPTION == 1 )
-	static void __interrupt __far prvPreemptiveTick( void )
-	{
-		/* Get the scheduler to update the task states following the tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Switch in the context of the next task to be run. */
-			portSWITCH_CONTEXT();
-		}
-
-		/* Reset the PIC ready for the next time. */
-		portRESET_PIC();
-	}
-#else
-	static void __interrupt __far prvNonPreemptiveTick( void )
-	{
-		/* Same as preemptive tick, but the cooperative scheduler is being used
-		so we don't have to switch in the context of the next task. */
-		xTaskIncrementTick();
-		portRESET_PIC();
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-static void __interrupt __far prvYieldProcessor( void )
-{
-	/* Switch in the context of the next task to be run. */
-	portSWITCH_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Jump back to the processor state prior to starting the
-	scheduler.  This means we are not going to be using a
-	task stack frame so the task can be deleted. */
-	longjmp( xJumpBuf, 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvExitFunction( void )
-{
-const uint16_t usTimerDisable = 0x0000;
-uint16_t usTimer0Control;
-
-	/* Interrupts should be disabled here anyway - but no
-	harm in making sure. */
-	portDISABLE_INTERRUPTS();
-	if( xSchedulerRunning == pdTRUE )
-	{
-		/* Put back the switch interrupt routines that was in place
-		before the scheduler started. */
-		_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
-	}
-
-	/* Disable the timer used for the tick to ensure the scheduler is
-	not called before restoring interrupts.  There was previously nothing
-	on this timer so there is no old ISR to restore. */
-	portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
-
-	/* Restart the DOS tick. */
-	usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
-	usTimer0Control |= portTIMER_INTERRUPT_ENABLE;
-	portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
-
-
-	portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetTickFrequency( uint32_t ulTickRateHz )
-{
-const uint16_t usMaxCountRegister = 0xff5a;
-const uint16_t usTimerPriorityRegister = 0xff32;
-const uint16_t usTimerEnable = 0xC000;
-const uint16_t usRetrigger = 0x0001;
-const uint16_t usTimerHighPriority = 0x0000;
-uint16_t usTimer0Control;
-
-/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */
-
-const uint32_t ulClockFrequency = ( uint32_t ) 0x7f31a0UL;
-
-uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
-
-	portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
-	portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
-	portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority );
-
-	/* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */
-	usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
-	usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE;
-	portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
-}
-
-
-/*lint +e950 */
-
diff --git a/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h b/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h
deleted file mode 100755
index e5ad60e..0000000
--- a/FreeRTOS/Source/portable/BCC/16BitDOS/Flsh186/prtmacro.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		long
-#define portLONG		long
-#define portSHORT		int
-#define portSTACK_TYPE	uint16_t
-#define portBASE_TYPE	portSHORT
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-#define portENTER_CRITICAL()			__asm{ pushf }  \
-										__asm{ cli 	 }	\
-
-#define portEXIT_CRITICAL()				__asm{ popf }
-
-#define portDISABLE_INTERRUPTS()		__asm{ cli }
-
-#define portENABLE_INTERRUPTS()			__asm{ sti }
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portNOP()						__asm{ nop }
-#define portSTACK_GROWTH				( -1 )
-#define portSWITCH_INT_NUMBER 			0x80
-#define portYIELD()						__asm{ int portSWITCH_INT_NUMBER }
-#define portTICK_PERIOD_MS		( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT      2
-#define portINITIAL_SW		( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
-/*-----------------------------------------------------------*/
-
-/* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )				inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
-#define portINPUT_WORD( xAddr )				inpw( xAddr )
-#define portOUTPUT_WORD( xAddr, usValue )	outpw( xAddr, usValue )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/BCC/16BitDOS/PC/port.c b/FreeRTOS/Source/portable/BCC/16BitDOS/PC/port.c
deleted file mode 100755
index bab75b1..0000000
--- a/FreeRTOS/Source/portable/BCC/16BitDOS/PC/port.c
+++ /dev/null
@@ -1,288 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-Changes from V2.6.1
-
-	+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
-	  macro to be consistent with the later ports.
-
-Changes from V4.0.1
-	
-	+ Add function prvSetTickFrequencyDefault() to set the DOS tick back to
-	  its proper value when the scheduler exits. 
-*/
-
-#include 
-#include 
-#include 
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "portasm.h"
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the industrial
- * PC port.
- *----------------------------------------------------------*/
-
-/*lint -e950 Non ANSI reserved words okay in this file only. */
-
-#define portTIMER_INT_NUMBER	0x08
-
-/* Setup hardware for required tick interrupt rate. */
-static void prvSetTickFrequency( uint32_t ulTickRateHz );
-
-/* Restore hardware to as it was prior to starting the scheduler. */
-static void prvExitFunction( void );
-
-/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
-directly.  We chain to the DOS tick as close as possible to the standard DOS
-tick rate. */
-static void prvPortResetPIC( void );
-
-/* The ISR used depends on whether the preemptive or cooperative
-scheduler is being used. */
-#if( configUSE_PREEMPTION == 1 )
-	/* Tick service routine used by the scheduler when preemptive scheduling is
-	being used. */
-	static void __interrupt __far prvPreemptiveTick( void );
-#else
-	/* Tick service routine used by the scheduler when cooperative scheduling is
-	being used. */
-	static void __interrupt __far prvNonPreemptiveTick( void );
-#endif
-
-/* Trap routine used by taskYIELD() to manually cause a context switch. */
-static void __interrupt __far prvYieldProcessor( void );
-
-/* Set the tick frequency back so the floppy drive works correctly when the
-scheduler exits. */
-static void prvSetTickFrequencyDefault( void );
-
-/*lint -e956 File scopes necessary here. */
-
-/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */
-static int16_t sDOSTickCounter;
-
-/* Set true when the vectors are set so the scheduler will service the tick. */
-static BaseType_t xSchedulerRunning = pdFALSE;				
-
-/* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
-static void ( __interrupt __far *pxOldSwitchISR )();		
-
-/* Points to the original routine installed on the vector we use to chain to the DOS tick.  This is then used to restore the original routine during prvExitFunction(). */
-static void ( __interrupt __far *pxOldSwitchISRPlus1 )();	
-
-/* Used to restore the original DOS context when the scheduler is ended. */
-static jmp_buf xJumpBuf;
-
-/*lint +e956 */
-
-/*-----------------------------------------------------------*/
-BaseType_t xPortStartScheduler( void )
-{
-pxISR pxOriginalTickISR;
-	
-	/* This is called with interrupts already disabled. */
-
-	/* Remember what was on the interrupts we are going to use
-	so we can put them back later if required. */
-	pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
-	pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
-	pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
-
-	prvSetTickFrequency( configTICK_RATE_HZ );
-
-	/* Put our manual switch (yield) function on a known
-	vector. */
-	_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
-
-	/* Put the old tick on a different interrupt number so we can
-	call it when we want. */
-	_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
-
-	/* The ISR used depends on whether the preemptive or cooperative
-	scheduler is being used. */
-	#if( configUSE_PREEMPTION == 1 )
-	{
-		/* Put our tick switch function on the timer interrupt. */
-		_dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
-	}
-	#else
-	{
-		/* We want the timer interrupt to just increment the tick count. */
-		_dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
-	}
-    #endif
-
-	/* Setup a counter that is used to call the DOS interrupt as close
-	to it's original frequency as can be achieved given our chosen tick
-	frequency. */
-	sDOSTickCounter = portTICKS_PER_DOS_TICK;
-
-	/* Clean up function if we want to return to DOS. */
-	if( setjmp( xJumpBuf ) != 0 )
-	{
-		prvExitFunction();
-		xSchedulerRunning = pdFALSE;
-	}
-	else
-	{
-		xSchedulerRunning = pdTRUE;
-
-		/* Kick off the scheduler by setting up the context of the first task. */
-		portFIRST_CONTEXT();
-	}
-
-	return xSchedulerRunning;
-}
-/*-----------------------------------------------------------*/
-
-/* The ISR used depends on whether the preemptive or cooperative
-scheduler is being used. */
-#if( configUSE_PREEMPTION == 1 )
-	static void __interrupt __far prvPreemptiveTick( void )
-	{
-		/* Get the scheduler to update the task states following the tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Switch in the context of the next task to be run. */
-			portSWITCH_CONTEXT();
-		}
-
-		/* Reset the PIC ready for the next time. */
-		prvPortResetPIC();
-	}
-#else
-	static void __interrupt __far prvNonPreemptiveTick( void )
-	{
-		/* Same as preemptive tick, but the cooperative scheduler is being used
-		so we don't have to switch in the context of the next task. */
-		xTaskIncrementTick();
-		prvPortResetPIC();
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-static void __interrupt __far prvYieldProcessor( void )
-{
-	/* Switch in the context of the next task to be run. */
-	portSWITCH_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-static void prvPortResetPIC( void )
-{
-	/* We are going to call the DOS tick interrupt at as close a
-	frequency to the normal DOS tick as possible. */
-
-	/* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
-	--sDOSTickCounter;
-	if( sDOSTickCounter <= 0 )
-	{
-		sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
-		__asm{ int	portSWITCH_INT_NUMBER + 1 };		 
-	}
-	else
-	{
-		/* Reset the PIC as the DOS tick is not being called to
-		do it. */
-		__asm
-		{
-			mov	al, 20H
-			out 20H, al
-		};
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Jump back to the processor state prior to starting the
-	scheduler.  This means we are not going to be using a
-	task stack frame so the task can be deleted. */
-	longjmp( xJumpBuf, 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvExitFunction( void )
-{
-void ( __interrupt __far *pxOriginalTickISR )();
-
-	/* Interrupts should be disabled here anyway - but no 
-	harm in making sure. */
-	portDISABLE_INTERRUPTS();
-	if( xSchedulerRunning == pdTRUE )
-	{
-		/* Set the DOS tick back onto the timer ticker. */
-		pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
-		_dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR );
-		prvSetTickFrequencyDefault();
-
-		/* Put back the switch interrupt routines that was in place
-		before the scheduler started. */
-		_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
-		_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
-	}
-	/* The tick timer is back how DOS wants it.  We can re-enable
-	interrupts without the scheduler being called. */
-	portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetTickFrequency( uint32_t ulTickRateHz )
-{
-const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
-const uint16_t usPIT0 = ( uint16_t ) 0x40;
-const uint32_t ulPIT_CONST = ( uint32_t ) 1193180UL;
-const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
-uint32_t ulOutput;
-
-	/* Setup the 8245 to tick at the wanted frequency. */
-	portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
-	ulOutput = ulPIT_CONST / ulTickRateHz;
-	portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) );
-	ulOutput >>= 8;
-	portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetTickFrequencyDefault( void )
-{
-const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
-const uint16_t usPIT0 = ( uint16_t ) 0x40;
-const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
-
-	portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
-	portOUTPUT_BYTE( usPIT0,0 );
-	portOUTPUT_BYTE( usPIT0,0 );
-}
-
-
-/*lint +e950 */
-
diff --git a/FreeRTOS/Source/portable/BCC/16BitDOS/PC/prtmacro.h b/FreeRTOS/Source/portable/BCC/16BitDOS/PC/prtmacro.h
deleted file mode 100755
index 678458f..0000000
--- a/FreeRTOS/Source/portable/BCC/16BitDOS/PC/prtmacro.h
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		long
-#define portDOUBLE		long
-#define portLONG		long
-#define portSHORT		int
-#define portSTACK_TYPE	uint16_t
-#define portBASE_TYPE	portSHORT
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-#define portENTER_CRITICAL()			__asm{ pushf }  \
-										__asm{ cli 	 }	\
-
-#define portEXIT_CRITICAL()				__asm{ popf }
-
-#define portDISABLE_INTERRUPTS()		__asm{ cli }
-
-#define portENABLE_INTERRUPTS()			__asm{ sti }
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portNOP()				__asm{ nop }
-#define portSTACK_GROWTH		( -1 )
-#define portSWITCH_INT_NUMBER 	0x80
-#define portYIELD()				__asm{ int portSWITCH_INT_NUMBER }
-#define portDOS_TICK_RATE		( 18.20648 )
-#define portTICK_PERIOD_MS		( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portTICKS_PER_DOS_TICK	( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
-#define portINITIAL_SW			( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
-#define portBYTE_ALIGNMENT		( 2 )
-/*-----------------------------------------------------------*/
-
-/* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )				inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/BCC/16BitDOS/common/portasm.h b/FreeRTOS/Source/portable/BCC/16BitDOS/common/portasm.h
deleted file mode 100755
index c9251ca..0000000
--- a/FreeRTOS/Source/portable/BCC/16BitDOS/common/portasm.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORT_ASM_H
-#define PORT_ASM_H
-
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-extern void vTaskSwitchContext( void );
-
-/*
- * Saves the stack pointer for one task into its TCB, calls
- * vTaskSwitchContext() to update the TCB being used, then restores the stack
- * from the new TCB read to run the task.
- */
-void portSWITCH_CONTEXT( void );
-
-/*
- * Load the stack pointer from the TCB of the task which is going to be first
- * to execute.  Then force an IRET so the registers and IP are popped off the
- * stack.
- */
-void portFIRST_CONTEXT( void );
-
-/* There are slightly different versions depending on whether you are building
-to include debugger information.  If debugger information is used then there
-are a couple of extra bytes left of the ISR stack (presumably for use by the
-debugger).  The true stack pointer is then stored in the bp register.  We add
-2 to the stack pointer to remove the extra bytes before we restore our context. */
-
-#define portSWITCH_CONTEXT()											\
-							asm { mov	ax, seg pxCurrentTCB		}	\
-							asm { mov	ds, ax						}	\
-							asm { les	bx, pxCurrentTCB			}	/* Save the stack pointer into the TCB. */		\
-							asm { mov	es:0x2[ bx ], ss			}	\
-							asm { mov	es:[ bx ], sp				}	\
-							asm { call  far ptr vTaskSwitchContext	}	/* Perform the switch. */						\
-							asm { mov	ax, seg pxCurrentTCB		}	/* Restore the stack pointer from the TCB. */	\
-							asm { mov	ds, ax						}	\
-							asm { les	bx, dword ptr pxCurrentTCB	}	\
-							asm { mov	ss, es:[ bx + 2 ]			}	\
-							asm { mov	sp, es:[ bx ]				}
-
-#define portFIRST_CONTEXT()												\
-							__asm { mov	ax, seg pxCurrentTCB		}	\
-							__asm { mov	ds, ax						}	\
-							__asm { les	bx, dword ptr pxCurrentTCB	}	\
-							__asm { mov	ss, es:[ bx + 2 ]			}	\
-							__asm { mov	sp, es:[ bx ]				}	\
-							__asm { pop	bp							}	\
-							__asm { pop	di							}	\
-							__asm { pop	si							}	\
-							__asm { pop	ds							}	\
-							__asm { pop	es							}	\
-							__asm { pop	dx							}	\
-							__asm { pop	cx							}	\
-							__asm { pop	bx							}	\
-							__asm { pop	ax							}	\
-							__asm { iret							}
-
-
-#endif
-
diff --git a/FreeRTOS/Source/portable/BCC/16BitDOS/common/portcomn.c b/FreeRTOS/Source/portable/BCC/16BitDOS/common/portcomn.c
deleted file mode 100755
index c45fe05..0000000
--- a/FreeRTOS/Source/portable/BCC/16BitDOS/common/portcomn.c
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-Changes from V1.00:
-
-	+ pxPortInitialiseStack() now initialises the stack of new tasks to the
-	  same format used by the compiler.  This allows the compiler generated
-	  interrupt mechanism to be used for context switches.
-
-Changes from V2.6.1
-
-	+ Move usPortCheckFreeStackSpace() to tasks.c.
-*/
-
-
-#include 
-#include 
-#include "FreeRTOS.h"
-
-/*-----------------------------------------------------------*/
-
-/* See header file for description. */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t DS_Reg = 0;
-
-	/* Place a few bytes of known values on the bottom of the stack.
-	This is just useful for debugging. */
-
-	*pxTopOfStack = 0x1111;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2222;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x3333;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x4444;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x5555;
-	pxTopOfStack--;
-
-
-	/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
-
-	/* We are going to start the scheduler using a return from interrupt
-	instruction to load the program counter, so first there would be the
-	function call with parameters preamble. */
-	
-	*pxTopOfStack = FP_SEG( pvParameters );
-	pxTopOfStack--;
-	*pxTopOfStack = FP_OFF( pvParameters );
-	pxTopOfStack--;
-	*pxTopOfStack = FP_SEG( pxCode );
-	pxTopOfStack--;
-	*pxTopOfStack = FP_OFF( pxCode );
-	pxTopOfStack--;
-
-	/* Next the status register and interrupt return address. */
-	*pxTopOfStack = portINITIAL_SW; 
-	pxTopOfStack--;
-	*pxTopOfStack = FP_SEG( pxCode );
-	pxTopOfStack--;
-	*pxTopOfStack = FP_OFF( pxCode );
-	pxTopOfStack--;
-
-	/* The remaining registers would be pushed on the stack by our context
-	switch function.  These are loaded with values simply to make debugging
-	easier. */
-	*pxTopOfStack = ( StackType_t ) 0xAAAA;	/* AX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xCCCC;	/* CX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xEEEE;	/* ES */
-	pxTopOfStack--;
-
-	/* We need the true data segment. */
-	__asm{	MOV DS_Reg, DS };
-
-	*pxTopOfStack = DS_Reg;						/* DS */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x0123;	/* SI */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DI */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BP */
-
-	/*lint +e950 +e611 +e923 */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/CCS/ARM_CM3/port.c b/FreeRTOS/Source/portable/CCS/ARM_CM3/port.c
deleted file mode 100755
index 784b0eb..0000000
--- a/FreeRTOS/Source/portable/CCS/ARM_CM3/port.c
+++ /dev/null
@@ -1,621 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
-	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
-
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR			( 45UL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortSysTickHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-extern void vPortStartFirstTask( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY
-setting. */
-const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t * pxPortInitialiseStack( StackType_t * pxTopOfStack,
-                                     TaskFunction_t pxCode,
-                                     void * pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-
-	/* Offset added to account for the way the MCU uses the stack on entry/exit
-	of interrupts, and to ensure alignment. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
-
-	/* Save code space by skipping register initialisation. */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Start the first task. */
-	vPortStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known. */
-	( void ) portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TICKLESS_IDLE == 1 )
-
-	#pragma WEAK( vPortSuppressTicksAndSleep )
-	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-	TickType_t xModifiableIdleTime;
-
-		/* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
-		is accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-		/* Calculate the reload value required to wait xExpectedIdleTime
-		tick periods.  -1 is used because this code will execute part way
-		through one of the tick periods. */
-		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-		if( ulReloadValue > ulStoppedTimerCompensation )
-		{
-			ulReloadValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Enter a critical section but don't use the taskENTER_CRITICAL()
-		method as that will mask interrupts that should exit sleep mode. */
-		__asm( "	cpsid i" );
-		__asm( "	dsb" );
-		__asm( "	isb" );
-
-
-		/* If a context switch is pending or a task is waiting for the scheduler
-		to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-		{
-			/* Restart from whatever is left in the count register to complete
-			this tick period. */
-			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Reset the reload register to the value required for normal tick
-			periods. */
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Re-enable interrupts - see comments above __disable_interrupt()
-			call above. */
-			__asm( "	cpsie i" );
-		}
-		else
-		{
-			/* Set the new reload value. */
-			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-			/* Clear the SysTick count flag and set the count value back to
-			zero. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-			set its parameter to 0 to indicate that its implementation contains
-			its own wait for interrupt or wait for event instruction, and so wfi
-			should not be executed again.  However, the original expected idle
-			time variable must remain unmodified, so a copy is taken. */
-			xModifiableIdleTime = xExpectedIdleTime;
-			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-			if( xModifiableIdleTime > 0 )
-			{
-				__asm( "	dsb" );
-				__asm( "	wfi" );
-				__asm( "	isb" );
-			}
-			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-			/* Re-enable interrupts to allow the interrupt that brought the MCU
-			out of sleep mode to execute immediately.  see comments above
-			__disable_interrupt() call above. */
-			__asm( "	cpsie i" );
-			__asm( "	dsb" );
-			__asm( "	isb" );
-
-			/* Disable interrupts again because the clock is about to be stopped
-			and interrupts that execute while the clock is stopped will increase
-			any slippage between the time maintained by the RTOS and calendar
-			time. */
-			__asm( "	cpsid i" );
-			__asm( "	dsb" );
-			__asm( "	isb" );
-
-			/* Disable the SysTick clock without reading the
-			portNVIC_SYSTICK_CTRL_REG register to ensure the
-			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
-			the time the SysTick is stopped for is accounted for as best it can
-			be, but using the tickless mode will inevitably result in some tiny
-			drift of the time maintained by the kernel with respect to calendar
-			time*/
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-			/* Determine if the SysTick clock has already counted to zero and
-			been set back to the current reload value (the reload back being
-			correct for the entire expected idle time) or if the SysTick is yet
-			to count to zero (in which case an interrupt other than the SysTick
-			must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-			{
-				uint32_t ulCalculatedLoadValue;
-
-				/* The tick interrupt is already pending, and the SysTick count
-				reloaded with ulReloadValue.  Reset the
-				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-				period. */
-				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-				/* Don't allow a tiny value, or values that have somehow
-				underflowed because the post sleep hook did something
-				that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-				{
-					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-				}
-
-				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-				/* As the pending tick will be processed as soon as this
-				function exits, the tick value maintained by the tick is stepped
-				forward by one less than the time spent waiting. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				Work out how long the sleep lasted rounded to complete tick
-				periods (not the ulReload value which accounted for part
-				ticks). */
-				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-				/* How many complete tick periods passed while the processor
-				was waiting? */
-				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-				/* The reload value is set to whatever fraction of a single tick
-				period remains. */
-				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-			}
-
-			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-			vTaskStepTick( ulCompleteTickPeriods );
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Exit with interrpts enabled. */
-			__asm( "	cpsie i" );
-		}
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-#pragma WEAK( vPortSetupTimerInterrupt )
-void vPortSetupTimerInterrupt( void )
-{
-	/* Calculate the constants required to configure the tick interrupt. */
-	#if( configUSE_TICKLESS_IDLE == 1 )
-	{
-		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-	}
-	#endif /* configUSE_TICKLESS_IDLE */
-
-	/* Stop and clear the SysTick. */
-	portNVIC_SYSTICK_CTRL_REG = 0UL;
-	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	extern uint32_t ulPortGetIPSR( void );
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		ulCurrentInterrupt = ulPortGetIPSR();
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/CCS/ARM_CM3/portasm.asm b/FreeRTOS/Source/portable/CCS/ARM_CM3/portasm.asm
deleted file mode 100755
index 6d04fc3..0000000
--- a/FreeRTOS/Source/portable/CCS/ARM_CM3/portasm.asm
+++ /dev/null
@@ -1,144 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	.thumb
-
-	.ref pxCurrentTCB
-	.ref vTaskSwitchContext
-	.ref ulMaxSyscallInterruptPriority
-
-	.def xPortPendSVHandler
-	.def ulPortGetIPSR
-	.def vPortSVCHandler
-	.def vPortStartFirstTask
-
-NVICOffsetConst:					.word 	0xE000ED08
-CPACRConst:							.word 	0xE000ED88
-pxCurrentTCBConst:					.word	pxCurrentTCB
-ulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority
-
-; -----------------------------------------------------------
-
-	.align 4
-ulPortGetIPSR: .asmfunc
- 	mrs r0, ipsr
- 	bx r14
- 	.endasmfunc
- ; -----------------------------------------------------------
-
-	.align 4
-vPortSetInterruptMask: .asmfunc
-	push {r0}
-	ldr r0, ulMaxSyscallInterruptPriorityConst
-	msr basepri, r0
-	pop {r0}
-	bx r14
-	.endasmfunc
-; -----------------------------------------------------------
-
-	.align 4
-xPortPendSVHandler: .asmfunc
-	mrs r0, psp
-	isb
-
-	;/* Get the location of the current TCB. */
-	ldr	r3, pxCurrentTCBConst
-	ldr	r2, [r3]
-
-	;/* Save the core registers. */
-	stmdb r0!, {r4-r11}
-
-	;/* Save the new top of stack into the first member of the TCB. */
-	str r0, [r2]
-
-	stmdb sp!, {r3, r14}
-	ldr r0, ulMaxSyscallInterruptPriorityConst
-	ldr r1, [r0]
-	msr basepri, r1
-	dsb
-	isb
-	bl vTaskSwitchContext
-	mov r0, #0
-	msr basepri, r0
-	ldmia sp!, {r3, r14}
-
-	;/* The first item in pxCurrentTCB is the task top of stack. */
-	ldr r1, [r3]
-	ldr r0, [r1]
-
-	;/* Pop the core registers. */
-	ldmia r0!, {r4-r11}
-
-	msr psp, r0
-	isb
-	bx r14
-	.endasmfunc
-
-; -----------------------------------------------------------
-
-	.align 4
-vPortSVCHandler: .asmfunc
-	;/* Get the location of the current TCB. */
-	ldr	r3, pxCurrentTCBConst
-	ldr r1, [r3]
-	ldr r0, [r1]
-	;/* Pop the core registers. */
-	ldmia r0!, {r4-r11}
-	msr psp, r0
-	isb
-	mov r0, #0
-	msr	basepri, r0
-	orr r14, #0xd
-	bx r14
-	.endasmfunc
-
-; -----------------------------------------------------------
-
-	.align 4
-vPortStartFirstTask: .asmfunc
-	;/* Use the NVIC offset register to locate the stack. */
-	ldr r0, NVICOffsetConst
-	ldr r0, [r0]
-	ldr r0, [r0]
-	;/* Set the msp back to the start of the stack. */
-	msr msp, r0
-	;/* Clear the bit that indicates the FPU is in use in case the FPU was used
-	;before the scheduler was started - which would otherwise result in the
-	;unnecessary leaving of space in the SVC stack for lazy saving of FPU
-	;registers. */
-	mov r0, #0
-	msr control, r0
-	;/* Call SVC to start the first task. */
-	cpsie i
-	cpsie f
-	dsb
-	isb
-	svc #0
-	.endasmfunc
-
-; -----------------------------------------------------------
-
diff --git a/FreeRTOS/Source/portable/CCS/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/CCS/ARM_CM3/portmacro.h
deleted file mode 100755
index 7d267c3..0000000
--- a/FreeRTOS/Source/portable/CCS/ARM_CM3/portmacro.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-
-/*-----------------------------------------------------------*/
-
-/* Compiler directives. */
-#define portWEAK_SYMBOL				__attribute__((weak))
-
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD()											\
-{															\
-	/* Set a PendSV to request a context switch. */			\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
-	__asm( "	dsb" );										\
-	__asm( "	isb" );										\
-}
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()										\
-{																		\
-	_set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
-	__asm( "	dsb" );													\
-	__asm( "	isb" );													\
-}
-
-#define portENABLE_INTERRUPTS()					_set_interrupt_priority( 0 )
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()		_set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( "	dsb" ); __asm( "	isb" )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	_set_interrupt_priority( x )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/CCS/ARM_CM4F/port.c b/FreeRTOS/Source/portable/CCS/ARM_CM4F/port.c
deleted file mode 100755
index 3824b56..0000000
--- a/FreeRTOS/Source/portable/CCS/ARM_CM4F/port.c
+++ /dev/null
@@ -1,644 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __TI_VFP_SUPPORT__
-	#error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
-	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
-
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR					( 0x01000000 )
-#define portINITIAL_EXC_RETURN				( 0xfffffffd )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR			( 45UL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortSysTickHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-extern void vPortStartFirstTask( void );
-
-/*
- * Turn the VFP on.
- */
-extern void vPortEnableVFP( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Required to allow portasm.asm access the configMAX_SYSCALL_INTERRUPT_PRIORITY
-setting. */
-const uint32_t ulMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-
-	/* Offset added to account for the way the MCU uses the stack on entry/exit
-	of interrupts, and to ensure alignment. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
-
-	/* Save code space by skipping register initialisation. */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-
-	/* A save method is being used that requires each task to maintain its
-	own exec return value. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-		
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Ensure the VFP is enabled - it should be anyway. */
-	vPortEnableVFP();
-
-	/* Lazy save always. */
-	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
-	/* Start the first task. */
-	vPortStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known. */
-	( void ) portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TICKLESS_IDLE == 1 )
-
-	#pragma WEAK( vPortSuppressTicksAndSleep )
-	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-	TickType_t xModifiableIdleTime;
-
-		/* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
-		is accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-		/* Calculate the reload value required to wait xExpectedIdleTime
-		tick periods.  -1 is used because this code will execute part way
-		through one of the tick periods. */
-		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-		if( ulReloadValue > ulStoppedTimerCompensation )
-		{
-			ulReloadValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Enter a critical section but don't use the taskENTER_CRITICAL()
-		method as that will mask interrupts that should exit sleep mode. */
-		__asm( "	cpsid i" );
-		__asm( "	dsb" );
-		__asm( "	isb" );
-
-
-		/* If a context switch is pending or a task is waiting for the scheduler
-		to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-		{
-			/* Restart from whatever is left in the count register to complete
-			this tick period. */
-			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Reset the reload register to the value required for normal tick
-			periods. */
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Re-enable interrupts - see comments above __disable_interrupt()
-			call above. */
-			__asm( "	cpsie i" );
-		}
-		else
-		{
-			/* Set the new reload value. */
-			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-			/* Clear the SysTick count flag and set the count value back to
-			zero. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-			set its parameter to 0 to indicate that its implementation contains
-			its own wait for interrupt or wait for event instruction, and so wfi
-			should not be executed again.  However, the original expected idle
-			time variable must remain unmodified, so a copy is taken. */
-			xModifiableIdleTime = xExpectedIdleTime;
-			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-			if( xModifiableIdleTime > 0 )
-			{
-				__asm( "	dsb" );
-				__asm( "	wfi" );
-				__asm( "	isb" );
-			}
-			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-			/* Re-enable interrupts to allow the interrupt that brought the MCU
-			out of sleep mode to execute immediately.  see comments above
-			__disable_interrupt() call above. */
-			__asm( "	cpsie i" );
-			__asm( "	dsb" );
-			__asm( "	isb" );
-
-			/* Disable interrupts again because the clock is about to be stopped
-			and interrupts that execute while the clock is stopped will increase
-			any slippage between the time maintained by the RTOS and calendar
-			time. */
-			__asm( "	cpsid i" );
-			__asm( "	dsb" );
-			__asm( "	isb" );
-
-			/* Disable the SysTick clock without reading the
-			portNVIC_SYSTICK_CTRL_REG register to ensure the
-			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
-			the time the SysTick is stopped for is accounted for as best it can
-			be, but using the tickless mode will inevitably result in some tiny
-			drift of the time maintained by the kernel with respect to calendar
-			time*/
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-			/* Determine if the SysTick clock has already counted to zero and
-			been set back to the current reload value (the reload back being
-			correct for the entire expected idle time) or if the SysTick is yet
-			to count to zero (in which case an interrupt other than the SysTick
-			must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-			{
-				uint32_t ulCalculatedLoadValue;
-
-				/* The tick interrupt is already pending, and the SysTick count
-				reloaded with ulReloadValue.  Reset the
-				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-				period. */
-				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-				/* Don't allow a tiny value, or values that have somehow
-				underflowed because the post sleep hook did something
-				that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-				{
-					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-				}
-
-				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-				/* As the pending tick will be processed as soon as this
-				function exits, the tick value maintained by the tick is stepped
-				forward by one less than the time spent waiting. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				Work out how long the sleep lasted rounded to complete tick
-				periods (not the ulReload value which accounted for part
-				ticks). */
-				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-				/* How many complete tick periods passed while the processor
-				was waiting? */
-				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-				/* The reload value is set to whatever fraction of a single tick
-				period remains. */
-				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-			}
-
-			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-			vTaskStepTick( ulCompleteTickPeriods );
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Exit with interrpts enabled. */
-			__asm( "	cpsie i" );
-		}
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-#pragma WEAK( vPortSetupTimerInterrupt )
-void vPortSetupTimerInterrupt( void )
-{
-	/* Calculate the constants required to configure the tick interrupt. */
-	#if( configUSE_TICKLESS_IDLE == 1 )
-	{
-		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-	}
-	#endif /* configUSE_TICKLESS_IDLE */
-
-	/* Stop and clear the SysTick. */
-	portNVIC_SYSTICK_CTRL_REG = 0UL;
-	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	extern uint32_t ulPortGetIPSR( void );
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		ulCurrentInterrupt = ulPortGetIPSR();
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/CCS/ARM_CM4F/portasm.asm b/FreeRTOS/Source/portable/CCS/ARM_CM4F/portasm.asm
deleted file mode 100755
index a2251b7..0000000
--- a/FreeRTOS/Source/portable/CCS/ARM_CM4F/portasm.asm
+++ /dev/null
@@ -1,171 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	.thumb
-
-	.ref pxCurrentTCB
-	.ref vTaskSwitchContext
-	.ref ulMaxSyscallInterruptPriority
-
-	.def xPortPendSVHandler
-	.def ulPortGetIPSR
-	.def vPortSVCHandler
-	.def vPortStartFirstTask
-	.def vPortEnableVFP
-
-NVICOffsetConst:					.word 	0xE000ED08
-CPACRConst:							.word 	0xE000ED88
-pxCurrentTCBConst:					.word	pxCurrentTCB
-ulMaxSyscallInterruptPriorityConst: .word ulMaxSyscallInterruptPriority
-
-; -----------------------------------------------------------
-
-	.align 4
-ulPortGetIPSR: .asmfunc
- 	mrs r0, ipsr
- 	bx r14
- 	.endasmfunc
- ; -----------------------------------------------------------
-
-	.align 4
-vPortSetInterruptMask: .asmfunc
-	push {r0}
-	ldr r0, ulMaxSyscallInterruptPriorityConst
-	msr basepri, r0
-	pop {r0}
-	bx r14
-	.endasmfunc
-; -----------------------------------------------------------
-
-	.align 4
-xPortPendSVHandler: .asmfunc
-	mrs r0, psp
-	isb
-
-	;/* Get the location of the current TCB. */
-	ldr	r3, pxCurrentTCBConst
-	ldr	r2, [r3]
-
-	;/* Is the task using the FPU context?  If so, push high vfp registers. */
-	tst r14, #0x10
-	it eq
-	vstmdbeq r0!, {s16-s31}
-
-	;/* Save the core registers. */
-	stmdb r0!, {r4-r11, r14}
-
-	;/* Save the new top of stack into the first member of the TCB. */
-	str r0, [r2]
-
-	stmdb sp!, {r0, r3}
-	ldr r0, ulMaxSyscallInterruptPriorityConst
-	ldr r1, [r0]
-	msr basepri, r1
-	dsb
-	isb
-	bl vTaskSwitchContext
-	mov r0, #0
-	msr basepri, r0
-	ldmia sp!, {r0, r3}
-
-	;/* The first item in pxCurrentTCB is the task top of stack. */
-	ldr r1, [r3]
-	ldr r0, [r1]
-
-	;/* Pop the core registers. */
-	ldmia r0!, {r4-r11, r14}
-
-	;/* Is the task using the FPU context?  If so, pop the high vfp registers
-	;too. */
-	tst r14, #0x10
-	it eq
-	vldmiaeq r0!, {s16-s31}
-
-	msr psp, r0
-	isb
-	bx r14
-	.endasmfunc
-
-; -----------------------------------------------------------
-
-	.align 4
-vPortSVCHandler: .asmfunc
-	;/* Get the location of the current TCB. */
-	ldr	r3, pxCurrentTCBConst
-	ldr r1, [r3]
-	ldr r0, [r1]
-	;/* Pop the core registers. */
-	ldmia r0!, {r4-r11, r14}
-	msr psp, r0
-	isb
-	mov r0, #0
-	msr	basepri, r0
-	bx r14
-	.endasmfunc
-
-; -----------------------------------------------------------
-
-	.align 4
-vPortStartFirstTask: .asmfunc
-	;/* Use the NVIC offset register to locate the stack. */
-	ldr r0, NVICOffsetConst
-	ldr r0, [r0]
-	ldr r0, [r0]
-	;/* Set the msp back to the start of the stack. */
-	msr msp, r0
-	;/* Clear the bit that indicates the FPU is in use in case the FPU was used
-	;before the scheduler was started - which would otherwise result in the
-	;unnecessary leaving of space in the SVC stack for lazy saving of FPU
-	;registers. */
-	mov r0, #0
-	msr control, r0
-	;/* Call SVC to start the first task. */
-	cpsie i
-	cpsie f
-	dsb
-	isb
-	svc #0
-	.endasmfunc
-
-; -----------------------------------------------------------
-
-	.align 4
-vPortEnableVFP: .asmfunc
-	;/* The FPU enable bits are in the CPACR. */
-	ldr.w r0, CPACRConst
-	ldr	r1, [r0]
-
-	;/* Enable CP10 and CP11 coprocessors, then save back. */
-	orr	r1, r1, #( 0xf << 20 )
-	str r1, [r0]
-	bx	r14
-	.endasmfunc
-
-	.end
-
-; -----------------------------------------------------------
-
diff --git a/FreeRTOS/Source/portable/CCS/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/CCS/ARM_CM4F/portmacro.h
deleted file mode 100755
index 81f7897..0000000
--- a/FreeRTOS/Source/portable/CCS/ARM_CM4F/portmacro.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD()											\
-{															\
-	/* Set a PendSV to request a context switch. */			\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
-	__asm( "	dsb" );										\
-	__asm( "	isb" );										\
-}
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()										\
-{																		\
-	_set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
-	__asm( "	dsb" );													\
-	__asm( "	isb" );													\
-}
-
-#define portENABLE_INTERRUPTS()					_set_interrupt_priority( 0 )
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()		_set_interrupt_priority( configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm( "	dsb" ); __asm( "	isb" )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	_set_interrupt_priority( x )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/port.c b/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/port.c
deleted file mode 100755
index c01fac2..0000000
--- a/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/port.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* FreeRTOS includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*-----------------------------------------------------------*/
-
-/* Count of the critical section nesting depth. */
-uint32_t ulCriticalNesting = 9999;
-
-/*-----------------------------------------------------------*/
-
-/* Registers required to configure the RTI. */
-#define portRTI_GCTRL_REG  		( * ( ( volatile uint32_t * ) 0xFFFFFC00 ) )
-#define portRTI_TBCTRL_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC04 ) )
-#define portRTI_COMPCTRL_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC0C ) )
-#define portRTI_CNT0_FRC0_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC10 ) )
-#define portRTI_CNT0_UC0_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC14 ) )
-#define portRTI_CNT0_CPUC0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC18 ) )
-#define portRTI_CNT0_COMP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC50 ) )
-#define portRTI_CNT0_UDCP0_REG  ( * ( ( volatile uint32_t * ) 0xFFFFFC54 ) )
-#define portRTI_SETINTENA_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC80 ) )
-#define portRTI_CLEARINTENA_REG ( * ( ( volatile uint32_t * ) 0xFFFFFC84 ) )
-#define portRTI_INTFLAG_REG  	( * ( ( volatile uint32_t * ) 0xFFFFFC88 ) )
-
-
-/* Constants required to set up the initial stack of each task. */
-#define portINITIAL_SPSR	   	( ( StackType_t ) 0x1F )
-#define portINITIAL_FPSCR	  	( ( StackType_t ) 0x00 )
-#define portINSTRUCTION_SIZE   	( ( StackType_t ) 0x04 )
-#define portTHUMB_MODE_BIT		( ( StackType_t ) 0x20 )
-
-/* The number of words on the stack frame between the saved Top Of Stack and
-R0 (in which the parameters are passed. */
-#define portSPACE_BETWEEN_TOS_AND_PARAMETERS	( 12 )
-
-/*-----------------------------------------------------------*/
-
-/* vPortStartFirstSTask() is defined in portASM.asm */
-extern void vPortStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/* Saved as part of the task context.  Set to pdFALSE if the task does not
-require an FPU context. */
-uint32_t ulTaskHasFPUContext = 0;
-
-/*-----------------------------------------------------------*/
-
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
-	pxOriginalTOS = pxTopOfStack;
-
-	#if __TI_VFP_SUPPORT__
-	{
-		/* Ensure the stack is correctly aligned on exit. */
-		pxTopOfStack--;
-	}
-	#endif
-
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* First on the stack is the return address - which is the start of the as
-	the task has not executed yet.  The offset is added to make the return
-	address appear as it would within an IRQ ISR. */
-	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
-	pxTopOfStack--;
-
-	#ifdef portPRELOAD_TASK_REGISTERS
-	{
-		*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-		pxTopOfStack--;
-	}
-	#else
-	{
-		pxTopOfStack -= portSPACE_BETWEEN_TOS_AND_PARAMETERS;
-	}
-	#endif
-
-	/* Function parameters are passed in R0. */
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* Set the status register for system mode, with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) ( ( _get_CPSR() & ~0xFF ) | portINITIAL_SPSR );
-
-	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
-	{
-		/* The task will start in thumb mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-
-	#ifdef __TI_VFP_SUPPORT__
-	{
-		pxTopOfStack--;
-
-		/* The last thing on the stack is the tasks ulUsingFPU value, which by
-		default is set to indicate that the stack frame does not include FPU
-		registers. */
-		*pxTopOfStack = pdFALSE;
-	}
-	#endif
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt(void)
-{
-	/* Disable timer 0. */
-	portRTI_GCTRL_REG &= 0xFFFFFFFEUL;
-
-	/* Use the internal counter. */
-	portRTI_TBCTRL_REG = 0x00000000U;
-
-	/* COMPSEL0 will use the RTIFRC0 counter. */
-	portRTI_COMPCTRL_REG = 0x00000000U;
-
-	/* Initialise the counter and the prescale counter registers. */
-	portRTI_CNT0_UC0_REG =  0x00000000U;
-	portRTI_CNT0_FRC0_REG =  0x00000000U;
-
-	/* Set Prescalar for RTI clock. */
-	portRTI_CNT0_CPUC0_REG = 0x00000001U;
-	portRTI_CNT0_COMP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
-	portRTI_CNT0_UDCP0_REG = ( configCPU_CLOCK_HZ / 2 ) / configTICK_RATE_HZ;
-
-	/* Clear interrupts. */
-	portRTI_INTFLAG_REG =  0x0007000FU;
-	portRTI_CLEARINTENA_REG	= 0x00070F0FU;
-
-	/* Enable the compare 0 interrupt. */
-	portRTI_SETINTENA_REG = 0x00000001U;
-	portRTI_GCTRL_REG |= 0x00000001U;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler(void)
-{
-	/* Start the timer that generates the tick ISR. */
-	prvSetupTimerInterrupt();
-
-	/* Reset the critical section nesting count read to execute the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task.  This is done from portASM.asm as ARM mode must be
-	used. */
-	vPortStartFirstTask();
-
-	/* Should not get here! */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-void vPortEndScheduler(void)
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_PREEMPTION == 0
-
-	/* The cooperative scheduler requires a normal IRQ service routine to
-	 * simply increment the system tick. */
-	__interrupt void vPortNonPreemptiveTick( void )
-	{
-		/* clear clock interrupt flag */
-		portRTI_INTFLAG_REG = 0x00000001;
-
-		/* Increment the tick count - this may make a delaying task ready
-		to run - but a context switch is not performed. */
-		xTaskIncrementTick();
-	}
-
- #else
-
-	/*
-	 **************************************************************************
-	 * The preemptive scheduler ISR is written in assembler and can be found
-	 * in the portASM.asm file. This will only get used if portUSE_PREEMPTION
-	 * is set to 1 in portmacro.h
-	 **************************************************************************
-	 */
-	void vPortPreemptiveTick( void );
-
-#endif
-/*-----------------------------------------------------------*/
-
-
-/*
- * Disable interrupts, and keep a count of the nesting depth.
- */
-void vPortEnterCritical( void )
-{
-	/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
-	portDISABLE_INTERRUPTS();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Decrement the critical nesting count, and if it has reached zero, re-enable
- * interrupts.
- */
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > 0 )
-	{
-		/* Decrement the nesting count as we are leaving a critical section. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then interrupts should be
-		re-enabled. */
-		if( ulCriticalNesting == 0 )
-		{
-			/* Enable interrupts as per portENABLE_INTERRUPTS(). */
-			portENABLE_INTERRUPTS();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if __TI_VFP_SUPPORT__
-
-	void vPortTaskUsesFPU( void )
-	{
-	extern void vPortInitialiseFPSCR( void );
-
-		/* A task is registering the fact that it needs an FPU context.  Set the
-		FPU flag (saved as part of the task context. */
-		ulTaskHasFPUContext = pdTRUE;
-
-		/* Initialise the floating point status register. */
-		vPortInitialiseFPSCR();
-	}
-
-#endif /* __TI_VFP_SUPPORT__ */
-
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portASM.asm b/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portASM.asm
deleted file mode 100755
index cec6166..0000000
--- a/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portASM.asm
+++ /dev/null
@@ -1,229 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-        .text
-        .arm
-        .ref vTaskSwitchContext
-        .ref xTaskIncrementTick
-        .ref ulTaskHasFPUContext
-		.ref pxCurrentTCB
-
-;/*-----------------------------------------------------------*/
-;
-; Save Task Context
-;
-portSAVE_CONTEXT .macro
-		DSB
-
-		; Push R0 as we are going to use it
-		STMDB	SP!, {R0}
-
-		; Set R0 to point to the task stack pointer.
-		STMDB	SP,{SP}^
-		SUB	SP, SP, #4
-		LDMIA	SP!,{R0}
-
-		; Push the return address onto the stack.
-		STMDB	R0!, {LR}
-
-		; Now LR has been saved, it can be used instead of R0.
-		MOV	LR, R0
-
-		; Pop R0 so it can be saved onto the task stack.
-		LDMIA	SP!, {R0}
-
-		; Push all the system mode registers onto the task stack.
-		STMDB	LR,{R0-LR}^
-		SUB	LR, LR, #60
-
-		; Push the SPSR onto the task stack.
-		MRS	R0, SPSR
-		STMDB	LR!, {R0}
-
-    .if (__TI_VFP_SUPPORT__)
-		;Determine if the task maintains an FPU context.
-		LDR	R0, ulFPUContextConst
-		LDR	R0, [R0]
-
-		; Test the flag
-		CMP		R0, #0
-
-		; If the task is not using a floating point context then skip the
-		; saving of the FPU registers.
-		BEQ		$+16
-		FSTMDBD	LR!, {D0-D15}
-		FMRX    R1,  FPSCR
-		STMFD   LR!, {R1}
-
-		; Save the flag
-		STMDB	LR!, {R0}
-	.endif
-
-		; Store the new top of stack for the task.
-		LDR	R0, pxCurrentTCBConst
-		LDR	R0, [R0]
-		STR	LR, [R0]
-
-        .endm
-
-;/*-----------------------------------------------------------*/
-;
-; Restore Task Context
-;
-portRESTORE_CONTEXT .macro
-		LDR		R0, pxCurrentTCBConst
-		LDR		R0, [R0]
-		LDR		LR, [R0]
-
-	.if (__TI_VFP_SUPPORT__)
-		; The floating point context flag is the first thing on the stack.
-		LDR		R0, ulFPUContextConst
-		LDMFD	LR!, {R1}
-		STR		R1, [R0]
-
-		; Test the flag
-		CMP		R1, #0
-
-		; If the task is not using a floating point context then skip the
-		; VFP register loads.
-		BEQ		$+16
-
-		; Restore the floating point context.
-		LDMFD   LR!, {R0}
-		FLDMIAD	LR!, {D0-D15}
-		FMXR    FPSCR, R0
-	.endif
-
-		; Get the SPSR from the stack.
-		LDMFD	LR!, {R0}
-		MSR		SPSR_CSXF, R0
-
-		; Restore all system mode registers for the task.
-		LDMFD	LR, {R0-R14}^
-
-		; Restore the return address.
-		LDR		LR, [LR, #+60]
-
-		; And return - correcting the offset in the LR to obtain the
-		; correct address.
-		SUBS	PC, LR, #4
-        .endm
-
-;/*-----------------------------------------------------------*/
-; Start the first task by restoring its context.
-
-        .def vPortStartFirstTask
-
-vPortStartFirstTask:
-        portRESTORE_CONTEXT
-
-;/*-----------------------------------------------------------*/
-; Yield to another task.
-
-        .def vPortYieldProcessor
-
-vPortYieldProcessor:
-		; Within an IRQ ISR the link register has an offset from the true return
-		; address.  SWI doesn't do this. Add the offset manually so the ISR
-		; return code can be used.
-        ADD     LR, LR, #4
-
-        ; First save the context of the current task.
-        portSAVE_CONTEXT
-
-        ; Select the next task to execute. */
-        BL      vTaskSwitchContext
-
-        ; Restore the context of the task selected to execute.
-        portRESTORE_CONTEXT
-
-;/*-----------------------------------------------------------*/
-; Yield to another task from within the FreeRTOS API
-
-		.def vPortYeildWithinAPI
-
-vPortYeildWithinAPI:
-		; Save the context of the current task.
-
-        portSAVE_CONTEXT
-		; Clear SSI flag.
-		MOVW    R0, #0xFFF4
-		MOVT 	R0, #0xFFFF
-		LDR     R0, [R0]
-
-		; Select the next task to execute. */
-        BL      vTaskSwitchContext
-
-        ; Restore the context of the task selected to execute.
-        portRESTORE_CONTEXT
-
-;/*-----------------------------------------------------------*/
-; Preemptive Tick
-
-        .def vPortPreemptiveTick
-
-vPortPreemptiveTick:
-
-		; Save the context of the current task.
-        portSAVE_CONTEXT
-
-        ; Clear interrupt flag
-        MOVW    R0, #0xFC88
-        MOVT    R0, #0xFFFF
-        MOV     R1, #1
-        STR     R1, [R0]
-
-        ; Increment the tick count, making any adjustments to the blocked lists
-        ; that may be necessary.
-        BL      xTaskIncrementTick
-
-        ; Select the next task to execute.
-        CMP	R0, #0
-        BLNE    vTaskSwitchContext
-
-        ; Restore the context of the task selected to execute.
-        portRESTORE_CONTEXT
-
-;-------------------------------------------------------------------------------
-
-	.if (__TI_VFP_SUPPORT__)
-
-		.def vPortInitialiseFPSCR
-
-vPortInitialiseFPSCR:
-
-		MOV		R0, #0
-		FMXR    FPSCR, R0
-		BX		LR
-
-	.endif ;__TI_VFP_SUPPORT__
-
-
-pxCurrentTCBConst	.word	pxCurrentTCB
-ulFPUContextConst 	.word   ulTaskHasFPUContext
-;-------------------------------------------------------------------------------
-
diff --git a/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h b/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h
deleted file mode 100755
index 414cc23..0000000
--- a/FreeRTOS/Source/portable/CCS/ARM_Cortex-R4/portmacro.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORTMACRO_H__
-#define __PORTMACRO_H__
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if (configUSE_16_BIT_TICKS == 1)
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY (TickType_t) 0xFFFF
-#else
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY (TickType_t) 0xFFFFFFFFF
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH    (-1)
-#define portTICK_PERIOD_MS    ((TickType_t) 1000 / configTICK_RATE_HZ)
-#define portBYTE_ALIGNMENT  8
-
-/* Critical section handling. */
-extern void vPortEnterCritical(void);
-extern void vPortExitCritical(void);
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-#define portDISABLE_INTERRUPTS()	asm( " CPSID I" )
-#define portENABLE_INTERRUPTS()		asm( " CPSIE I" )
-
-/* Scheduler utilities. */
-#pragma SWI_ALIAS( vPortYield, 0 )
-extern void vPortYield( void );
-#define portYIELD()             	vPortYield()
-#define portSYS_SSIR1_REG			( * ( ( volatile uint32_t * ) 0xFFFFFFB0 ) )
-#define portSYS_SSIR1_SSKEY			( 0x7500UL )
-#define portYIELD_WITHIN_API()		{ portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  asm( " DSB " ); asm( " ISB " ); }
-#define portYIELD_FROM_ISR( x )		if( x != pdFALSE ){ portSYS_SSIR1_REG = portSYS_SSIR1_SSKEY;  ( void ) portSYS_SSIR1_REG; }
-
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-/* Architecture specific optimisations. */
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION(vFunction, pvParameters)       void vFunction(void *pvParameters)
-#define portTASK_FUNCTION_PROTO(vFunction, pvParameters) void vFunction(void *pvParameters)
-
-#endif /* __PORTMACRO_H__ */
-
diff --git a/FreeRTOS/Source/portable/CCS/MSP430X/data_model.h b/FreeRTOS/Source/portable/CCS/MSP430X/data_model.h
deleted file mode 100755
index c777098..0000000
--- a/FreeRTOS/Source/portable/CCS/MSP430X/data_model.h
+++ /dev/null
@@ -1,53 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	.if $DEFINED( __LARGE_DATA_MODEL__ )
-		.define "pushm.a", pushm_x
-		.define "popm.a", popm_x
-		.define "push.a", push_x
-		.define "pop.a", pop_x
-		.define "mov.a", mov_x
-	.else
-		.define "pushm.w", pushm_x
-		.define "popm.w", popm_x
-		.define "push.w", push_x
-		.define "pop.w", pop_x
-		.define "mov.w", mov_x
-	.endif
-
-	.if $DEFINED( __LARGE_CODE_MODEL__ )
-		.define "calla", call_x
-		.define "reta", ret_x
-	.else
-		.define "call", call_x
-		.define "ret", ret_x
-	.endif
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/CCS/MSP430X/port.c b/FreeRTOS/Source/portable/CCS/MSP430X/port.c
deleted file mode 100755
index 2952a59..0000000
--- a/FreeRTOS/Source/portable/CCS/MSP430X/port.c
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MSP430X port.
- *----------------------------------------------------------*/
-
-/* Constants required for hardware setup.  The tick ISR runs off the ACLK,
-not the MCLK. */
-#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
-#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
-#define portFLAGS_INT_ENABLED			( ( StackType_t ) 0x08 )
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/* Each task maintains a count of the critical section nesting depth.  Each
-time a critical section is entered the count is incremented.  Each time a
-critical section is exited the count is decremented - with interrupts only
-being re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as this will cause problems during the startup
-sequence. */
-volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
-/*-----------------------------------------------------------*/
-
-
-/*
- * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
- * could have alternatively used the watchdog timer or timer 1.
- */
-void vPortSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint16_t *pusTopOfStack;
-uint32_t *pulTopOfStack, ulTemp;
-
-	/*
-		Place a few bytes of known values on the bottom of the stack.
-		This is just useful for debugging and can be included if required.
-
-		*pxTopOfStack = ( StackType_t ) 0x1111;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x2222;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x3333;
-		pxTopOfStack--;
-	*/
-
-	/* Data types are need either 16 bits or 32 bits depending on the data 
-	and code model used. */
-	if( sizeof( pxCode ) == sizeof( uint16_t ) )
-	{
-		pusTopOfStack = ( uint16_t * ) pxTopOfStack;
-		ulTemp = ( uint32_t ) pxCode;
-		*pusTopOfStack = ( uint16_t ) ulTemp;
-	}
-	else
-	{
-		/* Make room for a 20 bit value stored as a 32 bit value. */
-		pusTopOfStack = ( uint16_t * ) pxTopOfStack;		
-		pusTopOfStack--;
-		pulTopOfStack = ( uint32_t * ) pusTopOfStack;
-		*pulTopOfStack = ( uint32_t ) pxCode;
-	}
-
-	pusTopOfStack--;
-	*pusTopOfStack = portFLAGS_INT_ENABLED;
-	pusTopOfStack -= ( sizeof( StackType_t ) / 2 );
-	
-	/* From here on the size of stacked items depends on the memory model. */
-	pxTopOfStack = ( StackType_t * ) pusTopOfStack;
-
-	/* Next the general purpose registers. */
-	#ifdef PRELOAD_REGISTER_VALUES
-		*pxTopOfStack = ( StackType_t ) 0xffff;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0xeeee;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0xdddd;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0xbbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0xaaaa;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x9999;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x8888;
-		pxTopOfStack--;	
-		*pxTopOfStack = ( StackType_t ) 0x5555;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x6666;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x5555;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x4444;
-		pxTopOfStack--;
-	#else
-		pxTopOfStack -= 3;
-		*pxTopOfStack = ( StackType_t ) pvParameters;
-		pxTopOfStack -= 9;
-	#endif
-
-	/* A variable is used to keep track of the critical section nesting.
-	This variable has to be stored as part of the task context and is
-	initially set to zero. */
-	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
-
-	/* Return a pointer to the top of the stack we have generated so this can
-	be stored in the task control block for the task. */
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the MSP430 port will get stopped.  If required simply
-	disable the tick interrupt here. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Hardware initialisation to generate the RTOS tick.
- */
-void vPortSetupTimerInterrupt( void )
-{
-	vApplicationSetupTimerInterrupt();
-}
-/*-----------------------------------------------------------*/
-
-#pragma vector=configTICK_VECTOR
-interrupt void vTickISREntry( void )
-{
-extern void vPortTickISR( void );
-
-	__bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
-	#if configUSE_PREEMPTION == 1
-		extern void vPortPreemptiveTickISR( void );
-		vPortPreemptiveTickISR();
-	#else
-		extern void vPortCooperativeTickISR( void );
-		vPortCooperativeTickISR();
-	#endif
-}
-
-	
diff --git a/FreeRTOS/Source/portable/CCS/MSP430X/portext.asm b/FreeRTOS/Source/portable/CCS/MSP430X/portext.asm
deleted file mode 100755
index ca3b4de..0000000
--- a/FreeRTOS/Source/portable/CCS/MSP430X/portext.asm
+++ /dev/null
@@ -1,159 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-; * The definition of the "register test" tasks, as described at the top of
-; * main.c
-
-	.include data_model.h
-
-	.global xTaskIncrementTick
-	.global vTaskSwitchContext
-	.global vPortSetupTimerInterrupt
-	.global pxCurrentTCB
-	.global usCriticalNesting
-
-	.def vPortPreemptiveTickISR
-	.def vPortCooperativeTickISR
-	.def vPortYield
-	.def xPortStartScheduler
-
-;-----------------------------------------------------------
-
-portSAVE_CONTEXT .macro
-
-	;Save the remaining registers.
-	pushm_x	#12, r15
-	mov.w	&usCriticalNesting, r14
-	push_x r14
-	mov_x	&pxCurrentTCB, r12
-	mov_x	sp, 0( r12 )
-	.endm
-;-----------------------------------------------------------
-
-portRESTORE_CONTEXT .macro
-
-	mov_x	&pxCurrentTCB, r12
-	mov_x	@r12, sp
-	pop_x	r15
-	mov.w	r15, &usCriticalNesting
-	popm_x	#12, r15
-	nop
-	pop.w	sr
-	nop
-	ret_x
-	.endm
-;-----------------------------------------------------------
-
-;*
-;* The RTOS tick ISR.
-;*
-;* If the cooperative scheduler is in use this simply increments the tick
-;* count.
-;*
-;* If the preemptive scheduler is in use a context switch can also occur.
-;*/
-
-	.text
-	.align 2
-
-vPortPreemptiveTickISR: .asmfunc
-
-	; The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs
-	;to save it manually before it gets modified (interrupts get disabled).
-	push.w sr
-	portSAVE_CONTEXT
-
-	call_x	#xTaskIncrementTick
-	call_x	#vTaskSwitchContext
-
-	portRESTORE_CONTEXT
-	.endasmfunc
-;-----------------------------------------------------------
-
-	.align 2
-
-vPortCooperativeTickISR: .asmfunc
-
-	; The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs
-	;to save it manually before it gets modified (interrupts get disabled).
-	push.w sr
-	portSAVE_CONTEXT
-
-	call_x	#xTaskIncrementTick
-
-	portRESTORE_CONTEXT
-
-	.endasmfunc
-;-----------------------------------------------------------
-
-;
-; Manual context switch called by the portYIELD() macro.
-;
-
-	.align 2
-
-vPortYield: .asmfunc
-
-	; The sr needs saving before it is modified.
-	push.w	sr
-
-	; Now the SR is stacked we can disable interrupts.
-	dint
-	nop
-
-	; Save the context of the current task.
-	portSAVE_CONTEXT
-
-	; Select the next task to run.
-	call_x	#vTaskSwitchContext
-
-	; Restore the context of the new task.
-	portRESTORE_CONTEXT
-	.endasmfunc
-;-----------------------------------------------------------
-
-
-;
-; Start off the scheduler by initialising the RTOS tick timer, then restoring
-; the context of the first task.
-;
-
-	.align 2
-
-xPortStartScheduler: .asmfunc
-
-	; Setup the hardware to generate the tick.  Interrupts are disabled
-	; when this function is called.
-	call_x	#vPortSetupTimerInterrupt
-
-	; Restore the context of the first task that is going to run.
-	portRESTORE_CONTEXT
-	.endasmfunc
-;-----------------------------------------------------------
-
-	.end
-
diff --git a/FreeRTOS/Source/portable/CCS/MSP430X/portmacro.h b/FreeRTOS/Source/portable/CCS/MSP430X/portmacro.h
deleted file mode 100755
index a5f5f7d..0000000
--- a/FreeRTOS/Source/portable/CCS/MSP430X/portmacro.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Hardware includes. */
-#include "msp430.h"
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		int
-#define portBASE_TYPE	portSHORT
-
-/* The stack type changes depending on the data model. */
-#ifdef __LARGE_DATA_MODEL__
-	#define portSTACK_TYPE uint32_t
-#else
-	#define portSTACK_TYPE uint16_t
-	#define portPOINTER_SIZE_TYPE uint16_t
-#endif
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS()	_disable_interrupt(); _nop()
-#define portENABLE_INTERRUPTS()		_enable_interrupt(); _nop()
-/*-----------------------------------------------------------*/
-
-/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
-
-#define portENTER_CRITICAL()													\
-{																				\
-extern volatile uint16_t usCriticalNesting;										\
-																				\
-	portDISABLE_INTERRUPTS();													\
-																				\
-	/* Now interrupts are disabled usCriticalNesting can be accessed */			\
-	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
-	/* times portENTER_CRITICAL() has been called. */							\
-	usCriticalNesting++;														\
-}
-
-#define portEXIT_CRITICAL()														\
-{																				\
-extern volatile uint16_t usCriticalNesting;										\
-																				\
-	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
-	{																			\
-		/* Decrement the nesting count as we are leaving a critical section. */	\
-		usCriticalNesting--;													\
-																				\
-		/* If the nesting level has reached zero then interrupts should be */	\
-		/* re-enabled. */														\
-		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
-		{																		\
-			portENABLE_INTERRUPTS();											\
-		}																		\
-	}																			\
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/*
- * Manual context switch called by portYIELD or taskYIELD.
- */
-extern void vPortYield( void );
-#define portYIELD() vPortYield()
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			2
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()					__no_operation()
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR( x ) if( x ) vPortYield()
-
-void vApplicationSetupTimerInterrupt( void );
-
-/* sizeof( int ) != sizeof( long ) so a full printf() library is required if
-run time stats information is to be displayed. */
-#define portLU_PRINTF_SPECIFIER_REQUIRED
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/port.c b/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/port.c
deleted file mode 100755
index 565669e..0000000
--- a/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/port.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-
-#define portINITIAL_FORMAT_VECTOR		( ( StackType_t ) 0x4000 )
-
-/* Supervisor mode set. */
-#define portINITIAL_STATUS_REGISTER		( ( StackType_t ) 0x2000)
-
-/* The clock prescale into the timer peripheral. */
-#define portPRESCALE_VALUE				( ( uint8_t ) 10 )
-
-/* The clock frequency into the RTC. */
-#define portRTC_CLOCK_HZ				( ( uint32_t ) 1000 )
-
-asm void interrupt VectorNumber_VL1swi vPortYieldISR( void );
-static void prvSetupTimerInterrupt( void );
-
-/* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
-will be set to 0 prior to the first task being started. */
-static uint32_t ulCriticalNesting = 0x9999UL;
-
-/*-----------------------------------------------------------*/
-
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-
-uint32_t ulOriginalA5;
-
-	__asm{ MOVE.L A5, ulOriginalA5 };
-
-
-	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
-	pxTopOfStack--;
-
-	/* Exception stack frame starts with the return address. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
-	pxTopOfStack -= 14; /* A5 to D0. */
-
-	/* Parameter in A0. */
-	*( pxTopOfStack + 8 ) = ( StackType_t ) pvParameters;
-
-	/* A5 must be maintained as it is resurved by the compiler. */
-	*( pxTopOfStack + 13 ) = ulOriginalA5;
-
-	return pxTopOfStack;  
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortStartFirstTask( void );
-
-	ulCriticalNesting = 0UL;
-
-	/* Configure a timer to generate the tick interrupt. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task executing. */
-	vPortStartFirstTask();
-
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{				
-	/* Prescale by 1 - ie no prescale. */
-	RTCSC |= 8;
-	
-	/* Compare match value. */
-	RTCMOD = portRTC_CLOCK_HZ / configTICK_RATE_HZ;
-	
-	/* Enable the RTC to generate interrupts - interrupts are already disabled
-	when this code executes. */
-	RTCSC_RTIE = 1;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented as there is nothing to return to. */
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	if( ulCriticalNesting == 0UL )
-	{
-		/* Guard against context switches being pended simultaneously with a
-		critical section being entered. */
-		do
-		{
-			portDISABLE_INTERRUPTS();
-			if( INTC_FRC == 0UL )
-			{
-				break;
-			}
-
-			portENABLE_INTERRUPTS();
-
-		} while( 1 );
-	}
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	ulCriticalNesting--;
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortYieldHandler( void )
-{
-uint32_t ulSavedInterruptMask;
-
-	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Note this will clear all forced interrupts - this is done for speed. */
-		INTC_CFRC = 0x3E;
-		vTaskSwitchContext();
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
-}
-/*-----------------------------------------------------------*/
-
-void interrupt VectorNumber_Vrtc vPortTickISR( void )
-{
-uint32_t ulSavedInterruptMask;
-
-	/* Clear the interrupt. */
-	RTCSC |= RTCSC_RTIF_MASK;
-
-	/* Increment the RTOS tick. */
-	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			taskYIELD();
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
-}
-
diff --git a/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portasm.S b/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portasm.S
deleted file mode 100755
index eaeba54..0000000
--- a/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portasm.S
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * Purpose: Lowest level routines for all ColdFire processors.
- *
- * Notes:
- * 
- * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
- * supplied source files.
- */
-
-    .global ulPortSetIPL
-    .global _ulPortSetIPL
-    .global mcf5xxx_wr_cacrx
-    .global _mcf5xxx_wr_cacrx
-    .global vPortYieldISR
-    .global _vPortYieldISR
-    .global vPortStartFirstTask
-    .global _vPortStartFirstTask
-    .extern _pxCurrentTCB
-    .extern _vPortYieldHandler
-
-    .text
-
-.macro portSAVE_CONTEXT
-
-	lea.l		(-60, sp), sp
-	movem.l		d0-a6, (sp)
-	move.l		_pxCurrentTCB, a0
-	move.l		sp, (a0)
-
-	.endm
-
-.macro portRESTORE_CONTEXT
-
-	move.l		_pxCurrentTCB, a0
-	move.l		(a0), sp
-	movem.l		(sp), d0-a6
-	lea.l		(60, sp), sp
-	rte
-
-	.endm
-
-/********************************************************************/
-/*
- * This routines changes the IPL to the value passed into the routine.
- * It also returns the old IPL value back.
- * Calling convention from C:
- *   old_ipl = asm_set_ipl(new_ipl);
- * For the Diab Data C compiler, it passes return value thru D0.
- * Note that only the least significant three bits of the passed
- * value are used.
- */
-
-ulPortSetIPL:
-_ulPortSetIPL:
-    link    A6,#-8
-    movem.l D6-D7,(SP)
-
-    move.w  SR,D7       /* current sr    */
-
-    move.l  D7,D6       /* prepare return value  */
-    andi.l  #0x0700,D6  /* mask out IPL  */
-    lsr.l   #8,D6       /* IPL   */
-
-    andi.l  #0x07,D0    /* least significant three bits  */
-    lsl.l   #8,D0       /* move over to make mask    */
-
-    andi.l  #0x0000F8FF,D7  /* zero out current IPL  */
-    or.l    D0,D7           /* place new IPL in sr   */
-    move.w  D7,SR
-
-	move.l	D6, D0		/* Return value in D0. */
-    movem.l (SP),D6-D7
-    lea     8(SP),SP
-    unlk    A6
-    rts
-/********************************************************************/
-
-mcf5xxx_wr_cacrx:
-_mcf5xxx_wr_cacrx:
-    move.l  4(sp),d0
-    .long   0x4e7b0002  /* movec d0,cacr   */
-    nop
-    rts
-
-/********************************************************************/
-
-/* Yield interrupt. */
-_vPortYieldISR:
-vPortYieldISR:
-	portSAVE_CONTEXT
-	jsr _vPortYieldHandler
-	portRESTORE_CONTEXT
-
-/********************************************************************/
-
-
-vPortStartFirstTask:
-_vPortStartFirstTask:
-	portRESTORE_CONTEXT
-
-    .end
-
-
diff --git a/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h b/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h
deleted file mode 100755
index 2c557f3..0000000
--- a/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V1/portmacro.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			4
-#define portSTACK_GROWTH			-1
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortSetIPL( uint32_t );
-#define portDISABLE_INTERRUPTS()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portENABLE_INTERRUPTS()		ulPortSetIPL( 0 )
-
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-
-extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
-extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-#define portNOP()	asm volatile ( "nop" )
-
-/* Context switches are requested using the force register. */
-#define portYIELD()	INTC_SFRC = 0x3E; portNOP(); portNOP(); portNOP(); portNOP(); portNOP()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired != pdFALSE )	\
-													{									\
-														portYIELD();					\
-													}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/port.c b/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/port.c
deleted file mode 100755
index 0681eb3..0000000
--- a/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/port.c
+++ /dev/null
@@ -1,147 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-
-#define portINITIAL_FORMAT_VECTOR		( ( StackType_t ) 0x4000 )
-
-/* Supervisor mode set. */
-#define portINITIAL_STATUS_REGISTER		( ( StackType_t ) 0x2000)
-
-/* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
-will be set to 0 prior to the first task being started. */
-static uint32_t ulCriticalNesting = 0x9999UL;
-
-
-#define portSAVE_CONTEXT()				\
-	lea.l		(-60, %sp), %sp;		\
-	movem.l		%d0-%fp, (%sp);			\
-	move.l		pxCurrentTCB, %a0;		\
-	move.l		%sp, (%a0);
-
-#define portRESTORE_CONTEXT()			\
-	move.l		pxCurrentTCB, %a0;		\
-	move.l		(%a0), %sp;				\
-	movem.l		(%sp), %d0-%fp;			\
-	lea.l		%sp@(60), %sp;			\
-	rte
-
-
-
-/*-----------------------------------------------------------*/
-
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	*pxTopOfStack = ( StackType_t ) pvParameters;
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
-	pxTopOfStack--;
-
-	/* Exception stack frame starts with the return address. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
-	pxTopOfStack -= 14; /* A5 to D0. */
-
-    return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortStartFirstTask( void );
-
-	ulCriticalNesting = 0UL;
-
-	/* Configure the interrupts used by this port. */
-	vApplicationSetupInterrupts();
-
-	/* Start the first task executing. */
-	vPortStartFirstTask();
-
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented as there is nothing to return to. */
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	if( ulCriticalNesting == 0UL )
-	{
-		/* Guard against context switches being pended simultaneously with a
-		critical section being entered. */
-		do
-		{
-			portDISABLE_INTERRUPTS();
-			if( MCF_INTC0_INTFRCH == 0UL )
-			{
-				break;
-			}
-
-			portENABLE_INTERRUPTS();
-
-		} while( 1 );
-	}
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	ulCriticalNesting--;
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortYieldHandler( void )
-{
-uint32_t ulSavedInterruptMask;
-
-	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
-		/* Note this will clear all forced interrupts - this is done for speed. */
-		MCF_INTC0_INTFRCL = 0;
-		vTaskSwitchContext();
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portasm.S b/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portasm.S
deleted file mode 100755
index 55627c6..0000000
--- a/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portasm.S
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * Purpose: Lowest level routines for all ColdFire processors.
- *
- * Notes:
- * 
- * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
- * supplied source files.
- */
-
-    .global ulPortSetIPL
-    .global _ulPortSetIPL
-    .global mcf5xxx_wr_cacrx
-    .global _mcf5xxx_wr_cacrx
-    .global vPortYieldISR
-    .global _vPortYieldISR
-    .global vPortStartFirstTask
-    .global _vPortStartFirstTask
-    .extern _pxCurrentTCB
-    .extern _vPortYieldHandler
-
-    .text
-
-.macro portSAVE_CONTEXT
-
-	lea.l		(-60, sp), sp
-	movem.l		d0-a6, (sp)
-	move.l		_pxCurrentTCB, a0
-	move.l		sp, (a0)
-
-	.endm
-
-.macro portRESTORE_CONTEXT
-
-	move.l		_pxCurrentTCB, a0
-	move.l		(a0), sp
-	movem.l		(sp), d0-a6
-	lea.l		(60, sp), sp
-	rte
-
-	.endm
-
-/********************************************************************/
-/*
- * This routines changes the IPL to the value passed into the routine.
- * It also returns the old IPL value back.
- * Calling convention from C:
- *   old_ipl = asm_set_ipl(new_ipl);
- * For the Diab Data C compiler, it passes return value thru D0.
- * Note that only the least significant three bits of the passed
- * value are used.
- */
-
-ulPortSetIPL:
-_ulPortSetIPL:
-    link    A6,#-8
-    movem.l D6-D7,(SP)
-
-    move.w  SR,D7       /* current sr    */
-
-    move.l  D7,D0       /* prepare return value  */
-    andi.l  #0x0700,D0  /* mask out IPL  */
-    lsr.l   #8,D0       /* IPL   */
-
-    move.l  8(A6),D6    /* get argument  */
-    andi.l  #0x07,D6    /* least significant three bits  */
-    lsl.l   #8,D6       /* move over to make mask    */
-
-    andi.l  #0x0000F8FF,D7  /* zero out current IPL  */
-    or.l    D6,D7           /* place new IPL in sr   */
-    move.w  D7,SR
-
-    movem.l (SP),D6-D7
-    lea     8(SP),SP
-    unlk    A6
-    rts
-/********************************************************************/
-
-mcf5xxx_wr_cacrx:
-_mcf5xxx_wr_cacrx:
-    move.l  4(sp),d0
-    .long   0x4e7b0002  /* movec d0,cacr   */
-    nop
-    rts
-
-/********************************************************************/
-
-/* Yield interrupt. */
-_vPortYieldISR:
-vPortYieldISR:
-	portSAVE_CONTEXT
-	jsr _vPortYieldHandler
-	portRESTORE_CONTEXT
-
-/********************************************************************/
-
-
-vPortStartFirstTask:
-_vPortStartFirstTask:
-	portRESTORE_CONTEXT
-
-    .end
-
-
diff --git a/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h b/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h
deleted file mode 100755
index 9dc4bb8..0000000
--- a/FreeRTOS/Source/portable/CodeWarrior/ColdFire_V2/portmacro.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			4
-#define portSTACK_GROWTH			-1
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-uint32_t ulPortSetIPL( uint32_t );
-#define portDISABLE_INTERRUPTS()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portENABLE_INTERRUPTS()		ulPortSetIPL( 0 )
-
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-
-extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
-extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-#define portNOP()	asm volatile ( 	"nop" )
-
-/* Note this will overwrite all other bits in the force register, it is done this way for speed. */
-#define portYIELD()			MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP() /* -32 as we are using the high word of the 64bit mask. */
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired != pdFALSE )	\
-													{									\
-														portYIELD();					\
-													}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/CodeWarrior/HCS12/port.c b/FreeRTOS/Source/portable/CodeWarrior/HCS12/port.c
deleted file mode 100755
index eafd5a0..0000000
--- a/FreeRTOS/Source/portable/CodeWarrior/HCS12/port.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the HCS12 port.
- *----------------------------------------------------------*/
-
-
-/*
- * Configure a timer to generate the RTOS tick at the frequency specified 
- * within FreeRTOSConfig.h.
- */
-static void prvSetupTimerInterrupt( void );
-
-/* Interrupt service routines have to be in non-banked memory - as does the
-scheduler startup function. */
-#pragma CODE_SEG __NEAR_SEG NON_BANKED
-
-	/* Manual context switch function.  This is the SWI ISR. */
-	void interrupt vPortYield( void );
-
-	/* Tick context switch function.  This is the timer ISR. */
-	void interrupt vPortTickInterrupt( void );
-	
-	/* Simply called by xPortStartScheduler().  xPortStartScheduler() does not
-	start the scheduler directly because the header file containing the 
-	xPortStartScheduler() prototype is part of the common kernel code, and 
-	therefore cannot use the CODE_SEG pragma. */
-	static BaseType_t xBankedStartScheduler( void );
-
-#pragma CODE_SEG DEFAULT
-
-/* Calls to portENTER_CRITICAL() can be nested.  When they are nested the 
-critical section should not be left (i.e. interrupts should not be re-enabled)
-until the nesting depth reaches 0.  This variable simply tracks the nesting 
-depth.  Each task maintains it's own critical nesting depth variable so 
-uxCriticalNesting is saved and restored from the task stack during a context
-switch. */
-volatile UBaseType_t uxCriticalNesting = 0xff;
-
-/*-----------------------------------------------------------*/
-
-/* 
- * See header file for description. 
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* 
-		Place a few bytes of known values on the bottom of the stack.
-		This can be uncommented to provide useful stack markers when debugging.
-
-		*pxTopOfStack = ( StackType_t ) 0x11;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x22;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x33;
-		pxTopOfStack--;
-	*/
-
-
-
-	/* Setup the initial stack of the task.  The stack is set exactly as 
-	expected by the portRESTORE_CONTEXT() macro.  In this case the stack as
-	expected by the HCS12 RTI instruction. */
-
-
-	/* The address of the task function is placed in the stack byte at a time. */
-	*pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
-	pxTopOfStack--;
-
-	/* Next are all the registers that form part of the task context. */
-
-	/* Y register */
-	*pxTopOfStack = ( StackType_t ) 0xff;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xee;
-	pxTopOfStack--;
-
-	/* X register */
-	*pxTopOfStack = ( StackType_t ) 0xdd;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xcc;
-	pxTopOfStack--;
- 
-	/* A register contains parameter high byte. */
-	*pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
-	pxTopOfStack--;
-
-	/* B register contains parameter low byte. */
-	*pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
-	pxTopOfStack--;
-
-	/* CCR: Note that when the task starts interrupts will be enabled since
-	"I" bit of CCR is cleared */
-	*pxTopOfStack = ( StackType_t ) 0x00;
-	pxTopOfStack--;
-	
-	#ifdef BANKED_MODEL
-		/* The page of the task. */
-		*pxTopOfStack = ( StackType_t ) ( ( int ) pxCode );
-		pxTopOfStack--;
-	#endif
-	
-	/* Finally the critical nesting depth is initialised with 0 (not within
-	a critical section). */
-	*pxTopOfStack = ( StackType_t ) 0x00;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the HCS12 port will get stopped. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-	TickTimer_SetFreqHz( configTICK_RATE_HZ );
-	TickTimer_Enable();
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* xPortStartScheduler() does not start the scheduler directly because 
-	the header file containing the xPortStartScheduler() prototype is part 
-	of the common kernel code, and therefore cannot use the CODE_SEG pragma. 
-	Instead it simply calls the locally defined xBankedStartScheduler() - 
-	which does use the CODE_SEG pragma. */
-
-	return xBankedStartScheduler();
-}
-/*-----------------------------------------------------------*/
-
-#pragma CODE_SEG __NEAR_SEG NON_BANKED
-
-static BaseType_t xBankedStartScheduler( void )
-{
-	/* Configure the timer that will generate the RTOS tick.  Interrupts are
-	disabled when this function is called. */
-	prvSetupTimerInterrupt();
-
-	/* Restore the context of the first task. */
-	portRESTORE_CONTEXT();
-
-	/* Simulate the end of an interrupt to start the scheduler off. */
-	__asm( "rti" );
-
-	/* Should not get here! */
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Context switch functions.  These are both interrupt service routines.
- */
-
-/*
- * Manual context switch forced by calling portYIELD().  This is the SWI
- * handler.
- */
-void interrupt vPortYield( void )
-{
-	portSAVE_CONTEXT();
-	vTaskSwitchContext();
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * RTOS tick interrupt service routine.  If the cooperative scheduler is 
- * being used then this simply increments the tick count.  If the 
- * preemptive scheduler is being used a context switch can occur.
- */
-void interrupt vPortTickInterrupt( void )
-{
-	#if configUSE_PREEMPTION == 1
-	{
-		/* A context switch might happen so save the context. */
-		portSAVE_CONTEXT();
-
-		/* Increment the tick ... */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			vTaskSwitchContext();
-		}
-
-		TFLG1 = 1;								   
-
-		/* Restore the context of a task - which may be a different task
-		to that interrupted. */
-		portRESTORE_CONTEXT();	
-	}
-	#else
-	{
-		xTaskIncrementTick();
-		TFLG1 = 1;
-	}
-	#endif
-}
-
-#pragma CODE_SEG DEFAULT
-
-
diff --git a/FreeRTOS/Source/portable/CodeWarrior/HCS12/portmacro.h b/FreeRTOS/Source/portable/CodeWarrior/HCS12/portmacro.h
deleted file mode 100755
index b8832f3..0000000
--- a/FreeRTOS/Source/portable/CodeWarrior/HCS12/portmacro.h
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint8_t
-#define portBASE_TYPE	char
-
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			1
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portYIELD()					__asm( "swi" );
-#define portNOP()					__asm( "nop" );
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-#define portENABLE_INTERRUPTS()				__asm( "cli" )
-#define portDISABLE_INTERRUPTS()			__asm( "sei" )
-
-/*
- * Disable interrupts before incrementing the count of critical section nesting.
- * The nesting count is maintained so we know when interrupts should be
- * re-enabled.  Once interrupts are disabled the nesting count can be accessed
- * directly.  Each task maintains its own nesting count.
- */
-#define portENTER_CRITICAL()  									\
-{																\
-	extern volatile UBaseType_t uxCriticalNesting;	\
-																\
-	portDISABLE_INTERRUPTS();									\
-	uxCriticalNesting++;										\
-}
-
-/*
- * Interrupts are disabled so we can access the nesting count directly.  If the
- * nesting is found to be 0 (no nesting) then we are leaving the critical
- * section and interrupts can be re-enabled.
- */
-#define  portEXIT_CRITICAL()									\
-{																\
-	extern volatile UBaseType_t uxCriticalNesting;	\
-																\
-	uxCriticalNesting--;										\
-	if( uxCriticalNesting == 0 )								\
-	{															\
-		portENABLE_INTERRUPTS();								\
-	}															\
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/*
- * These macros are very simple as the processor automatically saves and
- * restores its registers as interrupts are entered and exited.  In
- * addition to the (automatically stacked) registers we also stack the
- * critical nesting count.  Each task maintains its own critical nesting
- * count as it is legitimate for a task to yield from within a critical
- * section.  If the banked memory model is being used then the PPAGE
- * register is also stored as part of the tasks context.
- */
-
-#ifdef BANKED_MODEL
-	/*
-	 * Load the stack pointer for the task, then pull the critical nesting
-	 * count and PPAGE register from the stack.  The remains of the
-	 * context are restored by the RTI instruction.
-	 */
-	#define portRESTORE_CONTEXT()									\
-	{																\
-		extern volatile void * pxCurrentTCB;						\
-		extern volatile UBaseType_t uxCriticalNesting;	\
-																	\
-		__asm( "ldx pxCurrentTCB" );								\
-		__asm( "lds 0, x" );										\
-		__asm( "pula" );											\
-		__asm( "staa uxCriticalNesting" );							\
-		__asm( "pula" );											\
-		__asm( "staa 0x30" ); /* 0x30 = PPAGE */					\
-	}
-
-	/*
-	 * By the time this macro is called the processor has already stacked the
-	 * registers.  Simply stack the nesting count and PPAGE value, then save
-	 * the task stack pointer.
-	 */
-	#define portSAVE_CONTEXT()										\
-	{																\
-		extern volatile void * pxCurrentTCB;						\
-		extern volatile UBaseType_t uxCriticalNesting;	\
-																	\
-		__asm( "ldaa 0x30" );  /* 0x30 = PPAGE */					\
-		__asm( "psha" );											\
-		__asm( "ldaa uxCriticalNesting" );							\
-		__asm( "psha" );											\
-		__asm( "ldx pxCurrentTCB" );								\
-		__asm( "sts 0, x" );										\
-	}
-#else
-
-	/*
-	 * These macros are as per the BANKED versions above, but without saving
-	 * and restoring the PPAGE register.
-	 */
-
-	#define portRESTORE_CONTEXT()									\
-	{																\
-		extern volatile void * pxCurrentTCB;						\
-		extern volatile UBaseType_t uxCriticalNesting;	\
-																	\
-		__asm( "ldx pxCurrentTCB" );								\
-		__asm( "lds 0, x" );										\
-		__asm( "pula" );											\
-		__asm( "staa uxCriticalNesting" );							\
-	}
-
-	#define portSAVE_CONTEXT()										\
-	{																\
-		extern volatile void * pxCurrentTCB;						\
-		extern volatile UBaseType_t uxCriticalNesting;	\
-																	\
-		__asm( "ldaa uxCriticalNesting" );							\
-		__asm( "psha" );											\
-		__asm( "ldx pxCurrentTCB" );								\
-		__asm( "sts 0, x" );										\
-	}
-#endif
-
-/*
- * Utility macro to call macros above in correct order in order to perform a
- * task switch from within a standard ISR.  This macro can only be used if
- * the ISR does not use any local (stack) variables.  If the ISR uses stack
- * variables portYIELD() should be used in it's place.
- */
-#define portTASK_SWITCH_FROM_ISR()								\
-	portSAVE_CONTEXT();											\
-	vTaskSwitchContext();										\
-	portRESTORE_CONTEXT();
-
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/Common/mpu_wrappers.c b/FreeRTOS/Source/portable/Common/mpu_wrappers.c
deleted file mode 100755
index 8b3ff27..0000000
--- a/FreeRTOS/Source/portable/Common/mpu_wrappers.c
+++ /dev/null
@@ -1,1337 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * Implementation of the wrapper functions used to raise the processor privilege
- * before calling a standard FreeRTOS API function.
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-#include "timers.h"
-#include "event_groups.h"
-#include "stream_buffer.h"
-#include "mpu_prototypes.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * @brief Calls the port specific code to raise the privilege.
- *
- * @return pdFALSE if privilege was raised, pdTRUE otherwise.
- */
-BaseType_t xPortRaisePrivilege( void ) FREERTOS_SYSTEM_CALL;
-
-/**
- * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
- * code to reset the privilege, otherwise does nothing.
- */
-void vPortResetPrivilege( BaseType_t xRunningPrivileged );
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortRaisePrivilege( void ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged;
-
-	/* Check whether the processor is already privileged. */
-	xRunningPrivileged = portIS_PRIVILEGED();
-
-	/* If the processor is not already privileged, raise privilege. */
-	if( xRunningPrivileged != pdTRUE )
-	{
-		portRAISE_PRIVILEGE();
-	}
-
-	return xRunningPrivileged;
-}
-/*-----------------------------------------------------------*/
-
-void vPortResetPrivilege( BaseType_t xRunningPrivileged )
-{
-	if( xRunningPrivileged != pdTRUE )
-	{
-		portRESET_PRIVILEGE();
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskCreateRestricted( pxTaskDefinition, pxCreatedTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif /* conifgSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	BaseType_t MPU_xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskCreateRestrictedStatic( pxTaskDefinition, pxCreatedTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif /* conifgSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	BaseType_t MPU_xTaskCreate( TaskFunction_t pvTaskCode, const char * const pcName, uint16_t usStackDepth, void *pvParameters, UBaseType_t uxPriority, TaskHandle_t *pxCreatedTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskCreate( pvTaskCode, pcName, usStackDepth, pvParameters, uxPriority, pxCreatedTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TaskHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskCreateStatic( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, puxStackBuffer, pxTaskBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const xRegions ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	vTaskAllocateMPURegions( xTask, xRegions );
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelete == 1 )
-	void MPU_vTaskDelete( TaskHandle_t pxTaskToDelete ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskDelete( pxTaskToDelete );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelayUntil == 1 )
-	void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, TickType_t xTimeIncrement ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskDelayUntil( pxPreviousWakeTime, xTimeIncrement );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskAbortDelay == 1 )
-	BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskAbortDelay( xTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelay == 1 )
-	void MPU_vTaskDelay( TickType_t xTicksToDelay ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskDelay( xTicksToDelay );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
-	UBaseType_t MPU_uxTaskPriorityGet( const TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	UBaseType_t uxReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		uxReturn = uxTaskPriorityGet( pxTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return uxReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskPrioritySet == 1 )
-	void MPU_vTaskPrioritySet( TaskHandle_t pxTask, UBaseType_t uxNewPriority ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskPrioritySet( pxTask, uxNewPriority );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_eTaskGetState == 1 )
-	eTaskState MPU_eTaskGetState( TaskHandle_t pxTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-	eTaskState eReturn;
-
-		eReturn = eTaskGetState( pxTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return eReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TRACE_FACILITY == 1 )
-	void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskGetInfo( xTask, pxTaskStatus, xGetFreeStackSpace, eState );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
-	TaskHandle_t MPU_xTaskGetIdleTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TaskHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGetIdleTaskHandle();
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-	void MPU_vTaskSuspend( TaskHandle_t pxTaskToSuspend ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskSuspend( pxTaskToSuspend );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-	void MPU_vTaskResume( TaskHandle_t pxTaskToResume ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskResume( pxTaskToResume );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-void MPU_vTaskSuspendAll( void ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	vTaskSuspendAll();
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xTaskResumeAll( void ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xTaskResumeAll();
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-TickType_t MPU_xTaskGetTickCount( void ) /* FREERTOS_SYSTEM_CALL */
-{
-TickType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xTaskGetTickCount();
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t MPU_uxTaskGetNumberOfTasks( void ) /* FREERTOS_SYSTEM_CALL */
-{
-UBaseType_t uxReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	uxReturn = uxTaskGetNumberOfTasks();
-	vPortResetPrivilege( xRunningPrivileged );
-	return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery ) /* FREERTOS_SYSTEM_CALL */
-{
-char *pcReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	pcReturn = pcTaskGetName( xTaskToQuery );
-	vPortResetPrivilege( xRunningPrivileged );
-	return pcReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetHandle == 1 )
-	TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TaskHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGetHandle( pcNameToQuery );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	void MPU_vTaskList( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskList( pcWriteBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskGetRunTimeStats( pcWriteBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
-	TickType_t MPU_xTaskGetIdleRunTimeCounter( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TickType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGetIdleRunTimeCounter();
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-	void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxTagValue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskSetApplicationTaskTag( xTask, pxTagValue );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-	TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TaskHookFunction_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGetApplicationTaskTag( xTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-	void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTaskSetThreadLocalStoragePointer( xTaskToSet, xIndex, pvValue );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-	void *MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) /* FREERTOS_SYSTEM_CALL */
-	{
-	void *pvReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		pvReturn = pvTaskGetThreadLocalStoragePointer( xTaskToQuery, xIndex );
-		vPortResetPrivilege( xRunningPrivileged );
-		return pvReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-	BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskCallApplicationTaskHook( xTask, pvParameter );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-	UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t *pxTaskStatusArray, UBaseType_t uxArraySize, uint32_t *pulTotalRunTime ) /* FREERTOS_SYSTEM_CALL */
-	{
-	UBaseType_t uxReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		uxReturn = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, pulTotalRunTime );
-		vPortResetPrivilege( xRunningPrivileged );
-		return uxReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
-	UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	UBaseType_t uxReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		uxReturn = uxTaskGetStackHighWaterMark( xTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return uxReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
-	configSTACK_DEPTH_TYPE MPU_uxTaskGetStackHighWaterMark2( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	configSTACK_DEPTH_TYPE uxReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		uxReturn = uxTaskGetStackHighWaterMark2( xTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return uxReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetCurrentTaskHandle == 1 )
-	TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TaskHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGetCurrentTaskHandle();
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetSchedulerState == 1 )
-	BaseType_t MPU_xTaskGetSchedulerState( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGetSchedulerState();
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	vTaskSetTimeOutState( pxTimeOut );
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xTaskCheckForTimeOut( pxTimeOut, pxTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-	BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskGenericNotify( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-	BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskNotifyWait( ulBitsToClearOnEntry, ulBitsToClearOnExit, pulNotificationValue, xTicksToWait );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-	uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-	{
-	uint32_t ulReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		ulReturn = ulTaskNotifyTake( xClearCountOnExit, xTicksToWait );
-		vPortResetPrivilege( xRunningPrivileged );
-		return ulReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-	BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTaskNotifyStateClear( xTask );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	QueueHandle_t MPU_xQueueGenericCreate( UBaseType_t uxQueueLength, UBaseType_t uxItemSize, uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueGenericCreate( uxQueueLength, uxItemSize, ucQueueType );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueGenericCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxStaticQueue, ucQueueType );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueGenericReset( QueueHandle_t pxQueue, BaseType_t xNewQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xQueueGenericReset( pxQueue, xNewQueue );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, BaseType_t xCopyPosition ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xQueueGenericSend( xQueue, pvItemToQueue, xTicksToWait, xCopyPosition );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t pxQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-UBaseType_t uxReturn;
-
-	uxReturn = uxQueueMessagesWaiting( pxQueue );
-	vPortResetPrivilege( xRunningPrivileged );
-	return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-UBaseType_t uxReturn;
-
-	uxReturn = uxQueueSpacesAvailable( xQueue );
-	vPortResetPrivilege( xRunningPrivileged );
-	return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueReceive( QueueHandle_t pxQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-BaseType_t xReturn;
-
-	xReturn = xQueueReceive( pxQueue, pvBuffer, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-BaseType_t xReturn;
-
-	xReturn = xQueuePeek( xQueue, pvBuffer, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-BaseType_t xReturn;
-
-	xReturn = xQueueSemaphoreTake( xQueue, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
-	TaskHandle_t MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-	void * xReturn;
-
-		xReturn = xQueueGetMutexHolder( xSemaphore );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueCreateMutex( ucQueueType );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-	QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueCreateMutexStatic( ucQueueType, pxStaticQueue );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	QueueHandle_t MPU_xQueueCreateCountingSemaphore( UBaseType_t uxCountValue, UBaseType_t uxInitialCount ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueCreateCountingSemaphore( uxCountValue, uxInitialCount );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
-	QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueCreateCountingSemaphoreStatic( uxMaxCount, uxInitialCount, pxStaticQueue );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-	BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xBlockTime ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueTakeMutexRecursive( xMutex, xBlockTime );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-	BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t xMutex ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueGiveMutexRecursive( xMutex );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-	QueueSetHandle_t MPU_xQueueCreateSet( UBaseType_t uxEventQueueLength ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueSetHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueCreateSet( uxEventQueueLength );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-	QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t xBlockTimeTicks ) /* FREERTOS_SYSTEM_CALL */
-	{
-	QueueSetMemberHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueSelectFromSet( xQueueSet, xBlockTimeTicks );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-	BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueAddToSet( xQueueOrSemaphore, xQueueSet );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-	BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xQueueRemoveFromSet( xQueueOrSemaphore, xQueueSet );
-		vPortResetPrivilege( xRunningPrivileged );
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if configQUEUE_REGISTRY_SIZE > 0
-	void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vQueueAddToRegistry( xQueue, pcName );
-
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if configQUEUE_REGISTRY_SIZE > 0
-	void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vQueueUnregisterQueue( xQueue );
-
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if configQUEUE_REGISTRY_SIZE > 0
-	const char *MPU_pcQueueGetName( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-	const char *pcReturn;
-
-		pcReturn = pcQueueGetName( xQueue );
-
-		vPortResetPrivilege( xRunningPrivileged );
-		return pcReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-void MPU_vQueueDelete( QueueHandle_t xQueue ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	vQueueDelete( xQueue );
-
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	void *MPU_pvPortMalloc( size_t xSize ) /* FREERTOS_SYSTEM_CALL */
-	{
-	void *pvReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		pvReturn = pvPortMalloc( xSize );
-
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return pvReturn;
-	}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	void MPU_vPortFree( void *pv ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vPortFree( pv );
-
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	void MPU_vPortInitialiseBlocks( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vPortInitialiseBlocks();
-
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	size_t MPU_xPortGetFreeHeapSize( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	size_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xPortGetFreeHeapSize();
-
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
-	TimerHandle_t MPU_xTimerCreate( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TimerHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerCreate( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_TIMERS == 1 ) )
-	TimerHandle_t MPU_xTimerCreateStatic( const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TimerHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerCreateStatic( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxTimerBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	void *MPU_pvTimerGetTimerID( const TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	void * pvReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		pvReturn = pvTimerGetTimerID( xTimer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return pvReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTimerSetTimerID( xTimer, pvNewID );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerIsTimerActive( xTimer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TaskHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerGetTimerDaemonTaskHandle();
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
-	BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerPendFunctionCall( xFunctionToPend, pvParameter1, ulParameter2, xTicksToWait );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	void MPU_vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		vTimerSetReloadMode( xTimer, uxAutoReload );
-		vPortResetPrivilege( xRunningPrivileged );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	const char * MPU_pcTimerGetName( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	const char * pcReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		pcReturn = pcTimerGetName( xTimer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return pcReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TickType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerGetPeriod( xTimer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	TickType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerGetExpiryTime( xTimer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-	BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-	{
-	BaseType_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xTimerGenericCommand( xTimer, xCommandID, xOptionalValue, pxHigherPriorityTaskWoken, xTicksToWait );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	EventGroupHandle_t MPU_xEventGroupCreate( void ) /* FREERTOS_SYSTEM_CALL */
-	{
-	EventGroupHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xEventGroupCreate();
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	EventGroupHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xEventGroupCreateStatic( pxEventGroupBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-EventBits_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xEventGroupWaitBits( xEventGroup, uxBitsToWaitFor, xClearOnExit, xWaitForAllBits, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) /* FREERTOS_SYSTEM_CALL */
-{
-EventBits_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xEventGroupClearBits( xEventGroup, uxBitsToClear );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) /* FREERTOS_SYSTEM_CALL */
-{
-EventBits_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xEventGroupSetBits( xEventGroup, uxBitsToSet );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-EventBits_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xEventGroupSync( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	vEventGroupDelete( xEventGroup );
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferSend( StreamBufferHandle_t xStreamBuffer, const void *pvTxData, size_t xDataLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-size_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferSend( xStreamBuffer, pvTxData, xDataLengthBytes, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-size_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferNextMessageLengthBytes( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer, void *pvRxData, size_t xBufferLengthBytes, TickType_t xTicksToWait ) /* FREERTOS_SYSTEM_CALL */
-{
-size_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferReceive( xStreamBuffer, pvRxData, xBufferLengthBytes, xTicksToWait );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void MPU_vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	vStreamBufferDelete( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferIsFull( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferIsEmpty( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferReset( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferReset( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-size_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferSpacesAvailable( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t MPU_xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-{
-size_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferBytesAvailable( xStreamBuffer );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t MPU_xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel ) /* FREERTOS_SYSTEM_CALL */
-{
-BaseType_t xReturn;
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	xReturn = xStreamBufferSetTriggerLevel( xStreamBuffer, xTriggerLevel );
-	vPortResetPrivilege( xRunningPrivileged );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-	StreamBufferHandle_t MPU_xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	StreamBufferHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xStreamBufferGenericCreate( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	StreamBufferHandle_t MPU_xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer, uint8_t * const pucStreamBufferStorageArea, StaticStreamBuffer_t * const pxStaticStreamBuffer ) /* FREERTOS_SYSTEM_CALL */
-	{
-	StreamBufferHandle_t xReturn;
-	BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-		xReturn = xStreamBufferGenericCreateStatic( xBufferSizeBytes, xTriggerLevelBytes, xIsMessageBuffer, pucStreamBufferStorageArea, pxStaticStreamBuffer );
-		vPortResetPrivilege( xRunningPrivileged );
-
-		return xReturn;
-	}
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-
-/* Functions that the application writer wants to execute in privileged mode
-can be defined in application_defined_privileged_functions.h.  The functions
-must take the same format as those above whereby the privilege state on exit
-equals the privilege state on entry.  For example:
-
-void MPU_FunctionName( [parameters ] )
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	FunctionName( [parameters ] );
-
-	vPortResetPrivilege( xRunningPrivileged );
-}
-*/
-
-#if configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS == 1
-	#include "application_defined_privileged_functions.h"
-#endif
diff --git a/FreeRTOS/Source/portable/Compiler/Arch/port.c b/FreeRTOS/Source/portable/Compiler/Arch/port.c
deleted file mode 100755
index 7320ba4..0000000
--- a/FreeRTOS/Source/portable/Compiler/Arch/port.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
-FreeRTOS Kernel V10.2.1
-Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-the Software, and to permit persons to whom the Software is furnished to do so,
-subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
- http://aws.amazon.com/freertos
- http://www.FreeRTOS.org
-*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	( void ) pxTopOfStack;
-	( void ) pxCode;
-	( void ) pvParameters;
-
-	/* FIX ME. */
-	return ( StackType_t * ) NULL;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* FIX ME. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Do not implement. */
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/Compiler/Arch/portmacro.h b/FreeRTOS/Source/portable/Compiler/Arch/portmacro.h
deleted file mode 100755
index 3c8b1e3..0000000
--- a/FreeRTOS/Source/portable/Compiler/Arch/portmacro.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
-FreeRTOS Kernel V10.2.1
-Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-
-Permission is hereby granted, free of charge, to any person obtaining a copy of
-this software and associated documentation files (the "Software"), to deal in
-the Software without restriction, including without limitation the rights to
-use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-the Software, and to permit persons to whom the Software is furnished to do so,
-subject to the following conditions:
-
-The above copyright notice and this permission notice shall be included in all
-copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
- http://aws.amazon.com/freertos
- http://www.FreeRTOS.org
-*/
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Type definitions. */
-#define portSTACK_TYPE	uint32_t
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8 /* FIX ME. */
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD() 	0 /* FIX ME. */
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) 0 /* FIX ME. */
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) 0 /* FIX ME. */
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = 0 /* FIX ME. */
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-#define portSET_INTERRUPT_MASK_FROM_ISR()		0 /* FIX ME. */
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	0 /* FIX ME. */
-#define portDISABLE_INTERRUPTS()				0 /* FIX ME. */
-#define portENABLE_INTERRUPTS()					0 /* FIX ME. */
-#define portENTER_CRITICAL()					0 /* FIX ME. */
-#define portEXIT_CRITICAL()						0 /* FIX ME. */
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/port.c b/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/port.c
deleted file mode 100755
index 17e74b2..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/port.c
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Atmel AT91R40008
- * port.
- *
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in this file.  The ISR routines, which can only be compiled
- * to ARM mode are contained in portISR.c.
- *----------------------------------------------------------*/
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Hardware specific definitions. */
-#include "AT91R40008.h"
-#include "pio.h"
-#include "aic.h"
-#include "tc.h"
-
-/* Constants required to setup the task context. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
-#define portTICK_PRIORITY_6				( 6 )
-/*-----------------------------------------------------------*/
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/* 
- * The scheduler can only be started from ARM mode, so 
- * vPortISRStartFirstSTask() is defined in portISR.c. 
- */
-extern void vPortISRStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/* 
- * Initialise the stack of a task to look exactly as if a call to 
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description. 
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
-	pxOriginalTOS = pxTopOfStack;
-	
-	/* To ensure asserts in tasks.c don't fail, although in this case the assert
-	is not really required. */
-	pxTopOfStack--;
-
-	/* Setup the initial stack of the task.  The stack is set exactly as 
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* First on the stack is the return address - which in this case is the
-	start of the task.  The offset is added to make the return address appear
-	as it would within an IRQ ISR. */
-	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;	
-
-	/* When the task starts is will expect to find the function parameter in
-	R0. */
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The last thing onto the stack is the status register, which is set for
-	system mode, with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	#ifdef THUMB_INTERWORK
-	{
-		/* We want the task to start in thumb mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-	#endif
-
-	pxTopOfStack--;
-
-	/* Some optimisation levels use the stack differently to others.  This 
-	means the interrupt flags cannot always be stored on the stack and will
-	instead be stored in a variable, which is then saved as part of the
-	tasks context. */
-	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task. */
-	vPortISRStartFirstTask();	
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the ARM port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the tick timer to generate the tick interrupts at the required frequency.
- */
-static void prvSetupTimerInterrupt( void )
-{
-volatile uint32_t ulDummy;
-
-	/* Enable clock to the tick timer... */
-	AT91C_BASE_PS->PS_PCER = portTIMER_CLK_ENABLE_BIT;
-
-	/* Stop the tick timer... */
-	portTIMER_REG_BASE_PTR->TC_CCR = TC_CLKDIS;
-
-	/* Start with tick timer interrupts disabled... */
-	portTIMER_REG_BASE_PTR->TC_IDR = 0xFFFFFFFF;
-
-	/* Clear any pending tick timer interrupts... */
-	ulDummy = portTIMER_REG_BASE_PTR->TC_SR;
-
-	/* Store interrupt handler function address in tick timer vector register...
-	The ISR installed depends on whether the preemptive or cooperative
-	scheduler is being used. */
-	#if configUSE_PREEMPTION == 1
-	{
-		extern void ( vPreemptiveTick )( void );
-		AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vPreemptiveTick;
-	}
-	#else  // else use cooperative scheduler
-	{
-		extern void ( vNonPreemptiveTick )( void );
-		AT91C_BASE_AIC->AIC_SVR[portTIMER_AIC_CHANNEL] = ( uint32_t ) vNonPreemptiveTick;
-	}
-	#endif
-
-	/* Tick timer interrupt level-sensitive, priority 6... */
-	AT91C_BASE_AIC->AIC_SMR[ portTIMER_AIC_CHANNEL ] = AIC_SRCTYPE_INT_LEVEL_SENSITIVE | portTICK_PRIORITY_6;
-
-	/* Enable the tick timer interrupt...
-
-	First at timer level */
-	portTIMER_REG_BASE_PTR->TC_IER = TC_CPCS;
-
-	/* Then at the AIC level. */
-	AT91C_BASE_AIC->AIC_IECR = (1 << portTIMER_AIC_CHANNEL);
-
-	/* Calculate timer compare value to achieve the desired tick rate... */
-	if( (configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2) ) <= 0xFFFF )
-	{
-		/* The tick rate is fast enough for us to use the faster timer input
-		clock (main clock / 2). */
-		portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK2 | TC_BURST_NONE | TC_CPCTRG;
-		portTIMER_REG_BASE_PTR->TC_RC  = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 2);
-	}
-	else
-	{
-		/* We must use a slower timer input clock (main clock / 8) because the
-		tick rate is too slow for the faster input clock. */
-		portTIMER_REG_BASE_PTR->TC_CMR = TC_WAVE | TC_CLKS_MCK8 | TC_BURST_NONE | TC_CPCTRG;
-		portTIMER_REG_BASE_PTR->TC_RC  = configCPU_CLOCK_HZ / (configTICK_RATE_HZ * 8);
-	}
-
-	/* Start tick timer... */
-	portTIMER_REG_BASE_PTR->TC_CCR = TC_SWTRG | TC_CLKEN;
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portISR.c b/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portISR.c
deleted file mode 100755
index 960d9ea..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portISR.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c  The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
-
-/*
-	Changes from V3.2.4
-
-	+ The assembler statements are now included in a single asm block rather
-	  than each line having its own asm block.
-*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to handle interrupts. */
-#define portCLEAR_AIC_INTERRUPT		( ( uint32_t ) 0 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/*-----------------------------------------------------------*/
-
-/* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
-
-/* 
- * The scheduler can only be started from ARM mode, hence the inclusion of this
- * function here.
- */
-void vPortISRStartFirstTask( void );
-/*-----------------------------------------------------------*/
-
-void vPortISRStartFirstTask( void )
-{
-	/* Simply start the scheduler.  This is included here as it can only be
-	called from ARM mode. */
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Called by portYIELD() or taskYIELD() to manually force a context switch.
- *
- * When a context switch is performed from the task level the saved task 
- * context is made to look as if it occurred from within the tick ISR.  This
- * way the same restore context function can be used when restoring the context
- * saved from the ISR or that saved from a call to vPortYieldProcessor.
- */
-void vPortYieldProcessor( void )
-{
-	/* Within an IRQ ISR the link register has an offset from the true return 
-	address, but an SWI ISR does not.  Add the offset manually so the same 
-	ISR return code can be used in both cases. */
-	asm volatile ( "ADD		LR, LR, #4" );
-
-	/* Perform the context switch.  First save the context of the current task. */
-	portSAVE_CONTEXT();
-
-	/* Find the highest priority task that is ready to run. */
-	vTaskSwitchContext();
-
-	/* Restore the context of the new task. */
-	portRESTORE_CONTEXT();	
-}
-/*-----------------------------------------------------------*/
-
-/* 
- * The ISR used for the scheduler tick depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-
-#if configUSE_PREEMPTION == 0
-
-	/* The cooperative scheduler requires a normal IRQ service routine to 
-	simply increment the system tick. */
-	void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
-	void vNonPreemptiveTick( void )
-	{		
-	static volatile uint32_t ulDummy;
-
-		/* Clear tick timer interrupt indication. */
-		ulDummy = portTIMER_REG_BASE_PTR->TC_SR;  
-
-		xTaskIncrementTick();
-
-		/* Acknowledge the interrupt at AIC level... */
-		AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
-	}
-
-#else  /* else preemption is turned on */
-
-	/* The preemptive scheduler is defined as "naked" as the full context is
-	saved on entry as part of the context switch. */
-	void vPreemptiveTick( void ) __attribute__((naked));
-	void vPreemptiveTick( void )
-	{
-		/* Save the context of the interrupted task. */
-		portSAVE_CONTEXT();	
-
-		/* WARNING - Do not use local (stack) variables here.  Use globals
-					 if you must! */
-		static volatile uint32_t ulDummy;
-
-		/* Clear tick timer interrupt indication. */
-		ulDummy = portTIMER_REG_BASE_PTR->TC_SR;  
-
-		/* Increment the RTOS tick count, then look for the highest priority 
-		task that is ready to run. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			vTaskSwitchContext();
-		}
-
-		/* Acknowledge the interrupt at AIC level... */
-		AT91C_BASE_AIC->AIC_EOICR = portCLEAR_AIC_INTERRUPT;
-
-		/* Restore the context of the new task. */
-		portRESTORE_CONTEXT();
-	}
-
-#endif
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt management utilities can only be called from ARM mode.  When
- * THUMB_INTERWORK is defined the utilities are defined as functions here to
- * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
- * the utilities are defined as macros in portmacro.h - as per other ports.
- */
-#ifdef THUMB_INTERWORK
-
-	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
-	void vPortDisableInterruptsFromThumb( void )
-	{
-		asm volatile ( 
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
-			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
-			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
-			"BX		R14" );					/* Return back to thumb.					*/
-	}
-			
-	void vPortEnableInterruptsFromThumb( void )
-	{
-		asm volatile ( 
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
-			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
-			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
-			"BX		R14" );					/* Return back to thumb.					*/
-	}
-
-#endif /* THUMB_INTERWORK */
-
-/* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels.  The interrupt flags can therefore not always
-be saved to the stack.  Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
-void vPortEnterCritical( void )
-{
-	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
-	asm volatile ( 
-		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
-		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
-		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
-		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
-		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed 
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as we are leaving a critical section. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then interrupts should be
-		re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Enable interrupts as per portEXIT_CRITICAL().				*/
-			asm volatile ( 
-				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
-				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
-				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
-				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
-				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
-		}
-	}
-}
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h
deleted file mode 100755
index fb11822..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_AT91FR40008/portmacro.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-	Changes from V3.2.3
-
-	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
-
-	Changes from V3.2.4
-
-	+ Removed the use of the %0 parameter within the assembler macros and
-	  replaced them with hard coded registers.  This will ensure the
-	  assembler does not select the link register as the temp register as
-	  was occasionally happening previously.
-
-	+ The assembler statements are now included in a single asm block rather
-	  than each line having its own asm block.
-
-	Changes from V4.5.0
-
-	+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
-	  and replaced them with portYIELD_FROM_ISR() macro.  Application code
-	  should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
-	  macros as per the V4.5.1 demo code.
-*/
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-#define portYIELD()					asm volatile ( "SWI 0" )
-#define portNOP()					asm volatile ( "NOP" )
-
-/*
- * These define the timer to use for generating the tick interrupt.
- * They are put in this file so they can be shared between "port.c"
- * and "portisr.c".
- */
-#define portTIMER_REG_BASE_PTR		AT91C_BASE_TC0
-#define portTIMER_CLK_ENABLE_BIT	AT91C_PS_TC0
-#define portTIMER_AIC_CHANNEL		( ( uint32_t ) 4 )
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/*
- * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
- * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
- * are included here for efficiency.  An attempt to call one from
- * THUMB mode code will result in a compile time error.
- */
-
-#define portRESTORE_CONTEXT()											\
-{																		\
-extern volatile void * volatile pxCurrentTCB;							\
-extern volatile uint32_t ulCriticalNesting;					\
-																		\
-	/* Set the LR to the task stack. */									\
-	asm volatile (														\
-	"LDR		R0, =pxCurrentTCB								\n\t"	\
-	"LDR		R0, [R0]										\n\t"	\
-	"LDR		LR, [R0]										\n\t"	\
-																		\
-	/* The critical nesting depth is the first item on the stack. */	\
-	/* Load it into the ulCriticalNesting variable. */					\
-	"LDR		R0, =ulCriticalNesting							\n\t"	\
-	"LDMFD	LR!, {R1}											\n\t"	\
-	"STR		R1, [R0]										\n\t"	\
-																		\
-	/* Get the SPSR from the stack. */									\
-	"LDMFD	LR!, {R0}											\n\t"	\
-	"MSR		SPSR, R0										\n\t"	\
-																		\
-	/* Restore all system mode registers for the task. */				\
-	"LDMFD	LR, {R0-R14}^										\n\t"	\
-	"NOP														\n\t"	\
-																		\
-	/* Restore the return address. */									\
-	"LDR		LR, [LR, #+60]									\n\t"	\
-																		\
-	/* And return - correcting the offset in the LR to obtain the */	\
-	/* correct address. */												\
-	"SUBS	PC, LR, #4											\n\t"	\
-	);																	\
-	( void ) ulCriticalNesting;											\
-	( void ) pxCurrentTCB;												\
-}
-/*-----------------------------------------------------------*/
-
-#define portSAVE_CONTEXT()												\
-{																		\
-extern volatile void * volatile pxCurrentTCB;							\
-extern volatile uint32_t ulCriticalNesting;					\
-																		\
-	/* Push R0 as we are going to use the register. */					\
-	asm volatile (														\
-	"STMDB	SP!, {R0}											\n\t"	\
-																		\
-	/* Set R0 to point to the task stack pointer. */					\
-	"STMDB	SP,{SP}^											\n\t"	\
-	"NOP														\n\t"	\
-	"SUB	SP, SP, #4											\n\t"	\
-	"LDMIA	SP!,{R0}											\n\t"	\
-																		\
-	/* Push the return address onto the stack. */						\
-	"STMDB	R0!, {LR}											\n\t"	\
-																		\
-	/* Now we have saved LR we can use it instead of R0. */				\
-	"MOV	LR, R0												\n\t"	\
-																		\
-	/* Pop R0 so we can save it onto the system mode stack. */			\
-	"LDMIA	SP!, {R0}											\n\t"	\
-																		\
-	/* Push all the system mode registers onto the task stack. */		\
-	"STMDB	LR,{R0-LR}^											\n\t"	\
-	"NOP														\n\t"	\
-	"SUB	LR, LR, #60											\n\t"	\
-																		\
-	/* Push the SPSR onto the task stack. */							\
-	"MRS	R0, SPSR											\n\t"	\
-	"STMDB	LR!, {R0}											\n\t"	\
-																		\
-	"LDR	R0, =ulCriticalNesting								\n\t"	\
-	"LDR	R0, [R0]											\n\t"	\
-	"STMDB	LR!, {R0}											\n\t"	\
-																		\
-	/* Store the new top of stack for the task. */						\
-	"LDR	R0, =pxCurrentTCB									\n\t"	\
-	"LDR	R0, [R0]											\n\t"	\
-	"STR	LR, [R0]											\n\t"	\
-	);																	\
-	( void ) ulCriticalNesting;											\
-	( void ) pxCurrentTCB;												\
-}
-
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
-
-/* Critical section handling. */
-
-/*
- * The interrupt management utilities can only be called from ARM mode.  When
- * THUMB_INTERWORK is defined the utilities are defined as functions in
- * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
- * defined then the utilities are defined as macros here - as per other ports.
- */
-
-#ifdef THUMB_INTERWORK
-
-	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
-	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
-	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
-
-#else
-
-	#define portDISABLE_INTERRUPTS()											\
-		asm volatile (															\
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
-			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
-			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
-
-	#define portENABLE_INTERRUPTS()												\
-		asm volatile (															\
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
-			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
-			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
-
-#endif /* THUMB_INTERWORK */
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL()		vPortEnterCritical();
-#define portEXIT_CRITICAL()			vPortExitCritical();
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h b/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
deleted file mode 100755
index 21b9b08..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/AT91SAM7X256.h
+++ /dev/null
@@ -1,2731 +0,0 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7X256.h
-// Object              : AT91SAM7X256 definitions
-// Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-// 
-// CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
-// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-//  ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X256_H
-#define AT91SAM7X256_H
-
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	// 
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	// 
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	// 
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	// 
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	// 
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	// 
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	// 
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	// 
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[85]; 	// 
-	AT91_REG	 PIOB_PER; 	// PIO Enable Register
-	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOB_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved13[1]; 	// 
-	AT91_REG	 PIOB_OER; 	// Output Enable Register
-	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOB_OSR; 	// Output Status Register
-	AT91_REG	 Reserved14[1]; 	// 
-	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved15[1]; 	// 
-	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved16[1]; 	// 
-	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved17[1]; 	// 
-	AT91_REG	 PIOB_ASR; 	// Select A Register
-	AT91_REG	 PIOB_BSR; 	// Select B Register
-	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved18[9]; 	// 
-	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved19[341]; 	// 
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved20[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved21[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved22[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved23[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved24[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved25[36]; 	// 
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved26[5]; 	// 
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved27[5]; 	// 
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	// 
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	// 
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	// 
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_VREG {
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
-#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[21]; 	// 
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	// 
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	// 
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	// 
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	// 
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	// 
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	// 
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
-
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
-#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	// 
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
-#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[2]; 	// 
-	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[3]; 	// 
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
-#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
-#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
-#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	// 
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN_MB {
-	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
-	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
-	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
-	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
-	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
-	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
-	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
-	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
-#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
-#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
-#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
-#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN {
-	AT91_REG	 CAN_MR; 	// Mode Register
-	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
-	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
-	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
-	AT91_REG	 CAN_SR; 	// Status Register
-	AT91_REG	 CAN_BR; 	// Baudrate Register
-	AT91_REG	 CAN_TIM; 	// Timer Register
-	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
-	AT91_REG	 CAN_ECR; 	// Error Counter Register
-	AT91_REG	 CAN_TCR; 	// Transfer Command Register
-	AT91_REG	 CAN_ACR; 	// Abort Command Register
-	AT91_REG	 Reserved0[52]; 	// 
-	AT91_REG	 CAN_VR; 	// Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
-	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
-	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
-	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
-	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
-	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
-	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
-	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
-	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
-	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
-	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
-	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
-	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
-	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
-	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
-	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
-#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
-#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
-#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
-#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
-#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
-#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
-#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-typedef struct _AT91S_EMAC {
-	AT91_REG	 EMAC_NCR; 	// Network Control Register
-	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
-	AT91_REG	 EMAC_NSR; 	// Network Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
-	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
-	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
-	AT91_REG	 EMAC_RSR; 	// Receive Status Register
-	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
-	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
-	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
-	AT91_REG	 EMAC_PTR; 	// Pause Time Register
-	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
-	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
-	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
-	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
-	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
-	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
-	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
-	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
-	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
-	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
-	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
-	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
-	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
-	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
-	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
-	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
-	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
-	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
-	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
-	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
-	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
-	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
-	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
-	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
-	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
-	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
-	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
-	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
-	AT91_REG	 Reserved1[13]; 	// 
-	AT91_REG	 EMAC_REV; 	// Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
-#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
-#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
-#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
-#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
-#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
-#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
-#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
-#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
-#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
-#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
-#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
-#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
-#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
-#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
-#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
-#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
-#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
-#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
-#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
-#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
-#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
-#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
-#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
-#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
-#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
-#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
-#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
-#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
-#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
-#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
-#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
-#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
-#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
-#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
-#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
-#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
-#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
-#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
-#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
-#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
-#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	// 
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_AES {
-	AT91_REG	 AES_CR; 	// Control Register
-	AT91_REG	 AES_MR; 	// Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AES_IER; 	// Interrupt Enable Register
-	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
-	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AES_ISR; 	// Interrupt Status Register
-	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
-	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
-	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
-	AT91_REG	 Reserved2[35]; 	// 
-	AT91_REG	 AES_VR; 	// AES Version Register
-	AT91_REG	 AES_RPR; 	// Receive Pointer Register
-	AT91_REG	 AES_RCR; 	// Receive Counter Register
-	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
-	AT91_REG	 AES_TCR; 	// Transmit Counter Register
-	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
-} AT91S_AES, *AT91PS_AES;
-
-// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
-#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
-#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
-#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
-#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
-#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
-#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
-#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
-#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
-#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
-#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
-#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_TDES {
-	AT91_REG	 TDES_CR; 	// Control Register
-	AT91_REG	 TDES_MR; 	// Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
-	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
-	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
-	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
-	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
-	AT91_REG	 Reserved2[2]; 	// 
-	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
-	AT91_REG	 Reserved3[2]; 	// 
-	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
-	AT91_REG	 Reserved4[37]; 	// 
-	AT91_REG	 TDES_VR; 	// TDES Version Register
-	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
-	AT91_REG	 TDES_RCR; 	// Receive Counter Register
-	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
-	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
-} AT91S_TDES, *AT91PS_TDES;
-
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
-#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
-#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
-#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
-#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
-#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
-#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
-#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
-#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
-#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ========== 
-// ========== Register definition for AIC peripheral ========== 
-#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ========== 
-#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ========== 
-#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ========== 
-#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ========== 
-#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ========== 
-#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ========== 
-#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ========== 
-#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ========== 
-#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ========== 
-#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ========== 
-#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ========== 
-#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ========== 
-#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ========== 
-#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ========== 
-#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ========== 
-#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ========== 
-#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ========== 
-#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ========== 
-#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ========== 
-#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ========== 
-#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ========== 
-#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ========== 
-#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ========== 
-#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ========== 
-#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ========== 
-#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ========== 
-#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ========== 
-#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ========== 
-#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ========== 
-#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ========== 
-#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ========== 
-#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ========== 
-#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ========== 
-#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ========== 
-#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ========== 
-#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ========== 
-#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ========== 
-#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ========== 
-#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ========== 
-#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ========== 
-#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ========== 
-#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ========== 
-#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ========== 
-#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ========== 
-#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ========== 
-#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ========== 
-#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ========== 
-#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ========== 
-#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ========== 
-#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
-#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
-#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
-#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
-#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
-#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
-#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
-#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
-#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
-#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
-
-#define AT91F_AIC_ConfigureIt( irq_id, priority, src_type, newHandler )		\
-{																			\
-    unsigned int mask ;														\
-																			\
-    mask = 0x1 << irq_id;													\
-    /* Disable the interrupt on the interrupt controller */					\
-    AT91C_BASE_AIC->AIC_IDCR = mask ;										\
-    /* Save the interrupt handler routine pointer and the interrupt priority */	\
-    AT91C_BASE_AIC->AIC_SVR[irq_id] = (unsigned int) newHandler ;			\
-    /* Store the Source Mode Register */									\
-    AT91C_BASE_AIC->AIC_SMR[irq_id] = src_type | priority  ;				\
-    /* Clear the interrupt on the interrupt controller */					\
-    AT91C_BASE_AIC->AIC_ICCR = mask ;										\
-}
-
-
-#endif
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h b/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
deleted file mode 100755
index 567ae74..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/ioat91sam7x256.h
+++ /dev/null
@@ -1,4698 +0,0 @@
-// - ----------------------------------------------------------------------------
-// -          ATMEL Microcontroller Software Support  -  ROUSSET  -
-// - ----------------------------------------------------------------------------
-// -  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-// -  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-// -  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-// -  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-// -  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-// -  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-// -  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// -  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// -  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-// -  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-// - ----------------------------------------------------------------------------
-// - File Name           : AT91SAM7X256.h
-// - Object              : AT91SAM7X256 definitions
-// - Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-// - 
-// - CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
-// - CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// - CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// - CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// - CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// - CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// - CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// - CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// - CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// - CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// - CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// - CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// - CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// - CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// - CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// - CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// - CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// - CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// - CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// - CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// - CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// - CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// - CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// - CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// - CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-// - ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X256_H
-#define AT91SAM7X256_H
-
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	// 
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	// 
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	// 
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	// 
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	// 
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	// 
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	// 
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	// 
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[85]; 	// 
-	AT91_REG	 PIOB_PER; 	// PIO Enable Register
-	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOB_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved13[1]; 	// 
-	AT91_REG	 PIOB_OER; 	// Output Enable Register
-	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOB_OSR; 	// Output Status Register
-	AT91_REG	 Reserved14[1]; 	// 
-	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved15[1]; 	// 
-	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved16[1]; 	// 
-	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved17[1]; 	// 
-	AT91_REG	 PIOB_ASR; 	// Select A Register
-	AT91_REG	 PIOB_BSR; 	// Select B Register
-	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved18[9]; 	// 
-	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved19[341]; 	// 
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved20[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved21[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved22[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved23[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved24[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved25[36]; 	// 
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved26[5]; 	// 
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved27[5]; 	// 
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	// 
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	// 
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	// 
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_VREG {
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
-#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[21]; 	// 
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	// 
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	// 
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	// 
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	// 
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	// 
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	// 
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
-
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
-#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	// 
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
-#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[2]; 	// 
-	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[3]; 	// 
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
-#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
-#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
-#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	// 
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN_MB {
-	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
-	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
-	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
-	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
-	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
-	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
-	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
-	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
-#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
-#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
-#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
-#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN {
-	AT91_REG	 CAN_MR; 	// Mode Register
-	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
-	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
-	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
-	AT91_REG	 CAN_SR; 	// Status Register
-	AT91_REG	 CAN_BR; 	// Baudrate Register
-	AT91_REG	 CAN_TIM; 	// Timer Register
-	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
-	AT91_REG	 CAN_ECR; 	// Error Counter Register
-	AT91_REG	 CAN_TCR; 	// Transfer Command Register
-	AT91_REG	 CAN_ACR; 	// Abort Command Register
-	AT91_REG	 Reserved0[52]; 	// 
-	AT91_REG	 CAN_VR; 	// Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
-	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
-	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
-	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
-	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
-	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
-	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
-	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
-	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
-	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
-	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
-	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
-	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
-	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
-	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
-	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
-#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
-#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
-#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
-#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
-#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
-#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
-#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-typedef struct _AT91S_EMAC {
-	AT91_REG	 EMAC_NCR; 	// Network Control Register
-	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
-	AT91_REG	 EMAC_NSR; 	// Network Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
-	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
-	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
-	AT91_REG	 EMAC_RSR; 	// Receive Status Register
-	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
-	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
-	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
-	AT91_REG	 EMAC_PTR; 	// Pause Time Register
-	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
-	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
-	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
-	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
-	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
-	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
-	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
-	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
-	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
-	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
-	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
-	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
-	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
-	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
-	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
-	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
-	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
-	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
-	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
-	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
-	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
-	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
-	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
-	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
-	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
-	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
-	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
-	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
-	AT91_REG	 Reserved1[13]; 	// 
-	AT91_REG	 EMAC_REV; 	// Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
-#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
-#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
-#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
-#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
-#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
-#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
-#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
-#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
-#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
-#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
-#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
-#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
-#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
-#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
-#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
-#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
-#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
-#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
-#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
-#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
-#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
-#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
-#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
-#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
-#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
-#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
-#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
-#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
-#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
-#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
-#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
-#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
-#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
-#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
-#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
-#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
-#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
-#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
-#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
-#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
-#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	// 
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_AES {
-	AT91_REG	 AES_CR; 	// Control Register
-	AT91_REG	 AES_MR; 	// Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AES_IER; 	// Interrupt Enable Register
-	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
-	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AES_ISR; 	// Interrupt Status Register
-	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
-	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
-	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
-	AT91_REG	 Reserved2[35]; 	// 
-	AT91_REG	 AES_VR; 	// AES Version Register
-	AT91_REG	 AES_RPR; 	// Receive Pointer Register
-	AT91_REG	 AES_RCR; 	// Receive Counter Register
-	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
-	AT91_REG	 AES_TCR; 	// Transmit Counter Register
-	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
-} AT91S_AES, *AT91PS_AES;
-
-// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
-#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
-#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
-#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
-#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
-#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
-#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
-#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
-#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
-#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
-#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
-#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_TDES {
-	AT91_REG	 TDES_CR; 	// Control Register
-	AT91_REG	 TDES_MR; 	// Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
-	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
-	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
-	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
-	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
-	AT91_REG	 Reserved2[2]; 	// 
-	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
-	AT91_REG	 Reserved3[2]; 	// 
-	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
-	AT91_REG	 Reserved4[37]; 	// 
-	AT91_REG	 TDES_VR; 	// TDES Version Register
-	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
-	AT91_REG	 TDES_RCR; 	// Receive Counter Register
-	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
-	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
-} AT91S_TDES, *AT91PS_TDES;
-
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
-#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
-#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
-#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
-#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
-#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
-#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
-#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
-#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
-#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ========== 
-// ========== Register definition for AIC peripheral ========== 
-#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ========== 
-#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ========== 
-#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ========== 
-#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ========== 
-#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ========== 
-#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ========== 
-#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ========== 
-#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ========== 
-#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ========== 
-#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ========== 
-#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ========== 
-#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ========== 
-#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ========== 
-#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ========== 
-#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ========== 
-#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ========== 
-#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ========== 
-#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ========== 
-#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ========== 
-#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ========== 
-#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ========== 
-#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ========== 
-#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ========== 
-#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ========== 
-#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ========== 
-#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ========== 
-#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ========== 
-#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ========== 
-#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ========== 
-#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ========== 
-#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ========== 
-#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ========== 
-#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ========== 
-#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ========== 
-#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ========== 
-#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ========== 
-#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ========== 
-#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ========== 
-#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ========== 
-#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ========== 
-#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ========== 
-#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ========== 
-#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ========== 
-#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ========== 
-#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ========== 
-#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ========== 
-#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ========== 
-#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ========== 
-#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ========== 
-#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
-#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
-#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
-#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
-#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
-#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
-#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
-#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
-#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
-#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
-
-
-
-// - Hardware register definition
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR System Peripherals
-// - *****************************************************************************
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// - *****************************************************************************
-// - -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#if 0 /*_RB_*/
-AT91C_AIC_PRIOR           EQU (0x7 <<  0) ;- (AIC) Priority Level
-AT91C_AIC_PRIOR_LOWEST    EQU (0x0) ;- (AIC) Lowest priority level
-AT91C_AIC_PRIOR_HIGHEST   EQU (0x7) ;- (AIC) Highest priority level
-AT91C_AIC_SRCTYPE         EQU (0x3 <<  5) ;- (AIC) Interrupt Source Type
-AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL EQU (0x0 <<  5) ;- (AIC) Internal Sources Code Label High-level Sensitive
-AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL EQU (0x0 <<  5) ;- (AIC) External Sources Code Label Low-level Sensitive
-AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE EQU (0x1 <<  5) ;- (AIC) Internal Sources Code Label Positive Edge triggered
-AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE EQU (0x1 <<  5) ;- (AIC) External Sources Code Label Negative Edge triggered
-AT91C_AIC_SRCTYPE_HIGH_LEVEL EQU (0x2 <<  5) ;- (AIC) Internal Or External Sources Code Label High-level Sensitive
-AT91C_AIC_SRCTYPE_POSITIVE_EDGE EQU (0x3 <<  5) ;- (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// - -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-AT91C_AIC_NFIQ            EQU (0x1 <<  0) ;- (AIC) NFIQ Status
-AT91C_AIC_NIRQ            EQU (0x1 <<  1) ;- (AIC) NIRQ Status
-// - -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-AT91C_AIC_DCR_PROT        EQU (0x1 <<  0) ;- (AIC) Protection Mode
-AT91C_AIC_DCR_GMSK        EQU (0x1 <<  1) ;- (AIC) General Mask
-#endif
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// - *****************************************************************************
-// - -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-AT91C_PDC_RXTEN           EQU (0x1 <<  0) ;- (PDC) Receiver Transfer Enable
-AT91C_PDC_RXTDIS          EQU (0x1 <<  1) ;- (PDC) Receiver Transfer Disable
-AT91C_PDC_TXTEN           EQU (0x1 <<  8) ;- (PDC) Transmitter Transfer Enable
-AT91C_PDC_TXTDIS          EQU (0x1 <<  9) ;- (PDC) Transmitter Transfer Disable
-// - -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Debug Unit
-// - *****************************************************************************
-// - -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-AT91C_US_RSTRX            EQU (0x1 <<  2) ;- (DBGU) Reset Receiver
-AT91C_US_RSTTX            EQU (0x1 <<  3) ;- (DBGU) Reset Transmitter
-AT91C_US_RXEN             EQU (0x1 <<  4) ;- (DBGU) Receiver Enable
-AT91C_US_RXDIS            EQU (0x1 <<  5) ;- (DBGU) Receiver Disable
-AT91C_US_TXEN             EQU (0x1 <<  6) ;- (DBGU) Transmitter Enable
-AT91C_US_TXDIS            EQU (0x1 <<  7) ;- (DBGU) Transmitter Disable
-AT91C_US_RSTSTA           EQU (0x1 <<  8) ;- (DBGU) Reset Status Bits
-// - -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-AT91C_US_PAR              EQU (0x7 <<  9) ;- (DBGU) Parity type
-AT91C_US_PAR_EVEN         EQU (0x0 <<  9) ;- (DBGU) Even Parity
-AT91C_US_PAR_ODD          EQU (0x1 <<  9) ;- (DBGU) Odd Parity
-AT91C_US_PAR_SPACE        EQU (0x2 <<  9) ;- (DBGU) Parity forced to 0 (Space)
-AT91C_US_PAR_MARK         EQU (0x3 <<  9) ;- (DBGU) Parity forced to 1 (Mark)
-AT91C_US_PAR_NONE         EQU (0x4 <<  9) ;- (DBGU) No Parity
-AT91C_US_PAR_MULTI_DROP   EQU (0x6 <<  9) ;- (DBGU) Multi-drop mode
-AT91C_US_CHMODE           EQU (0x3 << 14) ;- (DBGU) Channel Mode
-AT91C_US_CHMODE_NORMAL    EQU (0x0 << 14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-AT91C_US_CHMODE_AUTO      EQU (0x1 << 14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-AT91C_US_CHMODE_LOCAL     EQU (0x2 << 14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-AT91C_US_CHMODE_REMOTE    EQU (0x3 << 14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// - -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-AT91C_US_RXRDY            EQU (0x1 <<  0) ;- (DBGU) RXRDY Interrupt
-AT91C_US_TXRDY            EQU (0x1 <<  1) ;- (DBGU) TXRDY Interrupt
-AT91C_US_ENDRX            EQU (0x1 <<  3) ;- (DBGU) End of Receive Transfer Interrupt
-AT91C_US_ENDTX            EQU (0x1 <<  4) ;- (DBGU) End of Transmit Interrupt
-AT91C_US_OVRE             EQU (0x1 <<  5) ;- (DBGU) Overrun Interrupt
-AT91C_US_FRAME            EQU (0x1 <<  6) ;- (DBGU) Framing Error Interrupt
-AT91C_US_PARE             EQU (0x1 <<  7) ;- (DBGU) Parity Error Interrupt
-AT91C_US_TXEMPTY          EQU (0x1 <<  9) ;- (DBGU) TXEMPTY Interrupt
-AT91C_US_TXBUFE           EQU (0x1 << 11) ;- (DBGU) TXBUFE Interrupt
-AT91C_US_RXBUFF           EQU (0x1 << 12) ;- (DBGU) RXBUFF Interrupt
-AT91C_US_COMM_TX          EQU (0x1 << 30) ;- (DBGU) COMM_TX Interrupt
-AT91C_US_COMM_RX          EQU (0x1 << 31) ;- (DBGU) COMM_RX Interrupt
-// - -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// - -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// - -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// - -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-AT91C_US_FORCE_NTRST      EQU (0x1 <<  0) ;- (DBGU) Force NTRST in JTAG
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// - *****************************************************************************
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// - *****************************************************************************
-// - -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-AT91C_CKGR_MOSCEN         EQU (0x1 <<  0) ;- (CKGR) Main Oscillator Enable
-AT91C_CKGR_OSCBYPASS      EQU (0x1 <<  1) ;- (CKGR) Main Oscillator Bypass
-AT91C_CKGR_OSCOUNT        EQU (0xFF <<  8) ;- (CKGR) Main Oscillator Start-up Time
-// - -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-AT91C_CKGR_MAINF          EQU (0xFFFF <<  0) ;- (CKGR) Main Clock Frequency
-AT91C_CKGR_MAINRDY        EQU (0x1 << 16) ;- (CKGR) Main Clock Ready
-// - -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-AT91C_CKGR_DIV            EQU (0xFF <<  0) ;- (CKGR) Divider Selected
-AT91C_CKGR_DIV_0          EQU (0x0) ;- (CKGR) Divider output is 0
-AT91C_CKGR_DIV_BYPASS     EQU (0x1) ;- (CKGR) Divider is bypassed
-AT91C_CKGR_PLLCOUNT       EQU (0x3F <<  8) ;- (CKGR) PLL Counter
-AT91C_CKGR_OUT            EQU (0x3 << 14) ;- (CKGR) PLL Output Frequency Range
-AT91C_CKGR_OUT_0          EQU (0x0 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_1          EQU (0x1 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_2          EQU (0x2 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_OUT_3          EQU (0x3 << 14) ;- (CKGR) Please refer to the PLL datasheet
-AT91C_CKGR_MUL            EQU (0x7FF << 16) ;- (CKGR) PLL Multiplier
-AT91C_CKGR_USBDIV         EQU (0x3 << 28) ;- (CKGR) Divider for USB Clocks
-AT91C_CKGR_USBDIV_0       EQU (0x0 << 28) ;- (CKGR) Divider output is PLL clock output
-AT91C_CKGR_USBDIV_1       EQU (0x1 << 28) ;- (CKGR) Divider output is PLL clock output divided by 2
-AT91C_CKGR_USBDIV_2       EQU (0x2 << 28) ;- (CKGR) Divider output is PLL clock output divided by 4
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Power Management Controler
-// - *****************************************************************************
-// - -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-AT91C_PMC_PCK             EQU (0x1 <<  0) ;- (PMC) Processor Clock
-AT91C_PMC_UDP             EQU (0x1 <<  7) ;- (PMC) USB Device Port Clock
-AT91C_PMC_PCK0            EQU (0x1 <<  8) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK1            EQU (0x1 <<  9) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK2            EQU (0x1 << 10) ;- (PMC) Programmable Clock Output
-AT91C_PMC_PCK3            EQU (0x1 << 11) ;- (PMC) Programmable Clock Output
-// - -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// - -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// - -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// - -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// - -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// - -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-AT91C_PMC_CSS             EQU (0x3 <<  0) ;- (PMC) Programmable Clock Selection
-AT91C_PMC_CSS_SLOW_CLK    EQU (0x0) ;- (PMC) Slow Clock is selected
-AT91C_PMC_CSS_MAIN_CLK    EQU (0x1) ;- (PMC) Main Clock is selected
-AT91C_PMC_CSS_PLL_CLK     EQU (0x3) ;- (PMC) Clock from PLL is selected
-AT91C_PMC_PRES            EQU (0x7 <<  2) ;- (PMC) Programmable Clock Prescaler
-AT91C_PMC_PRES_CLK        EQU (0x0 <<  2) ;- (PMC) Selected clock
-AT91C_PMC_PRES_CLK_2      EQU (0x1 <<  2) ;- (PMC) Selected clock divided by 2
-AT91C_PMC_PRES_CLK_4      EQU (0x2 <<  2) ;- (PMC) Selected clock divided by 4
-AT91C_PMC_PRES_CLK_8      EQU (0x3 <<  2) ;- (PMC) Selected clock divided by 8
-AT91C_PMC_PRES_CLK_16     EQU (0x4 <<  2) ;- (PMC) Selected clock divided by 16
-AT91C_PMC_PRES_CLK_32     EQU (0x5 <<  2) ;- (PMC) Selected clock divided by 32
-AT91C_PMC_PRES_CLK_64     EQU (0x6 <<  2) ;- (PMC) Selected clock divided by 64
-// - -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// - -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-AT91C_PMC_MOSCS           EQU (0x1 <<  0) ;- (PMC) MOSC Status/Enable/Disable/Mask
-AT91C_PMC_LOCK            EQU (0x1 <<  2) ;- (PMC) PLL Status/Enable/Disable/Mask
-AT91C_PMC_MCKRDY          EQU (0x1 <<  3) ;- (PMC) MCK_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK0RDY         EQU (0x1 <<  8) ;- (PMC) PCK0_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK1RDY         EQU (0x1 <<  9) ;- (PMC) PCK1_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK2RDY         EQU (0x1 << 10) ;- (PMC) PCK2_RDY Status/Enable/Disable/Mask
-AT91C_PMC_PCK3RDY         EQU (0x1 << 11) ;- (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// - -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// - -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// - -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// - *****************************************************************************
-// - -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-AT91C_RSTC_PROCRST        EQU (0x1 <<  0) ;- (RSTC) Processor Reset
-AT91C_RSTC_PERRST         EQU (0x1 <<  2) ;- (RSTC) Peripheral Reset
-AT91C_RSTC_EXTRST         EQU (0x1 <<  3) ;- (RSTC) External Reset
-AT91C_RSTC_KEY            EQU (0xFF << 24) ;- (RSTC) Password
-// - -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-AT91C_RSTC_URSTS          EQU (0x1 <<  0) ;- (RSTC) User Reset Status
-AT91C_RSTC_BODSTS         EQU (0x1 <<  1) ;- (RSTC) Brownout Detection Status
-AT91C_RSTC_RSTTYP         EQU (0x7 <<  8) ;- (RSTC) Reset Type
-AT91C_RSTC_RSTTYP_POWERUP EQU (0x0 <<  8) ;- (RSTC) Power-up Reset. VDDCORE rising.
-AT91C_RSTC_RSTTYP_WAKEUP  EQU (0x1 <<  8) ;- (RSTC) WakeUp Reset. VDDCORE rising.
-AT91C_RSTC_RSTTYP_WATCHDOG EQU (0x2 <<  8) ;- (RSTC) Watchdog Reset. Watchdog overflow occured.
-AT91C_RSTC_RSTTYP_SOFTWARE EQU (0x3 <<  8) ;- (RSTC) Software Reset. Processor reset required by the software.
-AT91C_RSTC_RSTTYP_USER    EQU (0x4 <<  8) ;- (RSTC) User Reset. NRST pin detected low.
-AT91C_RSTC_RSTTYP_BROWNOUT EQU (0x5 <<  8) ;- (RSTC) Brownout Reset occured.
-AT91C_RSTC_NRSTL          EQU (0x1 << 16) ;- (RSTC) NRST pin level
-AT91C_RSTC_SRCMP          EQU (0x1 << 17) ;- (RSTC) Software Reset Command in Progress.
-// - -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-AT91C_RSTC_URSTEN         EQU (0x1 <<  0) ;- (RSTC) User Reset Enable
-AT91C_RSTC_URSTIEN        EQU (0x1 <<  4) ;- (RSTC) User Reset Interrupt Enable
-AT91C_RSTC_ERSTL          EQU (0xF <<  8) ;- (RSTC) User Reset Enable
-AT91C_RSTC_BODIEN         EQU (0x1 << 16) ;- (RSTC) Brownout Detection Interrupt Enable
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// - *****************************************************************************
-// - -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-AT91C_RTTC_RTPRES         EQU (0xFFFF <<  0) ;- (RTTC) Real-time Timer Prescaler Value
-AT91C_RTTC_ALMIEN         EQU (0x1 << 16) ;- (RTTC) Alarm Interrupt Enable
-AT91C_RTTC_RTTINCIEN      EQU (0x1 << 17) ;- (RTTC) Real Time Timer Increment Interrupt Enable
-AT91C_RTTC_RTTRST         EQU (0x1 << 18) ;- (RTTC) Real Time Timer Restart
-// - -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-AT91C_RTTC_ALMV           EQU (0x0 <<  0) ;- (RTTC) Alarm Value
-// - -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-AT91C_RTTC_CRTV           EQU (0x0 <<  0) ;- (RTTC) Current Real-time Value
-// - -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-AT91C_RTTC_ALMS           EQU (0x1 <<  0) ;- (RTTC) Real-time Alarm Status
-AT91C_RTTC_RTTINC         EQU (0x1 <<  1) ;- (RTTC) Real-time Timer Increment
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// - *****************************************************************************
-// - -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-AT91C_PITC_PIV            EQU (0xFFFFF <<  0) ;- (PITC) Periodic Interval Value
-AT91C_PITC_PITEN          EQU (0x1 << 24) ;- (PITC) Periodic Interval Timer Enabled
-AT91C_PITC_PITIEN         EQU (0x1 << 25) ;- (PITC) Periodic Interval Timer Interrupt Enable
-// - -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-AT91C_PITC_PITS           EQU (0x1 <<  0) ;- (PITC) Periodic Interval Timer Status
-// - -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-AT91C_PITC_CPIV           EQU (0xFFFFF <<  0) ;- (PITC) Current Periodic Interval Value
-AT91C_PITC_PICNT          EQU (0xFFF << 20) ;- (PITC) Periodic Interval Counter
-// - -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// - *****************************************************************************
-// - -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-AT91C_WDTC_WDRSTT         EQU (0x1 <<  0) ;- (WDTC) Watchdog Restart
-AT91C_WDTC_KEY            EQU (0xFF << 24) ;- (WDTC) Watchdog KEY Password
-// - -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-AT91C_WDTC_WDV            EQU (0xFFF <<  0) ;- (WDTC) Watchdog Timer Restart
-AT91C_WDTC_WDFIEN         EQU (0x1 << 12) ;- (WDTC) Watchdog Fault Interrupt Enable
-AT91C_WDTC_WDRSTEN        EQU (0x1 << 13) ;- (WDTC) Watchdog Reset Enable
-AT91C_WDTC_WDRPROC        EQU (0x1 << 14) ;- (WDTC) Watchdog Timer Restart
-AT91C_WDTC_WDDIS          EQU (0x1 << 15) ;- (WDTC) Watchdog Disable
-AT91C_WDTC_WDD            EQU (0xFFF << 16) ;- (WDTC) Watchdog Delta Value
-AT91C_WDTC_WDDBGHLT       EQU (0x1 << 28) ;- (WDTC) Watchdog Debug Halt
-AT91C_WDTC_WDIDLEHLT      EQU (0x1 << 29) ;- (WDTC) Watchdog Idle Halt
-// - -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-AT91C_WDTC_WDUNF          EQU (0x1 <<  0) ;- (WDTC) Watchdog Underflow
-AT91C_WDTC_WDERR          EQU (0x1 <<  1) ;- (WDTC) Watchdog Error
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// - *****************************************************************************
-// - -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
-AT91C_VREG_PSTDBY         EQU (0x1 <<  0) ;- (VREG) Voltage Regulator Power Standby Mode
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// - *****************************************************************************
-// - -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-AT91C_MC_RCB              EQU (0x1 <<  0) ;- (MC) Remap Command Bit
-// - -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-AT91C_MC_UNDADD           EQU (0x1 <<  0) ;- (MC) Undefined Addess Abort Status
-AT91C_MC_MISADD           EQU (0x1 <<  1) ;- (MC) Misaligned Addess Abort Status
-AT91C_MC_ABTSZ            EQU (0x3 <<  8) ;- (MC) Abort Size Status
-AT91C_MC_ABTSZ_BYTE       EQU (0x0 <<  8) ;- (MC) Byte
-AT91C_MC_ABTSZ_HWORD      EQU (0x1 <<  8) ;- (MC) Half-word
-AT91C_MC_ABTSZ_WORD       EQU (0x2 <<  8) ;- (MC) Word
-AT91C_MC_ABTTYP           EQU (0x3 << 10) ;- (MC) Abort Type Status
-AT91C_MC_ABTTYP_DATAR     EQU (0x0 << 10) ;- (MC) Data Read
-AT91C_MC_ABTTYP_DATAW     EQU (0x1 << 10) ;- (MC) Data Write
-AT91C_MC_ABTTYP_FETCH     EQU (0x2 << 10) ;- (MC) Code Fetch
-AT91C_MC_MST0             EQU (0x1 << 16) ;- (MC) Master 0 Abort Source
-AT91C_MC_MST1             EQU (0x1 << 17) ;- (MC) Master 1 Abort Source
-AT91C_MC_SVMST0           EQU (0x1 << 24) ;- (MC) Saved Master 0 Abort Source
-AT91C_MC_SVMST1           EQU (0x1 << 25) ;- (MC) Saved Master 1 Abort Source
-// - -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-AT91C_MC_FRDY             EQU (0x1 <<  0) ;- (MC) Flash Ready
-AT91C_MC_LOCKE            EQU (0x1 <<  2) ;- (MC) Lock Error
-AT91C_MC_PROGE            EQU (0x1 <<  3) ;- (MC) Programming Error
-AT91C_MC_NEBP             EQU (0x1 <<  7) ;- (MC) No Erase Before Programming
-AT91C_MC_FWS              EQU (0x3 <<  8) ;- (MC) Flash Wait State
-AT91C_MC_FWS_0FWS         EQU (0x0 <<  8) ;- (MC) 1 cycle for Read, 2 for Write operations
-AT91C_MC_FWS_1FWS         EQU (0x1 <<  8) ;- (MC) 2 cycles for Read, 3 for Write operations
-AT91C_MC_FWS_2FWS         EQU (0x2 <<  8) ;- (MC) 3 cycles for Read, 4 for Write operations
-AT91C_MC_FWS_3FWS         EQU (0x3 <<  8) ;- (MC) 4 cycles for Read, 4 for Write operations
-AT91C_MC_FMCN             EQU (0xFF << 16) ;- (MC) Flash Microsecond Cycle Number
-// - -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-AT91C_MC_FCMD             EQU (0xF <<  0) ;- (MC) Flash Command
-AT91C_MC_FCMD_START_PROG  EQU (0x1) ;- (MC) Starts the programming of th epage specified by PAGEN.
-AT91C_MC_FCMD_LOCK        EQU (0x2) ;- (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-AT91C_MC_FCMD_PROG_AND_LOCK EQU (0x3) ;- (MC) The lock sequence automatically happens after the programming sequence is completed.
-AT91C_MC_FCMD_UNLOCK      EQU (0x4) ;- (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-AT91C_MC_FCMD_ERASE_ALL   EQU (0x8) ;- (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-AT91C_MC_FCMD_SET_GP_NVM  EQU (0xB) ;- (MC) Set General Purpose NVM bits.
-AT91C_MC_FCMD_CLR_GP_NVM  EQU (0xD) ;- (MC) Clear General Purpose NVM bits.
-AT91C_MC_FCMD_SET_SECURITY EQU (0xF) ;- (MC) Set Security Bit.
-AT91C_MC_PAGEN            EQU (0x3FF <<  8) ;- (MC) Page Number
-AT91C_MC_KEY              EQU (0xFF << 24) ;- (MC) Writing Protect Key
-// - -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-AT91C_MC_SECURITY         EQU (0x1 <<  4) ;- (MC) Security Bit Status
-AT91C_MC_GPNVM0           EQU (0x1 <<  8) ;- (MC) Sector 0 Lock Status
-AT91C_MC_GPNVM1           EQU (0x1 <<  9) ;- (MC) Sector 1 Lock Status
-AT91C_MC_GPNVM2           EQU (0x1 << 10) ;- (MC) Sector 2 Lock Status
-AT91C_MC_GPNVM3           EQU (0x1 << 11) ;- (MC) Sector 3 Lock Status
-AT91C_MC_GPNVM4           EQU (0x1 << 12) ;- (MC) Sector 4 Lock Status
-AT91C_MC_GPNVM5           EQU (0x1 << 13) ;- (MC) Sector 5 Lock Status
-AT91C_MC_GPNVM6           EQU (0x1 << 14) ;- (MC) Sector 6 Lock Status
-AT91C_MC_GPNVM7           EQU (0x1 << 15) ;- (MC) Sector 7 Lock Status
-AT91C_MC_LOCKS0           EQU (0x1 << 16) ;- (MC) Sector 0 Lock Status
-AT91C_MC_LOCKS1           EQU (0x1 << 17) ;- (MC) Sector 1 Lock Status
-AT91C_MC_LOCKS2           EQU (0x1 << 18) ;- (MC) Sector 2 Lock Status
-AT91C_MC_LOCKS3           EQU (0x1 << 19) ;- (MC) Sector 3 Lock Status
-AT91C_MC_LOCKS4           EQU (0x1 << 20) ;- (MC) Sector 4 Lock Status
-AT91C_MC_LOCKS5           EQU (0x1 << 21) ;- (MC) Sector 5 Lock Status
-AT91C_MC_LOCKS6           EQU (0x1 << 22) ;- (MC) Sector 6 Lock Status
-AT91C_MC_LOCKS7           EQU (0x1 << 23) ;- (MC) Sector 7 Lock Status
-AT91C_MC_LOCKS8           EQU (0x1 << 24) ;- (MC) Sector 8 Lock Status
-AT91C_MC_LOCKS9           EQU (0x1 << 25) ;- (MC) Sector 9 Lock Status
-AT91C_MC_LOCKS10          EQU (0x1 << 26) ;- (MC) Sector 10 Lock Status
-AT91C_MC_LOCKS11          EQU (0x1 << 27) ;- (MC) Sector 11 Lock Status
-AT91C_MC_LOCKS12          EQU (0x1 << 28) ;- (MC) Sector 12 Lock Status
-AT91C_MC_LOCKS13          EQU (0x1 << 29) ;- (MC) Sector 13 Lock Status
-AT91C_MC_LOCKS14          EQU (0x1 << 30) ;- (MC) Sector 14 Lock Status
-AT91C_MC_LOCKS15          EQU (0x1 << 31) ;- (MC) Sector 15 Lock Status
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// - *****************************************************************************
-// - -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-AT91C_SPI_SPIEN           EQU (0x1 <<  0) ;- (SPI) SPI Enable
-AT91C_SPI_SPIDIS          EQU (0x1 <<  1) ;- (SPI) SPI Disable
-AT91C_SPI_SWRST           EQU (0x1 <<  7) ;- (SPI) SPI Software reset
-AT91C_SPI_LASTXFER        EQU (0x1 << 24) ;- (SPI) SPI Last Transfer
-// - -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-AT91C_SPI_MSTR            EQU (0x1 <<  0) ;- (SPI) Master/Slave Mode
-AT91C_SPI_PS              EQU (0x1 <<  1) ;- (SPI) Peripheral Select
-AT91C_SPI_PS_FIXED        EQU (0x0 <<  1) ;- (SPI) Fixed Peripheral Select
-AT91C_SPI_PS_VARIABLE     EQU (0x1 <<  1) ;- (SPI) Variable Peripheral Select
-AT91C_SPI_PCSDEC          EQU (0x1 <<  2) ;- (SPI) Chip Select Decode
-AT91C_SPI_FDIV            EQU (0x1 <<  3) ;- (SPI) Clock Selection
-AT91C_SPI_MODFDIS         EQU (0x1 <<  4) ;- (SPI) Mode Fault Detection
-AT91C_SPI_LLB             EQU (0x1 <<  7) ;- (SPI) Clock Selection
-AT91C_SPI_PCS             EQU (0xF << 16) ;- (SPI) Peripheral Chip Select
-AT91C_SPI_DLYBCS          EQU (0xFF << 24) ;- (SPI) Delay Between Chip Selects
-// - -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-AT91C_SPI_RD              EQU (0xFFFF <<  0) ;- (SPI) Receive Data
-AT91C_SPI_RPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
-// - -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-AT91C_SPI_TD              EQU (0xFFFF <<  0) ;- (SPI) Transmit Data
-AT91C_SPI_TPCS            EQU (0xF << 16) ;- (SPI) Peripheral Chip Select Status
-// - -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-AT91C_SPI_RDRF            EQU (0x1 <<  0) ;- (SPI) Receive Data Register Full
-AT91C_SPI_TDRE            EQU (0x1 <<  1) ;- (SPI) Transmit Data Register Empty
-AT91C_SPI_MODF            EQU (0x1 <<  2) ;- (SPI) Mode Fault Error
-AT91C_SPI_OVRES           EQU (0x1 <<  3) ;- (SPI) Overrun Error Status
-AT91C_SPI_ENDRX           EQU (0x1 <<  4) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_ENDTX           EQU (0x1 <<  5) ;- (SPI) End of Receiver Transfer
-AT91C_SPI_RXBUFF          EQU (0x1 <<  6) ;- (SPI) RXBUFF Interrupt
-AT91C_SPI_TXBUFE          EQU (0x1 <<  7) ;- (SPI) TXBUFE Interrupt
-AT91C_SPI_NSSR            EQU (0x1 <<  8) ;- (SPI) NSSR Interrupt
-AT91C_SPI_TXEMPTY         EQU (0x1 <<  9) ;- (SPI) TXEMPTY Interrupt
-AT91C_SPI_SPIENS          EQU (0x1 << 16) ;- (SPI) Enable Status
-// - -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// - -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// - -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// - -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-AT91C_SPI_CPOL            EQU (0x1 <<  0) ;- (SPI) Clock Polarity
-AT91C_SPI_NCPHA           EQU (0x1 <<  1) ;- (SPI) Clock Phase
-AT91C_SPI_CSAAT           EQU (0x1 <<  3) ;- (SPI) Chip Select Active After Transfer
-AT91C_SPI_BITS            EQU (0xF <<  4) ;- (SPI) Bits Per Transfer
-AT91C_SPI_BITS_8          EQU (0x0 <<  4) ;- (SPI) 8 Bits Per transfer
-AT91C_SPI_BITS_9          EQU (0x1 <<  4) ;- (SPI) 9 Bits Per transfer
-AT91C_SPI_BITS_10         EQU (0x2 <<  4) ;- (SPI) 10 Bits Per transfer
-AT91C_SPI_BITS_11         EQU (0x3 <<  4) ;- (SPI) 11 Bits Per transfer
-AT91C_SPI_BITS_12         EQU (0x4 <<  4) ;- (SPI) 12 Bits Per transfer
-AT91C_SPI_BITS_13         EQU (0x5 <<  4) ;- (SPI) 13 Bits Per transfer
-AT91C_SPI_BITS_14         EQU (0x6 <<  4) ;- (SPI) 14 Bits Per transfer
-AT91C_SPI_BITS_15         EQU (0x7 <<  4) ;- (SPI) 15 Bits Per transfer
-AT91C_SPI_BITS_16         EQU (0x8 <<  4) ;- (SPI) 16 Bits Per transfer
-AT91C_SPI_SCBR            EQU (0xFF <<  8) ;- (SPI) Serial Clock Baud Rate
-AT91C_SPI_DLYBS           EQU (0xFF << 16) ;- (SPI) Delay Before SPCK
-AT91C_SPI_DLYBCT          EQU (0xFF << 24) ;- (SPI) Delay Between Consecutive Transfers
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Usart
-// - *****************************************************************************
-// - -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-AT91C_US_STTBRK           EQU (0x1 <<  9) ;- (USART) Start Break
-AT91C_US_STPBRK           EQU (0x1 << 10) ;- (USART) Stop Break
-AT91C_US_STTTO            EQU (0x1 << 11) ;- (USART) Start Time-out
-AT91C_US_SENDA            EQU (0x1 << 12) ;- (USART) Send Address
-AT91C_US_RSTIT            EQU (0x1 << 13) ;- (USART) Reset Iterations
-AT91C_US_RSTNACK          EQU (0x1 << 14) ;- (USART) Reset Non Acknowledge
-AT91C_US_RETTO            EQU (0x1 << 15) ;- (USART) Rearm Time-out
-AT91C_US_DTREN            EQU (0x1 << 16) ;- (USART) Data Terminal ready Enable
-AT91C_US_DTRDIS           EQU (0x1 << 17) ;- (USART) Data Terminal ready Disable
-AT91C_US_RTSEN            EQU (0x1 << 18) ;- (USART) Request to Send enable
-AT91C_US_RTSDIS           EQU (0x1 << 19) ;- (USART) Request to Send Disable
-// - -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-AT91C_US_USMODE           EQU (0xF <<  0) ;- (USART) Usart mode
-AT91C_US_USMODE_NORMAL    EQU (0x0) ;- (USART) Normal
-AT91C_US_USMODE_RS485     EQU (0x1) ;- (USART) RS485
-AT91C_US_USMODE_HWHSH     EQU (0x2) ;- (USART) Hardware Handshaking
-AT91C_US_USMODE_MODEM     EQU (0x3) ;- (USART) Modem
-AT91C_US_USMODE_ISO7816_0 EQU (0x4) ;- (USART) ISO7816 protocol: T = 0
-AT91C_US_USMODE_ISO7816_1 EQU (0x6) ;- (USART) ISO7816 protocol: T = 1
-AT91C_US_USMODE_IRDA      EQU (0x8) ;- (USART) IrDA
-AT91C_US_USMODE_SWHSH     EQU (0xC) ;- (USART) Software Handshaking
-AT91C_US_CLKS             EQU (0x3 <<  4) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CLKS_CLOCK       EQU (0x0 <<  4) ;- (USART) Clock
-AT91C_US_CLKS_FDIV1       EQU (0x1 <<  4) ;- (USART) fdiv1
-AT91C_US_CLKS_SLOW        EQU (0x2 <<  4) ;- (USART) slow_clock (ARM)
-AT91C_US_CLKS_EXT         EQU (0x3 <<  4) ;- (USART) External (SCK)
-AT91C_US_CHRL             EQU (0x3 <<  6) ;- (USART) Clock Selection (Baud Rate generator Input Clock
-AT91C_US_CHRL_5_BITS      EQU (0x0 <<  6) ;- (USART) Character Length: 5 bits
-AT91C_US_CHRL_6_BITS      EQU (0x1 <<  6) ;- (USART) Character Length: 6 bits
-AT91C_US_CHRL_7_BITS      EQU (0x2 <<  6) ;- (USART) Character Length: 7 bits
-AT91C_US_CHRL_8_BITS      EQU (0x3 <<  6) ;- (USART) Character Length: 8 bits
-AT91C_US_SYNC             EQU (0x1 <<  8) ;- (USART) Synchronous Mode Select
-AT91C_US_NBSTOP           EQU (0x3 << 12) ;- (USART) Number of Stop bits
-AT91C_US_NBSTOP_1_BIT     EQU (0x0 << 12) ;- (USART) 1 stop bit
-AT91C_US_NBSTOP_15_BIT    EQU (0x1 << 12) ;- (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-AT91C_US_NBSTOP_2_BIT     EQU (0x2 << 12) ;- (USART) 2 stop bits
-AT91C_US_MSBF             EQU (0x1 << 16) ;- (USART) Bit Order
-AT91C_US_MODE9            EQU (0x1 << 17) ;- (USART) 9-bit Character length
-AT91C_US_CKLO             EQU (0x1 << 18) ;- (USART) Clock Output Select
-AT91C_US_OVER             EQU (0x1 << 19) ;- (USART) Over Sampling Mode
-AT91C_US_INACK            EQU (0x1 << 20) ;- (USART) Inhibit Non Acknowledge
-AT91C_US_DSNACK           EQU (0x1 << 21) ;- (USART) Disable Successive NACK
-AT91C_US_MAX_ITER         EQU (0x1 << 24) ;- (USART) Number of Repetitions
-AT91C_US_FILTER           EQU (0x1 << 28) ;- (USART) Receive Line Filter
-// - -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-AT91C_US_RXBRK            EQU (0x1 <<  2) ;- (USART) Break Received/End of Break
-AT91C_US_TIMEOUT          EQU (0x1 <<  8) ;- (USART) Receiver Time-out
-AT91C_US_ITERATION        EQU (0x1 << 10) ;- (USART) Max number of Repetitions Reached
-AT91C_US_NACK             EQU (0x1 << 13) ;- (USART) Non Acknowledge
-AT91C_US_RIIC             EQU (0x1 << 16) ;- (USART) Ring INdicator Input Change Flag
-AT91C_US_DSRIC            EQU (0x1 << 17) ;- (USART) Data Set Ready Input Change Flag
-AT91C_US_DCDIC            EQU (0x1 << 18) ;- (USART) Data Carrier Flag
-AT91C_US_CTSIC            EQU (0x1 << 19) ;- (USART) Clear To Send Input Change Flag
-// - -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// - -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// - -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-AT91C_US_RI               EQU (0x1 << 20) ;- (USART) Image of RI Input
-AT91C_US_DSR              EQU (0x1 << 21) ;- (USART) Image of DSR Input
-AT91C_US_DCD              EQU (0x1 << 22) ;- (USART) Image of DCD Input
-AT91C_US_CTS              EQU (0x1 << 23) ;- (USART) Image of CTS Input
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// - *****************************************************************************
-// - -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-AT91C_SSC_RXEN            EQU (0x1 <<  0) ;- (SSC) Receive Enable
-AT91C_SSC_RXDIS           EQU (0x1 <<  1) ;- (SSC) Receive Disable
-AT91C_SSC_TXEN            EQU (0x1 <<  8) ;- (SSC) Transmit Enable
-AT91C_SSC_TXDIS           EQU (0x1 <<  9) ;- (SSC) Transmit Disable
-AT91C_SSC_SWRST           EQU (0x1 << 15) ;- (SSC) Software Reset
-// - -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-AT91C_SSC_CKS             EQU (0x3 <<  0) ;- (SSC) Receive/Transmit Clock Selection
-AT91C_SSC_CKS_DIV         EQU (0x0) ;- (SSC) Divided Clock
-AT91C_SSC_CKS_TK          EQU (0x1) ;- (SSC) TK Clock signal
-AT91C_SSC_CKS_RK          EQU (0x2) ;- (SSC) RK pin
-AT91C_SSC_CKO             EQU (0x7 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode Selection
-AT91C_SSC_CKO_NONE        EQU (0x0 <<  2) ;- (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-AT91C_SSC_CKO_CONTINOUS   EQU (0x1 <<  2) ;- (SSC) Continuous Receive/Transmit Clock RK pin: Output
-AT91C_SSC_CKO_DATA_TX     EQU (0x2 <<  2) ;- (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-AT91C_SSC_CKI             EQU (0x1 <<  5) ;- (SSC) Receive/Transmit Clock Inversion
-AT91C_SSC_START           EQU (0xF <<  8) ;- (SSC) Receive/Transmit Start Selection
-AT91C_SSC_START_CONTINOUS EQU (0x0 <<  8) ;- (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-AT91C_SSC_START_TX        EQU (0x1 <<  8) ;- (SSC) Transmit/Receive start
-AT91C_SSC_START_LOW_RF    EQU (0x2 <<  8) ;- (SSC) Detection of a low level on RF input
-AT91C_SSC_START_HIGH_RF   EQU (0x3 <<  8) ;- (SSC) Detection of a high level on RF input
-AT91C_SSC_START_FALL_RF   EQU (0x4 <<  8) ;- (SSC) Detection of a falling edge on RF input
-AT91C_SSC_START_RISE_RF   EQU (0x5 <<  8) ;- (SSC) Detection of a rising edge on RF input
-AT91C_SSC_START_LEVEL_RF  EQU (0x6 <<  8) ;- (SSC) Detection of any level change on RF input
-AT91C_SSC_START_EDGE_RF   EQU (0x7 <<  8) ;- (SSC) Detection of any edge on RF input
-AT91C_SSC_START_0         EQU (0x8 <<  8) ;- (SSC) Compare 0
-AT91C_SSC_STTDLY          EQU (0xFF << 16) ;- (SSC) Receive/Transmit Start Delay
-AT91C_SSC_PERIOD          EQU (0xFF << 24) ;- (SSC) Receive/Transmit Period Divider Selection
-// - -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-AT91C_SSC_DATLEN          EQU (0x1F <<  0) ;- (SSC) Data Length
-AT91C_SSC_LOOP            EQU (0x1 <<  5) ;- (SSC) Loop Mode
-AT91C_SSC_MSBF            EQU (0x1 <<  7) ;- (SSC) Most Significant Bit First
-AT91C_SSC_DATNB           EQU (0xF <<  8) ;- (SSC) Data Number per Frame
-AT91C_SSC_FSLEN           EQU (0xF << 16) ;- (SSC) Receive/Transmit Frame Sync length
-AT91C_SSC_FSOS            EQU (0x7 << 20) ;- (SSC) Receive/Transmit Frame Sync Output Selection
-AT91C_SSC_FSOS_NONE       EQU (0x0 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-AT91C_SSC_FSOS_NEGATIVE   EQU (0x1 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-AT91C_SSC_FSOS_POSITIVE   EQU (0x2 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-AT91C_SSC_FSOS_LOW        EQU (0x3 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-AT91C_SSC_FSOS_HIGH       EQU (0x4 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-AT91C_SSC_FSOS_TOGGLE     EQU (0x5 << 20) ;- (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-AT91C_SSC_FSEDGE          EQU (0x1 << 24) ;- (SSC) Frame Sync Edge Detection
-// - -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// - -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-AT91C_SSC_DATDEF          EQU (0x1 <<  5) ;- (SSC) Data Default Value
-AT91C_SSC_FSDEN           EQU (0x1 << 23) ;- (SSC) Frame Sync Data Enable
-// - -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-AT91C_SSC_TXRDY           EQU (0x1 <<  0) ;- (SSC) Transmit Ready
-AT91C_SSC_TXEMPTY         EQU (0x1 <<  1) ;- (SSC) Transmit Empty
-AT91C_SSC_ENDTX           EQU (0x1 <<  2) ;- (SSC) End Of Transmission
-AT91C_SSC_TXBUFE          EQU (0x1 <<  3) ;- (SSC) Transmit Buffer Empty
-AT91C_SSC_RXRDY           EQU (0x1 <<  4) ;- (SSC) Receive Ready
-AT91C_SSC_OVRUN           EQU (0x1 <<  5) ;- (SSC) Receive Overrun
-AT91C_SSC_ENDRX           EQU (0x1 <<  6) ;- (SSC) End of Reception
-AT91C_SSC_RXBUFF          EQU (0x1 <<  7) ;- (SSC) Receive Buffer Full
-AT91C_SSC_TXSYN           EQU (0x1 << 10) ;- (SSC) Transmit Sync
-AT91C_SSC_RXSYN           EQU (0x1 << 11) ;- (SSC) Receive Sync
-AT91C_SSC_TXENA           EQU (0x1 << 16) ;- (SSC) Transmit Enable
-AT91C_SSC_RXENA           EQU (0x1 << 17) ;- (SSC) Receive Enable
-// - -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// - -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// - -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// - *****************************************************************************
-// - -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-AT91C_TWI_START           EQU (0x1 <<  0) ;- (TWI) Send a START Condition
-AT91C_TWI_STOP            EQU (0x1 <<  1) ;- (TWI) Send a STOP Condition
-AT91C_TWI_MSEN            EQU (0x1 <<  2) ;- (TWI) TWI Master Transfer Enabled
-AT91C_TWI_MSDIS           EQU (0x1 <<  3) ;- (TWI) TWI Master Transfer Disabled
-AT91C_TWI_SWRST           EQU (0x1 <<  7) ;- (TWI) Software Reset
-// - -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-AT91C_TWI_IADRSZ          EQU (0x3 <<  8) ;- (TWI) Internal Device Address Size
-AT91C_TWI_IADRSZ_NO       EQU (0x0 <<  8) ;- (TWI) No internal device address
-AT91C_TWI_IADRSZ_1_BYTE   EQU (0x1 <<  8) ;- (TWI) One-byte internal device address
-AT91C_TWI_IADRSZ_2_BYTE   EQU (0x2 <<  8) ;- (TWI) Two-byte internal device address
-AT91C_TWI_IADRSZ_3_BYTE   EQU (0x3 <<  8) ;- (TWI) Three-byte internal device address
-AT91C_TWI_MREAD           EQU (0x1 << 12) ;- (TWI) Master Read Direction
-AT91C_TWI_DADR            EQU (0x7F << 16) ;- (TWI) Device Address
-// - -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-AT91C_TWI_CLDIV           EQU (0xFF <<  0) ;- (TWI) Clock Low Divider
-AT91C_TWI_CHDIV           EQU (0xFF <<  8) ;- (TWI) Clock High Divider
-AT91C_TWI_CKDIV           EQU (0x7 << 16) ;- (TWI) Clock Divider
-// - -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-AT91C_TWI_TXCOMP          EQU (0x1 <<  0) ;- (TWI) Transmission Completed
-AT91C_TWI_RXRDY           EQU (0x1 <<  1) ;- (TWI) Receive holding register ReaDY
-AT91C_TWI_TXRDY           EQU (0x1 <<  2) ;- (TWI) Transmit holding register ReaDY
-AT91C_TWI_OVRE            EQU (0x1 <<  6) ;- (TWI) Overrun Error
-AT91C_TWI_UNRE            EQU (0x1 <<  7) ;- (TWI) Underrun Error
-AT91C_TWI_NACK            EQU (0x1 <<  8) ;- (TWI) Not Acknowledged
-// - -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// - -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// - -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// - *****************************************************************************
-// - -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-AT91C_PWMC_CPRE           EQU (0xF <<  0) ;- (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-AT91C_PWMC_CPRE_MCK       EQU (0x0) ;- (PWMC_CH) 
-AT91C_PWMC_CPRE_MCKA      EQU (0xB) ;- (PWMC_CH) 
-AT91C_PWMC_CPRE_MCKB      EQU (0xC) ;- (PWMC_CH) 
-AT91C_PWMC_CALG           EQU (0x1 <<  8) ;- (PWMC_CH) Channel Alignment
-AT91C_PWMC_CPOL           EQU (0x1 <<  9) ;- (PWMC_CH) Channel Polarity
-AT91C_PWMC_CPD            EQU (0x1 << 10) ;- (PWMC_CH) Channel Update Period
-// - -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-AT91C_PWMC_CDTY           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Duty Cycle
-// - -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-AT91C_PWMC_CPRD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Period
-// - -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-AT91C_PWMC_CCNT           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Counter
-// - -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-AT91C_PWMC_CUPD           EQU (0x0 <<  0) ;- (PWMC_CH) Channel Update
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// - *****************************************************************************
-// - -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-AT91C_PWMC_DIVA           EQU (0xFF <<  0) ;- (PWMC) CLKA divide factor.
-AT91C_PWMC_PREA           EQU (0xF <<  8) ;- (PWMC) Divider Input Clock Prescaler A
-AT91C_PWMC_PREA_MCK       EQU (0x0 <<  8) ;- (PWMC) 
-AT91C_PWMC_DIVB           EQU (0xFF << 16) ;- (PWMC) CLKB divide factor.
-AT91C_PWMC_PREB           EQU (0xF << 24) ;- (PWMC) Divider Input Clock Prescaler B
-AT91C_PWMC_PREB_MCK       EQU (0x0 << 24) ;- (PWMC) 
-// - -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-AT91C_PWMC_CHID0          EQU (0x1 <<  0) ;- (PWMC) Channel ID 0
-AT91C_PWMC_CHID1          EQU (0x1 <<  1) ;- (PWMC) Channel ID 1
-AT91C_PWMC_CHID2          EQU (0x1 <<  2) ;- (PWMC) Channel ID 2
-AT91C_PWMC_CHID3          EQU (0x1 <<  3) ;- (PWMC) Channel ID 3
-// - -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// - -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// - -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// - -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// - -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// - -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR USB Device Interface
-// - *****************************************************************************
-// - -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-AT91C_UDP_FRM_NUM         EQU (0x7FF <<  0) ;- (UDP) Frame Number as Defined in the Packet Field Formats
-AT91C_UDP_FRM_ERR         EQU (0x1 << 16) ;- (UDP) Frame Error
-AT91C_UDP_FRM_OK          EQU (0x1 << 17) ;- (UDP) Frame OK
-// - -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-AT91C_UDP_FADDEN          EQU (0x1 <<  0) ;- (UDP) Function Address Enable
-AT91C_UDP_CONFG           EQU (0x1 <<  1) ;- (UDP) Configured
-AT91C_UDP_ESR             EQU (0x1 <<  2) ;- (UDP) Enable Send Resume
-AT91C_UDP_RSMINPR         EQU (0x1 <<  3) ;- (UDP) A Resume Has Been Sent to the Host
-AT91C_UDP_RMWUPE          EQU (0x1 <<  4) ;- (UDP) Remote Wake Up Enable
-// - -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-AT91C_UDP_FADD            EQU (0xFF <<  0) ;- (UDP) Function Address Value
-AT91C_UDP_FEN             EQU (0x1 <<  8) ;- (UDP) Function Enable
-// - -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-AT91C_UDP_EPINT0          EQU (0x1 <<  0) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT1          EQU (0x1 <<  1) ;- (UDP) Endpoint 0 Interrupt
-AT91C_UDP_EPINT2          EQU (0x1 <<  2) ;- (UDP) Endpoint 2 Interrupt
-AT91C_UDP_EPINT3          EQU (0x1 <<  3) ;- (UDP) Endpoint 3 Interrupt
-AT91C_UDP_EPINT4          EQU (0x1 <<  4) ;- (UDP) Endpoint 4 Interrupt
-AT91C_UDP_EPINT5          EQU (0x1 <<  5) ;- (UDP) Endpoint 5 Interrupt
-AT91C_UDP_RXSUSP          EQU (0x1 <<  8) ;- (UDP) USB Suspend Interrupt
-AT91C_UDP_RXRSM           EQU (0x1 <<  9) ;- (UDP) USB Resume Interrupt
-AT91C_UDP_EXTRSM          EQU (0x1 << 10) ;- (UDP) USB External Resume Interrupt
-AT91C_UDP_SOFINT          EQU (0x1 << 11) ;- (UDP) USB Start Of frame Interrupt
-AT91C_UDP_WAKEUP          EQU (0x1 << 13) ;- (UDP) USB Resume Interrupt
-// - -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// - -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// - -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-AT91C_UDP_ENDBUSRES       EQU (0x1 << 12) ;- (UDP) USB End Of Bus Reset Interrupt
-// - -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// - -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-AT91C_UDP_EP0             EQU (0x1 <<  0) ;- (UDP) Reset Endpoint 0
-AT91C_UDP_EP1             EQU (0x1 <<  1) ;- (UDP) Reset Endpoint 1
-AT91C_UDP_EP2             EQU (0x1 <<  2) ;- (UDP) Reset Endpoint 2
-AT91C_UDP_EP3             EQU (0x1 <<  3) ;- (UDP) Reset Endpoint 3
-AT91C_UDP_EP4             EQU (0x1 <<  4) ;- (UDP) Reset Endpoint 4
-AT91C_UDP_EP5             EQU (0x1 <<  5) ;- (UDP) Reset Endpoint 5
-// - -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-AT91C_UDP_TXCOMP          EQU (0x1 <<  0) ;- (UDP) Generates an IN packet with data previously written in the DPR
-AT91C_UDP_RX_DATA_BK0     EQU (0x1 <<  1) ;- (UDP) Receive Data Bank 0
-AT91C_UDP_RXSETUP         EQU (0x1 <<  2) ;- (UDP) Sends STALL to the Host (Control endpoints)
-AT91C_UDP_ISOERROR        EQU (0x1 <<  3) ;- (UDP) Isochronous error (Isochronous endpoints)
-AT91C_UDP_TXPKTRDY        EQU (0x1 <<  4) ;- (UDP) Transmit Packet Ready
-AT91C_UDP_FORCESTALL      EQU (0x1 <<  5) ;- (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-AT91C_UDP_RX_DATA_BK1     EQU (0x1 <<  6) ;- (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-AT91C_UDP_DIR             EQU (0x1 <<  7) ;- (UDP) Transfer Direction
-AT91C_UDP_EPTYPE          EQU (0x7 <<  8) ;- (UDP) Endpoint type
-AT91C_UDP_EPTYPE_CTRL     EQU (0x0 <<  8) ;- (UDP) Control
-AT91C_UDP_EPTYPE_ISO_OUT  EQU (0x1 <<  8) ;- (UDP) Isochronous OUT
-AT91C_UDP_EPTYPE_BULK_OUT EQU (0x2 <<  8) ;- (UDP) Bulk OUT
-AT91C_UDP_EPTYPE_INT_OUT  EQU (0x3 <<  8) ;- (UDP) Interrupt OUT
-AT91C_UDP_EPTYPE_ISO_IN   EQU (0x5 <<  8) ;- (UDP) Isochronous IN
-AT91C_UDP_EPTYPE_BULK_IN  EQU (0x6 <<  8) ;- (UDP) Bulk IN
-AT91C_UDP_EPTYPE_INT_IN   EQU (0x7 <<  8) ;- (UDP) Interrupt IN
-AT91C_UDP_DTGLE           EQU (0x1 << 11) ;- (UDP) Data Toggle
-AT91C_UDP_EPEDS           EQU (0x1 << 15) ;- (UDP) Endpoint Enable Disable
-AT91C_UDP_RXBYTECNT       EQU (0x7FF << 16) ;- (UDP) Number Of Bytes Available in the FIFO
-// - -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
-AT91C_UDP_TXVDIS          EQU (0x1 <<  8) ;- (UDP) 
-AT91C_UDP_PUON            EQU (0x1 <<  9) ;- (UDP) Pull-up ON
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// - *****************************************************************************
-// - -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-AT91C_TC_CLKEN            EQU (0x1 <<  0) ;- (TC) Counter Clock Enable Command
-AT91C_TC_CLKDIS           EQU (0x1 <<  1) ;- (TC) Counter Clock Disable Command
-AT91C_TC_SWTRG            EQU (0x1 <<  2) ;- (TC) Software Trigger Command
-// - -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-AT91C_TC_CLKS             EQU (0x7 <<  0) ;- (TC) Clock Selection
-AT91C_TC_CLKS_TIMER_DIV1_CLOCK EQU (0x0) ;- (TC) Clock selected: TIMER_DIV1_CLOCK
-AT91C_TC_CLKS_TIMER_DIV2_CLOCK EQU (0x1) ;- (TC) Clock selected: TIMER_DIV2_CLOCK
-AT91C_TC_CLKS_TIMER_DIV3_CLOCK EQU (0x2) ;- (TC) Clock selected: TIMER_DIV3_CLOCK
-AT91C_TC_CLKS_TIMER_DIV4_CLOCK EQU (0x3) ;- (TC) Clock selected: TIMER_DIV4_CLOCK
-AT91C_TC_CLKS_TIMER_DIV5_CLOCK EQU (0x4) ;- (TC) Clock selected: TIMER_DIV5_CLOCK
-AT91C_TC_CLKS_XC0         EQU (0x5) ;- (TC) Clock selected: XC0
-AT91C_TC_CLKS_XC1         EQU (0x6) ;- (TC) Clock selected: XC1
-AT91C_TC_CLKS_XC2         EQU (0x7) ;- (TC) Clock selected: XC2
-AT91C_TC_CLKI             EQU (0x1 <<  3) ;- (TC) Clock Invert
-AT91C_TC_BURST            EQU (0x3 <<  4) ;- (TC) Burst Signal Selection
-AT91C_TC_BURST_NONE       EQU (0x0 <<  4) ;- (TC) The clock is not gated by an external signal
-AT91C_TC_BURST_XC0        EQU (0x1 <<  4) ;- (TC) XC0 is ANDed with the selected clock
-AT91C_TC_BURST_XC1        EQU (0x2 <<  4) ;- (TC) XC1 is ANDed with the selected clock
-AT91C_TC_BURST_XC2        EQU (0x3 <<  4) ;- (TC) XC2 is ANDed with the selected clock
-AT91C_TC_CPCSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RC Compare
-AT91C_TC_LDBSTOP          EQU (0x1 <<  6) ;- (TC) Counter Clock Stopped with RB Loading
-AT91C_TC_CPCDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disable with RC Compare
-AT91C_TC_LDBDIS           EQU (0x1 <<  7) ;- (TC) Counter Clock Disabled with RB Loading
-AT91C_TC_ETRGEDG          EQU (0x3 <<  8) ;- (TC) External Trigger Edge Selection
-AT91C_TC_ETRGEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
-AT91C_TC_ETRGEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
-AT91C_TC_ETRGEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
-AT91C_TC_ETRGEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
-AT91C_TC_EEVTEDG          EQU (0x3 <<  8) ;- (TC) External Event Edge Selection
-AT91C_TC_EEVTEDG_NONE     EQU (0x0 <<  8) ;- (TC) Edge: None
-AT91C_TC_EEVTEDG_RISING   EQU (0x1 <<  8) ;- (TC) Edge: rising edge
-AT91C_TC_EEVTEDG_FALLING  EQU (0x2 <<  8) ;- (TC) Edge: falling edge
-AT91C_TC_EEVTEDG_BOTH     EQU (0x3 <<  8) ;- (TC) Edge: each edge
-AT91C_TC_EEVT             EQU (0x3 << 10) ;- (TC) External Event  Selection
-AT91C_TC_EEVT_TIOB        EQU (0x0 << 10) ;- (TC) Signal selected as external event: TIOB TIOB direction: input
-AT91C_TC_EEVT_XC0         EQU (0x1 << 10) ;- (TC) Signal selected as external event: XC0 TIOB direction: output
-AT91C_TC_EEVT_XC1         EQU (0x2 << 10) ;- (TC) Signal selected as external event: XC1 TIOB direction: output
-AT91C_TC_EEVT_XC2         EQU (0x3 << 10) ;- (TC) Signal selected as external event: XC2 TIOB direction: output
-AT91C_TC_ABETRG           EQU (0x1 << 10) ;- (TC) TIOA or TIOB External Trigger Selection
-AT91C_TC_ENETRG           EQU (0x1 << 12) ;- (TC) External Event Trigger enable
-AT91C_TC_WAVESEL          EQU (0x3 << 13) ;- (TC) Waveform  Selection
-AT91C_TC_WAVESEL_UP       EQU (0x0 << 13) ;- (TC) UP mode without atomatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN   EQU (0x1 << 13) ;- (TC) UPDOWN mode without automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UP_AUTO  EQU (0x2 << 13) ;- (TC) UP mode with automatic trigger on RC Compare
-AT91C_TC_WAVESEL_UPDOWN_AUTO EQU (0x3 << 13) ;- (TC) UPDOWN mode with automatic trigger on RC Compare
-AT91C_TC_CPCTRG           EQU (0x1 << 14) ;- (TC) RC Compare Trigger Enable
-AT91C_TC_WAVE             EQU (0x1 << 15) ;- (TC) 
-AT91C_TC_ACPA             EQU (0x3 << 16) ;- (TC) RA Compare Effect on TIOA
-AT91C_TC_ACPA_NONE        EQU (0x0 << 16) ;- (TC) Effect: none
-AT91C_TC_ACPA_SET         EQU (0x1 << 16) ;- (TC) Effect: set
-AT91C_TC_ACPA_CLEAR       EQU (0x2 << 16) ;- (TC) Effect: clear
-AT91C_TC_ACPA_TOGGLE      EQU (0x3 << 16) ;- (TC) Effect: toggle
-AT91C_TC_LDRA             EQU (0x3 << 16) ;- (TC) RA Loading Selection
-AT91C_TC_LDRA_NONE        EQU (0x0 << 16) ;- (TC) Edge: None
-AT91C_TC_LDRA_RISING      EQU (0x1 << 16) ;- (TC) Edge: rising edge of TIOA
-AT91C_TC_LDRA_FALLING     EQU (0x2 << 16) ;- (TC) Edge: falling edge of TIOA
-AT91C_TC_LDRA_BOTH        EQU (0x3 << 16) ;- (TC) Edge: each edge of TIOA
-AT91C_TC_ACPC             EQU (0x3 << 18) ;- (TC) RC Compare Effect on TIOA
-AT91C_TC_ACPC_NONE        EQU (0x0 << 18) ;- (TC) Effect: none
-AT91C_TC_ACPC_SET         EQU (0x1 << 18) ;- (TC) Effect: set
-AT91C_TC_ACPC_CLEAR       EQU (0x2 << 18) ;- (TC) Effect: clear
-AT91C_TC_ACPC_TOGGLE      EQU (0x3 << 18) ;- (TC) Effect: toggle
-AT91C_TC_LDRB             EQU (0x3 << 18) ;- (TC) RB Loading Selection
-AT91C_TC_LDRB_NONE        EQU (0x0 << 18) ;- (TC) Edge: None
-AT91C_TC_LDRB_RISING      EQU (0x1 << 18) ;- (TC) Edge: rising edge of TIOA
-AT91C_TC_LDRB_FALLING     EQU (0x2 << 18) ;- (TC) Edge: falling edge of TIOA
-AT91C_TC_LDRB_BOTH        EQU (0x3 << 18) ;- (TC) Edge: each edge of TIOA
-AT91C_TC_AEEVT            EQU (0x3 << 20) ;- (TC) External Event Effect on TIOA
-AT91C_TC_AEEVT_NONE       EQU (0x0 << 20) ;- (TC) Effect: none
-AT91C_TC_AEEVT_SET        EQU (0x1 << 20) ;- (TC) Effect: set
-AT91C_TC_AEEVT_CLEAR      EQU (0x2 << 20) ;- (TC) Effect: clear
-AT91C_TC_AEEVT_TOGGLE     EQU (0x3 << 20) ;- (TC) Effect: toggle
-AT91C_TC_ASWTRG           EQU (0x3 << 22) ;- (TC) Software Trigger Effect on TIOA
-AT91C_TC_ASWTRG_NONE      EQU (0x0 << 22) ;- (TC) Effect: none
-AT91C_TC_ASWTRG_SET       EQU (0x1 << 22) ;- (TC) Effect: set
-AT91C_TC_ASWTRG_CLEAR     EQU (0x2 << 22) ;- (TC) Effect: clear
-AT91C_TC_ASWTRG_TOGGLE    EQU (0x3 << 22) ;- (TC) Effect: toggle
-AT91C_TC_BCPB             EQU (0x3 << 24) ;- (TC) RB Compare Effect on TIOB
-AT91C_TC_BCPB_NONE        EQU (0x0 << 24) ;- (TC) Effect: none
-AT91C_TC_BCPB_SET         EQU (0x1 << 24) ;- (TC) Effect: set
-AT91C_TC_BCPB_CLEAR       EQU (0x2 << 24) ;- (TC) Effect: clear
-AT91C_TC_BCPB_TOGGLE      EQU (0x3 << 24) ;- (TC) Effect: toggle
-AT91C_TC_BCPC             EQU (0x3 << 26) ;- (TC) RC Compare Effect on TIOB
-AT91C_TC_BCPC_NONE        EQU (0x0 << 26) ;- (TC) Effect: none
-AT91C_TC_BCPC_SET         EQU (0x1 << 26) ;- (TC) Effect: set
-AT91C_TC_BCPC_CLEAR       EQU (0x2 << 26) ;- (TC) Effect: clear
-AT91C_TC_BCPC_TOGGLE      EQU (0x3 << 26) ;- (TC) Effect: toggle
-AT91C_TC_BEEVT            EQU (0x3 << 28) ;- (TC) External Event Effect on TIOB
-AT91C_TC_BEEVT_NONE       EQU (0x0 << 28) ;- (TC) Effect: none
-AT91C_TC_BEEVT_SET        EQU (0x1 << 28) ;- (TC) Effect: set
-AT91C_TC_BEEVT_CLEAR      EQU (0x2 << 28) ;- (TC) Effect: clear
-AT91C_TC_BEEVT_TOGGLE     EQU (0x3 << 28) ;- (TC) Effect: toggle
-AT91C_TC_BSWTRG           EQU (0x3 << 30) ;- (TC) Software Trigger Effect on TIOB
-AT91C_TC_BSWTRG_NONE      EQU (0x0 << 30) ;- (TC) Effect: none
-AT91C_TC_BSWTRG_SET       EQU (0x1 << 30) ;- (TC) Effect: set
-AT91C_TC_BSWTRG_CLEAR     EQU (0x2 << 30) ;- (TC) Effect: clear
-AT91C_TC_BSWTRG_TOGGLE    EQU (0x3 << 30) ;- (TC) Effect: toggle
-// - -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-AT91C_TC_COVFS            EQU (0x1 <<  0) ;- (TC) Counter Overflow
-AT91C_TC_LOVRS            EQU (0x1 <<  1) ;- (TC) Load Overrun
-AT91C_TC_CPAS             EQU (0x1 <<  2) ;- (TC) RA Compare
-AT91C_TC_CPBS             EQU (0x1 <<  3) ;- (TC) RB Compare
-AT91C_TC_CPCS             EQU (0x1 <<  4) ;- (TC) RC Compare
-AT91C_TC_LDRAS            EQU (0x1 <<  5) ;- (TC) RA Loading
-AT91C_TC_LDRBS            EQU (0x1 <<  6) ;- (TC) RB Loading
-AT91C_TC_ETRGS            EQU (0x1 <<  7) ;- (TC) External Trigger
-AT91C_TC_CLKSTA           EQU (0x1 << 16) ;- (TC) Clock Enabling
-AT91C_TC_MTIOA            EQU (0x1 << 17) ;- (TC) TIOA Mirror
-AT91C_TC_MTIOB            EQU (0x1 << 18) ;- (TC) TIOA Mirror
-// - -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// - -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// - -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// - *****************************************************************************
-// - -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-AT91C_TCB_SYNC            EQU (0x1 <<  0) ;- (TCB) Synchro Command
-// - -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-AT91C_TCB_TC0XC0S         EQU (0x3 <<  0) ;- (TCB) External Clock Signal 0 Selection
-AT91C_TCB_TC0XC0S_TCLK0   EQU (0x0) ;- (TCB) TCLK0 connected to XC0
-AT91C_TCB_TC0XC0S_NONE    EQU (0x1) ;- (TCB) None signal connected to XC0
-AT91C_TCB_TC0XC0S_TIOA1   EQU (0x2) ;- (TCB) TIOA1 connected to XC0
-AT91C_TCB_TC0XC0S_TIOA2   EQU (0x3) ;- (TCB) TIOA2 connected to XC0
-AT91C_TCB_TC1XC1S         EQU (0x3 <<  2) ;- (TCB) External Clock Signal 1 Selection
-AT91C_TCB_TC1XC1S_TCLK1   EQU (0x0 <<  2) ;- (TCB) TCLK1 connected to XC1
-AT91C_TCB_TC1XC1S_NONE    EQU (0x1 <<  2) ;- (TCB) None signal connected to XC1
-AT91C_TCB_TC1XC1S_TIOA0   EQU (0x2 <<  2) ;- (TCB) TIOA0 connected to XC1
-AT91C_TCB_TC1XC1S_TIOA2   EQU (0x3 <<  2) ;- (TCB) TIOA2 connected to XC1
-AT91C_TCB_TC2XC2S         EQU (0x3 <<  4) ;- (TCB) External Clock Signal 2 Selection
-AT91C_TCB_TC2XC2S_TCLK2   EQU (0x0 <<  4) ;- (TCB) TCLK2 connected to XC2
-AT91C_TCB_TC2XC2S_NONE    EQU (0x1 <<  4) ;- (TCB) None signal connected to XC2
-AT91C_TCB_TC2XC2S_TIOA0   EQU (0x2 <<  4) ;- (TCB) TIOA0 connected to XC2
-AT91C_TCB_TC2XC2S_TIOA1   EQU (0x3 <<  4) ;- (TCB) TIOA2 connected to XC2
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// - *****************************************************************************
-// - -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
-AT91C_CAN_MTIMEMARK       EQU (0xFFFF <<  0) ;- (CAN_MB) Mailbox Timemark
-AT91C_CAN_PRIOR           EQU (0xF << 16) ;- (CAN_MB) Mailbox Priority
-AT91C_CAN_MOT             EQU (0x7 << 24) ;- (CAN_MB) Mailbox Object Type
-AT91C_CAN_MOT_DIS         EQU (0x0 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_RX          EQU (0x1 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_RXOVERWRITE EQU (0x2 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_TX          EQU (0x3 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_CONSUMER    EQU (0x4 << 24) ;- (CAN_MB) 
-AT91C_CAN_MOT_PRODUCER    EQU (0x5 << 24) ;- (CAN_MB) 
-// - -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
-AT91C_CAN_MIDvB           EQU (0x3FFFF <<  0) ;- (CAN_MB) Complementary bits for identifier in extended mode
-AT91C_CAN_MIDvA           EQU (0x7FF << 18) ;- (CAN_MB) Identifier for standard frame mode
-AT91C_CAN_MIDE            EQU (0x1 << 29) ;- (CAN_MB) Identifier Version
-// - -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
-// - -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
-// - -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
-AT91C_CAN_MTIMESTAMP      EQU (0xFFFF <<  0) ;- (CAN_MB) Timer Value
-AT91C_CAN_MDLC            EQU (0xF << 16) ;- (CAN_MB) Mailbox Data Length Code
-AT91C_CAN_MRTR            EQU (0x1 << 20) ;- (CAN_MB) Mailbox Remote Transmission Request
-AT91C_CAN_MABT            EQU (0x1 << 22) ;- (CAN_MB) Mailbox Message Abort
-AT91C_CAN_MRDY            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Ready
-AT91C_CAN_MMI             EQU (0x1 << 24) ;- (CAN_MB) Mailbox Message Ignored
-// - -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
-// - -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
-// - -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
-AT91C_CAN_MACR            EQU (0x1 << 22) ;- (CAN_MB) Abort Request for Mailbox
-AT91C_CAN_MTCR            EQU (0x1 << 23) ;- (CAN_MB) Mailbox Transfer Command
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// - *****************************************************************************
-// - -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
-AT91C_CAN_CANEN           EQU (0x1 <<  0) ;- (CAN) CAN Controller Enable
-AT91C_CAN_LPM             EQU (0x1 <<  1) ;- (CAN) Disable/Enable Low Power Mode
-AT91C_CAN_ABM             EQU (0x1 <<  2) ;- (CAN) Disable/Enable Autobaud/Listen Mode
-AT91C_CAN_OVL             EQU (0x1 <<  3) ;- (CAN) Disable/Enable Overload Frame
-AT91C_CAN_TEOF            EQU (0x1 <<  4) ;- (CAN) Time Stamp messages at each end of Frame
-AT91C_CAN_TTM             EQU (0x1 <<  5) ;- (CAN) Disable/Enable Time Trigger Mode
-AT91C_CAN_TIMFRZ          EQU (0x1 <<  6) ;- (CAN) Enable Timer Freeze
-AT91C_CAN_DRPT            EQU (0x1 <<  7) ;- (CAN) Disable Repeat
-// - -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
-AT91C_CAN_MB0             EQU (0x1 <<  0) ;- (CAN) Mailbox 0 Flag
-AT91C_CAN_MB1             EQU (0x1 <<  1) ;- (CAN) Mailbox 1 Flag
-AT91C_CAN_MB2             EQU (0x1 <<  2) ;- (CAN) Mailbox 2 Flag
-AT91C_CAN_MB3             EQU (0x1 <<  3) ;- (CAN) Mailbox 3 Flag
-AT91C_CAN_MB4             EQU (0x1 <<  4) ;- (CAN) Mailbox 4 Flag
-AT91C_CAN_MB5             EQU (0x1 <<  5) ;- (CAN) Mailbox 5 Flag
-AT91C_CAN_MB6             EQU (0x1 <<  6) ;- (CAN) Mailbox 6 Flag
-AT91C_CAN_MB7             EQU (0x1 <<  7) ;- (CAN) Mailbox 7 Flag
-AT91C_CAN_MB8             EQU (0x1 <<  8) ;- (CAN) Mailbox 8 Flag
-AT91C_CAN_MB9             EQU (0x1 <<  9) ;- (CAN) Mailbox 9 Flag
-AT91C_CAN_MB10            EQU (0x1 << 10) ;- (CAN) Mailbox 10 Flag
-AT91C_CAN_MB11            EQU (0x1 << 11) ;- (CAN) Mailbox 11 Flag
-AT91C_CAN_MB12            EQU (0x1 << 12) ;- (CAN) Mailbox 12 Flag
-AT91C_CAN_MB13            EQU (0x1 << 13) ;- (CAN) Mailbox 13 Flag
-AT91C_CAN_MB14            EQU (0x1 << 14) ;- (CAN) Mailbox 14 Flag
-AT91C_CAN_MB15            EQU (0x1 << 15) ;- (CAN) Mailbox 15 Flag
-AT91C_CAN_ERRA            EQU (0x1 << 16) ;- (CAN) Error Active Mode Flag
-AT91C_CAN_WARN            EQU (0x1 << 17) ;- (CAN) Warning Limit Flag
-AT91C_CAN_ERRP            EQU (0x1 << 18) ;- (CAN) Error Passive Mode Flag
-AT91C_CAN_BOFF            EQU (0x1 << 19) ;- (CAN) Bus Off Mode Flag
-AT91C_CAN_SLEEP           EQU (0x1 << 20) ;- (CAN) Sleep Flag
-AT91C_CAN_WAKEUP          EQU (0x1 << 21) ;- (CAN) Wakeup Flag
-AT91C_CAN_TOVF            EQU (0x1 << 22) ;- (CAN) Timer Overflow Flag
-AT91C_CAN_TSTP            EQU (0x1 << 23) ;- (CAN) Timestamp Flag
-AT91C_CAN_CERR            EQU (0x1 << 24) ;- (CAN) CRC Error
-AT91C_CAN_SERR            EQU (0x1 << 25) ;- (CAN) Stuffing Error
-AT91C_CAN_AERR            EQU (0x1 << 26) ;- (CAN) Acknowledgment Error
-AT91C_CAN_FERR            EQU (0x1 << 27) ;- (CAN) Form Error
-AT91C_CAN_BERR            EQU (0x1 << 28) ;- (CAN) Bit Error
-// - -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
-// - -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
-// - -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
-AT91C_CAN_RBSY            EQU (0x1 << 29) ;- (CAN) Receiver Busy
-AT91C_CAN_TBSY            EQU (0x1 << 30) ;- (CAN) Transmitter Busy
-AT91C_CAN_OVLY            EQU (0x1 << 31) ;- (CAN) Overload Busy
-// - -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
-AT91C_CAN_PHASE2          EQU (0x7 <<  0) ;- (CAN) Phase 2 segment
-AT91C_CAN_PHASE1          EQU (0x7 <<  4) ;- (CAN) Phase 1 segment
-AT91C_CAN_PROPAG          EQU (0x7 <<  8) ;- (CAN) Programmation time segment
-AT91C_CAN_SYNC            EQU (0x3 << 12) ;- (CAN) Re-synchronization jump width segment
-AT91C_CAN_BRP             EQU (0x7F << 16) ;- (CAN) Baudrate Prescaler
-AT91C_CAN_SMP             EQU (0x1 << 24) ;- (CAN) Sampling mode
-// - -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
-AT91C_CAN_TIMER           EQU (0xFFFF <<  0) ;- (CAN) Timer field
-// - -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
-// - -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
-AT91C_CAN_REC             EQU (0xFF <<  0) ;- (CAN) Receive Error Counter
-AT91C_CAN_TEC             EQU (0xFF << 16) ;- (CAN) Transmit Error Counter
-// - -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
-AT91C_CAN_TIMRST          EQU (0x1 << 31) ;- (CAN) Timer Reset Field
-// - -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// - *****************************************************************************
-// - -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
-AT91C_EMAC_LB             EQU (0x1 <<  0) ;- (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-AT91C_EMAC_LLB            EQU (0x1 <<  1) ;- (EMAC) Loopback local. 
-AT91C_EMAC_RE             EQU (0x1 <<  2) ;- (EMAC) Receive enable. 
-AT91C_EMAC_TE             EQU (0x1 <<  3) ;- (EMAC) Transmit enable. 
-AT91C_EMAC_MPE            EQU (0x1 <<  4) ;- (EMAC) Management port enable. 
-AT91C_EMAC_CLRSTAT        EQU (0x1 <<  5) ;- (EMAC) Clear statistics registers. 
-AT91C_EMAC_INCSTAT        EQU (0x1 <<  6) ;- (EMAC) Increment statistics registers. 
-AT91C_EMAC_WESTAT         EQU (0x1 <<  7) ;- (EMAC) Write enable for statistics registers. 
-AT91C_EMAC_BP             EQU (0x1 <<  8) ;- (EMAC) Back pressure. 
-AT91C_EMAC_TSTART         EQU (0x1 <<  9) ;- (EMAC) Start Transmission. 
-AT91C_EMAC_THALT          EQU (0x1 << 10) ;- (EMAC) Transmission Halt. 
-AT91C_EMAC_TPFR           EQU (0x1 << 11) ;- (EMAC) Transmit pause frame 
-AT91C_EMAC_TZQ            EQU (0x1 << 12) ;- (EMAC) Transmit zero quantum pause frame
-// - -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
-AT91C_EMAC_SPD            EQU (0x1 <<  0) ;- (EMAC) Speed. 
-AT91C_EMAC_FD             EQU (0x1 <<  1) ;- (EMAC) Full duplex. 
-AT91C_EMAC_JFRAME         EQU (0x1 <<  3) ;- (EMAC) Jumbo Frames. 
-AT91C_EMAC_CAF            EQU (0x1 <<  4) ;- (EMAC) Copy all frames. 
-AT91C_EMAC_NBC            EQU (0x1 <<  5) ;- (EMAC) No broadcast. 
-AT91C_EMAC_MTI            EQU (0x1 <<  6) ;- (EMAC) Multicast hash event enable
-AT91C_EMAC_UNI            EQU (0x1 <<  7) ;- (EMAC) Unicast hash enable. 
-AT91C_EMAC_BIG            EQU (0x1 <<  8) ;- (EMAC) Receive 1522 bytes. 
-AT91C_EMAC_EAE            EQU (0x1 <<  9) ;- (EMAC) External address match enable. 
-AT91C_EMAC_CLK            EQU (0x3 << 10) ;- (EMAC) 
-AT91C_EMAC_CLK_HCLK_8     EQU (0x0 << 10) ;- (EMAC) HCLK divided by 8
-AT91C_EMAC_CLK_HCLK_16    EQU (0x1 << 10) ;- (EMAC) HCLK divided by 16
-AT91C_EMAC_CLK_HCLK_32    EQU (0x2 << 10) ;- (EMAC) HCLK divided by 32
-AT91C_EMAC_CLK_HCLK_64    EQU (0x3 << 10) ;- (EMAC) HCLK divided by 64
-AT91C_EMAC_RTY            EQU (0x1 << 12) ;- (EMAC) 
-AT91C_EMAC_PAE            EQU (0x1 << 13) ;- (EMAC) 
-AT91C_EMAC_RBOF           EQU (0x3 << 14) ;- (EMAC) 
-AT91C_EMAC_RBOF_OFFSET_0  EQU (0x0 << 14) ;- (EMAC) no offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_1  EQU (0x1 << 14) ;- (EMAC) one byte offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_2  EQU (0x2 << 14) ;- (EMAC) two bytes offset from start of receive buffer
-AT91C_EMAC_RBOF_OFFSET_3  EQU (0x3 << 14) ;- (EMAC) three bytes offset from start of receive buffer
-AT91C_EMAC_RLCE           EQU (0x1 << 16) ;- (EMAC) Receive Length field Checking Enable
-AT91C_EMAC_DRFCS          EQU (0x1 << 17) ;- (EMAC) Discard Receive FCS
-AT91C_EMAC_EFRHD          EQU (0x1 << 18) ;- (EMAC) 
-AT91C_EMAC_IRXFCS         EQU (0x1 << 19) ;- (EMAC) Ignore RX FCS
-// - -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
-AT91C_EMAC_LINKR          EQU (0x1 <<  0) ;- (EMAC) 
-AT91C_EMAC_MDIO           EQU (0x1 <<  1) ;- (EMAC) 
-AT91C_EMAC_IDLE           EQU (0x1 <<  2) ;- (EMAC) 
-// - -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
-AT91C_EMAC_UBR            EQU (0x1 <<  0) ;- (EMAC) 
-AT91C_EMAC_COL            EQU (0x1 <<  1) ;- (EMAC) 
-AT91C_EMAC_RLES           EQU (0x1 <<  2) ;- (EMAC) 
-AT91C_EMAC_TGO            EQU (0x1 <<  3) ;- (EMAC) Transmit Go
-AT91C_EMAC_BEX            EQU (0x1 <<  4) ;- (EMAC) Buffers exhausted mid frame
-AT91C_EMAC_COMP           EQU (0x1 <<  5) ;- (EMAC) 
-AT91C_EMAC_UND            EQU (0x1 <<  6) ;- (EMAC) 
-// - -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-AT91C_EMAC_BNA            EQU (0x1 <<  0) ;- (EMAC) 
-AT91C_EMAC_REC            EQU (0x1 <<  1) ;- (EMAC) 
-AT91C_EMAC_OVR            EQU (0x1 <<  2) ;- (EMAC) 
-// - -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-AT91C_EMAC_MFD            EQU (0x1 <<  0) ;- (EMAC) 
-AT91C_EMAC_RCOMP          EQU (0x1 <<  1) ;- (EMAC) 
-AT91C_EMAC_RXUBR          EQU (0x1 <<  2) ;- (EMAC) 
-AT91C_EMAC_TXUBR          EQU (0x1 <<  3) ;- (EMAC) 
-AT91C_EMAC_TUNDR          EQU (0x1 <<  4) ;- (EMAC) 
-AT91C_EMAC_RLEX           EQU (0x1 <<  5) ;- (EMAC) 
-AT91C_EMAC_TXERR          EQU (0x1 <<  6) ;- (EMAC) 
-AT91C_EMAC_TCOMP          EQU (0x1 <<  7) ;- (EMAC) 
-AT91C_EMAC_LINK           EQU (0x1 <<  9) ;- (EMAC) 
-AT91C_EMAC_ROVR           EQU (0x1 << 10) ;- (EMAC) 
-AT91C_EMAC_HRESP          EQU (0x1 << 11) ;- (EMAC) 
-AT91C_EMAC_PFRE           EQU (0x1 << 12) ;- (EMAC) 
-AT91C_EMAC_PTZ            EQU (0x1 << 13) ;- (EMAC) 
-// - -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// - -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// - -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// - -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-AT91C_EMAC_DATA           EQU (0xFFFF <<  0) ;- (EMAC) 
-AT91C_EMAC_CODE           EQU (0x3 << 16) ;- (EMAC) 
-AT91C_EMAC_REGA           EQU (0x1F << 18) ;- (EMAC) 
-AT91C_EMAC_PHYA           EQU (0x1F << 23) ;- (EMAC) 
-AT91C_EMAC_RW             EQU (0x3 << 28) ;- (EMAC) 
-AT91C_EMAC_SOF            EQU (0x3 << 30) ;- (EMAC) 
-// - -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
-AT91C_EMAC_RMII           EQU (0x1 <<  0) ;- (EMAC) Reduce MII
-// - -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
-AT91C_EMAC_IP             EQU (0xFFFF <<  0) ;- (EMAC) ARP request IP address
-AT91C_EMAC_MAG            EQU (0x1 << 16) ;- (EMAC) Magic packet event enable
-AT91C_EMAC_ARP            EQU (0x1 << 17) ;- (EMAC) ARP request event enable
-AT91C_EMAC_SA1            EQU (0x1 << 18) ;- (EMAC) Specific address register 1 event enable
-// - -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
-AT91C_EMAC_REVREF         EQU (0xFFFF <<  0) ;- (EMAC) 
-AT91C_EMAC_PARTREF        EQU (0xFFFF << 16) ;- (EMAC) 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// - *****************************************************************************
-// - -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-AT91C_ADC_SWRST           EQU (0x1 <<  0) ;- (ADC) Software Reset
-AT91C_ADC_START           EQU (0x1 <<  1) ;- (ADC) Start Conversion
-// - -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-AT91C_ADC_TRGEN           EQU (0x1 <<  0) ;- (ADC) Trigger Enable
-AT91C_ADC_TRGEN_DIS       EQU (0x0) ;- (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-AT91C_ADC_TRGEN_EN        EQU (0x1) ;- (ADC) Hardware trigger selected by TRGSEL field is enabled.
-AT91C_ADC_TRGSEL          EQU (0x7 <<  1) ;- (ADC) Trigger Selection
-AT91C_ADC_TRGSEL_TIOA0    EQU (0x0 <<  1) ;- (ADC) Selected TRGSEL = TIAO0
-AT91C_ADC_TRGSEL_TIOA1    EQU (0x1 <<  1) ;- (ADC) Selected TRGSEL = TIAO1
-AT91C_ADC_TRGSEL_TIOA2    EQU (0x2 <<  1) ;- (ADC) Selected TRGSEL = TIAO2
-AT91C_ADC_TRGSEL_TIOA3    EQU (0x3 <<  1) ;- (ADC) Selected TRGSEL = TIAO3
-AT91C_ADC_TRGSEL_TIOA4    EQU (0x4 <<  1) ;- (ADC) Selected TRGSEL = TIAO4
-AT91C_ADC_TRGSEL_TIOA5    EQU (0x5 <<  1) ;- (ADC) Selected TRGSEL = TIAO5
-AT91C_ADC_TRGSEL_EXT      EQU (0x6 <<  1) ;- (ADC) Selected TRGSEL = External Trigger
-AT91C_ADC_LOWRES          EQU (0x1 <<  4) ;- (ADC) Resolution.
-AT91C_ADC_LOWRES_10_BIT   EQU (0x0 <<  4) ;- (ADC) 10-bit resolution
-AT91C_ADC_LOWRES_8_BIT    EQU (0x1 <<  4) ;- (ADC) 8-bit resolution
-AT91C_ADC_SLEEP           EQU (0x1 <<  5) ;- (ADC) Sleep Mode
-AT91C_ADC_SLEEP_NORMAL_MODE EQU (0x0 <<  5) ;- (ADC) Normal Mode
-AT91C_ADC_SLEEP_MODE      EQU (0x1 <<  5) ;- (ADC) Sleep Mode
-AT91C_ADC_PRESCAL         EQU (0x3F <<  8) ;- (ADC) Prescaler rate selection
-AT91C_ADC_STARTUP         EQU (0x1F << 16) ;- (ADC) Startup Time
-AT91C_ADC_SHTIM           EQU (0xF << 24) ;- (ADC) Sample & Hold Time
-// - -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-AT91C_ADC_CH0             EQU (0x1 <<  0) ;- (ADC) Channel 0
-AT91C_ADC_CH1             EQU (0x1 <<  1) ;- (ADC) Channel 1
-AT91C_ADC_CH2             EQU (0x1 <<  2) ;- (ADC) Channel 2
-AT91C_ADC_CH3             EQU (0x1 <<  3) ;- (ADC) Channel 3
-AT91C_ADC_CH4             EQU (0x1 <<  4) ;- (ADC) Channel 4
-AT91C_ADC_CH5             EQU (0x1 <<  5) ;- (ADC) Channel 5
-AT91C_ADC_CH6             EQU (0x1 <<  6) ;- (ADC) Channel 6
-AT91C_ADC_CH7             EQU (0x1 <<  7) ;- (ADC) Channel 7
-// - -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// - -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// - -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-AT91C_ADC_EOC0            EQU (0x1 <<  0) ;- (ADC) End of Conversion
-AT91C_ADC_EOC1            EQU (0x1 <<  1) ;- (ADC) End of Conversion
-AT91C_ADC_EOC2            EQU (0x1 <<  2) ;- (ADC) End of Conversion
-AT91C_ADC_EOC3            EQU (0x1 <<  3) ;- (ADC) End of Conversion
-AT91C_ADC_EOC4            EQU (0x1 <<  4) ;- (ADC) End of Conversion
-AT91C_ADC_EOC5            EQU (0x1 <<  5) ;- (ADC) End of Conversion
-AT91C_ADC_EOC6            EQU (0x1 <<  6) ;- (ADC) End of Conversion
-AT91C_ADC_EOC7            EQU (0x1 <<  7) ;- (ADC) End of Conversion
-AT91C_ADC_OVRE0           EQU (0x1 <<  8) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE1           EQU (0x1 <<  9) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE2           EQU (0x1 << 10) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE3           EQU (0x1 << 11) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE4           EQU (0x1 << 12) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE5           EQU (0x1 << 13) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE6           EQU (0x1 << 14) ;- (ADC) Overrun Error
-AT91C_ADC_OVRE7           EQU (0x1 << 15) ;- (ADC) Overrun Error
-AT91C_ADC_DRDY            EQU (0x1 << 16) ;- (ADC) Data Ready
-AT91C_ADC_GOVRE           EQU (0x1 << 17) ;- (ADC) General Overrun
-AT91C_ADC_ENDRX           EQU (0x1 << 18) ;- (ADC) End of Receiver Transfer
-AT91C_ADC_RXBUFF          EQU (0x1 << 19) ;- (ADC) RXBUFF Interrupt
-// - -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-AT91C_ADC_LDATA           EQU (0x3FF <<  0) ;- (ADC) Last Data Converted
-// - -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// - -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// - -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// - -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-AT91C_ADC_DATA            EQU (0x3FF <<  0) ;- (ADC) Converted Data
-// - -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// - -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// - -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// - -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// - -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// - -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// - -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// - *****************************************************************************
-// - -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
-AT91C_AES_START           EQU (0x1 <<  0) ;- (AES) Starts Processing
-AT91C_AES_SWRST           EQU (0x1 <<  8) ;- (AES) Software Reset
-AT91C_AES_LOADSEED        EQU (0x1 << 16) ;- (AES) Random Number Generator Seed Loading
-// - -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
-AT91C_AES_CIPHER          EQU (0x1 <<  0) ;- (AES) Processing Mode
-AT91C_AES_PROCDLY         EQU (0xF <<  4) ;- (AES) Processing Delay
-AT91C_AES_SMOD            EQU (0x3 <<  8) ;- (AES) Start Mode
-AT91C_AES_SMOD_MANUAL     EQU (0x0 <<  8) ;- (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-AT91C_AES_SMOD_AUTO       EQU (0x1 <<  8) ;- (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-AT91C_AES_SMOD_PDC        EQU (0x2 <<  8) ;- (AES) PDC Mode (cf datasheet).
-AT91C_AES_OPMOD           EQU (0x7 << 12) ;- (AES) Operation Mode
-AT91C_AES_OPMOD_ECB       EQU (0x0 << 12) ;- (AES) ECB Electronic CodeBook mode.
-AT91C_AES_OPMOD_CBC       EQU (0x1 << 12) ;- (AES) CBC Cipher Block Chaining mode.
-AT91C_AES_OPMOD_OFB       EQU (0x2 << 12) ;- (AES) OFB Output Feedback mode.
-AT91C_AES_OPMOD_CFB       EQU (0x3 << 12) ;- (AES) CFB Cipher Feedback mode.
-AT91C_AES_OPMOD_CTR       EQU (0x4 << 12) ;- (AES) CTR Counter mode.
-AT91C_AES_LOD             EQU (0x1 << 15) ;- (AES) Last Output Data Mode
-AT91C_AES_CFBS            EQU (0x7 << 16) ;- (AES) Cipher Feedback Data Size
-AT91C_AES_CFBS_128_BIT    EQU (0x0 << 16) ;- (AES) 128-bit.
-AT91C_AES_CFBS_64_BIT     EQU (0x1 << 16) ;- (AES) 64-bit.
-AT91C_AES_CFBS_32_BIT     EQU (0x2 << 16) ;- (AES) 32-bit.
-AT91C_AES_CFBS_16_BIT     EQU (0x3 << 16) ;- (AES) 16-bit.
-AT91C_AES_CFBS_8_BIT      EQU (0x4 << 16) ;- (AES) 8-bit.
-AT91C_AES_CKEY            EQU (0xF << 20) ;- (AES) Countermeasure Key
-AT91C_AES_CTYPE           EQU (0x1F << 24) ;- (AES) Countermeasure Type
-AT91C_AES_CTYPE_TYPE1_EN  EQU (0x1 << 24) ;- (AES) Countermeasure type 1 is enabled.
-AT91C_AES_CTYPE_TYPE2_EN  EQU (0x2 << 24) ;- (AES) Countermeasure type 2 is enabled.
-AT91C_AES_CTYPE_TYPE3_EN  EQU (0x4 << 24) ;- (AES) Countermeasure type 3 is enabled.
-AT91C_AES_CTYPE_TYPE4_EN  EQU (0x8 << 24) ;- (AES) Countermeasure type 4 is enabled.
-AT91C_AES_CTYPE_TYPE5_EN  EQU (0x10 << 24) ;- (AES) Countermeasure type 5 is enabled.
-// - -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
-AT91C_AES_DATRDY          EQU (0x1 <<  0) ;- (AES) DATRDY
-AT91C_AES_ENDRX           EQU (0x1 <<  1) ;- (AES) PDC Read Buffer End
-AT91C_AES_ENDTX           EQU (0x1 <<  2) ;- (AES) PDC Write Buffer End
-AT91C_AES_RXBUFF          EQU (0x1 <<  3) ;- (AES) PDC Read Buffer Full
-AT91C_AES_TXBUFE          EQU (0x1 <<  4) ;- (AES) PDC Write Buffer Empty
-AT91C_AES_URAD            EQU (0x1 <<  8) ;- (AES) Unspecified Register Access Detection
-// - -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
-// - -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
-// - -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
-AT91C_AES_URAT            EQU (0x7 << 12) ;- (AES) Unspecified Register Access Type Status
-AT91C_AES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (AES) Input data register written during the data processing in PDC mode.
-AT91C_AES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (AES) Output data register read during the data processing.
-AT91C_AES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (AES) Mode register written during the data processing.
-AT91C_AES_URAT_OUT_DAT_READ_SUBKEY EQU (0x3 << 12) ;- (AES) Output data register read during the sub-keys generation.
-AT91C_AES_URAT_MODEREG_WRITE_SUBKEY EQU (0x4 << 12) ;- (AES) Mode register written during the sub-keys generation.
-AT91C_AES_URAT_WO_REG_READ EQU (0x5 << 12) ;- (AES) Write-only register read access.
-
-// - *****************************************************************************
-// -              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// - *****************************************************************************
-// - -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
-AT91C_TDES_START          EQU (0x1 <<  0) ;- (TDES) Starts Processing
-AT91C_TDES_SWRST          EQU (0x1 <<  8) ;- (TDES) Software Reset
-// - -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
-AT91C_TDES_CIPHER         EQU (0x1 <<  0) ;- (TDES) Processing Mode
-AT91C_TDES_TDESMOD        EQU (0x1 <<  1) ;- (TDES) Single or Triple DES Mode
-AT91C_TDES_KEYMOD         EQU (0x1 <<  4) ;- (TDES) Key Mode
-AT91C_TDES_SMOD           EQU (0x3 <<  8) ;- (TDES) Start Mode
-AT91C_TDES_SMOD_MANUAL    EQU (0x0 <<  8) ;- (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-AT91C_TDES_SMOD_AUTO      EQU (0x1 <<  8) ;- (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-AT91C_TDES_SMOD_PDC       EQU (0x2 <<  8) ;- (TDES) PDC Mode (cf datasheet).
-AT91C_TDES_OPMOD          EQU (0x3 << 12) ;- (TDES) Operation Mode
-AT91C_TDES_OPMOD_ECB      EQU (0x0 << 12) ;- (TDES) ECB Electronic CodeBook mode.
-AT91C_TDES_OPMOD_CBC      EQU (0x1 << 12) ;- (TDES) CBC Cipher Block Chaining mode.
-AT91C_TDES_OPMOD_OFB      EQU (0x2 << 12) ;- (TDES) OFB Output Feedback mode.
-AT91C_TDES_OPMOD_CFB      EQU (0x3 << 12) ;- (TDES) CFB Cipher Feedback mode.
-AT91C_TDES_LOD            EQU (0x1 << 15) ;- (TDES) Last Output Data Mode
-AT91C_TDES_CFBS           EQU (0x3 << 16) ;- (TDES) Cipher Feedback Data Size
-AT91C_TDES_CFBS_64_BIT    EQU (0x0 << 16) ;- (TDES) 64-bit.
-AT91C_TDES_CFBS_32_BIT    EQU (0x1 << 16) ;- (TDES) 32-bit.
-AT91C_TDES_CFBS_16_BIT    EQU (0x2 << 16) ;- (TDES) 16-bit.
-AT91C_TDES_CFBS_8_BIT     EQU (0x3 << 16) ;- (TDES) 8-bit.
-// - -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
-AT91C_TDES_DATRDY         EQU (0x1 <<  0) ;- (TDES) DATRDY
-AT91C_TDES_ENDRX          EQU (0x1 <<  1) ;- (TDES) PDC Read Buffer End
-AT91C_TDES_ENDTX          EQU (0x1 <<  2) ;- (TDES) PDC Write Buffer End
-AT91C_TDES_RXBUFF         EQU (0x1 <<  3) ;- (TDES) PDC Read Buffer Full
-AT91C_TDES_TXBUFE         EQU (0x1 <<  4) ;- (TDES) PDC Write Buffer Empty
-AT91C_TDES_URAD           EQU (0x1 <<  8) ;- (TDES) Unspecified Register Access Detection
-// - -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
-// - -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
-// - -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
-AT91C_TDES_URAT           EQU (0x3 << 12) ;- (TDES) Unspecified Register Access Type Status
-AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC EQU (0x0 << 12) ;- (TDES) Input data register written during the data processing in PDC mode.
-AT91C_TDES_URAT_OUT_DAT_READ_DATPROC EQU (0x1 << 12) ;- (TDES) Output data register read during the data processing.
-AT91C_TDES_URAT_MODEREG_WRITE_DATPROC EQU (0x2 << 12) ;- (TDES) Mode register written during the data processing.
-AT91C_TDES_URAT_WO_REG_READ EQU (0x3 << 12) ;- (TDES) Write-only register read access.
-
-// - *****************************************************************************
-// -               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// - *****************************************************************************
-// - ========== Register definition for SYS peripheral ========== 
-// - ========== Register definition for AIC peripheral ========== 
-AT91C_AIC_IVR             EQU (0xFFFFF100) ;- (AIC) IRQ Vector Register
-AT91C_AIC_SMR             EQU (0xFFFFF000) ;- (AIC) Source Mode Register
-AT91C_AIC_FVR             EQU (0xFFFFF104) ;- (AIC) FIQ Vector Register
-AT91C_AIC_DCR             EQU (0xFFFFF138) ;- (AIC) Debug Control Register (Protect)
-AT91C_AIC_EOICR           EQU (0xFFFFF130) ;- (AIC) End of Interrupt Command Register
-AT91C_AIC_SVR             EQU (0xFFFFF080) ;- (AIC) Source Vector Register
-AT91C_AIC_FFSR            EQU (0xFFFFF148) ;- (AIC) Fast Forcing Status Register
-AT91C_AIC_ICCR            EQU (0xFFFFF128) ;- (AIC) Interrupt Clear Command Register
-AT91C_AIC_ISR             EQU (0xFFFFF108) ;- (AIC) Interrupt Status Register
-AT91C_AIC_IMR             EQU (0xFFFFF110) ;- (AIC) Interrupt Mask Register
-AT91C_AIC_IPR             EQU (0xFFFFF10C) ;- (AIC) Interrupt Pending Register
-AT91C_AIC_FFER            EQU (0xFFFFF140) ;- (AIC) Fast Forcing Enable Register
-AT91C_AIC_IECR            EQU (0xFFFFF120) ;- (AIC) Interrupt Enable Command Register
-AT91C_AIC_ISCR            EQU (0xFFFFF12C) ;- (AIC) Interrupt Set Command Register
-AT91C_AIC_FFDR            EQU (0xFFFFF144) ;- (AIC) Fast Forcing Disable Register
-AT91C_AIC_CISR            EQU (0xFFFFF114) ;- (AIC) Core Interrupt Status Register
-AT91C_AIC_IDCR            EQU (0xFFFFF124) ;- (AIC) Interrupt Disable Command Register
-AT91C_AIC_SPU             EQU (0xFFFFF134) ;- (AIC) Spurious Vector Register
-// - ========== Register definition for PDC_DBGU peripheral ========== 
-AT91C_DBGU_TCR            EQU (0xFFFFF30C) ;- (PDC_DBGU) Transmit Counter Register
-AT91C_DBGU_RNPR           EQU (0xFFFFF310) ;- (PDC_DBGU) Receive Next Pointer Register
-AT91C_DBGU_TNPR           EQU (0xFFFFF318) ;- (PDC_DBGU) Transmit Next Pointer Register
-AT91C_DBGU_TPR            EQU (0xFFFFF308) ;- (PDC_DBGU) Transmit Pointer Register
-AT91C_DBGU_RPR            EQU (0xFFFFF300) ;- (PDC_DBGU) Receive Pointer Register
-AT91C_DBGU_RCR            EQU (0xFFFFF304) ;- (PDC_DBGU) Receive Counter Register
-AT91C_DBGU_RNCR           EQU (0xFFFFF314) ;- (PDC_DBGU) Receive Next Counter Register
-AT91C_DBGU_PTCR           EQU (0xFFFFF320) ;- (PDC_DBGU) PDC Transfer Control Register
-AT91C_DBGU_PTSR           EQU (0xFFFFF324) ;- (PDC_DBGU) PDC Transfer Status Register
-AT91C_DBGU_TNCR           EQU (0xFFFFF31C) ;- (PDC_DBGU) Transmit Next Counter Register
-// - ========== Register definition for DBGU peripheral ========== 
-AT91C_DBGU_EXID           EQU (0xFFFFF244) ;- (DBGU) Chip ID Extension Register
-AT91C_DBGU_BRGR           EQU (0xFFFFF220) ;- (DBGU) Baud Rate Generator Register
-AT91C_DBGU_IDR            EQU (0xFFFFF20C) ;- (DBGU) Interrupt Disable Register
-AT91C_DBGU_CSR            EQU (0xFFFFF214) ;- (DBGU) Channel Status Register
-AT91C_DBGU_CIDR           EQU (0xFFFFF240) ;- (DBGU) Chip ID Register
-AT91C_DBGU_MR             EQU (0xFFFFF204) ;- (DBGU) Mode Register
-AT91C_DBGU_IMR            EQU (0xFFFFF210) ;- (DBGU) Interrupt Mask Register
-AT91C_DBGU_CR             EQU (0xFFFFF200) ;- (DBGU) Control Register
-AT91C_DBGU_FNTR           EQU (0xFFFFF248) ;- (DBGU) Force NTRST Register
-AT91C_DBGU_THR            EQU (0xFFFFF21C) ;- (DBGU) Transmitter Holding Register
-AT91C_DBGU_RHR            EQU (0xFFFFF218) ;- (DBGU) Receiver Holding Register
-AT91C_DBGU_IER            EQU (0xFFFFF208) ;- (DBGU) Interrupt Enable Register
-// - ========== Register definition for PIOA peripheral ========== 
-AT91C_PIOA_ODR            EQU (0xFFFFF414) ;- (PIOA) Output Disable Registerr
-AT91C_PIOA_SODR           EQU (0xFFFFF430) ;- (PIOA) Set Output Data Register
-AT91C_PIOA_ISR            EQU (0xFFFFF44C) ;- (PIOA) Interrupt Status Register
-AT91C_PIOA_ABSR           EQU (0xFFFFF478) ;- (PIOA) AB Select Status Register
-AT91C_PIOA_IER            EQU (0xFFFFF440) ;- (PIOA) Interrupt Enable Register
-AT91C_PIOA_PPUDR          EQU (0xFFFFF460) ;- (PIOA) Pull-up Disable Register
-AT91C_PIOA_IMR            EQU (0xFFFFF448) ;- (PIOA) Interrupt Mask Register
-AT91C_PIOA_PER            EQU (0xFFFFF400) ;- (PIOA) PIO Enable Register
-AT91C_PIOA_IFDR           EQU (0xFFFFF424) ;- (PIOA) Input Filter Disable Register
-AT91C_PIOA_OWDR           EQU (0xFFFFF4A4) ;- (PIOA) Output Write Disable Register
-AT91C_PIOA_MDSR           EQU (0xFFFFF458) ;- (PIOA) Multi-driver Status Register
-AT91C_PIOA_IDR            EQU (0xFFFFF444) ;- (PIOA) Interrupt Disable Register
-AT91C_PIOA_ODSR           EQU (0xFFFFF438) ;- (PIOA) Output Data Status Register
-AT91C_PIOA_PPUSR          EQU (0xFFFFF468) ;- (PIOA) Pull-up Status Register
-AT91C_PIOA_OWSR           EQU (0xFFFFF4A8) ;- (PIOA) Output Write Status Register
-AT91C_PIOA_BSR            EQU (0xFFFFF474) ;- (PIOA) Select B Register
-AT91C_PIOA_OWER           EQU (0xFFFFF4A0) ;- (PIOA) Output Write Enable Register
-AT91C_PIOA_IFER           EQU (0xFFFFF420) ;- (PIOA) Input Filter Enable Register
-AT91C_PIOA_PDSR           EQU (0xFFFFF43C) ;- (PIOA) Pin Data Status Register
-AT91C_PIOA_PPUER          EQU (0xFFFFF464) ;- (PIOA) Pull-up Enable Register
-AT91C_PIOA_OSR            EQU (0xFFFFF418) ;- (PIOA) Output Status Register
-AT91C_PIOA_ASR            EQU (0xFFFFF470) ;- (PIOA) Select A Register
-AT91C_PIOA_MDDR           EQU (0xFFFFF454) ;- (PIOA) Multi-driver Disable Register
-AT91C_PIOA_CODR           EQU (0xFFFFF434) ;- (PIOA) Clear Output Data Register
-AT91C_PIOA_MDER           EQU (0xFFFFF450) ;- (PIOA) Multi-driver Enable Register
-AT91C_PIOA_PDR            EQU (0xFFFFF404) ;- (PIOA) PIO Disable Register
-AT91C_PIOA_IFSR           EQU (0xFFFFF428) ;- (PIOA) Input Filter Status Register
-AT91C_PIOA_OER            EQU (0xFFFFF410) ;- (PIOA) Output Enable Register
-AT91C_PIOA_PSR            EQU (0xFFFFF408) ;- (PIOA) PIO Status Register
-// - ========== Register definition for PIOB peripheral ========== 
-AT91C_PIOB_OWDR           EQU (0xFFFFF6A4) ;- (PIOB) Output Write Disable Register
-AT91C_PIOB_MDER           EQU (0xFFFFF650) ;- (PIOB) Multi-driver Enable Register
-AT91C_PIOB_PPUSR          EQU (0xFFFFF668) ;- (PIOB) Pull-up Status Register
-AT91C_PIOB_IMR            EQU (0xFFFFF648) ;- (PIOB) Interrupt Mask Register
-AT91C_PIOB_ASR            EQU (0xFFFFF670) ;- (PIOB) Select A Register
-AT91C_PIOB_PPUDR          EQU (0xFFFFF660) ;- (PIOB) Pull-up Disable Register
-AT91C_PIOB_PSR            EQU (0xFFFFF608) ;- (PIOB) PIO Status Register
-AT91C_PIOB_IER            EQU (0xFFFFF640) ;- (PIOB) Interrupt Enable Register
-AT91C_PIOB_CODR           EQU (0xFFFFF634) ;- (PIOB) Clear Output Data Register
-AT91C_PIOB_OWER           EQU (0xFFFFF6A0) ;- (PIOB) Output Write Enable Register
-AT91C_PIOB_ABSR           EQU (0xFFFFF678) ;- (PIOB) AB Select Status Register
-AT91C_PIOB_IFDR           EQU (0xFFFFF624) ;- (PIOB) Input Filter Disable Register
-AT91C_PIOB_PDSR           EQU (0xFFFFF63C) ;- (PIOB) Pin Data Status Register
-AT91C_PIOB_IDR            EQU (0xFFFFF644) ;- (PIOB) Interrupt Disable Register
-AT91C_PIOB_OWSR           EQU (0xFFFFF6A8) ;- (PIOB) Output Write Status Register
-AT91C_PIOB_PDR            EQU (0xFFFFF604) ;- (PIOB) PIO Disable Register
-AT91C_PIOB_ODR            EQU (0xFFFFF614) ;- (PIOB) Output Disable Registerr
-AT91C_PIOB_IFSR           EQU (0xFFFFF628) ;- (PIOB) Input Filter Status Register
-AT91C_PIOB_PPUER          EQU (0xFFFFF664) ;- (PIOB) Pull-up Enable Register
-AT91C_PIOB_SODR           EQU (0xFFFFF630) ;- (PIOB) Set Output Data Register
-AT91C_PIOB_ISR            EQU (0xFFFFF64C) ;- (PIOB) Interrupt Status Register
-AT91C_PIOB_ODSR           EQU (0xFFFFF638) ;- (PIOB) Output Data Status Register
-AT91C_PIOB_OSR            EQU (0xFFFFF618) ;- (PIOB) Output Status Register
-AT91C_PIOB_MDSR           EQU (0xFFFFF658) ;- (PIOB) Multi-driver Status Register
-AT91C_PIOB_IFER           EQU (0xFFFFF620) ;- (PIOB) Input Filter Enable Register
-AT91C_PIOB_BSR            EQU (0xFFFFF674) ;- (PIOB) Select B Register
-AT91C_PIOB_MDDR           EQU (0xFFFFF654) ;- (PIOB) Multi-driver Disable Register
-AT91C_PIOB_OER            EQU (0xFFFFF610) ;- (PIOB) Output Enable Register
-AT91C_PIOB_PER            EQU (0xFFFFF600) ;- (PIOB) PIO Enable Register
-// - ========== Register definition for CKGR peripheral ========== 
-AT91C_CKGR_MOR            EQU (0xFFFFFC20) ;- (CKGR) Main Oscillator Register
-AT91C_CKGR_PLLR           EQU (0xFFFFFC2C) ;- (CKGR) PLL Register
-AT91C_CKGR_MCFR           EQU (0xFFFFFC24) ;- (CKGR) Main Clock  Frequency Register
-// - ========== Register definition for PMC peripheral ========== 
-AT91C_PMC_IDR             EQU (0xFFFFFC64) ;- (PMC) Interrupt Disable Register
-AT91C_PMC_MOR             EQU (0xFFFFFC20) ;- (PMC) Main Oscillator Register
-AT91C_PMC_PLLR            EQU (0xFFFFFC2C) ;- (PMC) PLL Register
-AT91C_PMC_PCER            EQU (0xFFFFFC10) ;- (PMC) Peripheral Clock Enable Register
-AT91C_PMC_PCKR            EQU (0xFFFFFC40) ;- (PMC) Programmable Clock Register
-AT91C_PMC_MCKR            EQU (0xFFFFFC30) ;- (PMC) Master Clock Register
-AT91C_PMC_SCDR            EQU (0xFFFFFC04) ;- (PMC) System Clock Disable Register
-AT91C_PMC_PCDR            EQU (0xFFFFFC14) ;- (PMC) Peripheral Clock Disable Register
-AT91C_PMC_SCSR            EQU (0xFFFFFC08) ;- (PMC) System Clock Status Register
-AT91C_PMC_PCSR            EQU (0xFFFFFC18) ;- (PMC) Peripheral Clock Status Register
-AT91C_PMC_MCFR            EQU (0xFFFFFC24) ;- (PMC) Main Clock  Frequency Register
-AT91C_PMC_SCER            EQU (0xFFFFFC00) ;- (PMC) System Clock Enable Register
-AT91C_PMC_IMR             EQU (0xFFFFFC6C) ;- (PMC) Interrupt Mask Register
-AT91C_PMC_IER             EQU (0xFFFFFC60) ;- (PMC) Interrupt Enable Register
-AT91C_PMC_SR              EQU (0xFFFFFC68) ;- (PMC) Status Register
-// - ========== Register definition for RSTC peripheral ========== 
-AT91C_RSTC_RCR            EQU (0xFFFFFD00) ;- (RSTC) Reset Control Register
-AT91C_RSTC_RMR            EQU (0xFFFFFD08) ;- (RSTC) Reset Mode Register
-AT91C_RSTC_RSR            EQU (0xFFFFFD04) ;- (RSTC) Reset Status Register
-// - ========== Register definition for RTTC peripheral ========== 
-AT91C_RTTC_RTSR           EQU (0xFFFFFD2C) ;- (RTTC) Real-time Status Register
-AT91C_RTTC_RTMR           EQU (0xFFFFFD20) ;- (RTTC) Real-time Mode Register
-AT91C_RTTC_RTVR           EQU (0xFFFFFD28) ;- (RTTC) Real-time Value Register
-AT91C_RTTC_RTAR           EQU (0xFFFFFD24) ;- (RTTC) Real-time Alarm Register
-// - ========== Register definition for PITC peripheral ========== 
-AT91C_PITC_PIVR           EQU (0xFFFFFD38) ;- (PITC) Period Interval Value Register
-AT91C_PITC_PISR           EQU (0xFFFFFD34) ;- (PITC) Period Interval Status Register
-AT91C_PITC_PIIR           EQU (0xFFFFFD3C) ;- (PITC) Period Interval Image Register
-AT91C_PITC_PIMR           EQU (0xFFFFFD30) ;- (PITC) Period Interval Mode Register
-// - ========== Register definition for WDTC peripheral ========== 
-AT91C_WDTC_WDCR           EQU (0xFFFFFD40) ;- (WDTC) Watchdog Control Register
-AT91C_WDTC_WDSR           EQU (0xFFFFFD48) ;- (WDTC) Watchdog Status Register
-AT91C_WDTC_WDMR           EQU (0xFFFFFD44) ;- (WDTC) Watchdog Mode Register
-// - ========== Register definition for VREG peripheral ========== 
-AT91C_VREG_MR             EQU (0xFFFFFD60) ;- (VREG) Voltage Regulator Mode Register
-// - ========== Register definition for MC peripheral ========== 
-AT91C_MC_ASR              EQU (0xFFFFFF04) ;- (MC) MC Abort Status Register
-AT91C_MC_RCR              EQU (0xFFFFFF00) ;- (MC) MC Remap Control Register
-AT91C_MC_FCR              EQU (0xFFFFFF64) ;- (MC) MC Flash Command Register
-AT91C_MC_AASR             EQU (0xFFFFFF08) ;- (MC) MC Abort Address Status Register
-AT91C_MC_FSR              EQU (0xFFFFFF68) ;- (MC) MC Flash Status Register
-AT91C_MC_FMR              EQU (0xFFFFFF60) ;- (MC) MC Flash Mode Register
-// - ========== Register definition for PDC_SPI1 peripheral ========== 
-AT91C_SPI1_PTCR           EQU (0xFFFE4120) ;- (PDC_SPI1) PDC Transfer Control Register
-AT91C_SPI1_RPR            EQU (0xFFFE4100) ;- (PDC_SPI1) Receive Pointer Register
-AT91C_SPI1_TNCR           EQU (0xFFFE411C) ;- (PDC_SPI1) Transmit Next Counter Register
-AT91C_SPI1_TPR            EQU (0xFFFE4108) ;- (PDC_SPI1) Transmit Pointer Register
-AT91C_SPI1_TNPR           EQU (0xFFFE4118) ;- (PDC_SPI1) Transmit Next Pointer Register
-AT91C_SPI1_TCR            EQU (0xFFFE410C) ;- (PDC_SPI1) Transmit Counter Register
-AT91C_SPI1_RCR            EQU (0xFFFE4104) ;- (PDC_SPI1) Receive Counter Register
-AT91C_SPI1_RNPR           EQU (0xFFFE4110) ;- (PDC_SPI1) Receive Next Pointer Register
-AT91C_SPI1_RNCR           EQU (0xFFFE4114) ;- (PDC_SPI1) Receive Next Counter Register
-AT91C_SPI1_PTSR           EQU (0xFFFE4124) ;- (PDC_SPI1) PDC Transfer Status Register
-// - ========== Register definition for SPI1 peripheral ========== 
-AT91C_SPI1_IMR            EQU (0xFFFE401C) ;- (SPI1) Interrupt Mask Register
-AT91C_SPI1_IER            EQU (0xFFFE4014) ;- (SPI1) Interrupt Enable Register
-AT91C_SPI1_MR             EQU (0xFFFE4004) ;- (SPI1) Mode Register
-AT91C_SPI1_RDR            EQU (0xFFFE4008) ;- (SPI1) Receive Data Register
-AT91C_SPI1_IDR            EQU (0xFFFE4018) ;- (SPI1) Interrupt Disable Register
-AT91C_SPI1_SR             EQU (0xFFFE4010) ;- (SPI1) Status Register
-AT91C_SPI1_TDR            EQU (0xFFFE400C) ;- (SPI1) Transmit Data Register
-AT91C_SPI1_CR             EQU (0xFFFE4000) ;- (SPI1) Control Register
-AT91C_SPI1_CSR            EQU (0xFFFE4030) ;- (SPI1) Chip Select Register
-// - ========== Register definition for PDC_SPI0 peripheral ========== 
-AT91C_SPI0_PTCR           EQU (0xFFFE0120) ;- (PDC_SPI0) PDC Transfer Control Register
-AT91C_SPI0_TPR            EQU (0xFFFE0108) ;- (PDC_SPI0) Transmit Pointer Register
-AT91C_SPI0_TCR            EQU (0xFFFE010C) ;- (PDC_SPI0) Transmit Counter Register
-AT91C_SPI0_RCR            EQU (0xFFFE0104) ;- (PDC_SPI0) Receive Counter Register
-AT91C_SPI0_PTSR           EQU (0xFFFE0124) ;- (PDC_SPI0) PDC Transfer Status Register
-AT91C_SPI0_RNPR           EQU (0xFFFE0110) ;- (PDC_SPI0) Receive Next Pointer Register
-AT91C_SPI0_RPR            EQU (0xFFFE0100) ;- (PDC_SPI0) Receive Pointer Register
-AT91C_SPI0_TNCR           EQU (0xFFFE011C) ;- (PDC_SPI0) Transmit Next Counter Register
-AT91C_SPI0_RNCR           EQU (0xFFFE0114) ;- (PDC_SPI0) Receive Next Counter Register
-AT91C_SPI0_TNPR           EQU (0xFFFE0118) ;- (PDC_SPI0) Transmit Next Pointer Register
-// - ========== Register definition for SPI0 peripheral ========== 
-AT91C_SPI0_IER            EQU (0xFFFE0014) ;- (SPI0) Interrupt Enable Register
-AT91C_SPI0_SR             EQU (0xFFFE0010) ;- (SPI0) Status Register
-AT91C_SPI0_IDR            EQU (0xFFFE0018) ;- (SPI0) Interrupt Disable Register
-AT91C_SPI0_CR             EQU (0xFFFE0000) ;- (SPI0) Control Register
-AT91C_SPI0_MR             EQU (0xFFFE0004) ;- (SPI0) Mode Register
-AT91C_SPI0_IMR            EQU (0xFFFE001C) ;- (SPI0) Interrupt Mask Register
-AT91C_SPI0_TDR            EQU (0xFFFE000C) ;- (SPI0) Transmit Data Register
-AT91C_SPI0_RDR            EQU (0xFFFE0008) ;- (SPI0) Receive Data Register
-AT91C_SPI0_CSR            EQU (0xFFFE0030) ;- (SPI0) Chip Select Register
-// - ========== Register definition for PDC_US1 peripheral ========== 
-AT91C_US1_RNCR            EQU (0xFFFC4114) ;- (PDC_US1) Receive Next Counter Register
-AT91C_US1_PTCR            EQU (0xFFFC4120) ;- (PDC_US1) PDC Transfer Control Register
-AT91C_US1_TCR             EQU (0xFFFC410C) ;- (PDC_US1) Transmit Counter Register
-AT91C_US1_PTSR            EQU (0xFFFC4124) ;- (PDC_US1) PDC Transfer Status Register
-AT91C_US1_TNPR            EQU (0xFFFC4118) ;- (PDC_US1) Transmit Next Pointer Register
-AT91C_US1_RCR             EQU (0xFFFC4104) ;- (PDC_US1) Receive Counter Register
-AT91C_US1_RNPR            EQU (0xFFFC4110) ;- (PDC_US1) Receive Next Pointer Register
-AT91C_US1_RPR             EQU (0xFFFC4100) ;- (PDC_US1) Receive Pointer Register
-AT91C_US1_TNCR            EQU (0xFFFC411C) ;- (PDC_US1) Transmit Next Counter Register
-AT91C_US1_TPR             EQU (0xFFFC4108) ;- (PDC_US1) Transmit Pointer Register
-// - ========== Register definition for US1 peripheral ========== 
-AT91C_US1_IF              EQU (0xFFFC404C) ;- (US1) IRDA_FILTER Register
-AT91C_US1_NER             EQU (0xFFFC4044) ;- (US1) Nb Errors Register
-AT91C_US1_RTOR            EQU (0xFFFC4024) ;- (US1) Receiver Time-out Register
-AT91C_US1_CSR             EQU (0xFFFC4014) ;- (US1) Channel Status Register
-AT91C_US1_IDR             EQU (0xFFFC400C) ;- (US1) Interrupt Disable Register
-AT91C_US1_IER             EQU (0xFFFC4008) ;- (US1) Interrupt Enable Register
-AT91C_US1_THR             EQU (0xFFFC401C) ;- (US1) Transmitter Holding Register
-AT91C_US1_TTGR            EQU (0xFFFC4028) ;- (US1) Transmitter Time-guard Register
-AT91C_US1_RHR             EQU (0xFFFC4018) ;- (US1) Receiver Holding Register
-AT91C_US1_BRGR            EQU (0xFFFC4020) ;- (US1) Baud Rate Generator Register
-AT91C_US1_IMR             EQU (0xFFFC4010) ;- (US1) Interrupt Mask Register
-AT91C_US1_FIDI            EQU (0xFFFC4040) ;- (US1) FI_DI_Ratio Register
-AT91C_US1_CR              EQU (0xFFFC4000) ;- (US1) Control Register
-AT91C_US1_MR              EQU (0xFFFC4004) ;- (US1) Mode Register
-// - ========== Register definition for PDC_US0 peripheral ========== 
-AT91C_US0_TNPR            EQU (0xFFFC0118) ;- (PDC_US0) Transmit Next Pointer Register
-AT91C_US0_RNPR            EQU (0xFFFC0110) ;- (PDC_US0) Receive Next Pointer Register
-AT91C_US0_TCR             EQU (0xFFFC010C) ;- (PDC_US0) Transmit Counter Register
-AT91C_US0_PTCR            EQU (0xFFFC0120) ;- (PDC_US0) PDC Transfer Control Register
-AT91C_US0_PTSR            EQU (0xFFFC0124) ;- (PDC_US0) PDC Transfer Status Register
-AT91C_US0_TNCR            EQU (0xFFFC011C) ;- (PDC_US0) Transmit Next Counter Register
-AT91C_US0_TPR             EQU (0xFFFC0108) ;- (PDC_US0) Transmit Pointer Register
-AT91C_US0_RCR             EQU (0xFFFC0104) ;- (PDC_US0) Receive Counter Register
-AT91C_US0_RPR             EQU (0xFFFC0100) ;- (PDC_US0) Receive Pointer Register
-AT91C_US0_RNCR            EQU (0xFFFC0114) ;- (PDC_US0) Receive Next Counter Register
-// - ========== Register definition for US0 peripheral ========== 
-AT91C_US0_BRGR            EQU (0xFFFC0020) ;- (US0) Baud Rate Generator Register
-AT91C_US0_NER             EQU (0xFFFC0044) ;- (US0) Nb Errors Register
-AT91C_US0_CR              EQU (0xFFFC0000) ;- (US0) Control Register
-AT91C_US0_IMR             EQU (0xFFFC0010) ;- (US0) Interrupt Mask Register
-AT91C_US0_FIDI            EQU (0xFFFC0040) ;- (US0) FI_DI_Ratio Register
-AT91C_US0_TTGR            EQU (0xFFFC0028) ;- (US0) Transmitter Time-guard Register
-AT91C_US0_MR              EQU (0xFFFC0004) ;- (US0) Mode Register
-AT91C_US0_RTOR            EQU (0xFFFC0024) ;- (US0) Receiver Time-out Register
-AT91C_US0_CSR             EQU (0xFFFC0014) ;- (US0) Channel Status Register
-AT91C_US0_RHR             EQU (0xFFFC0018) ;- (US0) Receiver Holding Register
-AT91C_US0_IDR             EQU (0xFFFC000C) ;- (US0) Interrupt Disable Register
-AT91C_US0_THR             EQU (0xFFFC001C) ;- (US0) Transmitter Holding Register
-AT91C_US0_IF              EQU (0xFFFC004C) ;- (US0) IRDA_FILTER Register
-AT91C_US0_IER             EQU (0xFFFC0008) ;- (US0) Interrupt Enable Register
-// - ========== Register definition for PDC_SSC peripheral ========== 
-AT91C_SSC_TNCR            EQU (0xFFFD411C) ;- (PDC_SSC) Transmit Next Counter Register
-AT91C_SSC_RPR             EQU (0xFFFD4100) ;- (PDC_SSC) Receive Pointer Register
-AT91C_SSC_RNCR            EQU (0xFFFD4114) ;- (PDC_SSC) Receive Next Counter Register
-AT91C_SSC_TPR             EQU (0xFFFD4108) ;- (PDC_SSC) Transmit Pointer Register
-AT91C_SSC_PTCR            EQU (0xFFFD4120) ;- (PDC_SSC) PDC Transfer Control Register
-AT91C_SSC_TCR             EQU (0xFFFD410C) ;- (PDC_SSC) Transmit Counter Register
-AT91C_SSC_RCR             EQU (0xFFFD4104) ;- (PDC_SSC) Receive Counter Register
-AT91C_SSC_RNPR            EQU (0xFFFD4110) ;- (PDC_SSC) Receive Next Pointer Register
-AT91C_SSC_TNPR            EQU (0xFFFD4118) ;- (PDC_SSC) Transmit Next Pointer Register
-AT91C_SSC_PTSR            EQU (0xFFFD4124) ;- (PDC_SSC) PDC Transfer Status Register
-// - ========== Register definition for SSC peripheral ========== 
-AT91C_SSC_RHR             EQU (0xFFFD4020) ;- (SSC) Receive Holding Register
-AT91C_SSC_RSHR            EQU (0xFFFD4030) ;- (SSC) Receive Sync Holding Register
-AT91C_SSC_TFMR            EQU (0xFFFD401C) ;- (SSC) Transmit Frame Mode Register
-AT91C_SSC_IDR             EQU (0xFFFD4048) ;- (SSC) Interrupt Disable Register
-AT91C_SSC_THR             EQU (0xFFFD4024) ;- (SSC) Transmit Holding Register
-AT91C_SSC_RCMR            EQU (0xFFFD4010) ;- (SSC) Receive Clock ModeRegister
-AT91C_SSC_IER             EQU (0xFFFD4044) ;- (SSC) Interrupt Enable Register
-AT91C_SSC_TSHR            EQU (0xFFFD4034) ;- (SSC) Transmit Sync Holding Register
-AT91C_SSC_SR              EQU (0xFFFD4040) ;- (SSC) Status Register
-AT91C_SSC_CMR             EQU (0xFFFD4004) ;- (SSC) Clock Mode Register
-AT91C_SSC_TCMR            EQU (0xFFFD4018) ;- (SSC) Transmit Clock Mode Register
-AT91C_SSC_CR              EQU (0xFFFD4000) ;- (SSC) Control Register
-AT91C_SSC_IMR             EQU (0xFFFD404C) ;- (SSC) Interrupt Mask Register
-AT91C_SSC_RFMR            EQU (0xFFFD4014) ;- (SSC) Receive Frame Mode Register
-// - ========== Register definition for TWI peripheral ========== 
-AT91C_TWI_IER             EQU (0xFFFB8024) ;- (TWI) Interrupt Enable Register
-AT91C_TWI_CR              EQU (0xFFFB8000) ;- (TWI) Control Register
-AT91C_TWI_SR              EQU (0xFFFB8020) ;- (TWI) Status Register
-AT91C_TWI_IMR             EQU (0xFFFB802C) ;- (TWI) Interrupt Mask Register
-AT91C_TWI_THR             EQU (0xFFFB8034) ;- (TWI) Transmit Holding Register
-AT91C_TWI_IDR             EQU (0xFFFB8028) ;- (TWI) Interrupt Disable Register
-AT91C_TWI_IADR            EQU (0xFFFB800C) ;- (TWI) Internal Address Register
-AT91C_TWI_MMR             EQU (0xFFFB8004) ;- (TWI) Master Mode Register
-AT91C_TWI_CWGR            EQU (0xFFFB8010) ;- (TWI) Clock Waveform Generator Register
-AT91C_TWI_RHR             EQU (0xFFFB8030) ;- (TWI) Receive Holding Register
-// - ========== Register definition for PWMC_CH3 peripheral ========== 
-AT91C_PWMC_CH3_CUPDR      EQU (0xFFFCC270) ;- (PWMC_CH3) Channel Update Register
-AT91C_PWMC_CH3_Reserved   EQU (0xFFFCC274) ;- (PWMC_CH3) Reserved
-AT91C_PWMC_CH3_CPRDR      EQU (0xFFFCC268) ;- (PWMC_CH3) Channel Period Register
-AT91C_PWMC_CH3_CDTYR      EQU (0xFFFCC264) ;- (PWMC_CH3) Channel Duty Cycle Register
-AT91C_PWMC_CH3_CCNTR      EQU (0xFFFCC26C) ;- (PWMC_CH3) Channel Counter Register
-AT91C_PWMC_CH3_CMR        EQU (0xFFFCC260) ;- (PWMC_CH3) Channel Mode Register
-// - ========== Register definition for PWMC_CH2 peripheral ========== 
-AT91C_PWMC_CH2_Reserved   EQU (0xFFFCC254) ;- (PWMC_CH2) Reserved
-AT91C_PWMC_CH2_CMR        EQU (0xFFFCC240) ;- (PWMC_CH2) Channel Mode Register
-AT91C_PWMC_CH2_CCNTR      EQU (0xFFFCC24C) ;- (PWMC_CH2) Channel Counter Register
-AT91C_PWMC_CH2_CPRDR      EQU (0xFFFCC248) ;- (PWMC_CH2) Channel Period Register
-AT91C_PWMC_CH2_CUPDR      EQU (0xFFFCC250) ;- (PWMC_CH2) Channel Update Register
-AT91C_PWMC_CH2_CDTYR      EQU (0xFFFCC244) ;- (PWMC_CH2) Channel Duty Cycle Register
-// - ========== Register definition for PWMC_CH1 peripheral ========== 
-AT91C_PWMC_CH1_Reserved   EQU (0xFFFCC234) ;- (PWMC_CH1) Reserved
-AT91C_PWMC_CH1_CUPDR      EQU (0xFFFCC230) ;- (PWMC_CH1) Channel Update Register
-AT91C_PWMC_CH1_CPRDR      EQU (0xFFFCC228) ;- (PWMC_CH1) Channel Period Register
-AT91C_PWMC_CH1_CCNTR      EQU (0xFFFCC22C) ;- (PWMC_CH1) Channel Counter Register
-AT91C_PWMC_CH1_CDTYR      EQU (0xFFFCC224) ;- (PWMC_CH1) Channel Duty Cycle Register
-AT91C_PWMC_CH1_CMR        EQU (0xFFFCC220) ;- (PWMC_CH1) Channel Mode Register
-// - ========== Register definition for PWMC_CH0 peripheral ========== 
-AT91C_PWMC_CH0_Reserved   EQU (0xFFFCC214) ;- (PWMC_CH0) Reserved
-AT91C_PWMC_CH0_CPRDR      EQU (0xFFFCC208) ;- (PWMC_CH0) Channel Period Register
-AT91C_PWMC_CH0_CDTYR      EQU (0xFFFCC204) ;- (PWMC_CH0) Channel Duty Cycle Register
-AT91C_PWMC_CH0_CMR        EQU (0xFFFCC200) ;- (PWMC_CH0) Channel Mode Register
-AT91C_PWMC_CH0_CUPDR      EQU (0xFFFCC210) ;- (PWMC_CH0) Channel Update Register
-AT91C_PWMC_CH0_CCNTR      EQU (0xFFFCC20C) ;- (PWMC_CH0) Channel Counter Register
-// - ========== Register definition for PWMC peripheral ========== 
-AT91C_PWMC_IDR            EQU (0xFFFCC014) ;- (PWMC) PWMC Interrupt Disable Register
-AT91C_PWMC_DIS            EQU (0xFFFCC008) ;- (PWMC) PWMC Disable Register
-AT91C_PWMC_IER            EQU (0xFFFCC010) ;- (PWMC) PWMC Interrupt Enable Register
-AT91C_PWMC_VR             EQU (0xFFFCC0FC) ;- (PWMC) PWMC Version Register
-AT91C_PWMC_ISR            EQU (0xFFFCC01C) ;- (PWMC) PWMC Interrupt Status Register
-AT91C_PWMC_SR             EQU (0xFFFCC00C) ;- (PWMC) PWMC Status Register
-AT91C_PWMC_IMR            EQU (0xFFFCC018) ;- (PWMC) PWMC Interrupt Mask Register
-AT91C_PWMC_MR             EQU (0xFFFCC000) ;- (PWMC) PWMC Mode Register
-AT91C_PWMC_ENA            EQU (0xFFFCC004) ;- (PWMC) PWMC Enable Register
-// - ========== Register definition for UDP peripheral ========== 
-AT91C_UDP_IMR             EQU (0xFFFB0018) ;- (UDP) Interrupt Mask Register
-AT91C_UDP_FADDR           EQU (0xFFFB0008) ;- (UDP) Function Address Register
-AT91C_UDP_NUM             EQU (0xFFFB0000) ;- (UDP) Frame Number Register
-AT91C_UDP_FDR             EQU (0xFFFB0050) ;- (UDP) Endpoint FIFO Data Register
-AT91C_UDP_ISR             EQU (0xFFFB001C) ;- (UDP) Interrupt Status Register
-AT91C_UDP_CSR             EQU (0xFFFB0030) ;- (UDP) Endpoint Control and Status Register
-AT91C_UDP_IDR             EQU (0xFFFB0014) ;- (UDP) Interrupt Disable Register
-AT91C_UDP_ICR             EQU (0xFFFB0020) ;- (UDP) Interrupt Clear Register
-AT91C_UDP_RSTEP           EQU (0xFFFB0028) ;- (UDP) Reset Endpoint Register
-AT91C_UDP_TXVC            EQU (0xFFFB0074) ;- (UDP) Transceiver Control Register
-AT91C_UDP_GLBSTATE        EQU (0xFFFB0004) ;- (UDP) Global State Register
-AT91C_UDP_IER             EQU (0xFFFB0010) ;- (UDP) Interrupt Enable Register
-// - ========== Register definition for TC0 peripheral ========== 
-AT91C_TC0_SR              EQU (0xFFFA0020) ;- (TC0) Status Register
-AT91C_TC0_RC              EQU (0xFFFA001C) ;- (TC0) Register C
-AT91C_TC0_RB              EQU (0xFFFA0018) ;- (TC0) Register B
-AT91C_TC0_CCR             EQU (0xFFFA0000) ;- (TC0) Channel Control Register
-AT91C_TC0_CMR             EQU (0xFFFA0004) ;- (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC0_IER             EQU (0xFFFA0024) ;- (TC0) Interrupt Enable Register
-AT91C_TC0_RA              EQU (0xFFFA0014) ;- (TC0) Register A
-AT91C_TC0_IDR             EQU (0xFFFA0028) ;- (TC0) Interrupt Disable Register
-AT91C_TC0_CV              EQU (0xFFFA0010) ;- (TC0) Counter Value
-AT91C_TC0_IMR             EQU (0xFFFA002C) ;- (TC0) Interrupt Mask Register
-// - ========== Register definition for TC1 peripheral ========== 
-AT91C_TC1_RB              EQU (0xFFFA0058) ;- (TC1) Register B
-AT91C_TC1_CCR             EQU (0xFFFA0040) ;- (TC1) Channel Control Register
-AT91C_TC1_IER             EQU (0xFFFA0064) ;- (TC1) Interrupt Enable Register
-AT91C_TC1_IDR             EQU (0xFFFA0068) ;- (TC1) Interrupt Disable Register
-AT91C_TC1_SR              EQU (0xFFFA0060) ;- (TC1) Status Register
-AT91C_TC1_CMR             EQU (0xFFFA0044) ;- (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC1_RA              EQU (0xFFFA0054) ;- (TC1) Register A
-AT91C_TC1_RC              EQU (0xFFFA005C) ;- (TC1) Register C
-AT91C_TC1_IMR             EQU (0xFFFA006C) ;- (TC1) Interrupt Mask Register
-AT91C_TC1_CV              EQU (0xFFFA0050) ;- (TC1) Counter Value
-// - ========== Register definition for TC2 peripheral ========== 
-AT91C_TC2_CMR             EQU (0xFFFA0084) ;- (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-AT91C_TC2_CCR             EQU (0xFFFA0080) ;- (TC2) Channel Control Register
-AT91C_TC2_CV              EQU (0xFFFA0090) ;- (TC2) Counter Value
-AT91C_TC2_RA              EQU (0xFFFA0094) ;- (TC2) Register A
-AT91C_TC2_RB              EQU (0xFFFA0098) ;- (TC2) Register B
-AT91C_TC2_IDR             EQU (0xFFFA00A8) ;- (TC2) Interrupt Disable Register
-AT91C_TC2_IMR             EQU (0xFFFA00AC) ;- (TC2) Interrupt Mask Register
-AT91C_TC2_RC              EQU (0xFFFA009C) ;- (TC2) Register C
-AT91C_TC2_IER             EQU (0xFFFA00A4) ;- (TC2) Interrupt Enable Register
-AT91C_TC2_SR              EQU (0xFFFA00A0) ;- (TC2) Status Register
-// - ========== Register definition for TCB peripheral ========== 
-AT91C_TCB_BMR             EQU (0xFFFA00C4) ;- (TCB) TC Block Mode Register
-AT91C_TCB_BCR             EQU (0xFFFA00C0) ;- (TCB) TC Block Control Register
-// - ========== Register definition for CAN_MB0 peripheral ========== 
-AT91C_CAN_MB0_MDL         EQU (0xFFFD0214) ;- (CAN_MB0) MailBox Data Low Register
-AT91C_CAN_MB0_MAM         EQU (0xFFFD0204) ;- (CAN_MB0) MailBox Acceptance Mask Register
-AT91C_CAN_MB0_MCR         EQU (0xFFFD021C) ;- (CAN_MB0) MailBox Control Register
-AT91C_CAN_MB0_MID         EQU (0xFFFD0208) ;- (CAN_MB0) MailBox ID Register
-AT91C_CAN_MB0_MSR         EQU (0xFFFD0210) ;- (CAN_MB0) MailBox Status Register
-AT91C_CAN_MB0_MFID        EQU (0xFFFD020C) ;- (CAN_MB0) MailBox Family ID Register
-AT91C_CAN_MB0_MDH         EQU (0xFFFD0218) ;- (CAN_MB0) MailBox Data High Register
-AT91C_CAN_MB0_MMR         EQU (0xFFFD0200) ;- (CAN_MB0) MailBox Mode Register
-// - ========== Register definition for CAN_MB1 peripheral ========== 
-AT91C_CAN_MB1_MDL         EQU (0xFFFD0234) ;- (CAN_MB1) MailBox Data Low Register
-AT91C_CAN_MB1_MID         EQU (0xFFFD0228) ;- (CAN_MB1) MailBox ID Register
-AT91C_CAN_MB1_MMR         EQU (0xFFFD0220) ;- (CAN_MB1) MailBox Mode Register
-AT91C_CAN_MB1_MSR         EQU (0xFFFD0230) ;- (CAN_MB1) MailBox Status Register
-AT91C_CAN_MB1_MAM         EQU (0xFFFD0224) ;- (CAN_MB1) MailBox Acceptance Mask Register
-AT91C_CAN_MB1_MDH         EQU (0xFFFD0238) ;- (CAN_MB1) MailBox Data High Register
-AT91C_CAN_MB1_MCR         EQU (0xFFFD023C) ;- (CAN_MB1) MailBox Control Register
-AT91C_CAN_MB1_MFID        EQU (0xFFFD022C) ;- (CAN_MB1) MailBox Family ID Register
-// - ========== Register definition for CAN_MB2 peripheral ========== 
-AT91C_CAN_MB2_MCR         EQU (0xFFFD025C) ;- (CAN_MB2) MailBox Control Register
-AT91C_CAN_MB2_MDH         EQU (0xFFFD0258) ;- (CAN_MB2) MailBox Data High Register
-AT91C_CAN_MB2_MID         EQU (0xFFFD0248) ;- (CAN_MB2) MailBox ID Register
-AT91C_CAN_MB2_MDL         EQU (0xFFFD0254) ;- (CAN_MB2) MailBox Data Low Register
-AT91C_CAN_MB2_MMR         EQU (0xFFFD0240) ;- (CAN_MB2) MailBox Mode Register
-AT91C_CAN_MB2_MAM         EQU (0xFFFD0244) ;- (CAN_MB2) MailBox Acceptance Mask Register
-AT91C_CAN_MB2_MFID        EQU (0xFFFD024C) ;- (CAN_MB2) MailBox Family ID Register
-AT91C_CAN_MB2_MSR         EQU (0xFFFD0250) ;- (CAN_MB2) MailBox Status Register
-// - ========== Register definition for CAN_MB3 peripheral ========== 
-AT91C_CAN_MB3_MFID        EQU (0xFFFD026C) ;- (CAN_MB3) MailBox Family ID Register
-AT91C_CAN_MB3_MAM         EQU (0xFFFD0264) ;- (CAN_MB3) MailBox Acceptance Mask Register
-AT91C_CAN_MB3_MID         EQU (0xFFFD0268) ;- (CAN_MB3) MailBox ID Register
-AT91C_CAN_MB3_MCR         EQU (0xFFFD027C) ;- (CAN_MB3) MailBox Control Register
-AT91C_CAN_MB3_MMR         EQU (0xFFFD0260) ;- (CAN_MB3) MailBox Mode Register
-AT91C_CAN_MB3_MSR         EQU (0xFFFD0270) ;- (CAN_MB3) MailBox Status Register
-AT91C_CAN_MB3_MDL         EQU (0xFFFD0274) ;- (CAN_MB3) MailBox Data Low Register
-AT91C_CAN_MB3_MDH         EQU (0xFFFD0278) ;- (CAN_MB3) MailBox Data High Register
-// - ========== Register definition for CAN_MB4 peripheral ========== 
-AT91C_CAN_MB4_MID         EQU (0xFFFD0288) ;- (CAN_MB4) MailBox ID Register
-AT91C_CAN_MB4_MMR         EQU (0xFFFD0280) ;- (CAN_MB4) MailBox Mode Register
-AT91C_CAN_MB4_MDH         EQU (0xFFFD0298) ;- (CAN_MB4) MailBox Data High Register
-AT91C_CAN_MB4_MFID        EQU (0xFFFD028C) ;- (CAN_MB4) MailBox Family ID Register
-AT91C_CAN_MB4_MSR         EQU (0xFFFD0290) ;- (CAN_MB4) MailBox Status Register
-AT91C_CAN_MB4_MCR         EQU (0xFFFD029C) ;- (CAN_MB4) MailBox Control Register
-AT91C_CAN_MB4_MDL         EQU (0xFFFD0294) ;- (CAN_MB4) MailBox Data Low Register
-AT91C_CAN_MB4_MAM         EQU (0xFFFD0284) ;- (CAN_MB4) MailBox Acceptance Mask Register
-// - ========== Register definition for CAN_MB5 peripheral ========== 
-AT91C_CAN_MB5_MSR         EQU (0xFFFD02B0) ;- (CAN_MB5) MailBox Status Register
-AT91C_CAN_MB5_MCR         EQU (0xFFFD02BC) ;- (CAN_MB5) MailBox Control Register
-AT91C_CAN_MB5_MFID        EQU (0xFFFD02AC) ;- (CAN_MB5) MailBox Family ID Register
-AT91C_CAN_MB5_MDH         EQU (0xFFFD02B8) ;- (CAN_MB5) MailBox Data High Register
-AT91C_CAN_MB5_MID         EQU (0xFFFD02A8) ;- (CAN_MB5) MailBox ID Register
-AT91C_CAN_MB5_MMR         EQU (0xFFFD02A0) ;- (CAN_MB5) MailBox Mode Register
-AT91C_CAN_MB5_MDL         EQU (0xFFFD02B4) ;- (CAN_MB5) MailBox Data Low Register
-AT91C_CAN_MB5_MAM         EQU (0xFFFD02A4) ;- (CAN_MB5) MailBox Acceptance Mask Register
-// - ========== Register definition for CAN_MB6 peripheral ========== 
-AT91C_CAN_MB6_MFID        EQU (0xFFFD02CC) ;- (CAN_MB6) MailBox Family ID Register
-AT91C_CAN_MB6_MID         EQU (0xFFFD02C8) ;- (CAN_MB6) MailBox ID Register
-AT91C_CAN_MB6_MAM         EQU (0xFFFD02C4) ;- (CAN_MB6) MailBox Acceptance Mask Register
-AT91C_CAN_MB6_MSR         EQU (0xFFFD02D0) ;- (CAN_MB6) MailBox Status Register
-AT91C_CAN_MB6_MDL         EQU (0xFFFD02D4) ;- (CAN_MB6) MailBox Data Low Register
-AT91C_CAN_MB6_MCR         EQU (0xFFFD02DC) ;- (CAN_MB6) MailBox Control Register
-AT91C_CAN_MB6_MDH         EQU (0xFFFD02D8) ;- (CAN_MB6) MailBox Data High Register
-AT91C_CAN_MB6_MMR         EQU (0xFFFD02C0) ;- (CAN_MB6) MailBox Mode Register
-// - ========== Register definition for CAN_MB7 peripheral ========== 
-AT91C_CAN_MB7_MCR         EQU (0xFFFD02FC) ;- (CAN_MB7) MailBox Control Register
-AT91C_CAN_MB7_MDH         EQU (0xFFFD02F8) ;- (CAN_MB7) MailBox Data High Register
-AT91C_CAN_MB7_MFID        EQU (0xFFFD02EC) ;- (CAN_MB7) MailBox Family ID Register
-AT91C_CAN_MB7_MDL         EQU (0xFFFD02F4) ;- (CAN_MB7) MailBox Data Low Register
-AT91C_CAN_MB7_MID         EQU (0xFFFD02E8) ;- (CAN_MB7) MailBox ID Register
-AT91C_CAN_MB7_MMR         EQU (0xFFFD02E0) ;- (CAN_MB7) MailBox Mode Register
-AT91C_CAN_MB7_MAM         EQU (0xFFFD02E4) ;- (CAN_MB7) MailBox Acceptance Mask Register
-AT91C_CAN_MB7_MSR         EQU (0xFFFD02F0) ;- (CAN_MB7) MailBox Status Register
-// - ========== Register definition for CAN peripheral ========== 
-AT91C_CAN_TCR             EQU (0xFFFD0024) ;- (CAN) Transfer Command Register
-AT91C_CAN_IMR             EQU (0xFFFD000C) ;- (CAN) Interrupt Mask Register
-AT91C_CAN_IER             EQU (0xFFFD0004) ;- (CAN) Interrupt Enable Register
-AT91C_CAN_ECR             EQU (0xFFFD0020) ;- (CAN) Error Counter Register
-AT91C_CAN_TIMESTP         EQU (0xFFFD001C) ;- (CAN) Time Stamp Register
-AT91C_CAN_MR              EQU (0xFFFD0000) ;- (CAN) Mode Register
-AT91C_CAN_IDR             EQU (0xFFFD0008) ;- (CAN) Interrupt Disable Register
-AT91C_CAN_ACR             EQU (0xFFFD0028) ;- (CAN) Abort Command Register
-AT91C_CAN_TIM             EQU (0xFFFD0018) ;- (CAN) Timer Register
-AT91C_CAN_SR              EQU (0xFFFD0010) ;- (CAN) Status Register
-AT91C_CAN_BR              EQU (0xFFFD0014) ;- (CAN) Baudrate Register
-AT91C_CAN_VR              EQU (0xFFFD00FC) ;- (CAN) Version Register
-// - ========== Register definition for EMAC peripheral ========== 
-AT91C_EMAC_ISR            EQU (0xFFFDC024) ;- (EMAC) Interrupt Status Register
-AT91C_EMAC_SA4H           EQU (0xFFFDC0B4) ;- (EMAC) Specific Address 4 Top, Last 2 bytes
-AT91C_EMAC_SA1L           EQU (0xFFFDC098) ;- (EMAC) Specific Address 1 Bottom, First 4 bytes
-AT91C_EMAC_ELE            EQU (0xFFFDC078) ;- (EMAC) Excessive Length Errors Register
-AT91C_EMAC_LCOL           EQU (0xFFFDC05C) ;- (EMAC) Late Collision Register
-AT91C_EMAC_RLE            EQU (0xFFFDC088) ;- (EMAC) Receive Length Field Mismatch Register
-AT91C_EMAC_WOL            EQU (0xFFFDC0C4) ;- (EMAC) Wake On LAN Register
-AT91C_EMAC_DTF            EQU (0xFFFDC058) ;- (EMAC) Deferred Transmission Frame Register
-AT91C_EMAC_TUND           EQU (0xFFFDC064) ;- (EMAC) Transmit Underrun Error Register
-AT91C_EMAC_NCR            EQU (0xFFFDC000) ;- (EMAC) Network Control Register
-AT91C_EMAC_SA4L           EQU (0xFFFDC0B0) ;- (EMAC) Specific Address 4 Bottom, First 4 bytes
-AT91C_EMAC_RSR            EQU (0xFFFDC020) ;- (EMAC) Receive Status Register
-AT91C_EMAC_SA3L           EQU (0xFFFDC0A8) ;- (EMAC) Specific Address 3 Bottom, First 4 bytes
-AT91C_EMAC_TSR            EQU (0xFFFDC014) ;- (EMAC) Transmit Status Register
-AT91C_EMAC_IDR            EQU (0xFFFDC02C) ;- (EMAC) Interrupt Disable Register
-AT91C_EMAC_RSE            EQU (0xFFFDC074) ;- (EMAC) Receive Symbol Errors Register
-AT91C_EMAC_ECOL           EQU (0xFFFDC060) ;- (EMAC) Excessive Collision Register
-AT91C_EMAC_TID            EQU (0xFFFDC0B8) ;- (EMAC) Type ID Checking Register
-AT91C_EMAC_HRB            EQU (0xFFFDC090) ;- (EMAC) Hash Address Bottom[31:0]
-AT91C_EMAC_TBQP           EQU (0xFFFDC01C) ;- (EMAC) Transmit Buffer Queue Pointer
-AT91C_EMAC_USRIO          EQU (0xFFFDC0C0) ;- (EMAC) USER Input/Output Register
-AT91C_EMAC_PTR            EQU (0xFFFDC038) ;- (EMAC) Pause Time Register
-AT91C_EMAC_SA2H           EQU (0xFFFDC0A4) ;- (EMAC) Specific Address 2 Top, Last 2 bytes
-AT91C_EMAC_ROV            EQU (0xFFFDC070) ;- (EMAC) Receive Overrun Errors Register
-AT91C_EMAC_ALE            EQU (0xFFFDC054) ;- (EMAC) Alignment Error Register
-AT91C_EMAC_RJA            EQU (0xFFFDC07C) ;- (EMAC) Receive Jabbers Register
-AT91C_EMAC_RBQP           EQU (0xFFFDC018) ;- (EMAC) Receive Buffer Queue Pointer
-AT91C_EMAC_TPF            EQU (0xFFFDC08C) ;- (EMAC) Transmitted Pause Frames Register
-AT91C_EMAC_NCFGR          EQU (0xFFFDC004) ;- (EMAC) Network Configuration Register
-AT91C_EMAC_HRT            EQU (0xFFFDC094) ;- (EMAC) Hash Address Top[63:32]
-AT91C_EMAC_USF            EQU (0xFFFDC080) ;- (EMAC) Undersize Frames Register
-AT91C_EMAC_FCSE           EQU (0xFFFDC050) ;- (EMAC) Frame Check Sequence Error Register
-AT91C_EMAC_TPQ            EQU (0xFFFDC0BC) ;- (EMAC) Transmit Pause Quantum Register
-AT91C_EMAC_MAN            EQU (0xFFFDC034) ;- (EMAC) PHY Maintenance Register
-AT91C_EMAC_FTO            EQU (0xFFFDC040) ;- (EMAC) Frames Transmitted OK Register
-AT91C_EMAC_REV            EQU (0xFFFDC0FC) ;- (EMAC) Revision Register
-AT91C_EMAC_IMR            EQU (0xFFFDC030) ;- (EMAC) Interrupt Mask Register
-AT91C_EMAC_SCF            EQU (0xFFFDC044) ;- (EMAC) Single Collision Frame Register
-AT91C_EMAC_PFR            EQU (0xFFFDC03C) ;- (EMAC) Pause Frames received Register
-AT91C_EMAC_MCF            EQU (0xFFFDC048) ;- (EMAC) Multiple Collision Frame Register
-AT91C_EMAC_NSR            EQU (0xFFFDC008) ;- (EMAC) Network Status Register
-AT91C_EMAC_SA2L           EQU (0xFFFDC0A0) ;- (EMAC) Specific Address 2 Bottom, First 4 bytes
-AT91C_EMAC_FRO            EQU (0xFFFDC04C) ;- (EMAC) Frames Received OK Register
-AT91C_EMAC_IER            EQU (0xFFFDC028) ;- (EMAC) Interrupt Enable Register
-AT91C_EMAC_SA1H           EQU (0xFFFDC09C) ;- (EMAC) Specific Address 1 Top, Last 2 bytes
-AT91C_EMAC_CSE            EQU (0xFFFDC068) ;- (EMAC) Carrier Sense Error Register
-AT91C_EMAC_SA3H           EQU (0xFFFDC0AC) ;- (EMAC) Specific Address 3 Top, Last 2 bytes
-AT91C_EMAC_RRE            EQU (0xFFFDC06C) ;- (EMAC) Receive Ressource Error Register
-AT91C_EMAC_STE            EQU (0xFFFDC084) ;- (EMAC) SQE Test Error Register
-// - ========== Register definition for PDC_ADC peripheral ========== 
-AT91C_ADC_PTSR            EQU (0xFFFD8124) ;- (PDC_ADC) PDC Transfer Status Register
-AT91C_ADC_PTCR            EQU (0xFFFD8120) ;- (PDC_ADC) PDC Transfer Control Register
-AT91C_ADC_TNPR            EQU (0xFFFD8118) ;- (PDC_ADC) Transmit Next Pointer Register
-AT91C_ADC_TNCR            EQU (0xFFFD811C) ;- (PDC_ADC) Transmit Next Counter Register
-AT91C_ADC_RNPR            EQU (0xFFFD8110) ;- (PDC_ADC) Receive Next Pointer Register
-AT91C_ADC_RNCR            EQU (0xFFFD8114) ;- (PDC_ADC) Receive Next Counter Register
-AT91C_ADC_RPR             EQU (0xFFFD8100) ;- (PDC_ADC) Receive Pointer Register
-AT91C_ADC_TCR             EQU (0xFFFD810C) ;- (PDC_ADC) Transmit Counter Register
-AT91C_ADC_TPR             EQU (0xFFFD8108) ;- (PDC_ADC) Transmit Pointer Register
-AT91C_ADC_RCR             EQU (0xFFFD8104) ;- (PDC_ADC) Receive Counter Register
-// - ========== Register definition for ADC peripheral ========== 
-AT91C_ADC_CDR2            EQU (0xFFFD8038) ;- (ADC) ADC Channel Data Register 2
-AT91C_ADC_CDR3            EQU (0xFFFD803C) ;- (ADC) ADC Channel Data Register 3
-AT91C_ADC_CDR0            EQU (0xFFFD8030) ;- (ADC) ADC Channel Data Register 0
-AT91C_ADC_CDR5            EQU (0xFFFD8044) ;- (ADC) ADC Channel Data Register 5
-AT91C_ADC_CHDR            EQU (0xFFFD8014) ;- (ADC) ADC Channel Disable Register
-AT91C_ADC_SR              EQU (0xFFFD801C) ;- (ADC) ADC Status Register
-AT91C_ADC_CDR4            EQU (0xFFFD8040) ;- (ADC) ADC Channel Data Register 4
-AT91C_ADC_CDR1            EQU (0xFFFD8034) ;- (ADC) ADC Channel Data Register 1
-AT91C_ADC_LCDR            EQU (0xFFFD8020) ;- (ADC) ADC Last Converted Data Register
-AT91C_ADC_IDR             EQU (0xFFFD8028) ;- (ADC) ADC Interrupt Disable Register
-AT91C_ADC_CR              EQU (0xFFFD8000) ;- (ADC) ADC Control Register
-AT91C_ADC_CDR7            EQU (0xFFFD804C) ;- (ADC) ADC Channel Data Register 7
-AT91C_ADC_CDR6            EQU (0xFFFD8048) ;- (ADC) ADC Channel Data Register 6
-AT91C_ADC_IER             EQU (0xFFFD8024) ;- (ADC) ADC Interrupt Enable Register
-AT91C_ADC_CHER            EQU (0xFFFD8010) ;- (ADC) ADC Channel Enable Register
-AT91C_ADC_CHSR            EQU (0xFFFD8018) ;- (ADC) ADC Channel Status Register
-AT91C_ADC_MR              EQU (0xFFFD8004) ;- (ADC) ADC Mode Register
-AT91C_ADC_IMR             EQU (0xFFFD802C) ;- (ADC) ADC Interrupt Mask Register
-// - ========== Register definition for PDC_AES peripheral ========== 
-AT91C_AES_TPR             EQU (0xFFFA4108) ;- (PDC_AES) Transmit Pointer Register
-AT91C_AES_PTCR            EQU (0xFFFA4120) ;- (PDC_AES) PDC Transfer Control Register
-AT91C_AES_RNPR            EQU (0xFFFA4110) ;- (PDC_AES) Receive Next Pointer Register
-AT91C_AES_TNCR            EQU (0xFFFA411C) ;- (PDC_AES) Transmit Next Counter Register
-AT91C_AES_TCR             EQU (0xFFFA410C) ;- (PDC_AES) Transmit Counter Register
-AT91C_AES_RCR             EQU (0xFFFA4104) ;- (PDC_AES) Receive Counter Register
-AT91C_AES_RNCR            EQU (0xFFFA4114) ;- (PDC_AES) Receive Next Counter Register
-AT91C_AES_TNPR            EQU (0xFFFA4118) ;- (PDC_AES) Transmit Next Pointer Register
-AT91C_AES_RPR             EQU (0xFFFA4100) ;- (PDC_AES) Receive Pointer Register
-AT91C_AES_PTSR            EQU (0xFFFA4124) ;- (PDC_AES) PDC Transfer Status Register
-// - ========== Register definition for AES peripheral ========== 
-AT91C_AES_IVxR            EQU (0xFFFA4060) ;- (AES) Initialization Vector x Register
-AT91C_AES_MR              EQU (0xFFFA4004) ;- (AES) Mode Register
-AT91C_AES_VR              EQU (0xFFFA40FC) ;- (AES) AES Version Register
-AT91C_AES_ODATAxR         EQU (0xFFFA4050) ;- (AES) Output Data x Register
-AT91C_AES_IDATAxR         EQU (0xFFFA4040) ;- (AES) Input Data x Register
-AT91C_AES_CR              EQU (0xFFFA4000) ;- (AES) Control Register
-AT91C_AES_IDR             EQU (0xFFFA4014) ;- (AES) Interrupt Disable Register
-AT91C_AES_IMR             EQU (0xFFFA4018) ;- (AES) Interrupt Mask Register
-AT91C_AES_IER             EQU (0xFFFA4010) ;- (AES) Interrupt Enable Register
-AT91C_AES_KEYWxR          EQU (0xFFFA4020) ;- (AES) Key Word x Register
-AT91C_AES_ISR             EQU (0xFFFA401C) ;- (AES) Interrupt Status Register
-// - ========== Register definition for PDC_TDES peripheral ========== 
-AT91C_TDES_RNCR           EQU (0xFFFA8114) ;- (PDC_TDES) Receive Next Counter Register
-AT91C_TDES_TCR            EQU (0xFFFA810C) ;- (PDC_TDES) Transmit Counter Register
-AT91C_TDES_RCR            EQU (0xFFFA8104) ;- (PDC_TDES) Receive Counter Register
-AT91C_TDES_TNPR           EQU (0xFFFA8118) ;- (PDC_TDES) Transmit Next Pointer Register
-AT91C_TDES_RNPR           EQU (0xFFFA8110) ;- (PDC_TDES) Receive Next Pointer Register
-AT91C_TDES_RPR            EQU (0xFFFA8100) ;- (PDC_TDES) Receive Pointer Register
-AT91C_TDES_TNCR           EQU (0xFFFA811C) ;- (PDC_TDES) Transmit Next Counter Register
-AT91C_TDES_TPR            EQU (0xFFFA8108) ;- (PDC_TDES) Transmit Pointer Register
-AT91C_TDES_PTSR           EQU (0xFFFA8124) ;- (PDC_TDES) PDC Transfer Status Register
-AT91C_TDES_PTCR           EQU (0xFFFA8120) ;- (PDC_TDES) PDC Transfer Control Register
-// - ========== Register definition for TDES peripheral ========== 
-AT91C_TDES_KEY2WxR        EQU (0xFFFA8028) ;- (TDES) Key 2 Word x Register
-AT91C_TDES_KEY3WxR        EQU (0xFFFA8030) ;- (TDES) Key 3 Word x Register
-AT91C_TDES_IDR            EQU (0xFFFA8014) ;- (TDES) Interrupt Disable Register
-AT91C_TDES_VR             EQU (0xFFFA80FC) ;- (TDES) TDES Version Register
-AT91C_TDES_IVxR           EQU (0xFFFA8060) ;- (TDES) Initialization Vector x Register
-AT91C_TDES_ODATAxR        EQU (0xFFFA8050) ;- (TDES) Output Data x Register
-AT91C_TDES_IMR            EQU (0xFFFA8018) ;- (TDES) Interrupt Mask Register
-AT91C_TDES_MR             EQU (0xFFFA8004) ;- (TDES) Mode Register
-AT91C_TDES_CR             EQU (0xFFFA8000) ;- (TDES) Control Register
-AT91C_TDES_IER            EQU (0xFFFA8010) ;- (TDES) Interrupt Enable Register
-AT91C_TDES_ISR            EQU (0xFFFA801C) ;- (TDES) Interrupt Status Register
-AT91C_TDES_IDATAxR        EQU (0xFFFA8040) ;- (TDES) Input Data x Register
-AT91C_TDES_KEY1WxR        EQU (0xFFFA8020) ;- (TDES) Key 1 Word x Register
-
-// - *****************************************************************************
-// -               PIO DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_PIO_PA0             EQU (1 <<  0) ;- Pin Controlled by PA0
-AT91C_PA0_RXD0            EQU (AT91C_PIO_PA0) ;-  USART 0 Receive Data
-AT91C_PIO_PA1             EQU (1 <<  1) ;- Pin Controlled by PA1
-AT91C_PA1_TXD0            EQU (AT91C_PIO_PA1) ;-  USART 0 Transmit Data
-AT91C_PIO_PA10            EQU (1 << 10) ;- Pin Controlled by PA10
-AT91C_PA10_TWD            EQU (AT91C_PIO_PA10) ;-  TWI Two-wire Serial Data
-AT91C_PIO_PA11            EQU (1 << 11) ;- Pin Controlled by PA11
-AT91C_PA11_TWCK           EQU (AT91C_PIO_PA11) ;-  TWI Two-wire Serial Clock
-AT91C_PIO_PA12            EQU (1 << 12) ;- Pin Controlled by PA12
-AT91C_PA12_NPCS00         EQU (AT91C_PIO_PA12) ;-  SPI 0 Peripheral Chip Select 0
-AT91C_PIO_PA13            EQU (1 << 13) ;- Pin Controlled by PA13
-AT91C_PA13_NPCS01         EQU (AT91C_PIO_PA13) ;-  SPI 0 Peripheral Chip Select 1
-AT91C_PA13_PCK1           EQU (AT91C_PIO_PA13) ;-  PMC Programmable Clock Output 1
-AT91C_PIO_PA14            EQU (1 << 14) ;- Pin Controlled by PA14
-AT91C_PA14_NPCS02         EQU (AT91C_PIO_PA14) ;-  SPI 0 Peripheral Chip Select 2
-AT91C_PA14_IRQ1           EQU (AT91C_PIO_PA14) ;-  External Interrupt 1
-AT91C_PIO_PA15            EQU (1 << 15) ;- Pin Controlled by PA15
-AT91C_PA15_NPCS03         EQU (AT91C_PIO_PA15) ;-  SPI 0 Peripheral Chip Select 3
-AT91C_PA15_TCLK2          EQU (AT91C_PIO_PA15) ;-  Timer Counter 2 external clock input
-AT91C_PIO_PA16            EQU (1 << 16) ;- Pin Controlled by PA16
-AT91C_PA16_MISO0          EQU (AT91C_PIO_PA16) ;-  SPI 0 Master In Slave
-AT91C_PIO_PA17            EQU (1 << 17) ;- Pin Controlled by PA17
-AT91C_PA17_MOSI0          EQU (AT91C_PIO_PA17) ;-  SPI 0 Master Out Slave
-AT91C_PIO_PA18            EQU (1 << 18) ;- Pin Controlled by PA18
-AT91C_PA18_SPCK0          EQU (AT91C_PIO_PA18) ;-  SPI 0 Serial Clock
-AT91C_PIO_PA19            EQU (1 << 19) ;- Pin Controlled by PA19
-AT91C_PA19_CANRX          EQU (AT91C_PIO_PA19) ;-  CAN Receive
-AT91C_PIO_PA2             EQU (1 <<  2) ;- Pin Controlled by PA2
-AT91C_PA2_SCK0            EQU (AT91C_PIO_PA2) ;-  USART 0 Serial Clock
-AT91C_PA2_NPCS11          EQU (AT91C_PIO_PA2) ;-  SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PA20            EQU (1 << 20) ;- Pin Controlled by PA20
-AT91C_PA20_CANTX          EQU (AT91C_PIO_PA20) ;-  CAN Transmit
-AT91C_PIO_PA21            EQU (1 << 21) ;- Pin Controlled by PA21
-AT91C_PA21_TF             EQU (AT91C_PIO_PA21) ;-  SSC Transmit Frame Sync
-AT91C_PA21_NPCS10         EQU (AT91C_PIO_PA21) ;-  SPI 1 Peripheral Chip Select 0
-AT91C_PIO_PA22            EQU (1 << 22) ;- Pin Controlled by PA22
-AT91C_PA22_TK             EQU (AT91C_PIO_PA22) ;-  SSC Transmit Clock
-AT91C_PA22_SPCK1          EQU (AT91C_PIO_PA22) ;-  SPI 1 Serial Clock
-AT91C_PIO_PA23            EQU (1 << 23) ;- Pin Controlled by PA23
-AT91C_PA23_TD             EQU (AT91C_PIO_PA23) ;-  SSC Transmit data
-AT91C_PA23_MOSI1          EQU (AT91C_PIO_PA23) ;-  SPI 1 Master Out Slave
-AT91C_PIO_PA24            EQU (1 << 24) ;- Pin Controlled by PA24
-AT91C_PA24_RD             EQU (AT91C_PIO_PA24) ;-  SSC Receive Data
-AT91C_PA24_MISO1          EQU (AT91C_PIO_PA24) ;-  SPI 1 Master In Slave
-AT91C_PIO_PA25            EQU (1 << 25) ;- Pin Controlled by PA25
-AT91C_PA25_RK             EQU (AT91C_PIO_PA25) ;-  SSC Receive Clock
-AT91C_PA25_NPCS11         EQU (AT91C_PIO_PA25) ;-  SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PA26            EQU (1 << 26) ;- Pin Controlled by PA26
-AT91C_PA26_RF             EQU (AT91C_PIO_PA26) ;-  SSC Receive Frame Sync
-AT91C_PA26_NPCS12         EQU (AT91C_PIO_PA26) ;-  SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PA27            EQU (1 << 27) ;- Pin Controlled by PA27
-AT91C_PA27_DRXD           EQU (AT91C_PIO_PA27) ;-  DBGU Debug Receive Data
-AT91C_PA27_PCK3           EQU (AT91C_PIO_PA27) ;-  PMC Programmable Clock Output 3
-AT91C_PIO_PA28            EQU (1 << 28) ;- Pin Controlled by PA28
-AT91C_PA28_DTXD           EQU (AT91C_PIO_PA28) ;-  DBGU Debug Transmit Data
-AT91C_PIO_PA29            EQU (1 << 29) ;- Pin Controlled by PA29
-AT91C_PA29_FIQ            EQU (AT91C_PIO_PA29) ;-  AIC Fast Interrupt Input
-AT91C_PA29_NPCS13         EQU (AT91C_PIO_PA29) ;-  SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PA3             EQU (1 <<  3) ;- Pin Controlled by PA3
-AT91C_PA3_RTS0            EQU (AT91C_PIO_PA3) ;-  USART 0 Ready To Send
-AT91C_PA3_NPCS12          EQU (AT91C_PIO_PA3) ;-  SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PA30            EQU (1 << 30) ;- Pin Controlled by PA30
-AT91C_PA30_IRQ0           EQU (AT91C_PIO_PA30) ;-  External Interrupt 0
-AT91C_PA30_PCK2           EQU (AT91C_PIO_PA30) ;-  PMC Programmable Clock Output 2
-AT91C_PIO_PA4             EQU (1 <<  4) ;- Pin Controlled by PA4
-AT91C_PA4_CTS0            EQU (AT91C_PIO_PA4) ;-  USART 0 Clear To Send
-AT91C_PA4_NPCS13          EQU (AT91C_PIO_PA4) ;-  SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PA5             EQU (1 <<  5) ;- Pin Controlled by PA5
-AT91C_PA5_RXD1            EQU (AT91C_PIO_PA5) ;-  USART 1 Receive Data
-AT91C_PIO_PA6             EQU (1 <<  6) ;- Pin Controlled by PA6
-AT91C_PA6_TXD1            EQU (AT91C_PIO_PA6) ;-  USART 1 Transmit Data
-AT91C_PIO_PA7             EQU (1 <<  7) ;- Pin Controlled by PA7
-AT91C_PA7_SCK1            EQU (AT91C_PIO_PA7) ;-  USART 1 Serial Clock
-AT91C_PA7_NPCS01          EQU (AT91C_PIO_PA7) ;-  SPI 0 Peripheral Chip Select 1
-AT91C_PIO_PA8             EQU (1 <<  8) ;- Pin Controlled by PA8
-AT91C_PA8_RTS1            EQU (AT91C_PIO_PA8) ;-  USART 1 Ready To Send
-AT91C_PA8_NPCS02          EQU (AT91C_PIO_PA8) ;-  SPI 0 Peripheral Chip Select 2
-AT91C_PIO_PA9             EQU (1 <<  9) ;- Pin Controlled by PA9
-AT91C_PA9_CTS1            EQU (AT91C_PIO_PA9) ;-  USART 1 Clear To Send
-AT91C_PA9_NPCS03          EQU (AT91C_PIO_PA9) ;-  SPI 0 Peripheral Chip Select 3
-AT91C_PIO_PB0             EQU (1 <<  0) ;- Pin Controlled by PB0
-AT91C_PB0_ETXCK_EREFCK    EQU (AT91C_PIO_PB0) ;-  Ethernet MAC Transmit Clock/Reference Clock
-AT91C_PB0_PCK0            EQU (AT91C_PIO_PB0) ;-  PMC Programmable Clock Output 0
-AT91C_PIO_PB1             EQU (1 <<  1) ;- Pin Controlled by PB1
-AT91C_PB1_ETXEN           EQU (AT91C_PIO_PB1) ;-  Ethernet MAC Transmit Enable
-AT91C_PIO_PB10            EQU (1 << 10) ;- Pin Controlled by PB10
-AT91C_PB10_ETX2           EQU (AT91C_PIO_PB10) ;-  Ethernet MAC Transmit Data 2
-AT91C_PB10_NPCS11         EQU (AT91C_PIO_PB10) ;-  SPI 1 Peripheral Chip Select 1
-AT91C_PIO_PB11            EQU (1 << 11) ;- Pin Controlled by PB11
-AT91C_PB11_ETX3           EQU (AT91C_PIO_PB11) ;-  Ethernet MAC Transmit Data 3
-AT91C_PB11_NPCS12         EQU (AT91C_PIO_PB11) ;-  SPI 1 Peripheral Chip Select 2
-AT91C_PIO_PB12            EQU (1 << 12) ;- Pin Controlled by PB12
-AT91C_PB12_ETXER          EQU (AT91C_PIO_PB12) ;-  Ethernet MAC Transmikt Coding Error
-AT91C_PB12_TCLK0          EQU (AT91C_PIO_PB12) ;-  Timer Counter 0 external clock input
-AT91C_PIO_PB13            EQU (1 << 13) ;- Pin Controlled by PB13
-AT91C_PB13_ERX2           EQU (AT91C_PIO_PB13) ;-  Ethernet MAC Receive Data 2
-AT91C_PB13_NPCS01         EQU (AT91C_PIO_PB13) ;-  SPI 0 Peripheral Chip Select 1
-AT91C_PIO_PB14            EQU (1 << 14) ;- Pin Controlled by PB14
-AT91C_PB14_ERX3           EQU (AT91C_PIO_PB14) ;-  Ethernet MAC Receive Data 3
-AT91C_PB14_NPCS02         EQU (AT91C_PIO_PB14) ;-  SPI 0 Peripheral Chip Select 2
-AT91C_PIO_PB15            EQU (1 << 15) ;- Pin Controlled by PB15
-AT91C_PB15_ERXDV          EQU (AT91C_PIO_PB15) ;-  Ethernet MAC Receive Data Valid
-AT91C_PIO_PB16            EQU (1 << 16) ;- Pin Controlled by PB16
-AT91C_PB16_ECOL           EQU (AT91C_PIO_PB16) ;-  Ethernet MAC Collision Detected
-AT91C_PB16_NPCS13         EQU (AT91C_PIO_PB16) ;-  SPI 1 Peripheral Chip Select 3
-AT91C_PIO_PB17            EQU (1 << 17) ;- Pin Controlled by PB17
-AT91C_PB17_ERXCK          EQU (AT91C_PIO_PB17) ;-  Ethernet MAC Receive Clock
-AT91C_PB17_NPCS03         EQU (AT91C_PIO_PB17) ;-  SPI 0 Peripheral Chip Select 3
-AT91C_PIO_PB18            EQU (1 << 18) ;- Pin Controlled by PB18
-AT91C_PB18_EF100          EQU (AT91C_PIO_PB18) ;-  Ethernet MAC Force 100 Mbits/sec
-AT91C_PB18_ADTRG          EQU (AT91C_PIO_PB18) ;-  ADC External Trigger
-AT91C_PIO_PB19            EQU (1 << 19) ;- Pin Controlled by PB19
-AT91C_PB19_PWM0           EQU (AT91C_PIO_PB19) ;-  PWM Channel 0
-AT91C_PB19_TCLK1          EQU (AT91C_PIO_PB19) ;-  Timer Counter 1 external clock input
-AT91C_PIO_PB2             EQU (1 <<  2) ;- Pin Controlled by PB2
-AT91C_PB2_ETX0            EQU (AT91C_PIO_PB2) ;-  Ethernet MAC Transmit Data 0
-AT91C_PIO_PB20            EQU (1 << 20) ;- Pin Controlled by PB20
-AT91C_PB20_PWM1           EQU (AT91C_PIO_PB20) ;-  PWM Channel 1
-AT91C_PB20_PCK0           EQU (AT91C_PIO_PB20) ;-  PMC Programmable Clock Output 0
-AT91C_PIO_PB21            EQU (1 << 21) ;- Pin Controlled by PB21
-AT91C_PB21_PWM2           EQU (AT91C_PIO_PB21) ;-  PWM Channel 2
-AT91C_PB21_PCK1           EQU (AT91C_PIO_PB21) ;-  PMC Programmable Clock Output 1
-AT91C_PIO_PB22            EQU (1 << 22) ;- Pin Controlled by PB22
-AT91C_PB22_PWM3           EQU (AT91C_PIO_PB22) ;-  PWM Channel 3
-AT91C_PB22_PCK2           EQU (AT91C_PIO_PB22) ;-  PMC Programmable Clock Output 2
-AT91C_PIO_PB23            EQU (1 << 23) ;- Pin Controlled by PB23
-AT91C_PB23_TIOA0          EQU (AT91C_PIO_PB23) ;-  Timer Counter 0 Multipurpose Timer I/O Pin A
-AT91C_PB23_DCD1           EQU (AT91C_PIO_PB23) ;-  USART 1 Data Carrier Detect
-AT91C_PIO_PB24            EQU (1 << 24) ;- Pin Controlled by PB24
-AT91C_PB24_TIOB0          EQU (AT91C_PIO_PB24) ;-  Timer Counter 0 Multipurpose Timer I/O Pin B
-AT91C_PB24_DSR1           EQU (AT91C_PIO_PB24) ;-  USART 1 Data Set ready
-AT91C_PIO_PB25            EQU (1 << 25) ;- Pin Controlled by PB25
-AT91C_PB25_TIOA1          EQU (AT91C_PIO_PB25) ;-  Timer Counter 1 Multipurpose Timer I/O Pin A
-AT91C_PB25_DTR1           EQU (AT91C_PIO_PB25) ;-  USART 1 Data Terminal ready
-AT91C_PIO_PB26            EQU (1 << 26) ;- Pin Controlled by PB26
-AT91C_PB26_TIOB1          EQU (AT91C_PIO_PB26) ;-  Timer Counter 1 Multipurpose Timer I/O Pin B
-AT91C_PB26_RI1            EQU (AT91C_PIO_PB26) ;-  USART 1 Ring Indicator
-AT91C_PIO_PB27            EQU (1 << 27) ;- Pin Controlled by PB27
-AT91C_PB27_TIOA2          EQU (AT91C_PIO_PB27) ;-  Timer Counter 2 Multipurpose Timer I/O Pin A
-AT91C_PB27_PWM0           EQU (AT91C_PIO_PB27) ;-  PWM Channel 0
-AT91C_PIO_PB28            EQU (1 << 28) ;- Pin Controlled by PB28
-AT91C_PB28_TIOB2          EQU (AT91C_PIO_PB28) ;-  Timer Counter 2 Multipurpose Timer I/O Pin B
-AT91C_PB28_PWM1           EQU (AT91C_PIO_PB28) ;-  PWM Channel 1
-AT91C_PIO_PB29            EQU (1 << 29) ;- Pin Controlled by PB29
-AT91C_PB29_PCK1           EQU (AT91C_PIO_PB29) ;-  PMC Programmable Clock Output 1
-AT91C_PB29_PWM2           EQU (AT91C_PIO_PB29) ;-  PWM Channel 2
-AT91C_PIO_PB3             EQU (1 <<  3) ;- Pin Controlled by PB3
-AT91C_PB3_ETX1            EQU (AT91C_PIO_PB3) ;-  Ethernet MAC Transmit Data 1
-AT91C_PIO_PB30            EQU (1 << 30) ;- Pin Controlled by PB30
-AT91C_PB30_PCK2           EQU (AT91C_PIO_PB30) ;-  PMC Programmable Clock Output 2
-AT91C_PB30_PWM3           EQU (AT91C_PIO_PB30) ;-  PWM Channel 3
-AT91C_PIO_PB4             EQU (1 <<  4) ;- Pin Controlled by PB4
-AT91C_PB4_ECRS_ECRSDV     EQU (AT91C_PIO_PB4) ;-  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-AT91C_PIO_PB5             EQU (1 <<  5) ;- Pin Controlled by PB5
-AT91C_PB5_ERX0            EQU (AT91C_PIO_PB5) ;-  Ethernet MAC Receive Data 0
-AT91C_PIO_PB6             EQU (1 <<  6) ;- Pin Controlled by PB6
-AT91C_PB6_ERX1            EQU (AT91C_PIO_PB6) ;-  Ethernet MAC Receive Data 1
-AT91C_PIO_PB7             EQU (1 <<  7) ;- Pin Controlled by PB7
-AT91C_PB7_ERXER           EQU (AT91C_PIO_PB7) ;-  Ethernet MAC Receive Error
-AT91C_PIO_PB8             EQU (1 <<  8) ;- Pin Controlled by PB8
-AT91C_PB8_EMDC            EQU (AT91C_PIO_PB8) ;-  Ethernet MAC Management Data Clock
-AT91C_PIO_PB9             EQU (1 <<  9) ;- Pin Controlled by PB9
-AT91C_PB9_EMDIO           EQU (AT91C_PIO_PB9) ;-  Ethernet MAC Management Data Input/Output
-
-// - *****************************************************************************
-// -               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_ID_FIQ              EQU ( 0) ;- Advanced Interrupt Controller (FIQ)
-AT91C_ID_SYS              EQU ( 1) ;- System Peripheral
-AT91C_ID_PIOA             EQU ( 2) ;- Parallel IO Controller A
-AT91C_ID_PIOB             EQU ( 3) ;- Parallel IO Controller B
-AT91C_ID_SPI0             EQU ( 4) ;- Serial Peripheral Interface 0
-AT91C_ID_SPI1             EQU ( 5) ;- Serial Peripheral Interface 1
-AT91C_ID_US0              EQU ( 6) ;- USART 0
-AT91C_ID_US1              EQU ( 7) ;- USART 1
-AT91C_ID_SSC              EQU ( 8) ;- Serial Synchronous Controller
-AT91C_ID_TWI              EQU ( 9) ;- Two-Wire Interface
-AT91C_ID_PWMC             EQU (10) ;- PWM Controller
-AT91C_ID_UDP              EQU (11) ;- USB Device Port
-AT91C_ID_TC0              EQU (12) ;- Timer Counter 0
-AT91C_ID_TC1              EQU (13) ;- Timer Counter 1
-AT91C_ID_TC2              EQU (14) ;- Timer Counter 2
-AT91C_ID_CAN              EQU (15) ;- Control Area Network Controller
-AT91C_ID_EMAC             EQU (16) ;- Ethernet MAC
-AT91C_ID_ADC              EQU (17) ;- Analog-to-Digital Converter
-AT91C_ID_AES              EQU (18) ;- Advanced Encryption Standard 128-bit
-AT91C_ID_TDES             EQU (19) ;- Triple Data Encryption Standard
-AT91C_ID_20_Reserved      EQU (20) ;- Reserved
-AT91C_ID_21_Reserved      EQU (21) ;- Reserved
-AT91C_ID_22_Reserved      EQU (22) ;- Reserved
-AT91C_ID_23_Reserved      EQU (23) ;- Reserved
-AT91C_ID_24_Reserved      EQU (24) ;- Reserved
-AT91C_ID_25_Reserved      EQU (25) ;- Reserved
-AT91C_ID_26_Reserved      EQU (26) ;- Reserved
-AT91C_ID_27_Reserved      EQU (27) ;- Reserved
-AT91C_ID_28_Reserved      EQU (28) ;- Reserved
-AT91C_ID_29_Reserved      EQU (29) ;- Reserved
-AT91C_ID_IRQ0             EQU (30) ;- Advanced Interrupt Controller (IRQ0)
-AT91C_ID_IRQ1             EQU (31) ;- Advanced Interrupt Controller (IRQ1)
-
-// - *****************************************************************************
-// -               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_BASE_SYS            EQU (0xFFFFF000) ;- (SYS) Base Address
-AT91C_BASE_AIC            EQU (0xFFFFF000) ;- (AIC) Base Address
-AT91C_BASE_PDC_DBGU       EQU (0xFFFFF300) ;- (PDC_DBGU) Base Address
-AT91C_BASE_DBGU           EQU (0xFFFFF200) ;- (DBGU) Base Address
-AT91C_BASE_PIOA           EQU (0xFFFFF400) ;- (PIOA) Base Address
-AT91C_BASE_PIOB           EQU (0xFFFFF600) ;- (PIOB) Base Address
-AT91C_BASE_CKGR           EQU (0xFFFFFC20) ;- (CKGR) Base Address
-AT91C_BASE_PMC            EQU (0xFFFFFC00) ;- (PMC) Base Address
-AT91C_BASE_RSTC           EQU (0xFFFFFD00) ;- (RSTC) Base Address
-AT91C_BASE_RTTC           EQU (0xFFFFFD20) ;- (RTTC) Base Address
-AT91C_BASE_PITC           EQU (0xFFFFFD30) ;- (PITC) Base Address
-AT91C_BASE_WDTC           EQU (0xFFFFFD40) ;- (WDTC) Base Address
-AT91C_BASE_VREG           EQU (0xFFFFFD60) ;- (VREG) Base Address
-AT91C_BASE_MC             EQU (0xFFFFFF00) ;- (MC) Base Address
-AT91C_BASE_PDC_SPI1       EQU (0xFFFE4100) ;- (PDC_SPI1) Base Address
-AT91C_BASE_SPI1           EQU (0xFFFE4000) ;- (SPI1) Base Address
-AT91C_BASE_PDC_SPI0       EQU (0xFFFE0100) ;- (PDC_SPI0) Base Address
-AT91C_BASE_SPI0           EQU (0xFFFE0000) ;- (SPI0) Base Address
-AT91C_BASE_PDC_US1        EQU (0xFFFC4100) ;- (PDC_US1) Base Address
-AT91C_BASE_US1            EQU (0xFFFC4000) ;- (US1) Base Address
-AT91C_BASE_PDC_US0        EQU (0xFFFC0100) ;- (PDC_US0) Base Address
-AT91C_BASE_US0            EQU (0xFFFC0000) ;- (US0) Base Address
-AT91C_BASE_PDC_SSC        EQU (0xFFFD4100) ;- (PDC_SSC) Base Address
-AT91C_BASE_SSC            EQU (0xFFFD4000) ;- (SSC) Base Address
-AT91C_BASE_TWI            EQU (0xFFFB8000) ;- (TWI) Base Address
-AT91C_BASE_PWMC_CH3       EQU (0xFFFCC260) ;- (PWMC_CH3) Base Address
-AT91C_BASE_PWMC_CH2       EQU (0xFFFCC240) ;- (PWMC_CH2) Base Address
-AT91C_BASE_PWMC_CH1       EQU (0xFFFCC220) ;- (PWMC_CH1) Base Address
-AT91C_BASE_PWMC_CH0       EQU (0xFFFCC200) ;- (PWMC_CH0) Base Address
-AT91C_BASE_PWMC           EQU (0xFFFCC000) ;- (PWMC) Base Address
-AT91C_BASE_UDP            EQU (0xFFFB0000) ;- (UDP) Base Address
-AT91C_BASE_TC0            EQU (0xFFFA0000) ;- (TC0) Base Address
-AT91C_BASE_TC1            EQU (0xFFFA0040) ;- (TC1) Base Address
-AT91C_BASE_TC2            EQU (0xFFFA0080) ;- (TC2) Base Address
-AT91C_BASE_TCB            EQU (0xFFFA0000) ;- (TCB) Base Address
-AT91C_BASE_CAN_MB0        EQU (0xFFFD0200) ;- (CAN_MB0) Base Address
-AT91C_BASE_CAN_MB1        EQU (0xFFFD0220) ;- (CAN_MB1) Base Address
-AT91C_BASE_CAN_MB2        EQU (0xFFFD0240) ;- (CAN_MB2) Base Address
-AT91C_BASE_CAN_MB3        EQU (0xFFFD0260) ;- (CAN_MB3) Base Address
-AT91C_BASE_CAN_MB4        EQU (0xFFFD0280) ;- (CAN_MB4) Base Address
-AT91C_BASE_CAN_MB5        EQU (0xFFFD02A0) ;- (CAN_MB5) Base Address
-AT91C_BASE_CAN_MB6        EQU (0xFFFD02C0) ;- (CAN_MB6) Base Address
-AT91C_BASE_CAN_MB7        EQU (0xFFFD02E0) ;- (CAN_MB7) Base Address
-AT91C_BASE_CAN            EQU (0xFFFD0000) ;- (CAN) Base Address
-AT91C_BASE_EMAC           EQU (0xFFFDC000) ;- (EMAC) Base Address
-AT91C_BASE_PDC_ADC        EQU (0xFFFD8100) ;- (PDC_ADC) Base Address
-AT91C_BASE_ADC            EQU (0xFFFD8000) ;- (ADC) Base Address
-AT91C_BASE_PDC_AES        EQU (0xFFFA4100) ;- (PDC_AES) Base Address
-AT91C_BASE_AES            EQU (0xFFFA4000) ;- (AES) Base Address
-AT91C_BASE_PDC_TDES       EQU (0xFFFA8100) ;- (PDC_TDES) Base Address
-AT91C_BASE_TDES           EQU (0xFFFA8000) ;- (TDES) Base Address
-
-// - *****************************************************************************
-// -               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// - *****************************************************************************
-AT91C_ISRAM               EQU (0x00200000) ;- Internal SRAM base address
-AT91C_ISRAM_SIZE          EQU (0x00010000) ;- Internal SRAM size in byte (64 Kbyte)
-AT91C_IFLASH              EQU (0x00100000) ;- Internal ROM base address
-AT91C_IFLASH_SIZE         EQU (0x00040000) ;- Internal ROM size in byte (256 Kbyte)
-
-
-
-#endif /* AT91SAM7X256_H */
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c b/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
deleted file mode 100755
index bb2ad9b..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.c
+++ /dev/null
@@ -1,51 +0,0 @@
-//* ----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//* ----------------------------------------------------------------------------
-//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//* ----------------------------------------------------------------------------
-//* File Name           : lib_AT91SAM7X256.h
-//* Object              : AT91SAM7X256 inlined functions
-//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-//*
-//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
-//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
-//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
-//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
-//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
-//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
-//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
-//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
-//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
-//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
-//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
-//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
-//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
-//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
-//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
-//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
-//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
-//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
-//* ----------------------------------------------------------------------------
-
-
-#include "AT91SAM7X256.h"
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h b/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
deleted file mode 100755
index 5720bad..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/lib_AT91SAM7X256.h
+++ /dev/null
@@ -1,4558 +0,0 @@
-//* ----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//* ----------------------------------------------------------------------------
-//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//* ----------------------------------------------------------------------------
-//* File Name           : lib_AT91SAM7X256.h
-//* Object              : AT91SAM7X256 inlined functions
-//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-//*
-//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
-//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
-//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
-//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
-//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
-//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
-//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
-//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
-//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
-//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
-//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
-//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
-//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
-//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
-//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
-//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
-//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
-//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
-//* ----------------------------------------------------------------------------
-
-#ifndef lib_AT91SAM7X256_H
-#define lib_AT91SAM7X256_H
-
-/* *****************************************************************************
-                SOFTWARE API FOR AIC
-   ***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AIC_ConfigureIt (
-	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
-	unsigned int irq_id,     // \arg interrupt number to initialize
-	unsigned int priority,   // \arg priority to give to the interrupt
-	unsigned int src_type,   // \arg activation and sense of activation
-	void (*newHandler) (void) ) // \arg address of the interrupt handler
-{
-	unsigned int oldHandler;
-    unsigned int mask ;
-
-    oldHandler = pAic->AIC_SVR[irq_id];
-
-    mask = 0x1 << irq_id ;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Save the interrupt handler routine pointer and the interrupt priority
-    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
-    //* Store the Source Mode Register
-    pAic->AIC_SMR[irq_id] = src_type | priority  ;
-    //* Clear the interrupt on the interrupt controller
-    pAic->AIC_ICCR = mask ;
-
-	return oldHandler;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_EnableIt
-//* \brief Enable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_EnableIt (
-	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-	unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    //* Enable the interrupt on the interrupt controller
-    pAic->AIC_IECR = 0x1 << irq_id ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_DisableIt
-//* \brief Disable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_DisableIt (
-	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-	unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    unsigned int mask = 0x1 << irq_id;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = mask ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ClearIt
-//* \brief Clear corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_ClearIt (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg interrupt number to initialize
-{
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = (0x1 << irq_id);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_AcknowledgeIt
-//* \brief Acknowledge corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_AcknowledgeIt (
-	AT91PS_AIC pAic)     // \arg pointer to the AIC registers
-{
-    pAic->AIC_EOICR = pAic->AIC_EOICR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_SetExceptionVector
-//* \brief Configure vector handler
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_SetExceptionVector (
-	unsigned int *pVector, // \arg pointer to the AIC registers
-	void (*Handler) () )   // \arg Interrupt Handler
-{
-	unsigned int oldVector = *pVector;
-
-	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
-		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
-	else
-		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
-
-	return oldVector;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Trig
-//* \brief Trig an IT
-//*----------------------------------------------------------------------------
-__inline void  AT91F_AIC_Trig (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg interrupt number
-{
-	pAic->AIC_ISCR = (0x1 << irq_id) ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsActive
-//* \brief Test if an IT is active
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsActive (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg Interrupt Number
-{
-	return (pAic->AIC_ISR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsPending
-//* \brief Test if an IT is pending
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsPending (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg Interrupt Number
-{
-	return (pAic->AIC_IPR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Open
-//* \brief Set exception vectors and AIC registers to default values
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_Open(
-	AT91PS_AIC pAic,        // \arg pointer to the AIC registers
-	void (*IrqHandler) (),  // \arg Default IRQ vector exception
-	void (*FiqHandler) (),  // \arg Default FIQ vector exception
-	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
-	void (*SpuriousHandler) (), // \arg Default Spurious Handler
-	unsigned int protectMode)   // \arg Debug Control Register
-{
-	int i;
-
-	// Disable all interrupts and set IVR to the default handler
-	for (i = 0; i < 32; ++i) {
-		AT91F_AIC_DisableIt(pAic, i);
-		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
-	}
-
-	// Set the IRQ exception vector
-	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
-	// Set the Fast Interrupt exception vector
-	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
-
-	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
-	pAic->AIC_DCR = protectMode;
-}
-/* *****************************************************************************
-                SOFTWARE API FOR PDC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextRx
-//* \brief Set the next receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextRx (
-	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
-	char *address,       // \arg address to the next bloc to be received
-	unsigned int bytes)  // \arg number of bytes to be received
-{
-	pPDC->PDC_RNPR = (unsigned int) address;
-	pPDC->PDC_RNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextTx
-//* \brief Set the next transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextTx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be transmitted
-	unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-	pPDC->PDC_TNPR = (unsigned int) address;
-	pPDC->PDC_TNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetRx
-//* \brief Set the receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetRx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be received
-	unsigned int bytes)    // \arg number of bytes to be received
-{
-	pPDC->PDC_RPR = (unsigned int) address;
-	pPDC->PDC_RCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetTx
-//* \brief Set the transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetTx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be transmitted
-	unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-	pPDC->PDC_TPR = (unsigned int) address;
-	pPDC->PDC_TCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableTx
-//* \brief Enable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableTx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableRx
-//* \brief Enable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableRx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableTx
-//* \brief Disable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableTx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableRx
-//* \brief Disable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableRx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsTxEmpty
-//* \brief Test if the current transfer descriptor has been sent
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_TCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextTxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_TNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsRxEmpty
-//* \brief Test if the current transfer descriptor has been filled
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_RCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextRxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_RNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Open
-//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Open (
-	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-	AT91F_PDC_DisableRx(pPDC);
-	AT91F_PDC_DisableTx(pPDC);
-
-	//* Reset all Counter register Next buffer first
-	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-    //* Enable the RX and TX PDC transfer requests
-	AT91F_PDC_EnableRx(pPDC);
-	AT91F_PDC_EnableTx(pPDC);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Close
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Close (
-	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-	AT91F_PDC_DisableRx(pPDC);
-	AT91F_PDC_DisableTx(pPDC);
-
-	//* Reset all Counter register Next buffer first
-	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SendFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_SendFrame(
-	AT91PS_PDC pPDC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	if (AT91F_PDC_IsTxEmpty(pPDC)) {
-		//* Buffer and next buffer can be initialized
-		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
-		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
-		return 2;
-	}
-	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
-		//* Only one buffer can be initialized
-		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
-		return 1;
-	}
-	else {
-		//* All buffer are in use...
-		return 0;
-	}
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_ReceiveFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_ReceiveFrame (
-	AT91PS_PDC pPDC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	if (AT91F_PDC_IsRxEmpty(pPDC)) {
-		//* Buffer and next buffer can be initialized
-		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
-		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
-		return 2;
-	}
-	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
-		//* Only one buffer can be initialized
-		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
-		return 1;
-	}
-	else {
-		//* All buffer are in use...
-		return 0;
-	}
-}
-/* *****************************************************************************
-                SOFTWARE API FOR DBGU
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptEnable
-//* \brief Enable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptEnable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be enabled
-{
-        pDbgu->DBGU_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptDisable
-//* \brief Disable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptDisable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be disabled
-{
-        pDbgu->DBGU_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_GetInterruptMaskStatus
-//* \brief Return DBGU Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
-        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
-{
-        return pDbgu->DBGU_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_IsInterruptMasked
-//* \brief Test if DBGU Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_DBGU_IsInterruptMasked(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PIO
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPeriph
-//* \brief Enable pins to be drived by peripheral
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPeriph(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int periphAEnable,  // \arg PERIPH A to enable
-	unsigned int periphBEnable)  // \arg PERIPH B to enable
-
-{
-	pPio->PIO_ASR = periphAEnable;
-	pPio->PIO_BSR = periphBEnable;
-	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOutput
-//* \brief Enable PIO in output mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOutput(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int pioEnable)      // \arg PIO to be enabled
-{
-	pPio->PIO_PER = pioEnable; // Set in PIO mode
-	pPio->PIO_OER = pioEnable; // Configure in Output
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInput
-//* \brief Enable PIO in input mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInput(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int inputEnable)      // \arg PIO to be enabled
-{
-	// Disable output
-	pPio->PIO_ODR  = inputEnable;
-	pPio->PIO_PER  = inputEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOpendrain
-//* \brief Configure PIO in open drain
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOpendrain(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int multiDrvEnable) // \arg pio to be configured in open drain
-{
-	// Configure the multi-drive option
-	pPio->PIO_MDDR = ~multiDrvEnable;
-	pPio->PIO_MDER = multiDrvEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPullup
-//* \brief Enable pullup on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPullup(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int pullupEnable)   // \arg enable pullup on PIO
-{
-		// Connect or not Pullup
-	pPio->PIO_PPUDR = ~pullupEnable;
-	pPio->PIO_PPUER = pullupEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgDirectDrive
-//* \brief Enable direct drive on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgDirectDrive(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int directDrive)    // \arg PIO to be configured with direct drive
-
-{
-	// Configure the Direct Drive
-	pPio->PIO_OWDR  = ~directDrive;
-	pPio->PIO_OWER  = directDrive;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInputFilter
-//* \brief Enable input filter on input PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInputFilter(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int inputFilter)    // \arg PIO to be configured with input filter
-
-{
-	// Configure the Direct Drive
-	pPio->PIO_IFDR  = ~inputFilter;
-	pPio->PIO_IFER  = inputFilter;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInput
-//* \brief Return PIO input value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
-	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-	return pPio->PIO_PDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputSet
-//* \brief Test if PIO is input flag is active
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputSet(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PIO_GetInput(pPio) & flag);
-}
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_SetOutput
-//* \brief Set to 1 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_SetOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be set
-{
-	pPio->PIO_SODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ClearOutput
-//* \brief Set to 0 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ClearOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be cleared
-{
-	pPio->PIO_CODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ForceOutput
-//* \brief Force output when Direct drive option is enabled
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ForceOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be forced
-{
-	pPio->PIO_ODSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Enable
-//* \brief Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Enable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled 
-{
-        pPio->PIO_PER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Disable
-//* \brief Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Disable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled 
-{
-        pPio->PIO_PDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetStatus
-//* \brief Return PIO Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsSet
-//* \brief Test if PIO is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputEnable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be enabled
-{
-        pPio->PIO_OER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputDisable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be disabled
-{
-        pPio->PIO_ODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputStatus
-//* \brief Return PIO Output Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOuputSet
-//* \brief Test if PIO Output is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterEnable
-//* \brief Input Filter Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be enabled
-{
-        pPio->PIO_IFER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterDisable
-//* \brief Input Filter Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be disabled
-{
-        pPio->PIO_IFDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInputFilterStatus
-//* \brief Return PIO Input Filter Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IFSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputFilterSet
-//* \brief Test if PIO Input filter is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputFilterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputDataStatus
-//* \brief Return PIO Output Data Status 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status 
-	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ODSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptEnable
-//* \brief Enable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be enabled
-{
-        pPio->PIO_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptDisable
-//* \brief Disable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be disabled
-{
-        pPio->PIO_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptMaskStatus
-//* \brief Return PIO Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptMasked
-//* \brief Test if PIO Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptMasked(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptSet
-//* \brief Test if PIO Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverEnable
-//* \brief Multi Driver Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
-{
-        pPio->PIO_MDER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverDisable
-//* \brief Multi Driver Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
-{
-        pPio->PIO_MDDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetMultiDriverStatus
-//* \brief Return PIO Multi Driver Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_MDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsMultiDriverSet
-//* \brief Test if PIO MultiDriver is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsMultiDriverSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_A_RegisterSelection
-//* \brief PIO A Register Selection 
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_A_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio A register selection
-{
-        pPio->PIO_ASR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_B_RegisterSelection
-//* \brief PIO B Register Selection 
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_B_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio B register selection 
-{
-        pPio->PIO_BSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Get_AB_RegisterStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ABSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsAB_RegisterSet
-//* \brief Test if PIO AB Register is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsAB_RegisterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteEnable
-//* \brief Output Write Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be enabled
-{
-        pPio->PIO_OWER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteDisable
-//* \brief Output Write Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be disabled
-{
-        pPio->PIO_OWDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputWriteStatus
-//* \brief Return PIO Output Write Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OWSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputWriteSet
-//* \brief Test if PIO OutputWrite is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputWriteSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetCfgPullup
-//* \brief Return PIO Configuration Pullup
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup 
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PPUSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputDataStatusSet
-//* \brief Test if PIO Output Data Status is Set 
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputDataStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsCfgPullupStatusSet
-//* \brief Test if PIO Configuration Pullup Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsCfgPullupStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkEnableReg
-//* \brief Configure the System Clock Enable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkEnableReg (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int mode)
-{
-	//* Write to the SCER register
-	pPMC->PMC_SCER = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkDisableReg
-//* \brief Configure the System Clock Disable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkDisableReg (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int mode)
-{
-	//* Write to the SCDR register
-	pPMC->PMC_SCDR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetSysClkStatusReg
-//* \brief Return the System Clock Status Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
-	AT91PS_PMC pPMC // pointer to a CAN controller
-	)
-{
-	return pPMC->PMC_SCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePeriphClock
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePeriphClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-	pPMC->PMC_PCER = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePeriphClock
-//* \brief Disable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePeriphClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-	pPMC->PMC_PCDR = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetPeriphClock
-//* \brief Get peripheral clock status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetPeriphClock (
-	AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-	return pPMC->PMC_PCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscillatorReg (
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int mode)
-{
-	pCKGR->CKGR_MOR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	return pCKGR->CKGR_MOR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_EnableMainOscillator
-//* \brief Enable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_EnableMainOscillator(
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_DisableMainOscillator
-//* \brief Disable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_DisableMainOscillator (
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
-//* \brief Cfg MOR Register according to the main osc startup time
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscStartUpTime (
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
-	pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClockFreqReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	return pCKGR->CKGR_MCFR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClock
-//* \brief Return Main clock in Hz
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClock (
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgMCKReg
-//* \brief Cfg Master Clock Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgMCKReg (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int mode)
-{
-	pPMC->PMC_MCKR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMCKReg
-//* \brief Return Master Clock Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMCKReg(
-	AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-	return pPMC->PMC_MCKR;
-}
-
-//*------------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMasterClock
-//* \brief Return master clock in Hz which correponds to processor clock for ARM7
-//*------------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMasterClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	unsigned int reg = pPMC->PMC_MCKR;
-	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
-	unsigned int pllDivider, pllMultiplier;
-
-	switch (reg & AT91C_PMC_CSS) {
-		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
-			return slowClock / prescaler;
-		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
-			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
-		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
-			reg = pCKGR->CKGR_PLLR;
-			pllDivider    = (reg  & AT91C_CKGR_DIV);
-			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
-			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
-	}
-	return 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePCK (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
-	unsigned int mode)
-{
-	pPMC->PMC_PCKR[pck] = mode;
-	pPMC->PMC_SCER = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePCK (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
-{
-	pPMC->PMC_SCDR = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnableIt
-//* \brief Enable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnableIt (
-	AT91PS_PMC pPMC,     // pointer to a PMC controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pPMC->PMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisableIt
-//* \brief Disable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisableIt (
-	AT91PS_PMC pPMC, // pointer to a PMC controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pPMC->PMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetStatus
-//* \brief Return PMC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
-	AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-	return pPMC->PMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetInterruptMaskStatus
-//* \brief Return PMC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
-	AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-	return pPMC->PMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsInterruptMasked
-//* \brief Test if PMC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsInterruptMasked(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsStatusSet
-//* \brief Test if PMC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsStatusSet(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PMC_GetStatus(pPMC) & flag);
-}/* *****************************************************************************
-                SOFTWARE API FOR RSTC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTSoftReset
-//* \brief Start Software Reset
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSoftReset(
-        AT91PS_RSTC pRSTC,
-        unsigned int reset)
-{
-	pRSTC->RSTC_RCR = (0xA5000000 | reset);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTSetMode
-//* \brief Set Reset Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSetMode(
-        AT91PS_RSTC pRSTC,
-        unsigned int mode)
-{
-	pRSTC->RSTC_RMR = (0xA5000000 | mode);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTGetMode
-//* \brief Get Reset Mode
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetMode(
-        AT91PS_RSTC pRSTC)
-{
-	return (pRSTC->RSTC_RMR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTGetStatus
-//* \brief Get Reset Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetStatus(
-        AT91PS_RSTC pRSTC)
-{
-	return (pRSTC->RSTC_RSR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTIsSoftRstActive
-//* \brief Return !=0 if software reset is still not completed
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTIsSoftRstActive(
-        AT91PS_RSTC pRSTC)
-{
-	return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR RTTC
-   ***************************************************************************** */
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_SetRTT_TimeBase()
-//* \brief  Set the RTT prescaler according to the TimeBase in ms
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetTimeBase(
-        AT91PS_RTTC pRTTC, 
-        unsigned int ms)
-{
-	if (ms > 2000)
-		return 1;   // AT91C_TIME_OUT_OF_RANGE
-	pRTTC->RTTC_RTMR &= ~0xFFFF;	
-	pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);	
-	return 0;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTSetPrescaler()
-//* \brief  Set the new prescaler value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetPrescaler(
-        AT91PS_RTTC pRTTC, 
-        unsigned int rtpres)
-{
-	pRTTC->RTTC_RTMR &= ~0xFFFF;	
-	pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);	
-	return (pRTTC->RTTC_RTMR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTRestart()
-//* \brief  Restart the RTT prescaler
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTRestart(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;	
-}
-
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetAlarmINT()
-//* \brief  Enable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmINT(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ClearAlarmINT()
-//* \brief  Disable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearAlarmINT(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetRttIncINT()
-//* \brief  Enable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetRttIncINT(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ClearRttIncINT()
-//* \brief  Disable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearRttIncINT(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetAlarmValue()
-//* \brief  Set RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmValue(
-        AT91PS_RTTC pRTTC, unsigned int alarm)
-{
-	pRTTC->RTTC_RTAR = alarm;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_GetAlarmValue()
-//* \brief  Get RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetAlarmValue(
-        AT91PS_RTTC pRTTC)
-{
-	return(pRTTC->RTTC_RTAR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTGetStatus()
-//* \brief  Read the RTT status
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetStatus(
-        AT91PS_RTTC pRTTC)
-{
-	return(pRTTC->RTTC_RTSR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ReadValue()
-//* \brief  Read the RTT value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTReadValue(
-        AT91PS_RTTC pRTTC)
-{
-        register volatile unsigned int val1,val2;
-	do
-	{
-		val1 = pRTTC->RTTC_RTVR;
-		val2 = pRTTC->RTTC_RTVR;
-	}	
-	while(val1 != val2);
-	return(val1);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR PITC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITInit
-//* \brief System timer init : period in µsecond, system clock freq in MHz
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITInit(
-        AT91PS_PITC pPITC,
-        unsigned int period,
-        unsigned int pit_frequency)
-{
-	pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
-	pPITC->PITC_PIMR |= AT91C_PITC_PITEN;	 
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITSetPIV
-//* \brief Set the PIT Periodic Interval Value 
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITSetPIV(
-        AT91PS_PITC pPITC,
-        unsigned int piv)
-{
-	pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITEnableInt
-//* \brief Enable PIT periodic interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITEnableInt(
-        AT91PS_PITC pPITC)
-{
-	pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;	 
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITDisableInt
-//* \brief Disable PIT periodic interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITDisableInt(
-        AT91PS_PITC pPITC)
-{
-	pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;	 
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITGetMode
-//* \brief Read PIT mode register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetMode(
-        AT91PS_PITC pPITC)
-{
-	return(pPITC->PITC_PIMR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITGetStatus
-//* \brief Read PIT status register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetStatus(
-        AT91PS_PITC pPITC)
-{
-	return(pPITC->PITC_PISR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITGetPIIR
-//* \brief Read PIT CPIV and PICNT without ressetting the counters
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetPIIR(
-        AT91PS_PITC pPITC)
-{
-	return(pPITC->PITC_PIIR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITGetPIVR
-//* \brief Read System timer CPIV and PICNT without ressetting the counters
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetPIVR(
-        AT91PS_PITC pPITC)
-{
-	return(pPITC->PITC_PIVR);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR WDTC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTSetMode
-//* \brief Set Watchdog Mode Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_WDTSetMode(
-        AT91PS_WDTC pWDTC,
-        unsigned int Mode)
-{
-	pWDTC->WDTC_WDMR = Mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTRestart
-//* \brief Restart Watchdog
-//*----------------------------------------------------------------------------
-__inline void AT91F_WDTRestart(
-        AT91PS_WDTC pWDTC)
-{
-	pWDTC->WDTC_WDCR = 0xA5000001;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTSGettatus
-//* \brief Get Watchdog Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_WDTSGettatus(
-        AT91PS_WDTC pWDTC)
-{
-	return(pWDTC->WDTC_WDSR & 0x3);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTGetPeriod
-//* \brief Translate ms into Watchdog Compatible value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
-{
-	if ((ms < 4) || (ms > 16000))
-		return 0;
-	return((ms << 8) / 1000);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR VREG
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_VREG_Enable_LowPowerMode
-//* \brief Enable VREG Low Power Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_VREG_Enable_LowPowerMode(
-        AT91PS_VREG pVREG)
-{
-	pVREG->VREG_MR |= AT91C_VREG_PSTDBY;	 
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_VREG_Disable_LowPowerMode
-//* \brief Disable VREG Low Power Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_VREG_Disable_LowPowerMode(
-        AT91PS_VREG pVREG)
-{
-	pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;	 
-}/* *****************************************************************************
-                SOFTWARE API FOR MC
-   ***************************************************************************** */
-
-#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_Remap
-//* \brief Make Remap
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_Remap (void)     //  
-{
-    AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
-    
-    pMC->MC_RCR = AT91C_MC_RCB;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_CfgModeReg
-//* \brief Configure the EFC Mode Register of the MC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_EFC_CfgModeReg (
-	AT91PS_MC pMC, // pointer to a MC controller
-	unsigned int mode)        // mode register 
-{
-	// Write to the FMR register
-	pMC->MC_FMR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_GetModeReg
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_GetModeReg(
-	AT91PS_MC pMC) // pointer to a MC controller
-{
-	return pMC->MC_FMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_ComputeFMCN
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
-	int master_clock) // master clock in Hz
-{
-	return (master_clock/1000000 +2);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_PerformCmd
-//* \brief Perform EFC Command
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_EFC_PerformCmd (
-	AT91PS_MC pMC, // pointer to a MC controller
-    unsigned int transfer_cmd)
-{
-	pMC->MC_FCR = transfer_cmd;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_GetStatus
-//* \brief Return MC EFC Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_GetStatus(
-	AT91PS_MC pMC) // pointer to a MC controller
-{
-	return pMC->MC_FSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_IsInterruptMasked
-//* \brief Test if EFC MC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
-        AT91PS_MC pMC,   // \arg  pointer to a MC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_IsInterruptSet
-//* \brief Test if EFC MC Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
-        AT91PS_MC pMC,   // \arg  pointer to a MC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_MC_EFC_GetStatus(pMC) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR SPI
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Open
-//* \brief Open a SPI Port
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_Open (
-        const unsigned int null)  // \arg
-{
-        /* NOT DEFINED AT THIS MOMENT */
-        return ( 0 );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgCs
-//* \brief Configure SPI chip select register
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgCs (
-	AT91PS_SPI pSPI,     // pointer to a SPI controller
-	int cs,     // SPI cs number (0 to 3)
- 	int val)   //  chip select register
-{
-	//* Write to the CSR register
-	*(pSPI->SPI_CSR + cs) = val;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_EnableIt
-//* \brief Enable SPI interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_EnableIt (
-	AT91PS_SPI pSPI,     // pointer to a SPI controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pSPI->SPI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_DisableIt
-//* \brief Disable SPI interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_DisableIt (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pSPI->SPI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Reset
-//* \brief Reset the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Reset (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SWRST;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Enable
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Enable (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Disable
-//* \brief Disable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Disable (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgMode
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgMode (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	int mode)        // mode register 
-{
-	//* Write to the MR register
-	pSPI->SPI_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgPCS
-//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgPCS (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	char PCS_Device) // PCS of the Device
-{	
- 	//* Write to the MR register
-	pSPI->SPI_MR &= 0xFFF0FFFF;
-	pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_ReceiveFrame (
-	AT91PS_SPI pSPI,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pSPI->SPI_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_SendFrame(
-	AT91PS_SPI pSPI,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pSPI->SPI_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Close
-//* \brief Close SPI: disable IT disable transfert, close PDC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Close (
-	AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
-{
-    //* Reset all the Chip Select register
-    pSPI->SPI_CSR[0] = 0 ;
-    pSPI->SPI_CSR[1] = 0 ;
-    pSPI->SPI_CSR[2] = 0 ;
-    pSPI->SPI_CSR[3] = 0 ;
-
-    //* Reset the SPI mode
-    pSPI->SPI_MR = 0  ;
-
-    //* Disable all interrupts
-    pSPI->SPI_IDR = 0xFFFFFFFF ;
-
-    //* Abort the Peripheral Data Transfers
-    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
-
-    //* Disable receiver and transmitter and stop any activity immediately
-    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_PutChar (
-	AT91PS_SPI pSPI,
-	unsigned int character,
-             unsigned int cs_number )
-{
-    unsigned int value_for_cs;
-    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
-    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-__inline int AT91F_SPI_GetChar (
-	const AT91PS_SPI pSPI)
-{
-    return((pSPI->SPI_RDR) & 0xFFFF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_GetInterruptMaskStatus
-//* \brief Return SPI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
-        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
-{
-        return pSpi->SPI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_IsInterruptMasked
-//* \brief Test if SPI Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_SPI_IsInterruptMasked(
-        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR USART
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Baudrate
-//* \brief Calculate the baudrate
-//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
-                        AT91C_US_NBSTOP_1_BIT + \
-                        AT91C_US_PAR_NONE + \
-                        AT91C_US_CHRL_8_BITS + \
-                        AT91C_US_CLKS_CLOCK )
-
-//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
-                            AT91C_US_NBSTOP_1_BIT + \
-                            AT91C_US_PAR_NONE + \
-                            AT91C_US_CHRL_8_BITS + \
-                            AT91C_US_CLKS_EXT )
-
-//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
-                       AT91C_US_USMODE_NORMAL + \
-                       AT91C_US_NBSTOP_1_BIT + \
-                       AT91C_US_PAR_NONE + \
-                       AT91C_US_CHRL_8_BITS + \
-                       AT91C_US_CLKS_CLOCK )
-
-//* SCK used Label
-#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
-
-//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
-#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
-					   		 AT91C_US_CLKS_CLOCK +\
-                       		 AT91C_US_NBSTOP_1_BIT + \
-                       		 AT91C_US_PAR_EVEN + \
-                       		 AT91C_US_CHRL_8_BITS + \
-                       		 AT91C_US_CKLO +\
-                       		 AT91C_US_OVER)
-
-//* Standard IRDA mode
-#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
-                            AT91C_US_NBSTOP_1_BIT + \
-                            AT91C_US_PAR_NONE + \
-                            AT91C_US_CHRL_8_BITS + \
-                            AT91C_US_CLKS_CLOCK )
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Baudrate
-//* \brief Caluculate baud_value according to the main clock and the baud rate
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_Baudrate (
-	const unsigned int main_clock, // \arg peripheral clock
-	const unsigned int baud_rate)  // \arg UART baudrate
-{
-	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
-	if ((baud_value % 10) >= 5)
-		baud_value = (baud_value / 10) + 1;
-	else
-		baud_value /= 10;
-	return baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetBaudrate (
-	AT91PS_USART pUSART,    // \arg pointer to a USART controller
-	unsigned int mainClock, // \arg peripheral clock
-	unsigned int speed)     // \arg UART baudrate
-{
-	//* Define the baud rate divisor register
-	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetTimeguard
-//* \brief Set USART timeguard
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetTimeguard (
-	AT91PS_USART pUSART,    // \arg pointer to a USART controller
-	unsigned int timeguard) // \arg timeguard value
-{
-	//* Write the Timeguard Register
-	pUSART->US_TTGR = timeguard ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableIt
-//* \brief Enable USART IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableIt (
-	AT91PS_USART pUSART, // \arg pointer to a USART controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pUSART->US_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableIt
-//* \brief Disable USART IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableIt (
-	AT91PS_USART pUSART, // \arg pointer to a USART controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IER register
-	pUSART->US_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Configure
-//* \brief Configure USART
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_Configure (
-	AT91PS_USART pUSART,     // \arg pointer to a USART controller
-	unsigned int mainClock,  // \arg peripheral clock
-	unsigned int mode ,      // \arg mode Register to be programmed
-	unsigned int baudRate ,  // \arg baudrate to be programmed
-	unsigned int timeguard ) // \arg timeguard to be programmed
-{
-    //* Disable interrupts
-    pUSART->US_IDR = (unsigned int) -1;
-
-    //* Reset receiver and transmitter
-    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
-
-	//* Define the baud rate divisor register
-	AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
-
-	//* Write the Timeguard Register
-	AT91F_US_SetTimeguard(pUSART, timeguard);
-
-    //* Clear Transmit and Receive Counters
-    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
-
-    //* Define the USART mode
-    pUSART->US_MR = mode  ;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableRx
-//* \brief Enable receiving characters
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Enable receiver
-    pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableTx
-//* \brief Enable sending characters
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Enable  transmitter
-    pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ResetRx
-//* \brief Reset Receiver and re-enable it
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_ResetRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-	//* Reset receiver
-	pUSART->US_CR = AT91C_US_RSTRX;
-    //* Re-Enable receiver
-    pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ResetTx
-//* \brief Reset Transmitter and re-enable it
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_ResetTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-	//* Reset transmitter
-	pUSART->US_CR = AT91C_US_RSTTX;
-    //* Enable transmitter
-    pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableRx
-//* \brief Disable Receiver
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Disable receiver
-    pUSART->US_CR = AT91C_US_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableTx
-//* \brief Disable Transmitter
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Disable transmitter
-    pUSART->US_CR = AT91C_US_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Close
-//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_Close (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Reset the baud rate divisor register
-    pUSART->US_BRGR = 0 ;
-
-    //* Reset the USART mode
-    pUSART->US_MR = 0  ;
-
-    //* Reset the Timeguard Register
-    pUSART->US_TTGR = 0;
-
-    //* Disable all interrupts
-    pUSART->US_IDR = 0xFFFFFFFF ;
-
-    //* Abort the Peripheral Data Transfers
-    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
-
-    //* Disable receiver and transmitter and stop any activity immediately
-    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_TxReady
-//* \brief Return 1 if a character can be written in US_THR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_TxReady (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR & AT91C_US_TXRDY);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_RxReady
-//* \brief Return 1 if a character can be read in US_RHR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_RxReady (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR & AT91C_US_RXRDY);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Error
-//* \brief Return the error flag
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_Error (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR &
-    	(AT91C_US_OVRE |  // Overrun error
-    	 AT91C_US_FRAME | // Framing error
-    	 AT91C_US_PARE));  // Parity error
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_PutChar (
-	AT91PS_USART pUSART,
-	int character )
-{
-    pUSART->US_THR = (character & 0x1FF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-__inline int AT91F_US_GetChar (
-	const AT91PS_USART pUSART)
-{
-    return((pUSART->US_RHR) & 0x1FF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_SendFrame(
-	AT91PS_USART pUSART,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pUSART->US_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_ReceiveFrame (
-	AT91PS_USART pUSART,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pUSART->US_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetIrdaFilter
-//* \brief Set the value of IrDa filter tregister
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetIrdaFilter (
-	AT91PS_USART pUSART,
-	unsigned char value
-)
-{
-	pUSART->US_IF = value;
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR SSC
-   ***************************************************************************** */
-//* Define the standard I2S mode configuration
-
-//* Configuration to set in the SSC Transmit Clock Mode Register
-//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
-//* 			  nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
-									   AT91C_SSC_CKS_DIV   +\
-                            		   AT91C_SSC_CKO_CONTINOUS      +\
-                            		   AT91C_SSC_CKG_NONE    +\
-                                       AT91C_SSC_START_FALL_RF +\
-                           			   AT91C_SSC_STTOUT  +\
-                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
-                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
-
-
-//* Configuration to set in the SSC Transmit Frame Mode Register
-//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
-//* 			 nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
-									(nb_bit_by_slot-1)  +\
-                            		AT91C_SSC_MSBF   +\
-                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
-                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
-                            		AT91C_SSC_FSOS_NEGATIVE)
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_SetBaudrate (
-        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
-        unsigned int mainClock, // \arg peripheral clock
-        unsigned int speed)     // \arg SSC baudrate
-{
-        unsigned int baud_value;
-        //* Define the baud rate divisor register
-        if (speed == 0)
-           baud_value = 0;
-        else
-        {
-           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
-           if ((baud_value % 10) >= 5)
-                  baud_value = (baud_value / 10) + 1;
-           else
-                  baud_value /= 10;
-        }
-
-        pSSC->SSC_CMR = baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_Configure
-//* \brief Configure SSC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_Configure (
-             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
-             unsigned int syst_clock,  // \arg System Clock Frequency
-             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
-             unsigned int clock_rx,    // \arg Receiver Clock Parameters
-             unsigned int mode_rx,     // \arg mode Register to be programmed
-             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
-             unsigned int mode_tx)     // \arg mode Register to be programmed
-{
-    //* Disable interrupts
-	pSSC->SSC_IDR = (unsigned int) -1;
-
-    //* Reset receiver and transmitter
-	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
-
-    //* Define the Clock Mode Register
-	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
-
-     //* Write the Receive Clock Mode Register
-	pSSC->SSC_RCMR =  clock_rx;
-
-     //* Write the Transmit Clock Mode Register
-	pSSC->SSC_TCMR =  clock_tx;
-
-     //* Write the Receive Frame Mode Register
-	pSSC->SSC_RFMR =  mode_rx;
-
-     //* Write the Transmit Frame Mode Register
-	pSSC->SSC_TFMR =  mode_tx;
-
-    //* Clear Transmit and Receive Counters
-	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
-
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableRx
-//* \brief Enable receiving datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableRx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Enable receiver
-    pSSC->SSC_CR = AT91C_SSC_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableRx
-//* \brief Disable receiving datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableRx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Disable receiver
-    pSSC->SSC_CR = AT91C_SSC_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableTx
-//* \brief Enable sending datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableTx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Enable  transmitter
-    pSSC->SSC_CR = AT91C_SSC_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableTx
-//* \brief Disable sending datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableTx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Disable  transmitter
-    pSSC->SSC_CR = AT91C_SSC_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableIt
-//* \brief Enable SSC IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableIt (
-	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pSSC->SSC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableIt
-//* \brief Disable SSC IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableIt (
-	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pSSC->SSC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_ReceiveFrame (
-	AT91PS_SSC pSSC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pSSC->SSC_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_SendFrame(
-	AT91PS_SSC pSSC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pSSC->SSC_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_GetInterruptMaskStatus
-//* \brief Return SSC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
-        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
-{
-        return pSsc->SSC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_IsInterruptMasked
-//* \brief Test if SSC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_SSC_IsInterruptMasked(
-        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR TWI
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_EnableIt
-//* \brief Enable TWI IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_EnableIt (
-	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pTWI->TWI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_DisableIt
-//* \brief Disable TWI IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_DisableIt (
-	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pTWI->TWI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_Configure
-//* \brief Configure TWI in master mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
-{
-    //* Disable interrupts
-	pTWI->TWI_IDR = (unsigned int) -1;
-
-    //* Reset peripheral
-	pTWI->TWI_CR = AT91C_TWI_SWRST;
-
-	//* Set Master mode
-	pTWI->TWI_CR = AT91C_TWI_MSEN;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_GetInterruptMaskStatus
-//* \brief Return TWI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
-        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
-{
-        return pTwi->TWI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_IsInterruptMasked
-//* \brief Test if TWI Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_TWI_IsInterruptMasked(
-        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PWMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_GetStatus
-//* \brief Return PWM Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
-	AT91PS_PWMC pPWM) // pointer to a PWM controller
-{
-	return pPWM->PWMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_InterruptEnable
-//* \brief Enable PWM Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_InterruptEnable(
-        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  PWM interrupt to be enabled
-{
-        pPwm->PWMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_InterruptDisable
-//* \brief Disable PWM Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_InterruptDisable(
-        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  PWM interrupt to be disabled
-{
-        pPwm->PWMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_GetInterruptMaskStatus
-//* \brief Return PWM Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
-        AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
-{
-        return pPwm->PWMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_IsInterruptMasked
-//* \brief Test if PWM Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_IsInterruptMasked(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_IsStatusSet
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_IsStatusSet(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PWMC_GetStatus(pPWM) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_CfgChannel
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CfgChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int channelId, // \arg PWM channel ID
-        unsigned int mode, // \arg  PWM mode
-        unsigned int period, // \arg PWM period
-        unsigned int duty) // \arg PWM duty cycle
-{
-	pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
-	pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
-	pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_StartChannel
-//* \brief Enable channel
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_StartChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  Channels IDs to be enabled
-{
-	pPWM->PWMC_ENA = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_StopChannel
-//* \brief Disable channel
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_StopChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  Channels IDs to be enabled
-{
-	pPWM->PWMC_DIS = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_UpdateChannel
-//* \brief Update Period or Duty Cycle
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_UpdateChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int channelId, // \arg PWM channel ID
-        unsigned int update) // \arg  Channels IDs to be enabled
-{
-	pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR UDP
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EnableIt
-//* \brief Enable UDP IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EnableIt (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pUDP->UDP_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_DisableIt
-//* \brief Disable UDP IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_DisableIt (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pUDP->UDP_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_SetAddress
-//* \brief Set UDP functional address
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_SetAddress (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char address)   // \arg new UDP address
-{
-	pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EnableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EnableEp (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char endpoint)   // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_DisableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_DisableEp (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char endpoint)   // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_SetState
-//* \brief Set UDP Device state
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_SetState (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg new UDP address
-{
-	pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
-	pUDP->UDP_GLBSTATE  |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_GetState
-//* \brief return UDP Device state
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
-	AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
-{
-	return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_ResetEp
-//* \brief Reset UDP endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg Endpoints to be reset
-{
-	pUDP->UDP_RSTEP = flag;
-	pUDP->UDP_RSTEP = 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpStall
-//* \brief Endpoint will STALL requests
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpStall(
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char endpoint)   // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpWrite
-//* \brief Write value in the DPR
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpWrite(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned char value)     // \arg value to be written in the DPR
-{
-	pUDP->UDP_FDR[endpoint] = value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpRead
-//* \brief Return value from the DPR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_EpRead(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	return pUDP->UDP_FDR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpEndOfWr
-//* \brief Notify the UDP that values in DPR are ready to be sent
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpEndOfWr(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpClear
-//* \brief Clear flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpClear(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned int flag)       // \arg flag to be cleared
-{
-	pUDP->UDP_CSR[endpoint] &= ~(flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpSet
-//* \brief Set flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpSet(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned int flag)       // \arg flag to be cleared
-{
-	pUDP->UDP_CSR[endpoint] |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpStatus
-//* \brief Return the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_EpStatus(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	return pUDP->UDP_CSR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_GetInterruptMaskStatus
-//* \brief Return UDP Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
-        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
-{
-        return pUdp->UDP_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_IsInterruptMasked
-//* \brief Test if UDP Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_UDP_IsInterruptMasked(
-        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR TC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_InterruptEnable
-//* \brief Enable TC Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC_InterruptEnable(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  TC interrupt to be enabled
-{
-        pTc->TC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_InterruptDisable
-//* \brief Disable TC Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC_InterruptDisable(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  TC interrupt to be disabled
-{
-        pTc->TC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_GetInterruptMaskStatus
-//* \brief Return TC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
-        AT91PS_TC pTc) // \arg  pointer to a TC controller
-{
-        return pTc->TC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_IsInterruptMasked
-//* \brief Test if TC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_TC_IsInterruptMasked(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR CAN
-   ***************************************************************************** */
-#define	STANDARD_FORMAT 0
-#define	EXTENDED_FORMAT 1
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_InitMailboxRegisters()
-//* \brief Configure the corresponding mailbox
-//*----------------------------------------------------------------------------
-__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB	CAN_Mailbox,
-								int  			mode_reg,
-								int 			acceptance_mask_reg,
-								int  			id_reg,
-								int  			data_low_reg,
-								int  			data_high_reg,
-								int  			control_reg)
-{
-	CAN_Mailbox->CAN_MB_MCR 	= 0x0;
-	CAN_Mailbox->CAN_MB_MMR 	= mode_reg;
-	CAN_Mailbox->CAN_MB_MAM 	= acceptance_mask_reg;
-	CAN_Mailbox->CAN_MB_MID 	= id_reg;
-	CAN_Mailbox->CAN_MB_MDL 	= data_low_reg; 		
-	CAN_Mailbox->CAN_MB_MDH 	= data_high_reg;
-	CAN_Mailbox->CAN_MB_MCR 	= control_reg;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_EnableCAN()
-//* \brief 
-//*----------------------------------------------------------------------------
-__inline void AT91F_EnableCAN(
-	AT91PS_CAN pCAN)     // pointer to a CAN controller
-{
-	pCAN->CAN_MR |= AT91C_CAN_CANEN;
-
-	// Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
-	while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DisableCAN()
-//* \brief 
-//*----------------------------------------------------------------------------
-__inline void AT91F_DisableCAN(
-	AT91PS_CAN pCAN)     // pointer to a CAN controller
-{
-	pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_EnableIt
-//* \brief Enable CAN interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_EnableIt (
-	AT91PS_CAN pCAN,     // pointer to a CAN controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pCAN->CAN_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_DisableIt
-//* \brief Disable CAN interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_DisableIt (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pCAN->CAN_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetStatus
-//* \brief Return CAN Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
-	AT91PS_CAN pCAN) // pointer to a CAN controller
-{
-	return pCAN->CAN_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetInterruptMaskStatus
-//* \brief Return CAN Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
-	AT91PS_CAN pCAN) // pointer to a CAN controller
-{
-	return pCAN->CAN_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_IsInterruptMasked
-//* \brief Test if CAN Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_IsInterruptMasked(
-        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_IsStatusSet
-//* \brief Test if CAN Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_IsStatusSet(
-        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_CAN_GetStatus(pCAN) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgModeReg
-//* \brief Configure the Mode Register of the CAN controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgModeReg (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-	unsigned int mode)        // mode register 
-{
-	//* Write to the MR register
-	pCAN->CAN_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetModeReg
-//* \brief Return the Mode Register of the CAN controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetModeReg (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_MR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgBaudrateReg
-//* \brief Configure the Baudrate of the CAN controller for the network
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgBaudrateReg (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-	unsigned int baudrate_cfg)
-{
-	//* Write to the BR register
-	pCAN->CAN_BR = baudrate_cfg;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetBaudrate
-//* \brief Return the Baudrate of the CAN controller for the network value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetBaudrate (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_BR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetInternalCounter
-//* \brief Return CAN Timer Regsiter Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetInternalCounter (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_TIM;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetTimestamp
-//* \brief Return CAN Timestamp Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetTimestamp (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_TIMESTP;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetErrorCounter
-//* \brief Return CAN Error Counter Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetErrorCounter (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_ECR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_InitTransferRequest
-//* \brief Request for a transfer on the corresponding mailboxes
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_InitTransferRequest (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-    unsigned int transfer_cmd)
-{
-	pCAN->CAN_TCR = transfer_cmd;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_InitAbortRequest
-//* \brief Abort the corresponding mailboxes
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_InitAbortRequest (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-    unsigned int abort_cmd)
-{
-	pCAN->CAN_ACR = abort_cmd;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageModeReg
-//* \brief Program the Message Mode Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageModeReg (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int mode)
-{
-	CAN_Mailbox->CAN_MB_MMR = mode;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageModeReg
-//* \brief Return the Message Mode Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageModeReg (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MMR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageIDReg
-//* \brief Program the Message ID Register
-//* \brief Version == 0 for Standard messsage, Version == 1 for Extended  
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageIDReg (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int id,
-    unsigned char version)
-{
-	if(version==0)	// IDvA Standard Format
-		CAN_Mailbox->CAN_MB_MID = id<<18;
-	else	// IDvB Extended Format
-		CAN_Mailbox->CAN_MB_MID = id | (1<<29);	// set MIDE bit
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageIDReg
-//* \brief Return the Message ID Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageIDReg (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MID;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageAcceptanceMaskReg
-//* \brief Program the Message Acceptance Mask Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int mask)
-{
-	CAN_Mailbox->CAN_MB_MAM = mask;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageAcceptanceMaskReg
-//* \brief Return the Message Acceptance Mask Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MAM;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetFamilyID
-//* \brief Return the Message ID Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetFamilyID (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MFID;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageCtrl
-//* \brief Request and config for a transfer on the corresponding mailbox
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageCtrlReg (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int message_ctrl_cmd)
-{
-	CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageStatus
-//* \brief Return CAN Mailbox Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageStatus (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MSR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageDataLow
-//* \brief Program data low value
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageDataLow (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int data)
-{
-	CAN_Mailbox->CAN_MB_MDL = data;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageDataLow
-//* \brief Return data low value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageDataLow (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MDL;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageDataHigh
-//* \brief Program data high value
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageDataHigh (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int data)
-{
-	CAN_Mailbox->CAN_MB_MDH = data;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageDataHigh
-//* \brief Return data high value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageDataHigh (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MDH;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_Open
-//* \brief Open a CAN Port
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_Open (
-        const unsigned int null)  // \arg
-{
-        /* NOT DEFINED AT THIS MOMENT */
-        return ( 0 );
-}
-/* *****************************************************************************
-                SOFTWARE API FOR ADC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_EnableIt
-//* \brief Enable ADC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_EnableIt (
-	AT91PS_ADC pADC,     // pointer to a ADC controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pADC->ADC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_DisableIt
-//* \brief Disable ADC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_DisableIt (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pADC->ADC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetStatus
-//* \brief Return ADC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
-	AT91PS_ADC pADC) // pointer to a ADC controller
-{
-	return pADC->ADC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetInterruptMaskStatus
-//* \brief Return ADC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
-	AT91PS_ADC pADC) // pointer to a ADC controller
-{
-	return pADC->ADC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_IsInterruptMasked
-//* \brief Test if ADC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_IsInterruptMasked(
-        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_IsStatusSet
-//* \brief Test if ADC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_IsStatusSet(
-        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_ADC_GetStatus(pADC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgModeReg
-//* \brief Configure the Mode Register of the ADC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgModeReg (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int mode)        // mode register 
-{
-	//* Write to the MR register
-	pADC->ADC_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetModeReg
-//* \brief Return the Mode Register of the ADC controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetModeReg (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_MR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgTimings
-//* \brief Configure the different necessary timings of the ADC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgTimings (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int mck_clock, // in MHz 
-	unsigned int adc_clock, // in MHz 
-	unsigned int startup_time, // in us 
-	unsigned int sample_and_hold_time)	// in ns  
-{
-	unsigned int prescal,startup,shtim;
-	
-	prescal = mck_clock/(2*adc_clock) - 1;
-	startup = adc_clock*startup_time/8 - 1;
-	shtim = adc_clock*sample_and_hold_time/1000 - 1;
-	
-	//* Write to the MR register
-	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_EnableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_EnableChannel (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int channel)        // mode register 
-{
-	//* Write to the CHER register
-	pADC->ADC_CHER = channel;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_DisableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_DisableChannel (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int channel)        // mode register 
-{
-	//* Write to the CHDR register
-	pADC->ADC_CHDR = channel;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetChannelStatus
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetChannelStatus (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CHSR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_StartConversion
-//* \brief Software request for a analog to digital conversion 
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_StartConversion (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	pADC->ADC_CR = AT91C_ADC_START;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_SoftReset
-//* \brief Software reset
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_SoftReset (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	pADC->ADC_CR = AT91C_ADC_SWRST;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetLastConvertedData
-//* \brief Return the Last Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetLastConvertedData (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_LCDR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH0
-//* \brief Return the Channel 0 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR0;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH1
-//* \brief Return the Channel 1 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR1;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH2
-//* \brief Return the Channel 2 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR2;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH3
-//* \brief Return the Channel 3 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR3;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH4
-//* \brief Return the Channel 4 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR4;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH5
-//* \brief Return the Channel 5 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR5;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH6
-//* \brief Return the Channel 6 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR6;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH7
-//* \brief Return the Channel 7 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR7;	
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR AES
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_EnableIt
-//* \brief Enable AES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_EnableIt (
-	AT91PS_AES pAES,     // pointer to a AES controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pAES->AES_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_DisableIt
-//* \brief Disable AES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_DisableIt (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pAES->AES_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_GetStatus
-//* \brief Return AES Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
-	AT91PS_AES pAES) // pointer to a AES controller
-{
-	return pAES->AES_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_GetInterruptMaskStatus
-//* \brief Return AES Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
-	AT91PS_AES pAES) // pointer to a AES controller
-{
-	return pAES->AES_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_IsInterruptMasked
-//* \brief Test if AES Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_IsInterruptMasked(
-        AT91PS_AES pAES,   // \arg  pointer to a AES controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_IsStatusSet
-//* \brief Test if AES Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_IsStatusSet(
-        AT91PS_AES pAES,   // \arg  pointer to a AES controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_AES_GetStatus(pAES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_CfgModeReg
-//* \brief Configure the Mode Register of the AES controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_CfgModeReg (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned int mode)        // mode register 
-{
-	//* Write to the MR register
-	pAES->AES_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_GetModeReg
-//* \brief Return the Mode Register of the AES controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetModeReg (
-	AT91PS_AES pAES // pointer to a AES controller
-	)
-{
-	return pAES->AES_MR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_StartProcessing
-//* \brief Start Encryption or Decryption
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_StartProcessing (
-	AT91PS_AES pAES // pointer to a AES controller
-	)
-{
-	pAES->AES_CR = AT91C_AES_START;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_SoftReset
-//* \brief Reset AES
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_SoftReset (
-	AT91PS_AES pAES // pointer to a AES controller
-	)
-{
-	pAES->AES_CR = AT91C_AES_SWRST;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_LoadNewSeed
-//* \brief Load New Seed in the random number generator
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_LoadNewSeed (
-	AT91PS_AES pAES // pointer to a AES controller
-	)
-{
-	pAES->AES_CR = AT91C_AES_LOADSEED;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_SetCryptoKey
-//* \brief Set Cryptographic Key x
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_SetCryptoKey (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned char index,
-	unsigned int keyword
-	)
-{
-	pAES->AES_KEYWxR[index] = keyword;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_InputData
-//* \brief Set Input Data x
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_InputData (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned char index,
-	unsigned int indata
-	)
-{
-	pAES->AES_IDATAxR[index] = indata;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_GetOutputData
-//* \brief Get Output Data x
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetOutputData (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned char index
-	)
-{
-	return pAES->AES_ODATAxR[index];	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_SetInitializationVector
-//* \brief Set Initialization Vector (or Counter) x
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_SetInitializationVector (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned char index,
-	unsigned int initvector
-	)
-{
-	pAES->AES_IVxR[index] = initvector;	
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR TDES
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_EnableIt
-//* \brief Enable TDES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_EnableIt (
-	AT91PS_TDES pTDES,     // pointer to a TDES controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pTDES->TDES_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_DisableIt
-//* \brief Disable TDES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_DisableIt (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pTDES->TDES_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_GetStatus
-//* \brief Return TDES Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
-	AT91PS_TDES pTDES) // pointer to a TDES controller
-{
-	return pTDES->TDES_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_GetInterruptMaskStatus
-//* \brief Return TDES Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
-	AT91PS_TDES pTDES) // pointer to a TDES controller
-{
-	return pTDES->TDES_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_IsInterruptMasked
-//* \brief Test if TDES Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_IsInterruptMasked(
-        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_IsStatusSet
-//* \brief Test if TDES Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_IsStatusSet(
-        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_TDES_GetStatus(pTDES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_CfgModeReg
-//* \brief Configure the Mode Register of the TDES controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_CfgModeReg (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned int mode)        // mode register 
-{
-	//* Write to the MR register
-	pTDES->TDES_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_GetModeReg
-//* \brief Return the Mode Register of the TDES controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetModeReg (
-	AT91PS_TDES pTDES // pointer to a TDES controller
-	)
-{
-	return pTDES->TDES_MR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_StartProcessing
-//* \brief Start Encryption or Decryption
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_StartProcessing (
-	AT91PS_TDES pTDES // pointer to a TDES controller
-	)
-{
-	pTDES->TDES_CR = AT91C_TDES_START;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SoftReset
-//* \brief Reset TDES
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SoftReset (
-	AT91PS_TDES pTDES // pointer to a TDES controller
-	)
-{
-	pTDES->TDES_CR = AT91C_TDES_SWRST;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SetCryptoKey1
-//* \brief Set Cryptographic Key 1 Word x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetCryptoKey1 (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int keyword
-	)
-{
-	pTDES->TDES_KEY1WxR[index] = keyword;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SetCryptoKey2
-//* \brief Set Cryptographic Key 2 Word x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetCryptoKey2 (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int keyword
-	)
-{
-	pTDES->TDES_KEY2WxR[index] = keyword;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SetCryptoKey3
-//* \brief Set Cryptographic Key 3 Word x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetCryptoKey3 (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int keyword
-	)
-{
-	pTDES->TDES_KEY3WxR[index] = keyword;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_InputData
-//* \brief Set Input Data x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_InputData (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int indata
-	)
-{
-	pTDES->TDES_IDATAxR[index] = indata;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_GetOutputData
-//* \brief Get Output Data x
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetOutputData (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index
-	)
-{
-	return pTDES->TDES_ODATAxR[index];	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SetInitializationVector
-//* \brief Set Initialization Vector x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetInitializationVector (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int initvector
-	)
-{
-	pTDES->TDES_IVxR[index] = initvector;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  DBGU
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_CfgPIO
-//* \brief Configure PIO controllers to drive DBGU signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA27_DRXD    ) |
-		((unsigned int) AT91C_PA28_DTXD    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PMC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgPIO
-//* \brief Configure PIO controllers to drive PMC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB30_PCK2    ) |
-		((unsigned int) AT91C_PB29_PCK1    ), // Peripheral A
-		((unsigned int) AT91C_PB20_PCK0    ) |
-		((unsigned int) AT91C_PB0_PCK0    ) |
-		((unsigned int) AT91C_PB22_PCK2    ) |
-		((unsigned int) AT91C_PB21_PCK1    )); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA30_PCK2    ) |
-		((unsigned int) AT91C_PA13_PCK1    ) |
-		((unsigned int) AT91C_PA27_PCK3    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_VREG_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  VREG
-//*----------------------------------------------------------------------------
-__inline void AT91F_VREG_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  RSTC
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SSC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SSC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_CfgPIO
-//* \brief Configure PIO controllers to drive SSC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA25_RK      ) |
-		((unsigned int) AT91C_PA22_TK      ) |
-		((unsigned int) AT91C_PA21_TF      ) |
-		((unsigned int) AT91C_PA24_RD      ) |
-		((unsigned int) AT91C_PA26_RF      ) |
-		((unsigned int) AT91C_PA23_TD      ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  WDTC
-//*----------------------------------------------------------------------------
-__inline void AT91F_WDTC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US1
-//*----------------------------------------------------------------------------
-__inline void AT91F_US1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_US1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US1_CfgPIO
-//* \brief Configure PIO controllers to drive US1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_US1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PB26_RI1     ) |
-		((unsigned int) AT91C_PB24_DSR1    ) |
-		((unsigned int) AT91C_PB23_DCD1    ) |
-		((unsigned int) AT91C_PB25_DTR1    )); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA7_SCK1    ) |
-		((unsigned int) AT91C_PA8_RTS1    ) |
-		((unsigned int) AT91C_PA6_TXD1    ) |
-		((unsigned int) AT91C_PA5_RXD1    ) |
-		((unsigned int) AT91C_PA9_CTS1    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US0
-//*----------------------------------------------------------------------------
-__inline void AT91F_US0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_US0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US0_CfgPIO
-//* \brief Configure PIO controllers to drive US0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_US0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA0_RXD0    ) |
-		((unsigned int) AT91C_PA4_CTS0    ) |
-		((unsigned int) AT91C_PA3_RTS0    ) |
-		((unsigned int) AT91C_PA2_SCK0    ) |
-		((unsigned int) AT91C_PA1_TXD0    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SPI1
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SPI1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI1_CfgPIO
-//* \brief Configure PIO controllers to drive SPI1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PB16_NPCS13  ) |
-		((unsigned int) AT91C_PB10_NPCS11  ) |
-		((unsigned int) AT91C_PB11_NPCS12  )); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA4_NPCS13  ) |
-		((unsigned int) AT91C_PA29_NPCS13  ) |
-		((unsigned int) AT91C_PA21_NPCS10  ) |
-		((unsigned int) AT91C_PA22_SPCK1   ) |
-		((unsigned int) AT91C_PA25_NPCS11  ) |
-		((unsigned int) AT91C_PA2_NPCS11  ) |
-		((unsigned int) AT91C_PA24_MISO1   ) |
-		((unsigned int) AT91C_PA3_NPCS12  ) |
-		((unsigned int) AT91C_PA26_NPCS12  ) |
-		((unsigned int) AT91C_PA23_MOSI1   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SPI0
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SPI0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI0_CfgPIO
-//* \brief Configure PIO controllers to drive SPI0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PB13_NPCS01  ) |
-		((unsigned int) AT91C_PB17_NPCS03  ) |
-		((unsigned int) AT91C_PB14_NPCS02  )); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA16_MISO0   ) |
-		((unsigned int) AT91C_PA13_NPCS01  ) |
-		((unsigned int) AT91C_PA15_NPCS03  ) |
-		((unsigned int) AT91C_PA17_MOSI0   ) |
-		((unsigned int) AT91C_PA18_SPCK0   ) |
-		((unsigned int) AT91C_PA14_NPCS02  ) |
-		((unsigned int) AT91C_PA12_NPCS00  ), // Peripheral A
-		((unsigned int) AT91C_PA7_NPCS01  ) |
-		((unsigned int) AT91C_PA9_NPCS03  ) |
-		((unsigned int) AT91C_PA8_NPCS02  )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PITC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  AIC
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_FIQ) |
-		((unsigned int) 1 << AT91C_ID_IRQ0) |
-		((unsigned int) 1 << AT91C_ID_IRQ1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_CfgPIO
-//* \brief Configure PIO controllers to drive AIC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA30_IRQ0    ) |
-		((unsigned int) AT91C_PA29_FIQ     ), // Peripheral A
-		((unsigned int) AT91C_PA14_IRQ1    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  AES
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_AES));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TWI
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TWI));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_CfgPIO
-//* \brief Configure PIO controllers to drive TWI signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA11_TWCK    ) |
-		((unsigned int) AT91C_PA10_TWD     ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  ADC
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_ADC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgPIO
-//* \brief Configure PIO controllers to drive ADC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PB18_ADTRG   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH3_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH3 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH3_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB22_PWM3    ), // Peripheral A
-		((unsigned int) AT91C_PB30_PWM3    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH2_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH2 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH2_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB21_PWM2    ), // Peripheral A
-		((unsigned int) AT91C_PB29_PWM2    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH1_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB20_PWM1    ), // Peripheral A
-		((unsigned int) AT91C_PB28_PWM1    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH0_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB19_PWM0    ), // Peripheral A
-		((unsigned int) AT91C_PB27_PWM0    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RTTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  RTTC
-//*----------------------------------------------------------------------------
-__inline void AT91F_RTTC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  UDP
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_UDP));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TDES
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TDES));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_EMAC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  EMAC
-//*----------------------------------------------------------------------------
-__inline void AT91F_EMAC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_EMAC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_EMAC_CfgPIO
-//* \brief Configure PIO controllers to drive EMAC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_EMAC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB2_ETX0    ) |
-		((unsigned int) AT91C_PB12_ETXER   ) |
-		((unsigned int) AT91C_PB16_ECOL    ) |
-		((unsigned int) AT91C_PB11_ETX3    ) |
-		((unsigned int) AT91C_PB6_ERX1    ) |
-		((unsigned int) AT91C_PB15_ERXDV   ) |
-		((unsigned int) AT91C_PB13_ERX2    ) |
-		((unsigned int) AT91C_PB3_ETX1    ) |
-		((unsigned int) AT91C_PB8_EMDC    ) |
-		((unsigned int) AT91C_PB5_ERX0    ) |
-		//((unsigned int) AT91C_PB18_EF100   ) |
-		((unsigned int) AT91C_PB14_ERX3    ) |
-		((unsigned int) AT91C_PB4_ECRS_ECRSDV) |
-		((unsigned int) AT91C_PB1_ETXEN   ) |
-		((unsigned int) AT91C_PB10_ETX2    ) |
-		((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
-		((unsigned int) AT91C_PB9_EMDIO   ) |
-		((unsigned int) AT91C_PB7_ERXER   ) |
-		((unsigned int) AT91C_PB17_ERXCK   ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC0
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC0_CfgPIO
-//* \brief Configure PIO controllers to drive TC0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB23_TIOA0   ) |
-		((unsigned int) AT91C_PB24_TIOB0   ), // Peripheral A
-		((unsigned int) AT91C_PB12_TCLK0   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC1
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC1_CfgPIO
-//* \brief Configure PIO controllers to drive TC1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB25_TIOA1   ) |
-		((unsigned int) AT91C_PB26_TIOB1   ), // Peripheral A
-		((unsigned int) AT91C_PB19_TCLK1   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC2_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC2
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC2_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC2));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC2_CfgPIO
-//* \brief Configure PIO controllers to drive TC2 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC2_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB28_TIOB2   ) |
-		((unsigned int) AT91C_PB27_TIOA2   ), // Peripheral A
-		0); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA15_TCLK2   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  MC
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIOA_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PIOA
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIOA_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PIOA));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIOB_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PIOB
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIOB_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PIOB));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  CAN
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_CAN));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgPIO
-//* \brief Configure PIO controllers to drive CAN signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA20_CANTX   ) |
-		((unsigned int) AT91C_PA19_CANRX   ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PWMC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PWMC));
-}
-
-#endif // lib_AT91SAM7X256_H
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/port.c b/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/port.c
deleted file mode 100755
index df7ac2b..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/port.c
+++ /dev/null
@@ -1,213 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM7 port.
- *
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in this file.  The ISR routines, which can only be compiled
- * to ARM mode are contained in portISR.c.
- *----------------------------------------------------------*/
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Processor constants. */
-#include "AT91SAM7X256.h"
-
-/* Constants required to setup the task context. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
-
-/* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER			( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE			0x00
-#define portINTERRUPT_ON_MATCH		( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH	( ( uint32_t ) 0x02 )
-
-/* Constants required to setup the PIT. */
-#define portPIT_CLOCK_DIVISOR			( ( uint32_t ) 16 )
-#define portPIT_COUNTER_VALUE			( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
-
-#define portINT_LEVEL_SENSITIVE  0
-#define portPIT_ENABLE      	( ( uint16_t ) 0x1 << 24 )
-#define portPIT_INT_ENABLE     	( ( uint16_t ) 0x1 << 25 )
-/*-----------------------------------------------------------*/
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/* 
- * The scheduler can only be started from ARM mode, so 
- * vPortISRStartFirstSTask() is defined in portISR.c. 
- */
-extern void vPortISRStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/* 
- * Initialise the stack of a task to look exactly as if a call to 
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description. 
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
-	pxOriginalTOS = pxTopOfStack;
-
-	/* To ensure asserts in tasks.c don't fail, although in this case the assert
-	is not really required. */
-	pxTopOfStack--;
-
-	/* Setup the initial stack of the task.  The stack is set exactly as 
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* First on the stack is the return address - which in this case is the
-	start of the task.  The offset is added to make the return address appear
-	as it would within an IRQ ISR. */
-	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* R14 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;	
-
-	/* When the task starts is will expect to find the function parameter in
-	R0. */
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The last thing onto the stack is the status register, which is set for
-	system mode, with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	#ifdef THUMB_INTERWORK
-	{
-		/* We want the task to start in thumb mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-	#endif
-
-	pxTopOfStack--;
-
-	/* Some optimisation levels use the stack differently to others.  This 
-	means the interrupt flags cannot always be stored on the stack and will
-	instead be stored in a variable, which is then saved as part of the
-	tasks context. */
-	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task. */
-	vPortISRStartFirstTask();	
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the ARM port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the timer 0 to generate the tick interrupts at the required frequency.
- */
-static void prvSetupTimerInterrupt( void )
-{
-AT91PS_PITC pxPIT = AT91C_BASE_PITC;
-
-	/* Setup the AIC for PIT interrupts.  The interrupt routine chosen depends
-	on whether the preemptive or cooperative scheduler is being used. */
-	#if configUSE_PREEMPTION == 0
-
-		extern void ( vNonPreemptiveTick ) ( void );
-		AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vNonPreemptiveTick );
-
-	#else
-		
-		extern void ( vPreemptiveTick )( void );
-		AT91F_AIC_ConfigureIt( AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPreemptiveTick );
-
-	#endif
-
-	/* Configure the PIT period. */
-	pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
-
-	/* Enable the interrupt.  Global interrupts are disables at this point so 
-	this is safe. */
-    AT91C_BASE_AIC->AIC_IECR = 0x1 << AT91C_ID_SYS;
-}
-/*-----------------------------------------------------------*/
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c b/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c
deleted file mode 100755
index e2f0f67..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portISR.c
+++ /dev/null
@@ -1,227 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c  The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
-
-/*
-	Changes from V3.2.4
-
-	+ The assembler statements are now included in a single asm block rather
-	  than each line having its own asm block.
-*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#include "AT91SAM7X256.h"
-
-/* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/*-----------------------------------------------------------*/
-
-/* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
-
-/*
- * The scheduler can only be started from ARM mode, hence the inclusion of this
- * function here.
- */
-void vPortISRStartFirstTask( void );
-/*-----------------------------------------------------------*/
-
-void vPortISRStartFirstTask( void )
-{
-	/* Simply start the scheduler.  This is included here as it can only be
-	called from ARM mode. */
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Called by portYIELD() or taskYIELD() to manually force a context switch.
- *
- * When a context switch is performed from the task level the saved task
- * context is made to look as if it occurred from within the tick ISR.  This
- * way the same restore context function can be used when restoring the context
- * saved from the ISR or that saved from a call to vPortYieldProcessor.
- */
-void vPortYieldProcessor( void )
-{
-	/* Within an IRQ ISR the link register has an offset from the true return
-	address, but an SWI ISR does not.  Add the offset manually so the same
-	ISR return code can be used in both cases. */
-	__asm volatile ( "ADD		LR, LR, #4" );
-
-	/* Perform the context switch.  First save the context of the current task. */
-	portSAVE_CONTEXT();
-
-	/* Find the highest priority task that is ready to run. */
-	vTaskSwitchContext();
-
-	/* Restore the context of the new task. */
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * The ISR used for the scheduler tick depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-
-#if configUSE_PREEMPTION == 0
-
-	/* The cooperative scheduler requires a normal IRQ service routine to
-	simply increment the system tick. */
-	void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
-	void vNonPreemptiveTick( void )
-	{
-		uint32_t ulDummy;
-
-		/* Increment the tick count - which may wake some tasks but as the
-		preemptive scheduler is not being used any woken task is not given
-		processor time no matter what its priority. */
-		xTaskIncrementTick();
-
-		/* Clear the PIT interrupt. */
-		ulDummy = AT91C_BASE_PITC->PITC_PIVR;
-
-		/* End the interrupt in the AIC. */
-		AT91C_BASE_AIC->AIC_EOICR = ulDummy;
-	}
-
-#else
-
-	/* The preemptive scheduler is defined as "naked" as the full context is
-	saved on entry as part of the context switch. */
-	void vPreemptiveTick( void ) __attribute__((naked));
-	void vPreemptiveTick( void )
-	{
-		/* Save the context of the current task. */
-		portSAVE_CONTEXT();
-
-		/* Increment the tick count - this may wake a task. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Find the highest priority task that is ready to run. */
-			vTaskSwitchContext();
-		}
-
-		/* End the interrupt in the AIC. */
-		AT91C_BASE_AIC->AIC_EOICR = AT91C_BASE_PITC->PITC_PIVR;
-
-		portRESTORE_CONTEXT();
-	}
-
-#endif
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt management utilities can only be called from ARM mode.  When
- * THUMB_INTERWORK is defined the utilities are defined as functions here to
- * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
- * the utilities are defined as macros in portmacro.h - as per other ports.
- */
-void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
-void vPortDisableInterruptsFromThumb( void )
-{
-	__asm volatile (
-		"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
-		"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
-		"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
-		"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
-		"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
-		"BX		R14" );					/* Return back to thumb.					*/
-}
-
-void vPortEnableInterruptsFromThumb( void )
-{
-	__asm volatile (
-		"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
-		"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
-		"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/
-		"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
-		"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
-		"BX		R14" );					/* Return back to thumb.					*/
-}
-
-
-/* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels.  The interrupt flags can therefore not always
-be saved to the stack.  Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
-void vPortEnterCritical( void )
-{
-	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
-	__asm volatile (
-		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
-		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
-		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
-		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
-		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as we are leaving a critical section. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then interrupts should be
-		re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Enable interrupts as per portEXIT_CRITICAL().					*/
-			__asm volatile (
-				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/
-				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/
-				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/
-				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/
-				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
-		}
-	}
-}
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h
deleted file mode 100755
index de8e5d4..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-	Changes from V3.2.3
-
-	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
-
-	Changes from V3.2.4
-
-	+ Removed the use of the %0 parameter within the assembler macros and
-	  replaced them with hard coded registers.  This will ensure the
-	  assembler does not select the link register as the temp register as
-	  was occasionally happening previously.
-
-	+ The assembler statements are now included in a single asm block rather
-	  than each line having its own asm block.
-
-	Changes from V4.5.0
-
-	+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
-	  and replaced them with portYIELD_FROM_ISR() macro.  Application code
-	  should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
-	  macros as per the V4.5.1 demo code.
-*/
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	portLONG
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-#define portNOP()					__asm volatile ( "NOP" );
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
-
-/*
- * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
- * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
- * are included here for efficiency.  An attempt to call one from
- * THUMB mode code will result in a compile time error.
- */
-
-#define portRESTORE_CONTEXT()											\
-{																		\
-extern volatile void * volatile pxCurrentTCB;							\
-extern volatile uint32_t ulCriticalNesting;					\
-																		\
-	/* Set the LR to the task stack. */									\
-	__asm volatile (													\
-	"LDR		R0, =pxCurrentTCB								\n\t"	\
-	"LDR		R0, [R0]										\n\t"	\
-	"LDR		LR, [R0]										\n\t"	\
-																		\
-	/* The critical nesting depth is the first item on the stack. */	\
-	/* Load it into the ulCriticalNesting variable. */					\
-	"LDR		R0, =ulCriticalNesting							\n\t"	\
-	"LDMFD	LR!, {R1}											\n\t"	\
-	"STR		R1, [R0]										\n\t"	\
-																		\
-	/* Get the SPSR from the stack. */									\
-	"LDMFD	LR!, {R0}											\n\t"	\
-	"MSR		SPSR, R0										\n\t"	\
-																		\
-	/* Restore all system mode registers for the task. */				\
-	"LDMFD	LR, {R0-R14}^										\n\t"	\
-	"NOP														\n\t"	\
-																		\
-	/* Restore the return address. */									\
-	"LDR		LR, [LR, #+60]									\n\t"	\
-																		\
-	/* And return - correcting the offset in the LR to obtain the */	\
-	/* correct address. */												\
-	"SUBS	PC, LR, #4											\n\t"	\
-	);																	\
-	( void ) ulCriticalNesting;											\
-	( void ) pxCurrentTCB;												\
-}
-/*-----------------------------------------------------------*/
-
-#define portSAVE_CONTEXT()												\
-{																		\
-extern volatile void * volatile pxCurrentTCB;							\
-extern volatile uint32_t ulCriticalNesting;					\
-																		\
-	/* Push R0 as we are going to use the register. */					\
-	__asm volatile (													\
-	"STMDB	SP!, {R0}											\n\t"	\
-																		\
-	/* Set R0 to point to the task stack pointer. */					\
-	"STMDB	SP,{SP}^											\n\t"	\
-	"NOP														\n\t"	\
-	"SUB	SP, SP, #4											\n\t"	\
-	"LDMIA	SP!,{R0}											\n\t"	\
-																		\
-	/* Push the return address onto the stack. */						\
-	"STMDB	R0!, {LR}											\n\t"	\
-																		\
-	/* Now we have saved LR we can use it instead of R0. */				\
-	"MOV	LR, R0												\n\t"	\
-																		\
-	/* Pop R0 so we can save it onto the system mode stack. */			\
-	"LDMIA	SP!, {R0}											\n\t"	\
-																		\
-	/* Push all the system mode registers onto the task stack. */		\
-	"STMDB	LR,{R0-LR}^											\n\t"	\
-	"NOP														\n\t"	\
-	"SUB	LR, LR, #60											\n\t"	\
-																		\
-	/* Push the SPSR onto the task stack. */							\
-	"MRS	R0, SPSR											\n\t"	\
-	"STMDB	LR!, {R0}											\n\t"	\
-																		\
-	"LDR	R0, =ulCriticalNesting								\n\t"	\
-	"LDR	R0, [R0]											\n\t"	\
-	"STMDB	LR!, {R0}											\n\t"	\
-																		\
-	/* Store the new top of stack for the task. */						\
-	"LDR	R0, =pxCurrentTCB									\n\t"	\
-	"LDR	R0, [R0]											\n\t"	\
-	"STR	LR, [R0]											\n\t"	\
-	);																	\
-	( void ) ulCriticalNesting;											\
-	( void ) pxCurrentTCB;												\
-}
-
-
-#define portYIELD_FROM_ISR()		vTaskSwitchContext()
-#define portYIELD()					__asm volatile ( "SWI 0" )
-/*-----------------------------------------------------------*/
-
-
-/* Critical section management. */
-
-/*
- * The interrupt management utilities can only be called from ARM mode.  When
- * THUMB_INTERWORK is defined the utilities are defined as functions in
- * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
- * defined then the utilities are defined as macros here - as per other ports.
- */
-
-#ifdef THUMB_INTERWORK
-
-	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
-	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
-	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
-
-#else
-
-	#define portDISABLE_INTERRUPTS()											\
-		__asm volatile (														\
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
-			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
-			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
-
-	#define portENABLE_INTERRUPTS()												\
-		__asm volatile (														\
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
-			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
-			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
-
-#endif /* THUMB_INTERWORK */
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL()		vPortEnterCritical();
-#define portEXIT_CRITICAL()			vPortExitCritical();
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/port.c b/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/port.c
deleted file mode 100755
index 713df07..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/port.c
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM7 port.
- *
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in this file.  The ISR routines, which can only be compiled
- * to ARM mode are contained in portISR.c.
- *----------------------------------------------------------*/
-
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to setup the task context. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
-
-/* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER			( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE			0x00
-#define portINTERRUPT_ON_MATCH		( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH	( ( uint32_t ) 0x02 )
-
-/* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL		( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT	( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE		( ( uint32_t ) 0x0020 )
-
-/*-----------------------------------------------------------*/
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/* 
- * The scheduler can only be started from ARM mode, so 
- * vPortISRStartFirstSTask() is defined in portISR.c. 
- */
-extern void vPortISRStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/* 
- * Initialise the stack of a task to look exactly as if a call to 
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description. 
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
-	pxOriginalTOS = pxTopOfStack;
-
-	/* To ensure asserts in tasks.c don't fail, although in this case the assert
-	is not really required. */
-	pxTopOfStack--;
-
-	/* Setup the initial stack of the task.  The stack is set exactly as 
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* First on the stack is the return address - which in this case is the
-	start of the task.  The offset is added to make the return address appear
-	as it would within an IRQ ISR. */
-	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;	
-
-	/* When the task starts is will expect to find the function parameter in
-	R0. */
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The last thing onto the stack is the status register, which is set for
-	system mode, with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
-	{
-		/* We want the task to start in thumb mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-
-	pxTopOfStack--;
-
-	/* Some optimisation levels use the stack differently to others.  This 
-	means the interrupt flags cannot always be stored on the stack and will
-	instead be stored in a variable, which is then saved as part of the
-	tasks context. */
-	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task. */
-	vPortISRStartFirstTask();	
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the ARM port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the timer 0 to generate the tick interrupts at the required frequency.
- */
-static void prvSetupTimerInterrupt( void )
-{
-uint32_t ulCompareMatch;
-extern void ( vTickISR )( void );
-
-	/* A 1ms tick does not require the use of the timer prescale.  This is
-	defaulted to zero but can be used if necessary. */
-	T0_PR = portPRESCALE_VALUE;
-
-	/* Calculate the match value required for our wanted tick rate. */
-	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-
-	/* Protect against divide by zero.  Using an if() statement still results
-	in a warning - hence the #if. */
-	#if portPRESCALE_VALUE != 0
-	{
-		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
-	}
-	#endif
-	T0_MR0 = ulCompareMatch;
-
-	/* Generate tick with timer 0 compare match. */
-	T0_MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
-
-	/* Setup the VIC for the timer. */
-	VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
-	VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
-	
-	/* The ISR installed depends on whether the preemptive or cooperative
-	scheduler is being used. */
-
-	VICVectAddr0 = ( int32_t ) vTickISR;
-	VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
-
-	/* Start the timer - interrupts are disabled when this function is called
-	so it is okay to do this here. */
-	T0_TCR = portENABLE_TIMER;
-}
-/*-----------------------------------------------------------*/
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portISR.c b/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portISR.c
deleted file mode 100755
index 9912644..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portISR.c
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c  The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
-
-/*
-	Changes from V2.5.2
-
-	+ The critical section management functions have been changed.  These no
-	  longer modify the stack and are safe to use at all optimisation levels.
-	  The functions are now also the same for both ARM and THUMB modes.
-
-	Changes from V2.6.0
-
-	+ Removed the 'static' from the definition of vNonPreemptiveTick() to
-	  allow the demo to link when using the cooperative scheduler.
-
-	Changes from V3.2.4
-
-	+ The assembler statements are now included in a single asm block rather
-	  than each line having its own asm block.
-*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/*-----------------------------------------------------------*/
-
-/* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
-
-/*
- * The scheduler can only be started from ARM mode, hence the inclusion of this
- * function here.
- */
-void vPortISRStartFirstTask( void );
-/*-----------------------------------------------------------*/
-
-void vPortISRStartFirstTask( void )
-{
-	/* Simply start the scheduler.  This is included here as it can only be
-	called from ARM mode. */
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Called by portYIELD() or taskYIELD() to manually force a context switch.
- *
- * When a context switch is performed from the task level the saved task
- * context is made to look as if it occurred from within the tick ISR.  This
- * way the same restore context function can be used when restoring the context
- * saved from the ISR or that saved from a call to vPortYieldProcessor.
- */
-void vPortYieldProcessor( void )
-{
-	/* Within an IRQ ISR the link register has an offset from the true return
-	address, but an SWI ISR does not.  Add the offset manually so the same
-	ISR return code can be used in both cases. */
-	__asm volatile ( "ADD		LR, LR, #4" );
-
-	/* Perform the context switch.  First save the context of the current task. */
-	portSAVE_CONTEXT();
-
-	/* Find the highest priority task that is ready to run. */
-	__asm volatile ( "bl vTaskSwitchContext" );
-
-	/* Restore the context of the new task. */
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * The ISR used for the scheduler tick.
- */
-void vTickISR( void ) __attribute__((naked));
-void vTickISR( void )
-{
-	/* Save the context of the interrupted task. */
-	portSAVE_CONTEXT();
-
-	/* Increment the RTOS tick count, then look for the highest priority
-	task that is ready to run. */
-	__asm volatile
-	(
-		"	bl xTaskIncrementTick	\t\n" \
-		"	cmp r0, #0				\t\n" \
-		"	beq SkipContextSwitch	\t\n" \
-		"	bl vTaskSwitchContext	\t\n" \
-		"SkipContextSwitch:			\t\n"
-	);
-
-	/* Ready for the next interrupt. */
-	T0_IR = portTIMER_MATCH_ISR_BIT;
-	VICVectAddr = portCLEAR_VIC_INTERRUPT;
-
-	/* Restore the context of the new task. */
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt management utilities can only be called from ARM mode.  When
- * THUMB_INTERWORK is defined the utilities are defined as functions here to
- * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
- * the utilities are defined as macros in portmacro.h - as per other ports.
- */
-#ifdef THUMB_INTERWORK
-
-	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
-	void vPortDisableInterruptsFromThumb( void )
-	{
-		__asm volatile (
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
-			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
-			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
-			"BX		R14" );					/* Return back to thumb.					*/
-	}
-
-	void vPortEnableInterruptsFromThumb( void )
-	{
-		__asm volatile (
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
-			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
-			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
-			"BX		R14" );					/* Return back to thumb.					*/
-	}
-
-#endif /* THUMB_INTERWORK */
-
-/* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels.  The interrupt flags can therefore not always
-be saved to the stack.  Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
-void vPortEnterCritical( void )
-{
-	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
-	__asm volatile (
-		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
-		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
-		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
-		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
-		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as we are leaving a critical section. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then interrupts should be
-		re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Enable interrupts as per portEXIT_CRITICAL().					*/
-			__asm volatile (
-				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/
-				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/
-				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/
-				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/
-				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
-		}
-	}
-}
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portmacro.h
deleted file mode 100755
index f36f5a1..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_LPC2000/portmacro.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	portLONG
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-#define portNOP()					__asm volatile ( "NOP" );
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
-
-/*
- * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
- * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
- * are included here for efficiency.  An attempt to call one from
- * THUMB mode code will result in a compile time error.
- */
-
-#define portRESTORE_CONTEXT()											\
-{																		\
-extern volatile void * volatile pxCurrentTCB;							\
-extern volatile uint32_t ulCriticalNesting;					\
-																		\
-	/* Set the LR to the task stack. */									\
-	__asm volatile (													\
-	"LDR		R0, =pxCurrentTCB								\n\t"	\
-	"LDR		R0, [R0]										\n\t"	\
-	"LDR		LR, [R0]										\n\t"	\
-																		\
-	/* The critical nesting depth is the first item on the stack. */	\
-	/* Load it into the ulCriticalNesting variable. */					\
-	"LDR		R0, =ulCriticalNesting							\n\t"	\
-	"LDMFD	LR!, {R1}											\n\t"	\
-	"STR		R1, [R0]										\n\t"	\
-																		\
-	/* Get the SPSR from the stack. */									\
-	"LDMFD	LR!, {R0}											\n\t"	\
-	"MSR		SPSR, R0										\n\t"	\
-																		\
-	/* Restore all system mode registers for the task. */				\
-	"LDMFD	LR, {R0-R14}^										\n\t"	\
-	"NOP														\n\t"	\
-																		\
-	/* Restore the return address. */									\
-	"LDR		LR, [LR, #+60]									\n\t"	\
-																		\
-	/* And return - correcting the offset in the LR to obtain the */	\
-	/* correct address. */												\
-	"SUBS	PC, LR, #4											\n\t"	\
-	);																	\
-	( void ) ulCriticalNesting;											\
-	( void ) pxCurrentTCB;												\
-}
-/*-----------------------------------------------------------*/
-
-#define portSAVE_CONTEXT()												\
-{																		\
-extern volatile void * volatile pxCurrentTCB;							\
-extern volatile uint32_t ulCriticalNesting;					\
-																		\
-	/* Push R0 as we are going to use the register. */					\
-	__asm volatile (													\
-	"STMDB	SP!, {R0}											\n\t"	\
-																		\
-	/* Set R0 to point to the task stack pointer. */					\
-	"STMDB	SP,{SP}^											\n\t"	\
-	"NOP														\n\t"	\
-	"SUB	SP, SP, #4											\n\t"	\
-	"LDMIA	SP!,{R0}											\n\t"	\
-																		\
-	/* Push the return address onto the stack. */						\
-	"STMDB	R0!, {LR}											\n\t"	\
-																		\
-	/* Now we have saved LR we can use it instead of R0. */				\
-	"MOV	LR, R0												\n\t"	\
-																		\
-	/* Pop R0 so we can save it onto the system mode stack. */			\
-	"LDMIA	SP!, {R0}											\n\t"	\
-																		\
-	/* Push all the system mode registers onto the task stack. */		\
-	"STMDB	LR,{R0-LR}^											\n\t"	\
-	"NOP														\n\t"	\
-	"SUB	LR, LR, #60											\n\t"	\
-																		\
-	/* Push the SPSR onto the task stack. */							\
-	"MRS	R0, SPSR											\n\t"	\
-	"STMDB	LR!, {R0}											\n\t"	\
-																		\
-	"LDR	R0, =ulCriticalNesting								\n\t"	\
-	"LDR	R0, [R0]											\n\t"	\
-	"STMDB	LR!, {R0}											\n\t"	\
-																		\
-	/* Store the new top of stack for the task. */						\
-	"LDR	R0, =pxCurrentTCB									\n\t"	\
-	"LDR	R0, [R0]											\n\t"	\
-	"STR	LR, [R0]											\n\t"	\
-	);																	\
-	( void ) ulCriticalNesting;											\
-	( void ) pxCurrentTCB;												\
-}
-
-extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR()		vTaskSwitchContext()
-#define portYIELD()					__asm volatile ( "SWI 0" )
-/*-----------------------------------------------------------*/
-
-
-/* Critical section management. */
-
-/*
- * The interrupt management utilities can only be called from ARM mode.  When
- * THUMB_INTERWORK is defined the utilities are defined as functions in
- * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
- * defined then the utilities are defined as macros here - as per other ports.
- */
-
-#ifdef THUMB_INTERWORK
-
-	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
-	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
-	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
-
-#else
-
-	#define portDISABLE_INTERRUPTS()											\
-		__asm volatile (														\
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
-			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
-			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
-
-	#define portENABLE_INTERRUPTS()												\
-		__asm volatile (														\
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
-			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
-			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
-
-#endif /* THUMB_INTERWORK */
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL()		vPortEnterCritical();
-#define portEXIT_CRITICAL()			vPortExitCritical();
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/port.c b/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/port.c
deleted file mode 100755
index 2e2a81e..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/port.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM7 port.
- *
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in this file.  The ISR routines, which can only be compiled
- * to ARM mode are contained in portISR.c.
- *----------------------------------------------------------*/
-
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to setup the task context. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
-
-/* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER                ( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE              0x00
-#define portINTERRUPT_ON_MATCH          ( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH        ( ( uint32_t ) 0x02 )
-
-/* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL           ( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT       ( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE            ( ( uint32_t ) 0x0020 )
-
-/*-----------------------------------------------------------*/
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/* 
- * The scheduler can only be started from ARM mode, so 
- * vPortISRStartFirstSTask() is defined in portISR.c. 
- */
-extern void vPortISRStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/* 
- * Initialise the stack of a task to look exactly as if a call to 
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description. 
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
-	pxOriginalTOS = pxTopOfStack;
-	
-	/* To ensure asserts in tasks.c don't fail, although in this case the assert
-	is not really required. */
-	pxTopOfStack--;
-
-	/* Setup the initial stack of the task.  The stack is set exactly as 
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* First on the stack is the return address - which in this case is the
-	start of the task.  The offset is added to make the return address appear
-	as it would within an IRQ ISR. */
-	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* R14 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;	
-
-	/* When the task starts is will expect to find the function parameter in
-	R0. */
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The last thing onto the stack is the status register, which is set for
-	system mode, with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00 )
-	{
-		/* We want the task to start in thumb mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-
-	pxTopOfStack--;
-
-	/* Some optimisation levels use the stack differently to others.  This 
-	means the interrupt flags cannot always be stored on the stack and will
-	instead be stored in a variable, which is then saved as part of the
-	tasks context. */
-	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task. */
-	vPortISRStartFirstTask();	
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the ARM port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the timer 0 to generate the tick interrupts at the required frequency.
- */
-static void prvSetupTimerInterrupt( void )
-{
-uint32_t ulCompareMatch;
-
-	PCLKSEL0 = (PCLKSEL0 & (~(0x3<<2))) | (0x01 << 2);
-	T0TCR  = 2;         /* Stop and reset the timer */
-	T0CTCR = 0;         /* Timer mode               */
-	
-	/* A 1ms tick does not require the use of the timer prescale.  This is
-	defaulted to zero but can be used if necessary. */
-	T0PR = portPRESCALE_VALUE;
-
-	/* Calculate the match value required for our wanted tick rate. */
-	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-
-	/* Protect against divide by zero.  Using an if() statement still results
-	in a warning - hence the #if. */
-	#if portPRESCALE_VALUE != 0
-	{
-		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
-	}
-	#endif
-	T0MR1 = ulCompareMatch;
-
-	/* Generate tick with timer 0 compare match. */
-	T0MCR  = (3 << 3);  /* Reset timer on match and generate interrupt */
-
-	/* Setup the VIC for the timer. */
-	VICIntEnable = 0x00000010;
-	
-	/* The ISR installed depends on whether the preemptive or cooperative
-	scheduler is being used. */
-	#if configUSE_PREEMPTION == 1
-	{
-		extern void ( vPreemptiveTick )( void );
-		VICVectAddr4 = ( int32_t ) vPreemptiveTick;
-	}
-	#else
-	{
-		extern void ( vNonPreemptiveTick )( void );
-		VICVectAddr4 = ( int32_t ) vNonPreemptiveTick;
-	}
-	#endif
-
-	VICVectCntl4 = 1;
-
-	/* Start the timer - interrupts are disabled when this function is called
-	so it is okay to do this here. */
-	T0TCR = portENABLE_TIMER;
-}
-/*-----------------------------------------------------------*/
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portISR.c b/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portISR.c
deleted file mode 100755
index 1e25640..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portISR.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c  The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/*-----------------------------------------------------------*/
-
-/* ISR to handle manual context switches (from a call to taskYIELD()). */
-void vPortYieldProcessor( void ) __attribute__((interrupt("SWI"), naked));
-
-/* 
- * The scheduler can only be started from ARM mode, hence the inclusion of this
- * function here.
- */
-void vPortISRStartFirstTask( void );
-/*-----------------------------------------------------------*/
-
-void vPortISRStartFirstTask( void )
-{
-	/* Simply start the scheduler.  This is included here as it can only be
-	called from ARM mode. */
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Called by portYIELD() or taskYIELD() to manually force a context switch.
- *
- * When a context switch is performed from the task level the saved task 
- * context is made to look as if it occurred from within the tick ISR.  This
- * way the same restore context function can be used when restoring the context
- * saved from the ISR or that saved from a call to vPortYieldProcessor.
- */
-void vPortYieldProcessor( void )
-{
-	/* Within an IRQ ISR the link register has an offset from the true return 
-	address, but an SWI ISR does not.  Add the offset manually so the same 
-	ISR return code can be used in both cases. */
-	__asm volatile ( "ADD		LR, LR, #4" );
-
-	/* Perform the context switch.  First save the context of the current task. */
-	portSAVE_CONTEXT();
-
-	/* Find the highest priority task that is ready to run. */
-	__asm volatile( "bl			vTaskSwitchContext" );
-
-	/* Restore the context of the new task. */
-	portRESTORE_CONTEXT();	
-}
-/*-----------------------------------------------------------*/
-
-/* 
- * The ISR used for the scheduler tick depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-
-
-#if configUSE_PREEMPTION == 0
-
-	/* The cooperative scheduler requires a normal IRQ service routine to 
-	simply increment the system tick. */
-	void vNonPreemptiveTick( void ) __attribute__ ((interrupt ("IRQ")));
-	void vNonPreemptiveTick( void )
-	{	
-		xTaskIncrementTick();
-		T0IR = 2;
-		VICVectAddr = portCLEAR_VIC_INTERRUPT;
-	}
-
-#else
-
-	/* The preemptive scheduler is defined as "naked" as the full context is
-	saved on entry as part of the context switch. */
-	void vPreemptiveTick( void ) __attribute__((naked));
-	void vPreemptiveTick( void )
-	{
-		/* Save the context of the interrupted task. */
-		portSAVE_CONTEXT();	
-
-		/* Increment the RTOS tick count, then look for the highest priority 
-		task that is ready to run. */
-		__asm volatile
-		(
-			"	bl xTaskIncrementTick	\t\n" \
-			"	cmp r0, #0				\t\n" \
-			"	beq SkipContextSwitch	\t\n" \
-			"	bl vTaskSwitchContext	\t\n" \
-			"SkipContextSwitch:			\t\n"
-		);
-
-		/* Ready for the next interrupt. */
-		T0IR = 2;
-		VICVectAddr = portCLEAR_VIC_INTERRUPT;
-		
-		/* Restore the context of the new task. */
-		portRESTORE_CONTEXT();
-	}
-
-#endif
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt management utilities can only be called from ARM mode.  When
- * THUMB_INTERWORK is defined the utilities are defined as functions here to
- * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
- * the utilities are defined as macros in portmacro.h - as per other ports.
- */
-#ifdef THUMB_INTERWORK
-
-	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
-	void vPortDisableInterruptsFromThumb( void )
-	{
-		__asm volatile ( 
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
-			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
-			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
-			"BX		R14" );					/* Return back to thumb.					*/
-	}
-			
-	void vPortEnableInterruptsFromThumb( void )
-	{
-		__asm volatile ( 
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
-			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
-			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
-			"BX		R14" );					/* Return back to thumb.					*/
-	}
-
-#endif /* THUMB_INTERWORK */
-
-/* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels.  The interrupt flags can therefore not always
-be saved to the stack.  Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
-void vPortEnterCritical( void )
-{
-	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
-	__asm volatile ( 
-		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
-		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
-		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
-		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
-		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed 
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as we are leaving a critical section. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then interrupts should be
-		re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Enable interrupts as per portEXIT_CRITICAL().					*/
-			__asm volatile ( 
-				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
-				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
-				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
-				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
-				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
-		}
-	}
-}
diff --git a/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portmacro.h
deleted file mode 100755
index 0ef784c..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM7_LPC23xx/portmacro.h
+++ /dev/null
@@ -1,249 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-	Changes from V3.2.3
-
-	+ Modified portENTER_SWITCHING_ISR() to allow use with GCC V4.0.1.
-
-	Changes from V3.2.4
-
-	+ Removed the use of the %0 parameter within the assembler macros and
-	  replaced them with hard coded registers.  This will ensure the
-	  assembler does not select the link register as the temp register as
-	  was occasionally happening previously.
-
-	+ The assembler statements are now included in a single asm block rather
-	  than each line having its own asm block.
-
-	Changes from V4.5.0
-
-	+ Removed the portENTER_SWITCHING_ISR() and portEXIT_SWITCHING_ISR() macros
-	  and replaced them with portYIELD_FROM_ISR() macro.  Application code
-	  should now make use of the portSAVE_CONTEXT() and portRESTORE_CONTEXT()
-	  macros as per the V4.5.1 demo code.
-*/
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	portLONG
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-#define portNOP()					__asm volatile ( "NOP" );
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
-
-/*
- * portRESTORE_CONTEXT, portRESTORE_CONTEXT, portENTER_SWITCHING_ISR
- * and portEXIT_SWITCHING_ISR can only be called from ARM mode, but
- * are included here for efficiency.  An attempt to call one from
- * THUMB mode code will result in a compile time error.
- */
-
-#define portRESTORE_CONTEXT()											\
-{																		\
-extern volatile void * volatile pxCurrentTCB;							\
-extern volatile uint32_t ulCriticalNesting;					\
-																		\
-	/* Set the LR to the task stack. */									\
-	__asm volatile (													\
-	"LDR		R0, =pxCurrentTCB								\n\t"	\
-	"LDR		R0, [R0]										\n\t"	\
-	"LDR		LR, [R0]										\n\t"	\
-																		\
-	/* The critical nesting depth is the first item on the stack. */	\
-	/* Load it into the ulCriticalNesting variable. */					\
-	"LDR		R0, =ulCriticalNesting							\n\t"	\
-	"LDMFD	LR!, {R1}											\n\t"	\
-	"STR		R1, [R0]										\n\t"	\
-																		\
-	/* Get the SPSR from the stack. */									\
-	"LDMFD	LR!, {R0}											\n\t"	\
-	"MSR		SPSR, R0										\n\t"	\
-																		\
-	/* Restore all system mode registers for the task. */				\
-	"LDMFD	LR, {R0-R14}^										\n\t"	\
-	"NOP														\n\t"	\
-																		\
-	/* Restore the return address. */									\
-	"LDR		LR, [LR, #+60]									\n\t"	\
-																		\
-	/* And return - correcting the offset in the LR to obtain the */	\
-	/* correct address. */												\
-	"SUBS	PC, LR, #4											\n\t"	\
-	);																	\
-	( void ) ulCriticalNesting;											\
-	( void ) pxCurrentTCB;												\
-}
-/*-----------------------------------------------------------*/
-
-#define portSAVE_CONTEXT()												\
-{																		\
-extern volatile void * volatile pxCurrentTCB;							\
-extern volatile uint32_t ulCriticalNesting;					\
-																		\
-	/* Push R0 as we are going to use the register. */					\
-	__asm volatile (													\
-	"STMDB	SP!, {R0}											\n\t"	\
-																		\
-	/* Set R0 to point to the task stack pointer. */					\
-	"STMDB	SP,{SP}^											\n\t"	\
-	"NOP														\n\t"	\
-	"SUB	SP, SP, #4											\n\t"	\
-	"LDMIA	SP!,{R0}											\n\t"	\
-																		\
-	/* Push the return address onto the stack. */						\
-	"STMDB	R0!, {LR}											\n\t"	\
-																		\
-	/* Now we have saved LR we can use it instead of R0. */				\
-	"MOV	LR, R0												\n\t"	\
-																		\
-	/* Pop R0 so we can save it onto the system mode stack. */			\
-	"LDMIA	SP!, {R0}											\n\t"	\
-																		\
-	/* Push all the system mode registers onto the task stack. */		\
-	"STMDB	LR,{R0-LR}^											\n\t"	\
-	"NOP														\n\t"	\
-	"SUB	LR, LR, #60											\n\t"	\
-																		\
-	/* Push the SPSR onto the task stack. */							\
-	"MRS	R0, SPSR											\n\t"	\
-	"STMDB	LR!, {R0}											\n\t"	\
-																		\
-	"LDR	R0, =ulCriticalNesting								\n\t"	\
-	"LDR	R0, [R0]											\n\t"	\
-	"STMDB	LR!, {R0}											\n\t"	\
-																		\
-	/* Store the new top of stack for the task. */						\
-	"LDR	R0, =pxCurrentTCB									\n\t"	\
-	"LDR	R0, [R0]											\n\t"	\
-	"STR	LR, [R0]											\n\t"	\
-	);																	\
-	( void ) ulCriticalNesting;											\
-	( void ) pxCurrentTCB;												\
-}
-
-
-#define portYIELD_FROM_ISR()		vTaskSwitchContext()
-#define portYIELD()					__asm volatile ( "SWI 0" )
-/*-----------------------------------------------------------*/
-
-
-/* Critical section management. */
-
-/*
- * The interrupt management utilities can only be called from ARM mode.  When
- * THUMB_INTERWORK is defined the utilities are defined as functions in
- * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
- * defined then the utilities are defined as macros here - as per other ports.
- */
-
-#ifdef THUMB_INTERWORK
-
-	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
-	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
-	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
-
-#else
-
-	#define portDISABLE_INTERRUPTS()											\
-		__asm volatile (															\
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
-			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
-			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
-
-	#define portENABLE_INTERRUPTS()												\
-		__asm volatile (															\
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
-			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
-			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
-
-#endif /* THUMB_INTERWORK */
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL()		vPortEnterCritical();
-#define portEXIT_CRITICAL()			vPortExitCritical();
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
deleted file mode 100755
index d6e1e64..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/port.c
+++ /dev/null
@@ -1,518 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
-	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
-	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configUNIQUE_INTERRUPT_PRIORITIES
-	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configSETUP_TICK_INTERRUPT
-	#error configSETUP_TICK_INTERRUPT() must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif /* configSETUP_TICK_INTERRUPT */
-
-#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/* In case security extensions are implemented. */
-#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-#endif
-
-/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
-portmacro.h. */
-#ifndef configCLEAR_TICK_INTERRUPT
-	#define configCLEAR_TICK_INTERRUPT()
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING			( ( size_t ) 0 )
-
-/* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE				( 0xFFUL )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
-
-/* Constants required to setup the initial task context. */
-#define portSP_ELx						( ( StackType_t ) 0x01 )
-#define portSP_EL0						( ( StackType_t ) 0x00 )
-
-#if defined( GUEST )
-	#define portEL1						( ( StackType_t ) 0x04 )
-	#define portINITIAL_PSTATE				( portEL1 | portSP_EL0 )
-#else
-	#define portEL3						( ( StackType_t ) 0x0c )
-	/* At the time of writing, the BSP only supports EL3. */
-	#define portINITIAL_PSTATE			( portEL3 | portSP_EL0 )
-#endif
-
-
-/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
-
-/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK			( 0x0C )
-
-/* The I bit in the DAIF bits. */
-#define portDAIF_I						( 0x80 )
-
-/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK()									\
-{																	\
-	portDISABLE_INTERRUPTS();										\
-	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;			\
-	__asm volatile (	"DSB SY		\n"								\
-						"ISB SY		\n" );							\
-	portENABLE_INTERRUPTS();										\
-}
-
-/* Hardware specifics used when sanity checking the configuration. */
-#define portINTERRUPT_PRIORITY_REGISTER_OFFSET		0x400UL
-#define portMAX_8_BIT_VALUE							( ( uint8_t ) 0xff )
-#define portBIT_0_SET								( ( uint8_t ) 0x01 )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing.  This function is necessarily written in
- * assembly code so is implemented in portASM.s.
- */
-extern void vPortRestoreTaskContext( void );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
-volatile uint64_t ullCriticalNesting = 9999ULL;
-
-/* Saved as part of the task context.  If ullPortTaskHasFPUContext is non-zero
-then floating point context must be saved and restored for the task. */
-uint64_t ullPortTaskHasFPUContext = pdFALSE;
-
-/* Set to 1 to pend a context switch from an ISR. */
-uint64_t ullPortYieldRequired = pdFALSE;
-
-/* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
-uint64_t ullPortInterruptNesting = 0;
-
-/* Used in the ASM code. */
-__attribute__(( used )) const uint64_t ullICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
-__attribute__(( used )) const uint64_t ullICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
-__attribute__(( used )) const uint64_t ullICCPMR = portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
-__attribute__(( used )) const uint64_t ullMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* First all the general purpose registers. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x0101010101010101ULL;	/* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x0303030303030303ULL;	/* R3 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x0202020202020202ULL;	/* R2 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x0505050505050505ULL;	/* R5 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x0404040404040404ULL;	/* R4 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x0707070707070707ULL;	/* R7 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x0606060606060606ULL;	/* R6 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x0909090909090909ULL;	/* R9 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x0808080808080808ULL;	/* R8 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x1111111111111111ULL;	/* R11 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x1010101010101010ULL;	/* R10 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x1313131313131313ULL;	/* R13 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x1212121212121212ULL;	/* R12 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x1515151515151515ULL;	/* R15 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x1414141414141414ULL;	/* R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x1717171717171717ULL;	/* R17 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x1616161616161616ULL;	/* R16 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x1919191919191919ULL;	/* R19 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x1818181818181818ULL;	/* R18 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2121212121212121ULL;	/* R21 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2020202020202020ULL;	/* R20 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2323232323232323ULL;	/* R23 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2222222222222222ULL;	/* R22 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2525252525252525ULL;	/* R25 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2424242424242424ULL;	/* R24 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2727272727272727ULL;	/* R27 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2626262626262626ULL;	/* R26 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2929292929292929ULL;	/* R29 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2828282828282828ULL;	/* R28 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00;	/* XZR - has no effect, used so there are an even number of registers. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00;	/* R30 - procedure call link register. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = portINITIAL_PSTATE;
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) pxCode; /* Exception return address. */
-	pxTopOfStack--;
-
-	/* The task will start with a critical nesting count of 0 as interrupts are
-	enabled. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-	pxTopOfStack--;
-
-	/* The task will start without a floating point context.  A task that uses
-	the floating point hardware must call vPortTaskUsesFPU() before executing
-	any floating point instructions. */
-	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-uint32_t ulAPSR;
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine how many priority bits are implemented in the GIC.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to
-		all possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Shift to the least significant bits. */
-		while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
-		{
-			ucMaxPriorityValue >>= ( uint8_t ) 0x01;
-		}
-
-		/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
-		value. */
-
-		configASSERT( ucMaxPriorityValue >= portLOWEST_INTERRUPT_PRIORITY );
-
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-
-	/* At the time of writing, the BSP only supports EL3. */
-	__asm volatile ( "MRS %0, CurrentEL" : "=r" ( ulAPSR ) );
-	ulAPSR &= portAPSR_MODE_BITS_MASK;
-
-#if defined( GUEST )
-	#warning Building for execution as a guest under XEN. THIS IS NOT A FULLY TESTED PATH.
-	configASSERT( ulAPSR == portEL1 );
-	if( ulAPSR == portEL1 )
-#else
-	configASSERT( ulAPSR == portEL3 );
-	if( ulAPSR == portEL3 )
-#endif
-	{
-		/* Only continue if the binary point value is set to its lowest possible
-		setting.  See the comments in vPortValidateInterruptPriority() below for
-		more information. */
-		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
-
-		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
-		{
-			/* Interrupts are turned off in the CPU itself to ensure a tick does
-			not execute	while the scheduler is being started.  Interrupts are
-			automatically turned back on in the CPU when the first task starts
-			executing. */
-			portDISABLE_INTERRUPTS();
-
-			/* Start the timer that generates the tick ISR. */
-			configSETUP_TICK_INTERRUPT();
-
-			/* Start the first task executing. */
-			vPortRestoreTaskContext();
-		}
-	}
-
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( ullCriticalNesting == 1000ULL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	/* Mask interrupts up to the max syscall interrupt priority. */
-	uxPortSetInterruptMask();
-
-	/* Now interrupts are disabled ullCriticalNesting can be accessed
-	directly.  Increment ullCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ullCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( ullCriticalNesting == 1ULL )
-	{
-		configASSERT( ullPortInterruptNesting == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ullCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as the critical section is being
-		exited. */
-		ullCriticalNesting--;
-
-		/* If the nesting level has reached zero then all interrupt
-		priorities must be re-enabled. */
-		if( ullCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Critical nesting has reached zero so all interrupt priorities
-			should be unmasked. */
-			portCLEAR_INTERRUPT_MASK();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void FreeRTOS_Tick_Handler( void )
-{
-	/* Must be the lowest possible priority. */
-	#if !defined( QEMU )
-	{
-		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER == ( uint32_t ) ( portLOWEST_USABLE_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
-	}
-	#endif
-
-	/* Interrupts should not be enabled before this point. */
-	#if( configASSERT_DEFINED == 1 )
-	{
-		uint32_t ulMaskBits;
-
-		__asm volatile( "mrs %0, daif" : "=r"( ulMaskBits ) :: "memory" );
-		configASSERT( ( ulMaskBits & portDAIF_I ) != 0 );
-	}
-	#endif /* configASSERT_DEFINED */
-
-	/* Set interrupt mask before altering scheduler structures.   The tick
-	handler runs at the lowest priority, so interrupts cannot already be masked,
-	so there is no need to save and restore the current mask value.  It is
-	necessary to turn off interrupts in the CPU itself while the ICCPMR is being
-	updated. */
-	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-	__asm volatile (	"dsb sy		\n"
-						"isb sy		\n" ::: "memory" );
-
-	/* Ok to enable interrupts after the interrupt source has been cleared. */
-	configCLEAR_TICK_INTERRUPT();
-	portENABLE_INTERRUPTS();
-
-	/* Increment the RTOS tick. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		ullPortYieldRequired = pdTRUE;
-	}
-
-	/* Ensure all interrupt priorities are active again. */
-	portCLEAR_INTERRUPT_MASK();
-}
-/*-----------------------------------------------------------*/
-
-void vPortTaskUsesFPU( void )
-{
-	/* A task is registering the fact that it needs an FPU context.  Set the
-	FPU flag (which is saved as part of the task context). */
-	ullPortTaskHasFPUContext = pdTRUE;
-
-	/* Consider initialising the FPSR here - but probably not necessary in
-	AArch64. */
-}
-/*-----------------------------------------------------------*/
-
-void vPortClearInterruptMask( UBaseType_t uxNewMaskValue )
-{
-	if( uxNewMaskValue == pdFALSE )
-	{
-		portCLEAR_INTERRUPT_MASK();
-	}
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxPortSetInterruptMask( void )
-{
-uint32_t ulReturn;
-
-	/* Interrupt in the CPU must be turned off while the ICCPMR is being
-	updated. */
-	portDISABLE_INTERRUPTS();
-	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
-	{
-		/* Interrupts were already masked. */
-		ulReturn = pdTRUE;
-	}
-	else
-	{
-		ulReturn = pdFALSE;
-		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-		__asm volatile (	"dsb sy		\n"
-							"isb sy		\n" ::: "memory" );
-	}
-	portENABLE_INTERRUPTS();
-
-	return ulReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-		/* The following assertion will fail if a service routine (ISR) for
-		an interrupt that has been assigned a priority above
-		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-		function.  ISR safe FreeRTOS API functions must *only* be called
-		from interrupts that have been assigned a priority at or below
-		configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-		Numerically low interrupt priority numbers represent logically high
-		interrupt priorities, therefore the priority of the interrupt must
-		be set to a value equal to or numerically *higher* than
-		configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-		FreeRTOS maintains separate thread and ISR API functions to ensure
-		interrupt entry is as fast and simple as possible. */
-		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
-
-		/* Priority grouping:  The interrupt controller (GIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		The priority grouping is configured by the GIC's binary point register
-		(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
-		possible value (which may be above 0). */
-		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
-	}
-
-#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S
deleted file mode 100755
index 5d07851..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portASM.S
+++ /dev/null
@@ -1,431 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	.text
-
-	/* Variables and functions. */
-	.extern ullMaxAPIPriorityMask
-	.extern pxCurrentTCB
-	.extern vTaskSwitchContext
-	.extern vApplicationIRQHandler
-	.extern ullPortInterruptNesting
-	.extern ullPortTaskHasFPUContext
-	.extern ullCriticalNesting
-	.extern ullPortYieldRequired
-	.extern ullICCEOIR
-	.extern ullICCIAR
-	.extern _freertos_vector_table
-
-	.global FreeRTOS_IRQ_Handler
-	.global FreeRTOS_SWI_Handler
-	.global vPortRestoreTaskContext
-
-
-.macro portSAVE_CONTEXT
-
-	/* Switch to use the EL0 stack pointer. */
-	MSR 	SPSEL, #0
-
-	/* Save the entire context. */
-	STP 	X0, X1, [SP, #-0x10]!
-	STP 	X2, X3, [SP, #-0x10]!
-	STP 	X4, X5, [SP, #-0x10]!
-	STP 	X6, X7, [SP, #-0x10]!
-	STP 	X8, X9, [SP, #-0x10]!
-	STP 	X10, X11, [SP, #-0x10]!
-	STP 	X12, X13, [SP, #-0x10]!
-	STP 	X14, X15, [SP, #-0x10]!
-	STP 	X16, X17, [SP, #-0x10]!
-	STP 	X18, X19, [SP, #-0x10]!
-	STP 	X20, X21, [SP, #-0x10]!
-	STP 	X22, X23, [SP, #-0x10]!
-	STP 	X24, X25, [SP, #-0x10]!
-	STP 	X26, X27, [SP, #-0x10]!
-	STP 	X28, X29, [SP, #-0x10]!
-	STP 	X30, XZR, [SP, #-0x10]!
-
-	/* Save the SPSR. */
-#if defined( GUEST )
-	MRS		X3, SPSR_EL1
-	MRS		X2, ELR_EL1
-#else
-	MRS		X3, SPSR_EL3
-	/* Save the ELR. */
-	MRS		X2, ELR_EL3
-#endif
-
-	STP 	X2, X3, [SP, #-0x10]!
-
-	/* Save the critical section nesting depth. */
-	LDR		X0, ullCriticalNestingConst
-	LDR		X3, [X0]
-
-	/* Save the FPU context indicator. */
-	LDR		X0, ullPortTaskHasFPUContextConst
-	LDR		X2, [X0]
-
-	/* Save the FPU context, if any (32 128-bit registers). */
-	CMP		X2, #0
-	B.EQ	1f
-	STP		Q0, Q1, [SP,#-0x20]!
-	STP		Q2, Q3, [SP,#-0x20]!
-	STP		Q4, Q5, [SP,#-0x20]!
-	STP		Q6, Q7, [SP,#-0x20]!
-	STP		Q8, Q9, [SP,#-0x20]!
-	STP		Q10, Q11, [SP,#-0x20]!
-	STP		Q12, Q13, [SP,#-0x20]!
-	STP		Q14, Q15, [SP,#-0x20]!
-	STP		Q16, Q17, [SP,#-0x20]!
-	STP		Q18, Q19, [SP,#-0x20]!
-	STP		Q20, Q21, [SP,#-0x20]!
-	STP		Q22, Q23, [SP,#-0x20]!
-	STP		Q24, Q25, [SP,#-0x20]!
-	STP		Q26, Q27, [SP,#-0x20]!
-	STP		Q28, Q29, [SP,#-0x20]!
-	STP		Q30, Q31, [SP,#-0x20]!
-
-1:
-	/* Store the critical nesting count and FPU context indicator. */
-	STP 	X2, X3, [SP, #-0x10]!
-
-	LDR 	X0, pxCurrentTCBConst
-	LDR 	X1, [X0]
-	MOV 	X0, SP   /* Move SP into X0 for saving. */
-	STR 	X0, [X1]
-
-	/* Switch to use the ELx stack pointer. */
-	MSR 	SPSEL, #1
-
-	.endm
-
-; /**********************************************************************/
-
-.macro portRESTORE_CONTEXT
-
-	/* Switch to use the EL0 stack pointer. */
-	MSR 	SPSEL, #0
-
-	/* Set the SP to point to the stack of the task being restored. */
-	LDR		X0, pxCurrentTCBConst
-	LDR		X1, [X0]
-	LDR		X0, [X1]
-	MOV		SP, X0
-
-	LDP 	X2, X3, [SP], #0x10  /* Critical nesting and FPU context. */
-
-	/* Set the PMR register to be correct for the current critical nesting
-	depth. */
-	LDR		X0, ullCriticalNestingConst /* X0 holds the address of ullCriticalNesting. */
-	MOV		X1, #255					/* X1 holds the unmask value. */
-	LDR		X4, ullICCPMRConst			/* X4 holds the address of the ICCPMR constant. */
-	CMP		X3, #0
-	LDR		X5, [X4] 					/* X5 holds the address of the ICCPMR register. */
-	B.EQ	1f
-	LDR		X6, ullMaxAPIPriorityMaskConst
-	LDR		X1, [X6]					/* X1 holds the mask value. */
-1:
-	STR		W1, [X5]					/* Write the mask value to ICCPMR. */
-	DSB 	SY							/* _RB_Barriers probably not required here. */
-	ISB 	SY
-	STR		X3, [X0]					/* Restore the task's critical nesting count. */
-
-	/* Restore the FPU context indicator. */
-	LDR		X0, ullPortTaskHasFPUContextConst
-	STR		X2, [X0]
-
-	/* Restore the FPU context, if any. */
-	CMP		X2, #0
-	B.EQ	1f
-	LDP		Q30, Q31, [SP], #0x20
-	LDP		Q28, Q29, [SP], #0x20
-	LDP		Q26, Q27, [SP], #0x20
-	LDP		Q24, Q25, [SP], #0x20
-	LDP		Q22, Q23, [SP], #0x20
-	LDP		Q20, Q21, [SP], #0x20
-	LDP		Q18, Q19, [SP], #0x20
-	LDP		Q16, Q17, [SP], #0x20
-	LDP		Q14, Q15, [SP], #0x20
-	LDP		Q12, Q13, [SP], #0x20
-	LDP		Q10, Q11, [SP], #0x20
-	LDP		Q8, Q9, [SP], #0x20
-	LDP		Q6, Q7, [SP], #0x20
-	LDP		Q4, Q5, [SP], #0x20
-	LDP		Q2, Q3, [SP], #0x20
-	LDP		Q0, Q1, [SP], #0x20
-1:
-	LDP 	X2, X3, [SP], #0x10  /* SPSR and ELR. */
-
-#if defined( GUEST )
-	/* Restore the SPSR. */
-	MSR		SPSR_EL1, X3
-	/* Restore the ELR. */
-	MSR		ELR_EL1, X2
-#else
-	/* Restore the SPSR. */
-	MSR		SPSR_EL3, X3 /*_RB_ Assumes started in EL3. */
-	/* Restore the ELR. */
-	MSR		ELR_EL3, X2
-#endif
-
-	LDP 	X30, XZR, [SP], #0x10
-	LDP 	X28, X29, [SP], #0x10
-	LDP 	X26, X27, [SP], #0x10
-	LDP 	X24, X25, [SP], #0x10
-	LDP 	X22, X23, [SP], #0x10
-	LDP 	X20, X21, [SP], #0x10
-	LDP 	X18, X19, [SP], #0x10
-	LDP 	X16, X17, [SP], #0x10
-	LDP 	X14, X15, [SP], #0x10
-	LDP 	X12, X13, [SP], #0x10
-	LDP 	X10, X11, [SP], #0x10
-	LDP 	X8, X9, [SP], #0x10
-	LDP 	X6, X7, [SP], #0x10
-	LDP 	X4, X5, [SP], #0x10
-	LDP 	X2, X3, [SP], #0x10
-	LDP 	X0, X1, [SP], #0x10
-
-	/* Switch to use the ELx stack pointer.  _RB_ Might not be required. */
-	MSR 	SPSEL, #1
-
-	ERET
-
-	.endm
-
-
-/******************************************************************************
- * FreeRTOS_SWI_Handler handler is used to perform a context switch.
- *****************************************************************************/
-.align 8
-.type FreeRTOS_SWI_Handler, %function
-FreeRTOS_SWI_Handler:
-	/* Save the context of the current task and select a new task to run. */
-	portSAVE_CONTEXT
-#if defined( GUEST )
-	MRS		X0, ESR_EL1
-#else
-	MRS		X0, ESR_EL3
-#endif
-
-	LSR		X1, X0, #26
-
-#if defined( GUEST )
-	CMP		X1, #0x15 	/* 0x15 = SVC instruction. */
-#else
-	CMP		X1, #0x17 	/* 0x17 = SMC instruction. */
-#endif
-	B.NE	FreeRTOS_Abort
-	BL 		vTaskSwitchContext
-
-	portRESTORE_CONTEXT
-
-FreeRTOS_Abort:
-	/* Full ESR is in X0, exception class code is in X1. */
-	B		.
-
-/******************************************************************************
- * vPortRestoreTaskContext is used to start the scheduler.
- *****************************************************************************/
-.align 8
-.type vPortRestoreTaskContext, %function
-vPortRestoreTaskContext:
-.set freertos_vector_base,	_freertos_vector_table
-
-	/* Install the FreeRTOS interrupt handlers. */
-	LDR		X1, =freertos_vector_base
-#if defined( GUEST )
-	MSR		VBAR_EL1, X1
-#else
-	MSR		VBAR_EL3, X1
-#endif
-	DSB		SY
-	ISB		SY
-
-	/* Start the first task. */
-	portRESTORE_CONTEXT
-
-
-/******************************************************************************
- * FreeRTOS_IRQ_Handler handles IRQ entry and exit.
- *****************************************************************************/
-.align 8
-.type FreeRTOS_IRQ_Handler, %function
-FreeRTOS_IRQ_Handler:
-	/* Save volatile registers. */
-	STP		X0, X1, [SP, #-0x10]!
-	STP		X2, X3, [SP, #-0x10]!
-	STP		X4, X5, [SP, #-0x10]!
-	STP		X6, X7, [SP, #-0x10]!
-	STP		X8, X9, [SP, #-0x10]!
-	STP		X10, X11, [SP, #-0x10]!
-	STP		X12, X13, [SP, #-0x10]!
-	STP		X14, X15, [SP, #-0x10]!
-	STP		X16, X17, [SP, #-0x10]!
-	STP		X18, X19, [SP, #-0x10]!
-	STP		X29, X30, [SP, #-0x10]!
-
-	/* Save the SPSR and ELR. */
-#if defined( GUEST )
-	MRS		X3, SPSR_EL1
-	MRS		X2, ELR_EL1
-#else
-	MRS		X3, SPSR_EL3
-	MRS		X2, ELR_EL3
-#endif
-	STP 	X2, X3, [SP, #-0x10]!
-
-	/* Increment the interrupt nesting counter. */
-	LDR		X5, ullPortInterruptNestingConst
-	LDR		X1, [X5]	/* Old nesting count in X1. */
-	ADD		X6, X1, #1
-	STR		X6, [X5]	/* Address of nesting count variable in X5. */
-
-	/* Maintain the interrupt nesting information across the function call. */
-	STP		X1, X5, [SP, #-0x10]!
-
-	/* Read value from the interrupt acknowledge register, which is stored in W0
-	for future parameter and interrupt clearing use. */
-	LDR 	X2, ullICCIARConst
-	LDR		X3, [X2]
-	LDR		W0, [X3]	/* ICCIAR in W0 as parameter. */
-
-	/* Maintain the ICCIAR value across the function call. */
-	STP		X0, X1, [SP, #-0x10]!
-
-	/* Call the C handler. */
-	BL vApplicationIRQHandler
-
-	/* Disable interrupts. */
-	MSR 	DAIFSET, #2
-	DSB		SY
-	ISB		SY
-
-	/* Restore the ICCIAR value. */
-	LDP		X0, X1, [SP], #0x10
-
-	/* End IRQ processing by writing ICCIAR to the EOI register. */
-	LDR 	X4, ullICCEOIRConst
-	LDR		X4, [X4]
-	STR		W0, [X4]
-
-	/* Restore the critical nesting count. */
-	LDP		X1, X5, [SP], #0x10
-	STR		X1, [X5]
-
-	/* Has interrupt nesting unwound? */
-	CMP		X1, #0
-	B.NE	Exit_IRQ_No_Context_Switch
-
-	/* Is a context switch required? */
-	LDR		X0, ullPortYieldRequiredConst
-	LDR		X1, [X0]
-	CMP		X1, #0
-	B.EQ	Exit_IRQ_No_Context_Switch
-
-	/* Reset ullPortYieldRequired to 0. */
-	MOV		X2, #0
-	STR		X2, [X0]
-
-	/* Restore volatile registers. */
-	LDP 	X4, X5, [SP], #0x10  /* SPSR and ELR. */
-#if defined( GUEST )
-	MSR		SPSR_EL1, X5
-	MSR		ELR_EL1, X4
-#else
-	MSR		SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
-	MSR		ELR_EL3, X4
-#endif
-	DSB		SY
-	ISB		SY
-
-	LDP		X29, X30, [SP], #0x10
-	LDP		X18, X19, [SP], #0x10
-	LDP		X16, X17, [SP], #0x10
-	LDP		X14, X15, [SP], #0x10
-	LDP		X12, X13, [SP], #0x10
-	LDP		X10, X11, [SP], #0x10
-	LDP		X8, X9, [SP], #0x10
-	LDP		X6, X7, [SP], #0x10
-	LDP		X4, X5, [SP], #0x10
-	LDP		X2, X3, [SP], #0x10
-	LDP		X0, X1, [SP], #0x10
-
-	/* Save the context of the current task and select a new task to run. */
-	portSAVE_CONTEXT
-	BL vTaskSwitchContext
-	portRESTORE_CONTEXT
-
-Exit_IRQ_No_Context_Switch:
-	/* Restore volatile registers. */
-	LDP 	X4, X5, [SP], #0x10  /* SPSR and ELR. */
-#if defined( GUEST )
-	MSR		SPSR_EL1, X5
-	MSR		ELR_EL1, X4
-#else
-	MSR		SPSR_EL3, X5 /*_RB_ Assumes started in EL3. */
-	MSR		ELR_EL3, X4
-#endif
-	DSB		SY
-	ISB		SY
-
-	LDP		X29, X30, [SP], #0x10
-	LDP		X18, X19, [SP], #0x10
-	LDP		X16, X17, [SP], #0x10
-	LDP		X14, X15, [SP], #0x10
-	LDP		X12, X13, [SP], #0x10
-	LDP		X10, X11, [SP], #0x10
-	LDP		X8, X9, [SP], #0x10
-	LDP		X6, X7, [SP], #0x10
-	LDP		X4, X5, [SP], #0x10
-	LDP		X2, X3, [SP], #0x10
-	LDP		X0, X1, [SP], #0x10
-
-	ERET
-
-
-
-
-.align 8
-pxCurrentTCBConst: .dword pxCurrentTCB
-ullCriticalNestingConst: .dword ullCriticalNesting
-ullPortTaskHasFPUContextConst: .dword ullPortTaskHasFPUContext
-
-ullICCPMRConst: .dword ullICCPMR
-ullMaxAPIPriorityMaskConst: .dword ullMaxAPIPriorityMask
-vApplicationIRQHandlerConst: .word vApplicationIRQHandler
-ullPortInterruptNestingConst: .dword ullPortInterruptNesting
-ullPortYieldRequiredConst: .dword ullPortYieldRequired
-ullICCIARConst:	.dword ullICCIAR
-ullICCEOIRConst: .dword ullICCEOIR
-
-
-
-.end
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
deleted file mode 100755
index f201cf0..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CA53_64_BIT/portmacro.h
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-	extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	size_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef portBASE_TYPE BaseType_t;
-typedef uint64_t UBaseType_t;
-
-typedef uint64_t TickType_t;
-#define portMAX_DELAY ( ( TickType_t ) 0xffffffffffffffff )
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			16
-#define portPOINTER_SIZE_TYPE 		uint64_t
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{												\
-extern uint64_t ullPortYieldRequired;			\
-												\
-	if( xSwitchRequired != pdFALSE )			\
-	{											\
-		ullPortYieldRequired = pdTRUE;			\
-	}											\
-}
-
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#if defined( GUEST )
-	#define portYIELD() __asm volatile ( "SVC 0" ::: "memory" )
-#else
-	#define portYIELD() __asm volatile ( "SMC 0" ::: "memory" )
-#endif
-/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern UBaseType_t uxPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( UBaseType_t uxNewMaskValue );
-extern void vPortInstallFreeRTOSVectorTable( void );
-
-#define portDISABLE_INTERRUPTS()									\
-	__asm volatile ( "MSR DAIFSET, #2" ::: "memory" );				\
-	__asm volatile ( "DSB SY" );									\
-	__asm volatile ( "ISB SY" );
-
-#define portENABLE_INTERRUPTS()										\
-	__asm volatile ( "MSR DAIFCLR, #2" ::: "memory" );				\
-	__asm volatile ( "DSB SY" );									\
-	__asm volatile ( "ISB SY" );
-
-
-/* These macros do not globally disable/enable interrupts.  They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL()		vPortEnterCritical();
-#define portEXIT_CRITICAL()			vPortExitCritical();
-#define portSET_INTERRUPT_MASK_FROM_ISR()		uxPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
-
-/* Prototype of the FreeRTOS tick handler.  This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
-void FreeRTOS_Tick_Handler( void );
-
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
-void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif /* configASSERT */
-
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE __inline
-
-#ifdef __cplusplus
-	} /* extern C */
-#endif
-
-
-/* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
-#if configUNIQUE_INTERRUPT_PRIORITIES == 16
-	#define portPRIORITY_SHIFT 4
-	#define portMAX_BINARY_POINT_VALUE	3
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
-	#define portPRIORITY_SHIFT 3
-	#define portMAX_BINARY_POINT_VALUE	2
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
-	#define portPRIORITY_SHIFT 2
-	#define portMAX_BINARY_POINT_VALUE	1
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
-	#define portPRIORITY_SHIFT 1
-	#define portMAX_BINARY_POINT_VALUE	0
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
-	#define portPRIORITY_SHIFT 0
-	#define portMAX_BINARY_POINT_VALUE	0
-#else
-	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
-
-/* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET  						( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET 				( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET 					( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET							( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET						( 0x14 )
-
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c b/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c
deleted file mode 100755
index 0f7c96c..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CA9/port.c
+++ /dev/null
@@ -1,568 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
-	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
-	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configUNIQUE_INTERRUPT_PRIORITIES
-	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configSETUP_TICK_INTERRUPT
-	#error configSETUP_TICK_INTERRUPT() must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif /* configSETUP_TICK_INTERRUPT */
-
-#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/* In case security extensions are implemented. */
-#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-#endif
-
-/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
-portmacro.h. */
-#ifndef configCLEAR_TICK_INTERRUPT
-	#define configCLEAR_TICK_INTERRUPT()
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
-
-/* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE				( 0xFFUL )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
-
-/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portINTERRUPT_ENABLE_BIT		( 0x80UL )
-#define portTHUMB_MODE_ADDRESS			( 0x01UL )
-
-/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
-
-/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK			( 0x1F )
-
-/* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE				( 0x10 )
-
-/* The critical section macros only mask interrupts up to an application
-determined priority level.  Sometimes it is necessary to turn interrupt off in
-the CPU itself before modifying certain hardware registers. */
-#define portCPU_IRQ_DISABLE()										\
-	__asm volatile ( "CPSID i" ::: "memory" );						\
-	__asm volatile ( "DSB" );										\
-	__asm volatile ( "ISB" );
-
-#define portCPU_IRQ_ENABLE()										\
-	__asm volatile ( "CPSIE i" ::: "memory" );						\
-	__asm volatile ( "DSB" );										\
-	__asm volatile ( "ISB" );
-
-
-/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK()									\
-{																	\
-	portCPU_IRQ_DISABLE();											\
-	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;			\
-	__asm volatile (	"DSB		\n"								\
-						"ISB		\n" );							\
-	portCPU_IRQ_ENABLE();											\
-}
-
-#define portINTERRUPT_PRIORITY_REGISTER_OFFSET		0x400UL
-#define portMAX_8_BIT_VALUE							( ( uint8_t ) 0xff )
-#define portBIT_0_SET								( ( uint8_t ) 0x01 )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/* The space on the stack required to hold the FPU registers.  This is 32 64-bit
-registers, plus a 32-bit status register. */
-#define portFPU_REGISTER_WORDS	( ( 32 * 2 ) + 1 )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing.  This function is necessarily written in
- * assembly code so is implemented in portASM.s.
- */
-extern void vPortRestoreTaskContext( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*
- * If the application provides an implementation of vApplicationIRQHandler(),
- * then it will get called directly without saving the FPU registers on
- * interrupt entry, and this weak implementation of
- * vApplicationFPUSafeIRQHandler() is just provided to remove linkage errors -
- * it should never actually get called so its implementation contains a
- * call to configASSERT() that will always fail.
- *
- * If the application provides its own implementation of
- * vApplicationFPUSafeIRQHandler() then the implementation of
- * vApplicationIRQHandler() provided in portASM.S will save the FPU registers
- * before calling it.
- *
- * Therefore, if the application writer wants FPU registers to be saved on
- * interrupt entry their IRQ handler must be called
- * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
- * FPU registers to be saved on interrupt entry their IRQ handler must be
- * called vApplicationIRQHandler().
- */
-void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR ) __attribute__((weak) );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
-volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
-
-/* Set to 1 to pend a context switch from an ISR. */
-volatile uint32_t ulPortYieldRequired = pdFALSE;
-
-/* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
-volatile uint32_t ulPortInterruptNesting = 0UL;
-
-/* Used in the asm file. */
-__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulICCPMR	= portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro.
-
-	The fist real value on the stack is the status register, which is set for
-	system mode, with interrupts enabled.  A few NULLs are added first to ensure
-	GDB does not try decoding a non-existent return address. */
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
-	{
-		/* The task will start in THUMB mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-
-	pxTopOfStack--;
-
-	/* Next the return address, which in this case is the start of the task. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-
-	/* Next all the registers other than the stack pointer. */
-	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The task will start with a critical nesting count of 0 as interrupts are
-	enabled. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-
-	#if( configUSE_TASK_FPU_SUPPORT == 1 )
-	{
-		/* The task will start without a floating point context.  A task that
-		uses the floating point hardware must call vPortTaskUsesFPU() before
-		executing any floating point instructions. */
-		pxTopOfStack--;
-		*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
-	}
-	#elif( configUSE_TASK_FPU_SUPPORT == 2 )
-	{
-		/* The task will start with a floating point context.  Leave enough
-		space for the registers - and ensure they are initialised to 0. */
-		pxTopOfStack -= portFPU_REGISTER_WORDS;
-		memset( pxTopOfStack, 0x00, portFPU_REGISTER_WORDS * sizeof( StackType_t ) );
-
-		pxTopOfStack--;
-		*pxTopOfStack = pdTRUE;
-		ulPortTaskHasFPUContext = pdTRUE;
-	}
-	#else
-	{
-		#error Invalid configUSE_TASK_FPU_SUPPORT setting - configUSE_TASK_FPU_SUPPORT must be set to 1, 2, or left undefined.
-	}
-	#endif
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( ulPortInterruptNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-uint32_t ulAPSR;
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine how many priority bits are implemented in the GIC.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to
-		all possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Shift to the least significant bits. */
-		while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
-		{
-			ucMaxPriorityValue >>= ( uint8_t ) 0x01;
-		}
-
-		/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
-		value. */
-		configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-
-	/* Only continue if the CPU is not in User mode.  The CPU must be in a
-	Privileged mode for the scheduler to start. */
-	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
-	ulAPSR &= portAPSR_MODE_BITS_MASK;
-	configASSERT( ulAPSR != portAPSR_USER_MODE );
-
-	if( ulAPSR != portAPSR_USER_MODE )
-	{
-		/* Only continue if the binary point value is set to its lowest possible
-		setting.  See the comments in vPortValidateInterruptPriority() below for
-		more information. */
-		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
-
-		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
-		{
-			/* Interrupts are turned off in the CPU itself to ensure tick does
-			not execute	while the scheduler is being started.  Interrupts are
-			automatically turned back on in the CPU when the first task starts
-			executing. */
-			portCPU_IRQ_DISABLE();
-
-			/* Start the timer that generates the tick ISR. */
-			configSETUP_TICK_INTERRUPT();
-
-			/* Start the first task executing. */
-			vPortRestoreTaskContext();
-		}
-	}
-
-	/* Will only get here if vTaskStartScheduler() was called with the CPU in
-	a non-privileged mode or the binary point register was not set to its lowest
-	possible value.  prvTaskExitError() is referenced to prevent a compiler
-	warning about it being defined but not referenced in the case that the user
-	defines their own exit address. */
-	( void ) prvTaskExitError;
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	/* Mask interrupts up to the max syscall interrupt priority. */
-	ulPortSetInterruptMask();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( ulCriticalNesting == 1 )
-	{
-		configASSERT( ulPortInterruptNesting == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as the critical section is being
-		exited. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then all interrupt
-		priorities must be re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Critical nesting has reached zero so all interrupt priorities
-			should be unmasked. */
-			portCLEAR_INTERRUPT_MASK();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void FreeRTOS_Tick_Handler( void )
-{
-	/* Set interrupt mask before altering scheduler structures.   The tick
-	handler runs at the lowest priority, so interrupts cannot already be masked,
-	so there is no need to save and restore the current mask value.  It is
-	necessary to turn off interrupts in the CPU itself while the ICCPMR is being
-	updated. */
-	portCPU_IRQ_DISABLE();
-	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-	__asm volatile (	"dsb		\n"
-						"isb		\n" ::: "memory" );
-	portCPU_IRQ_ENABLE();
-
-	/* Increment the RTOS tick. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		ulPortYieldRequired = pdTRUE;
-	}
-
-	/* Ensure all interrupt priorities are active again. */
-	portCLEAR_INTERRUPT_MASK();
-	configCLEAR_TICK_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_FPU_SUPPORT != 2 )
-
-	void vPortTaskUsesFPU( void )
-	{
-	uint32_t ulInitialFPSCR = 0;
-
-		/* A task is registering the fact that it needs an FPU context.  Set the
-		FPU flag (which is saved as part of the task context). */
-		ulPortTaskHasFPUContext = pdTRUE;
-
-		/* Initialise the floating point status register. */
-		__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
-	}
-
-#endif /* configUSE_TASK_FPU_SUPPORT */
-/*-----------------------------------------------------------*/
-
-void vPortClearInterruptMask( uint32_t ulNewMaskValue )
-{
-	if( ulNewMaskValue == pdFALSE )
-	{
-		portCLEAR_INTERRUPT_MASK();
-	}
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortSetInterruptMask( void )
-{
-uint32_t ulReturn;
-
-	/* Interrupt in the CPU must be turned off while the ICCPMR is being
-	updated. */
-	portCPU_IRQ_DISABLE();
-	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
-	{
-		/* Interrupts were already masked. */
-		ulReturn = pdTRUE;
-	}
-	else
-	{
-		ulReturn = pdFALSE;
-		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-		__asm volatile (	"dsb		\n"
-							"isb		\n" ::: "memory" );
-	}
-	portCPU_IRQ_ENABLE();
-
-	return ulReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-		/* The following assertion will fail if a service routine (ISR) for
-		an interrupt that has been assigned a priority above
-		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-		function.  ISR safe FreeRTOS API functions must *only* be called
-		from interrupts that have been assigned a priority at or below
-		configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-		Numerically low interrupt priority numbers represent logically high
-		interrupt priorities, therefore the priority of the interrupt must
-		be set to a value equal to or numerically *higher* than
-		configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-		FreeRTOS maintains separate thread and ISR API functions to ensure
-		interrupt entry is as fast and simple as possible. */
-		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
-
-		/* Priority grouping:  The interrupt controller (GIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		The priority grouping is configured by the GIC's binary point register
-		(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
-		possible value (which may be above 0). */
-		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
-	}
-
-#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
-
-void vApplicationFPUSafeIRQHandler( uint32_t ulICCIAR )
-{
-	( void ) ulICCIAR;
-	configASSERT( ( volatile void * ) NULL );
-}
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA9/portASM.S b/FreeRTOS/Source/portable/GCC/ARM_CA9/portASM.S
deleted file mode 100755
index f43ce96..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CA9/portASM.S
+++ /dev/null
@@ -1,323 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	.text
-	.arm
-
-	.set SYS_MODE,	0x1f
-	.set SVC_MODE,	0x13
-	.set IRQ_MODE,	0x12
-
-	/* Hardware registers. */
-	.extern ulICCIAR
-	.extern ulICCEOIR
-	.extern ulICCPMR
-
-	/* Variables and functions. */
-	.extern ulMaxAPIPriorityMask
-	.extern _freertos_vector_table
-	.extern pxCurrentTCB
-	.extern vTaskSwitchContext
-	.extern vApplicationIRQHandler
-	.extern ulPortInterruptNesting
-	.extern ulPortTaskHasFPUContext
-
-	.global FreeRTOS_IRQ_Handler
-	.global FreeRTOS_SWI_Handler
-	.global vPortRestoreTaskContext
-
-
-
-
-.macro portSAVE_CONTEXT
-
-	/* Save the LR and SPSR onto the system mode stack before switching to
-	system mode to save the remaining system mode registers. */
-	SRSDB	sp!, #SYS_MODE
-	CPS		#SYS_MODE
-	PUSH	{R0-R12, R14}
-
-	/* Push the critical nesting count. */
-	LDR		R2, ulCriticalNestingConst
-	LDR		R1, [R2]
-	PUSH	{R1}
-
-	/* Does the task have a floating point context that needs saving?  If
-	ulPortTaskHasFPUContext is 0 then no. */
-	LDR		R2, ulPortTaskHasFPUContextConst
-	LDR		R3, [R2]
-	CMP		R3, #0
-
-	/* Save the floating point context, if any. */
-	FMRXNE  R1,  FPSCR
-	VPUSHNE {D0-D15}
-	VPUSHNE	{D16-D31}
-	PUSHNE	{R1}
-
-	/* Save ulPortTaskHasFPUContext itself. */
-	PUSH	{R3}
-
-	/* Save the stack pointer in the TCB. */
-	LDR		R0, pxCurrentTCBConst
-	LDR		R1, [R0]
-	STR		SP, [R1]
-
-	.endm
-
-; /**********************************************************************/
-
-.macro portRESTORE_CONTEXT
-
-	/* Set the SP to point to the stack of the task being restored. */
-	LDR		R0, pxCurrentTCBConst
-	LDR		R1, [R0]
-	LDR		SP, [R1]
-
-	/* Is there a floating point context to restore?  If the restored
-	ulPortTaskHasFPUContext is zero then no. */
-	LDR		R0, ulPortTaskHasFPUContextConst
-	POP		{R1}
-	STR		R1, [R0]
-	CMP		R1, #0
-
-	/* Restore the floating point context, if any. */
-	POPNE 	{R0}
-	VPOPNE	{D16-D31}
-	VPOPNE	{D0-D15}
-	VMSRNE  FPSCR, R0
-
-	/* Restore the critical section nesting depth. */
-	LDR		R0, ulCriticalNestingConst
-	POP		{R1}
-	STR		R1, [R0]
-
-	/* Ensure the priority mask is correct for the critical nesting depth. */
-	LDR		R2, ulICCPMRConst
-	LDR		R2, [R2]
-	CMP		R1, #0
-	MOVEQ	R4, #255
-	LDRNE	R4, ulMaxAPIPriorityMaskConst
-	LDRNE	R4, [R4]
-	STR		R4, [R2]
-
-	/* Restore all system mode registers other than the SP (which is already
-	being used). */
-	POP		{R0-R12, R14}
-
-	/* Return to the task code, loading CPSR on the way. */
-	RFEIA	sp!
-
-	.endm
-
-
-
-
-/******************************************************************************
- * SVC handler is used to start the scheduler.
- *****************************************************************************/
-.align 4
-.type FreeRTOS_SWI_Handler, %function
-FreeRTOS_SWI_Handler:
-	/* Save the context of the current task and select a new task to run. */
-	portSAVE_CONTEXT
-	LDR R0, vTaskSwitchContextConst
-	BLX	R0
-	portRESTORE_CONTEXT
-
-
-/******************************************************************************
- * vPortRestoreTaskContext is used to start the scheduler.
- *****************************************************************************/
-.type vPortRestoreTaskContext, %function
-vPortRestoreTaskContext:
-	/* Switch to system mode. */
-	CPS		#SYS_MODE
-	portRESTORE_CONTEXT
-
-.align 4
-.type FreeRTOS_IRQ_Handler, %function
-FreeRTOS_IRQ_Handler:
-	/* Return to the interrupted instruction. */
-	SUB		lr, lr, #4
-
-	/* Push the return address and SPSR. */
-	PUSH	{lr}
-	MRS		lr, SPSR
-	PUSH	{lr}
-
-	/* Change to supervisor mode to allow reentry. */
-	CPS		#SVC_MODE
-
-	/* Push used registers. */
-	PUSH	{r0-r4, r12}
-
-	/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
-	for future use.  r1 holds the original ulPortInterruptNesting value for
-	future use. */
-	LDR		r3, ulPortInterruptNestingConst
-	LDR		r1, [r3]
-	ADD		r4, r1, #1
-	STR		r4, [r3]
-
-	/* Read value from the interrupt acknowledge register, which is stored in r0
-	for future parameter and interrupt clearing use. */
-	LDR 	r2, ulICCIARConst
-	LDR		r2, [r2]
-	LDR		r0, [r2]
-
-	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
-	future use.  _RB_ Does this ever actually need to be done provided the start
-	of the stack is 8-byte aligned? */
-	MOV		r2, sp
-	AND		r2, r2, #4
-	SUB		sp, sp, r2
-
-	/* Call the interrupt handler.  r4 pushed to maintain alignment. */
-	PUSH	{r0-r4, lr}
-	LDR		r1, vApplicationIRQHandlerConst
-	BLX		r1
-	POP		{r0-r4, lr}
-	ADD		sp, sp, r2
-
-	CPSID	i
-	DSB
-	ISB
-
-	/* Write the value read from ICCIAR to ICCEOIR. */
-	LDR 	r4, ulICCEOIRConst
-	LDR		r4, [r4]
-	STR		r0, [r4]
-
-	/* Restore the old nesting count. */
-	STR		r1, [r3]
-
-	/* A context switch is never performed if the nesting count is not 0. */
-	CMP		r1, #0
-	BNE		exit_without_switch
-
-	/* Did the interrupt request a context switch?  r1 holds the address of
-	ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
-	use. */
-	LDR		r1, =ulPortYieldRequired
-	LDR		r0, [r1]
-	CMP		r0, #0
-	BNE		switch_before_exit
-
-exit_without_switch:
-	/* No context switch.  Restore used registers, LR_irq and SPSR before
-	returning. */
-	POP		{r0-r4, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	MOVS	PC, LR
-
-switch_before_exit:
-	/* A context swtich is to be performed.  Clear the context switch pending
-	flag. */
-	MOV		r0, #0
-	STR		r0, [r1]
-
-	/* Restore used registers, LR-irq and SPSR before saving the context
-	to the task stack. */
-	POP		{r0-r4, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	portSAVE_CONTEXT
-
-	/* Call the function that selects the new task to execute.
-	vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
-	instructions, or 8 byte aligned stack allocated data.  LR does not need
-	saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
-	LDR		R0, vTaskSwitchContextConst
-	BLX		R0
-
-	/* Restore the context of, and branch to, the task selected to execute
-	next. */
-	portRESTORE_CONTEXT
-
-
-/******************************************************************************
- * If the application provides an implementation of vApplicationIRQHandler(),
- * then it will get called directly without saving the FPU registers on
- * interrupt entry, and this weak implementation of
- * vApplicationIRQHandler() will not get called.
- *
- * If the application provides its own implementation of
- * vApplicationFPUSafeIRQHandler() then this implementation of
- * vApplicationIRQHandler() will be called, save the FPU registers, and then
- * call vApplicationFPUSafeIRQHandler().
- *
- * Therefore, if the application writer wants FPU registers to be saved on
- * interrupt entry their IRQ handler must be called
- * vApplicationFPUSafeIRQHandler(), and if the application writer does not want
- * FPU registers to be saved on interrupt entry their IRQ handler must be
- * called vApplicationIRQHandler().
- *****************************************************************************/
-
-.align 4
-.weak vApplicationIRQHandler
-.type vApplicationIRQHandler, %function
-vApplicationIRQHandler:
-	PUSH	{LR}
-	FMRX	R1,  FPSCR
-	VPUSH	{D0-D15}
-	VPUSH	{D16-D31}
-	PUSH	{R1}
-
-	LDR		r1, vApplicationFPUSafeIRQHandlerConst
-	BLX		r1
-
-	POP		{R0}
-	VPOP	{D16-D31}
-	VPOP	{D0-D15}
-	VMSR	FPSCR, R0
-
-	POP {PC}
-
-
-ulICCIARConst:	.word ulICCIAR
-ulICCEOIRConst:	.word ulICCEOIR
-ulICCPMRConst: .word ulICCPMR
-pxCurrentTCBConst: .word pxCurrentTCB
-ulCriticalNestingConst: .word ulCriticalNesting
-ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
-ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
-vTaskSwitchContextConst: .word vTaskSwitchContext
-vApplicationIRQHandlerConst: .word vApplicationIRQHandler
-ulPortInterruptNestingConst: .word ulPortInterruptNesting
-vApplicationFPUSafeIRQHandlerConst: .word vApplicationFPUSafeIRQHandler
-
-.end
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
deleted file mode 100755
index ca82a7c..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CA9/portmacro.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-	extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{												\
-extern uint32_t ulPortYieldRequired;			\
-												\
-	if( xSwitchRequired != pdFALSE )			\
-	{											\
-		ulPortYieldRequired = pdTRUE;			\
-	}											\
-}
-
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
-
-
-/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-extern void vPortInstallFreeRTOSVectorTable( void );
-
-/* These macros do not globally disable/enable interrupts.  They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL()		vPortEnterCritical();
-#define portEXIT_CRITICAL()			vPortExitCritical();
-#define portDISABLE_INTERRUPTS()	ulPortSetInterruptMask()
-#define portENABLE_INTERRUPTS()		vPortClearInterruptMask( 0 )
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
-
-/* Prototype of the FreeRTOS tick handler.  This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
-void FreeRTOS_Tick_Handler( void );
-
-/* If configUSE_TASK_FPU_SUPPORT is set to 1 (or left undefined) then tasks are
-created without an FPU context and must call vPortTaskUsesFPU() to give
-themselves an FPU context before using any FPU instructions.  If
-configUSE_TASK_FPU_SUPPORT is set to 2 then all tasks will have an FPU context
-by default. */
-#if( configUSE_TASK_FPU_SUPPORT != 2 )
-	void vPortTaskUsesFPU( void );
-#else
-	/* Each task has an FPU context already, so define this function away to
-	nothing to prevent it being called accidentally. */
-	#define vPortTaskUsesFPU()
-#endif
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif /* configASSERT */
-
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE __inline
-
-#ifdef __cplusplus
-	} /* extern C */
-#endif
-
-
-/* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
-#if configUNIQUE_INTERRUPT_PRIORITIES == 16
-	#define portPRIORITY_SHIFT 4
-	#define portMAX_BINARY_POINT_VALUE	3
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
-	#define portPRIORITY_SHIFT 3
-	#define portMAX_BINARY_POINT_VALUE	2
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
-	#define portPRIORITY_SHIFT 2
-	#define portMAX_BINARY_POINT_VALUE	1
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
-	#define portPRIORITY_SHIFT 1
-	#define portMAX_BINARY_POINT_VALUE	0
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
-	#define portPRIORITY_SHIFT 0
-	#define portMAX_BINARY_POINT_VALUE	0
-#else
-	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
-
-/* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET  						( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET 				( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET 					( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET							( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET						( 0x14 )
-
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
deleted file mode 100755
index fe846d0..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM0/port.c
+++ /dev/null
@@ -1,362 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM0 port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL			( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD			( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE	( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL				( ( volatile uint32_t *) 0xe000ed04 )
-#define portNVIC_SYSPRI2				( ( volatile uint32_t *) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK			0x00000004
-#define portNVIC_SYSTICK_INT			0x00000002
-#define portNVIC_SYSTICK_ENABLE			0x00000001
-#define portNVIC_PENDSVSET				0x10000000
-#define portMIN_INTERRUPT_PRIORITY		( 255UL )
-#define portNVIC_PENDSV_PRI				( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI			( portMIN_INTERRUPT_PRIORITY << 24UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR			( 0x01000000 )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/*
- * Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__ (( naked ));
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void vPortStartFirstTask( void ) __attribute__ (( naked ));
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-	pxTopOfStack -= 8; /* R11..R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		started to remove a compiler warning about the function being defined
-		but never called.  ulDummy is used purely to quieten other warnings
-		about code appearing after this function is called - making ulDummy
-		volatile makes the compiler think the function could return and
-		therefore not output an 'unreachable code' warning for code that appears
-		after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
-	/* This function is no longer used, but retained for backward
-	compatibility. */
-}
-/*-----------------------------------------------------------*/
-
-void vPortStartFirstTask( void )
-{
-	/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
-	table offset register that can be used to locate the initial stack value.
-	Not all M0 parts have the application vector table at address 0. */
-	__asm volatile(
-	"	.syntax unified				\n"
-	"	ldr  r2, pxCurrentTCBConst2	\n" /* Obtain location of pxCurrentTCB. */
-	"	ldr  r3, [r2]				\n"
-	"	ldr  r0, [r3]				\n" /* The first item in pxCurrentTCB is the task top of stack. */
-	"	adds r0, #32					\n" /* Discard everything up to r0. */
-	"	msr  psp, r0					\n" /* This is now the new top of stack to use in the task. */
-	"	movs r0, #2					\n" /* Switch to the psp stack. */
-	"	msr  CONTROL, r0				\n"
-	"	isb							\n"
-	"	pop  {r0-r5}					\n" /* Pop the registers that are saved automatically. */
-	"	mov  lr, r5					\n" /* lr is now in r5. */
-	"	pop  {r3}					\n" /* Return address is now in r3. */
-	"	pop  {r2}					\n" /* Pop and discard XPSR. */
-	"	cpsie i						\n" /* The first task has its context and interrupts can be enabled. */
-	"	bx   r3						\n" /* Finally, jump to the user defined task code. */
-	"								\n"
-	"	.align 4					\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB	  "
-				  );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
-	*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Start the first task. */
-	vPortStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing!  Call the task
-	exit error function to prevent compiler warnings about a static function
-	not being called in the case that the application writer overrides this
-	functionality by defining configTASK_RETURN_ADDRESS.  Call
-	vTaskSwitchContext() so link time optimisation does not remove the
-	symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortYield( void )
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is completely
-	within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-    portDISABLE_INTERRUPTS();
-    uxCriticalNesting++;
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-    uxCriticalNesting--;
-    if( uxCriticalNesting == 0 )
-    {
-        portENABLE_INTERRUPTS();
-    }
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void )
-{
-	__asm volatile(
-					" mrs r0, PRIMASK	\n"
-					" cpsid i			\n"
-					" bx lr				  "
-					::: "memory"
-				  );
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* To avoid compiler warnings.  The return statement will nevere be reached,
-	but some compilers warn if it is not included, while others won't compile if
-	it is. */
-	return 0;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask )
-{
-	__asm volatile(
-					" msr PRIMASK, r0	\n"
-					" bx lr				  "
-					::: "memory"
-				  );
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* Just to avoid compiler warning.  ulMask is used from the asm code but
-	the compiler can't see that.  Some compilers generate warnings without the
-	following line, while others generate warnings if the line is included. */
-	( void ) ulMask;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
-	/* This is a naked function. */
-
-	__asm volatile
-	(
-	"	.syntax unified						\n"
-	"	mrs r0, psp							\n"
-	"										\n"
-	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
-	"	ldr	r2, [r3]						\n"
-	"										\n"
-	"	subs r0, r0, #32					\n" /* Make space for the remaining low registers. */
-	"	str r0, [r2]						\n" /* Save the new top of stack. */
-	"	stmia r0!, {r4-r7}					\n" /* Store the low registers that are not saved automatically. */
-	" 	mov r4, r8							\n" /* Store the high registers. */
-	" 	mov r5, r9							\n"
-	" 	mov r6, r10							\n"
-	" 	mov r7, r11							\n"
-	" 	stmia r0!, {r4-r7}					\n"
-	"										\n"
-	"	push {r3, r14}						\n"
-	"	cpsid i								\n"
-	"	bl vTaskSwitchContext				\n"
-	"	cpsie i								\n"
-	"	pop {r2, r3}						\n" /* lr goes in r3. r2 now holds tcb pointer. */
-	"										\n"
-	"	ldr r1, [r2]						\n"
-	"	ldr r0, [r1]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
-	"	adds r0, r0, #16					\n" /* Move to the high registers. */
-	"	ldmia r0!, {r4-r7}					\n" /* Pop the high registers. */
-	" 	mov r8, r4							\n"
-	" 	mov r9, r5							\n"
-	" 	mov r10, r6							\n"
-	" 	mov r11, r7							\n"
-	"										\n"
-	"	msr psp, r0							\n" /* Remember the new top of stack for the task. */
-	"										\n"
-	"	subs r0, r0, #32					\n" /* Go back for the low registers that are not automatically restored. */
-	" 	ldmia r0!, {r4-r7}					\n" /* Pop low registers.  */
-	"										\n"
-	"	bx r3								\n"
-	"										\n"
-	"	.align 4							\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB	  "
-	);
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-void prvSetupTimerInterrupt( void )
-{
-	/* Stop and reset the SysTick. */
-	*(portNVIC_SYSTICK_CTRL) = 0UL;
-	*(portNVIC_SYSTICK_CURRENT_VALUE) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
deleted file mode 100755
index a4fdae0..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM0/portmacro.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
-extern void vPortYield( void );
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portYIELD()					vPortYield()
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulSetInterruptMaskFromISR( void ) __attribute__((naked));
-extern void vClearInterruptMaskFromISR( uint32_t ulMask )  __attribute__((naked));
-
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()				__asm volatile 	( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()					__asm volatile 	( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#define portNOP()
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/port.c
deleted file mode 100755
index bd85a6f..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.c b/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
deleted file mode 100755
index c8345c7..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.c
+++ /dev/null
@@ -1,468 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r5, #1										\n" /* r5 = 1. */
-	"	bics r4, r5										\n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	movs r5, #4										\n" /* r5 = 4. */
-	"	str  r5, [r2]									\n" /* Program RNR = 4. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read first set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write first set of RBAR/RLAR registers. */
-	"	movs r5, #5										\n" /* r5 = 5. */
-	"	str  r5, [r2]									\n" /* Program RNR = 5. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read second set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write second set of RBAR/RLAR registers. */
-	"	movs r5, #6										\n" /* r5 = 6. */
-	"	str  r5, [r2]									\n" /* Program RNR = 6. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read third set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write third set of RBAR/RLAR registers. */
-	"	movs r5, #7										\n" /* r5 = 7. */
-	"	str  r5, [r2]									\n" /* Program RNR = 7. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst2							\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write fourth set of RBAR/RLAR registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r5, #1										\n" /* r5 = 1. */
-	"	orrs r4, r5										\n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	"	ldr  r5, xSecureContextConst2					\n"
-	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	"	ldr  r4, xSecureContextConst2					\n"
-	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	"xSecureContextConst2: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	tst r0, r1										\n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-	"	beq running_privileged							\n" /* If the result of previous AND operation was 0, branch. */
-	"	movs r0, #0										\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	bx lr											\n" /* Return. */
-	" running_privileged:								\n"
-	"	movs r0, #1										\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs r0, control									\n" /* Read the CONTROL register. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	bics r0, r1										\n" /* Clear the bit 0. */
-	"	msr control, r0									\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	orrs r0, r1										\n" /* r0 = r0 | r1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* To avoid compiler warnings.  The return statement will never be reached,
-	 * but some compilers warn if it is not included, while others won't compile
-	 * if it is. */
-	return 0;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* Just to avoid compiler warning.  ulMask is used from the asm code but
-	 * the compiler can't see that.  Some compilers generate warnings without
-	 * the following line, while others generate warnings if the line is
-	 * included. */
-	( void ) ulMask;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"	.extern SecureContext_SaveContext				\n"
-	"	.extern SecureContext_LoadContext				\n"
-	"													\n"
-	"	mrs r1, psp										\n" /* Read PSP in r1. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-	"													\n"
-	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
-	"	push {r0-r2, r14}								\n"
-	"	bl SecureContext_SaveContext					\n"
-	"	pop {r0-r3}										\n" /* LR is now in r3. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"	b select_next_task								\n"
-	"													\n"
-	" save_ns_context:									\n"
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
-	"	stmia r1!, {r4-r7}								\n" /* Store the low registers that are not saved automatically. */
-	"	mov r4, r8										\n" /* r4 = r8. */
-	"	mov r5, r9										\n" /* r5 = r9. */
-	"	mov r6, r10										\n" /* r6 = r10. */
-	"	mov r7, r11										\n" /* r7 = r11. */
-	"	stmia r1!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	subs r1, r1, #48								\n" /* r1 = r1 - 48. */
-	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r7}							\n" /* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
-	"	mov r4, r8										\n" /* r4 = r8. */
-	"	mov r5, r9										\n" /* r5 = r9. */
-	"	mov r6, r10										\n" /* r6 = r10. */
-	"	mov r7, r11										\n" /* r7 = r11. */
-	"	stmia r1!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" select_next_task:									\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r5, #1										\n" /* r5 = 1. */
-	"	bics r4, r5										\n" /* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	movs r5, #4										\n" /* r5 = 4. */
-	"	str  r5, [r2]									\n" /* Program RNR = 4. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read first set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write first set of RBAR/RLAR registers. */
-	"	movs r5, #5										\n" /* r5 = 5. */
-	"	str  r5, [r2]									\n" /* Program RNR = 5. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read second set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write second set of RBAR/RLAR registers. */
-	"	movs r5, #6										\n" /* r5 = 6. */
-	"	str  r5, [r2]									\n" /* Program RNR = 6. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read third set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write third set of RBAR/RLAR registers. */
-	"	movs r5, #7										\n" /* r5 = 7. */
-	"	str  r5, [r2]									\n" /* Program RNR = 7. */
-	"	ldmia r3!, {r6,r7}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
-	"	ldr  r4, xRBARConst								\n" /* r4 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r4!, {r6,r7}								\n" /* Write fourth set of RBAR/RLAR registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r5, #1										\n" /* r5 = 1. */
-	"	orrs r4, r5										\n" /* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r4}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r4}										\n"
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#else /* configENABLE_MPU */
-	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r3}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r3}										\n"
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" restore_ns_context:								\n"
-	"	adds r1, r1, #16								\n" /* Move to the high registers. */
-	"	ldmia r1!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
-	"	mov r8, r4										\n" /* r8 = r4. */
-	"	mov r9, r5										\n" /* r9 = r5. */
-	"	mov r10, r6										\n" /* r10 = r6. */
-	"	mov r11, r7										\n" /* r11 = r7. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	subs r1, r1, #32								\n" /* Go back to the low registers. */
-	"	ldmia r1!, {r4-r7}								\n" /* Restore the low registers that are not automatically restored. */
-	"	bx lr											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	"xSecureContextConst: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	movs r0, #4										\n"
-	"	mov r1, lr										\n"
-	"	tst r0, r1										\n"
-	"	beq stacking_used_msp							\n"
-	"	mrs r0, psp										\n"
-	"	ldr r2, svchandler_address_const				\n"
-	"	bx r2											\n"
-	" stacking_used_msp:								\n"
-	"	mrs r0, msp										\n"
-	"	ldr r2, svchandler_address_const				\n"
-	"	bx r2											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
-	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
-	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
-	"	beq free_secure_context							\n"
-	"	bx lr											\n" /* There is no secure context (xSecureContext is NULL). */
-	" free_secure_context:								\n"
-	"	svc %0											\n" /* Secure context is freed in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.h b/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
deleted file mode 100755
index 2ecf04e..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
deleted file mode 100755
index bbab1b7..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23/non_secure/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M23"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.c b/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.c
deleted file mode 100755
index 53535cd..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief CONTROL value for privileged tasks.
- *
- * Bit[0] - 0 --> Thread mode is privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
-
-/**
- * @brief CONTROL value for un-privileged tasks.
- *
- * Bit[0] - 1 --> Thread mode is un-privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Structure to represent secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first addess of the allocated memory.
- */
-typedef struct SecureContext
-{
-	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
-	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
-	uint8_t *pucStackStart;				/**< First location of the stack memory. */
-} SecureContext_t;
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* No stack for thread mode until a task's context is loaded. */
-		secureportSET_PSPLIM( securecontextNO_STACK );
-		secureportSET_PSP( securecontextNO_STACK );
-
-		#if( configENABLE_MPU == 1 )
-		{
-			/* Configure thread mode to use PSP and to be unprivileged. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-		}
-		#else /* configENABLE_MPU */
-		{
-			/* Configure thread mode to use PSP and to be privileged.. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-		}
-		#endif /* configENABLE_MPU */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
-#else /* configENABLE_MPU */
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
-#endif /* configENABLE_MPU */
-{
-	uint8_t *pucStackMemory = NULL;
-	uint32_t ulIPSR;
-	SecureContextHandle_t xSecureContextHandle = NULL;
-	#if( configENABLE_MPU == 1 )
-		uint32_t *pulCurrentStackPointer = NULL;
-	#endif /* configENABLE_MPU */
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Allocate the context structure. */
-		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
-
-		if( xSecureContextHandle != NULL )
-		{
-			/* Allocate the stack space. */
-			pucStackMemory = pvPortMalloc( ulSecureStackSize );
-
-			if( pucStackMemory != NULL )
-			{
-				/* Since stack grows down, the starting point will be the last
-				 * location. Note that this location is next to the last
-				 * allocated byte because the hardware decrements the stack
-				 * pointer before writing i.e. if stack pointer is 0x2, a push
-				 * operation will decrement the stack pointer to 0x1 and then
-				 * write at 0x1. */
-				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
-
-				/* The stack cannot go beyond this location. This value is
-				 * programmed in the PSPLIM register on context switch.*/
-				xSecureContextHandle->pucStackLimit = pucStackMemory;
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Store the correct CONTROL value for the task on the stack.
-					 * This value is programmed in the CONTROL register on
-					 * context switch. */
-					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
-					pulCurrentStackPointer--;
-					if( ulIsTaskPrivileged )
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-					}
-					else
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-					}
-
-					/* Store the current stack pointer. This value is programmed in
-					 * the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
-				}
-				#else /* configENABLE_MPU */
-				{
-					/* Current SP is set to the starting of the stack. This
-					 * value programmed in the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
-
-				}
-				#endif /* configENABLE_MPU */
-			}
-			else
-			{
-				/* Free the context to avoid memory leak and make sure to return
-				 * NULL to indicate failure. */
-				vPortFree( xSecureContextHandle );
-				xSecureContextHandle = NULL;
-			}
-		}
-	}
-
-	return xSecureContextHandle;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Ensure that valid parameters are passed. */
-		secureportASSERT( xSecureContextHandle != NULL );
-
-		/* Free the stack space. */
-		vPortFree( xSecureContextHandle->pucStackLimit );
-
-		/* Free the context itself. */
-		vPortFree( xSecureContextHandle );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.h b/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.h
deleted file mode 100755
index e148bff..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_CONTEXT_H__
-#define __SECURE_CONTEXT_H__
-
-/* Standard includes. */
-#include 
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/**
- * @brief PSP value when no task's context is loaded.
- */
-#define securecontextNO_STACK	0x0
-
-/**
- * @brief Opaque handle.
- */
-struct SecureContext;
-typedef struct SecureContext*	SecureContextHandle_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Initializes the secure context management system.
- *
- * PSP is set to NULL and therefore a task must allocate and load a context
- * before calling any secure side function in the thread mode.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureContext_Init( void );
-
-/**
- * @brief Allocates a context on the secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
- * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
- *
- * @return Opaque context handle if context is successfully allocated, NULL
- * otherwise.
- */
-#if( configENABLE_MPU == 1 )
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
-#else /* configENABLE_MPU */
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
-#endif /* configENABLE_MPU */
-
-/**
- * @brief Frees the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the
- * context to be freed.
- */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Loads the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be loaded.
- */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Saves the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be saved.
- */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
-
-#endif /* __SECURE_CONTEXT_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c b/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
deleted file mode 100755
index e703498..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_context_port.c
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-#if( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	"	msr control, r3							\n" /* CONTROL = r3. */
-	#endif /* configENABLE_MPU */
-	"	msr psplim, r2							\n" /* PSPLIM = r2. */
-	"	msr psp, r1								\n" /* PSP = r1. */
-	"											\n"
-	" load_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:::"r0", "r1", "r2"
-	);
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	mrs r1, psp								\n" /* r1 = PSP. */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r2, control							\n" /* r2 = CONTROL. */
-	"	subs r1, r1, #4							\n" /* Make space for the CONTROL value on the stack. */
-	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	"	stmia r1!, {r2}							\n" /* Store CONTROL value on the stack. */
-	#else /* configENABLE_MPU */
-	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	#endif /* configENABLE_MPU */
-	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
-	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
-	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-	"											\n"
-	" save_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.c b/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
deleted file mode 100755
index 60fce5c..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure context heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Total heap size.
- */
-#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
-
-/* No test marker by default. */
-#ifndef mtCOVERAGE_TEST_MARKER
-	#define mtCOVERAGE_TEST_MARKER()
-#endif
-
-/* No tracing by default. */
-#ifndef traceMALLOC
-	#define traceMALLOC( pvReturn, xWantedSize )
-#endif
-
-/* No tracing by default. */
-#ifndef traceFREE
-	#define traceFREE( pv, xBlockSize )
-#endif
-
-/* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
-/*-----------------------------------------------------------*/
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	 * heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#else /* configAPPLICATION_ALLOCATED_HEAP */
-	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/**
- * @brief The linked list structure.
- *
- * This is used to link free blocks in order of their memory address.
- */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
-	size_t xBlockSize;						/**< The size of the free block. */
-} BlockLink_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Called automatically to setup the required heap structures the first
- * time pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/**
- * @brief Inserts a block of memory that is being freed into the correct
- * position in the list of free memory blocks.
- *
- * The block being freed will be merged with the block in front it and/or the
- * block behind it if the memory blocks are adjacent to each other.
- *
- * @param[in] pxBlockToInsert The block being freed.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The size of the structure placed at the beginning of each allocated
- * memory block must by correctly byte aligned.
- */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-
-/**
- * @brief Create a couple of list links to mark the start and end of the list.
- */
-static BlockLink_t xStart, *pxEnd = NULL;
-
-/**
- * @brief Keeps track of the number of free bytes remaining, but says nothing
- * about fragmentation.
- */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-size_t uxAddress;
-size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
-
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	uxAddress = ( size_t ) ucHeap;
-
-	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
-	{
-		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
-		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-	}
-
-	pucAlignedHeap = ( uint8_t * ) uxAddress;
-
-	/* xStart is used to hold a pointer to the first item in the list of free
-	 * blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
-
-	/* pxEnd is used to mark the end of the list of free blocks and is inserted
-	 * at the end of the heap space. */
-	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-	uxAddress -= xHeapStructSize;
-	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-	pxEnd = ( void * ) uxAddress;
-	pxEnd->xBlockSize = 0;
-	pxEnd->pxNextFreeBlock = NULL;
-
-	/* To start with there is a single free block that is sized to take up the
-	 * entire heap space, minus the space taken by pxEnd. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
-	/* Only one block exists - and it covers the entire usable heap space. */
-	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
-{
-BlockLink_t *pxIterator;
-uint8_t *puc;
-
-	/* Iterate through the list until a block is found that has a higher address
-	 * than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
-
-	/* Do the block being inserted, and the block it is being inserted after
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Do the block being inserted, and the block it is being inserted before
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
-
-	/* If the block being inserted plugged a gab, so was merged with the block
-	 * before and the block after, then it's pxNextFreeBlock pointer will have
-	 * already been set, and should not be set here as that would make it point
-	 * to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
-
-	/* If this is the first call to malloc then the heap will require
-	 * initialisation to setup the list of free blocks. */
-	if( pxEnd == NULL )
-	{
-		prvHeapInit();
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Check the requested block size is not so large that the top bit is set.
-	 * The top bit of the block size member of the BlockLink_t structure is used
-	 * to determine who owns the block - the application or the kernel, so it
-	 * must be free. */
-	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-	{
-		/* The wanted size is increased so it can contain a BlockLink_t
-		 * structure in addition to the requested amount of bytes. */
-		if( xWantedSize > 0 )
-		{
-			xWantedSize += xHeapStructSize;
-
-			/* Ensure that blocks are always aligned to the required number of
-			 * bytes. */
-			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
-			{
-				/* Byte alignment required. */
-				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-		{
-			/* Traverse the list from the start (lowest address) block until
-			 * one of adequate size is found. */
-			pxPreviousBlock = &xStart;
-			pxBlock = xStart.pxNextFreeBlock;
-			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-			{
-				pxPreviousBlock = pxBlock;
-				pxBlock = pxBlock->pxNextFreeBlock;
-			}
-
-			/* If the end marker was reached then a block of adequate size was
-			 * not found. */
-			if( pxBlock != pxEnd )
-			{
-				/* Return the memory space pointed to - jumping over the
-				 * BlockLink_t structure at its start. */
-				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-				/* This block is being returned for use so must be taken out
-				 * of the list of free blocks. */
-				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-				/* If the block is larger than required it can be split into
-				 * two. */
-				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
-				{
-					/* This block is to be split into two.  Create a new
-					 * block following the number of bytes requested. The void
-					 * cast is used to prevent byte alignment warnings from the
-					 * compiler. */
-					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-
-					/* Calculate the sizes of two blocks split from the single
-					 * block. */
-					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-					pxBlock->xBlockSize = xWantedSize;
-
-					/* Insert the new block into the list of free blocks. */
-					prvInsertBlockIntoFreeList( pxNewBlockLink );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-				{
-					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* The block is being returned - it is allocated and owned by
-				 * the application and has no "next" block. */
-				pxBlock->xBlockSize |= xBlockAllocatedBit;
-				pxBlock->pxNextFreeBlock = NULL;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	traceMALLOC( pvReturn, xWantedSize );
-
-	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
-
-	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		 * before it. */
-		puc -= xHeapStructSize;
-
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
-
-		/* Check the block is actually allocated. */
-		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
-
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				 * allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-				secureportDISABLE_NON_SECURE_INTERRUPTS();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				secureportENABLE_NON_SECURE_INTERRUPTS();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.h b/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
deleted file mode 100755
index 69e4f2a..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_heap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_HEAP_H__
-#define __SECURE_HEAP_H__
-
-/* Standard includes. */
-#include 
-
-/**
- * @brief Allocates memory from heap.
- *
- * @param[in] xWantedSize The size of the memory to be allocated.
- *
- * @return Pointer to the memory region if the allocation is successful, NULL
- * otherwise.
- */
-void *pvPortMalloc( size_t xWantedSize );
-
-/**
- * @brief Frees the previously allocated memory.
- *
- * @param[in] pv Pointer to the memory to be freed.
- */
-void vPortFree( void *pv );
-
-#endif /* __SECURE_HEAP_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.c b/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.c
deleted file mode 100755
index c6525f7..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure init includes. */
-#include "secure_init.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS			( 29UL )
-#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS				( 26UL )
-#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
-
-#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS			( 10UL )
-#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS			( 11UL )
-#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
-									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
-									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
-		 * permitted. CP11 should be programmed to the same value as CP10. */
-		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
-
-		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
-		 * that we can enable/disable lazy stacking in port.c file. */
-		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
-
-		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
-		 * registers (S16-S31) are also pushed to stack on exception entry and
-		 * restored on exception return. */
-		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.h b/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.h
deleted file mode 100755
index 6c5bc71..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_init.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_INIT_H__
-#define __SECURE_INIT_H__
-
-/**
- * @brief De-prioritizes the non-secure exceptions.
- *
- * This is needed to ensure that the non-secure PendSV runs at the lowest
- * priority. Context switch is done in the non-secure PendSV handler.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_DePrioritizeNSExceptions( void );
-
-/**
- * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
- *
- * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
- * Registers are not leaked to the non-secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_EnableNSFPUAccess( void );
-
-#endif /* __SECURE_INIT_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h b/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
deleted file mode 100755
index 760edab..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23/secure/secure_port_macros.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_PORT_MACROS_H__
-#define __SECURE_PORT_MACROS_H__
-
-/**
- * @brief Byte alignment requirements.
- */
-#define secureportBYTE_ALIGNMENT					8
-#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
-
-/**
- * @brief Macro to declare a function as non-secure callable.
- */
-#if defined( __IAR_SYSTEMS_ICC__ )
-	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
-#else
-	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
-#endif
-
-/**
- * @brief Set the secure PRIMASK value.
- */
-#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Set the non-secure PRIMASK value.
- */
-#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Read the PSP value in the given variable.
- */
-#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
-	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
-
-/**
- * @brief Set the PSP to the given value.
- */
-#define secureportSET_PSP( pucCurrentStackPointer ) \
-	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
-
-/**
- * @brief Set the PSPLIM to the given value.
- */
-#define secureportSET_PSPLIM( pucStackLimit ) \
-	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
-
-/**
- * @brief Set the NonSecure MSP to the given value.
- */
-#define secureportSET_MSP_NS( pucMainStackPointer ) \
-	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
-
-/**
- * @brief Set the CONTROL register to the given value.
- */
-#define secureportSET_CONTROL( ulControl ) \
-	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
-
-/**
- * @brief Read the Interrupt Program Status Register (IPSR) value in the given
- * variable.
- */
-#define secureportREAD_IPSR( ulIPSR ) \
-	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
-
-/**
- * @brief PRIMASK value to enable interrupts.
- */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
-
-/**
- * @brief PRIMASK value to disable interrupts.
- */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
-
-/**
- * @brief Disable secure interrupts.
- */
-#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Disable non-secure interrupts.
- *
- * This effectively disables context switches.
- */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Enable non-secure interrupts.
- */
-#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Assert definition.
- */
-#define secureportASSERT( x )						\
-	if( ( x ) == 0 )								\
-	{												\
-		secureportDISABLE_SECURE_INTERRUPTS();		\
-		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
-		for( ;; );									\
-	}
-
-#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
deleted file mode 100755
index bd85a6f..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c b/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
deleted file mode 100755
index 5b8e604..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.c
+++ /dev/null
@@ -1,381 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r4, #1										\n" /* r4 = 1. */
-	"	bics r3, r4										\n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
-	"	str r3, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r1]									\n" /* r4 = *r1 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str  r4, [r2]									\n" /* Program RNR = 4. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read first set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write first set of RBAR/RLAR registers. */
-	"	movs r4, #5										\n" /* r4 = 5. */
-	"	str  r4, [r2]									\n" /* Program RNR = 5. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read second set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write second set of RBAR/RLAR registers. */
-	"	movs r4, #6										\n" /* r4 = 6. */
-	"	str  r4, [r2]									\n" /* Program RNR = 6. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read third set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write third set of RBAR/RLAR registers. */
-	"	movs r4, #7										\n" /* r4 = 7. */
-	"	str  r4, [r2]									\n" /* Program RNR = 7. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst2							\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write fourth set of RBAR/RLAR registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r4, #1										\n" /* r4 = 1. */
-	"	orrs r3, r4										\n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
-	"	str r3, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	tst r0, r1										\n" /* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-	"	beq running_privileged							\n" /* If the result of previous AND operation was 0, branch. */
-	"	movs r0, #0										\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	bx lr											\n" /* Return. */
-	" running_privileged:								\n"
-	"	movs r0, #1										\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs  r0, control								\n" /* Read the CONTROL register. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	bics r0, r1										\n" /* Clear the bit 0. */
-	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	movs r1, #1										\n" /* r1 = 1. */
-	"	orrs r0, r1										\n" /* r0 = r0 | r1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* To avoid compiler warnings.  The return statement will never be reached,
-	 * but some compilers warn if it is not included, while others won't compile
-	 * if it is. */
-	return 0;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* Just to avoid compiler warning.  ulMask is used from the asm code but
-	 * the compiler can't see that.  Some compilers generate warnings without
-	 * the following line, while others generate warnings if the line is
-	 * included. */
-	( void ) ulMask;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	mrs r0, psp										\n" /* Read PSP in r0. */
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r0, r0, #44								\n" /* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
-	"	mrs r2, control									\n" /* r2 = CONTROL. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r0!, {r1-r7}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
-	"	mov r4, r8										\n" /* r4 = r8. */
-	"	mov r5, r9										\n" /* r5 = r9. */
-	"	mov r6, r10										\n" /* r6 = r10. */
-	"	mov r7, r11										\n" /* r7 = r11. */
-	"	stmia r0!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
-	#else /* configENABLE_MPU */
-	"	subs r0, r0, #40								\n" /* Make space for PSPLIM, LR and the remaining registers on the stack. */
-	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r0!, {r2-r7}								\n" /* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
-	"	mov r4, r8										\n" /* r4 = r8. */
-	"	mov r5, r9										\n" /* r5 = r9. */
-	"	mov r6, r10										\n" /* r6 = r10. */
-	"	mov r7, r11										\n" /* r7 = r11. */
-	"	stmia r0!, {r4-r7}								\n" /* Store the high registers that are not saved automatically. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r4, #1										\n" /* r4 = 1. */
-	"	bics r3, r4										\n" /* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
-	"	str r3, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r1]									\n" /* r4 = *r1 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str  r4, [r2]									\n" /* Program RNR = 4. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read first set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write first set of RBAR/RLAR registers. */
-	"	movs r4, #5										\n" /* r4 = 5. */
-	"	str  r4, [r2]									\n" /* Program RNR = 5. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read second set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write second set of RBAR/RLAR registers. */
-	"	movs r4, #6										\n" /* r4 = 6. */
-	"	str  r4, [r2]									\n" /* Program RNR = 6. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read third set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write third set of RBAR/RLAR registers. */
-	"	movs r4, #7										\n" /* r4 = 7. */
-	"	str  r4, [r2]									\n" /* Program RNR = 7. */
-	"	ldmia r1!, {r5,r6}								\n" /* Read fourth set of RBAR/RLAR from TCB. */
-	"	ldr  r3, xRBARConst								\n" /* r3 = 0xe000ed9c [Location of RBAR]. */
-	"	stmia r3!, {r5,r6}								\n" /* Write fourth set of RBAR/RLAR registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r3, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	movs r4, #1										\n" /* r4 = 1. */
-	"	orrs r3, r4										\n" /* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
-	"	str r3, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	adds r0, r0, #28								\n" /* Move to the high registers. */
-	"	ldmia r0!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
-	"	mov r8, r4										\n" /* r8 = r4. */
-	"	mov r9, r5										\n" /* r9 = r5. */
-	"	mov r10, r6										\n" /* r10 = r6. */
-	"	mov r11, r7										\n" /* r11 = r7. */
-	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
-	"	subs r0, r0, #44								\n" /* Move to the starting of the saved context. */
-	"	ldmia r0!, {r1-r7}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
-	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
-	"	bx r3											\n"
-	#else /* configENABLE_MPU */
-	"	adds r0, r0, #24								\n" /* Move to the high registers. */
-	"	ldmia r0!, {r4-r7}								\n" /* Restore the high registers that are not automatically restored. */
-	"	mov r8, r4										\n" /* r8 = r4. */
-	"	mov r9, r5										\n" /* r9 = r5. */
-	"	mov r10, r6										\n" /* r10 = r6. */
-	"	mov r11, r7										\n" /* r11 = r7. */
-	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
-	"	subs r0, r0, #40								\n" /* Move to the starting of the saved context. */
-	"	ldmia r0!, {r2-r7}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	bx r3											\n"
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	movs r0, #4										\n"
-	"	mov r1, lr										\n"
-	"	tst r0, r1										\n"
-	"	beq stacking_used_msp							\n"
-	"	mrs r0, psp										\n"
-	"	ldr r2, svchandler_address_const				\n"
-	"	bx r2											\n"
-	" stacking_used_msp:								\n"
-	"	mrs r0, msp										\n"
-	"	ldr r2, svchandler_address_const				\n"
-	"	bx r2											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h b/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
deleted file mode 100755
index 2ecf04e..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
deleted file mode 100755
index bbab1b7..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM23_NTZ/non_secure/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M23"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
deleted file mode 100755
index 3c0c8e0..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3/port.c
+++ /dev/null
@@ -1,717 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM3 port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
-defined.  The value should also ensure backward compatibility.
-FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
-#ifndef configKERNEL_INTERRUPT_PRIORITY
-	#define configKERNEL_INTERRUPT_PRIORITY 255
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
-
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR					( 0x01000000UL )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR			( 45UL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__ (( naked ));
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void ) __attribute__ (( naked ));
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		started to remove a compiler warning about the function being defined
-		but never called.  ulDummy is used purely to quieten other warnings
-		about code appearing after this function is called - making ulDummy
-		volatile makes the compiler think the function could return and
-		therefore not output an 'unreachable code' warning for code that appears
-		after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
-	__asm volatile (
-					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
-					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
-					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
-					"	ldmia r0!, {r4-r11}				\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
-					"	msr psp, r0						\n" /* Restore the task stack pointer. */
-					"	isb								\n"
-					"	mov r0, #0 						\n"
-					"	msr	basepri, r0					\n"
-					"	orr r14, #0xd					\n"
-					"	bx r14							\n"
-					"									\n"
-					"	.align 4						\n"
-					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-				);
-}
-/*-----------------------------------------------------------*/
-
-static void prvPortStartFirstTask( void )
-{
-	__asm volatile(
-					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
-					" ldr r0, [r0] 			\n"
-					" ldr r0, [r0] 			\n"
-					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
-					" cpsie i				\n" /* Globally enable interrupts. */
-					" cpsie f				\n"
-					" dsb					\n"
-					" isb					\n"
-					" svc 0					\n" /* System call to start first task. */
-					" nop					\n"
-				);
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Start the first task. */
-	prvPortStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing!  Call the task
-	exit error function to prevent compiler warnings about a static function
-	not being called in the case that the application writer overrides this
-	functionality by defining configTASK_RETURN_ADDRESS.  Call
-	vTaskSwitchContext() so link time optimisation does not remove the
-	symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
-	/* This is a naked function. */
-
-	__asm volatile
-	(
-	"	mrs r0, psp							\n"
-	"	isb									\n"
-	"										\n"
-	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
-	"	ldr	r2, [r3]						\n"
-	"										\n"
-	"	stmdb r0!, {r4-r11}					\n" /* Save the remaining registers. */
-	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
-	"										\n"
-	"	stmdb sp!, {r3, r14}				\n"
-	"	mov r0, %0							\n"
-	"	msr basepri, r0						\n"
-	"	bl vTaskSwitchContext				\n"
-	"	mov r0, #0							\n"
-	"	msr basepri, r0						\n"
-	"	ldmia sp!, {r3, r14}				\n"
-	"										\n" /* Restore the context, including the critical nesting count. */
-	"	ldr r1, [r3]						\n"
-	"	ldr r0, [r1]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
-	"	ldmia r0!, {r4-r11}					\n" /* Pop the registers. */
-	"	msr psp, r0							\n"
-	"	isb									\n"
-	"	bx r14								\n"
-	"										\n"
-	"	.align 4							\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
-	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
-	);
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known. */
-	portDISABLE_INTERRUPTS();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TICKLESS_IDLE == 1 )
-
-	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-	TickType_t xModifiableIdleTime;
-
-		/* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
-		is accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-		/* Calculate the reload value required to wait xExpectedIdleTime
-		tick periods.  -1 is used because this code will execute part way
-		through one of the tick periods. */
-		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-		if( ulReloadValue > ulStoppedTimerCompensation )
-		{
-			ulReloadValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Enter a critical section but don't use the taskENTER_CRITICAL()
-		method as that will mask interrupts that should exit sleep mode. */
-		__asm volatile( "cpsid i" ::: "memory" );
-		__asm volatile( "dsb" );
-		__asm volatile( "isb" );
-
-		/* If a context switch is pending or a task is waiting for the scheduler
-		to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-		{
-			/* Restart from whatever is left in the count register to complete
-			this tick period. */
-			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Reset the reload register to the value required for normal tick
-			periods. */
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Re-enable interrupts - see comments above the cpsid instruction()
-			above. */
-			__asm volatile( "cpsie i" ::: "memory" );
-		}
-		else
-		{
-			/* Set the new reload value. */
-			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-			/* Clear the SysTick count flag and set the count value back to
-			zero. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-			set its parameter to 0 to indicate that its implementation contains
-			its own wait for interrupt or wait for event instruction, and so wfi
-			should not be executed again.  However, the original expected idle
-			time variable must remain unmodified, so a copy is taken. */
-			xModifiableIdleTime = xExpectedIdleTime;
-			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-			if( xModifiableIdleTime > 0 )
-			{
-				__asm volatile( "dsb" ::: "memory" );
-				__asm volatile( "wfi" );
-				__asm volatile( "isb" );
-			}
-			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-			/* Re-enable interrupts to allow the interrupt that brought the MCU
-			out of sleep mode to execute immediately.  see comments above
-			__disable_interrupt() call above. */
-			__asm volatile( "cpsie i" ::: "memory" );
-			__asm volatile( "dsb" );
-			__asm volatile( "isb" );
-
-			/* Disable interrupts again because the clock is about to be stopped
-			and interrupts that execute while the clock is stopped will increase
-			any slippage between the time maintained by the RTOS and calendar
-			time. */
-			__asm volatile( "cpsid i" ::: "memory" );
-			__asm volatile( "dsb" );
-			__asm volatile( "isb" );
-
-			/* Disable the SysTick clock without reading the
-			portNVIC_SYSTICK_CTRL_REG register to ensure the
-			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
-			the time the SysTick is stopped for is accounted for as best it can
-			be, but using the tickless mode will inevitably result in some tiny
-			drift of the time maintained by the kernel with respect to calendar
-			time*/
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-			/* Determine if the SysTick clock has already counted to zero and
-			been set back to the current reload value (the reload back being
-			correct for the entire expected idle time) or if the SysTick is yet
-			to count to zero (in which case an interrupt other than the SysTick
-			must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-			{
-				uint32_t ulCalculatedLoadValue;
-
-				/* The tick interrupt is already pending, and the SysTick count
-				reloaded with ulReloadValue.  Reset the
-				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-				period. */
-				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-				/* Don't allow a tiny value, or values that have somehow
-				underflowed because the post sleep hook did something
-				that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-				{
-					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-				}
-
-				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-				/* As the pending tick will be processed as soon as this
-				function exits, the tick value maintained by the tick is stepped
-				forward by one less than the time spent waiting. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				Work out how long the sleep lasted rounded to complete tick
-				periods (not the ulReload value which accounted for part
-				ticks). */
-				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-				/* How many complete tick periods passed while the processor
-				was waiting? */
-				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-				/* The reload value is set to whatever fraction of a single tick
-				period remains. */
-				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-			}
-
-			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-			vTaskStepTick( ulCompleteTickPeriods );
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Exit with interrpts enabled. */
-			__asm volatile( "cpsie i" ::: "memory" );
-		}
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
-{
-	/* Calculate the constants required to configure the tick interrupt. */
-	#if( configUSE_TICKLESS_IDLE == 1 )
-	{
-		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-	}
-	#endif /* configUSE_TICKLESS_IDLE */
-
-	/* Stop and clear the SysTick. */
-	portNVIC_SYSTICK_CTRL_REG = 0UL;
-	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		/* Obtain the number of the currently executing interrupt. */
-		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
deleted file mode 100755
index f1becb3..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3/portmacro.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD() 															\
-{																				\
-	/* Set a PendSV to request a context switch. */								\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
-																				\
-	/* Barriers are normally not required but do ensure the code is completely	\
-	within the specified behaviour for the architecture. */						\
-	__asm volatile( "dsb" ::: "memory" );										\
-	__asm volatile( "isb" );													\
-}
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
-#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
-#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Generic helper function. */
-	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-	{
-	uint8_t ucReturn;
-
-		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
-		return ucReturn;
-	}
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-#define portINLINE	__inline
-
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE inline __attribute__(( always_inline))
-#endif
-
-portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
-{
-uint32_t ulCurrentInterrupt;
-BaseType_t xReturn;
-
-	/* Obtain the number of the currently executing interrupt. */
-	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-	if( ulCurrentInterrupt == 0 )
-	{
-		xReturn = pdFALSE;
-	}
-	else
-	{
-		xReturn = pdTRUE;
-	}
-
-	return xReturn;
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortRaiseBASEPRI( void )
-{
-uint32_t ulNewBASEPRI;
-
-	__asm volatile
-	(
-		"	mov %0, %1												\n" \
-		"	msr basepri, %0											\n" \
-		"	isb														\n" \
-		"	dsb														\n" \
-		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
-{
-uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
-
-	__asm volatile
-	(
-		"	mrs %0, basepri											\n" \
-		"	mov %1, %2												\n" \
-		"	msr basepri, %1											\n" \
-		"	isb														\n" \
-		"	dsb														\n" \
-		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
-
-	/* This return will not be reached but is necessary to prevent compiler
-	warnings. */
-	return ulOriginalBASEPRI;
-}
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
-{
-	__asm volatile
-	(
-		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c
deleted file mode 100755
index bd85a6f..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c b/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
deleted file mode 100755
index 3a24f3a..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.c
+++ /dev/null
@@ -1,415 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r3]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr  r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str  r4, [r2]									\n" /* Program RNR = 4. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r3!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r4}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	"	ldr  r5, xSecureContextConst2					\n"
-	"	str  r1, [r5]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r3								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r4											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	"	ldr  r4, xSecureContextConst2					\n"
-	"	str  r1, [r4]									\n" /* Set xSecureContext to this task's value for the same. */
-	"	msr  psplim, r2									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	"xSecureContextConst2: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne											\n"
-	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs r0, control									\n" /* Read the CONTROL register. */
-	"	bic r0, #1										\n" /* Clear the bit 0. */
-	"	msr control, r0									\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	orr r0, #1										\n" /* r0 = r0 | 1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	cpsie f											\n"
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* To avoid compiler warnings.  The return statement will never be reached,
-	 * but some compilers warn if it is not included, while others won't compile
-	 * if it is. */
-	return 0;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* Just to avoid compiler warning.  ulMask is used from the asm code but
-	 * the compiler can't see that.  Some compilers generate warnings without
-	 * the following line, while others generate warnings if the line is
-	 * included. */
-	( void ) ulMask;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"	.extern SecureContext_SaveContext				\n"
-	"	.extern SecureContext_LoadContext				\n"
-	"													\n"
-	"	mrs r1, psp										\n" /* Read PSP in r1. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	ldr r0, [r2]									\n" /* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-	"													\n"
-	"	cbz r0, save_ns_context							\n" /* No secure context to save. */
-	"	push {r0-r2, r14}								\n"
-	"	bl SecureContext_SaveContext					\n"
-	"	pop {r0-r3}										\n" /* LR is now in r3. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl save_ns_context								\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #16								\n" /* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r4}							\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #12								\n" /* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"	b select_next_task								\n"
-	"													\n"
-	" save_ns_context:									\n"
-	"	ldr r3, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r2, [r3]									\n" /* Read pxCurrentTCB. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vstmdbeq r1!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	subs r1, r1, #48								\n" /* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #16								\n" /* r1 = r1 + 16. */
-	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mrs r3, control									\n" /* r3 = CONTROL. */
-	"	mov r4, lr										\n" /* r4 = LR/EXC_RETURN. */
-	"	subs r1, r1, #16								\n" /* r1 = r1 - 16. */
-	"	stm r1, {r0, r2-r4}								\n" /* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-	"	subs r1, r1, #44								\n" /* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-	"	str r1, [r2]									\n" /* Save the new top of stack in TCB. */
-	"	adds r1, r1, #12								\n" /* r1 = r1 + 12. */
-	"	stm r1, {r4-r11}								\n" /* Store the registers that are not saved automatically. */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	subs r1, r1, #12								\n" /* r1 = r1 - 12. */
-	"	stmia r1!, {r0, r2-r3}							\n" /* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" select_next_task:									\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r3, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r1, [r3]									\n" /* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	"	ldr r4, [r3]									\n" /* r4 = *r3 i.e. r4 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r4, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r4, #4										\n" /* r4 = 4. */
-	"	str r4, [r2]									\n" /* Program RNR = 4. */
-	"	adds r3, #4										\n" /* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r3!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r0, r2-r4}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r3									\n" /* Restore the CONTROL register value for the task. */
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r4}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r4}										\n"
-	"	mov lr, r4										\n" /* LR = r4. */
-	"	lsls r2, r4, #25								\n" /* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#else /* configENABLE_MPU */
-	"	ldmia r1!, {r0, r2-r3}							\n" /* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	ldr r2, xSecureContextConst						\n" /* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	"	str r0, [r2]									\n" /* Restore the task's xSecureContext. */
-	"	cbz r0, restore_ns_context						\n" /* If there is no secure context for the task, restore the non-secure context. */
-	"	push {r1,r3}									\n"
-	"	bl SecureContext_LoadContext					\n" /* Restore the secure context. */
-	"	pop {r1,r3}										\n"
-	"	mov lr, r3										\n" /* LR = r3. */
-	"	lsls r2, r3, #25								\n" /* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	"	bpl restore_ns_context							\n" /* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	#endif /* configENABLE_MPU */
-	"													\n"
-	" restore_ns_context:								\n"
-	"	ldmia r1!, {r4-r11}								\n" /* Restore the registers that are not automatically restored. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vldmiaeq r1!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-	"	msr psp, r1										\n" /* Remember the new top of stack for the task. */
-	"	bx lr											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	"xSecureContextConst: .word xSecureContext			\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	tst lr, #4										\n"
-	"	ite eq											\n"
-	"	mrseq r0, msp									\n"
-	"	mrsne r0, psp									\n"
-	"	ldr r1, svchandler_address_const				\n"
-	"	bx r1											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	svc %0											\n" /* Secure context is allocated in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_ALLOCATE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r1, [r0]									\n" /* The first item in the TCB is the top of the stack. */
-	"	ldr r0, [r1]									\n" /* The first item on the stack is the task's xSecureContext. */
-	"	cmp r0, #0										\n" /* Raise svc if task's xSecureContext is not NULL. */
-	"	it ne											\n"
-	"	svcne %0										\n" /* Secure context is freed in the supervisor call. */
-	"	bx lr											\n" /* Return. */
-	:: "i" ( portSVC_FREE_SECURE_CONTEXT ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h b/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
deleted file mode 100755
index 2ecf04e..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
deleted file mode 100755
index d051ddc..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33/non_secure/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c b/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c
deleted file mode 100755
index 53535cd..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief CONTROL value for privileged tasks.
- *
- * Bit[0] - 0 --> Thread mode is privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
-
-/**
- * @brief CONTROL value for un-privileged tasks.
- *
- * Bit[0] - 1 --> Thread mode is un-privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Structure to represent secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first addess of the allocated memory.
- */
-typedef struct SecureContext
-{
-	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
-	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
-	uint8_t *pucStackStart;				/**< First location of the stack memory. */
-} SecureContext_t;
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* No stack for thread mode until a task's context is loaded. */
-		secureportSET_PSPLIM( securecontextNO_STACK );
-		secureportSET_PSP( securecontextNO_STACK );
-
-		#if( configENABLE_MPU == 1 )
-		{
-			/* Configure thread mode to use PSP and to be unprivileged. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-		}
-		#else /* configENABLE_MPU */
-		{
-			/* Configure thread mode to use PSP and to be privileged.. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-		}
-		#endif /* configENABLE_MPU */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
-#else /* configENABLE_MPU */
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
-#endif /* configENABLE_MPU */
-{
-	uint8_t *pucStackMemory = NULL;
-	uint32_t ulIPSR;
-	SecureContextHandle_t xSecureContextHandle = NULL;
-	#if( configENABLE_MPU == 1 )
-		uint32_t *pulCurrentStackPointer = NULL;
-	#endif /* configENABLE_MPU */
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Allocate the context structure. */
-		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
-
-		if( xSecureContextHandle != NULL )
-		{
-			/* Allocate the stack space. */
-			pucStackMemory = pvPortMalloc( ulSecureStackSize );
-
-			if( pucStackMemory != NULL )
-			{
-				/* Since stack grows down, the starting point will be the last
-				 * location. Note that this location is next to the last
-				 * allocated byte because the hardware decrements the stack
-				 * pointer before writing i.e. if stack pointer is 0x2, a push
-				 * operation will decrement the stack pointer to 0x1 and then
-				 * write at 0x1. */
-				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
-
-				/* The stack cannot go beyond this location. This value is
-				 * programmed in the PSPLIM register on context switch.*/
-				xSecureContextHandle->pucStackLimit = pucStackMemory;
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Store the correct CONTROL value for the task on the stack.
-					 * This value is programmed in the CONTROL register on
-					 * context switch. */
-					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
-					pulCurrentStackPointer--;
-					if( ulIsTaskPrivileged )
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-					}
-					else
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-					}
-
-					/* Store the current stack pointer. This value is programmed in
-					 * the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
-				}
-				#else /* configENABLE_MPU */
-				{
-					/* Current SP is set to the starting of the stack. This
-					 * value programmed in the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
-
-				}
-				#endif /* configENABLE_MPU */
-			}
-			else
-			{
-				/* Free the context to avoid memory leak and make sure to return
-				 * NULL to indicate failure. */
-				vPortFree( xSecureContextHandle );
-				xSecureContextHandle = NULL;
-			}
-		}
-	}
-
-	return xSecureContextHandle;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Ensure that valid parameters are passed. */
-		secureportASSERT( xSecureContextHandle != NULL );
-
-		/* Free the stack space. */
-		vPortFree( xSecureContextHandle->pucStackLimit );
-
-		/* Free the context itself. */
-		vPortFree( xSecureContextHandle );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h b/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h
deleted file mode 100755
index e148bff..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_CONTEXT_H__
-#define __SECURE_CONTEXT_H__
-
-/* Standard includes. */
-#include 
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/**
- * @brief PSP value when no task's context is loaded.
- */
-#define securecontextNO_STACK	0x0
-
-/**
- * @brief Opaque handle.
- */
-struct SecureContext;
-typedef struct SecureContext*	SecureContextHandle_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Initializes the secure context management system.
- *
- * PSP is set to NULL and therefore a task must allocate and load a context
- * before calling any secure side function in the thread mode.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureContext_Init( void );
-
-/**
- * @brief Allocates a context on the secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
- * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
- *
- * @return Opaque context handle if context is successfully allocated, NULL
- * otherwise.
- */
-#if( configENABLE_MPU == 1 )
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
-#else /* configENABLE_MPU */
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
-#endif /* configENABLE_MPU */
-
-/**
- * @brief Frees the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the
- * context to be freed.
- */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Loads the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be loaded.
- */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Saves the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be saved.
- */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
-
-#endif /* __SECURE_CONTEXT_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c b/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
deleted file mode 100755
index 7c556f5..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_context_port.c
+++ /dev/null
@@ -1,88 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, load_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	ldmia r0!, {r1, r2}						\n" /* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r1!, {r3}							\n" /* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	"	msr control, r3							\n" /* CONTROL = r3. */
-	#endif /* configENABLE_MPU */
-	"	msr psplim, r2							\n" /* PSPLIM = r2. */
-	"	msr psp, r1								\n" /* PSP = r1. */
-	"											\n"
-	" load_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:::"r0", "r1", "r2"
-	);
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
-{
-	/* xSecureContextHandle value is in r0. */
-	__asm volatile
-	(
-	"	.syntax unified							\n"
-	"											\n"
-	"	mrs r1, ipsr							\n" /* r1 = IPSR. */
-	"	cbz r1, save_ctx_therad_mode			\n" /* Do nothing if the processor is running in the Thread Mode. */
-	"	mrs r1, psp								\n" /* r1 = PSP. */
-	#if( configENABLE_FPU == 1 )
-	"	vstmdb r1!, {s0}						\n" /* Trigger the defferred stacking of FPU registers. */
-	"	vldmia r1!, {s0}						\n" /* Nullify the effect of the pervious statement. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r2, control							\n" /* r2 = CONTROL. */
-	"	stmdb r1!, {r2}							\n" /* Store CONTROL value on the stack. */
-	#endif /* configENABLE_MPU */
-	"	str r1, [r0]							\n" /* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	"	movs r1, %0								\n" /* r1 = securecontextNO_STACK. */
-	"	msr psplim, r1							\n" /* PSPLIM = securecontextNO_STACK. */
-	"	msr psp, r1								\n" /* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-	"											\n"
-	" save_ctx_therad_mode:						\n"
-	"	nop										\n"
-	"											\n"
-	:: "i" ( securecontextNO_STACK ) : "r1", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c b/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
deleted file mode 100755
index 60fce5c..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure context heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Total heap size.
- */
-#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
-
-/* No test marker by default. */
-#ifndef mtCOVERAGE_TEST_MARKER
-	#define mtCOVERAGE_TEST_MARKER()
-#endif
-
-/* No tracing by default. */
-#ifndef traceMALLOC
-	#define traceMALLOC( pvReturn, xWantedSize )
-#endif
-
-/* No tracing by default. */
-#ifndef traceFREE
-	#define traceFREE( pv, xBlockSize )
-#endif
-
-/* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
-/*-----------------------------------------------------------*/
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	 * heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#else /* configAPPLICATION_ALLOCATED_HEAP */
-	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/**
- * @brief The linked list structure.
- *
- * This is used to link free blocks in order of their memory address.
- */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
-	size_t xBlockSize;						/**< The size of the free block. */
-} BlockLink_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Called automatically to setup the required heap structures the first
- * time pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/**
- * @brief Inserts a block of memory that is being freed into the correct
- * position in the list of free memory blocks.
- *
- * The block being freed will be merged with the block in front it and/or the
- * block behind it if the memory blocks are adjacent to each other.
- *
- * @param[in] pxBlockToInsert The block being freed.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The size of the structure placed at the beginning of each allocated
- * memory block must by correctly byte aligned.
- */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-
-/**
- * @brief Create a couple of list links to mark the start and end of the list.
- */
-static BlockLink_t xStart, *pxEnd = NULL;
-
-/**
- * @brief Keeps track of the number of free bytes remaining, but says nothing
- * about fragmentation.
- */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-size_t uxAddress;
-size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
-
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	uxAddress = ( size_t ) ucHeap;
-
-	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
-	{
-		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
-		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-	}
-
-	pucAlignedHeap = ( uint8_t * ) uxAddress;
-
-	/* xStart is used to hold a pointer to the first item in the list of free
-	 * blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
-
-	/* pxEnd is used to mark the end of the list of free blocks and is inserted
-	 * at the end of the heap space. */
-	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-	uxAddress -= xHeapStructSize;
-	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-	pxEnd = ( void * ) uxAddress;
-	pxEnd->xBlockSize = 0;
-	pxEnd->pxNextFreeBlock = NULL;
-
-	/* To start with there is a single free block that is sized to take up the
-	 * entire heap space, minus the space taken by pxEnd. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
-	/* Only one block exists - and it covers the entire usable heap space. */
-	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
-{
-BlockLink_t *pxIterator;
-uint8_t *puc;
-
-	/* Iterate through the list until a block is found that has a higher address
-	 * than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
-
-	/* Do the block being inserted, and the block it is being inserted after
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Do the block being inserted, and the block it is being inserted before
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
-
-	/* If the block being inserted plugged a gab, so was merged with the block
-	 * before and the block after, then it's pxNextFreeBlock pointer will have
-	 * already been set, and should not be set here as that would make it point
-	 * to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
-
-	/* If this is the first call to malloc then the heap will require
-	 * initialisation to setup the list of free blocks. */
-	if( pxEnd == NULL )
-	{
-		prvHeapInit();
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Check the requested block size is not so large that the top bit is set.
-	 * The top bit of the block size member of the BlockLink_t structure is used
-	 * to determine who owns the block - the application or the kernel, so it
-	 * must be free. */
-	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-	{
-		/* The wanted size is increased so it can contain a BlockLink_t
-		 * structure in addition to the requested amount of bytes. */
-		if( xWantedSize > 0 )
-		{
-			xWantedSize += xHeapStructSize;
-
-			/* Ensure that blocks are always aligned to the required number of
-			 * bytes. */
-			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
-			{
-				/* Byte alignment required. */
-				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-		{
-			/* Traverse the list from the start (lowest address) block until
-			 * one of adequate size is found. */
-			pxPreviousBlock = &xStart;
-			pxBlock = xStart.pxNextFreeBlock;
-			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-			{
-				pxPreviousBlock = pxBlock;
-				pxBlock = pxBlock->pxNextFreeBlock;
-			}
-
-			/* If the end marker was reached then a block of adequate size was
-			 * not found. */
-			if( pxBlock != pxEnd )
-			{
-				/* Return the memory space pointed to - jumping over the
-				 * BlockLink_t structure at its start. */
-				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-				/* This block is being returned for use so must be taken out
-				 * of the list of free blocks. */
-				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-				/* If the block is larger than required it can be split into
-				 * two. */
-				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
-				{
-					/* This block is to be split into two.  Create a new
-					 * block following the number of bytes requested. The void
-					 * cast is used to prevent byte alignment warnings from the
-					 * compiler. */
-					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-
-					/* Calculate the sizes of two blocks split from the single
-					 * block. */
-					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-					pxBlock->xBlockSize = xWantedSize;
-
-					/* Insert the new block into the list of free blocks. */
-					prvInsertBlockIntoFreeList( pxNewBlockLink );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-				{
-					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* The block is being returned - it is allocated and owned by
-				 * the application and has no "next" block. */
-				pxBlock->xBlockSize |= xBlockAllocatedBit;
-				pxBlock->pxNextFreeBlock = NULL;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	traceMALLOC( pvReturn, xWantedSize );
-
-	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
-
-	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		 * before it. */
-		puc -= xHeapStructSize;
-
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
-
-		/* Check the block is actually allocated. */
-		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
-
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				 * allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-				secureportDISABLE_NON_SECURE_INTERRUPTS();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				secureportENABLE_NON_SECURE_INTERRUPTS();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h b/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
deleted file mode 100755
index 69e4f2a..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_heap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_HEAP_H__
-#define __SECURE_HEAP_H__
-
-/* Standard includes. */
-#include 
-
-/**
- * @brief Allocates memory from heap.
- *
- * @param[in] xWantedSize The size of the memory to be allocated.
- *
- * @return Pointer to the memory region if the allocation is successful, NULL
- * otherwise.
- */
-void *pvPortMalloc( size_t xWantedSize );
-
-/**
- * @brief Frees the previously allocated memory.
- *
- * @param[in] pv Pointer to the memory to be freed.
- */
-void vPortFree( void *pv );
-
-#endif /* __SECURE_HEAP_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c b/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c
deleted file mode 100755
index c6525f7..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure init includes. */
-#include "secure_init.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS			( 29UL )
-#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS				( 26UL )
-#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
-
-#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS			( 10UL )
-#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS			( 11UL )
-#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
-									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
-									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
-		 * permitted. CP11 should be programmed to the same value as CP10. */
-		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
-
-		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
-		 * that we can enable/disable lazy stacking in port.c file. */
-		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
-
-		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
-		 * registers (S16-S31) are also pushed to stack on exception entry and
-		 * restored on exception return. */
-		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h b/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h
deleted file mode 100755
index 6c5bc71..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_init.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_INIT_H__
-#define __SECURE_INIT_H__
-
-/**
- * @brief De-prioritizes the non-secure exceptions.
- *
- * This is needed to ensure that the non-secure PendSV runs at the lowest
- * priority. Context switch is done in the non-secure PendSV handler.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_DePrioritizeNSExceptions( void );
-
-/**
- * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
- *
- * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
- * Registers are not leaked to the non-secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_EnableNSFPUAccess( void );
-
-#endif /* __SECURE_INIT_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h b/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
deleted file mode 100755
index 760edab..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33/secure/secure_port_macros.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_PORT_MACROS_H__
-#define __SECURE_PORT_MACROS_H__
-
-/**
- * @brief Byte alignment requirements.
- */
-#define secureportBYTE_ALIGNMENT					8
-#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
-
-/**
- * @brief Macro to declare a function as non-secure callable.
- */
-#if defined( __IAR_SYSTEMS_ICC__ )
-	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
-#else
-	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
-#endif
-
-/**
- * @brief Set the secure PRIMASK value.
- */
-#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Set the non-secure PRIMASK value.
- */
-#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Read the PSP value in the given variable.
- */
-#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
-	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
-
-/**
- * @brief Set the PSP to the given value.
- */
-#define secureportSET_PSP( pucCurrentStackPointer ) \
-	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
-
-/**
- * @brief Set the PSPLIM to the given value.
- */
-#define secureportSET_PSPLIM( pucStackLimit ) \
-	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
-
-/**
- * @brief Set the NonSecure MSP to the given value.
- */
-#define secureportSET_MSP_NS( pucMainStackPointer ) \
-	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
-
-/**
- * @brief Set the CONTROL register to the given value.
- */
-#define secureportSET_CONTROL( ulControl ) \
-	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
-
-/**
- * @brief Read the Interrupt Program Status Register (IPSR) value in the given
- * variable.
- */
-#define secureportREAD_IPSR( ulIPSR ) \
-	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
-
-/**
- * @brief PRIMASK value to enable interrupts.
- */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
-
-/**
- * @brief PRIMASK value to disable interrupts.
- */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
-
-/**
- * @brief Disable secure interrupts.
- */
-#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Disable non-secure interrupts.
- *
- * This effectively disables context switches.
- */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Enable non-secure interrupts.
- */
-#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Assert definition.
- */
-#define secureportASSERT( x )						\
-	if( ( x ) == 0 )								\
-	{												\
-		secureportDISABLE_SECURE_INTERRUPTS();		\
-		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
-		for( ;; );									\
-	}
-
-#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
deleted file mode 100755
index bd85a6f..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c b/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
deleted file mode 100755
index ba4a69c..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE ensures that PRIVILEGED_FUNCTION
- * is defined correctly and privileged functions are placed in correct sections. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Portasm includes. */
-#include "portasm.h"
-
-/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE is needed to be defined only for the
- * header files. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-void vRestoreContextOfFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	ldr  r2, pxCurrentTCBConst2						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr  r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr  r0, [r1]									\n" /* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr  r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
-	"	ldr  r2, xMAIR0Const2							\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str  r3, [r2]									\n" /* Program MAIR0. */
-	"	ldr  r2, xRNRConst2								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r3, #4										\n" /* r3 = 4. */
-	"	str  r3, [r2]									\n" /* Program RNR = 4. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	ldr  r2, xRBARConst2							\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r1!, {r4-r11}								\n" /* Read 4 set of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst2							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldm  r0!, {r1-r3}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	msr  control, r2								\n" /* Set this task's CONTROL value. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r3											\n" /* Finally, branch to EXC_RETURN. */
-	#else /* configENABLE_MPU */
-	"	ldm  r0!, {r1-r2}								\n" /* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	"	msr  psplim, r1									\n" /* Set this task's PSPLIM value. */
-	"	movs r1, #2										\n" /* r1 = 2. */
-	"	msr  CONTROL, r1								\n" /* Switch to use PSP in the thread mode. */
-	"	adds r0, #32									\n" /* Discard everything up to r0. */
-	"	msr  psp, r0									\n" /* This is now the new top of stack to use in the task. */
-	"	isb												\n"
-	"	bx   r2											\n" /* Finally, branch to EXC_RETURN. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst2: .word 0xe000ed94					\n"
-	"xMAIR0Const2: .word 0xe000edc0						\n"
-	"xRNRConst2: .word 0xe000ed98						\n"
-	"xRBARConst2: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	tst r0, #1										\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne											\n"
-	"	movne r0, #0									\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1									\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr											\n" /* Return. */
-	"													\n"
-	"	.align 4										\n"
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vRaisePrivilege( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	 __asm volatile
-	(
-	"	mrs  r0, control								\n" /* Read the CONTROL register. */
-	"	bic r0, #1										\n" /* Clear the bit 0. */
-	"	msr  control, r0								\n" /* Write back the new CONTROL value. */
-	"	bx lr											\n" /* Return to the caller. */
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control									\n" /* r0 = CONTROL. */
-	"	orr r0, #1										\n" /* r0 = r0 | 1. */
-	"	msr control, r0									\n" /* CONTROL = r0. */
-	"	bx lr											\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vStartFirstTask( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	ldr r0, xVTORConst								\n" /* Use the NVIC offset register to locate the stack. */
-	"	ldr r0, [r0]									\n" /* Read the VTOR register which gives the address of vector table. */
-	"	ldr r0, [r0]									\n" /* The first entry in vector table is stack pointer. */
-	"	msr msp, r0										\n" /* Set the MSP back to the start of the stack. */
-	"	cpsie i											\n" /* Globally enable interrupts. */
-	"	cpsie f											\n"
-	"	dsb												\n"
-	"	isb												\n"
-	"	svc %0											\n" /* System call to start the first task. */
-	"	nop												\n"
-	"													\n"
-	"   .align 4										\n"
-	"xVTORConst: .word 0xe000ed08						\n"
-	:: "i" ( portSVC_START_SCHEDULER ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	mrs r0, PRIMASK									\n"
-	"	cpsid i											\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* To avoid compiler warnings.  The return statement will never be reached,
-	 * but some compilers warn if it is not included, while others won't compile
-	 * if it is. */
-	return 0;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void vClearInterruptMaskFromISR( __attribute__( ( unused ) ) uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	msr PRIMASK, r0									\n"
-	"	bx lr											\n"
-	::: "memory"
-	);
-
-#if !defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
-	/* Just to avoid compiler warning.  ulMask is used from the asm code but
-	 * the compiler can't see that.  Some compilers generate warnings without
-	 * the following line, while others generate warnings if the line is
-	 * included. */
-	( void ) ulMask;
-#endif
-}
-/*-----------------------------------------------------------*/
-
-void PendSV_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	.syntax unified									\n"
-	"													\n"
-	"	mrs r0, psp										\n" /* Read PSP in r0. */
-	#if( configENABLE_FPU == 1 )
-	"	tst lr, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vstmdbeq r0!, {s16-s31}							\n" /* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if( configENABLE_MPU == 1 )
-	"	mrs r1, psplim									\n" /* r1 = PSPLIM. */
-	"	mrs r2, control									\n" /* r2 = CONTROL. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmdb r0!, {r1-r11}								\n" /* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
-	#else /* configENABLE_MPU */
-	"	mrs r2, psplim									\n" /* r2 = PSPLIM. */
-	"	mov r3, lr										\n" /* r3 = LR/EXC_RETURN. */
-	"	stmdb r0!, {r2-r11}								\n" /* Store on the stack - PSPLIM, LR and registers that are not automatically saved. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	str r0, [r1]									\n" /* Save the new top of stack in TCB. */
-	"													\n"
-	"	cpsid i											\n"
-	"	bl vTaskSwitchContext							\n"
-	"	cpsie i											\n"
-	"													\n"
-	"	ldr r2, pxCurrentTCBConst						\n" /* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	"	ldr r1, [r2]									\n" /* Read pxCurrentTCB. */
-	"	ldr r0, [r1]									\n" /* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	dmb												\n" /* Complete outstanding transfers before disabling MPU. */
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	bic r4, #1										\n" /* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Disable MPU. */
-	"													\n"
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	"	ldr r3, [r1]									\n" /* r3 = *r1 i.e. r3 = MAIR0. */
-	"	ldr r2, xMAIR0Const								\n" /* r2 = 0xe000edc0 [Location of MAIR0]. */
-	"	str r3, [r2]									\n" /* Program MAIR0. */
-	"	ldr r2, xRNRConst								\n" /* r2 = 0xe000ed98 [Location of RNR]. */
-	"	movs r3, #4										\n" /* r3 = 4. */
-	"	str r3, [r2]									\n" /* Program RNR = 4. */
-	"	adds r1, #4										\n" /* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	"	ldr r2, xRBARConst								\n" /* r2 = 0xe000ed9c [Location of RBAR]. */
-	"	ldmia r1!, {r4-r11}								\n" /* Read 4 sets of RBAR/RLAR registers from TCB. */
-	"	stmia r2!, {r4-r11}								\n" /* Write 4 set of RBAR/RLAR registers using alias registers. */
-	"													\n"
-	"	ldr r2, xMPUCTRLConst							\n" /* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	"	ldr r4, [r2]									\n" /* Read the value of MPU_CTRL. */
-	"	orr r4, #1										\n" /* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	"	str r4, [r2]									\n" /* Enable MPU. */
-	"	dsb												\n" /* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	ldmia r0!, {r1-r11}								\n" /* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
-	#else /* configENABLE_MPU */
-	"	ldmia r0!, {r2-r11}								\n" /* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-	#endif /* configENABLE_MPU */
-	"													\n"
-	#if( configENABLE_FPU == 1 )
-	"	tst r3, #0x10									\n" /* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	"	it eq											\n"
-	"	vldmiaeq r0!, {s16-s31}							\n" /* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-	"													\n"
-	#if( configENABLE_MPU == 1 )
-	"	msr psplim, r1									\n" /* Restore the PSPLIM register value for the task. */
-	"	msr control, r2									\n" /* Restore the CONTROL register value for the task. */
-	#else /* configENABLE_MPU */
-	"	msr psplim, r2									\n" /* Restore the PSPLIM register value for the task. */
-	#endif /* configENABLE_MPU */
-	"	msr psp, r0										\n" /* Remember the new top of stack for the task. */
-	"	bx r3											\n"
-	"													\n"
-	"	.align 4										\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB				\n"
-	#if( configENABLE_MPU == 1 )
-	"xMPUCTRLConst: .word 0xe000ed94					\n"
-	"xMAIR0Const: .word 0xe000edc0						\n"
-	"xRNRConst: .word 0xe000ed98						\n"
-	"xRBARConst: .word 0xe000ed9c						\n"
-	#endif /* configENABLE_MPU */
-	);
-}
-/*-----------------------------------------------------------*/
-
-void SVC_Handler( void ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */
-{
-	__asm volatile
-	(
-	"	tst lr, #4										\n"
-	"	ite eq											\n"
-	"	mrseq r0, msp									\n"
-	"	mrsne r0, psp									\n"
-	"	ldr r1, svchandler_address_const				\n"
-	"	bx r1											\n"
-	"													\n"
-	"	.align 4										\n"
-	"svchandler_address_const: .word vPortSVCHandler_C	\n"
-	);
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h b/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
deleted file mode 100755
index 2ecf04e..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
deleted file mode 100755
index d051ddc..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM33_NTZ/non_secure/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__attribute__(( used ))
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
deleted file mode 100755
index 454f90f..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/port.c
+++ /dev/null
@@ -1,797 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM3 port.
- *----------------------------------------------------------*/
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK	( 0 )
-#endif
-
-/* Constants required to access and manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL_REG				( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG				( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG		( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG					( *	( ( volatile uint32_t * ) 0xe000ed20 ) )
-#define portNVIC_SYSPRI1_REG					( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
-#define portNVIC_SYS_CTRL_STATE_REG				( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
-#define portNVIC_MEM_FAULT_ENABLE				( 1UL << 16UL )
-
-/* Constants required to access and manipulate the MPU. */
-#define portMPU_TYPE_REG						( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_REGION_BASE_ADDRESS_REG			( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
-#define portMPU_REGION_ATTRIBUTE_REG			( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
-#define portMPU_CTRL_REG						( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portEXPECTED_MPU_TYPE_VALUE				( 8UL << 8UL ) /* 8 regions, unified. */
-#define portMPU_ENABLE							( 0x01UL )
-#define portMPU_BACKGROUND_ENABLE				( 1UL << 2UL )
-#define portPRIVILEGED_EXECUTION_START_ADDRESS	( 0UL )
-#define portMPU_REGION_VALID					( 0x10UL )
-#define portMPU_REGION_ENABLE					( 0x01UL )
-#define portPERIPHERALS_START_ADDRESS			0x40000000UL
-#define portPERIPHERALS_END_ADDRESS				0x5FFFFFFFUL
-
-/* Constants required to access and manipulate the SysTick. */
-#define portNVIC_SYSTICK_INT					( 0x00000002UL )
-#define portNVIC_SYSTICK_ENABLE					( 0x00000001UL )
-#define portNVIC_PENDSV_PRI						( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI						( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR						( 0x01000000 )
-#define portINITIAL_CONTROL_IF_UNPRIVILEGED		( 0x03 )
-#define portINITIAL_CONTROL_IF_PRIVILEGED		( 0x02 )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Offsets in the stack to the parameters when inside the SVC handler. */
-#define portOFFSET_TO_PC						( 6 )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
-
-/*
- * Configure a number of standard MPU regions that are used by all tasks.
- */
-static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Return the smallest MPU region size that a given number of bytes will fit
- * into.  The region size is returned as the value that should be programmed
- * into the region attribute register for that region.
- */
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Standard FreeRTOS exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;
-void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/*
- * Starts the scheduler by restoring the context of the first task to run.
- */
-static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/*
- * C portion of the SVC handler.  The SVC handler is split between an asm entry
- * and a C wrapper for simplicity of coding and maintenance.
- */
-static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Calls the port specific code to raise the privilege.
- *
- * @return pdFALSE if privilege was raised, pdTRUE otherwise.
- */
-extern BaseType_t xPortRaisePrivilege( void );
-
-/**
- * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
- * code to reset the privilege, otherwise does nothing.
- */
-extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable.  Note this is not saved as part of the task context as context
-switches can only occur when uxCriticalNesting is zero. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = 0;	/* LR */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-	pxTopOfStack -= 9;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	if( xRunPrivileged == pdTRUE )
-	{
-		*pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
-	}
-	else
-	{
-		*pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
-	}
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
-	/* Assumes psp was in use. */
-	__asm volatile
-	(
-		#ifndef USE_PROCESS_STACK	/* Code should not be required if a main() is using the process stack. */
-			"	tst lr, #4						\n"
-			"	ite eq							\n"
-			"	mrseq r0, msp					\n"
-			"	mrsne r0, psp					\n"
-		#else
-			"	mrs r0, psp						\n"
-		#endif
-			"	b %0							\n"
-			::"i"(prvSVCHandler):"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-static void prvSVCHandler(	uint32_t *pulParam )
-{
-uint8_t ucSVCNumber;
-
-	/* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
-	xPSR.  The first argument (r0) is pulParam[ 0 ]. */
-	ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
-	switch( ucSVCNumber )
-	{
-		case portSVC_START_SCHEDULER	:	portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
-											prvRestoreContextOfFirstTask();
-											break;
-
-		case portSVC_YIELD				:	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-											/* Barriers are normally not required
-											but do ensure the code is completely
-											within the specified behaviour for the
-											architecture. */
-											__asm volatile( "dsb" ::: "memory" );
-											__asm volatile( "isb" );
-
-											break;
-
-		case portSVC_RAISE_PRIVILEGE	:	__asm volatile
-											(
-												"	mrs r1, control		\n" /* Obtain current control value. */
-												"	bic r1, #1			\n" /* Set privilege bit. */
-												"	msr control, r1		\n" /* Write back new control value. */
-												::: "r1", "memory"
-											);
-											break;
-
-		default							:	/* Unknown SVC call. */
-											break;
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvRestoreContextOfFirstTask( void )
-{
-	__asm volatile
-	(
-		"	ldr r0, =0xE000ED08				\n" /* Use the NVIC offset register to locate the stack. */
-		"	ldr r0, [r0]					\n"
-		"	ldr r0, [r0]					\n"
-		"	msr msp, r0						\n" /* Set the msp back to the start of the stack. */
-		"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
-		"	ldr r1, [r3]					\n"
-		"	ldr r0, [r1]					\n" /* The first item in the TCB is the task top of stack. */
-		"	add r1, r1, #4					\n" /* Move onto the second item in the TCB... */
-		"	ldr r2, =0xe000ed9c				\n" /* Region Base Address register. */
-		"	ldmia r1!, {r4-r11}				\n" /* Read 4 sets of MPU registers. */
-		"	stmia r2!, {r4-r11}				\n" /* Write 4 sets of MPU registers. */
-		"	ldmia r0!, {r3, r4-r11}			\n" /* Pop the registers that are not automatically saved on exception entry. */
-		"	msr control, r3					\n"
-		"	msr psp, r0						\n" /* Restore the task stack pointer. */
-		"	mov r0, #0						\n"
-		"	msr	basepri, r0					\n"
-		"	ldr r14, =0xfffffffd			\n" /* Load exec return code. */
-		"	bx r14							\n"
-		"									\n"
-		"	.align 4						\n"
-		"pxCurrentTCBConst2: .word pxCurrentTCB	\n"
-	);
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See
-	http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-	configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the same priority as the kernel, and the SVC
-	handler higher priority so it can be used to exit a critical section (where
-	lower priorities are masked). */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Configure the regions in the MPU that are common to all tasks. */
-	prvSetupMPU();
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Start the first task. */
-	__asm volatile(
-					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
-					" ldr r0, [r0] 			\n"
-					" ldr r0, [r0] 			\n"
-					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
-					" cpsie i				\n" /* Globally enable interrupts. */
-					" cpsie f				\n"
-					" dsb					\n"
-					" isb					\n"
-					" svc %0				\n" /* System call to start first task. */
-					" nop					\n"
-					:: "i" (portSVC_START_SCHEDULER) : "memory" );
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
-	/* This is a naked function. */
-
-	__asm volatile
-	(
-		"	mrs r0, psp							\n"
-		"										\n"
-		"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
-		"	ldr	r2, [r3]						\n"
-		"										\n"
-		"	mrs r1, control						\n"
-		"	stmdb r0!, {r1, r4-r11}				\n" /* Save the remaining registers. */
-		"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
-		"										\n"
-		"	stmdb sp!, {r3, r14}				\n"
-		"	mov r0, %0							\n"
-		"	msr basepri, r0						\n"
-		"	dsb									\n"
-		"	isb									\n"
-		"	bl vTaskSwitchContext				\n"
-		"	mov r0, #0							\n"
-		"	msr basepri, r0						\n"
-		"	ldmia sp!, {r3, r14}				\n"
-		"										\n"	/* Restore the context. */
-		"	ldr r1, [r3]						\n"
-		"	ldr r0, [r1]						\n" /* The first item in the TCB is the task top of stack. */
-		"	add r1, r1, #4						\n" /* Move onto the second item in the TCB... */
-		"	ldr r2, =0xe000ed9c					\n" /* Region Base Address register. */
-		"	ldmia r1!, {r4-r11}					\n" /* Read 4 sets of MPU registers. */
-		"	stmia r2!, {r4-r11}					\n" /* Write 4 sets of MPU registers. */
-		"	ldmia r0!, {r3, r4-r11}				\n" /* Pop the registers that are not automatically saved on exception entry. */
-		"	msr control, r3						\n"
-		"										\n"
-		"	msr psp, r0							\n"
-		"	bx r14								\n"
-		"										\n"
-		"	.align 4							\n"
-		"pxCurrentTCBConst: .word pxCurrentTCB	\n"
-		::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
-	);
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-uint32_t ulDummy;
-
-	ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
-{
-	/* Stop and clear the SysTick. */
-	portNVIC_SYSTICK_CTRL_REG = 0UL;
-	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupMPU( void )
-{
-extern uint32_t __privileged_functions_end__[];
-extern uint32_t __FLASH_segment_start__[];
-extern uint32_t __FLASH_segment_end__[];
-extern uint32_t __privileged_data_start__[];
-extern uint32_t __privileged_data_end__[];
-
-	/* Check the expected MPU is present. */
-	if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-	{
-		/* First setup the entire flash for unprivileged read only access. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
-											( portMPU_REGION_VALID ) |
-											( portUNPRIVILEGED_FLASH_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_ONLY ) |
-										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-										( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
-										( portMPU_REGION_ENABLE );
-
-		/* Setup the first 16K for privileged only access (even though less
-		than 10K is actually being used).  This is where the kernel code is
-		placed. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
-											( portMPU_REGION_VALID ) |
-											( portPRIVILEGED_FLASH_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
-										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-										( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
-										( portMPU_REGION_ENABLE );
-
-		/* Setup the privileged data RAM region.  This is where the kernel data
-		is placed. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
-											( portMPU_REGION_VALID ) |
-											( portPRIVILEGED_RAM_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-										prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
-										( portMPU_REGION_ENABLE );
-
-		/* By default allow everything to access the general peripherals.  The
-		system peripherals and registers are protected. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( portPERIPHERALS_START_ADDRESS ) |
-											( portMPU_REGION_VALID ) |
-											( portGENERAL_PERIPHERALS_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
-										( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
-										( portMPU_REGION_ENABLE );
-
-		/* Enable the memory fault exception. */
-		portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
-
-		/* Enable the MPU with the background region configured. */
-		portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
-	}
-}
-/*-----------------------------------------------------------*/
-
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
-{
-uint32_t ulRegionSize, ulReturnValue = 4;
-
-	/* 32 is the smallest region size, 31 is the largest valid value for
-	ulReturnValue. */
-	for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
-	{
-		if( ulActualSizeInBytes <= ulRegionSize )
-		{
-			break;
-		}
-		else
-		{
-			ulReturnValue++;
-		}
-	}
-
-	/* Shift the code by one before returning so it can be written directly
-	into the the correct bit position of the attribute register. */
-	return ( ulReturnValue << 1UL );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control							\n" /* r0 = CONTROL. */
-	"	tst r0, #1								\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne									\n"
-	"	movne r0, #0							\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1							\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr									\n" /* Return. */
-	"											\n"
-	"	.align 4								\n"
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control							\n" /* r0 = CONTROL. */
-	"	orr r0, #1								\n" /* r0 = r0 | 1. */
-	"	msr control, r0							\n" /* CONTROL = r0. */
-	"	bx lr									\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-{
-extern uint32_t __SRAM_segment_start__[];
-extern uint32_t __SRAM_segment_end__[];
-extern uint32_t __privileged_data_start__[];
-extern uint32_t __privileged_data_end__[];
-int32_t lIndex;
-uint32_t ul;
-
-	if( xRegions == NULL )
-	{
-		/* No MPU regions are specified so allow access to all RAM. */
-		xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
-				( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
-				( portMPU_REGION_VALID ) |
-				( portSTACK_REGION );
-
-		xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
-				( portMPU_REGION_READ_WRITE ) |
-				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-				( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
-				( portMPU_REGION_ENABLE );
-
-		/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
-		just removed the privileged only parameters. */
-		xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
-				( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
-				( portMPU_REGION_VALID ) |
-				( portSTACK_REGION + 1 );
-
-		xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
-				( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-				prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
-				( portMPU_REGION_ENABLE );
-
-		/* Invalidate all other regions. */
-		for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
-		{
-			xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
-			xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
-		}
-	}
-	else
-	{
-		/* This function is called automatically when the task is created - in
-		which case the stack region parameters will be valid.  At all other
-		times the stack parameters will not be valid and it is assumed that the
-		stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
-					( ( uint32_t ) pxBottomOfStack ) |
-					( portMPU_REGION_VALID ) |
-					( portSTACK_REGION ); /* Region number. */
-
-			xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
-					( portMPU_REGION_READ_WRITE ) | /* Read and write. */
-					( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
-					( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-					( portMPU_REGION_ENABLE );
-		}
-
-		lIndex = 0;
-
-		for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
-		{
-			if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
-			{
-				/* Translate the generic region definition contained in
-				xRegions into the CM3 specific MPU settings that are then
-				stored in xMPUSettings. */
-				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
-						( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
-						( portMPU_REGION_VALID ) |
-						( portSTACK_REGION + ul ); /* Region number. */
-
-				xMPUSettings->xRegion[ ul ].ulRegionAttribute =
-						( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
-						( xRegions[ lIndex ].ulParameters ) |
-						( portMPU_REGION_ENABLE );
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
-				xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		/* Obtain the number of the currently executing interrupt. */
-		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredicable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
deleted file mode 100755
index 3458b0e..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM3_MPU/portmacro.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* MPU specific constants. */
-#define portUSING_MPU_WRAPPERS		1
-#define portPRIVILEGE_BIT			( 0x80000000UL )
-
-#define portMPU_REGION_READ_WRITE				( 0x03UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY		( 0x05UL << 24UL )
-#define portMPU_REGION_READ_ONLY				( 0x06UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_WRITE	( 0x01UL << 24UL )
-#define portMPU_REGION_CACHEABLE_BUFFERABLE		( 0x07UL << 16UL )
-#define portMPU_REGION_EXECUTE_NEVER			( 0x01UL << 28UL )
-
-#define portUNPRIVILEGED_FLASH_REGION		( 0UL )
-#define portPRIVILEGED_FLASH_REGION			( 1UL )
-#define portPRIVILEGED_RAM_REGION			( 2UL )
-#define portGENERAL_PERIPHERALS_REGION		( 3UL )
-#define portSTACK_REGION					( 4UL )
-#define portFIRST_CONFIGURABLE_REGION	    ( 5UL )
-#define portLAST_CONFIGURABLE_REGION		( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS		( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS				( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
-
-typedef struct MPU_REGION_REGISTERS
-{
-	uint32_t ulRegionBaseAddress;
-	uint32_t ulRegionAttribute;
-} xMPU_REGION_REGISTERS;
-
-/* Plus 1 to create space for the stack region. */
-typedef struct MPU_SETTINGS
-{
-	xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
-} xMPU_SETTINGS;
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-/* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER				0
-#define portSVC_YIELD						1
-#define portSVC_RAISE_PRIVILEGE				2
-
-/* Scheduler utilities. */
-
-#define portYIELD()				__asm volatile ( "	SVC	%0	\n" :: "i" (portSVC_YIELD) : "memory" )
-#define portYIELD_WITHIN_API() 													\
-{																				\
-	/* Set a PendSV to request a context switch. */								\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
-																				\
-	/* Barriers are normally not required but do ensure the code is completely	\
-	within the specified behaviour for the architecture. */						\
-	__asm volatile( "dsb" ::: "memory" );										\
-	__asm volatile( "isb" );													\
-}
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
-#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
-#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Generic helper function. */
-	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-	{
-	uint8_t ucReturn;
-
-		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
-		return ucReturn;
-	}
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-#define portINLINE	__inline
-
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE inline __attribute__(( always_inline))
-#endif
-/*-----------------------------------------------------------*/
-
-extern BaseType_t xIsPrivileged( void );
-extern void vResetPrivilege( void );
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-#define portIS_PRIVILEGED()			xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
-*/
-#define portRAISE_PRIVILEGE()		__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
-#define portRESET_PRIVILEGE()		vResetPrivilege()
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
-{
-uint32_t ulCurrentInterrupt;
-BaseType_t xReturn;
-
-	/* Obtain the number of the currently executing interrupt. */
-	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-	if( ulCurrentInterrupt == 0 )
-	{
-		xReturn = pdFALSE;
-	}
-	else
-	{
-		xReturn = pdTRUE;
-	}
-
-	return xReturn;
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortRaiseBASEPRI( void )
-{
-uint32_t ulNewBASEPRI;
-
-	__asm volatile
-	(
-		"	mov %0, %1												\n"	\
-		"	msr basepri, %0											\n" \
-		"	isb														\n" \
-		"	dsb														\n" \
-		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
-{
-uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
-
-	__asm volatile
-	(
-		"	mrs %0, basepri											\n" \
-		"	mov %1, %2												\n"	\
-		"	msr basepri, %1											\n" \
-		"	isb														\n" \
-		"	dsb														\n" \
-		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
-
-	/* This return will not be reached but is necessary to prevent compiler
-	warnings. */
-	return ulOriginalBASEPRI;
-}
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
-{
-	__asm volatile
-	(
-		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
deleted file mode 100755
index 720058f..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM4F/port.c
+++ /dev/null
@@ -1,775 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __VFP_FP__
-	#error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
-
-/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
-r0p1 port. */
-#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
-#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
-#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )
-
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR					( 0x01000000 )
-#define portINITIAL_EXC_RETURN				( 0xfffffffd )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR			( 45UL )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__ (( naked ));
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void ) __attribute__ (( naked ));
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
-
-/*
- * Function to enable the VFP.
- */
-static void vPortEnableVFP( void ) __attribute__ (( naked ));
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-
-	/* Offset added to account for the way the MCU uses the stack on entry/exit
-	of interrupts, and to ensure alignment. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-
-	/* Save code space by skipping register initialisation. */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-
-	/* A save method is being used that requires each task to maintain its
-	own exec return value. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0;
-
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		started to remove a compiler warning about the function being defined
-		but never called.  ulDummy is used purely to quieten other warnings
-		about code appearing after this function is called - making ulDummy
-		volatile makes the compiler think the function could return and
-		therefore not output an 'unreachable code' warning for code that appears
-		after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
-	__asm volatile (
-					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
-					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
-					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
-					"	ldmia r0!, {r4-r11, r14}		\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
-					"	msr psp, r0						\n" /* Restore the task stack pointer. */
-					"	isb								\n"
-					"	mov r0, #0 						\n"
-					"	msr	basepri, r0					\n"
-					"	bx r14							\n"
-					"									\n"
-					"	.align 4						\n"
-					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-				);
-}
-/*-----------------------------------------------------------*/
-
-static void prvPortStartFirstTask( void )
-{
-	/* Start the first task.  This also clears the bit that indicates the FPU is
-	in use in case the FPU was used before the scheduler was started - which
-	would otherwise result in the unnecessary leaving of space in the SVC stack
-	for lazy saving of FPU registers. */
-	__asm volatile(
-					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
-					" ldr r0, [r0] 			\n"
-					" ldr r0, [r0] 			\n"
-					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
-					" mov r0, #0			\n" /* Clear the bit that indicates the FPU is in use, see comment above. */
-					" msr control, r0		\n"
-					" cpsie i				\n" /* Globally enable interrupts. */
-					" cpsie f				\n"
-					" dsb					\n"
-					" isb					\n"
-					" svc 0					\n" /* System call to start first task. */
-					" nop					\n"
-				);
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
-	/* This port can be used on all revisions of the Cortex-M7 core other than
-	the r0p1 parts.  r0p1 parts should use the port from the
-	/source/portable/GCC/ARM_CM7/r0p1 directory. */
-	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
-	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Ensure the VFP is enabled - it should be anyway. */
-	vPortEnableVFP();
-
-	/* Lazy save always. */
-	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
-	/* Start the first task. */
-	prvPortStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing!  Call the task
-	exit error function to prevent compiler warnings about a static function
-	not being called in the case that the application writer overrides this
-	functionality by defining configTASK_RETURN_ADDRESS.  Call
-	vTaskSwitchContext() so link time optimisation does not remove the
-	symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
-	/* This is a naked function. */
-
-	__asm volatile
-	(
-	"	mrs r0, psp							\n"
-	"	isb									\n"
-	"										\n"
-	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
-	"	ldr	r2, [r3]						\n"
-	"										\n"
-	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, push high vfp registers. */
-	"	it eq								\n"
-	"	vstmdbeq r0!, {s16-s31}				\n"
-	"										\n"
-	"	stmdb r0!, {r4-r11, r14}			\n" /* Save the core registers. */
-	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
-	"										\n"
-	"	stmdb sp!, {r0, r3}					\n"
-	"	mov r0, %0 							\n"
-	"	msr basepri, r0						\n"
-	"	dsb									\n"
-	"	isb									\n"
-	"	bl vTaskSwitchContext				\n"
-	"	mov r0, #0							\n"
-	"	msr basepri, r0						\n"
-	"	ldmia sp!, {r0, r3}					\n"
-	"										\n"
-	"	ldr r1, [r3]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
-	"	ldr r0, [r1]						\n"
-	"										\n"
-	"	ldmia r0!, {r4-r11, r14}			\n" /* Pop the core registers. */
-	"										\n"
-	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
-	"	it eq								\n"
-	"	vldmiaeq r0!, {s16-s31}				\n"
-	"										\n"
-	"	msr psp, r0							\n"
-	"	isb									\n"
-	"										\n"
-	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
-		#if WORKAROUND_PMU_CM001 == 1
-	"			push { r14 }				\n"
-	"			pop { pc }					\n"
-		#endif
-	#endif
-	"										\n"
-	"	bx r14								\n"
-	"										\n"
-	"	.align 4							\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
-	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
-	);
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known. */
-	portDISABLE_INTERRUPTS();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TICKLESS_IDLE == 1 )
-
-	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-	TickType_t xModifiableIdleTime;
-
-		/* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
-		is accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-		/* Calculate the reload value required to wait xExpectedIdleTime
-		tick periods.  -1 is used because this code will execute part way
-		through one of the tick periods. */
-		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-		if( ulReloadValue > ulStoppedTimerCompensation )
-		{
-			ulReloadValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Enter a critical section but don't use the taskENTER_CRITICAL()
-		method as that will mask interrupts that should exit sleep mode. */
-		__asm volatile( "cpsid i" ::: "memory" );
-		__asm volatile( "dsb" );
-		__asm volatile( "isb" );
-
-		/* If a context switch is pending or a task is waiting for the scheduler
-		to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-		{
-			/* Restart from whatever is left in the count register to complete
-			this tick period. */
-			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Reset the reload register to the value required for normal tick
-			periods. */
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Re-enable interrupts - see comments above the cpsid instruction()
-			above. */
-			__asm volatile( "cpsie i" ::: "memory" );
-		}
-		else
-		{
-			/* Set the new reload value. */
-			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-			/* Clear the SysTick count flag and set the count value back to
-			zero. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-			set its parameter to 0 to indicate that its implementation contains
-			its own wait for interrupt or wait for event instruction, and so wfi
-			should not be executed again.  However, the original expected idle
-			time variable must remain unmodified, so a copy is taken. */
-			xModifiableIdleTime = xExpectedIdleTime;
-			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-			if( xModifiableIdleTime > 0 )
-			{
-				__asm volatile( "dsb" ::: "memory" );
-				__asm volatile( "wfi" );
-				__asm volatile( "isb" );
-			}
-			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-			/* Re-enable interrupts to allow the interrupt that brought the MCU
-			out of sleep mode to execute immediately.  see comments above
-			__disable_interrupt() call above. */
-			__asm volatile( "cpsie i" ::: "memory" );
-			__asm volatile( "dsb" );
-			__asm volatile( "isb" );
-
-			/* Disable interrupts again because the clock is about to be stopped
-			and interrupts that execute while the clock is stopped will increase
-			any slippage between the time maintained by the RTOS and calendar
-			time. */
-			__asm volatile( "cpsid i" ::: "memory" );
-			__asm volatile( "dsb" );
-			__asm volatile( "isb" );
-
-			/* Disable the SysTick clock without reading the
-			portNVIC_SYSTICK_CTRL_REG register to ensure the
-			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
-			the time the SysTick is stopped for is accounted for as best it can
-			be, but using the tickless mode will inevitably result in some tiny
-			drift of the time maintained by the kernel with respect to calendar
-			time*/
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-			/* Determine if the SysTick clock has already counted to zero and
-			been set back to the current reload value (the reload back being
-			correct for the entire expected idle time) or if the SysTick is yet
-			to count to zero (in which case an interrupt other than the SysTick
-			must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-			{
-				uint32_t ulCalculatedLoadValue;
-
-				/* The tick interrupt is already pending, and the SysTick count
-				reloaded with ulReloadValue.  Reset the
-				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-				period. */
-				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-				/* Don't allow a tiny value, or values that have somehow
-				underflowed because the post sleep hook did something
-				that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-				{
-					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-				}
-
-				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-				/* As the pending tick will be processed as soon as this
-				function exits, the tick value maintained by the tick is stepped
-				forward by one less than the time spent waiting. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				Work out how long the sleep lasted rounded to complete tick
-				periods (not the ulReload value which accounted for part
-				ticks). */
-				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-				/* How many complete tick periods passed while the processor
-				was waiting? */
-				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-				/* The reload value is set to whatever fraction of a single tick
-				period remains. */
-				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-			}
-
-			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-			vTaskStepTick( ulCompleteTickPeriods );
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Exit with interrpts enabled. */
-			__asm volatile( "cpsie i" ::: "memory" );
-		}
-	}
-
-#endif /* #if configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
-{
-	/* Calculate the constants required to configure the tick interrupt. */
-	#if( configUSE_TICKLESS_IDLE == 1 )
-	{
-		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-	}
-	#endif /* configUSE_TICKLESS_IDLE */
-
-	/* Stop and clear the SysTick. */
-	portNVIC_SYSTICK_CTRL_REG = 0UL;
-	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-/* This is a naked function. */
-static void vPortEnableVFP( void )
-{
-	__asm volatile
-	(
-		"	ldr.w r0, =0xE000ED88		\n" /* The FPU enable bits are in the CPACR. */
-		"	ldr r1, [r0]				\n"
-		"								\n"
-		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
-		"	str r1, [r0]				\n"
-		"	bx r14						"
-	);
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		/* Obtain the number of the currently executing interrupt. */
-		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
deleted file mode 100755
index fd31d22..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM4F/portmacro.h
+++ /dev/null
@@ -1,243 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD() 															\
-{																				\
-	/* Set a PendSV to request a context switch. */								\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
-																				\
-	/* Barriers are normally not required but do ensure the code is completely	\
-	within the specified behaviour for the architecture. */						\
-	__asm volatile( "dsb" ::: "memory" );										\
-	__asm volatile( "isb" );													\
-}
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
-#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
-#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Generic helper function. */
-	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-	{
-	uint8_t ucReturn;
-
-		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
-		return ucReturn;
-	}
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-#define portINLINE	__inline
-
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE inline __attribute__(( always_inline))
-#endif
-
-portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
-{
-uint32_t ulCurrentInterrupt;
-BaseType_t xReturn;
-
-	/* Obtain the number of the currently executing interrupt. */
-	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-	if( ulCurrentInterrupt == 0 )
-	{
-		xReturn = pdFALSE;
-	}
-	else
-	{
-		xReturn = pdTRUE;
-	}
-
-	return xReturn;
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortRaiseBASEPRI( void )
-{
-uint32_t ulNewBASEPRI;
-
-	__asm volatile
-	(
-		"	mov %0, %1												\n"	\
-		"	msr basepri, %0											\n" \
-		"	isb														\n" \
-		"	dsb														\n" \
-		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
-{
-uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
-
-	__asm volatile
-	(
-		"	mrs %0, basepri											\n" \
-		"	mov %1, %2												\n"	\
-		"	msr basepri, %1											\n" \
-		"	isb														\n" \
-		"	dsb														\n" \
-		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
-
-	/* This return will not be reached but is necessary to prevent compiler
-	warnings. */
-	return ulOriginalBASEPRI;
-}
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
-{
-	__asm volatile
-	(
-		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c
deleted file mode 100755
index 9c68178..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/port.c
+++ /dev/null
@@ -1,851 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM3 port.
- *----------------------------------------------------------*/
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __VFP_FP__
-	#error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK	( 0 )
-#endif
-
-/* Constants required to access and manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL_REG				( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG				( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG		( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG					( *	( ( volatile uint32_t * ) 0xe000ed20 ) )
-#define portNVIC_SYSPRI1_REG					( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
-#define portNVIC_SYS_CTRL_STATE_REG				( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
-#define portNVIC_MEM_FAULT_ENABLE				( 1UL << 16UL )
-
-/* Constants required to access and manipulate the MPU. */
-#define portMPU_TYPE_REG						( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_REGION_BASE_ADDRESS_REG			( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
-#define portMPU_REGION_ATTRIBUTE_REG			( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
-#define portMPU_CTRL_REG						( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portEXPECTED_MPU_TYPE_VALUE				( 8UL << 8UL ) /* 8 regions, unified. */
-#define portMPU_ENABLE							( 0x01UL )
-#define portMPU_BACKGROUND_ENABLE				( 1UL << 2UL )
-#define portPRIVILEGED_EXECUTION_START_ADDRESS	( 0UL )
-#define portMPU_REGION_VALID					( 0x10UL )
-#define portMPU_REGION_ENABLE					( 0x01UL )
-#define portPERIPHERALS_START_ADDRESS			0x40000000UL
-#define portPERIPHERALS_END_ADDRESS				0x5FFFFFFFUL
-
-/* Constants required to access and manipulate the SysTick. */
-#define portNVIC_SYSTICK_INT					( 0x00000002UL )
-#define portNVIC_SYSTICK_ENABLE					( 0x00000001UL )
-#define portNVIC_PENDSV_PRI						( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI						( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR								( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS				( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR						( 0x01000000UL )
-#define portINITIAL_EXC_RETURN					( 0xfffffffdUL )
-#define portINITIAL_CONTROL_IF_UNPRIVILEGED		( 0x03 )
-#define portINITIAL_CONTROL_IF_PRIVILEGED		( 0x02 )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Offsets in the stack to the parameters when inside the SVC handler. */
-#define portOFFSET_TO_PC						( 6 )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
-
-/*
- * Configure a number of standard MPU regions that are used by all tasks.
- */
-static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Return the smallest MPU region size that a given number of bytes will fit
- * into.  The region size is returned as the value that should be programmed
- * into the region attribute register for that region.
- */
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Standard FreeRTOS exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-void xPortSysTickHandler( void )  __attribute__ ((optimize("3"))) PRIVILEGED_FUNCTION;
-void vPortSVCHandler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/*
- * Starts the scheduler by restoring the context of the first task to run.
- */
-static void prvRestoreContextOfFirstTask( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/*
- * C portion of the SVC handler.  The SVC handler is split between an asm entry
- * and a C wrapper for simplicity of coding and maintenance.
- */
-static void prvSVCHandler( uint32_t *pulRegisters ) __attribute__(( noinline )) PRIVILEGED_FUNCTION;
-
-/*
- * Function to enable the VFP.
- */
- static void vPortEnableVFP( void ) __attribute__ (( naked ));
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Calls the port specific code to raise the privilege.
- *
- * @return pdFALSE if privilege was raised, pdTRUE otherwise.
- */
-extern BaseType_t xPortRaisePrivilege( void );
-
-/**
- * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
- * code to reset the privilege, otherwise does nothing.
- */
-extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable.  Note this is not saved as part of the task context as context
-switches can only occur when uxCriticalNesting is zero. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = 0;	/* LR */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-
-	/* A save method is being used that requires each task to maintain its
-	own exec return value. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-	pxTopOfStack -= 9;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	if( xRunPrivileged == pdTRUE )
-	{
-		*pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
-	}
-	else
-	{
-		*pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
-	}
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
-	/* Assumes psp was in use. */
-	__asm volatile
-	(
-		#ifndef USE_PROCESS_STACK	/* Code should not be required if a main() is using the process stack. */
-			"	tst lr, #4						\n"
-			"	ite eq							\n"
-			"	mrseq r0, msp					\n"
-			"	mrsne r0, psp					\n"
-		#else
-			"	mrs r0, psp						\n"
-		#endif
-			"	b %0							\n"
-			::"i"(prvSVCHandler):"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-static void prvSVCHandler(	uint32_t *pulParam )
-{
-uint8_t ucSVCNumber;
-
-	/* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
-	xPSR.  The first argument (r0) is pulParam[ 0 ]. */
-	ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
-	switch( ucSVCNumber )
-	{
-		case portSVC_START_SCHEDULER	:	portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
-											prvRestoreContextOfFirstTask();
-											break;
-
-		case portSVC_YIELD				:	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-											/* Barriers are normally not required
-											but do ensure the code is completely
-											within the specified behaviour for the
-											architecture. */
-											__asm volatile( "dsb" ::: "memory" );
-											__asm volatile( "isb" );
-
-											break;
-
-		case portSVC_RAISE_PRIVILEGE	:	__asm volatile
-											(
-												"	mrs r1, control		\n" /* Obtain current control value. */
-												"	bic r1, #1			\n" /* Set privilege bit. */
-												"	msr control, r1		\n" /* Write back new control value. */
-												::: "r1", "memory"
-											);
-											break;
-
-		default							:	/* Unknown SVC call. */
-											break;
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvRestoreContextOfFirstTask( void )
-{
-	__asm volatile
-	(
-		"	ldr r0, =0xE000ED08				\n" /* Use the NVIC offset register to locate the stack. */
-		"	ldr r0, [r0]					\n"
-		"	ldr r0, [r0]					\n"
-		"	msr msp, r0						\n" /* Set the msp back to the start of the stack. */
-		"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
-		"	ldr r1, [r3]					\n"
-		"	ldr r0, [r1]					\n" /* The first item in the TCB is the task top of stack. */
-		"	add r1, r1, #4					\n" /* Move onto the second item in the TCB... */
-		"	ldr r2, =0xe000ed9c				\n" /* Region Base Address register. */
-		"	ldmia r1!, {r4-r11}				\n" /* Read 4 sets of MPU registers. */
-		"	stmia r2!, {r4-r11}				\n" /* Write 4 sets of MPU registers. */
-		"	ldmia r0!, {r3-r11, r14}		\n" /* Pop the registers that are not automatically saved on exception entry. */
-		"	msr control, r3					\n"
-		"	msr psp, r0						\n" /* Restore the task stack pointer. */
-		"	mov r0, #0						\n"
-		"	msr	basepri, r0					\n"
-		"	bx r14							\n"
-		"									\n"
-		"	.align 4						\n"
-		"pxCurrentTCBConst2: .word pxCurrentTCB	\n"
-	);
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See
-	http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-	configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the same priority as the kernel, and the SVC
-	handler higher priority so it can be used to exit a critical section (where
-	lower priorities are masked). */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Configure the regions in the MPU that are common to all tasks. */
-	prvSetupMPU();
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Ensure the VFP is enabled - it should be anyway. */
-	vPortEnableVFP();
-
-	/* Lazy save always. */
-	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
-	/* Start the first task.  This also clears the bit that indicates the FPU is
-	in use in case the FPU was used before the scheduler was started - which
-	would otherwise result in the unnecessary leaving of space in the SVC stack
-	for lazy saving of FPU registers. */
-	__asm volatile(
-					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
-					" ldr r0, [r0] 			\n"
-					" ldr r0, [r0] 			\n"
-					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
-					" mov r0, #0			\n" /* Clear the bit that indicates the FPU is in use, see comment above. */
-					" msr control, r0		\n"
-					" cpsie i				\n" /* Globally enable interrupts. */
-					" cpsie f				\n"
-					" dsb					\n"
-					" isb					\n"
-					" svc %0				\n" /* System call to start first task. */
-					" nop					\n"
-					:: "i" (portSVC_START_SCHEDULER) : "memory" );
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
-	/* This is a naked function. */
-
-	__asm volatile
-	(
-		"	mrs r0, psp							\n"
-		"	isb									\n"
-		"										\n"
-		"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
-		"	ldr	r2, [r3]						\n"
-		"										\n"
-		"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, push high vfp registers. */
-		"	it eq								\n"
-		"	vstmdbeq r0!, {s16-s31}				\n"
-		"										\n"
-		"	mrs r1, control						\n"
-		"	stmdb r0!, {r1, r4-r11, r14}		\n" /* Save the remaining registers. */
-		"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
-		"										\n"
-		"	stmdb sp!, {r0, r3}					\n"
-		"	mov r0, %0							\n"
-		"	msr basepri, r0						\n"
-		"	dsb									\n"
-		"	isb									\n"
-		"	bl vTaskSwitchContext				\n"
-		"	mov r0, #0							\n"
-		"	msr basepri, r0						\n"
-		"	ldmia sp!, {r0, r3}					\n"
-		"										\n" /* Restore the context. */
-		"	ldr r1, [r3]						\n"
-		"	ldr r0, [r1]						\n" /* The first item in the TCB is the task top of stack. */
-		"	add r1, r1, #4						\n" /* Move onto the second item in the TCB... */
-		"	ldr r2, =0xe000ed9c					\n" /* Region Base Address register. */
-		"	ldmia r1!, {r4-r11}					\n" /* Read 4 sets of MPU registers. */
-		"	stmia r2!, {r4-r11}					\n" /* Write 4 sets of MPU registers. */
-		"	ldmia r0!, {r3-r11, r14}			\n" /* Pop the registers that are not automatically saved on exception entry. */
-		"	msr control, r3						\n"
-		"										\n"
-		"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
-		"	it eq								\n"
-		"	vldmiaeq r0!, {s16-s31}				\n"
-		"										\n"
-		"	msr psp, r0							\n"
-		"	bx r14								\n"
-		"										\n"
-		"	.align 4							\n"
-		"pxCurrentTCBConst: .word pxCurrentTCB	\n"
-		::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
-	);
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-uint32_t ulDummy;
-
-	ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
-{
-	/* Stop and clear the SysTick. */
-	portNVIC_SYSTICK_CTRL_REG = 0UL;
-	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE );
-}
-/*-----------------------------------------------------------*/
-
-/* This is a naked function. */
-static void vPortEnableVFP( void )
-{
-	__asm volatile
-	(
-		"	ldr.w r0, =0xE000ED88		\n" /* The FPU enable bits are in the CPACR. */
-		"	ldr r1, [r0]				\n"
-		"								\n"
-		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
-		"	str r1, [r0]				\n"
-		"	bx r14						"
-	);
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupMPU( void )
-{
-extern uint32_t __privileged_functions_end__[];
-extern uint32_t __FLASH_segment_start__[];
-extern uint32_t __FLASH_segment_end__[];
-extern uint32_t __privileged_data_start__[];
-extern uint32_t __privileged_data_end__[];
-
-	/* Check the expected MPU is present. */
-	if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-	{
-		/* First setup the entire flash for unprivileged read only access. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
-											( portMPU_REGION_VALID ) |
-											( portUNPRIVILEGED_FLASH_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_ONLY ) |
-										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-										( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
-										( portMPU_REGION_ENABLE );
-
-		/* Setup the first nK for privileged only access (even though less
-		than 10K is actually being used).  This is where the kernel code is
-		placed. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
-											( portMPU_REGION_VALID ) |
-											( portPRIVILEGED_FLASH_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
-										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-										( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
-										( portMPU_REGION_ENABLE );
-
-		/* Setup the privileged data RAM region.  This is where the kernel data
-		is placed. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
-											( portMPU_REGION_VALID ) |
-											( portPRIVILEGED_RAM_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-										prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
-										( portMPU_REGION_ENABLE );
-
-		/* By default allow everything to access the general peripherals.  The
-		system peripherals and registers are protected. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( portPERIPHERALS_START_ADDRESS ) |
-											( portMPU_REGION_VALID ) |
-											( portGENERAL_PERIPHERALS_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
-										( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
-										( portMPU_REGION_ENABLE );
-
-		/* Enable the memory fault exception. */
-		portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
-
-		/* Enable the MPU with the background region configured. */
-		portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
-	}
-}
-/*-----------------------------------------------------------*/
-
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
-{
-uint32_t ulRegionSize, ulReturnValue = 4;
-
-	/* 32 is the smallest region size, 31 is the largest valid value for
-	ulReturnValue. */
-	for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
-	{
-		if( ulActualSizeInBytes <= ulRegionSize )
-		{
-			break;
-		}
-		else
-		{
-			ulReturnValue++;
-		}
-	}
-
-	/* Shift the code by one before returning so it can be written directly
-	into the the correct bit position of the attribute register. */
-	return ( ulReturnValue << 1UL );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control							\n" /* r0 = CONTROL. */
-	"	tst r0, #1								\n" /* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	"	ite ne									\n"
-	"	movne r0, #0							\n" /* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	"	moveq r0, #1							\n" /* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	"	bx lr									\n" /* Return. */
-	"											\n"
-	"	.align 4								\n"
-	::: "r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vResetPrivilege( void ) /* __attribute__ (( naked )) */
-{
-	__asm volatile
-	(
-	"	mrs r0, control							\n" /* r0 = CONTROL. */
-	"	orr r0, #1								\n" /* r0 = r0 | 1. */
-	"	msr control, r0							\n" /* CONTROL = r0. */
-	"	bx lr									\n" /* Return to the caller. */
-	:::"r0", "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-{
-extern uint32_t __SRAM_segment_start__[];
-extern uint32_t __SRAM_segment_end__[];
-extern uint32_t __privileged_data_start__[];
-extern uint32_t __privileged_data_end__[];
-int32_t lIndex;
-uint32_t ul;
-
-	if( xRegions == NULL )
-	{
-		/* No MPU regions are specified so allow access to all RAM. */
-		xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
-				( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
-				( portMPU_REGION_VALID ) |
-				( portSTACK_REGION );
-
-		xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
-				( portMPU_REGION_READ_WRITE ) |
-				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-				( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
-				( portMPU_REGION_ENABLE );
-
-		/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
-		just removed the privileged only parameters. */
-		xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
-				( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
-				( portMPU_REGION_VALID ) |
-				( portSTACK_REGION + 1 );
-
-		xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
-				( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-				prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
-				( portMPU_REGION_ENABLE );
-
-		/* Invalidate all other regions. */
-		for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
-		{
-			xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
-			xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
-		}
-	}
-	else
-	{
-		/* This function is called automatically when the task is created - in
-		which case the stack region parameters will be valid.  At all other
-		times the stack parameters will not be valid and it is assumed that the
-		stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
-					( ( uint32_t ) pxBottomOfStack ) |
-					( portMPU_REGION_VALID ) |
-					( portSTACK_REGION ); /* Region number. */
-
-			xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
-					( portMPU_REGION_READ_WRITE ) | /* Read and write. */
-					( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
-					( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-					( portMPU_REGION_ENABLE );
-		}
-
-		lIndex = 0;
-
-		for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
-		{
-			if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
-			{
-				/* Translate the generic region definition contained in
-				xRegions into the CM3 specific MPU settings that are then
-				stored in xMPUSettings. */
-				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
-						( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
-						( portMPU_REGION_VALID ) |
-						( portSTACK_REGION + ul ); /* Region number. */
-
-				xMPUSettings->xRegion[ ul ].ulRegionAttribute =
-						( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
-						( xRegions[ lIndex ].ulParameters ) |
-						( portMPU_REGION_ENABLE );
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
-				xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		/* Obtain the number of the currently executing interrupt. */
-		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredicable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
deleted file mode 100755
index 3458b0e..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM4_MPU/portmacro.h
+++ /dev/null
@@ -1,301 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* MPU specific constants. */
-#define portUSING_MPU_WRAPPERS		1
-#define portPRIVILEGE_BIT			( 0x80000000UL )
-
-#define portMPU_REGION_READ_WRITE				( 0x03UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY		( 0x05UL << 24UL )
-#define portMPU_REGION_READ_ONLY				( 0x06UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_WRITE	( 0x01UL << 24UL )
-#define portMPU_REGION_CACHEABLE_BUFFERABLE		( 0x07UL << 16UL )
-#define portMPU_REGION_EXECUTE_NEVER			( 0x01UL << 28UL )
-
-#define portUNPRIVILEGED_FLASH_REGION		( 0UL )
-#define portPRIVILEGED_FLASH_REGION			( 1UL )
-#define portPRIVILEGED_RAM_REGION			( 2UL )
-#define portGENERAL_PERIPHERALS_REGION		( 3UL )
-#define portSTACK_REGION					( 4UL )
-#define portFIRST_CONFIGURABLE_REGION	    ( 5UL )
-#define portLAST_CONFIGURABLE_REGION		( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS		( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS				( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, #1 \n msr control, r0 " ::: "r0", "memory" )
-
-typedef struct MPU_REGION_REGISTERS
-{
-	uint32_t ulRegionBaseAddress;
-	uint32_t ulRegionAttribute;
-} xMPU_REGION_REGISTERS;
-
-/* Plus 1 to create space for the stack region. */
-typedef struct MPU_SETTINGS
-{
-	xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
-} xMPU_SETTINGS;
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-/* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER				0
-#define portSVC_YIELD						1
-#define portSVC_RAISE_PRIVILEGE				2
-
-/* Scheduler utilities. */
-
-#define portYIELD()				__asm volatile ( "	SVC	%0	\n" :: "i" (portSVC_YIELD) : "memory" )
-#define portYIELD_WITHIN_API() 													\
-{																				\
-	/* Set a PendSV to request a context switch. */								\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
-																				\
-	/* Barriers are normally not required but do ensure the code is completely	\
-	within the specified behaviour for the architecture. */						\
-	__asm volatile( "dsb" ::: "memory" );										\
-	__asm volatile( "isb" );													\
-}
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
-#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
-#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Generic helper function. */
-	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-	{
-	uint8_t ucReturn;
-
-		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
-		return ucReturn;
-	}
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-#define portINLINE	__inline
-
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE inline __attribute__(( always_inline))
-#endif
-/*-----------------------------------------------------------*/
-
-extern BaseType_t xIsPrivileged( void );
-extern void vResetPrivilege( void );
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-#define portIS_PRIVILEGED()			xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
-*/
-#define portRAISE_PRIVILEGE()		__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
-#define portRESET_PRIVILEGE()		vResetPrivilege()
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
-{
-uint32_t ulCurrentInterrupt;
-BaseType_t xReturn;
-
-	/* Obtain the number of the currently executing interrupt. */
-	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-	if( ulCurrentInterrupt == 0 )
-	{
-		xReturn = pdFALSE;
-	}
-	else
-	{
-		xReturn = pdTRUE;
-	}
-
-	return xReturn;
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortRaiseBASEPRI( void )
-{
-uint32_t ulNewBASEPRI;
-
-	__asm volatile
-	(
-		"	mov %0, %1												\n"	\
-		"	msr basepri, %0											\n" \
-		"	isb														\n" \
-		"	dsb														\n" \
-		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
-{
-uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
-
-	__asm volatile
-	(
-		"	mrs %0, basepri											\n" \
-		"	mov %1, %2												\n"	\
-		"	msr basepri, %1											\n" \
-		"	isb														\n" \
-		"	dsb														\n" \
-		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
-
-	/* This return will not be reached but is necessary to prevent compiler
-	warnings. */
-	return ulOriginalBASEPRI;
-}
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
-{
-	__asm volatile
-	(
-		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM7/ReadMe.txt b/FreeRTOS/Source/portable/GCC/ARM_CM7/ReadMe.txt
deleted file mode 100755
index 4cf25c5..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM7/ReadMe.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
-The best option depends on the revision of the ARM Cortex-M7 core in use.  The
-revision is specified by an 'r' number, and a 'p' number, so will look something
-like 'r0p1'.  Check the documentation for the microcontroller in use to find the 
-revision of the Cortex-M7 core used in that microcontroller.  If in doubt, use 
-the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
-with all core revisions.
-
-The first option is to use the ARM Cortex-M4F port, and the second option is to
-use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
-
-If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
-used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in 
-the /FreeRTOS/Source/portable/GCC/ARM_CM4F directory.
-
-If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
-Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1
-directory.
\ No newline at end of file
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
deleted file mode 100755
index 7822afb..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/port.c
+++ /dev/null
@@ -1,765 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __VFP_FP__
-	#error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
-
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR					( 0x01000000 )
-#define portINITIAL_EXC_RETURN				( 0xfffffffd )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR			( 45UL )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void ) __attribute__ (( naked ));
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void ) __attribute__ (( naked ));
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
-
-/*
- * Function to enable the VFP.
- */
-static void vPortEnableVFP( void ) __attribute__ (( naked ));
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-
-	/* Offset added to account for the way the MCU uses the stack on entry/exit
-	of interrupts, and to ensure alignment. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-
-	/* Save code space by skipping register initialisation. */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-
-	/* A save method is being used that requires each task to maintain its
-	own exec return value. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0;
-
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		started to remove a compiler warning about the function being defined
-		but never called.  ulDummy is used purely to quieten other warnings
-		about code appearing after this function is called - making ulDummy
-		volatile makes the compiler think the function could return and
-		therefore not output an 'unreachable code' warning for code that appears
-		after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
-	__asm volatile (
-					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
-					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
-					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
-					"	ldmia r0!, {r4-r11, r14}		\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
-					"	msr psp, r0						\n" /* Restore the task stack pointer. */
-					"	isb								\n"
-					"	mov r0, #0 						\n"
-					"	msr	basepri, r0					\n"
-					"	bx r14							\n"
-					"									\n"
-					"	.align 4						\n"
-					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
-				);
-}
-/*-----------------------------------------------------------*/
-
-static void prvPortStartFirstTask( void )
-{
-	/* Start the first task.  This also clears the bit that indicates the FPU is
-	in use in case the FPU was used before the scheduler was started - which
-	would otherwise result in the unnecessary leaving of space in the SVC stack
-	for lazy saving of FPU registers. */
-	__asm volatile(
-					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
-					" ldr r0, [r0] 			\n"
-					" ldr r0, [r0] 			\n"
-					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
-					" mov r0, #0			\n" /* Clear the bit that indicates the FPU is in use, see comment above. */
-					" msr control, r0		\n"
-					" cpsie i				\n" /* Globally enable interrupts. */
-					" cpsie f				\n"
-					" dsb					\n"
-					" isb					\n"
-					" svc 0					\n" /* System call to start first task. */
-					" nop					\n"
-				);
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Ensure the VFP is enabled - it should be anyway. */
-	vPortEnableVFP();
-
-	/* Lazy save always. */
-	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
-	/* Start the first task. */
-	prvPortStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing!  Call the task
-	exit error function to prevent compiler warnings about a static function
-	not being called in the case that the application writer overrides this
-	functionality by defining configTASK_RETURN_ADDRESS.  Call
-	vTaskSwitchContext() so link time optimisation does not remove the
-	symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
-	/* This is a naked function. */
-
-	__asm volatile
-	(
-	"	mrs r0, psp							\n"
-	"	isb									\n"
-	"										\n"
-	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
-	"	ldr	r2, [r3]						\n"
-	"										\n"
-	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, push high vfp registers. */
-	"	it eq								\n"
-	"	vstmdbeq r0!, {s16-s31}				\n"
-	"										\n"
-	"	stmdb r0!, {r4-r11, r14}			\n" /* Save the core registers. */
-	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
-	"										\n"
-	"	stmdb sp!, {r0, r3}					\n"
-	"	mov r0, %0 							\n"
-	"	cpsid i								\n" /* Errata workaround. */
-	"	msr basepri, r0						\n"
-	"	dsb									\n"
-	"	isb									\n"
-	"	cpsie i								\n" /* Errata workaround. */
-	"	bl vTaskSwitchContext				\n"
-	"	mov r0, #0							\n"
-	"	msr basepri, r0						\n"
-	"	ldmia sp!, {r0, r3}					\n"
-	"										\n"
-	"	ldr r1, [r3]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
-	"	ldr r0, [r1]						\n"
-	"										\n"
-	"	ldmia r0!, {r4-r11, r14}			\n" /* Pop the core registers. */
-	"										\n"
-	"	tst r14, #0x10						\n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
-	"	it eq								\n"
-	"	vldmiaeq r0!, {s16-s31}				\n"
-	"										\n"
-	"	msr psp, r0							\n"
-	"	isb									\n"
-	"										\n"
-	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata workaround. */
-		#if WORKAROUND_PMU_CM001 == 1
-	"			push { r14 }				\n"
-	"			pop { pc }					\n"
-		#endif
-	#endif
-	"										\n"
-	"	bx r14								\n"
-	"										\n"
-	"	.align 4							\n"
-	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
-	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
-	);
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known. */
-	portDISABLE_INTERRUPTS();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TICKLESS_IDLE == 1 )
-
-	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-	TickType_t xModifiableIdleTime;
-
-		/* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
-		is accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-		/* Calculate the reload value required to wait xExpectedIdleTime
-		tick periods.  -1 is used because this code will execute part way
-		through one of the tick periods. */
-		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-		if( ulReloadValue > ulStoppedTimerCompensation )
-		{
-			ulReloadValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Enter a critical section but don't use the taskENTER_CRITICAL()
-		method as that will mask interrupts that should exit sleep mode. */
-		__asm volatile( "cpsid i" ::: "memory" );
-		__asm volatile( "dsb" );
-		__asm volatile( "isb" );
-
-		/* If a context switch is pending or a task is waiting for the scheduler
-		to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-		{
-			/* Restart from whatever is left in the count register to complete
-			this tick period. */
-			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Reset the reload register to the value required for normal tick
-			periods. */
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Re-enable interrupts - see comments above the cpsid instruction()
-			above. */
-			__asm volatile( "cpsie i" ::: "memory" );
-		}
-		else
-		{
-			/* Set the new reload value. */
-			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-			/* Clear the SysTick count flag and set the count value back to
-			zero. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-			set its parameter to 0 to indicate that its implementation contains
-			its own wait for interrupt or wait for event instruction, and so wfi
-			should not be executed again.  However, the original expected idle
-			time variable must remain unmodified, so a copy is taken. */
-			xModifiableIdleTime = xExpectedIdleTime;
-			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-			if( xModifiableIdleTime > 0 )
-			{
-				__asm volatile( "dsb" ::: "memory" );
-				__asm volatile( "wfi" );
-				__asm volatile( "isb" );
-			}
-			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-			/* Re-enable interrupts to allow the interrupt that brought the MCU
-			out of sleep mode to execute immediately.  see comments above
-			__disable_interrupt() call above. */
-			__asm volatile( "cpsie i" ::: "memory" );
-			__asm volatile( "dsb" );
-			__asm volatile( "isb" );
-
-			/* Disable interrupts again because the clock is about to be stopped
-			and interrupts that execute while the clock is stopped will increase
-			any slippage between the time maintained by the RTOS and calendar
-			time. */
-			__asm volatile( "cpsid i" ::: "memory" );
-			__asm volatile( "dsb" );
-			__asm volatile( "isb" );
-
-			/* Disable the SysTick clock without reading the
-			portNVIC_SYSTICK_CTRL_REG register to ensure the
-			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
-			the time the SysTick is stopped for is accounted for as best it can
-			be, but using the tickless mode will inevitably result in some tiny
-			drift of the time maintained by the kernel with respect to calendar
-			time*/
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-			/* Determine if the SysTick clock has already counted to zero and
-			been set back to the current reload value (the reload back being
-			correct for the entire expected idle time) or if the SysTick is yet
-			to count to zero (in which case an interrupt other than the SysTick
-			must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-			{
-				uint32_t ulCalculatedLoadValue;
-
-				/* The tick interrupt is already pending, and the SysTick count
-				reloaded with ulReloadValue.  Reset the
-				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-				period. */
-				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-				/* Don't allow a tiny value, or values that have somehow
-				underflowed because the post sleep hook did something
-				that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-				{
-					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-				}
-
-				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-				/* As the pending tick will be processed as soon as this
-				function exits, the tick value maintained by the tick is stepped
-				forward by one less than the time spent waiting. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				Work out how long the sleep lasted rounded to complete tick
-				periods (not the ulReload value which accounted for part
-				ticks). */
-				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-				/* How many complete tick periods passed while the processor
-				was waiting? */
-				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-				/* The reload value is set to whatever fraction of a single tick
-				period remains. */
-				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-			}
-
-			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-			vTaskStepTick( ulCompleteTickPeriods );
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Exit with interrpts enabled. */
-			__asm volatile( "cpsie i" ::: "memory" );
-		}
-	}
-
-#endif /* #if configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
-{
-	/* Calculate the constants required to configure the tick interrupt. */
-	#if( configUSE_TICKLESS_IDLE == 1 )
-	{
-		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-	}
-	#endif /* configUSE_TICKLESS_IDLE */
-
-	/* Stop and clear the SysTick. */
-	portNVIC_SYSTICK_CTRL_REG = 0UL;
-	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-/* This is a naked function. */
-static void vPortEnableVFP( void )
-{
-	__asm volatile
-	(
-		"	ldr.w r0, =0xE000ED88		\n" /* The FPU enable bits are in the CPACR. */
-		"	ldr r1, [r0]				\n"
-		"								\n"
-		"	orr r1, r1, #( 0xf << 20 )	\n" /* Enable CP10 and CP11 coprocessors, then save back. */
-		"	str r1, [r0]				\n"
-		"	bx r14						"
-	);
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		/* Obtain the number of the currently executing interrupt. */
-		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
deleted file mode 100755
index 62543ac..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CM7/r0p1/portmacro.h
+++ /dev/null
@@ -1,247 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD() 															\
-{																				\
-	/* Set a PendSV to request a context switch. */								\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
-																				\
-	/* Barriers are normally not required but do ensure the code is completely	\
-	within the specified behaviour for the architecture. */						\
-	__asm volatile( "dsb" ::: "memory" );										\
-	__asm volatile( "isb" );													\
-}
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
-#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
-#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Generic helper function. */
-	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-	{
-	uint8_t ucReturn;
-
-		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) : "memory" );
-		return ucReturn;
-	}
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-#define portINLINE	__inline
-
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE inline __attribute__(( always_inline))
-#endif
-
-portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
-{
-uint32_t ulCurrentInterrupt;
-BaseType_t xReturn;
-
-	/* Obtain the number of the currently executing interrupt. */
-	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-	if( ulCurrentInterrupt == 0 )
-	{
-		xReturn = pdFALSE;
-	}
-	else
-	{
-		xReturn = pdTRUE;
-	}
-
-	return xReturn;
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortRaiseBASEPRI( void )
-{
-uint32_t ulNewBASEPRI;
-
-	__asm volatile
-	(
-		"	mov %0, %1												\n"	\
-		"	cpsid i													\n" \
-		"	msr basepri, %0											\n" \
-		"	isb														\n" \
-		"	dsb														\n" \
-		"	cpsie i													\n" \
-		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
-}
-
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
-{
-uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
-
-	__asm volatile
-	(
-		"	mrs %0, basepri											\n" \
-		"	mov %1, %2												\n"	\
-		"	cpsid i													\n" \
-		"	msr basepri, %1											\n" \
-		"	isb														\n" \
-		"	dsb														\n" \
-		"	cpsie i													\n" \
-		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) : "memory"
-	);
-
-	/* This return will not be reached but is necessary to prevent compiler
-	warnings. */
-	return ulOriginalBASEPRI;
-}
-/*-----------------------------------------------------------*/
-
-portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
-{
-	__asm volatile
-	(
-		"	msr basepri, %0	" :: "r" ( ulNewMaskValue ) : "memory"
-	);
-}
-/*-----------------------------------------------------------*/
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c b/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
deleted file mode 100755
index 1328c45..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CR5/port.c
+++ /dev/null
@@ -1,525 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
-	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
-	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configUNIQUE_INTERRUPT_PRIORITIES
-	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configSETUP_TICK_INTERRUPT
-	#error configSETUP_TICK_INTERRUPT() must be defined.  Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif /* configSETUP_TICK_INTERRUPT */
-
-#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  Refer to Cortex-A equivalent: http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/* In case security extensions are implemented. */
-#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-#endif
-
-/* Some vendor specific files default configCLEAR_TICK_INTERRUPT() in
-portmacro.h. */
-#ifndef configCLEAR_TICK_INTERRUPT
-	#define configCLEAR_TICK_INTERRUPT()
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
-
-/* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE				( 0xFFUL )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
-
-/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portINTERRUPT_ENABLE_BIT		( 0x80UL )
-#define portTHUMB_MODE_ADDRESS			( 0x01UL )
-
-/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
-
-/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK			( 0x1F )
-
-/* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE				( 0x10 )
-
-/* The critical section macros only mask interrupts up to an application
-determined priority level.  Sometimes it is necessary to turn interrupt off in
-the CPU itself before modifying certain hardware registers. */
-#define portCPU_IRQ_DISABLE()										\
-	__asm volatile ( "CPSID i" ::: "memory" );						\
-	__asm volatile ( "DSB" );										\
-	__asm volatile ( "ISB" );
-
-#define portCPU_IRQ_ENABLE()										\
-	__asm volatile ( "CPSIE i" ::: "memory" );						\
-	__asm volatile ( "DSB" );										\
-	__asm volatile ( "ISB" );
-
-
-/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK()									\
-{																	\
-	portCPU_IRQ_DISABLE();											\
-	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;			\
-	__asm volatile (	"DSB		\n"								\
-						"ISB		\n" );							\
-	portCPU_IRQ_ENABLE();											\
-}
-
-#define portINTERRUPT_PRIORITY_REGISTER_OFFSET		0x400UL
-#define portMAX_8_BIT_VALUE							( ( uint8_t ) 0xff )
-#define portBIT_0_SET								( ( uint8_t ) 0x01 )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case is messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing.  This function is necessarily written in
- * assembly code so is implemented in portASM.s.
- */
-extern void vPortRestoreTaskContext( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
-uint32_t ulPortTaskHasFPUContext = pdFALSE;
-
-/* Set to 1 to pend a context switch from an ISR. */
-uint32_t ulPortYieldRequired = pdFALSE;
-
-/* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
-uint32_t ulPortInterruptNesting = 0UL;
-
-/* Used in asm code. */
-__attribute__(( used )) const uint32_t ulICCIAR = portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulICCEOIR = portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulICCPMR	= portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS;
-__attribute__(( used )) const uint32_t ulMaxAPIPriorityMask = ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro.
-
-	The fist real value on the stack is the status register, which is set for
-	system mode, with interrupts enabled.  A few NULLs are added first to ensure
-	GDB does not try decoding a non-existent return address. */
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
-	{
-		/* The task will start in THUMB mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-
-	pxTopOfStack--;
-
-	/* Next the return address, which in this case is the start of the task. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-
-	/* Next all the registers other than the stack pointer. */
-	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The task will start with a critical nesting count of 0 as interrupts are
-	enabled. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-	pxTopOfStack--;
-
-	/* The task will start without a floating point context.  A task that uses
-	the floating point hardware must call vPortTaskUsesFPU() before executing
-	any floating point instructions. */
-	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( ulPortInterruptNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-uint32_t ulAPSR, ulCycles = 8; /* 8 bits per byte. */
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( configINTERRUPT_CONTROLLER_BASE_ADDRESS + portINTERRUPT_PRIORITY_REGISTER_OFFSET );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine how many priority bits are implemented in the GIC.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to
-		all possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Shift to the least significant bits. */
-		while( ( ucMaxPriorityValue & portBIT_0_SET ) != portBIT_0_SET )
-		{
-			ucMaxPriorityValue >>= ( uint8_t ) 0x01;
-
-			/* If ulCycles reaches 0 then ucMaxPriorityValue must have been
-			read as 0, indicating a misconfiguration. */
-			ulCycles--;
-			if( ulCycles == 0 )
-			{
-				break;
-			}
-		}
-
-		/* Sanity check configUNIQUE_INTERRUPT_PRIORITIES matches the read
-		value. */
-		configASSERT( ucMaxPriorityValue == portLOWEST_INTERRUPT_PRIORITY );
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Only continue if the CPU is not in User mode.  The CPU must be in a
-	Privileged mode for the scheduler to start. */
-	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
-	ulAPSR &= portAPSR_MODE_BITS_MASK;
-	configASSERT( ulAPSR != portAPSR_USER_MODE );
-
-	if( ulAPSR != portAPSR_USER_MODE )
-	{
-		/* Only continue if the binary point value is set to its lowest possible
-		setting.  See the comments in vPortValidateInterruptPriority() below for
-		more information. */
-		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
-
-		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
-		{
-			/* Interrupts are turned off in the CPU itself to ensure tick does
-			not execute	while the scheduler is being started.  Interrupts are
-			automatically turned back on in the CPU when the first task starts
-			executing. */
-			portCPU_IRQ_DISABLE();
-
-			/* Start the timer that generates the tick ISR. */
-			configSETUP_TICK_INTERRUPT();
-
-			/* Start the first task executing. */
-			vPortRestoreTaskContext();
-		}
-	}
-
-	/* Will only get here if vTaskStartScheduler() was called with the CPU in
-	a non-privileged mode or the binary point register was not set to its lowest
-	possible value.  prvTaskExitError() is referenced to prevent a compiler
-	warning about it being defined but not referenced in the case that the user
-	defines their own exit address. */
-	( void ) prvTaskExitError;
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	/* Mask interrupts up to the max syscall interrupt priority. */
-	ulPortSetInterruptMask();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( ulCriticalNesting == 1 )
-	{
-		configASSERT( ulPortInterruptNesting == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as the critical section is being
-		exited. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then all interrupt
-		priorities must be re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Critical nesting has reached zero so all interrupt priorities
-			should be unmasked. */
-			portCLEAR_INTERRUPT_MASK();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void FreeRTOS_Tick_Handler( void )
-{
-	/* Set interrupt mask before altering scheduler structures.   The tick
-	handler runs at the lowest priority, so interrupts cannot already be masked,
-	so there is no need to save and restore the current mask value.  It is
-	necessary to turn off interrupts in the CPU itself while the ICCPMR is being
-	updated. */
-	portCPU_IRQ_DISABLE();
-	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-	__asm volatile (	"dsb		\n"
-						"isb		\n" ::: "memory" );
-	portCPU_IRQ_ENABLE();
-
-	/* Increment the RTOS tick. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		ulPortYieldRequired = pdTRUE;
-	}
-
-	/* Ensure all interrupt priorities are active again. */
-	portCLEAR_INTERRUPT_MASK();
-	configCLEAR_TICK_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortTaskUsesFPU( void )
-{
-uint32_t ulInitialFPSCR = 0;
-
-	/* A task is registering the fact that it needs an FPU context.  Set the
-	FPU flag (which is saved as part of the task context). */
-	ulPortTaskHasFPUContext = pdTRUE;
-
-	/* Initialise the floating point status register. */
-	__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortClearInterruptMask( uint32_t ulNewMaskValue )
-{
-	if( ulNewMaskValue == pdFALSE )
-	{
-		portCLEAR_INTERRUPT_MASK();
-	}
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortSetInterruptMask( void )
-{
-uint32_t ulReturn;
-
-	/* Interrupt in the CPU must be turned off while the ICCPMR is being
-	updated. */
-	portCPU_IRQ_DISABLE();
-	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
-	{
-		/* Interrupts were already masked. */
-		ulReturn = pdTRUE;
-	}
-	else
-	{
-		ulReturn = pdFALSE;
-		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-		__asm volatile (	"dsb		\n"
-							"isb		\n" ::: "memory" );
-	}
-	portCPU_IRQ_ENABLE();
-
-	return ulReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-		/* The following assertion will fail if a service routine (ISR) for
-		an interrupt that has been assigned a priority above
-		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-		function.  ISR safe FreeRTOS API functions must *only* be called
-		from interrupts that have been assigned a priority at or below
-		configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-		Numerically low interrupt priority numbers represent logically high
-		interrupt priorities, therefore the priority of the interrupt must
-		be set to a value equal to or numerically *higher* than
-		configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-		FreeRTOS maintains separate thread and ISR API functions to ensure
-		interrupt entry is as fast and simple as possible. */
-
-		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
-
-		/* Priority grouping:  The interrupt controller (GIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		The priority grouping is configured by the GIC's binary point register
-		(ICCBPR).  Writing 0 to ICCBPR will ensure it is set to its lowest
-		possible value (which may be above 0). */
-		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
-	}
-
-#endif /* configASSERT_DEFINED */
-/*-----------------------------------------------------------*/
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S b/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
deleted file mode 100755
index cda842e..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CR5/portASM.S
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	.text
-	.arm
-
-	.set SYS_MODE,	0x1f
-	.set SVC_MODE,	0x13
-	.set IRQ_MODE,	0x12
-
-	/* Hardware registers. */
-	.extern ulICCIAR
-	.extern ulICCEOIR
-	.extern ulICCPMR
-
-	/* Variables and functions. */
-	.extern ulMaxAPIPriorityMask
-	.extern _freertos_vector_table
-	.extern pxCurrentTCB
-	.extern vTaskSwitchContext
-	.extern vApplicationIRQHandler
-	.extern ulPortInterruptNesting
-	.extern ulPortTaskHasFPUContext
-
-	.global FreeRTOS_IRQ_Handler
-	.global FreeRTOS_SWI_Handler
-	.global vPortRestoreTaskContext
-
-.macro portSAVE_CONTEXT
-
-	/* Save the LR and SPSR onto the system mode stack before switching to
-	system mode to save the remaining system mode registers. */
-	SRSDB	sp!, #SYS_MODE
-	CPS		#SYS_MODE
-	PUSH	{R0-R12, R14}
-
-	/* Push the critical nesting count. */
-	LDR		R2, ulCriticalNestingConst
-	LDR		R1, [R2]
-	PUSH	{R1}
-
-	/* Does the task have a floating point context that needs saving?  If
-	ulPortTaskHasFPUContext is 0 then no. */
-	LDR		R2, ulPortTaskHasFPUContextConst
-	LDR		R3, [R2]
-	CMP		R3, #0
-
-	/* Save the floating point context, if any. */
-	FMRXNE  R1,  FPSCR
-	VPUSHNE {D0-D15}
-	/*VPUSHNE	{D16-D31}*/
-	PUSHNE	{R1}
-
-	/* Save ulPortTaskHasFPUContext itself. */
-	PUSH	{R3}
-
-	/* Save the stack pointer in the TCB. */
-	LDR		R0, pxCurrentTCBConst
-	LDR		R1, [R0]
-	STR		SP, [R1]
-
-	.endm
-
-; /**********************************************************************/
-
-.macro portRESTORE_CONTEXT
-
-	/* Set the SP to point to the stack of the task being restored. */
-	LDR		R0, pxCurrentTCBConst
-	LDR		R1, [R0]
-	LDR		SP, [R1]
-
-	/* Is there a floating point context to restore?  If the restored
-	ulPortTaskHasFPUContext is zero then no. */
-	LDR		R0, ulPortTaskHasFPUContextConst
-	POP		{R1}
-	STR		R1, [R0]
-	CMP		R1, #0
-
-	/* Restore the floating point context, if any. */
-	POPNE 	{R0}
-	/*VPOPNE	{D16-D31}*/
-	VPOPNE	{D0-D15}
-	VMSRNE  FPSCR, R0
-
-	/* Restore the critical section nesting depth. */
-	LDR		R0, ulCriticalNestingConst
-	POP		{R1}
-	STR		R1, [R0]
-
-	/* Ensure the priority mask is correct for the critical nesting depth. */
-	LDR		R2, ulICCPMRConst
-	LDR		R2, [R2]
-	CMP		R1, #0
-	MOVEQ	R4, #255
-	LDRNE	R4, ulMaxAPIPriorityMaskConst
-	LDRNE	R4, [R4]
-	STR		R4, [R2]
-
-	/* Restore all system mode registers other than the SP (which is already
-	being used). */
-	POP		{R0-R12, R14}
-
-	/* Return to the task code, loading CPSR on the way. */
-	RFEIA	sp!
-
-	.endm
-
-
-
-
-/******************************************************************************
- * SVC handler is used to start the scheduler.
- *****************************************************************************/
-.align 4
-.type FreeRTOS_SWI_Handler, %function
-FreeRTOS_SWI_Handler:
-	/* Save the context of the current task and select a new task to run. */
-	portSAVE_CONTEXT
-	LDR R0, vTaskSwitchContextConst
-	BLX	R0
-	portRESTORE_CONTEXT
-
-
-/******************************************************************************
- * vPortRestoreTaskContext is used to start the scheduler.
- *****************************************************************************/
-.type vPortRestoreTaskContext, %function
-vPortRestoreTaskContext:
-	/* Switch to system mode. */
-	CPS		#SYS_MODE
-	portRESTORE_CONTEXT
-
-.align 4
-.type FreeRTOS_IRQ_Handler, %function
-FreeRTOS_IRQ_Handler:
-
-	/* Return to the interrupted instruction. */
-	SUB		lr, lr, #4
-
-	/* Push the return address and SPSR. */
-	PUSH	{lr}
-	MRS		lr, SPSR
-	PUSH	{lr}
-
-	/* Change to supervisor mode to allow reentry. */
-	CPS		#SVC_MODE
-
-	/* Push used registers. */
-	PUSH	{r0-r4, r12}
-
-	/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
-	for future use.  r1 holds the original ulPortInterruptNesting value for
-	future use. */
-	LDR		r3, ulPortInterruptNestingConst
-	LDR		r1, [r3]
-	ADD		r4, r1, #1
-	STR		r4, [r3]
-
-	/* Read value from the interrupt acknowledge register, which is stored in r0
-	for future parameter and interrupt clearing use. */
-	LDR 	r2, ulICCIARConst
-	LDR		r2, [r2]
-	LDR		r0, [r2]
-
-	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
-	future use.  _RB_ Is this ever needed provided the start of the stack is
-	alligned on an 8-byte boundary? */
-	MOV		r2, sp
-	AND		r2, r2, #4
-	SUB		sp, sp, r2
-
-	/* Call the interrupt handler. */
-	PUSH	{r0-r4, lr}
-	LDR		r1, vApplicationIRQHandlerConst
-	BLX		r1
-	POP		{r0-r4, lr}
-	ADD		sp, sp, r2
-
-	CPSID	i
-	DSB
-	ISB
-
-	/* Write the value read from ICCIAR to ICCEOIR. */
-	LDR 	r4, ulICCEOIRConst
-	LDR		r4, [r4]
-	STR		r0, [r4]
-
-	/* Restore the old nesting count. */
-	STR		r1, [r3]
-
-	/* A context switch is never performed if the nesting count is not 0. */
-	CMP		r1, #0
-	BNE		exit_without_switch
-
-	/* Did the interrupt request a context switch?  r1 holds the address of
-	ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
-	use. */
-	LDR		r1, =ulPortYieldRequired
-	LDR		r0, [r1]
-	CMP		r0, #0
-	BNE		switch_before_exit
-
-exit_without_switch:
-	/* No context switch.  Restore used registers, LR_irq and SPSR before
-	returning. */
-	POP		{r0-r4, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	MOVS	PC, LR
-
-switch_before_exit:
-	/* A context swtich is to be performed.  Clear the context switch pending
-	flag. */
-	MOV		r0, #0
-	STR		r0, [r1]
-
-	/* Restore used registers, LR-irq and SPSR before saving the context
-	to the task stack. */
-	POP		{r0-r4, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	portSAVE_CONTEXT
-
-	/* Call the function that selects the new task to execute.
-	vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
-	instructions, or 8 byte aligned stack allocated data.  LR does not need
-	saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
-	LDR		R0, vTaskSwitchContextConst
-	BLX		R0
-
-	/* Restore the context of, and branch to, the task selected to execute
-	next. */
-	portRESTORE_CONTEXT
-
-ulICCIARConst:	.word ulICCIAR
-ulICCEOIRConst:	.word ulICCEOIR
-ulICCPMRConst: .word ulICCPMR
-pxCurrentTCBConst: .word pxCurrentTCB
-ulCriticalNestingConst: .word ulCriticalNesting
-ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
-ulMaxAPIPriorityMaskConst: .word ulMaxAPIPriorityMask
-vTaskSwitchContextConst: .word vTaskSwitchContext
-vApplicationIRQHandlerConst: .word vApplicationIRQHandler
-ulPortInterruptNestingConst: .word ulPortInterruptNesting
-
-.end
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
deleted file mode 100755
index 5a4601c..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CR5/portmacro.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-	extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{												\
-extern uint32_t ulPortYieldRequired;			\
-												\
-	if( xSwitchRequired != pdFALSE )			\
-	{											\
-		ulPortYieldRequired = pdTRUE;			\
-	}											\
-}
-
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SWI 0" ::: "memory" );
-
-
-/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-extern void vPortInstallFreeRTOSVectorTable( void );
-
-/* These macros do not globally disable/enable interrupts.  They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL()		vPortEnterCritical();
-#define portEXIT_CRITICAL()			vPortExitCritical();
-#define portDISABLE_INTERRUPTS()	ulPortSetInterruptMask()
-#define portENABLE_INTERRUPTS()		vPortClearInterruptMask( 0 )
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
-
-/* Prototype of the FreeRTOS tick handler.  This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
-void FreeRTOS_Tick_Handler( void );
-
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
-void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __builtin_clz( uxReadyPriorities ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif /* configASSERT */
-
-#define portNOP() __asm volatile( "NOP" )
-
-
-#ifdef __cplusplus
-	} /* extern C */
-#endif
-
-
-/* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
-#if configUNIQUE_INTERRUPT_PRIORITIES == 16
-	#define portPRIORITY_SHIFT 4
-	#define portMAX_BINARY_POINT_VALUE	3
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
-	#define portPRIORITY_SHIFT 3
-	#define portMAX_BINARY_POINT_VALUE	2
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
-	#define portPRIORITY_SHIFT 2
-	#define portMAX_BINARY_POINT_VALUE	1
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
-	#define portPRIORITY_SHIFT 1
-	#define portMAX_BINARY_POINT_VALUE	0
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
-	#define portPRIORITY_SHIFT 0
-	#define portMAX_BINARY_POINT_VALUE	0
-#else
-	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
-
-/* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET  						( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET 				( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET 					( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET							( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET						( 0x14 )
-
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c b/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
deleted file mode 100755
index 96e01f0..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/port.c
+++ /dev/null
@@ -1,319 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#ifndef configSETUP_TICK_INTERRUPT
-	#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
-#endif
-
-#ifndef configCLEAR_TICK_INTERRUPT
-	#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
-
-/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS			( 0x01UL )
-
-/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK			( 0x1F )
-
-/* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE				( 0x10 )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing.  This function is necessarily written in
- * assembly code so is implemented in portASM.s.
- */
-extern void vPortRestoreTaskContext( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
-volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
-
-/* Set to 1 to pend a context switch from an ISR. */
-volatile uint32_t ulPortYieldRequired = pdFALSE;
-
-/* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
-volatile uint32_t ulPortInterruptNesting = 0UL;
-
-/* Used in the asm file to clear an interrupt. */
-__attribute__(( used )) const uint32_t ulICCEOIR = configEOI_ADDRESS;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro.
-
-	The fist real value on the stack is the status register, which is set for
-	system mode, with interrupts enabled.  A few NULLs are added first to ensure
-	GDB does not try decoding a non-existent return address. */
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
-	{
-		/* The task will start in THUMB mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-
-	pxTopOfStack--;
-
-	/* Next the return address, which in this case is the start of the task. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-
-	/* Next all the registers other than the stack pointer. */
-	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The task will start with a critical nesting count of 0 as interrupts are
-	enabled. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-	pxTopOfStack--;
-
-	/* The task will start without a floating point context.  A task that uses
-	the floating point hardware must call vPortTaskUsesFPU() before executing
-	any floating point instructions. */
-	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( ulPortInterruptNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-uint32_t ulAPSR;
-
-	/* Only continue if the CPU is not in User mode.  The CPU must be in a
-	Privileged mode for the scheduler to start. */
-	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) :: "memory" );
-	ulAPSR &= portAPSR_MODE_BITS_MASK;
-	configASSERT( ulAPSR != portAPSR_USER_MODE );
-
-	if( ulAPSR != portAPSR_USER_MODE )
-	{
-		/* Start the timer that generates the tick ISR. */
-		portDISABLE_INTERRUPTS();
-		configSETUP_TICK_INTERRUPT();
-
-		/* Start the first task executing. */
-		vPortRestoreTaskContext();
-	}
-
-	/* Will only get here if vTaskStartScheduler() was called with the CPU in
-	a non-privileged mode or the binary point register was not set to its lowest
-	possible value.  prvTaskExitError() is referenced to prevent a compiler
-	warning about it being defined but not referenced in the case that the user
-	defines their own exit address. */
-	( void ) prvTaskExitError;
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( ulCriticalNesting == 1 )
-	{
-		configASSERT( ulPortInterruptNesting == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as the critical section is being
-		exited. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then all interrupt
-		priorities must be re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Critical nesting has reached zero so all interrupt priorities
-			should be unmasked. */
-			portENABLE_INTERRUPTS();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void FreeRTOS_Tick_Handler( void )
-{
-uint32_t ulInterruptStatus;
-
-	ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-
-	/* Increment the RTOS tick. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		ulPortYieldRequired = pdTRUE;
-	}
-
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
-
-	configCLEAR_TICK_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortTaskUsesFPU( void )
-{
-uint32_t ulInitialFPSCR = 0;
-
-	/* A task is registering the fact that it needs an FPU context.  Set the
-	FPU flag (which is saved as part of the task context). */
-	ulPortTaskHasFPUContext = pdTRUE;
-
-	/* Initialise the floating point status register. */
-	__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) : "memory" );
-}
-/*-----------------------------------------------------------*/
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S b/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S
deleted file mode 100755
index a1c0077..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S
+++ /dev/null
@@ -1,264 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	.text
-	.arm
-
-	.set SYS_MODE,	0x1f
-	.set SVC_MODE,	0x13
-	.set IRQ_MODE,	0x12
-
-	/* Variables and functions. */
-	.extern ulMaxAPIPriorityMask
-	.extern _freertos_vector_table
-	.extern pxCurrentTCB
-	.extern vTaskSwitchContext
-	.extern vApplicationIRQHandler
-	.extern ulPortInterruptNesting
-	.extern ulPortTaskHasFPUContext
-	.extern ulICCEOIR
-	.extern ulPortYieldRequired
-
-	.global FreeRTOS_IRQ_Handler
-	.global FreeRTOS_SVC_Handler
-	.global vPortRestoreTaskContext
-
-
-.macro portSAVE_CONTEXT
-
-	/* Save the LR and SPSR onto the system mode stack before switching to
-	system mode to save the remaining system mode registers. */
-	SRSDB	sp!, #SYS_MODE
-	CPS		#SYS_MODE
-	PUSH	{R0-R12, R14}
-
-	/* Push the critical nesting count. */
-	LDR		R2, ulCriticalNestingConst
-	LDR		R1, [R2]
-	PUSH	{R1}
-
-	/* Does the task have a floating point context that needs saving?  If
-	ulPortTaskHasFPUContext is 0 then no. */
-	LDR		R2, ulPortTaskHasFPUContextConst
-	LDR		R3, [R2]
-	CMP		R3, #0
-
-	/* Save the floating point context, if any. */
-	FMRXNE  R1,  FPSCR
-	VPUSHNE {D0-D15}
-#if configFPU_D32 == 1
-	VPUSHNE	{D16-D31}
-#endif /* configFPU_D32 */
-	PUSHNE	{R1}
-
-	/* Save ulPortTaskHasFPUContext itself. */
-	PUSH	{R3}
-
-	/* Save the stack pointer in the TCB. */
-	LDR		R0, pxCurrentTCBConst
-	LDR		R1, [R0]
-	STR		SP, [R1]
-
-	.endm
-
-; /**********************************************************************/
-
-.macro portRESTORE_CONTEXT
-
-	/* Set the SP to point to the stack of the task being restored. */
-	LDR		R0, pxCurrentTCBConst
-	LDR		R1, [R0]
-	LDR		SP, [R1]
-
-	/* Is there a floating point context to restore?  If the restored
-	ulPortTaskHasFPUContext is zero then no. */
-	LDR		R0, ulPortTaskHasFPUContextConst
-	POP		{R1}
-	STR		R1, [R0]
-	CMP		R1, #0
-
-	/* Restore the floating point context, if any. */
-	POPNE 	{R0}
-#if configFPU_D32 == 1
-	VPOPNE	{D16-D31}
-#endif /* configFPU_D32 */
-	VPOPNE	{D0-D15}
-	VMSRNE  FPSCR, R0
-
-	/* Restore the critical section nesting depth. */
-	LDR		R0, ulCriticalNestingConst
-	POP		{R1}
-	STR		R1, [R0]
-
-	/* Restore all system mode registers other than the SP (which is already
-	being used). */
-	POP		{R0-R12, R14}
-
-	/* Return to the task code, loading CPSR on the way. */
-	RFEIA	sp!
-
-	.endm
-
-
-
-
-/******************************************************************************
- * SVC handler is used to yield.
- *****************************************************************************/
-.align 4
-.type FreeRTOS_SVC_Handler, %function
-FreeRTOS_SVC_Handler:
-	/* Save the context of the current task and select a new task to run. */
-	portSAVE_CONTEXT
-	LDR R0, vTaskSwitchContextConst
-	BLX	R0
-	portRESTORE_CONTEXT
-
-
-/******************************************************************************
- * vPortRestoreTaskContext is used to start the scheduler.
- *****************************************************************************/
-.align 4
-.type vPortRestoreTaskContext, %function
-vPortRestoreTaskContext:
-	/* Switch to system mode. */
-	CPS		#SYS_MODE
-	portRESTORE_CONTEXT
-
-.align 4
-.type FreeRTOS_IRQ_Handler, %function
-FreeRTOS_IRQ_Handler:
-	/* Return to the interrupted instruction. */
-	SUB		lr, lr, #4
-
-	/* Push the return address and SPSR. */
-	PUSH	{lr}
-	MRS		lr, SPSR
-	PUSH	{lr}
-
-	/* Change to supervisor mode to allow reentry. */
-	CPS		#0x13
-
-	/* Push used registers. */
-	PUSH	{r0-r3, r12}
-
-	/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
-	for future use.  r1 holds the original ulPortInterruptNesting value for
-	future use. */
-	LDR		r3, ulPortInterruptNestingConst
-	LDR		r1, [r3]
-	ADD		r0, r1, #1
-	STR		r0, [r3]
-
-	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
-	future use. */
-	MOV		r0, sp
-	AND		r2, r0, #4
-	SUB		sp, sp, r2
-
-	/* Call the interrupt handler. */
-	PUSH	{r0-r3, lr}
-	LDR		r1, vApplicationIRQHandlerConst
-	BLX		r1
-	POP		{r0-r3, lr}
-	ADD		sp, sp, r2
-
-	CPSID	i
-	DSB
-	ISB
-
-	/* Write to the EOI register. */
-	LDR 	r0, ulICCEOIRConst
-	LDR		r2, [r0]
-	STR		r0, [r2]
-
-	/* Restore the old nesting count. */
-	STR		r1, [r3]
-
-	/* A context switch is never performed if the nesting count is not 0. */
-	CMP		r1, #0
-	BNE		exit_without_switch
-
-	/* Did the interrupt request a context switch?  r1 holds the address of
-	ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
-	use. */
-	LDR		r1, ulPortYieldRequiredConst
-	LDR		r0, [r1]
-	CMP		r0, #0
-	BNE		switch_before_exit
-
-exit_without_switch:
-	/* No context switch.  Restore used registers, LR_irq and SPSR before
-	returning. */
-	POP		{r0-r3, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	MOVS	PC, LR
-
-switch_before_exit:
-	/* A context swtich is to be performed.  Clear the context switch pending
-	flag. */
-	MOV		r0, #0
-	STR		r0, [r1]
-
-	/* Restore used registers, LR-irq and SPSR before saving the context
-	to the task stack. */
-	POP		{r0-r3, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	portSAVE_CONTEXT
-
-	/* Call the function that selects the new task to execute.
-	vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
-	instructions, or 8 byte aligned stack allocated data.  LR does not need
-	saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
-	LDR		R0, vTaskSwitchContextConst
-	BLX		R0
-
-	/* Restore the context of, and branch to, the task selected to execute
-	next. */
-	portRESTORE_CONTEXT
-
-ulICCEOIRConst:	.word ulICCEOIR
-pxCurrentTCBConst: .word pxCurrentTCB
-ulCriticalNestingConst: .word ulCriticalNesting
-ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
-vTaskSwitchContextConst: .word vTaskSwitchContext
-vApplicationIRQHandlerConst: .word vApplicationIRQHandler
-ulPortInterruptNestingConst: .word ulPortInterruptNesting
-ulPortYieldRequiredConst: .word ulPortYieldRequired
-
-.end
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h b/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
deleted file mode 100755
index a4505b0..0000000
--- a/FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-	extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{												\
-extern volatile uint32_t ulPortYieldRequired;	\
-												\
-	if( xSwitchRequired != pdFALSE )			\
-	{											\
-		ulPortYieldRequired = pdTRUE;			\
-	}											\
-}
-
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SWI 0		\n"				\
-									 "ISB		  " ::: "memory" );
-
-
-/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-extern void vPortInstallFreeRTOSVectorTable( void );
-
-/* The I bit within the CPSR. */
-#define portINTERRUPT_ENABLE_BIT	( 1 << 7 )
-
-/* In the absence of a priority mask register, these functions and macros
-globally enable and disable interrupts. */
-#define portENTER_CRITICAL()		vPortEnterCritical();
-#define portEXIT_CRITICAL()			vPortExitCritical();
-#define portENABLE_INTERRUPTS()		__asm volatile ( "CPSIE i 	\n"	::: "memory" );
-#define portDISABLE_INTERRUPTS()	__asm volatile ( "CPSID i 	\n"		\
-													 "DSB		\n"		\
-													 "ISB		  " ::: "memory" );
-
-__attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
-{
-volatile uint32_t ulCPSR;
-
-	__asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) :: "memory" );
-	ulCPSR &= portINTERRUPT_ENABLE_BIT;
-	portDISABLE_INTERRUPTS();
-	return ulCPSR;
-}
-
-#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	if( x == 0 ) portENABLE_INTERRUPTS()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
-
-/* Prototype of the FreeRTOS tick handler.  This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
-void FreeRTOS_Tick_Handler( void );
-
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
-void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE __inline
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#ifdef __cplusplus
-	} /* extern C */
-#endif
-
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/ATMega323/port.c b/FreeRTOS/Source/portable/GCC/ATMega323/port.c
deleted file mode 100755
index 1d968f0..0000000
--- a/FreeRTOS/Source/portable/GCC/ATMega323/port.c
+++ /dev/null
@@ -1,426 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* 
-
-Changes from V2.6.0
-
-	+ AVR port - Replaced the inb() and outb() functions with direct memory
-	  access.  This allows the port to be built with the 20050414 build of
-	  WinAVR.
-*/
-
-#include 
-#include 
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the AVR port.
- *----------------------------------------------------------*/
-
-/* Start tasks with interrupts enables. */
-#define portFLAGS_INT_ENABLED					( ( StackType_t ) 0x80 )
-
-/* Hardware constants for timer 1. */
-#define portCLEAR_COUNTER_ON_MATCH				( ( uint8_t ) 0x08 )
-#define portPRESCALE_64							( ( uint8_t ) 0x03 )
-#define portCLOCK_PRESCALER						( ( uint32_t ) 64 )
-#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE	( ( uint8_t ) 0x10 )
-
-/*-----------------------------------------------------------*/
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
-
-/* 
- * Macro to save all the general purpose registers, the save the stack pointer
- * into the TCB.  
- * 
- * The first thing we do is save the flags then disable interrupts.  This is to 
- * guard our stack against having a context switch interrupt after we have already 
- * pushed the registers onto the stack - causing the 32 registers to be on the 
- * stack twice. 
- * 
- * r1 is set to zero as the compiler expects it to be thus, however some
- * of the math routines make use of R1. 
- * 
- * The interrupts will have been disabled during the call to portSAVE_CONTEXT()
- * so we need not worry about reading/writing to the stack pointer. 
- */
-
-#define portSAVE_CONTEXT()									\
-	asm volatile (	"push	r0						\n\t"	\
-					"in		r0, __SREG__			\n\t"	\
-					"cli							\n\t"	\
-					"push	r0						\n\t"	\
-					"push	r1						\n\t"	\
-					"clr	r1						\n\t"	\
-					"push	r2						\n\t"	\
-					"push	r3						\n\t"	\
-					"push	r4						\n\t"	\
-					"push	r5						\n\t"	\
-					"push	r6						\n\t"	\
-					"push	r7						\n\t"	\
-					"push	r8						\n\t"	\
-					"push	r9						\n\t"	\
-					"push	r10						\n\t"	\
-					"push	r11						\n\t"	\
-					"push	r12						\n\t"	\
-					"push	r13						\n\t"	\
-					"push	r14						\n\t"	\
-					"push	r15						\n\t"	\
-					"push	r16						\n\t"	\
-					"push	r17						\n\t"	\
-					"push	r18						\n\t"	\
-					"push	r19						\n\t"	\
-					"push	r20						\n\t"	\
-					"push	r21						\n\t"	\
-					"push	r22						\n\t"	\
-					"push	r23						\n\t"	\
-					"push	r24						\n\t"	\
-					"push	r25						\n\t"	\
-					"push	r26						\n\t"	\
-					"push	r27						\n\t"	\
-					"push	r28						\n\t"	\
-					"push	r29						\n\t"	\
-					"push	r30						\n\t"	\
-					"push	r31						\n\t"	\
-					"lds	r26, pxCurrentTCB		\n\t"	\
-					"lds	r27, pxCurrentTCB + 1	\n\t"	\
-					"in		r0, 0x3d				\n\t"	\
-					"st		x+, r0					\n\t"	\
-					"in		r0, 0x3e				\n\t"	\
-					"st		x+, r0					\n\t"	\
-				);
-
-/* 
- * Opposite to portSAVE_CONTEXT().  Interrupts will have been disabled during
- * the context save so we can write to the stack pointer. 
- */
-
-#define portRESTORE_CONTEXT()								\
-	asm volatile (	"lds	r26, pxCurrentTCB		\n\t"	\
-					"lds	r27, pxCurrentTCB + 1	\n\t"	\
-					"ld		r28, x+					\n\t"	\
-					"out	__SP_L__, r28			\n\t"	\
-					"ld		r29, x+					\n\t"	\
-					"out	__SP_H__, r29			\n\t"	\
-					"pop	r31						\n\t"	\
-					"pop	r30						\n\t"	\
-					"pop	r29						\n\t"	\
-					"pop	r28						\n\t"	\
-					"pop	r27						\n\t"	\
-					"pop	r26						\n\t"	\
-					"pop	r25						\n\t"	\
-					"pop	r24						\n\t"	\
-					"pop	r23						\n\t"	\
-					"pop	r22						\n\t"	\
-					"pop	r21						\n\t"	\
-					"pop	r20						\n\t"	\
-					"pop	r19						\n\t"	\
-					"pop	r18						\n\t"	\
-					"pop	r17						\n\t"	\
-					"pop	r16						\n\t"	\
-					"pop	r15						\n\t"	\
-					"pop	r14						\n\t"	\
-					"pop	r13						\n\t"	\
-					"pop	r12						\n\t"	\
-					"pop	r11						\n\t"	\
-					"pop	r10						\n\t"	\
-					"pop	r9						\n\t"	\
-					"pop	r8						\n\t"	\
-					"pop	r7						\n\t"	\
-					"pop	r6						\n\t"	\
-					"pop	r5						\n\t"	\
-					"pop	r4						\n\t"	\
-					"pop	r3						\n\t"	\
-					"pop	r2						\n\t"	\
-					"pop	r1						\n\t"	\
-					"pop	r0						\n\t"	\
-					"out	__SREG__, r0			\n\t"	\
-					"pop	r0						\n\t"	\
-				);
-
-/*-----------------------------------------------------------*/
-
-/*
- * Perform hardware setup to enable ticks from timer 1, compare match A.
- */
-static void prvSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-/* 
- * See header file for description. 
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint16_t usAddress;
-
-	/* Place a few bytes of known values on the bottom of the stack. 
-	This is just useful for debugging. */
-
-	*pxTopOfStack = 0x11;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x22;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x33;
-	pxTopOfStack--;
-
-	/* Simulate how the stack would look after a call to vPortYield() generated by 
-	the compiler. */
-
-	/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
-
-	/* The start of the task code will be popped off the stack last, so place
-	it on first. */
-	usAddress = ( uint16_t ) pxCode;
-	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
-	pxTopOfStack--;
-
-	usAddress >>= 8;
-	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
-	pxTopOfStack--;
-
-	/* Next simulate the stack as if after a call to portSAVE_CONTEXT().  
-	portSAVE_CONTEXT places the flags on the stack immediately after r0
-	to ensure the interrupts get disabled as soon as possible, and so ensuring
-	the stack use is minimal should a context switch interrupt occur. */
-	*pxTopOfStack = ( StackType_t ) 0x00;	/* R0 */
-	pxTopOfStack--;
-	*pxTopOfStack = portFLAGS_INT_ENABLED;
-	pxTopOfStack--;
-
-
-	/* Now the remaining registers.   The compiler expects R1 to be 0. */
-	*pxTopOfStack = ( StackType_t ) 0x00;	/* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x02;	/* R2 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x05;	/* R5 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x06;	/* R6 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x07;	/* R7 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x08;	/* R8 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x09;	/* R9 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x10;	/* R10 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x11;	/* R11 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12;	/* R12 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x13;	/* R13 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x14;	/* R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x15;	/* R15 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x16;	/* R16 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x17;	/* R17 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x18;	/* R18 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x19;	/* R19 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x20;	/* R20 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x21;	/* R21 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x22;	/* R22 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x23;	/* R23 */
-	pxTopOfStack--;
-
-	/* Place the parameter on the stack in the expected location. */
-	usAddress = ( uint16_t ) pvParameters;
-	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
-	pxTopOfStack--;
-
-	usAddress >>= 8;
-	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0x26;	/* R26 X */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x27;	/* R27 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x28;	/* R28 Y */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x29;	/* R29 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x30;	/* R30 Z */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x031;	/* R31 */
-	pxTopOfStack--;
-
-	/*lint +e950 +e611 +e923 */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Setup the hardware to generate the tick. */
-	prvSetupTimerInterrupt();
-
-	/* Restore the context of the first task that is going to run. */
-	portRESTORE_CONTEXT();
-
-	/* Simulate a function call end as generated by the compiler.  We will now
-	jump to the start of the task the context of which we have just restored. */
-	asm volatile ( "ret" );
-
-	/* Should not get here. */
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the AVR port will get stopped.  If required simply
-	disable the tick interrupt here. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch.  The first thing we do is save the registers so we
- * can use a naked attribute.
- */
-void vPortYield( void ) __attribute__ ( ( naked ) );
-void vPortYield( void )
-{
-	portSAVE_CONTEXT();
-	vTaskSwitchContext();
-	portRESTORE_CONTEXT();
-
-	asm volatile ( "ret" );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Context switch function used by the tick.  This must be identical to 
- * vPortYield() from the call to vTaskSwitchContext() onwards.  The only
- * difference from vPortYield() is the tick count is incremented as the
- * call comes from the tick ISR.
- */
-void vPortYieldFromTick( void ) __attribute__ ( ( naked ) );
-void vPortYieldFromTick( void )
-{
-	portSAVE_CONTEXT();
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		vTaskSwitchContext();
-	}
-	portRESTORE_CONTEXT();
-
-	asm volatile ( "ret" );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup timer 1 compare match A to generate a tick interrupt.
- */
-static void prvSetupTimerInterrupt( void )
-{
-uint32_t ulCompareMatch;
-uint8_t ucHighByte, ucLowByte;
-
-	/* Using 16bit timer 1 to generate the tick.  Correct fuses must be
-	selected for the configCPU_CLOCK_HZ clock. */
-
-	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-
-	/* We only have 16 bits so have to scale to get our required tick rate. */
-	ulCompareMatch /= portCLOCK_PRESCALER;
-
-	/* Adjust for correct value. */
-	ulCompareMatch -= ( uint32_t ) 1;
-
-	/* Setup compare match value for compare match A.  Interrupts are disabled 
-	before this is called so we need not worry here. */
-	ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
-	ulCompareMatch >>= 8;
-	ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
-	OCR1AH = ucHighByte;
-	OCR1AL = ucLowByte;
-
-	/* Setup clock source and compare match behaviour. */
-	ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
-	TCCR1B = ucLowByte;
-
-	/* Enable the interrupt - this is okay as interrupt are currently globally
-	disabled. */
-	ucLowByte = TIMSK;
-	ucLowByte |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
-	TIMSK = ucLowByte;
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_PREEMPTION == 1
-
-	/*
-	 * Tick ISR for preemptive scheduler.  We can use a naked attribute as
-	 * the context is saved at the start of vPortYieldFromTick().  The tick
-	 * count is incremented after the context is saved.
-	 */
-	void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal, naked ) );
-	void SIG_OUTPUT_COMPARE1A( void )
-	{
-		vPortYieldFromTick();
-		asm volatile ( "reti" );
-	}
-#else
-
-	/*
-	 * Tick ISR for the cooperative scheduler.  All this does is increment the
-	 * tick count.  We don't need to switch context, this can only be done by
-	 * manual calls to taskYIELD();
-	 */
-	void SIG_OUTPUT_COMPARE1A( void ) __attribute__ ( ( signal ) );
-	void SIG_OUTPUT_COMPARE1A( void )
-	{
-		xTaskIncrementTick();
-	}
-#endif
-
-
-	
diff --git a/FreeRTOS/Source/portable/GCC/ATMega323/portmacro.h b/FreeRTOS/Source/portable/GCC/ATMega323/portmacro.h
deleted file mode 100755
index 998f24c..0000000
--- a/FreeRTOS/Source/portable/GCC/ATMega323/portmacro.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-Changes from V1.2.3
-
-	+ portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
-	  base 16.
-*/
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		int
-#define portSTACK_TYPE	uint8_t
-#define portBASE_TYPE	char
-
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-#define portENTER_CRITICAL()		asm volatile ( "in		__tmp_reg__, __SREG__" :: );	\
-									asm volatile ( "cli" :: );								\
-									asm volatile ( "push	__tmp_reg__" :: )
-
-#define portEXIT_CRITICAL()			asm volatile ( "pop		__tmp_reg__" :: );				\
-									asm volatile ( "out		__SREG__, __tmp_reg__" :: )
-
-#define portDISABLE_INTERRUPTS()	asm volatile ( "cli" :: );
-#define portENABLE_INTERRUPTS()		asm volatile ( "sei" :: );
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			1
-#define portNOP()					asm volatile ( "nop" );
-/*-----------------------------------------------------------*/
-
-/* Kernel utilities. */
-extern void vPortYield( void ) __attribute__ ( ( naked ) );
-#define portYIELD()					vPortYield()
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/AVR32_UC3/exception.S b/FreeRTOS/Source/portable/GCC/AVR32_UC3/exception.S
deleted file mode 100755
index 5ba76a5..0000000
--- a/FreeRTOS/Source/portable/GCC/AVR32_UC3/exception.S
+++ /dev/null
@@ -1,297 +0,0 @@
-/*This file is prepared for Doxygen automatic documentation generation.*/
-/*! \file *********************************************************************
- *
- * \brief Exception and interrupt vectors.
- *
- * This file maps all events supported by an AVR32UC.
- *
- * - Compiler:           GNU GCC for AVR32
- * - Supported devices:  All AVR32UC devices with an INTC module can be used.
- * - AppNote:
- *
- * \author               Atmel Corporation: http://www.atmel.com \n
- *                       Support and FAQ: http://support.atmel.no/
- *
- ******************************************************************************/
-
-/* Copyright (c) 2007, Atmel Corporation All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of ATMEL may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
- * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include 
-#include "intc.h"
-
-
-//! @{
-//! \verbatim
-
-
-  .section  .exception, "ax", @progbits
-
-
-// Start of Exception Vector Table.
-
-  // EVBA must be aligned with a power of two strictly greater than the EVBA-
-  // relative offset of the last vector.
-  .balign 0x200
-
-  // Export symbol.
-  .global _evba
-  .type _evba, @function
-_evba:
-
-        .org  0x000
-        // Unrecoverable Exception.
-_handle_Unrecoverable_Exception:
-        rjmp $
-
-        .org  0x004
-        // TLB Multiple Hit: UNUSED IN AVR32UC.
-_handle_TLB_Multiple_Hit:
-        rjmp $
-
-        .org  0x008
-        // Bus Error Data Fetch.
-_handle_Bus_Error_Data_Fetch:
-        rjmp $
-
-        .org  0x00C
-         // Bus Error Instruction Fetch.
-_handle_Bus_Error_Instruction_Fetch:
-        rjmp $
-
-        .org  0x010
-        // NMI.
-_handle_NMI:
-        rjmp $
-
-        .org  0x014
-        // Instruction Address.
-_handle_Instruction_Address:
-        rjmp $
-
-        .org  0x018
-        // ITLB Protection.
-_handle_ITLB_Protection:
-        rjmp $
-
-        .org  0x01C
-        // Breakpoint.
-_handle_Breakpoint:
-        rjmp $
-
-        .org  0x020
-        // Illegal Opcode.
-_handle_Illegal_Opcode:
-        rjmp $
-
-        .org  0x024
-        // Unimplemented Instruction.
-_handle_Unimplemented_Instruction:
-        rjmp $
-
-        .org  0x028
-        // Privilege Violation.
-_handle_Privilege_Violation:
-        rjmp $
-
-        .org  0x02C
-        // Floating-Point: UNUSED IN AVR32UC.
-_handle_Floating_Point:
-        rjmp $
-
-        .org  0x030
-        // Coprocessor Absent: UNUSED IN AVR32UC.
-_handle_Coprocessor_Absent:
-        rjmp $
-
-        .org  0x034
-        // Data Address (Read).
-_handle_Data_Address_Read:
-        rjmp $
-
-        .org  0x038
-        // Data Address (Write).
-_handle_Data_Address_Write:
-        rjmp $
-
-        .org  0x03C
-        // DTLB Protection (Read).
-_handle_DTLB_Protection_Read:
-        rjmp $
-
-        .org  0x040
-        // DTLB Protection (Write).
-_handle_DTLB_Protection_Write:
-        rjmp $
-
-        .org  0x044
-        // DTLB Modified: UNUSED IN AVR32UC.
-_handle_DTLB_Modified:
-        rjmp $
-
-        .org  0x050
-        // ITLB Miss: UNUSED IN AVR32UC.
-_handle_ITLB_Miss:
-        rjmp $
-
-        .org  0x060
-        // DTLB Miss (Read): UNUSED IN AVR32UC.
-_handle_DTLB_Miss_Read:
-        rjmp $
-
-        .org  0x070
-        // DTLB Miss (Write): UNUSED IN AVR32UC.
-_handle_DTLB_Miss_Write:
-        rjmp $
-
-        .org  0x100
-        // Supervisor Call.
-_handle_Supervisor_Call:
-        lda.w   pc, SCALLYield
-
-
-// Interrupt support.
-// The interrupt controller must provide the offset address relative to EVBA.
-// Important note:
-//   All interrupts call a C function named _get_interrupt_handler.
-//   This function will read group and interrupt line number to then return in
-//   R12 a pointer to a user-provided interrupt handler.
-
-  .balign 4
-
-_int0:
-  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
-  // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
-  mfsr    r12, AVR32_SR
-  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
-  cp.w    r12, 0b110
-  brlo    _int0_normal
-  lddsp   r12, sp[0 * 4]
-  stdsp   sp[6 * 4], r12
-  lddsp   r12, sp[1 * 4]
-  stdsp   sp[7 * 4], r12
-  lddsp   r12, sp[3 * 4]
-  sub     sp, -6 * 4
-  rete
-_int0_normal:
-#endif
-  mov     r12, 0  // Pass the int_lev parameter to the _get_interrupt_handler function.
-  call    _get_interrupt_handler
-  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
-  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
-  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-_int1:
-  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
-  // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
-  mfsr    r12, AVR32_SR
-  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
-  cp.w    r12, 0b110
-  brlo    _int1_normal
-  lddsp   r12, sp[0 * 4]
-  stdsp   sp[6 * 4], r12
-  lddsp   r12, sp[1 * 4]
-  stdsp   sp[7 * 4], r12
-  lddsp   r12, sp[3 * 4]
-  sub     sp, -6 * 4
-  rete
-_int1_normal:
-#endif
-  mov     r12, 1  // Pass the int_lev parameter to the _get_interrupt_handler function.
-  call    _get_interrupt_handler
-  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
-  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
-  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-_int2:
-  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
-  // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
-  mfsr    r12, AVR32_SR
-  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
-  cp.w    r12, 0b110
-  brlo    _int2_normal
-  lddsp   r12, sp[0 * 4]
-  stdsp   sp[6 * 4], r12
-  lddsp   r12, sp[1 * 4]
-  stdsp   sp[7 * 4], r12
-  lddsp   r12, sp[3 * 4]
-  sub     sp, -6 * 4
-  rete
-_int2_normal:
-#endif
-  mov     r12, 2  // Pass the int_lev parameter to the _get_interrupt_handler function.
-  call    _get_interrupt_handler
-  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
-  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
-  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-_int3:
-  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
-  // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
-  mfsr    r12, AVR32_SR
-  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
-  cp.w    r12, 0b110
-  brlo    _int3_normal
-  lddsp   r12, sp[0 * 4]
-  stdsp   sp[6 * 4], r12
-  lddsp   r12, sp[1 * 4]
-  stdsp   sp[7 * 4], r12
-  lddsp   r12, sp[3 * 4]
-  sub     sp, -6 * 4
-  rete
-_int3_normal:
-#endif
-  mov     r12, 3  // Pass the int_lev parameter to the _get_interrupt_handler function.
-  call    _get_interrupt_handler
-  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
-  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
-  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-
-// Constant data area.
-
-  .balign 4
-
-  // Values to store in the interrupt priority registers for the various interrupt priority levels.
-  // The interrupt priority registers contain the interrupt priority level and
-  // the EVBA-relative interrupt vector offset.
-  .global ipr_val
-  .type ipr_val, @object
-ipr_val:
-  .word (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
-        (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
-        (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
-        (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
-
-
-//! \endverbatim
-//! @}
diff --git a/FreeRTOS/Source/portable/GCC/AVR32_UC3/port.c b/FreeRTOS/Source/portable/GCC/AVR32_UC3/port.c
deleted file mode 100755
index 4f00e4c..0000000
--- a/FreeRTOS/Source/portable/GCC/AVR32_UC3/port.c
+++ /dev/null
@@ -1,435 +0,0 @@
-/*This file has been prepared for Doxygen automatic documentation generation.*/
-/*! \file *********************************************************************
- *
- * \brief FreeRTOS port source for AVR32 UC3.
- *
- * - Compiler:           GNU GCC for AVR32
- * - Supported devices:  All AVR32 devices can be used.
- * - AppNote:
- *
- * \author               Atmel Corporation: http://www.atmel.com \n
- *                       Support and FAQ: http://support.atmel.no/
- *
- *****************************************************************************/
-
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/* Standard includes. */
-#include 
-#include 
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* AVR32 UC3 includes. */
-#include 
-#include "gpio.h"
-#if( configTICK_USE_TC==1 )
-	#include "tc.h"
-#endif
-
-
-/* Constants required to setup the task context. */
-#define portINITIAL_SR            ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
-#define portINSTRUCTION_SIZE      ( ( StackType_t ) 0 )
-
-/* Each task maintains its own critical nesting variable. */
-#define portNO_CRITICAL_NESTING   ( ( uint32_t ) 0 )
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-#if( configTICK_USE_TC==0 )
-	static void prvScheduleNextTick( void );
-#else
-	static void prvClearTcInt( void );
-#endif
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Low-level initialization routine called during startup, before the main
- * function.
- * This version comes in replacement to the default one provided by Newlib.
- * Newlib's _init_startup only calls init_exceptions, but Newlib's exception
- * vectors are not compatible with the SCALL management in the current FreeRTOS
- * port. More low-level initializations are besides added here.
- */
-void _init_startup(void)
-{
-	/* Import the Exception Vector Base Address. */
-	extern void _evba;
-
-	#if configHEAP_INIT
-		extern void __heap_start__;
-		extern void __heap_end__;
-		BaseType_t *pxMem;
-	#endif
-
-	/* Load the Exception Vector Base Address in the corresponding system register. */
-	Set_system_register( AVR32_EVBA, ( int ) &_evba );
-
-	/* Enable exceptions. */
-	ENABLE_ALL_EXCEPTIONS();
-
-	/* Initialize interrupt handling. */
-	INTC_init_interrupts();
-
-	#if configHEAP_INIT
-
-		/* Initialize the heap used by malloc. */
-		for( pxMem = &__heap_start__; pxMem < ( BaseType_t * )&__heap_end__; )
-		{
-			*pxMem++ = 0xA5A5A5A5;
-		}
-
-	#endif
-
-	/* Give the used CPU clock frequency to Newlib, so it can work properly. */
-	set_cpu_hz( configCPU_CLOCK_HZ );
-
-	/* Code section present if and only if the debug trace is activated. */
-	#if configDBG
-	{
-		static const gpio_map_t DBG_USART_GPIO_MAP =
-		{
-			{ configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
-			{ configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
-		};
-
-		/* Initialize the USART used for the debug trace with the configured parameters. */
-		set_usart_base( ( void * ) configDBG_USART );
-		gpio_enable_module( DBG_USART_GPIO_MAP,
-		                    sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
-		usart_init( configDBG_USART_BAUDRATE );
-	}
-	#endif
-}
-/*-----------------------------------------------------------*/
-
-/*
- * malloc, realloc and free are meant to be called through respectively
- * pvPortMalloc, pvPortRealloc and vPortFree.
- * The latter functions call the former ones from within sections where tasks
- * are suspended, so the latter functions are task-safe. __malloc_lock and
- * __malloc_unlock use the same mechanism to also keep the former functions
- * task-safe as they may be called directly from Newlib's functions.
- * However, all these functions are interrupt-unsafe and SHALL THEREFORE NOT BE
- * CALLED FROM WITHIN AN INTERRUPT, because __malloc_lock and __malloc_unlock do
- * not call portENTER_CRITICAL and portEXIT_CRITICAL in order not to disable
- * interrupts during memory allocation management as this may be a very time-
- * consuming process.
- */
-
-/*
- * Lock routine called by Newlib on malloc / realloc / free entry to guarantee a
- * safe section as memory allocation management uses global data.
- * See the aforementioned details.
- */
-void __malloc_lock(struct _reent *ptr)
-{
-	vTaskSuspendAll();
-}
-
-/*
- * Unlock routine called by Newlib on malloc / realloc / free exit to guarantee
- * a safe section as memory allocation management uses global data.
- * See the aforementioned details.
- */
-void __malloc_unlock(struct _reent *ptr)
-{
-	xTaskResumeAll();
-}
-/*-----------------------------------------------------------*/
-
-/* Added as there is no such function in FreeRTOS. */
-void *pvPortRealloc( void *pv, size_t xWantedSize )
-{
-void *pvReturn;
-
-	vTaskSuspendAll();
-	{
-		pvReturn = realloc( pv, xWantedSize );
-	}
-	xTaskResumeAll();
-
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-/* The cooperative scheduler requires a normal IRQ service routine to
-simply increment the system tick. */
-/* The preemptive scheduler is defined as "naked" as the full context is saved
-on entry as part of the context switch. */
-__attribute__((__naked__)) static void vTick( void )
-{
-	/* Save the context of the interrupted task. */
-	portSAVE_CONTEXT_OS_INT();
-
-	#if( configTICK_USE_TC==1 )
-		/* Clear the interrupt flag. */
-		prvClearTcInt();
-	#else
-		/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
-		clock cycles from now. */
-		prvScheduleNextTick();
-	#endif
-
-	/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
-	calls in a critical section . */
-	portENTER_CRITICAL();
-		xTaskIncrementTick();
-	portEXIT_CRITICAL();
-
-	/* Restore the context of the "elected task". */
-	portRESTORE_CONTEXT_OS_INT();
-}
-/*-----------------------------------------------------------*/
-
-__attribute__((__naked__)) void SCALLYield( void )
-{
-	/* Save the context of the interrupted task. */
-	portSAVE_CONTEXT_SCALL();
-	vTaskSwitchContext();
-	portRESTORE_CONTEXT_SCALL();
-}
-/*-----------------------------------------------------------*/
-
-/* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels.  The interrupt flags can therefore not always
-be saved to the stack.  Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
-__attribute__((__noinline__)) void vPortEnterCritical( void )
-{
-	/* Disable interrupts */
-	portDISABLE_INTERRUPTS();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	 directly.  Increment ulCriticalNesting to keep a count of how many times
-	 portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-__attribute__((__noinline__)) void vPortExitCritical( void )
-{
-	if(ulCriticalNesting > portNO_CRITICAL_NESTING)
-	{
-		ulCriticalNesting--;
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Enable all interrupt/exception. */
-			portENABLE_INTERRUPTS();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* When the task starts, it will expect to find the function parameter in R12. */
-	pxTopOfStack--;
-	*pxTopOfStack-- = ( StackType_t ) 0x08080808;					/* R8 */
-	*pxTopOfStack-- = ( StackType_t ) 0x09090909;					/* R9 */
-	*pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A;					/* R10 */
-	*pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B;					/* R11 */
-	*pxTopOfStack-- = ( StackType_t ) pvParameters;					/* R12 */
-	*pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF;					/* R14/LR */
-	*pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
-	*pxTopOfStack-- = ( StackType_t ) portINITIAL_SR;				/* SR */
-	*pxTopOfStack-- = ( StackType_t ) 0xFF0000FF;					/* R0 */
-	*pxTopOfStack-- = ( StackType_t ) 0x01010101;					/* R1 */
-	*pxTopOfStack-- = ( StackType_t ) 0x02020202;					/* R2 */
-	*pxTopOfStack-- = ( StackType_t ) 0x03030303;					/* R3 */
-	*pxTopOfStack-- = ( StackType_t ) 0x04040404;					/* R4 */
-	*pxTopOfStack-- = ( StackType_t ) 0x05050505;					/* R5 */
-	*pxTopOfStack-- = ( StackType_t ) 0x06060606;					/* R6 */
-	*pxTopOfStack-- = ( StackType_t ) 0x07070707;					/* R7 */
-	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;			/* ulCriticalNesting */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task. */
-	portRESTORE_CONTEXT();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the AVR32 port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
-clock cycles from now. */
-#if( configTICK_USE_TC==0 )
-	static void prvScheduleFirstTick(void)
-	{
-		uint32_t lCycles;
-
-		lCycles = Get_system_register(AVR32_COUNT);
-		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
-		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
-		// generation feature does not get disabled.
-		if(0 == lCycles)
-		{
-			lCycles++;
-		}
-		Set_system_register(AVR32_COMPARE, lCycles);
-	}
-	
-	__attribute__((__noinline__)) static void prvScheduleNextTick(void)
-	{
-		uint32_t lCycles, lCount;
-
-		lCycles = Get_system_register(AVR32_COMPARE);
-		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
-		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
-		// generation feature does not get disabled.
-		if(0 == lCycles)
-		{
-			lCycles++;
-		}
-		lCount = Get_system_register(AVR32_COUNT);
-		if( lCycles < lCount )
-		{		// We missed a tick, recover for the next.
-			lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
-		}
-		Set_system_register(AVR32_COMPARE, lCycles);
-	}
-#else
-	__attribute__((__noinline__)) static void prvClearTcInt(void)
-	{
-		AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt(void)
-{
-#if( configTICK_USE_TC==1 )
-
-	volatile avr32_tc_t *tc = &AVR32_TC;
-
-	// Options for waveform genration.
-	tc_waveform_opt_t waveform_opt =
-	{
-	.channel  = configTICK_TC_CHANNEL,             /* Channel selection. */
-
-	.bswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOB. */
-	.beevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOB. */
-	.bcpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOB. */
-	.bcpb     = TC_EVT_EFFECT_NOOP,                /* RB compare effect on TIOB. */
-
-	.aswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOA. */
-	.aeevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOA. */
-	.acpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOA: toggle. */
-	.acpa     = TC_EVT_EFFECT_NOOP,                /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
-
-	.wavsel   = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
-	.enetrg   = FALSE,                             /* External event trigger enable. */
-	.eevt     = 0,                                 /* External event selection. */
-	.eevtedg  = TC_SEL_NO_EDGE,                    /* External event edge selection. */
-	.cpcdis   = FALSE,                             /* Counter disable when RC compare. */
-	.cpcstop  = FALSE,                             /* Counter clock stopped with RC compare. */
-
-	.burst    = FALSE,                             /* Burst signal selection. */
-	.clki     = FALSE,                             /* Clock inversion. */
-	.tcclks   = TC_CLOCK_SOURCE_TC2                /* Internal source clock 2. */
-	};
-
-	tc_interrupt_t tc_interrupt =
-	{
-		.etrgs=0,
-		.ldrbs=0,
-		.ldras=0,
-		.cpcs =1,
-		.cpbs =0,
-		.cpas =0,
-		.lovrs=0,
-		.covfs=0,
-	};
-
-#endif
-
-	/* Disable all interrupt/exception. */
-	portDISABLE_INTERRUPTS();
-
-	/* Register the compare interrupt handler to the interrupt controller and
-	enable the compare interrupt. */
-
-	#if( configTICK_USE_TC==1 )
-	{
-		INTC_register_interrupt(&vTick, configTICK_TC_IRQ, INT0);
-
-		/* Initialize the timer/counter. */
-		tc_init_waveform(tc, &waveform_opt);
-
-		/* Set the compare triggers.
-		Remember TC counter is 16-bits, so counting second is not possible!
-		That's why we configure it to count ms. */
-		tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
-
-		tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
-
-		/* Start the timer/counter. */
-		tc_start(tc, configTICK_TC_CHANNEL);
-	}
-	#else
-	{
-		INTC_register_interrupt(&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
-		prvScheduleFirstTick();
-	}
-	#endif
-}
diff --git a/FreeRTOS/Source/portable/GCC/AVR32_UC3/portmacro.h b/FreeRTOS/Source/portable/GCC/AVR32_UC3/portmacro.h
deleted file mode 100755
index 7fb10ed..0000000
--- a/FreeRTOS/Source/portable/GCC/AVR32_UC3/portmacro.h
+++ /dev/null
@@ -1,667 +0,0 @@
-/*This file has been prepared for Doxygen automatic documentation generation.*/
-/*! \file *********************************************************************
- *
- * \brief FreeRTOS port source for AVR32 UC3.
- *
- * - Compiler:           GNU GCC for AVR32
- * - Supported devices:  All AVR32 devices can be used.
- * - AppNote:
- *
- * \author               Atmel Corporation: http://www.atmel.com \n
- *                       Support and FAQ: http://support.atmel.no/
- *
- *****************************************************************************/
-
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-#include 
-#include "intc.h"
-#include "compiler.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#define TASK_DELAY_MS(x)   ( (x)        /portTICK_PERIOD_MS )
-#define TASK_DELAY_S(x)    ( (x)*1000   /portTICK_PERIOD_MS )
-#define TASK_DELAY_MIN(x)  ( (x)*60*1000/portTICK_PERIOD_MS )
-
-#define configTICK_TC_IRQ             ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT    4
-#define portNOP()             {__asm__ __volatile__ ("nop");}
-/*-----------------------------------------------------------*/
-
-
-/*-----------------------------------------------------------*/
-
-/* INTC-specific. */
-#define DISABLE_ALL_EXCEPTIONS()    Disable_global_exception()
-#define ENABLE_ALL_EXCEPTIONS()     Enable_global_exception()
-
-#define DISABLE_ALL_INTERRUPTS()    Disable_global_interrupt()
-#define ENABLE_ALL_INTERRUPTS()     Enable_global_interrupt()
-
-#define DISABLE_INT_LEVEL(int_lev)  Disable_interrupt_level(int_lev)
-#define ENABLE_INT_LEVEL(int_lev)   Enable_interrupt_level(int_lev)
-
-
-/*
- * Debug trace.
- * Activated if and only if configDBG is nonzero.
- * Prints a formatted string to stdout.
- * The current source file name and line number are output with a colon before
- * the formatted string.
- * A carriage return and a linefeed are appended to the output.
- * stdout is redirected to the USART configured by configDBG_USART.
- * The parameters are the same as for the standard printf function.
- * There is no return value.
- * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
- * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
- */
-#if configDBG
-#define portDBG_TRACE(...) \
-{\
-  fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);\
-  printf(__VA_ARGS__);\
-  fputs("\r\n", stdout);\
-}
-#else
-#define portDBG_TRACE(...)
-#endif
-
-
-/* Critical section management. */
-#define portDISABLE_INTERRUPTS()  DISABLE_ALL_INTERRUPTS()
-#define portENABLE_INTERRUPTS()   ENABLE_ALL_INTERRUPTS()
-
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL()      vPortEnterCritical();
-#define portEXIT_CRITICAL()       vPortExitCritical();
-
-
-/* Added as there is no such function in FreeRTOS. */
-extern void *pvPortRealloc( void *pv, size_t xSize );
-/*-----------------------------------------------------------*/
-
-
-/*=============================================================================================*/
-
-/*
- * Restore Context for cases other than INTi.
- */
-#define portRESTORE_CONTEXT()															\
-{																						\
-  extern volatile uint32_t ulCriticalNesting;									\
-  extern volatile void *volatile pxCurrentTCB;											\
-																						\
-  __asm__ __volatile__ (																\
-    /* Set SP to point to new stack */													\
-    "mov     r8, LO(%[pxCurrentTCB])													\n\t"\
-    "orh     r8, HI(%[pxCurrentTCB])													\n\t"\
-    "ld.w    r0, r8[0]																	\n\t"\
-    "ld.w    sp, r0[0]																	\n\t"\
-																						\
-    /* Restore ulCriticalNesting variable */											\
-    "ld.w    r0, sp++																	\n\t"\
-    "mov     r8, LO(%[ulCriticalNesting])												\n\t"\
-    "orh     r8, HI(%[ulCriticalNesting])												\n\t"\
-    "st.w    r8[0], r0																	\n\t"\
-																						\
-    /* Restore R0..R7 */																\
-    "ldm     sp++, r0-r7																\n\t"\
-    /* R0-R7 should not be used below this line */										\
-    /* Skip PC and SR (will do it at the end) */										\
-    "sub     sp, -2*4																	\n\t"\
-    /* Restore R8..R12 and LR */														\
-    "ldm     sp++, r8-r12, lr															\n\t"\
-    /* Restore SR */																	\
-    "ld.w    r0, sp[-8*4]\n\t" /* R0 is modified, is restored later. */					\
-    "mtsr    %[SR], r0																	\n\t"\
-    /* Restore r0 */																	\
-    "ld.w    r0, sp[-9*4]																\n\t"\
-    /* Restore PC */																	\
-    "ld.w    pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */		\
-    :																					\
-    : [ulCriticalNesting] "i" (&ulCriticalNesting),										\
-      [pxCurrentTCB] "i" (&pxCurrentTCB),												\
-      [SR] "i" (AVR32_SR)																\
-  );																					\
-}
-
-
-/*
- * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
- * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
- *
- * Had to make different versions because registers saved on the system stack
- * are not the same between INT0..3 exceptions and the scall exception.
- */
-
-// Task context stack layout:
-  // R8  (*)
-  // R9  (*)
-  // R10 (*)
-  // R11 (*)
-  // R12 (*)
-  // R14/LR (*)
-  // R15/PC (*)
-  // SR (*)
-  // R0
-  // R1
-  // R2
-  // R3
-  // R4
-  // R5
-  // R6
-  // R7
-  // ulCriticalNesting
-// (*) automatically done for INT0..INT3, but not for SCALL
-
-/*
- * The ISR used for the scheduler tick depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-#if configUSE_PREEMPTION == 0
-
-/*
- * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
- */
-#define portSAVE_CONTEXT_OS_INT()														\
-{																						\
-  /* Save R0..R7 */																		\
-  __asm__ __volatile__ ("stm     --sp, r0-r7");											\
-																						\
-  /* With the cooperative scheduler, as there is no context switch by interrupt, */		\
-  /* there is also no context save. */													\
-}
-
-/*
- * portRESTORE_CONTEXT_OS_INT() for Tick exception.
- */
-#define portRESTORE_CONTEXT_OS_INT()													\
-{																						\
-  __asm__ __volatile__ (																\
-    /* Restore R0..R7 */																\
-    "ldm     sp++, r0-r7\n\t"															\
-																						\
-    /* With the cooperative scheduler, as there is no context switch by interrupt, */	\
-    /* there is also no context restore. */												\
-    "rete"																				\
-  );																					\
-}
-
-#else
-
-/*
- * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
- */
-#define portSAVE_CONTEXT_OS_INT()																	\
-{																									\
-  extern volatile uint32_t ulCriticalNesting;												\
-  extern volatile void *volatile pxCurrentTCB;														\
-																									\
-  /* When we come here */																			\
-  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */					\
-																									\
-  __asm__ __volatile__ (																			\
-    /* Save R0..R7 */																				\
-    "stm     --sp, r0-r7																			\n\t"\
-																									\
-    /* Save ulCriticalNesting variable  - R0 is overwritten */										\
-    "mov     r8, LO(%[ulCriticalNesting])\n\t"														\
-    "orh     r8, HI(%[ulCriticalNesting])\n\t"														\
-    "ld.w    r0, r8[0]																				\n\t"\
-    "st.w    --sp, r0																				\n\t"\
-																									\
-    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
-    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
-    /* level and allow other lower interrupt level to occur). */									\
-    /* In this case we don't want to do a task switch because we don't know what the stack */		\
-    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
-    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
-    /* will just be restoring the interrupt handler, no way!!! */									\
-    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
-    "ld.w    r0, sp[9*4]\n\t" /* Read SR in stack */												\
-    "bfextu  r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */									\
-    "cp.w    r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */						\
-    "brhi    LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]													\n\t"\
-																									\
-    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */					\
-    /* NOTE: we don't enter a critical section here because all interrupt handlers */				\
-    /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */							\
-    /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */			\
-    /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */		\
-    "mov     r8, LO(%[pxCurrentTCB])\n\t"															\
-    "orh     r8, HI(%[pxCurrentTCB])\n\t"															\
-    "ld.w    r0, r8[0]\n\t"																			\
-    "st.w    r0[0], sp\n"																			\
-																									\
-    "LABEL_INT_SKIP_SAVE_CONTEXT_%[LINE]:"															\
-    :																								\
-    : [ulCriticalNesting] "i" (&ulCriticalNesting),													\
-      [pxCurrentTCB] "i" (&pxCurrentTCB),															\
-      [LINE] "i" (__LINE__)																			\
-  );																								\
-}
-
-/*
- * portRESTORE_CONTEXT_OS_INT() for Tick exception.
- */
-#define portRESTORE_CONTEXT_OS_INT()																\
-{																									\
-  extern volatile uint32_t ulCriticalNesting;												\
-  extern volatile void *volatile pxCurrentTCB;														\
-																									\
-  /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */		\
-  /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
-  /* level and allow other lower interrupt level to occur). */										\
-  /* In this case we don't want to do a task switch because we don't know what the stack */			\
-  /* currently looks like (we don't know what the interrupted interrupt handler was doing). */		\
-  /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */			\
-  /* will just be restoring the interrupt handler, no way!!! */										\
-  __asm__ __volatile__ (																			\
-    "ld.w    r0, sp[9*4]\n\t" /* Read SR in stack */												\
-    "bfextu  r0, r0, 22, 3\n\t" /* Extract the mode bits to R0. */									\
-    "cp.w    r0, 1\n\t" /* Compare the mode bits with supervisor mode(b'001) */						\
-    "brhi    LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]"												\
-    :																								\
-    : [LINE] "i" (__LINE__)																			\
-  );																								\
-																									\
-  /* Else */																						\
-  /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */		\
-  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
-  portENTER_CRITICAL();																				\
-  vTaskSwitchContext();																				\
-  portEXIT_CRITICAL();																				\
-																									\
-  /* Restore all registers */																		\
-																									\
-  __asm__ __volatile__ (																			\
-    /* Set SP to point to new stack */																\
-    "mov     r8, LO(%[pxCurrentTCB])																\n\t"\
-    "orh     r8, HI(%[pxCurrentTCB])																\n\t"\
-    "ld.w    r0, r8[0]																				\n\t"\
-    "ld.w    sp, r0[0]																				\n"\
-																									\
-    "LABEL_INT_SKIP_RESTORE_CONTEXT_%[LINE]:														\n\t"\
-																									\
-    /* Restore ulCriticalNesting variable */														\
-    "ld.w    r0, sp++																				\n\t"																			\
-    "mov     r8, LO(%[ulCriticalNesting])															\n\t"\
-    "orh     r8, HI(%[ulCriticalNesting])															\n\t"\
-    "st.w    r8[0], r0																				\n\t"\
-																									\
-    /* Restore R0..R7 */																			\
-    "ldm     sp++, r0-r7																			\n\t"\
-																									\
-    /* Now, the stack should be R8..R12, LR, PC and SR */											\
-    "rete"																							\
-    :																								\
-    : [ulCriticalNesting] "i" (&ulCriticalNesting),													\
-      [pxCurrentTCB] "i" (&pxCurrentTCB),															\
-      [LINE] "i" (__LINE__)																			\
-  );																								\
-}
-
-#endif
-
-
-/*
- * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
- *
- * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
- *
- */
-#define portSAVE_CONTEXT_SCALL()															\
-{																							\
-  extern volatile uint32_t ulCriticalNesting;										\
-  extern volatile void *volatile pxCurrentTCB;												\
-																							\
-  /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */		\
-  /* If SR[M2:M0] == 001 */																	\
-  /*    PC and SR are on the stack.  */														\
-  /* Else (other modes) */																	\
-  /*    Nothing on the stack. */															\
-																							\
-  /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */		\
-  /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */		\
-  /* in an interrupt|exception handler. */													\
-																							\
-  __asm__ __volatile__ (																	\
-    /* in order to save R0-R7 */															\
-    "sub     sp, 6*4																		\n\t"\
-    /* Save R0..R7 */																		\
-    "stm     --sp, r0-r7																	\n\t"\
-																							\
-    /* in order to save R8-R12 and LR */													\
-    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */			\
-    "sub     r7, sp,-16*4																	\n\t"\
-    /* Copy PC and SR in other places in the stack. */										\
-    "ld.w    r0, r7[-2*4]																	\n\t" /* Read SR */\
-    "st.w    r7[-8*4], r0																	\n\t" /* Copy SR */\
-    "ld.w    r0, r7[-1*4]																	\n\t" /* Read PC */\
-    "st.w    r7[-7*4], r0																	\n\t" /* Copy PC */\
-																							\
-    /* Save R8..R12 and LR on the stack. */													\
-    "stm     --r7, r8-r12, lr																\n\t"\
-																							\
-    /* Arriving here we have the following stack organizations: */							\
-    /* R8..R12, LR, PC, SR, R0..R7. */														\
-																							\
-    /* Now we can finalize the save. */														\
-																							\
-    /* Save ulCriticalNesting variable  - R0 is overwritten */								\
-    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
-    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
-    "ld.w    r0, r8[0]																		\n\t"\
-    "st.w    --sp, r0"																		\
-    :																						\
-    : [ulCriticalNesting] "i" (&ulCriticalNesting)											\
-  );																						\
-																							\
-  /* Disable the its which may cause a context switch (i.e. cause a change of */			\
-  /* pxCurrentTCB). */																		\
-  /* Basically, all accesses to the pxCurrentTCB structure should be put in a */			\
-  /* critical section because it is a global structure. */									\
-  portENTER_CRITICAL();																		\
-																							\
-  /* Store SP in the first member of the structure pointed to by pxCurrentTCB */			\
-  __asm__ __volatile__ (																	\
-    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
-    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
-    "ld.w    r0, r8[0]																		\n\t"\
-    "st.w    r0[0], sp"																		\
-    :																						\
-    : [pxCurrentTCB] "i" (&pxCurrentTCB)													\
-  );																						\
-}
-
-/*
- * portRESTORE_CONTEXT() for SupervisorCALL exception.
- */
-#define portRESTORE_CONTEXT_SCALL()															\
-{																							\
-  extern volatile uint32_t ulCriticalNesting;										\
-  extern volatile void *volatile pxCurrentTCB;												\
-																							\
-  /* Restore all registers */																\
-																							\
-  /* Set SP to point to new stack */														\
-  __asm__ __volatile__ (																	\
-    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
-    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
-    "ld.w    r0, r8[0]																		\n\t"\
-    "ld.w    sp, r0[0]"																		\
-    :																						\
-    : [pxCurrentTCB] "i" (&pxCurrentTCB)													\
-  );																						\
-																							\
-  /* Leave pxCurrentTCB variable access critical section */									\
-  portEXIT_CRITICAL();																		\
-																							\
-  __asm__ __volatile__ (																	\
-    /* Restore ulCriticalNesting variable */												\
-    "ld.w    r0, sp++																		\n\t"\
-    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
-    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
-    "st.w    r8[0], r0																		\n\t"\
-																							\
-    /* skip PC and SR */																	\
-    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */			\
-    "sub     r7, sp, -10*4																	\n\t"\
-    /* Restore r8-r12 and LR */																\
-    "ldm     r7++, r8-r12, lr																\n\t"\
-																							\
-    /* RETS will take care of the extra PC and SR restore. */								\
-    /* So, we have to prepare the stack for this. */										\
-    "ld.w    r0, r7[-8*4]																	\n\t" /* Read SR */\
-    "st.w    r7[-2*4], r0																	\n\t" /* Copy SR */\
-    "ld.w    r0, r7[-7*4]																	\n\t" /* Read PC */\
-    "st.w    r7[-1*4], r0																	\n\t" /* Copy PC */\
-																							\
-    /* Restore R0..R7 */																	\
-    "ldm     sp++, r0-r7																	\n\t"\
-																							\
-    "sub     sp, -6*4																		\n\t"\
-																							\
-    "rets"																					\
-    :																						\
-    : [ulCriticalNesting] "i" (&ulCriticalNesting)											\
-  );																						\
-}
-
-
-/*
- * The ISR used depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-#if configUSE_PREEMPTION == 0
-
-/*
- * ISR entry and exit macros.  These are only required if a task switch
- * is required from the ISR.
- */
-#define portENTER_SWITCHING_ISR()															\
-{																							\
-  /* Save R0..R7 */																			\
-  __asm__ __volatile__ ("stm     --sp, r0-r7");												\
-																							\
-  /* With the cooperative scheduler, as there is no context switch by interrupt, */			\
-  /* there is also no context save. */														\
-}
-
-/*
- * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
- */
-#define portEXIT_SWITCHING_ISR()															\
-{																							\
-  __asm__ __volatile__ (																	\
-    /* Restore R0..R7 */																	\
-    "ldm     sp++, r0-r7																	\n\t"\
-																							\
-    /* With the cooperative scheduler, as there is no context switch by interrupt, */		\
-    /* there is also no context restore. */													\
-    "rete"																					\
-  );																						\
-}
-
-#else
-
-/*
- * ISR entry and exit macros.  These are only required if a task switch
- * is required from the ISR.
- */
-#define portENTER_SWITCHING_ISR()															\
-{																							\
-  extern volatile uint32_t ulCriticalNesting;										\
-  extern volatile void *volatile pxCurrentTCB;												\
-																							\
-  /* When we come here */																	\
-  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */			\
-																							\
-  __asm__ __volatile__ (																	\
-    /* Save R0..R7 */																		\
-    "stm     --sp, r0-r7																	\n\t"\
-																							\
-    /* Save ulCriticalNesting variable  - R0 is overwritten */								\
-    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
-    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
-    "ld.w    r0, r8[0]																		\n\t"\
-    "st.w    --sp, r0																		\n\t"\
-																									\
-    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
-    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
-    /* level and allow other lower interrupt level to occur). */									\
-    /* In this case we don't want to do a task switch because we don't know what the stack */		\
-    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
-    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
-    /* will just be restoring the interrupt handler, no way!!! */									\
-    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
-    "ld.w    r0, sp[9*4]																	\n\t" /* Read SR in stack */\
-    "bfextu  r0, r0, 22, 3																	\n\t" /* Extract the mode bits to R0. */\
-    "cp.w    r0, 1																			\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
-    "brhi    LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]											\n\t"\
-																							\
-    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */			\
-    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
-    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
-    "ld.w    r0, r8[0]																		\n\t"\
-    "st.w    r0[0], sp																		\n"\
-																							\
-    "LABEL_ISR_SKIP_SAVE_CONTEXT_%[LINE]:"													\
-    :																						\
-    : [ulCriticalNesting] "i" (&ulCriticalNesting),											\
-      [pxCurrentTCB] "i" (&pxCurrentTCB),													\
-      [LINE] "i" (__LINE__)																	\
-  );																						\
-}
-
-/*
- * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
- */
-#define portEXIT_SWITCHING_ISR()															\
-{																							\
-  extern volatile uint32_t ulCriticalNesting;										\
-  extern volatile void *volatile pxCurrentTCB;												\
-																							\
-  __asm__ __volatile__ (																	\
-    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */		\
-    /* interrupt handler (which was of a higher priority level but decided to lower its priority */		\
-    /* level and allow other lower interrupt level to occur). */										\
-    /* In this case it's of no use to switch context and restore a new SP because we purposedly */		\
-    /* did not previously save SP in its TCB. */																				\
-    "ld.w    r0, sp[9*4]																	\n\t" /* Read SR in stack */\
-    "bfextu  r0, r0, 22, 3																	\n\t" /* Extract the mode bits to R0. */\
-    "cp.w    r0, 1																			\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
-    "brhi    LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]											\n\t"\
-																							\
-    /* If a switch is required then we just need to call */									\
-    /* vTaskSwitchContext() as the context has already been */								\
-    /* saved. */																			\
-    "cp.w    r12, 1																			\n\t" /* Check if Switch context is required. */\
-    "brne    LABEL_ISR_RESTORE_CONTEXT_%[LINE]"												\
-    :																						\
-    : [LINE] "i" (__LINE__)																	\
-  );																						\
-																							\
-  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */	\
-  portENTER_CRITICAL();																		\
-  vTaskSwitchContext();																		\
-  portEXIT_CRITICAL();																		\
-																							\
-  __asm__ __volatile__ (																	\
-    "LABEL_ISR_RESTORE_CONTEXT_%[LINE]:														\n\t"\
-    /* Restore the context of which ever task is now the highest */							\
-    /* priority that is ready to run. */													\
-																							\
-    /* Restore all registers */																\
-																							\
-    /* Set SP to point to new stack */														\
-    "mov     r8, LO(%[pxCurrentTCB])														\n\t"\
-    "orh     r8, HI(%[pxCurrentTCB])														\n\t"\
-    "ld.w    r0, r8[0]																		\n\t"\
-    "ld.w    sp, r0[0]																		\n"\
-																							\
-    "LABEL_ISR_SKIP_RESTORE_CONTEXT_%[LINE]:												\n\t"\
-																							\
-    /* Restore ulCriticalNesting variable */												\
-    "ld.w    r0, sp++																		\n\t"\
-    "mov     r8, LO(%[ulCriticalNesting])													\n\t"\
-    "orh     r8, HI(%[ulCriticalNesting])													\n\t"\
-    "st.w    r8[0], r0																		\n\t"\
-																							\
-    /* Restore R0..R7 */																	\
-    "ldm     sp++, r0-r7																	\n\t"\
-																							\
-    /* Now, the stack should be R8..R12, LR, PC and SR  */									\
-    "rete"																					\
-    :																						\
-    : [ulCriticalNesting] "i" (&ulCriticalNesting),											\
-      [pxCurrentTCB] "i" (&pxCurrentTCB),													\
-      [LINE] "i" (__LINE__)																	\
-  );																						\
-}
-
-#endif
-
-
-#define portYIELD()                 {__asm__ __volatile__ ("scall");}
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/GCC/CORTUS_APS3/port.c b/FreeRTOS/Source/portable/GCC/CORTUS_APS3/port.c
deleted file mode 100755
index 3ac5846..0000000
--- a/FreeRTOS/Source/portable/GCC/CORTUS_APS3/port.c
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Machine includes */
-#include 
-#include 
-/*-----------------------------------------------------------*/
-
-/* The initial PSR has the Previous Interrupt Enabled (PIEN) flag set. */
-#define portINITIAL_PSR			( 0x00020000 )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Perform any hardware configuration necessary to generate the tick interrupt.
- */
-static void prvSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Make space on the stack for the context - this leaves a couple of spaces
-	empty.  */
-	pxTopOfStack -= 20;
-
-	/* Fill the registers with known values to assist debugging. */
-	pxTopOfStack[ 16 ] = 0;
-	pxTopOfStack[ 15 ] = portINITIAL_PSR;
-	pxTopOfStack[ 14 ] = ( uint32_t ) pxCode;
-	pxTopOfStack[ 13 ] = 0x00000000UL; /* R15. */
-	pxTopOfStack[ 12 ] = 0x00000000UL; /* R14. */
-	pxTopOfStack[ 11 ] = 0x0d0d0d0dUL;
-	pxTopOfStack[ 10 ] = 0x0c0c0c0cUL;
-	pxTopOfStack[ 9 ] = 0x0b0b0b0bUL;
-	pxTopOfStack[ 8 ] = 0x0a0a0a0aUL;
-	pxTopOfStack[ 7 ] = 0x09090909UL;
-	pxTopOfStack[ 6 ] = 0x08080808UL;
-	pxTopOfStack[ 5 ] = 0x07070707UL;
-	pxTopOfStack[ 4 ] = 0x06060606UL;
-	pxTopOfStack[ 3 ] = 0x05050505UL;
-	pxTopOfStack[ 2 ] = 0x04040404UL;
-	pxTopOfStack[ 1 ] = 0x03030303UL;
-	pxTopOfStack[ 0 ] = ( uint32_t ) pvParameters;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Set-up the timer interrupt. */
-	prvSetupTimerInterrupt();
-
-	/* Integrated Interrupt Controller: Enable all interrupts. */
-	ic->ien = 1;
-
-	/* Restore callee saved registers. */
-	portRESTORE_CONTEXT();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-	/* Enable timer interrupts */
-	counter1->reload = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1;
-	counter1->value = counter1->reload;
-	counter1->mask = 1;
-
-	/* Set the IRQ Handler priority and enable it. */
-	irq[ IRQ_COUNTER1 ].ien = 1;
-}
-/*-----------------------------------------------------------*/
-
-/* Trap 31 handler. */
-void interrupt31_handler( void ) __attribute__((naked));
-void interrupt31_handler( void )
-{
-	portSAVE_CONTEXT();
-	__asm volatile ( "call vTaskSwitchContext" );
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-static void prvProcessTick( void ) __attribute__((noinline));
-static void prvProcessTick( void )
-{
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		vTaskSwitchContext();
-	}
-		
-	/* Clear the Tick Interrupt. */
-	counter1->expired = 0;
-}
-/*-----------------------------------------------------------*/
-
-/* Timer 1 interrupt handler, used for tick interrupt. */
-void interrupt7_handler( void ) __attribute__((naked));
-void interrupt7_handler( void )
-{
-	portSAVE_CONTEXT();
-	prvProcessTick();
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Nothing to do. Unlikely to want to end. */
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/CORTUS_APS3/portmacro.h b/FreeRTOS/Source/portable/GCC/CORTUS_APS3/portmacro.h
deleted file mode 100755
index 1192e03..0000000
--- a/FreeRTOS/Source/portable/GCC/CORTUS_APS3/portmacro.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include 
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH							( -1 )
-#define portTICK_PERIOD_MS							( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT							4
-#define portNOP()									__asm__ volatile ( "mov r0, r0" )
-#define portCRITICAL_NESTING_IN_TCB					1
-#define portIRQ_TRAP_YIELD							31
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-extern void vPortYield( void );
-
-/*---------------------------------------------------------------------------*/
-
-#define portYIELD()		asm __volatile__( " trap #%0 "::"i"(portIRQ_TRAP_YIELD):"memory")
-/*---------------------------------------------------------------------------*/
-
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()		vTaskEnterCritical()
-#define portEXIT_CRITICAL()			vTaskExitCritical()
-/*---------------------------------------------------------------------------*/
-
-/* Critical section management. */
-#define portDISABLE_INTERRUPTS() 	cpu_int_disable()
-#define portENABLE_INTERRUPTS() 	cpu_int_enable()
-
-/*---------------------------------------------------------------------------*/
-
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken != pdFALSE ) vTaskSwitchContext()
-
-/*---------------------------------------------------------------------------*/
-
-#define portSAVE_CONTEXT()				\
-	asm __volatile__																								\
-	(																												\
-		"sub	r1, #68					\n" /* Make space on the stack for the context. */							\
-		"std	r2, [r1] + 	0			\n"																			\
-		"stq	r4, [r1] +	8			\n"																			\
-		"stq	r8, [r1] +	24			\n"																			\
-		"stq	r12, [r1] +	40			\n"																			\
-		"mov	r6, rtt					\n"																			\
-		"mov	r7, psr					\n"																			\
-		"std	r6, [r1] +	56			\n"																			\
-		"movhi	r2, #16384				\n"	/* Set the pointer to the IC. */										\
-		"ldub	r3, [r2] + 2			\n"	/* Load the current interrupt mask. */									\
-		"st		r3, [r1]+ 64			\n"	/* Store the interrupt mask on the stack. */ 							\
-		"ld		r2, [r0]+short(pxCurrentTCB)	\n"	/* Load the pointer to the TCB. */								\
-		"st		r1, [r2]				\n"	/* Save the stack pointer into the TCB. */								\
-		"mov	r14, r1					\n"	/* Compiler expects r14 to be set to the function stack. */				\
-	);
-/*---------------------------------------------------------------------------*/
-
-#define portRESTORE_CONTEXT()																						\
-	asm __volatile__(																								\
-		"ld		r2, [r0]+short(pxCurrentTCB)	\n"	/* Load the TCB to find the stack pointer and context. */		\
-		"ld		r1, [r2]				\n"																			\
-		"movhi	r2, #16384				\n"	/* Set the pointer to the IC. */										\
-		"ld		r3, [r1] + 64			\n"	/* Load the previous interrupt mask. */									\
-		"stb	r3, [r2] + 2  			\n"	/* Set the current interrupt mask to be the previous. */				\
-		"ldd	r6, [r1] + 56			\n"	/* Restore context. */													\
-		"mov	rtt, r6					\n"																			\
-		"mov	psr, r7					\n"																			\
-		"ldd	r2, [r1] + 0			\n"																			\
-		"ldq	r4, [r1] +	8			\n"																			\
-		"ldq	r8, [r1] +	24			\n"																			\
-		"ldq	r12, [r1] +	40			\n"																			\
-		"add	r1, #68					\n"																			\
-		"rti							\n"																			\
-	 );
-
-/*---------------------------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*---------------------------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/GCC/ColdFire_V2/port.c b/FreeRTOS/Source/portable/GCC/ColdFire_V2/port.c
deleted file mode 100755
index 1ee2add..0000000
--- a/FreeRTOS/Source/portable/GCC/ColdFire_V2/port.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#define portINITIAL_FORMAT_VECTOR		( ( StackType_t ) 0x4000 )
-
-/* Supervisor mode set. */
-#define portINITIAL_STATUS_REGISTER		( ( StackType_t ) 0x2000)
-
-/* Used to keep track of the number of nested calls to taskENTER_CRITICAL().  This
-will be set to 0 prior to the first task being started. */
-static uint32_t ulCriticalNesting = 0x9999UL;
-
-/*-----------------------------------------------------------*/
-
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	*pxTopOfStack = ( StackType_t ) pvParameters;
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
-	pxTopOfStack--;
-
-	/* Exception stack frame starts with the return address. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( portINITIAL_FORMAT_VECTOR << 16UL ) | ( portINITIAL_STATUS_REGISTER );
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0x0; /*FP*/
-	pxTopOfStack -= 14; /* A5 to D0. */
-
-    return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortStartFirstTask( void );
-
-	ulCriticalNesting = 0UL;
-
-	/* Configure the interrupts used by this port. */
-	vApplicationSetupInterrupts();
-
-	/* Start the first task executing. */
-	vPortStartFirstTask();
-
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented as there is nothing to return to. */
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	if( ulCriticalNesting == 0UL )
-	{
-		/* Guard against context switches being pended simultaneously with a
-		critical section being entered. */
-		do
-		{
-			portDISABLE_INTERRUPTS();
-			if( MCF_INTC0_INTFRCL == 0UL )
-			{
-				break;
-			}
-
-			portENABLE_INTERRUPTS();
-
-		} while( 1 );
-	}
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	ulCriticalNesting--;
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortYieldHandler( void )
-{
-uint32_t ulSavedInterruptMask;
-
-	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
-		/* Note this will clear all forced interrupts - this is done for speed. */
-		MCF_INTC0_INTFRCL = 0;
-		vTaskSwitchContext();
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
-}
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ColdFire_V2/portasm.S b/FreeRTOS/Source/portable/GCC/ColdFire_V2/portasm.S
deleted file mode 100755
index 4076d4d..0000000
--- a/FreeRTOS/Source/portable/GCC/ColdFire_V2/portasm.S
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * Purpose: Lowest level routines for all ColdFire processors.
- *
- * Notes:
- * 
- * ulPortSetIPL() and mcf5xxx_wr_cacr() copied with permission from FreeScale
- * supplied source files.
- */
-
-    .global ulPortSetIPL
-    .global mcf5xxx_wr_cacr
-    .global __cs3_isr_interrupt_80
-    .global vPortStartFirstTask
-
-    .text
-
-.macro portSAVE_CONTEXT
-
-	lea.l		(-60, %sp), %sp
-	movem.l		%d0-%fp, (%sp)
-	move.l		pxCurrentTCB, %a0
-	move.l		%sp, (%a0)
-
-	.endm
-
-.macro portRESTORE_CONTEXT
-
-	move.l		pxCurrentTCB, %a0
-	move.l		(%a0), %sp
-	movem.l		(%sp), %d0-%fp
-	lea.l		%sp@(60), %sp
-	rte
-
-	.endm
-
-/********************************************************************/
-/*
- * This routines changes the IPL to the value passed into the routine.
- * It also returns the old IPL value back.
- * Calling convention from C:
- *   old_ipl = asm_set_ipl(new_ipl);
- * For the Diab Data C compiler, it passes return value thru D0.
- * Note that only the least significant three bits of the passed
- * value are used.
- */
-
-ulPortSetIPL:
-    link    A6,#-8
-    movem.l D6-D7,(SP)
-
-    move.w  SR,D7       /* current sr    */
-
-    move.l  D7,D0       /* prepare return value  */
-    andi.l  #0x0700,D0  /* mask out IPL  */
-    lsr.l   #8,D0       /* IPL   */
-
-    move.l  8(A6),D6    /* get argument  */
-    andi.l  #0x07,D6    /* least significant three bits  */
-    lsl.l   #8,D6       /* move over to make mask    */
-
-    andi.l  #0x0000F8FF,D7  /* zero out current IPL  */
-    or.l    D6,D7           /* place new IPL in sr   */
-    move.w  D7,SR
-
-    movem.l (SP),D6-D7
-    lea     8(SP),SP
-    unlk    A6
-    rts
-/********************************************************************/
-
-mcf5xxx_wr_cacr:
-    move.l  4(sp),d0
-    .long   0x4e7b0002  /* movec d0,cacr   */
-    nop
-    rts
-
-/********************************************************************/
-
-/* Yield interrupt. */
-__cs3_isr_interrupt_80:
-	portSAVE_CONTEXT
-	jsr vPortYieldHandler
-	portRESTORE_CONTEXT
-
-/********************************************************************/
-
-
-vPortStartFirstTask:
-	portRESTORE_CONTEXT
-
-    .end
-
-
diff --git a/FreeRTOS/Source/portable/GCC/ColdFire_V2/portmacro.h b/FreeRTOS/Source/portable/GCC/ColdFire_V2/portmacro.h
deleted file mode 100755
index 0fc0526..0000000
--- a/FreeRTOS/Source/portable/GCC/ColdFire_V2/portmacro.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			4
-#define portSTACK_GROWTH			-1
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-uint32_t ulPortSetIPL( uint32_t );
-#define portDISABLE_INTERRUPTS()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portENABLE_INTERRUPTS()		ulPortSetIPL( 0 )
-
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-
-extern UBaseType_t uxPortSetInterruptMaskFromISR( void );
-extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR()	ulPortSetIPL( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) ulPortSetIPL( uxSavedStatusRegister )
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-#define portNOP()	asm volatile ( 	"nop" )
-
-/* Note this will overwrite all other bits in the force register, it is done this way for speed. */
-#define portYIELD()			MCF_INTC0_INTFRCL = ( 1UL << configYIELD_INTERRUPT_VECTOR ); portNOP(); portNOP()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired != pdFALSE )	\
-													{									\
-														portYIELD();					\
-													}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/H8S2329/port.c b/FreeRTOS/Source/portable/GCC/H8S2329/port.c
deleted file mode 100755
index 9f39b97..0000000
--- a/FreeRTOS/Source/portable/GCC/H8S2329/port.c
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the H8S port.
- *----------------------------------------------------------*/
-
-
-/*-----------------------------------------------------------*/
-
-/* When the task starts interrupts should be enabled. */
-#define portINITIAL_CCR			( ( StackType_t ) 0x00 )
-
-/* Hardware specific constants used to generate the RTOS tick from the TPU. */
-#define portCLEAR_ON_TGRA_COMPARE_MATCH ( ( uint8_t ) 0x20 )
-#define portCLOCK_DIV_64				( ( uint8_t ) 0x03 )
-#define portCLOCK_DIV					( ( uint32_t ) 64 )
-#define portTGRA_INTERRUPT_ENABLE		( ( uint8_t ) 0x01 )
-#define portTIMER_CHANNEL				( ( uint8_t ) 0x02 )
-#define portMSTP13						( ( uint16_t ) 0x2000 )
-
-/*
- * Setup TPU channel one for the RTOS tick at the requested frequency.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * The ISR used by portYIELD(). This is installed as a trap handler.
- */
-void vPortYield( void ) __attribute__ ( ( saveall, interrupt_handler ) );
-
-/*-----------------------------------------------------------*/
-
-/* 
- * See header file for description. 
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint32_t ulValue;
-
-	/* This requires an even address. */
-	ulValue = ( uint32_t ) pxTopOfStack;
-	if( ulValue & 1UL )
-	{
-		pxTopOfStack = pxTopOfStack - 1;
-	}
-
-	/* Place a few bytes of known values on the bottom of the stack. 
-	This is just useful for debugging. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0xaa;
-	pxTopOfStack--;
-	*pxTopOfStack = 0xbb;
-	pxTopOfStack--;
-	*pxTopOfStack = 0xcc;
-	pxTopOfStack--;
-	*pxTopOfStack = 0xdd;
-
-	/* The initial stack mimics an interrupt stack.  First there is the program
-	counter (24 bits). */
-	ulValue = ( uint32_t ) pxCode;
-
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
-	pxTopOfStack--;
-	ulValue >>= 8UL;
-	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
-	pxTopOfStack--;
-	ulValue >>= 8UL;
-	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
-
-	/* Followed by the CCR. */	
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_CCR;
-
-	/* Next all the general purpose registers - with the parameters being passed
-	in ER0.  The parameter order must match that used by the compiler when the
-	"saveall" function attribute is used. */
-
-	/* ER6 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x66;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x66;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x66;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x66;
-	
-	/* ER0 */
-	ulValue = ( uint32_t ) pvParameters;
-
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
-	pxTopOfStack--;
-	ulValue >>= 8UL;
-	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
-	pxTopOfStack--;
-	ulValue >>= 8UL;
-	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
-	pxTopOfStack--;
-	ulValue >>= 8UL;
-	*pxTopOfStack = ( StackType_t ) ( ulValue & 0xff );
-	
-	/* ER1 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x11;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x11;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x11;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x11;
-
-	/* ER2 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x22;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x22;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x22;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x22;
-
-	/* ER3 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x33;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x33;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x33;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x33;
-
-	/* ER4 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x44;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x44;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x44;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x44;
-
-	/* ER5 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x55;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x55;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x55;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x55;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void * pxCurrentTCB;
-
-	/* Setup the hardware to generate the tick. */
-	prvSetupTimerInterrupt();
-
-	/* Restore the context of the first task that is going to run.  This
-	mirrors the function epilogue code generated by the compiler when the
-	"saveall" function attribute is used. */
-	asm volatile ( 
-					"MOV.L		@_pxCurrentTCB, ER6			\n\t"
-					"MOV.L		@ER6, ER7					\n\t"
-					"LDM.L     	@SP+, (ER4-ER5)				\n\t"
-					"LDM.L     	@SP+, (ER0-ER3)				\n\t"
-					"MOV.L     	@ER7+, ER6					\n\t"
-					"RTE									\n\t"
-				);
-
-	( void ) pxCurrentTCB;
-
-	/* Should not get here. */
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the h8 port will get stopped. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch.  This is a trap handler.  The "saveall" function
- * attribute is used so the context is saved by the compiler prologue.  All
- * we have to do is save the stack pointer.
- */
-void vPortYield( void )
-{
-	portSAVE_STACK_POINTER();
-		vTaskSwitchContext();
-	portRESTORE_STACK_POINTER();
-}
-/*-----------------------------------------------------------*/
-
-/* 
- * The interrupt handler installed for the RTOS tick depends on whether the 
- * preemptive or cooperative scheduler is being used. 
- */
-#if( configUSE_PREEMPTION == 1 )
-
-	/* 
-	 * The preemptive scheduler is used so the ISR calls vTaskSwitchContext().
-	 * The function prologue saves the context so all we have to do is save
-	 * the stack pointer.
-	 */
-	void vTickISR( void ) __attribute__ ( ( saveall, interrupt_handler ) );
-	void vTickISR( void )
-	{
-		portSAVE_STACK_POINTER();
-		
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			vTaskSwitchContext();
-		}
-
-		/* Clear the interrupt. */
-		TSR1 &= ~0x01;
-
-		portRESTORE_STACK_POINTER();
-	}
-
-#else
-
-	/*
-	 * The cooperative scheduler is being used so all we have to do is 
-	 * periodically increment the tick.  This can just be a normal ISR and
-	 * the "saveall" attribute is not required.
-	 */
-	void vTickISR( void ) __attribute__ ( ( interrupt_handler ) );
-	void vTickISR( void )
-	{
-		xTaskIncrementTick();
-
-		/* Clear the interrupt. */
-		TSR1 &= ~0x01;
-	}
-
-#endif
-/*-----------------------------------------------------------*/
-
-/*
- * Setup timer 1 compare match to generate a tick interrupt.
- */
-static void prvSetupTimerInterrupt( void )
-{
-const uint32_t ulCompareMatch = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / portCLOCK_DIV;
-
-	/* Turn the module on. */
-	MSTPCR &= ~portMSTP13;
-
-	/* Configure timer 1. */
-	TCR1 = portCLEAR_ON_TGRA_COMPARE_MATCH | portCLOCK_DIV_64;
-
-	/* Configure the compare match value for a tick of configTICK_RATE_HZ. */
-	TGR1A = ulCompareMatch;
-
-	/* Start the timer and enable the interrupt - we can do this here as 
-	interrupts are globally disabled when this function is called. */
-	TIER1 |= portTGRA_INTERRUPT_ENABLE;
-	TSTR |= portTIMER_CHANNEL;
-}
-/*-----------------------------------------------------------*/
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/H8S2329/portmacro.h b/FreeRTOS/Source/portable/GCC/H8S2329/portmacro.h
deleted file mode 100755
index 05ec873..0000000
--- a/FreeRTOS/Source/portable/GCC/H8S2329/portmacro.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint8_t
-#define portBASE_TYPE	char
-
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			2
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portYIELD()					asm volatile( "TRAPA #0" )
-#define portNOP()					asm volatile( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-#define portENABLE_INTERRUPTS()		asm volatile( "ANDC	#0x7F, CCR" );
-#define portDISABLE_INTERRUPTS()	asm volatile( "ORC  #0x80, CCR" );
-
-/* Push the CCR then disable interrupts. */
-#define portENTER_CRITICAL()  		asm volatile( "STC	CCR, @-ER7" ); \
-                               		portDISABLE_INTERRUPTS();
-
-/* Pop the CCR to set the interrupt masking back to its previous state. */
-#define  portEXIT_CRITICAL()    	asm volatile( "LDC  @ER7+, CCR" );
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* Context switch macros.  These macros are very simple as the context
-is saved simply by selecting the saveall attribute of the context switch
-interrupt service routines.  These macros save and restore the stack
-pointer to the TCB. */
-
-#define portSAVE_STACK_POINTER()								\
-extern void* pxCurrentTCB;										\
-																\
-	asm volatile(												\
-					"MOV.L	@_pxCurrentTCB, ER5			\n\t" 	\
-					"MOV.L	ER7, @ER5					\n\t"	\
-				);												\
-	( void ) pxCurrentTCB;
-
-
-#define	portRESTORE_STACK_POINTER()								\
-extern void* pxCurrentTCB;										\
-																\
-	asm volatile(												\
-					"MOV.L	@_pxCurrentTCB, ER5			\n\t"	\
-					"MOV.L	@ER5, ER7					\n\t"	\
-				);												\
-	( void ) pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
-
-/* Macros to allow a context switch from within an application ISR. */
-
-#define portENTER_SWITCHING_ISR() portSAVE_STACK_POINTER(); {
-
-#define portEXIT_SWITCHING_ISR( x )							\
-	if( x )													\
-	{														\
-		extern void vTaskSwitchContext( void );				\
-		vTaskSwitchContext();								\
-	}														\
-	} portRESTORE_STACK_POINTER();
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/HCS12/port.c b/FreeRTOS/Source/portable/GCC/HCS12/port.c
deleted file mode 100755
index f1673c3..0000000
--- a/FreeRTOS/Source/portable/GCC/HCS12/port.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* GCC/HCS12 port by Jefferson L Smith, 2005 */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Port includes */
-#include 
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the HCS12 port.
- *----------------------------------------------------------*/
-
-
-/*
- * Configure a timer to generate the RTOS tick at the frequency specified 
- * within FreeRTOSConfig.h.
- */
-static void prvSetupTimerInterrupt( void );
-
-/* NOTE: Interrupt service routines must be in non-banked memory - as does the
-scheduler startup function. */
-#define ATTR_NEAR	__attribute__((near))
-
-/* Manual context switch function.  This is the SWI ISR. */
-// __attribute__((interrupt))
-void ATTR_NEAR vPortYield( void );
-
-/* Tick context switch function.  This is the timer ISR. */
-// __attribute__((interrupt))
-void ATTR_NEAR vPortTickInterrupt( void );
-
-/* Function in non-banked memory which actually switches to first task. */
-BaseType_t ATTR_NEAR xStartSchedulerNear( void );
-
-/* Calls to portENTER_CRITICAL() can be nested.  When they are nested the 
-critical section should not be left (i.e. interrupts should not be re-enabled)
-until the nesting depth reaches 0.  This variable simply tracks the nesting 
-depth.  Each task maintains it's own critical nesting depth variable so 
-uxCriticalNesting is saved and restored from the task stack during a context
-switch. */
-volatile UBaseType_t uxCriticalNesting = 0x80;  // un-initialized
-
-/*-----------------------------------------------------------*/
-
-/* 
- * See header file for description. 
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-
-
-	/* Setup the initial stack of the task.  The stack is set exactly as 
-	expected by the portRESTORE_CONTEXT() macro.  In this case the stack as
-	expected by the HCS12 RTI instruction. */
-
-
-	/* The address of the task function is placed in the stack byte at a time. */
-	*pxTopOfStack   = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 1 );
-	*--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pxCode) ) + 0 );
-
-	/* Next are all the registers that form part of the task context. */
-
-	/* Y register */
-	*--pxTopOfStack = ( StackType_t ) 0xff;
-	*--pxTopOfStack = ( StackType_t ) 0xee;
-
-	/* X register */
-	*--pxTopOfStack = ( StackType_t ) 0xdd;
-	*--pxTopOfStack = ( StackType_t ) 0xcc;
- 
-	/* A register contains parameter high byte. */
-	*--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 0 );
-
-	/* B register contains parameter low byte. */
-	*--pxTopOfStack = ( StackType_t ) *( ((StackType_t *) (&pvParameters) ) + 1 );
-
-	/* CCR: Note that when the task starts interrupts will be enabled since
-	"I" bit of CCR is cleared */
-	*--pxTopOfStack = ( StackType_t ) 0x80;		// keeps Stop disabled (MCU default)
-	
-	/* tmp softregs used by GCC. Values right now don't	matter. */
-	__asm("\n\
-		movw _.frame, 2,-%0							\n\
-		movw _.tmp, 2,-%0							\n\
-		movw _.z, 2,-%0								\n\
-		movw _.xy, 2,-%0							\n\
-		;movw _.d2, 2,-%0							\n\
-		;movw _.d1, 2,-%0							\n\
-	": "=A"(pxTopOfStack) : "0"(pxTopOfStack) );
-
-	#ifdef BANKED_MODEL
-		/* The page of the task. */
-		*--pxTopOfStack = 0x30;      // can only directly start in PPAGE 0x30
-	#endif
-	
-	/* The critical nesting depth is initialised with 0 (meaning not in
-	a critical section). */
-	*--pxTopOfStack = ( StackType_t ) 0x00;
-
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the HCS12 port will get stopped. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-	/* Enable hardware RTI timer */
-	/* Ignores configTICK_RATE_HZ */
-	RTICTL = 0x50;			// 16 MHz xtal: 976.56 Hz, 1024mS 
-	CRGINT |= 0x80;			// RTIE
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* xPortStartScheduler() does not start the scheduler directly because 
-	the header file containing the xPortStartScheduler() prototype is part 
-	of the common kernel code, and therefore cannot use the CODE_SEG pragma. 
-	Instead it simply calls the locally defined xNearStartScheduler() - 
-	which does use the CODE_SEG pragma. */
-
-	int16_t register d;
-	__asm ("jmp  xStartSchedulerNear		; will never return": "=d"(d));
-	return d;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStartSchedulerNear( void )
-{
-	/* Configure the timer that will generate the RTOS tick.  Interrupts are
-	disabled when this function is called. */
-	prvSetupTimerInterrupt();
-
-	/* Restore the context of the first task. */
-	portRESTORE_CONTEXT();
-
-	portISR_TAIL();
-
-	/* Should not get here! */
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Context switch functions.  These are interrupt service routines.
- */
-
-/*
- * Manual context switch forced by calling portYIELD().  This is the SWI
- * handler.
- */
-void vPortYield( void )
-{
-	portISR_HEAD();
-	/* NOTE: This is the trap routine (swi) although not defined as a trap.
-	   It will fill the stack the same way as an ISR in order to mix preemtion
-	   and cooperative yield. */
-
-	portSAVE_CONTEXT();
-	vTaskSwitchContext();
-	portRESTORE_CONTEXT();
-
-	portISR_TAIL();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * RTOS tick interrupt service routine.  If the cooperative scheduler is 
- * being used then this simply increments the tick count.  If the 
- * preemptive scheduler is being used a context switch can occur.
- */
-void vPortTickInterrupt( void )
-{
-	portISR_HEAD();
-
-	/* Clear tick timer flag */
-	CRGFLG = 0x80;
-
-	#if configUSE_PREEMPTION == 1
-	{
-		/* A context switch might happen so save the context. */
-		portSAVE_CONTEXT();
-
-		/* Increment the tick ... */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is necessary. */
-			vTaskSwitchContext();
-		}
-
-		/* Restore the context of a task - which may be a different task
-		to that interrupted. */
-		portRESTORE_CONTEXT();
-	}
-	#else
-	{
-		xTaskIncrementTick();
-	}
-	#endif
-
-	portISR_TAIL();
-}
-
diff --git a/FreeRTOS/Source/portable/GCC/HCS12/portmacro.h b/FreeRTOS/Source/portable/GCC/HCS12/portmacro.h
deleted file mode 100755
index 2dceeb1..0000000
--- a/FreeRTOS/Source/portable/GCC/HCS12/portmacro.h
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint8_t
-#define portBASE_TYPE	char
-
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			1
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portYIELD()					__asm( "swi" );
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-#define portENABLE_INTERRUPTS()				__asm( "cli" )
-#define portDISABLE_INTERRUPTS()			__asm( "sei" )
-
-/*
- * Disable interrupts before incrementing the count of critical section nesting.
- * The nesting count is maintained so we know when interrupts should be
- * re-enabled.  Once interrupts are disabled the nesting count can be accessed
- * directly.  Each task maintains its own nesting count.
- */
-#define portENTER_CRITICAL()  									\
-{																\
-	extern volatile UBaseType_t uxCriticalNesting;	\
-																\
-	portDISABLE_INTERRUPTS();									\
-	uxCriticalNesting++;										\
-}
-
-/*
- * Interrupts are disabled so we can access the nesting count directly.  If the
- * nesting is found to be 0 (no nesting) then we are leaving the critical
- * section and interrupts can be re-enabled.
- */
-#define  portEXIT_CRITICAL()									\
-{																\
-	extern volatile UBaseType_t uxCriticalNesting;	\
-																\
-	uxCriticalNesting--;										\
-	if( uxCriticalNesting == 0 )								\
-	{															\
-		portENABLE_INTERRUPTS();								\
-	}															\
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/*
- * These macros are very simple as the processor automatically saves and
- * restores its registers as interrupts are entered and exited.  In
- * addition to the (automatically stacked) registers we also stack the
- * critical nesting count.  Each task maintains its own critical nesting
- * count as it is legitimate for a task to yield from within a critical
- * section.  If the banked memory model is being used then the PPAGE
- * register is also stored as part of the tasks context.
- */
-
-#ifdef BANKED_MODEL
-	/*
-	 * Load the stack pointer for the task, then pull the critical nesting
-	 * count and PPAGE register from the stack.  The remains of the
-	 * context are restored by the RTI instruction.
-	 */
-	#define portRESTORE_CONTEXT()							\
-	{										\
-		__asm( "								\n\
-		.globl pxCurrentTCB			; void *			\n\
-		.globl uxCriticalNesting		; char				\n\
-											\n\
-		ldx  pxCurrentTCB							\n\
-		lds  0,x				; Stack				\n\
-											\n\
-		movb 1,sp+,uxCriticalNesting						\n\
-		movb 1,sp+,0x30				; PPAGE				\n\
-		" );									\
-	}
-
-	/*
-	 * By the time this macro is called the processor has already stacked the
-	 * registers.  Simply stack the nesting count and PPAGE value, then save
-	 * the task stack pointer.
-	 */
-	#define portSAVE_CONTEXT()							\
-	{										\
-		__asm( "								\n\
-		.globl pxCurrentTCB			; void *			\n\
-		.globl uxCriticalNesting		; char				\n\
-											\n\
-		movb 0x30, 1,-sp			; PPAGE				\n\
-		movb uxCriticalNesting, 1,-sp						\n\
-											\n\
-		ldx  pxCurrentTCB							\n\
-		sts  0,x				; Stack				\n\
-		" );									\
-	}
-#else
-
-	/*
-	 * These macros are as per the BANKED versions above, but without saving
-	 * and restoring the PPAGE register.
-	 */
-
-	#define portRESTORE_CONTEXT()							\
-	{										\
-		__asm( "								\n\
-		.globl pxCurrentTCB			; void *			\n\
-		.globl uxCriticalNesting		; char				\n\
-											\n\
-		ldx  pxCurrentTCB							\n\
-		lds  0,x				; Stack				\n\
-											\n\
-		movb 1,sp+,uxCriticalNesting						\n\
-		" );									\
-	}
-
-	#define portSAVE_CONTEXT()							\
-	{										\
-		__asm( "								\n\
-		.globl pxCurrentTCB			; void *			\n\
-		.globl uxCriticalNesting		; char				\n\
-											\n\
-		movb uxCriticalNesting, 1,-sp						\n\
-											\n\
-		ldx  pxCurrentTCB							\n\
-		sts  0,x				; Stack				\n\
-		" );									\
-	}
-#endif
-
-/*
- * Utility macros to save/restore correct software registers for GCC. This is
- * useful when GCC does not generate appropriate ISR head/tail code.
- */
-#define portISR_HEAD()									\
-{											\
-		__asm("									\n\
-		movw _.frame, 2,-sp							\n\
-		movw _.tmp, 2,-sp							\n\
-		movw _.z, 2,-sp								\n\
-		movw _.xy, 2,-sp							\n\
-		;movw _.d2, 2,-sp							\n\
-		;movw _.d1, 2,-sp							\n\
-		");									\
-}
-
-#define portISR_TAIL()									\
-{											\
-		__asm("									\n\
-		movw 2,sp+, _.xy							\n\
-		movw 2,sp+, _.z								\n\
-		movw 2,sp+, _.tmp							\n\
-		movw 2,sp+, _.frame							\n\
-		;movw 2,sp+, _.d1							\n\
-		;movw 2,sp+, _.d2							\n\
-		rti									\n\
-		");									\
-}
-
-/*
- * Utility macro to call macros above in correct order in order to perform a
- * task switch from within a standard ISR.  This macro can only be used if
- * the ISR does not use any local (stack) variables.  If the ISR uses stack
- * variables portYIELD() should be used in it's place.
- */
-
-#define portTASK_SWITCH_FROM_ISR()								\
-	portSAVE_CONTEXT();											\
-	vTaskSwitchContext();										\
-	portRESTORE_CONTEXT();
-
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/IA32_flat/ISR_Support.h b/FreeRTOS/Source/portable/GCC/IA32_flat/ISR_Support.h
deleted file mode 100755
index 62fe635..0000000
--- a/FreeRTOS/Source/portable/GCC/IA32_flat/ISR_Support.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	.extern ulTopOfSystemStack
-	.extern ulInterruptNesting
-
-/*-----------------------------------------------------------*/
-
-.macro portFREERTOS_INTERRUPT_ENTRY
-
-	/* Save general purpose registers. */
-	pusha
-
-	/* If ulInterruptNesting is zero the rest of the task context will need
-	saving and a stack switch might be required. */
-	movl	ulInterruptNesting, %eax
-	test	%eax, %eax
-	jne		2f
-
-	/* Interrupts are not nested, so save the rest of the task context. */
-	.if configSUPPORT_FPU == 1
-
-		/* If the task has a buffer allocated to save the FPU context then
-		save the FPU context now. */
-		movl	pucPortTaskFPUContextBuffer, %eax
-		test	%eax, %eax
-		je		1f
-		fnsave	( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
-		fwait
-
-		1:
-		/* Save the address of the FPU context, if any. */
-		push	pucPortTaskFPUContextBuffer
-
-	.endif /* configSUPPORT_FPU */
-
-	/* Find the TCB. */
-	movl 	pxCurrentTCB, %eax
-
-	/* Stack location is first item in the TCB. */
-	movl	%esp, (%eax)
-
-	/* Switch stacks. */
-	movl 	ulTopOfSystemStack, %esp
-	movl	%esp, %ebp
-
-	2:
-	/* Increment nesting count. */
-	add 	$1, ulInterruptNesting
-
-.endm
-/*-----------------------------------------------------------*/
-
-.macro portINTERRUPT_EPILOGUE
-
-	cli
-	sub		$1, ulInterruptNesting
-
-	/* If the nesting has unwound to zero. */
-	movl	ulInterruptNesting, %eax
-	test	%eax, %eax
-	jne		2f
-
-	/* If a yield was requested then select a new TCB now. */
-	movl	ulPortYieldPending, %eax
-	test	%eax, %eax
-	je		1f
-	movl	$0, ulPortYieldPending
-	call	vTaskSwitchContext
-
-	1:
-	/* Stack location is first item in the TCB. */
-	movl 	pxCurrentTCB, %eax
-	movl	(%eax), %esp
-
-	.if configSUPPORT_FPU == 1
-
-		/* Restore address of task's FPU context buffer. */
-		pop 	pucPortTaskFPUContextBuffer
-
-		/* If the task has a buffer allocated in which its FPU context is saved,
-		then restore it now. */
-		movl	pucPortTaskFPUContextBuffer, %eax
-		test	%eax, %eax
-		je		1f
-		frstor	( %eax )
-		1:
-	.endif
-
-	2:
-	popa
-
-.endm
-/*-----------------------------------------------------------*/
-
-.macro portFREERTOS_INTERRUPT_EXIT
-
-	portINTERRUPT_EPILOGUE
-	/* EOI. */
-	movl	$0x00, (0xFEE000B0)
-	iret
-
-.endm
diff --git a/FreeRTOS/Source/portable/GCC/IA32_flat/port.c b/FreeRTOS/Source/portable/GCC/IA32_flat/port.c
deleted file mode 100755
index 96f88eb..0000000
--- a/FreeRTOS/Source/portable/GCC/IA32_flat/port.c
+++ /dev/null
@@ -1,686 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#if( configISR_STACK_SIZE < ( configMINIMAL_STACK_SIZE * 2 ) )
-	#warning configISR_STACK_SIZE is probably too small!
-#endif /* ( configISR_STACK_SIZE < configMINIMAL_STACK_SIZE * 2 ) */
-
-#if( ( configMAX_API_CALL_INTERRUPT_PRIORITY > portMAX_PRIORITY ) || ( configMAX_API_CALL_INTERRUPT_PRIORITY < 2 ) )
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be between 2 and 15
-#endif
-
-#if( ( configSUPPORT_FPU == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
-	#error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port with an FPU
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
-
-/* Only the IF bit is set so tasks start with interrupts enabled. */
-#define portINITIAL_EFLAGS				( 0x200UL )
-
-/* Error interrupts are at the highest priority vectors. */
-#define portAPIC_LVT_ERROR_VECTOR 		( 0xfe )
-#define portAPIC_SPURIOUS_INT_VECTOR 	( 0xff )
-
-/* EFLAGS bits. */
-#define portEFLAGS_IF					( 0x200UL )
-
-/* FPU context size if FSAVE is used. */
-#define portFPU_CONTEXT_SIZE_BYTES 		108
-
-/* The expected size of each entry in the IDT.  Used to check structure packing
- is set correctly. */
-#define portEXPECTED_IDT_ENTRY_SIZE		8
-
-/* Default flags setting for entries in the IDT. */
-#define portIDT_FLAGS					( 0x8E )
-
-/* This is the lowest possible ISR vector available to application code. */
-#define portAPIC_MIN_ALLOWABLE_VECTOR	( 0x20 )
-
-/* If configASSERT() is defined then the system stack is filled with this value
-to allow for a crude stack overflow check. */
-#define portSTACK_WORD					( 0xecececec )
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing.
- */
-extern void vPortStartFirstTask( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*
- * Complete one descriptor in the IDT.
- */
-static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags );
-
-/*
- * The default handler installed in each IDT position.
- */
-extern void vPortCentralInterruptWrapper( void );
-
-/*
- * Handler for portYIELD().
- */
-extern void vPortYieldCall( void );
-
-/*
- * Configure the APIC to generate the RTOS tick.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * Tick interrupt handler.
- */
-extern void vPortTimerHandler( void );
-
-/*
- * Check an interrupt vector is not too high, too low, in use by FreeRTOS, or
- * already in use by the application.
- */
-static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting.  This
-variable must be initialised to a non zero value to ensure interrupts don't
-inadvertently become unmasked before the scheduler starts. It is set to zero
-before the first task starts executing. */
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/* A structure used to map the various fields of an IDT entry into separate
-structure members. */
-struct IDTEntry
-{
-	uint16_t usISRLow;				/* Low 16 bits of handler address. */
-	uint16_t usSegmentSelector;		/* Flat model means this is not changed. */
-	uint8_t ucZero;					/* Must be set to zero. */
-	uint8_t ucFlags;				/* Flags for this entry. */
-	uint16_t usISRHigh;				/* High 16 bits of handler address. */
-} __attribute__( ( packed ) );
-typedef struct IDTEntry IDTEntry_t;
-
-
-/* Use to pass the location of the IDT to the CPU. */
-struct IDTPointer
-{
-   uint16_t usTableLimit;
-   uint32_t ulTableBase;                /* The address of the first entry in xInterruptDescriptorTable. */
-} __attribute__( ( __packed__ ) );
-typedef struct IDTPointer IDTPointer_t;
-
-/* The IDT itself. */
-static __attribute__ ( ( aligned( 32 ) ) ) IDTEntry_t xInterruptDescriptorTable[ portNUM_VECTORS ];
-
-#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
-
-	/* A table in which application defined interrupt handlers are stored.  These
-	are called by the central interrupt handler if a common interrupt entry
-	point it used. */
-	static ISR_Handler_t xInterruptHandlerTable[ portNUM_VECTORS ] = { NULL };
-
-#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
-
-#if ( configSUPPORT_FPU == 1 )
-
-	/* Saved as part of the task context.  If pucPortTaskFPUContextBuffer is NULL
-	then the task does not have an FPU context.  If pucPortTaskFPUContextBuffer is
-	not NULL then it points to a buffer into which the FPU context can be saved. */
-	uint8_t *pucPortTaskFPUContextBuffer __attribute__((used)) = pdFALSE;
-
-#endif /* configSUPPORT_FPU */
-
-/* The stack used by interrupt handlers. */
-static uint32_t ulSystemStack[ configISR_STACK_SIZE ] __attribute__((used))  = { 0 };
-
-/* Don't use the very top of the system stack so the return address
-appears as 0 if the debugger tries to unwind the stack. */
-volatile uint32_t ulTopOfSystemStack __attribute__((used)) = ( uint32_t ) &( ulSystemStack[ configISR_STACK_SIZE - 5 ] );
-
-/* If a yield is requested from an interrupt or from a critical section then
-the yield is not performed immediately, and ulPortYieldPending is set to pdTRUE
-instead to indicate the yield should be performed at the end of the interrupt
-when the critical section is exited. */
-volatile uint32_t ulPortYieldPending __attribute__((used)) = pdFALSE;
-
-/* Counts the interrupt nesting depth.  Used to know when to switch to the
-interrupt/system stack and when to save/restore a complete context. */
-volatile uint32_t ulInterruptNesting __attribute__((used)) = 0;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint32_t ulCodeSegment;
-
-	/* Setup the initial stack as expected by the portFREERTOS_INTERRUPT_EXIT macro. */
-
-	*pxTopOfStack = 0x00;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x00;
-	pxTopOfStack--;
-
-	/* Parameters first. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;
-	pxTopOfStack--;
-
-	/* There is nothing to return to so assert if attempting to use the return
-	address. */
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;
-	pxTopOfStack--;
-
-	/* iret used to start the task pops up to here. */
-	*pxTopOfStack = portINITIAL_EFLAGS;
-	pxTopOfStack--;
-
-	/* CS */
-	__asm volatile( "movl %%cs, %0" : "=r" ( ulCodeSegment ) );
-	*pxTopOfStack = ulCodeSegment;
-	pxTopOfStack--;
-
-	/* First instruction in the task. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-
-	/* General purpose registers as expected by a POPA instruction. */
-	*pxTopOfStack = 0xEA;
-	pxTopOfStack--;
-
-	*pxTopOfStack = 0xEC;
-	pxTopOfStack--;
-
-	*pxTopOfStack = 0xED1; /* EDX */
-	pxTopOfStack--;
-
-	*pxTopOfStack = 0xEB1; /* EBX */
-	pxTopOfStack--;
-
-	/* Hole for ESP. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = 0x00; /* EBP */
-	pxTopOfStack--;
-
-	*pxTopOfStack = 0xE5; /* ESI */
-	pxTopOfStack--;
-
-	*pxTopOfStack = 0xeeeeeeee; /* EDI */
-
-	#if ( configSUPPORT_FPU == 1 )
-	{
-		pxTopOfStack--;
-
-		/* Buffer for FPU context, which is initialised to NULL as tasks are not
-		created with an FPU context. */
-		*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
-	}
-	#endif /* configSUPPORT_FPU */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetInterruptGate( uint8_t ucNumber, ISR_Handler_t pxHandlerFunction, uint8_t ucFlags )
-{
-uint16_t usCodeSegment;
-uint32_t ulBase = ( uint32_t ) pxHandlerFunction;
-
-	xInterruptDescriptorTable[ ucNumber ].usISRLow = ( uint16_t ) ( ulBase & USHRT_MAX );
-	xInterruptDescriptorTable[ ucNumber ].usISRHigh = ( uint16_t ) ( ( ulBase >> 16UL ) & USHRT_MAX );
-
-	/* When the flat model is used the CS will never change. */
-	__asm volatile( "mov %%cs, %0" : "=r" ( usCodeSegment ) );
-	xInterruptDescriptorTable[ ucNumber ].usSegmentSelector = usCodeSegment;
-	xInterruptDescriptorTable[ ucNumber ].ucZero = 0;
-	xInterruptDescriptorTable[ ucNumber ].ucFlags = ucFlags;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetupIDT( void )
-{
-uint32_t ulNum;
-IDTPointer_t xIDT;
-
-	#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
-	{
-		for( ulNum = 0; ulNum < portNUM_VECTORS; ulNum++ )
-		{
-			/* If a handler has not already been installed on this vector. */
-			if( ( xInterruptDescriptorTable[ ulNum ].usISRLow == 0x00 ) && ( xInterruptDescriptorTable[ ulNum ].usISRHigh == 0x00 ) )
-			{
-				prvSetInterruptGate( ( uint8_t ) ulNum, vPortCentralInterruptWrapper, portIDT_FLAGS );
-			}
-		}
-	}
-	#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
-
-	/* Set IDT address. */
-	xIDT.ulTableBase = ( uint32_t ) xInterruptDescriptorTable;
-	xIDT.usTableLimit = sizeof( xInterruptDescriptorTable ) - 1;
-
-	/* Set IDT in CPU. */
-	__asm volatile( "lidt %0" :: "m" (xIDT) );
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-extern void vPortAPICErrorHandlerWrapper( void );
-extern void vPortAPICSpuriousHandler( void );
-
-	/* Initialise LAPIC to a well known state. */
-	portAPIC_LDR = 0xFFFFFFFF;
-	portAPIC_LDR = ( ( portAPIC_LDR & 0x00FFFFFF ) | 0x00000001 );
-	portAPIC_LVT_TIMER = portAPIC_DISABLE;
-	portAPIC_LVT_PERF = portAPIC_NMI;
-	portAPIC_LVT_LINT0 = portAPIC_DISABLE;
-	portAPIC_LVT_LINT1 = portAPIC_DISABLE;
-	portAPIC_TASK_PRIORITY = 0;
-
-	/* Install APIC timer ISR vector. */
-	prvSetInterruptGate( ( uint8_t ) portAPIC_TIMER_INT_VECTOR, vPortTimerHandler, portIDT_FLAGS );
-
-	/* Install API error handler. */
-	prvSetInterruptGate( ( uint8_t ) portAPIC_LVT_ERROR_VECTOR, vPortAPICErrorHandlerWrapper, portIDT_FLAGS );
-
-	/* Install Yield handler. */
-	prvSetInterruptGate( ( uint8_t ) portAPIC_YIELD_INT_VECTOR, vPortYieldCall, portIDT_FLAGS );
-
-	/* Install spurious interrupt vector. */
-	prvSetInterruptGate( ( uint8_t ) portAPIC_SPURIOUS_INT_VECTOR, vPortAPICSpuriousHandler, portIDT_FLAGS );
-
-	/* Enable the APIC, mapping the spurious interrupt at the same time. */
-	portAPIC_SPURIOUS_INT = portAPIC_SPURIOUS_INT_VECTOR | portAPIC_ENABLE_BIT;
-
-	/* Set timer error vector. */
-	portAPIC_LVT_ERROR = portAPIC_LVT_ERROR_VECTOR;
-
-	/* Set the interrupt frequency. */
-	portAPIC_TMRDIV = portAPIC_DIV_16;
-	portAPIC_TIMER_INITIAL_COUNT = ( ( configCPU_CLOCK_HZ >> 4UL ) / configTICK_RATE_HZ ) - 1UL;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-BaseType_t xWord;
-
-	/* Some versions of GCC require the -mno-ms-bitfields command line option
-	for packing to work. */
-	configASSERT( sizeof( struct IDTEntry ) == portEXPECTED_IDT_ENTRY_SIZE );
-
-	/* Fill part of the system stack with a known value to help detect stack
-	overflow.  A few zeros are left so GDB doesn't get confused unwinding
-	the stack. */
-	for( xWord = 0; xWord < configISR_STACK_SIZE - 20; xWord++ )
-	{
-		ulSystemStack[ xWord ] = portSTACK_WORD;
-	}
-
-	/* Initialise Interrupt Descriptor Table (IDT). */
-	vPortSetupIDT();
-
-	/* Initialise LAPIC and install system handlers. */
-	prvSetupTimerInterrupt();
-
-	/* Make sure the stack used by interrupts is aligned. */
-	ulTopOfSystemStack &= ~portBYTE_ALIGNMENT_MASK;
-
-	ulCriticalNesting = 0;
-
-	/* Enable LAPIC Counter.*/
-	portAPIC_LVT_TIMER = portAPIC_TIMER_PERIODIC | portAPIC_TIMER_INT_VECTOR;
-
-	/* Sometimes needed. */
-	portAPIC_TMRDIV = portAPIC_DIV_16;
-
-	/* Should not return from the following function as the scheduler will then
-	be executing the tasks. */
-	vPortStartFirstTask();
-
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	if( ulCriticalNesting == 0 )
-	{
-		#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
-		{
-			__asm volatile( "cli" );
-		}
-		#else
-		{
-			portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
-			configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
-		}
-		#endif
-	}
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as the critical section is being
-		exited. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then all interrupt
-		priorities must be re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Critical nesting has reached zero so all interrupt priorities
-			should be unmasked. */
-			#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
-			{
-				__asm volatile( "sti" );
-			}
-			#else
-			{
-				portAPIC_TASK_PRIORITY = 0;
-			}
-			#endif
-
-			/* If a yield was pended from within the critical section then
-			perform the yield now. */
-			if( ulPortYieldPending != pdFALSE )
-			{
-				ulPortYieldPending = pdFALSE;
-				__asm volatile( portYIELD_INTERRUPT );
-			}
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortSetInterruptMask( void )
-{
-volatile uint32_t ulOriginalMask;
-
-	/* Set mask to max syscall priority. */
-	#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
-	{
-		/* Return whether interrupts were already enabled or not.  Pop adjusts
-		the stack first. */
-		__asm volatile( "pushf		\t\n"
-						"pop %0		\t\n"
-						"cli			"
-						: "=rm" (ulOriginalMask) :: "memory" );
-
-		ulOriginalMask &= portEFLAGS_IF;
-	}
-	#else
-	{
-		/* Return original mask. */
-		ulOriginalMask = portAPIC_TASK_PRIORITY;
-		portAPIC_TASK_PRIORITY = portMAX_API_CALL_PRIORITY;
-		configASSERT( portAPIC_TASK_PRIORITY == portMAX_API_CALL_PRIORITY );
-	}
-	#endif
-
-	return ulOriginalMask;
-}
-/*-----------------------------------------------------------*/
-
-void vPortClearInterruptMask( uint32_t ulNewMaskValue )
-{
-	#if( configMAX_API_CALL_INTERRUPT_PRIORITY == portMAX_PRIORITY )
-	{
-		if( ulNewMaskValue != pdFALSE )
-		{
-			__asm volatile( "sti" );
-		}
-	}
-	#else
-	{
-		portAPIC_TASK_PRIORITY = ulNewMaskValue;
-		configASSERT( portAPIC_TASK_PRIORITY == ulNewMaskValue );
-	}
-	#endif
-}
-/*-----------------------------------------------------------*/
-
-#if ( configSUPPORT_FPU == 1 )
-
-	void vPortTaskUsesFPU( void )
-	{
-		/* A task is registering the fact that it needs an FPU context.  Allocate a
-		buffer into which the context can be saved. */
-		pucPortTaskFPUContextBuffer = ( uint8_t * ) pvPortMalloc( portFPU_CONTEXT_SIZE_BYTES );
-		configASSERT( pucPortTaskFPUContextBuffer );
-
-		/* Initialise the floating point registers. */
-		__asm volatile(	"fninit" );
-	}
-
-#endif /* configSUPPORT_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortAPICErrorHandler( void )
-{
-/* Variable to hold the APIC error status for viewing in the debugger. */
-volatile uint32_t ulErrorStatus = 0;
-
-	portAPIC_ERROR_STATUS = 0;
-	ulErrorStatus = portAPIC_ERROR_STATUS;
-	( void ) ulErrorStatus;
-
-	/* Force an assert. */
-	configASSERT( ulCriticalNesting == ~0UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
-
-	void vPortCentralInterruptHandler( uint32_t ulVector )
-	{
-		if( ulVector < portNUM_VECTORS )
-		{
-			if( xInterruptHandlerTable[ ulVector ] != NULL )
-			{
-				( xInterruptHandlerTable[ ulVector ] )();
-			}
-		}
-
-		/* Check for a system stack overflow. */
-		configASSERT( ulSystemStack[ 10 ] == portSTACK_WORD );
-		configASSERT( ulSystemStack[ 12 ] == portSTACK_WORD );
-		configASSERT( ulSystemStack[ 14 ] == portSTACK_WORD );
-	}
-
-#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1 )
-
-	BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
-	{
-	BaseType_t xReturn;
-
-		xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
-
-		if( xReturn != pdFAIL )
-		{
-			/* Save the handler passed in by the application in the vector number
-			passed in.  The addresses are then called from the central interrupt
-			handler. */
-			xInterruptHandlerTable[ ulVectorNumber ] = pxHandler;
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber )
-{
-BaseType_t xReturn;
-
-	xReturn = prvCheckValidityOfVectorNumber( ulVectorNumber );
-
-	if( xReturn != pdFAIL )
-	{
-		taskENTER_CRITICAL();
-		{
-			/* Update the IDT to include the application defined handler. */
-			prvSetInterruptGate( ( uint8_t ) ulVectorNumber, ( ISR_Handler_t ) pxHandler, portIDT_FLAGS );
-		}
-		taskEXIT_CRITICAL();
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvCheckValidityOfVectorNumber( uint32_t ulVectorNumber )
-{
-BaseType_t xReturn;
-
-	/* Check validity of vector number. */
-	if( ulVectorNumber >= portNUM_VECTORS )
-	{
-		/* Too high. */
-		xReturn = pdFAIL;
-	}
-	else if( ulVectorNumber < portAPIC_MIN_ALLOWABLE_VECTOR )
-	{
-		/* Too low. */
-		xReturn = pdFAIL;
-	}
-	else if( ulVectorNumber == portAPIC_TIMER_INT_VECTOR )
-	{
-		/* In use by FreeRTOS. */
-		xReturn = pdFAIL;
-	}
-	else if( ulVectorNumber == portAPIC_YIELD_INT_VECTOR )
-	{
-		/* In use by FreeRTOS. */
-		xReturn = pdFAIL;
-	}
-	else if( ulVectorNumber == portAPIC_LVT_ERROR_VECTOR )
-	{
-		/* In use by FreeRTOS. */
-		xReturn = pdFAIL;
-	}
-	else if( ulVectorNumber == portAPIC_SPURIOUS_INT_VECTOR )
-	{
-		/* In use by FreeRTOS. */
-		xReturn = pdFAIL;
-	}
-	else if( xInterruptHandlerTable[ ulVectorNumber ] != NULL )
-	{
-		/* Already in use by the application. */
-		xReturn = pdFAIL;
-	}
-	else
-	{
-		xReturn = pdPASS;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vGenerateYieldInterrupt( void )
-{
-	__asm volatile( portYIELD_INTERRUPT );
-}
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/IA32_flat/portASM.S b/FreeRTOS/Source/portable/GCC/IA32_flat/portASM.S
deleted file mode 100755
index fd5579b..0000000
--- a/FreeRTOS/Source/portable/GCC/IA32_flat/portASM.S
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-.file "portASM.S"
-#include "FreeRTOSConfig.h"
-#include "ISR_Support.h"
-
-	.extern pxCurrentTCB
-	.extern vTaskSwitchContext
-	.extern vPortCentralInterruptHandler
-	.extern xTaskIncrementTick
-	.extern vPortAPICErrorHandler
-	.extern pucPortTaskFPUContextBuffer
-	.extern ulPortYieldPending
-
-	.global vPortStartFirstTask
-	.global vPortCentralInterruptWrapper
-	.global vPortAPICErrorHandlerWrapper
-	.global vPortTimerHandler
-	.global vPortYieldCall
-	.global vPortAPICSpuriousHandler
-
-	.text
-
-/*-----------------------------------------------------------*/
-
-.align 4
-.func vPortYieldCall
-vPortYieldCall:
-	/* Save general purpose registers. */
-	pusha
-
-	.if configSUPPORT_FPU == 1
-
-		/* If the task has a buffer allocated to save the FPU context then save
-		the FPU context now. */
-		movl	pucPortTaskFPUContextBuffer, %eax
-		test	%eax, %eax
-		je		1f
-		fnsave	( %eax )
-		fwait
-
-		1:
-
-		/* Save the address of the FPU context, if any. */
-		push	pucPortTaskFPUContextBuffer
-
-	.endif /* configSUPPORT_FPU */
-
-	/* Find the TCB. */
-	movl 	pxCurrentTCB, %eax
-
-	/* Stack location is first item in the TCB. */
-	movl	%esp, (%eax)
-
-	call vTaskSwitchContext
-
-	/* Find the location of pxCurrentTCB again - a callee saved register could
-	be used in place of eax to prevent this second load, but that then relies
-	on the compiler and other asm code. */
-	movl 	pxCurrentTCB, %eax
-	movl	(%eax), %esp
-
-	.if configSUPPORT_FPU == 1
-
-		/* Restore address of task's FPU context buffer. */
-		pop 	pucPortTaskFPUContextBuffer
-
-		/* If the task has a buffer allocated in which its FPU context is saved,
-		then restore it now. */
-		movl	pucPortTaskFPUContextBuffer, %eax
-		test	%eax, %eax
-		je		1f
-		frstor	( %eax )
-		1:
-	.endif
-
-	popa
-	iret
-
-.endfunc
-/*-----------------------------------------------------------*/
-
-.align 4
-.func vPortStartFirstTask
-vPortStartFirstTask:
-
-	/* Find the TCB. */
-	movl 	pxCurrentTCB, %eax
-
-	/* Stack location is first item in the TCB. */
-	movl	(%eax), %esp
-
-	/* Restore FPU context flag. */
-	.if configSUPPORT_FPU == 1
-
-		pop 	pucPortTaskFPUContextBuffer
-
-	.endif /* configSUPPORT_FPU */
-
-	/* Restore general purpose registers. */
-	popa
-	iret
-.endfunc
-/*-----------------------------------------------------------*/
-
-.align 4
-.func vPortAPICErrorHandlerWrapper
-vPortAPICErrorHandlerWrapper:
-	pusha
-	call	vPortAPICErrorHandler
-	popa
-	/* EOI. */
-	movl	$0x00, (0xFEE000B0)
-	iret
-.endfunc
-/*-----------------------------------------------------------*/
-
-.align 4
-.func vPortTimerHandler
-vPortTimerHandler:
-
-	/* Save general purpose registers. */
-	pusha
-
-	/* Interrupts are not nested, so save the rest of the task context. */
-	.if configSUPPORT_FPU == 1
-
-		/* If the task has a buffer allocated to save the FPU context then save the
-		FPU context now. */
-		movl	pucPortTaskFPUContextBuffer, %eax
-		test	%eax, %eax
-		je		1f
-		fnsave	( %eax ) /* Save FLOP context into ucTempFPUBuffer array. */
-		fwait
-
-		1:
-		/* Save the address of the FPU context, if any. */
-		push	pucPortTaskFPUContextBuffer
-
-	.endif /* configSUPPORT_FPU */
-
-	/* Find the TCB. */
-	movl 	pxCurrentTCB, %eax
-
-	/* Stack location is first item in the TCB. */
-	movl	%esp, (%eax)
-
-	/* Switch stacks. */
-	movl 	ulTopOfSystemStack, %esp
-	movl	%esp, %ebp
-
-	/* Increment nesting count. */
-	add 	$1, ulInterruptNesting
-
-	call 	xTaskIncrementTick
-
-	sti
-
-	/* Is a switch to another task required? */
-	test	%eax, %eax
-	je		_skip_context_switch
-	cli
-	call	vTaskSwitchContext
-
-_skip_context_switch:
-	cli
-
-	/* Decrement the variable used to determine if a switch to a system
-	stack is necessary. */
-	sub		$1, ulInterruptNesting
-
-	/* Stack location is first item in the TCB. */
-	movl 	pxCurrentTCB, %eax
-	movl	(%eax), %esp
-
-	.if configSUPPORT_FPU == 1
-
-		/* Restore address of task's FPU context buffer. */
-		pop 	pucPortTaskFPUContextBuffer
-
-		/* If the task has a buffer allocated in which its FPU context is saved,
-		then restore it now. */
-		movl	pucPortTaskFPUContextBuffer, %eax
-		test	%eax, %eax
-		je		1f
-		frstor	( %eax )
-		1:
-	.endif
-
-	popa
-
-	/* EOI. */
-	movl	$0x00, (0xFEE000B0)
-	iret
-
-.endfunc
-/*-----------------------------------------------------------*/
-
-.if configUSE_COMMON_INTERRUPT_ENTRY_POINT == 1
-
-	.align 4
-	.func vPortCentralInterruptWrapper
-	vPortCentralInterruptWrapper:
-
-		portFREERTOS_INTERRUPT_ENTRY
-
-		movl $0xFEE00170, %eax 			/* Highest In Service Register (ISR) long word. */
-		movl $8, %ecx					/* Loop counter. */
-
-	next_isr_long_word:
-		test %ecx, %ecx					/* Loop counter reached 0? */
-		je wrapper_epilogue				/* Looked at all ISR registers without finding a bit set. */
-		sub $1, %ecx					/* Sub 1 from loop counter. */
-		movl (%eax), %ebx				/* Load next ISR long word. */
-		sub $0x10, %eax					/* Point to next ISR long word in case no bits are set in the current long word. */
-		test %ebx, %ebx					/* Are there any bits set? */
-		je next_isr_long_word			/* Look at next ISR long word if no bits were set. */
-		sti
-		bsr %ebx, %ebx					/* A bit was set, which one? */
-		movl $32, %eax					/* Destination operand for following multiplication. */
-		mul %ecx						/* Calculate base vector for current register, 32 vectors per register. */
-		add %ebx, %eax					/* Add bit offset into register to get final vector number. */
-		push %eax						/* Vector number is function parameter. */
-		call vPortCentralInterruptHandler
-		pop %eax						/* Remove parameter. */
-
-	wrapper_epilogue:
-		portFREERTOS_INTERRUPT_EXIT
-
-	.endfunc
-
-.endif /* configUSE_COMMON_INTERRUPT_ENTRY_POINT */
-/*-----------------------------------------------------------*/
-
-.align 4
-.func vPortAPISpuriousHandler
-vPortAPICSpuriousHandler:
-	iret
-
-.endfunc
-
-.end
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/IA32_flat/portmacro.h b/FreeRTOS/Source/portable/GCC/IA32_flat/portmacro.h
deleted file mode 100755
index 913e73a..0000000
--- a/FreeRTOS/Source/portable/GCC/IA32_flat/portmacro.h
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-	extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( ( TickType_t ) 0xffffffffUL )
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			32
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* The interrupt priority (for vectors 16 to 255) is determined using vector/16.
-The quotient is rounded to the nearest integer with 1 being the lowest priority
-and 15 is the highest.  Therefore the following two interrupts are at the lowest
-priority.  *NOTE 1* If the yield vector is changed then it must also be changed
-in the portYIELD_INTERRUPT definition immediately below. */
-#define portAPIC_TIMER_INT_VECTOR 		( 0x21 )
-#define portAPIC_YIELD_INT_VECTOR 		( 0x20 )
-
-/* Build yield interrupt instruction. */
-#define portYIELD_INTERRUPT "int $0x20"
-
-/* APIC register addresses. */
-#define portAPIC_EOI					( *( ( volatile uint32_t * ) 0xFEE000B0UL ) )
-
-/* APIC bit definitions. */
-#define portAPIC_ENABLE_BIT				( 1UL << 8UL )
-#define portAPIC_TIMER_PERIODIC 		( 1UL << 17UL )
-#define portAPIC_DISABLE 				( 1UL << 16UL )
-#define portAPIC_NMI 					( 4 << 8)
-#define portAPIC_DIV_16 				( 0x03 )
-
-/* Define local API register addresses. */
-#define portAPIC_ID_REGISTER			( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x20UL  ) ) )
-#define portAPIC_SPURIOUS_INT			( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xF0UL  ) ) )
-#define portAPIC_LVT_TIMER				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x320UL ) ) )
-#define portAPIC_TIMER_INITIAL_COUNT	( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x380UL ) ) )
-#define portAPIC_TIMER_CURRENT_COUNT	( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x390UL ) ) )
-#define portAPIC_TASK_PRIORITY			( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x80UL  ) ) )
-#define portAPIC_LVT_ERROR				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x370UL ) ) )
-#define portAPIC_ERROR_STATUS			( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x280UL ) ) )
-#define portAPIC_LDR	 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xD0UL  ) ) )
-#define portAPIC_TMRDIV 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x3E0UL ) ) )
-#define portAPIC_LVT_PERF 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x340UL ) ) )
-#define portAPIC_LVT_LINT0 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x350UL ) ) )
-#define portAPIC_LVT_LINT1 				( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0x360UL ) ) )
-
-/* Don't yield if inside a critical section - instead hold the yield pending
-so it is performed when the critical section is exited. */
-#define portYIELD() 								\
-{													\
-extern volatile uint32_t ulCriticalNesting;			\
-extern volatile uint32_t ulPortYieldPending;		\
-	if( ulCriticalNesting != 0 )					\
-	{												\
-		ulPortYieldPending = pdTRUE;				\
-	}												\
-	else											\
-	{												\
-		__asm volatile( portYIELD_INTERRUPT );		\
-	}												\
-}
-
-/* Called at the end of an ISR that can cause a context switch - pend a yield if
-xSwithcRequired is not false. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )	\
-{													\
-extern volatile uint32_t ulPortYieldPending;		\
-	if( xSwitchRequired != pdFALSE )				\
-	{												\
-		ulPortYieldPending = 1; 				 	\
-	}												\
-}
-
-/* Same as portEND_SWITCHING_ISR() - take your pick which name to use. */
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-
-/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
-
-/* Critical sections for use in interrupts. */
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask( x )
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-
-/* These macros do not globally disable/enable interrupts.  They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-#define portDISABLE_INTERRUPTS()	__asm volatile( "cli" )
-#define portENABLE_INTERRUPTS()		__asm volatile( "sti" )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
-
-/* Architecture specific optimisations. */
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )	\
-		__asm volatile(	"bsr %1, %0\n\t" 									\
-						:"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )
-
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#define portNOP() __asm volatile( "NOP" )
-
-/*-----------------------------------------------------------
- * Misc
- *----------------------------------------------------------*/
-
-#define portNUM_VECTORS		256
-#define portMAX_PRIORITY	15
-typedef void ( *ISR_Handler_t ) ( void );
-
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
-#ifndef configSUPPORT_FPU
-	#define configSUPPORT_FPU 0
-#endif
-
-#if configSUPPORT_FPU == 1
-	void vPortTaskUsesFPU( void );
-	#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-#endif
-
-/* See the comments under the configUSE_COMMON_INTERRUPT_ENTRY_POINT definition
-below. */
-BaseType_t xPortRegisterCInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
-BaseType_t xPortInstallInterruptHandler( ISR_Handler_t pxHandler, uint32_t ulVectorNumber );
-
-#ifndef configAPIC_BASE
-	/* configAPIC_BASE_ADDRESS sets the base address of the local APIC.  It can
-	be overridden in FreeRTOSConfig.h should it not be constant. */
-	#define configAPIC_BASE	0xFEE00000UL
-#endif
-
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	/* The FreeRTOS scheduling algorithm selects the task that will enter the
-	Running state.  configUSE_PORT_OPTIMISED_TASK_SELECTION is used to set how
-	that is done.
-
-	If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 0 then the task to
-	enter the Running state is selected using a portable algorithm written in
-	C.  This is the slowest method, but the algorithm does not restrict the
-	maximum number of unique RTOS task priorities that are available.
-
-	If configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 then the task to
-	enter the Running state is selected using a single assembly instruction.
-	This is the fastest method, but restricts the maximum number of unique RTOS
-	task priorities to 32 (the same task priority can be assigned to any number
-	of RTOS	tasks). */
-	#warning configUSE_PORT_OPTIMISED_TASK_SELECTION was not defined in FreeRTOSConfig.h and has been defaulted to 1
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#ifndef configUSE_COMMON_INTERRUPT_ENTRY_POINT
-	/* There are two ways of implementing interrupt handlers:
-
-		1) As standard C functions -
-
-		This method can only be used if configUSE_COMMON_INTERRUPT_ENTRY_POINT
-		is set to 1.  The C function is installed using
-		xPortRegisterCInterruptHandler().
-
-		This is the simplest of the two methods but incurs a slightly longer
-		interrupt entry time.
-
-		2) By using an assembly stub that wraps the handler in the FreeRTOS
-		   portFREERTOS_INTERRUPT_ENTRY and portFREERTOS_INTERRUPT_EXIT macros.
-
-		This method can always be used.  It is slightly more complex than
-		method 1 but benefits from a faster interrupt entry time. */
-	#warning configUSE_COMMON_INTERRUPT_ENTRY_POINT was not defined in FreeRTOSConfig.h and has been defaulted to 1.
-	#define configUSE_COMMON_INTERRUPT_ENTRY_POINT	1
-#endif
-
-#ifndef configISR_STACK_SIZE
-	/* Interrupt entry code will switch the stack in use to a dedicated system
-	stack.
-
-	configISR_STACK_SIZE defines the number of 32-bit values that can be stored
-	on the system stack, and must be large enough to hold a potentially nested
-	interrupt stack frame. */
-
-	#error configISR_STACK_SIZE was not defined in FreeRTOSConfig.h.
-#endif
-
-#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
-	/* Interrupt safe FreeRTOS functions (those that end in "FromISR" must not
-	be called from an interrupt that has a priority above that set by
-	configMAX_API_CALL_INTERRUPT_PRIORITY.  */
-	#warning configMAX_API_CALL_INTERRUPT_PRIORITY was not defined in FreeRTOSConfig.h and has been defaulted to 10
-	#define configMAX_API_CALL_INTERRUPT_PRIORITY 10
-#endif
-
-#ifndef configSUPPORT_FPU
-	#warning configSUPPORT_FPU was not defined in FreeRTOSConfig.h and has been defaulted to 0
-	#define configSUPPORT_FPU 0
-#endif
-
-/* The value written to the task priority register to raise the interrupt mask
-to the maximum from which FreeRTOS API calls can be made. */
-#define portAPIC_PRIORITY_SHIFT		( 4UL )
-#define portAPIC_MAX_SUB_PRIORITY	( 0x0fUL )
-#define portMAX_API_CALL_PRIORITY		( ( configMAX_API_CALL_INTERRUPT_PRIORITY << portAPIC_PRIORITY_SHIFT ) | portAPIC_MAX_SUB_PRIORITY )
-
-/* Asserts if interrupt safe FreeRTOS functions are called from a priority
-above the max system call interrupt priority. */
-#define portAPIC_PROCESSOR_PRIORITY	( *( ( volatile uint32_t * ) ( configAPIC_BASE + 0xA0UL  ) ) )
-#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( portAPIC_PROCESSOR_PRIORITY ) <= ( portMAX_API_CALL_PRIORITY ) )
-
-#ifdef __cplusplus
-	} /* extern C */
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/MCF5235/port.c b/FreeRTOS/Source/portable/GCC/MCF5235/port.c
deleted file mode 100755
index 1945a75..0000000
--- a/FreeRTOS/Source/portable/GCC/MCF5235/port.c
+++ /dev/null
@@ -1,285 +0,0 @@
-/*
-    FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
-    MCF5235 Port - Copyright (C) 2006 Christian Walter.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License** as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    FreeRTOS is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with FreeRTOS; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes FreeRTOS, without being obliged to provide
-    the source code for any proprietary components.  See the licensing section
-    of http://www.FreeRTOS.org for full details of how and when the exception
-    can be applied.
-
-    ***************************************************************************
-    ***************************************************************************
-    *                                                                         *
-    * Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *
-	*                                                                         *
-	* This is a concise, step by step, 'hands on' guide that describes both   *
-	* general multitasking concepts and FreeRTOS specifics. It presents and   *
-	* explains numerous examples that are written using the FreeRTOS API.     *
-	* Full source code for all the examples is provided in an accompanying    *
-	* .zip file.                                                              *
-    *                                                                         *
-    ***************************************************************************
-    ***************************************************************************
-
-	Please ensure to read the configuration and relevant port sections of the
-	online documentation.
-
-	http://www.FreeRTOS.org - Documentation, latest information, license and 
-	contact details.
-
-	http://www.SafeRTOS.com - A version that is certified for use in safety 
-	critical systems.
-
-	http://www.OpenRTOS.com - Commercial support, development, porting, 
-	licensing and training services.
-*/
-
-#include 
-
-#include "FreeRTOS.h"
-#include "FreeRTOSConfig.h"
-#include "task.h"
-
-/* ------------------------ Types ----------------------------------------- */
-typedef volatile uint32_t vuint32;
-typedef volatile uint16_t vuint16;
-typedef volatile uint8_t vuint8;
-
-/* ------------------------ Defines --------------------------------------- */
-#define portVECTOR_TABLE                __RAMVEC
-#define portVECTOR_SYSCALL              ( 32 + portTRAP_YIELD )
-#define portVECTOR_TIMER                ( 64 + 36 )
-
-#define MCF_PIT_PRESCALER               512UL
-#define MCF_PIT_TIMER_TICKS             ( FSYS_2 / MCF_PIT_PRESCALER )
-#define MCF_PIT_MODULUS_REGISTER(freq)  ( MCF_PIT_TIMER_TICKS / ( freq ) - 1UL)
-
-#define MCF_PIT_PMR0                    ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150002 ] ) )
-#define MCF_PIT_PCSR0                   ( *( vuint16 * )( void * )( &__IPSBAR[ 0x150000 ] ) )
-#define MCF_PIT_PCSR_PRE(x)             ( ( ( x ) & 0x000F ) << 8 )
-#define MCF_PIT_PCSR_EN                 ( 0x0001 )
-#define MCF_PIT_PCSR_RLD                ( 0x0002 )
-#define MCF_PIT_PCSR_PIF                ( 0x0004 )
-#define MCF_PIT_PCSR_PIE                ( 0x0008 )
-#define MCF_PIT_PCSR_OVW                ( 0x0010 )
-#define MCF_INTC0_ICR36                 ( *( vuint8 * )( void * )( &__IPSBAR[ 0x000C64 ] ) )
-#define MCF_INTC0_IMRH                  ( *( vuint32 * )( void * )( &__IPSBAR[ 0x000C08 ] ) )
-#define MCF_INTC0_IMRH_INT_MASK36       ( 0x00000010 )
-#define MCF_INTC0_IMRH_MASKALL          ( 0x00000001 )
-#define MCF_INTC0_ICRn_IP(x)            ( ( ( x ) & 0x07 ) << 0 )
-#define MCF_INTC0_ICRn_IL(x)            ( ( ( x ) & 0x07 ) << 3 )
-
-#define portNO_CRITICAL_NESTING         ( ( uint32_t ) 0 )
-#define portINITIAL_CRITICAL_NESTING    ( ( uint32_t ) 10 )
-
-/* ------------------------ Static variables ------------------------------ */
-volatile uint32_t              ulCriticalNesting = portINITIAL_CRITICAL_NESTING;
-
-/* ------------------------ Static functions ------------------------------ */
-#if configUSE_PREEMPTION == 0
-static void prvPortPreemptiveTick ( void ) __attribute__ ((interrupt_handler));
-#else
-static void prvPortPreemptiveTick ( void );
-#endif
-
-/* ------------------------ Start implementation -------------------------- */
-
-StackType_t *
-pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode,
-                       void *pvParameters )
-{
-    /* Place the parameter on the stack in the expected location. */
-    *pxTopOfStack = ( StackType_t ) pvParameters;
-    pxTopOfStack--;
-
-    /* Place dummy return address on stack. Tasks should never terminate so
-     * we can set this to anything. */
-    *pxTopOfStack = ( StackType_t ) 0;
-    pxTopOfStack--;
-
-    /* Create a Motorola Coldfire exception stack frame. First comes the return
-     * address. */
-    *pxTopOfStack = ( StackType_t ) pxCode;
-    pxTopOfStack--;
-
-    /* Format, fault-status, vector number for exception stack frame. Task
-     * run in supervisor mode. */
-    *pxTopOfStack = 0x40002000UL | ( portVECTOR_SYSCALL + 32 ) << 18;
-    pxTopOfStack--;
-
-    /* Set the initial critical section nesting counter to zero. This value
-     * is used to restore the value of ulCriticalNesting. */
-    *pxTopOfStack = 0;
-    *pxTopOfStack--;
-
-    *pxTopOfStack = ( StackType_t ) 0xA6;    /* A6 / FP */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xA5;    /* A5 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xA4;    /* A4 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xA3;    /* A3 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xA2;    /* A2 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xA1;    /* A1 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xA0;    /* A0 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xD7;    /* D7 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xD6;    /* D6 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xD5;    /* D5 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xD4;    /* D4 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xD3;    /* D3 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xD2;    /* D2 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xD1;    /* D1 */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) 0xD0;    /* D0 */
-
-    return pxTopOfStack;
-}
-
-/*
- * Called by portYIELD() or taskYIELD() to manually force a context switch.
- */
-static void
-prvPortYield( void )
-{
-    asm volatile ( "move.w  #0x2700, %sr\n\t" );
-#if _GCC_USES_FP == 1
-    asm volatile ( "unlk %fp\n\t" );
-#endif
-     /* Perform the context switch.  First save the context of the current task. */
-    portSAVE_CONTEXT(  );
-
-    /* Find the highest priority task that is ready to run. */
-    vTaskSwitchContext(  );
-
-    /* Restore the context of the new task. */
-    portRESTORE_CONTEXT(  );
-}
-
-#if configUSE_PREEMPTION == 0
-/*
- * The ISR used for the scheduler tick depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-static void
-prvPortPreemptiveTick ( void )
-{
-    /* The cooperative scheduler requires a normal IRQ service routine to
-     * simply increment the system tick.
-     */
-
-    xTaskIncrementTick();
-    MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
-}
-
-#else
-
-static void
-prvPortPreemptiveTick( void )
-{
-    asm volatile ( "move.w  #0x2700, %sr\n\t" );
-#if _GCC_USES_FP == 1
-    asm volatile ( "unlk %fp\n\t" );
-#endif
-    portSAVE_CONTEXT(  );
-    MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIF;
-    if( xTaskIncrementTick() != pdFALSE )
-	{
-		vTaskSwitchContext(  );
-	}
-    portRESTORE_CONTEXT(  );
-}
-#endif
-
-void
-vPortEnterCritical()
-{
-    /* FIXME: We should store the old IPL here - How are we supposed to do
-     * this.
-     */
-    ( void )portSET_IPL( portIPL_MAX );
-
-    /* Now interrupts are disabled ulCriticalNesting can be accessed
-     * directly.  Increment ulCriticalNesting to keep a count of how many times
-     * portENTER_CRITICAL() has been called. */
-    ulCriticalNesting++;
-}
-
-void
-vPortExitCritical()
-{
-    if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-    {
-        /* Decrement the nesting count as we are leaving a critical section. */
-        ulCriticalNesting--;
-
-        /* If the nesting level has reached zero then interrupts should be
-        re-enabled. */
-        if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-        {
-            ( void )portSET_IPL( 0 );
-        }
-    }
-}
-
-BaseType_t
-xPortStartScheduler( void )
-{
-    extern void     ( *portVECTOR_TABLE[  ] ) (  );
-
-    /* Add entry in vector table for yield system call. */
-    portVECTOR_TABLE[ portVECTOR_SYSCALL ] = prvPortYield;
-    /* Add entry in vector table for periodic timer. */
-    portVECTOR_TABLE[ portVECTOR_TIMER ] = prvPortPreemptiveTick;
-
-    /* Configure the timer for the system clock. */
-    if ( configTICK_RATE_HZ > 0)
-    {
-        /* Configure prescaler */
-        MCF_PIT_PCSR0 = MCF_PIT_PCSR_PRE( 0x9 ) | MCF_PIT_PCSR_RLD | MCF_PIT_PCSR_OVW;
-        /* Initialize the periodic timer interrupt. */
-        MCF_PIT_PMR0 = MCF_PIT_MODULUS_REGISTER( configTICK_RATE_HZ );
-        /* Configure interrupt priority and level and unmask interrupt. */
-        MCF_INTC0_ICR36 = MCF_INTC0_ICRn_IL( 0x1 ) | MCF_INTC0_ICRn_IP( 0x1 );
-        MCF_INTC0_IMRH &= ~( MCF_INTC0_IMRH_INT_MASK36 | MCF_INTC0_IMRH_MASKALL );
-        /* Enable interrupts */
-        MCF_PIT_PCSR0 |= MCF_PIT_PCSR_PIE | MCF_PIT_PCSR_EN | MCF_PIT_PCSR_PIF;
-    }
-
-    /* Restore the context of the first task that is going to run. */
-    portRESTORE_CONTEXT(  );
-
-    /* Should not get here. */
-    return pdTRUE;
-}
-
-void
-vPortEndScheduler( void )
-{
-}
diff --git a/FreeRTOS/Source/portable/GCC/MCF5235/portmacro.h b/FreeRTOS/Source/portable/GCC/MCF5235/portmacro.h
deleted file mode 100755
index 1951b6f..0000000
--- a/FreeRTOS/Source/portable/GCC/MCF5235/portmacro.h
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
-    FreeRTOS V4.1.1 - Copyright (C) 2003-2006 Richard Barry.
-    MCF5235 Port - Copyright (C) 2006 Christian Walter.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License** as published by
-    the Free Software Foundation; either version 2 of the License, or
-    (at your option) any later version.
-
-    FreeRTOS is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with FreeRTOS; if not, write to the Free Software
-    Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-
-    A special exception to the GPL can be applied should you wish to distribute
-    a combined work that includes FreeRTOS, without being obliged to provide
-    the source code for any proprietary components.  See the licensing section
-    of http://www.FreeRTOS.org for full details of how and when the exception
-    can be applied.
-
-    ***************************************************************************
-    ***************************************************************************
-    *                                                                         *
-    * Get the FreeRTOS eBook!  See http://www.FreeRTOS.org/Documentation      *
-	*                                                                         *
-	* This is a concise, step by step, 'hands on' guide that describes both   *
-	* general multitasking concepts and FreeRTOS specifics. It presents and   *
-	* explains numerous examples that are written using the FreeRTOS API.     *
-	* Full source code for all the examples is provided in an accompanying    *
-	* .zip file.                                                              *
-    *                                                                         *
-    ***************************************************************************
-    ***************************************************************************
-
-	Please ensure to read the configuration and relevant port sections of the
-	online documentation.
-
-	http://www.FreeRTOS.org - Documentation, latest information, license and
-	contact details.
-
-	http://www.SafeRTOS.com - A version that is certified for use in safety
-	critical systems.
-
-	http://www.OpenRTOS.com - Commercial support, development, porting,
-	licensing and training services.
-*/
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* ------------------------ Data types for Coldfire ----------------------- */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  unsigned int
-#define portBASE_TYPE   int
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-
-/* ------------------------ Architecture specifics ------------------------ */
-#define portSTACK_GROWTH                ( -1 )
-#define portTICK_PERIOD_MS                ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT              4
-
-#define portTRAP_YIELD                  0   /* Trap 0 */
-#define portIPL_MAX                     7   /* Only NMI interrupt 7 allowed. */
-
-/* ------------------------ FreeRTOS macros for port ---------------------- */
-
-/*
- * This function must be called when the current state of the active task
- * should be stored. It must be called immediately after exception
- * processing from the CPU, i.e. there exists a Coldfire exception frame at
- * the current position in the stack. The function reserves space on
- * the stack for the CPU registers and other task dependent values (e.g
- * ulCriticalNesting) and updates the top of the stack in the TCB.
- */
-#define portSAVE_CONTEXT()                                                   \
-    asm volatile ( /* reserve space for task state. */                       \
-                   "lea.l   (-64, %sp), %sp\n\t"                             \
-                   /* push data register %d0-%d7/%a0-%a6 on stack. */        \
-                   "movem.l %d0-%d7/%a0-%a6, (%sp)\n\t"                      \
-                   /* push ulCriticalNesting counter on stack. */            \
-                   "lea.l  (60, %sp), %a0\n\t"                               \
-                   "move.l  ulCriticalNesting, (%a0)\n\t"                    \
-                   /* set the new top of the stack in the TCB. */            \
-                   "move.l  pxCurrentTCB, %a0\n\t"                           \
-                   "move.l  %sp, (%a0)");
-
-/*.
- * This function restores the current active and continues its execution.
- * It loads the current TCB and restores the processor registers, the
- * task dependent values (e.g ulCriticalNesting). Finally execution
- * is continued by executing an rte instruction.
- */
-#define portRESTORE_CONTEXT()                                                \
-    asm volatile ( "move.l  pxCurrentTCB, %sp\n\t"                           \
-                   "move.l  (%sp), %sp\n\t"                                  \
-                   /* stack pointer now points to the saved registers. */    \
-                   "movem.l (%sp), %d0-%d7/%a0-%a6\n\t"                      \
-                   /* restore ulCriticalNesting counter from stack. */       \
-                   "lea.l   (%sp, 60), %sp\n\t"                              \
-                   "move.l  (%sp)+, ulCriticalNesting\n\t"                   \
-                   /* stack pointer now points to exception frame. */        \
-                   "rte\n\t" );
-
-#define portENTER_CRITICAL()                                                 \
-    vPortEnterCritical();
-
-#define portEXIT_CRITICAL()                                                  \
-    vPortExitCritical();
-
-#define portSET_IPL( xIPL )                                                  \
-    asm_set_ipl( xIPL )
-
-#define portDISABLE_INTERRUPTS() \
-    do { ( void )portSET_IPL( portIPL_MAX ); } while( 0 )
-#define portENABLE_INTERRUPTS() \
-    do { ( void )portSET_IPL( 0 ); } while( 0 )
-
-#define portYIELD()                                                          \
-    asm volatile ( " trap   %0\n\t" : : "i"(portTRAP_YIELD) )
-
-#define portNOP()                                                            \
-    asm volatile ( "nop\n\t" )
-
-#define portENTER_SWITCHING_ISR()                                            \
-    asm volatile ( "move.w  #0x2700, %sr" );                                 \
-    /* Save the context of the interrupted task. */                          \
-    portSAVE_CONTEXT(  );                                                    \
-    {
-
-#define portEXIT_SWITCHING_ISR( SwitchRequired )                             \
-        /* If a switch is required we call vTaskSwitchContext(). */          \
-        if( SwitchRequired )                                                 \
-        {                                                                    \
-            vTaskSwitchContext(  );                                          \
-        }                                                                    \
-    }                                                                        \
-    portRESTORE_CONTEXT(  );
-
-/* ------------------------ Function prototypes --------------------------- */
-void vPortEnterCritical( void );
-void vPortExitCritical( void );
-int asm_set_ipl( uint32_t int uiNewIPL );
-
-/* ------------------------ Compiler specifics ---------------------------- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )                   \
-    void vFunction( void *pvParameters )
-
-#define portTASK_FUNCTION( vFunction, pvParameters )                         \
-    void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/MSP430F449/port.c b/FreeRTOS/Source/portable/GCC/MSP430F449/port.c
deleted file mode 100755
index 4fee812..0000000
--- a/FreeRTOS/Source/portable/GCC/MSP430F449/port.c
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-	Changes from V2.5.2
-		
-	+ usCriticalNesting now has a volatile qualifier.
-*/
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MSP430 port.
- *----------------------------------------------------------*/
-
-/* Constants required for hardware setup.  The tick ISR runs off the ACLK, 
-not the MCLK. */
-#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
-#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
-#define portFLAGS_INT_ENABLED	( ( StackType_t ) 0x08 )
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/* Most ports implement critical sections by placing the interrupt flags on
-the stack before disabling interrupts.  Exiting the critical section is then
-simply a case of popping the flags from the stack.  As mspgcc does not use
-a frame pointer this cannot be done as modifying the stack will clobber all
-the stack variables.  Instead each task maintains a count of the critical
-section nesting depth.  Each time a critical section is entered the count is
-incremented.  Each time a critical section is left the count is decremented -
-with interrupts only being re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as this will cause problems during the startup
-sequence. */
-volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
-/*-----------------------------------------------------------*/
-
-/* 
- * Macro to save a task context to the task stack.  This simply pushes all the 
- * general purpose msp430 registers onto the stack, followed by the 
- * usCriticalNesting value used by the task.  Finally the resultant stack 
- * pointer value is saved into the task control block so it can be retrieved 
- * the next time the task executes.
- */
-#define portSAVE_CONTEXT()									\
-	asm volatile (	"push	r4						\n\t"	\
-					"push	r5						\n\t"	\
-					"push	r6						\n\t"	\
-					"push	r7						\n\t"	\
-					"push	r8						\n\t"	\
-					"push	r9						\n\t"	\
-					"push	r10						\n\t"	\
-					"push	r11						\n\t"	\
-					"push	r12						\n\t"	\
-					"push	r13						\n\t"	\
-					"push	r14						\n\t"	\
-					"push	r15						\n\t"	\
-					"mov.w	usCriticalNesting, r14	\n\t"	\
-					"push	r14						\n\t"	\
-					"mov.w	pxCurrentTCB, r12		\n\t"	\
-					"mov.w	r1, @r12				\n\t"	\
-				);
-
-/* 
- * Macro to restore a task context from the task stack.  This is effectively
- * the reverse of portSAVE_CONTEXT().  First the stack pointer value is
- * loaded from the task control block.  Next the value for usCriticalNesting
- * used by the task is retrieved from the stack - followed by the value of all
- * the general purpose msp430 registers.
- *
- * The bic instruction ensures there are no low power bits set in the status
- * register that is about to be popped from the stack.
- */
-#define portRESTORE_CONTEXT()								\
-	asm volatile (	"mov.w	pxCurrentTCB, r12		\n\t"	\
-					"mov.w	@r12, r1				\n\t"	\
-					"pop	r15						\n\t"	\
-					"mov.w	r15, usCriticalNesting	\n\t"	\
-					"pop	r15						\n\t"	\
-					"pop	r14						\n\t"	\
-					"pop	r13						\n\t"	\
-					"pop	r12						\n\t"	\
-					"pop	r11						\n\t"	\
-					"pop	r10						\n\t"	\
-					"pop	r9						\n\t"	\
-					"pop	r8						\n\t"	\
-					"pop	r7						\n\t"	\
-					"pop	r6						\n\t"	\
-					"pop	r5						\n\t"	\
-					"pop	r4						\n\t"	\
-					"bic	#(0xf0),0(r1)			\n\t"	\
-					"reti							\n\t"	\
-				);
-/*-----------------------------------------------------------*/
-
-/*
- * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
- * could have alternatively used the watchdog timer or timer 1.
- */
-static void prvSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-/* 
- * Initialise the stack of a task to look exactly as if a call to 
- * portSAVE_CONTEXT had been called.
- * 
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* 
-		Place a few bytes of known values on the bottom of the stack. 
-		This is just useful for debugging and can be included if required.
-
-		*pxTopOfStack = ( StackType_t ) 0x1111;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x2222;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x3333;
-		pxTopOfStack--; 
-	*/
-
-	/* The msp430 automatically pushes the PC then SR onto the stack before 
-	executing an ISR.  We want the stack to look just as if this has happened
-	so place a pointer to the start of the task on the stack first - followed
-	by the flags we want the task to use when it starts up. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-	*pxTopOfStack = portFLAGS_INT_ENABLED;
-	pxTopOfStack--;
-
-	/* Next the general purpose registers. */
-	*pxTopOfStack = ( StackType_t ) 0x4444;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x5555;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x6666;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x7777;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x8888;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x9999;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xaaaa;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xbbbb;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xcccc;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xdddd;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xeeee;
-	pxTopOfStack--;
-
-	/* When the task starts is will expect to find the function parameter in
-	R15. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;
-	pxTopOfStack--;
-
-	/* The code generated by the mspgcc compiler does not maintain separate
-	stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
-	use the stack as per other ports.  Instead a variable is used to keep
-	track of the critical section nesting.  This variable has to be stored
-	as part of the task context and is initially set to zero. */
-	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
-
-	/* Return a pointer to the top of the stack we have generated so this can
-	be stored in the task control block for the task. */
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Setup the hardware to generate the tick.  Interrupts are disabled when
-	this function is called. */
-	prvSetupTimerInterrupt();
-
-	/* Restore the context of the first task that is going to run. */
-	portRESTORE_CONTEXT();
-
-	/* Should not get here as the tasks are now running! */
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the MSP430 port will get stopped.  If required simply
-	disable the tick interrupt here. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch called by portYIELD or taskYIELD.  
- *
- * The first thing we do is save the registers so we can use a naked attribute.
- */
-void vPortYield( void ) __attribute__ ( ( naked ) );
-void vPortYield( void )
-{
-	/* We want the stack of the task being saved to look exactly as if the task
-	was saved during a pre-emptive RTOS tick ISR.  Before calling an ISR the 
-	msp430 places the status register onto the stack.  As this is a function 
-	call and not an ISR we have to do this manually. */
-	asm volatile ( "push	r2" );
-	_DINT();
-
-	/* Save the context of the current task. */
-	portSAVE_CONTEXT();
-
-	/* Switch to the highest priority task that is ready to run. */
-	vTaskSwitchContext();
-
-	/* Restore the context of the new task. */
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Hardware initialisation to generate the RTOS tick.  This uses timer 0
- * but could alternatively use the watchdog timer or timer 1. 
- */
-static void prvSetupTimerInterrupt( void )
-{
-	/* Ensure the timer is stopped. */
-	TACTL = 0;
-
-	/* Run the timer of the ACLK. */
-	TACTL = TASSEL_1;
-
-	/* Clear everything to start with. */
-	TACTL |= TACLR;
-
-	/* Set the compare match value according to the tick rate we want. */
-	TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
-
-	/* Enable the interrupts. */
-	TACCTL0 = CCIE;
-
-	/* Start up clean. */
-	TACTL |= TACLR;
-
-	/* Up mode. */
-	TACTL |= MC_1;
-}
-/*-----------------------------------------------------------*/
-
-/* 
- * The interrupt service routine used depends on whether the pre-emptive
- * scheduler is being used or not.
- */
-
-#if configUSE_PREEMPTION == 1
-
-	/*
-	 * Tick ISR for preemptive scheduler.  We can use a naked attribute as
-	 * the context is saved at the start of vPortYieldFromTick().  The tick
-	 * count is incremented after the context is saved.
-	 */
-	interrupt (TIMERA0_VECTOR) prvTickISR( void ) __attribute__ ( ( naked ) );
-	interrupt (TIMERA0_VECTOR) prvTickISR( void )
-	{
-		/* Save the context of the interrupted task. */
-		portSAVE_CONTEXT();
-
-		/* Increment the tick count then switch to the highest priority task
-		that is ready to run. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			vTaskSwitchContext();
-		}
-
-		/* Restore the context of the new task. */
-		portRESTORE_CONTEXT();
-	}
-
-#else
-
-	/*
-	 * Tick ISR for the cooperative scheduler.  All this does is increment the
-	 * tick count.  We don't need to switch context, this can only be done by
-	 * manual calls to taskYIELD();
-	 */
-	interrupt (TIMERA0_VECTOR) prvTickISR( void );
-	interrupt (TIMERA0_VECTOR) prvTickISR( void )
-	{
-		xTaskIncrementTick();
-	}
-#endif
-
-
-	
diff --git a/FreeRTOS/Source/portable/GCC/MSP430F449/portmacro.h b/FreeRTOS/Source/portable/GCC/MSP430F449/portmacro.h
deleted file mode 100755
index 7ba66f2..0000000
--- a/FreeRTOS/Source/portable/GCC/MSP430F449/portmacro.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		int
-#define portSTACK_TYPE	uint16_t
-#define portBASE_TYPE	short
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS()	asm volatile ( "DINT" ); asm volatile ( "NOP" )
-#define portENABLE_INTERRUPTS()		asm volatile ( "EINT" ); asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
-
-#define portENTER_CRITICAL()													\
-{																				\
-extern volatile uint16_t usCriticalNesting;							\
-																				\
-	portDISABLE_INTERRUPTS();													\
-																				\
-	/* Now interrupts are disabled ulCriticalNesting can be accessed */			\
-	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
-	/* times portENTER_CRITICAL() has been called. */							\
-	usCriticalNesting++;														\
-}
-
-#define portEXIT_CRITICAL()														\
-{																				\
-extern volatile uint16_t usCriticalNesting;							\
-																				\
-	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
-	{																			\
-		/* Decrement the nesting count as we are leaving a critical section. */	\
-		usCriticalNesting--;													\
-																				\
-		/* If the nesting level has reached zero then interrupts should be */	\
-		/* re-enabled. */														\
-		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
-		{																		\
-			portENABLE_INTERRUPTS();											\
-		}																		\
-	}																			\
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-extern void vPortYield( void ) __attribute__ ( ( naked ) );
-#define portYIELD()			vPortYield()
-#define portNOP()			asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Hardwware specifics. */
-#define portBYTE_ALIGNMENT			2
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c b/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c
deleted file mode 100755
index a453ea4..0000000
--- a/FreeRTOS/Source/portable/GCC/MicroBlaze/port.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MicroBlaze port.
- *----------------------------------------------------------*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Standard includes. */
-#include 
-
-/* Hardware includes. */
-#include 
-#include 
-#include 
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-	#error configSUPPORT_DYNAMIC_ALLOCATION must be set to 1 to use this port.
-#endif
-
-/* Tasks are started with interrupts enabled. */
-#define portINITIAL_MSR_STATE		( ( StackType_t ) 0x02 )
-
-/* Tasks are started with a critical section nesting of 0 - however prior
-to the scheduler being commenced we don't want the critical nesting level
-to reach zero, so it is initialised to a high value. */
-#define portINITIAL_NESTING_VALUE	( 0xff )
-
-/* Our hardware setup only uses one counter. */
-#define portCOUNTER_0 				0
-
-/* The stack used by the ISR is filled with a known value to assist in
-debugging. */
-#define portISR_STACK_FILL_VALUE	0x55555555
-
-/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task
-maintains it's own count, so this variable is saved as part of the task
-context. */
-volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
-
-/* To limit the amount of stack required by each task, this port uses a
-separate stack for interrupts. */
-uint32_t *pulISRStack;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
- * could have alternatively used the watchdog timer or timer 1.
- */
-static void prvSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been made.
- *
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-extern void *_SDA2_BASE_, *_SDA_BASE_;
-const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
-const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
-
-	/* Place a few bytes of known values on the bottom of the stack.
-	This is essential for the Microblaze port and these lines must
-	not be omitted.  The parameter value will overwrite the
-	0x22222222 value during the function prologue. */
-	*pxTopOfStack = ( StackType_t ) 0x11111111;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x22222222;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x33333333;
-	pxTopOfStack--;
-
-	/* First stack an initial value for the critical section nesting.  This
-	is initialised to zero as tasks are started with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) 0x00;	/* R0. */
-
-	/* Place an initial value for all the general purpose registers. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) ulR2;	/* R2 - small data area. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x06;	/* R6. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x07;	/* R7. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x08;	/* R8. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x09;	/* R9. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x0a;	/* R10. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x0b;	/* R11. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x0c;	/* R12. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) ulR13;	/* R13 - small data read write area. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;	/* R14. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x0f;	/* R15. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x10;	/* R16. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x11;	/* R17. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12;	/* R18. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x13;	/* R19. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x14;	/* R20. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x15;	/* R21. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x16;	/* R22. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x17;	/* R23. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x18;	/* R24. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x19;	/* R25. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x1a;	/* R26. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x1b;	/* R27. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x1c;	/* R28. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x1d;	/* R29. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x1e;	/* R30. */
-	pxTopOfStack--;
-
-	/* The MSR is stacked between R30 and R31. */
-	*pxTopOfStack = portINITIAL_MSR_STATE;
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0x1f;	/* R31. */
-	pxTopOfStack--;
-
-	/* Return a pointer to the top of the stack we have generated so this can
-	be stored in the task control block for the task. */
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void ( __FreeRTOS_interrupt_Handler )( void );
-extern void ( vStartFirstTask )( void );
-
-
-	/* Setup the FreeRTOS interrupt handler.  Code copied from crt0.s. */
-	asm volatile ( 	"la	r6, r0, __FreeRTOS_interrupt_handler		\n\t" \
-					"sw	r6, r1, r0									\n\t" \
-					"lhu r7, r1, r0									\n\t" \
-					"shi r7, r0, 0x12								\n\t" \
-					"shi r6, r0, 0x16 " );
-
-	/* Setup the hardware to generate the tick.  Interrupts are disabled when
-	this function is called. */
-	prvSetupTimerInterrupt();
-
-	/* Allocate the stack to be used by the interrupt handler. */
-	pulISRStack = ( uint32_t * ) pvPortMalloc( configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
-
-	/* Restore the context of the first task that is going to run. */
-	if( pulISRStack != NULL )
-	{
-		/* Fill the ISR stack with a known value to facilitate debugging. */
-		memset( pulISRStack, portISR_STACK_FILL_VALUE, configMINIMAL_STACK_SIZE * sizeof( StackType_t ) );
-		pulISRStack += ( configMINIMAL_STACK_SIZE - 1 );
-
-		/* Kick off the first task. */
-		vStartFirstTask();
-	}
-
-	/* Should not get here as the tasks are now running! */
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch called by portYIELD or taskYIELD.
- */
-void vPortYield( void )
-{
-extern void VPortYieldASM( void );
-
-	/* Perform the context switch in a critical section to assure it is
-	not interrupted by the tick ISR.  It is not a problem to do this as
-	each task maintains it's own interrupt status. */
-	portENTER_CRITICAL();
-		/* Jump directly to the yield function to ensure there is no
-		compiler generated prologue code. */
-		asm volatile (	"bralid r14, VPortYieldASM		\n\t" \
-						"or r0, r0, r0					\n\t" );
-	portEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Hardware initialisation to generate the RTOS tick.
- */
-static void prvSetupTimerInterrupt( void )
-{
-XTmrCtr xTimer;
-const uint32_t ulCounterValue = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-UBaseType_t uxMask;
-
-	/* The OPB timer1 is used to generate the tick.  Use the provided library
-	functions to enable the timer and set the tick frequency. */
-	XTmrCtr_mDisable( XPAR_OPB_TIMER_1_BASEADDR, XPAR_OPB_TIMER_1_DEVICE_ID );
-	XTmrCtr_Initialize( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
-   	XTmrCtr_mSetLoadReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCounterValue );
-	XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_LOAD_MASK | XTC_CSR_INT_OCCURED_MASK );
-
-	/* Set the timer interrupt enable bit while maintaining the other bit
-	states. */
-	uxMask = XIntc_In32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ) );
-	uxMask |= XPAR_OPB_TIMER_1_INTERRUPT_MASK;
-	XIntc_Out32( ( XPAR_OPB_INTC_0_BASEADDR + XIN_IER_OFFSET ), ( uxMask ) );
-
-	XTmrCtr_Start( &xTimer, XPAR_OPB_TIMER_1_DEVICE_ID );
-	XTmrCtr_mSetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, XTC_CSR_ENABLE_TMR_MASK | XTC_CSR_ENABLE_INT_MASK | XTC_CSR_AUTO_RELOAD_MASK | XTC_CSR_DOWN_COUNT_MASK | XTC_CSR_INT_OCCURED_MASK );
-	XIntc_mAckIntr( XPAR_INTC_SINGLE_BASEADDR, 1 );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt handler placed in the interrupt vector when the scheduler is
- * started.  The task context has already been saved when this is called.
- * This handler determines the interrupt source and calls the relevant
- * peripheral handler.
- */
-void vTaskISRHandler( void )
-{
-static uint32_t ulPending;
-
-	/* Which interrupts are pending? */
-	ulPending = XIntc_In32( ( XPAR_INTC_SINGLE_BASEADDR + XIN_IVR_OFFSET ) );
-
-	if( ulPending < XPAR_INTC_MAX_NUM_INTR_INPUTS )
-	{
-		static XIntc_VectorTableEntry *pxTablePtr;
-		static XIntc_Config *pxConfig;
-		static uint32_t ulInterruptMask;
-
-		ulInterruptMask = ( uint32_t ) 1 << ulPending;
-
-		/* Get the configuration data using the device ID */
-		pxConfig = &XIntc_ConfigTable[ ( uint32_t ) XPAR_INTC_SINGLE_DEVICE_ID ];
-
-		pxTablePtr = &( pxConfig->HandlerTable[ ulPending ] );
-		if( pxConfig->AckBeforeService & ( ulInterruptMask  ) )
-		{
-			XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
-			pxTablePtr->Handler( pxTablePtr->CallBackRef );
-		}
-		else
-		{
-			pxTablePtr->Handler( pxTablePtr->CallBackRef );
-			XIntc_mAckIntr( pxConfig->BaseAddress, ulInterruptMask );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Handler for the timer interrupt.
- */
-void vTickISR( void *pvBaseAddress )
-{
-uint32_t ulCSR;
-
-	/* Increment the RTOS tick - this might cause a task to unblock. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		vTaskSwitchContext();
-	}
-
-	/* Clear the timer interrupt */
-	ulCSR = XTmrCtr_mGetControlStatusReg(XPAR_OPB_TIMER_1_BASEADDR, 0);
-	XTmrCtr_mSetControlStatusReg( XPAR_OPB_TIMER_1_BASEADDR, portCOUNTER_0, ulCSR );
-}
-/*-----------------------------------------------------------*/
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s b/FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s
deleted file mode 100755
index 26baecf..0000000
--- a/FreeRTOS/Source/portable/GCC/MicroBlaze/portasm.s
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-	.extern pxCurrentTCB
-	.extern vTaskISRHandler
-	.extern vTaskSwitchContext
-	.extern uxCriticalNesting
-	.extern pulISRStack
-
-	.global __FreeRTOS_interrupt_handler
-	.global VPortYieldASM
-	.global vStartFirstTask
-
-
-.macro portSAVE_CONTEXT
-	/* Make room for the context on the stack. */
-	addik r1, r1, -132
-	/* Save r31 so it can then be used. */
-	swi r31, r1, 4
-	/* Copy the msr into r31 - this is stacked later. */
-	mfs r31, rmsr
-	/* Stack general registers. */
-	swi r30, r1, 12
-	swi r29, r1, 16
-	swi r28, r1, 20
-	swi r27, r1, 24
-	swi r26, r1, 28
-	swi r25, r1, 32
-	swi r24, r1, 36
-	swi r23, r1, 40
-	swi r22, r1, 44
-	swi r21, r1, 48
-	swi r20, r1, 52
-	swi r19, r1, 56
-	swi r18, r1, 60
-	swi r17, r1, 64
-	swi r16, r1, 68
-	swi r15, r1, 72
-	swi r13, r1, 80
-	swi r12, r1, 84
-	swi r11, r1, 88
-	swi r10, r1, 92
-	swi r9, r1, 96
-	swi r8, r1, 100
-	swi r7, r1, 104
-	swi r6, r1, 108
-	swi r5, r1, 112
-	swi r4, r1, 116
-	swi r3, r1, 120
-	swi r2, r1, 124
-	/* Stack the critical section nesting value. */
-	lwi r3, r0, uxCriticalNesting
-	swi r3, r1, 128
-	/* Save the top of stack value to the TCB. */
-	lwi r3, r0, pxCurrentTCB
-	sw	r1, r0, r3
-	
-	.endm
-
-.macro portRESTORE_CONTEXT
-	/* Load the top of stack value from the TCB. */
-	lwi r3, r0, pxCurrentTCB
-	lw	r1, r0, r3	
-	/* Restore the general registers. */
-	lwi r31, r1, 4		
-	lwi r30, r1, 12		
-	lwi r29, r1, 16	
-	lwi r28, r1, 20	
-	lwi r27, r1, 24	
-	lwi r26, r1, 28	
-	lwi r25, r1, 32	
-	lwi r24, r1, 36	
-	lwi r23, r1, 40	
-	lwi r22, r1, 44	
-	lwi r21, r1, 48	
-	lwi r20, r1, 52	
-	lwi r19, r1, 56	
-	lwi r18, r1, 60	
-	lwi r17, r1, 64	
-	lwi r16, r1, 68	
-	lwi r15, r1, 72	
-	lwi r14, r1, 76	
-	lwi r13, r1, 80	
-	lwi r12, r1, 84	
-	lwi r11, r1, 88	
-	lwi r10, r1, 92	
-	lwi r9, r1, 96	
-	lwi r8, r1, 100	
-	lwi r7, r1, 104
-	lwi r6, r1, 108
-	lwi r5, r1, 112
-	lwi r4, r1, 116
-	lwi r2, r1, 124
-
-	/* Load the critical nesting value. */
-	lwi r3, r1, 128
-	swi r3, r0, uxCriticalNesting
-
-	/* Obtain the MSR value from the stack. */
-	lwi r3, r1, 8
-
-	/* Are interrupts enabled in the MSR?  If so return using an return from 
-	interrupt instruction to ensure interrupts are enabled only once the task
-	is running again. */
-	andi r3, r3, 2
-	beqid r3, 36
-	or r0, r0, r0
-
-	/* Reload the rmsr from the stack, clear the enable interrupt bit in the
-	value before saving back to rmsr register, then return enabling interrupts
-	as we return. */
-	lwi r3, r1, 8
-	andi r3, r3, ~2
-	mts rmsr, r3
-	lwi r3, r1, 120
-	addik r1, r1, 132
-	rtid r14, 0
-	or r0, r0, r0
-
-	/* Reload the rmsr from the stack, place it in the rmsr register, and
-	return without enabling interrupts. */
-	lwi r3, r1, 8
-	mts rmsr, r3
-	lwi r3, r1, 120
-	addik r1, r1, 132
-	rtsd r14, 0
-	or r0, r0, r0
-
-	.endm
-
-	.text
-	.align  2
-
-
-__FreeRTOS_interrupt_handler:
-	portSAVE_CONTEXT
-	/* Entered via an interrupt so interrupts must be enabled in msr. */
-	ori r31, r31, 2
-	/* Stack msr. */
-	swi r31, r1, 8
-	/* Stack the return address.  As we entered via an interrupt we do
-	not need to modify the return address prior to stacking. */
-	swi r14, r1, 76
-	/* Now switch to use the ISR stack. */
-	lwi r3, r0, pulISRStack
-	add r1, r3, r0
-	bralid r15, vTaskISRHandler
-	or r0, r0, r0
-	portRESTORE_CONTEXT
-
-
-VPortYieldASM:
-	portSAVE_CONTEXT
-	/* Stack msr. */
-	swi r31, r1, 8
-	/* Modify the return address so we return to the instruction after the
-	exception. */
-	addi r14, r14, 8
-	swi r14, r1, 76
-	/* Now switch to use the ISR stack. */
-	lwi r3, r0, pulISRStack
-	add r1, r3, r0
-	bralid r15, vTaskSwitchContext
-	or r0, r0, r0
-	portRESTORE_CONTEXT
-
-vStartFirstTask:
-	portRESTORE_CONTEXT
-	
-	
-
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/MicroBlaze/portmacro.h b/FreeRTOS/Source/portable/GCC/MicroBlaze/portmacro.h
deleted file mode 100755
index 157acf6..0000000
--- a/FreeRTOS/Source/portable/GCC/MicroBlaze/portmacro.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros. */
-void microblaze_disable_interrupts( void );
-void microblaze_enable_interrupts( void );
-#define portDISABLE_INTERRUPTS()	microblaze_disable_interrupts()
-#define portENABLE_INTERRUPTS()		microblaze_enable_interrupts()
-/*-----------------------------------------------------------*/
-
-/* Critical section macros. */
-void vPortEnterCritical( void );
-void vPortExitCritical( void );
-#define portENTER_CRITICAL()		{														\
-										extern UBaseType_t uxCriticalNesting;	\
-										microblaze_disable_interrupts();					\
-										uxCriticalNesting++;								\
-									}
-
-#define portEXIT_CRITICAL()			{														\
-										extern UBaseType_t uxCriticalNesting;	\
-										/* Interrupts are disabled, so we can */			\
-										/* access the variable directly. */					\
-										uxCriticalNesting--;								\
-										if( uxCriticalNesting == 0 )			\
-										{													\
-											/* The nesting has unwound and we 				\
-											can enable interrupts again. */					\
-											portENABLE_INTERRUPTS();						\
-										}													\
-									}
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-void vPortYield( void );
-#define portYIELD() vPortYield()
-
-void vTaskSwitchContext();
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			4
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()					asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port.c b/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port.c
deleted file mode 100755
index 59a1564..0000000
--- a/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port.c
+++ /dev/null
@@ -1,452 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MicroBlaze port.
- *----------------------------------------------------------*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Standard includes. */
-#include 
-
-/* Hardware includes. */
-#include 
-#include 
-#include 
-
-/* Tasks are started with a critical section nesting of 0 - however, prior to
-the scheduler being commenced interrupts should not be enabled, so the critical
-nesting variable is initialised to a non-zero value. */
-#define portINITIAL_NESTING_VALUE	( 0xff )
-
-/* The bit within the MSR register that enabled/disables interrupts and 
-exceptions respectively. */
-#define portMSR_IE					( 0x02U )
-#define portMSR_EE					( 0x100U )
-
-/* If the floating point unit is included in the MicroBlaze build, then the
-FSR register is saved as part of the task context.  portINITIAL_FSR is the value
-given to the FSR register when the initial context is set up for a task being
-created. */
-#define portINITIAL_FSR				( 0U )
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the interrupt controller instance.
- */
-static int32_t prvInitialiseInterruptController( void );
-
-/* Ensure the interrupt controller instance variable is initialised before it is
- * used, and that the initialisation only happens once.
- */
-static int32_t prvEnsureInterruptControllerIsInitialised( void );
-
-/*-----------------------------------------------------------*/
-
-/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task
-maintains its own count, so this variable is saved as part of the task
-context. */
-volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
-
-/* This port uses a separate stack for interrupts.  This prevents the stack of
-every task needing to be large enough to hold an entire interrupt stack on top
-of the task stack. */
-uint32_t *pulISRStack;
-
-/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
-get set to 1.  ulTaskSwitchRequested is inspected just before the main interrupt
-handler exits.  If, at that time, ulTaskSwitchRequested is set to 1, the kernel
-will call vTaskSwitchContext() to ensure the task that runs immediately after
-the interrupt exists is the highest priority task that is able to run.  This is
-an unusual mechanism, but is used for this port because a single interrupt can
-cause the servicing of multiple peripherals - and it is inefficient to call
-vTaskSwitchContext() multiple times as each peripheral is serviced. */
-volatile uint32_t ulTaskSwitchRequested = 0UL;
-
-/* The instance of the interrupt controller used by this port.  This is required
-by the Xilinx library API functions. */
-static XIntc xInterruptControllerInstance;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been made.
- *
- * See the portable.h header file.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-extern void *_SDA2_BASE_, *_SDA_BASE_;
-const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
-const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
-
-	/* Place a few bytes of known values on the bottom of the stack.
-	This is essential for the Microblaze port and these lines must
-	not be omitted. */
-	*pxTopOfStack = ( StackType_t ) 0x00000000;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00000000;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00000000;
-	pxTopOfStack--;
-
-	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
-		/* The FSR value placed in the initial task context is just 0. */
-		*pxTopOfStack = portINITIAL_FSR;
-		pxTopOfStack--;
-	#endif
-
-	/* The MSR value placed in the initial task context should have interrupts
-	disabled.  Each task will enable interrupts automatically when it enters
-	the running state for the first time. */
-	*pxTopOfStack = mfmsr() & ~portMSR_IE;
-	
-	#if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
-	{
-		/* Ensure exceptions are enabled for the task. */
-		*pxTopOfStack |= portMSR_EE;
-	}
-	#endif
-
-	pxTopOfStack--;
-
-	/* First stack an initial value for the critical section nesting.  This
-	is initialised to zero. */
-	*pxTopOfStack = ( StackType_t ) 0x00;
-
-	/* R0 is always zero. */
-	/* R1 is the SP. */
-
-	/* Place an initial value for all the general purpose registers. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) ulR2;	/* R2 - read only small data area. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3 - return values and temporaries. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4 - return values and temporaries. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
-
-	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06;	/* R6 - other parameters and temporaries.  Used as the return address from vPortTaskEntryPoint. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07;	/* R7 - other parameters and temporaries. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08;	/* R8 - other parameters and temporaries. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09;	/* R9 - other parameters and temporaries. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x0a;	/* R10 - other parameters and temporaries. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x0b;	/* R11 - temporaries. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x0c;	/* R12 - temporaries. */
-		pxTopOfStack--;
-	#else
-		pxTopOfStack-= 8;
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) ulR13;	/* R13 - read/write small data area. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;	/* R14 - return address for interrupt. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) NULL;	/* R15 - return address for subroutine. */
-
-	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10;	/* R16 - return address for trap (debugger). */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11;	/* R17 - return address for exceptions, if configured. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12;	/* R18 - reserved for assembler and compiler temporaries. */
-		pxTopOfStack--;
-	#else
-		pxTopOfStack -= 4;
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) 0x00;	/* R19 - must be saved across function calls. Callee-save.  Seems to be interpreted as the frame pointer. */
-
-	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x14;	/* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save.  Not used by FreeRTOS. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x15;	/* R21 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x16;	/* R22 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x17;	/* R23 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x18;	/* R24 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x19;	/* R25 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x1a;	/* R26 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x1b;	/* R27 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x1c;	/* R28 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x1d;	/* R29 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x1e;	/* R30 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x1f;	/* R31 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-	#else
-		pxTopOfStack -= 13;
-	#endif
-
-	/* Return a pointer to the top of the stack that has been generated so this
-	can	be stored in the task control block for the task. */
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void ( vPortStartFirstTask )( void );
-extern uint32_t _stack[];
-
-	/* Setup the hardware to generate the tick.  Interrupts are disabled when
-	this function is called.
-
-	This port uses an application defined callback function to install the tick
-	interrupt handler because the kernel will run on lots of different
-	MicroBlaze and FPGA configurations - not all of	which will have the same
-	timer peripherals defined or available.  An example definition of
-	vApplicationSetupTimerInterrupt() is provided in the official demo
-	application that accompanies this port. */
-	vApplicationSetupTimerInterrupt();
-
-	/* Reuse the stack from main() as the stack for the interrupts/exceptions. */
-	pulISRStack = ( uint32_t * ) _stack;
-
-	/* Ensure there is enough space for the functions called from the interrupt
-	service routines to write back into the stack frame of the caller. */
-	pulISRStack -= 2;
-
-	/* Restore the context of the first task that is going to run.  From here
-	on, the created tasks will be executing. */
-	vPortStartFirstTask();
-
-	/* Should not get here as the tasks are now running! */
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch called by portYIELD or taskYIELD.
- */
-void vPortYield( void )
-{
-extern void VPortYieldASM( void );
-
-	/* Perform the context switch in a critical section to assure it is
-	not interrupted by the tick ISR.  It is not a problem to do this as
-	each task maintains its own interrupt status. */
-	portENTER_CRITICAL();
-	{
-		/* Jump directly to the yield function to ensure there is no
-		compiler generated prologue code. */
-		asm volatile (	"bralid r14, VPortYieldASM		\n\t" \
-						"or r0, r0, r0					\n\t" );
-	}
-	portEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnableInterrupt( uint8_t ucInterruptID )
-{
-int32_t lReturn;
-
-	/* An API function is provided to enable an interrupt in the interrupt
-	controller because the interrupt controller instance variable is private
-	to this file. */
-	lReturn = prvEnsureInterruptControllerIsInitialised();
-	if( lReturn == pdPASS )
-	{
-		XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
-	}
-
-	configASSERT( lReturn );
-}
-/*-----------------------------------------------------------*/
-
-void vPortDisableInterrupt( uint8_t ucInterruptID )
-{
-int32_t lReturn;
-
-	/* An API function is provided to disable an interrupt in the interrupt
-	controller because the interrupt controller instance variable is private
-	to this file. */
-	lReturn = prvEnsureInterruptControllerIsInitialised();
-
-	if( lReturn == pdPASS )
-	{
-		XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
-	}
-
-	configASSERT( lReturn );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
-{
-int32_t lReturn;
-
-	/* An API function is provided to install an interrupt handler because the
-	interrupt controller instance variable is private to this file. */
-
-	lReturn = prvEnsureInterruptControllerIsInitialised();
-
-	if( lReturn == pdPASS )
-	{
-		lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
-	}
-
-	if( lReturn == XST_SUCCESS )
-	{
-		lReturn = pdPASS;
-	}
-
-	configASSERT( lReturn == pdPASS );
-
-	return lReturn;
-}
-/*-----------------------------------------------------------*/
-
-static int32_t prvEnsureInterruptControllerIsInitialised( void )
-{
-static int32_t lInterruptControllerInitialised = pdFALSE;
-int32_t lReturn;
-
-	/* Ensure the interrupt controller instance variable is initialised before
-	it is used, and that the initialisation only happens once. */
-	if( lInterruptControllerInitialised != pdTRUE )
-	{
-		lReturn = prvInitialiseInterruptController();
-
-		if( lReturn == pdPASS )
-		{
-			lInterruptControllerInitialised = pdTRUE;
-		}
-	}
-	else
-	{
-		lReturn = pdPASS;
-	}
-
-	return lReturn;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Handler for the timer interrupt.  This is the handler that the application
- * defined callback function vApplicationSetupTimerInterrupt() should install.
- */
-void vPortTickISR( void *pvUnused )
-{
-extern void vApplicationClearTimerInterrupt( void );
-
-	/* Ensure the unused parameter does not generate a compiler warning. */
-	( void ) pvUnused;
-
-	/* This port uses an application defined callback function to clear the tick
-	interrupt because the kernel will run on lots of different MicroBlaze and
-	FPGA configurations - not all of which will have the same timer peripherals
-	defined or available.  An example definition of
-	vApplicationClearTimerInterrupt() is provided in the official demo
-	application that accompanies this port. */
-	vApplicationClearTimerInterrupt();
-
-	/* Increment the RTOS tick - this might cause a task to unblock. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		/* Force vTaskSwitchContext() to be called as the interrupt exits. */
-		ulTaskSwitchRequested = 1;
-	}
-}
-/*-----------------------------------------------------------*/
-
-static int32_t prvInitialiseInterruptController( void )
-{
-int32_t lStatus;
-
-	lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
-
-	if( lStatus == XST_SUCCESS )
-	{
-		/* Initialise the exception table. */
-		Xil_ExceptionInit();
-
-	    /* Service all pending interrupts each time the handler is entered. */
-	    XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
-
-	    /* Install exception handlers if the MicroBlaze is configured to handle
-	    exceptions, and the application defined constant
-	    configINSTALL_EXCEPTION_HANDLERS is set to 1. */
-		#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
-	    {
-	    	vPortExceptionsInstallHandlers();
-	    }
-		#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
-
-		/* Start the interrupt controller.  Interrupts are enabled when the
-		scheduler starts. */
-		lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
-
-		if( lStatus == XST_SUCCESS )
-		{
-			lStatus = pdPASS;
-		}
-		else
-		{
-			lStatus = pdFAIL;
-		}
-	}
-
-	configASSERT( lStatus == pdPASS );
-
-	return lStatus;
-}
-/*-----------------------------------------------------------*/
-
-
diff --git a/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port_exceptions.c b/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port_exceptions.c
deleted file mode 100755
index 2b1cb28..0000000
--- a/FreeRTOS/Source/portable/GCC/MicroBlazeV8/port_exceptions.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Hardware includes. */
-#include 
-#include 
-
-/* The Xilinx library defined exception entry point stacks a number of
-registers.  These definitions are offsets from the stack pointer to the various
-stacked register values. */
-#define portexR3_STACK_OFFSET	4
-#define portexR4_STACK_OFFSET	5
-#define portexR5_STACK_OFFSET	6
-#define portexR6_STACK_OFFSET	7
-#define portexR7_STACK_OFFSET	8
-#define portexR8_STACK_OFFSET	9
-#define portexR9_STACK_OFFSET	10
-#define portexR10_STACK_OFFSET	11
-#define portexR11_STACK_OFFSET	12
-#define portexR12_STACK_OFFSET	13
-#define portexR15_STACK_OFFSET	16
-#define portexR18_STACK_OFFSET  19
-#define portexMSR_STACK_OFFSET	20
-#define portexR19_STACK_OFFSET  -1
-
-/* This is defined to equal the size, in bytes, of the stack frame generated by
-the Xilinx standard library exception entry point.  It is required to determine
-the stack pointer value prior to the exception being entered. */
-#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
-
-/* The number of bytes a MicroBlaze instruction consumes. */
-#define portexINSTRUCTION_SIZE	4
-
-/* Exclude this entire file if the MicroBlaze is not configured to handle
-exceptions, or the application defined configuration constant
-configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
-#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
-
-/* This variable is set in the exception entry code, before
-vPortExceptionHandler is called. */
-uint32_t *pulStackPointerOnFunctionEntry = NULL;
-
-/* This is the structure that is filled with the MicroBlaze context as it
-existed immediately prior to the exception occurrence.  A pointer to this
-structure is passed into the vApplicationExceptionRegisterDump() callback
-function, if one is defined. */
-static xPortRegisterDump xRegisterDump;
-
-/* This is the FreeRTOS exception handler that is installed for all exception
-types.  It is called from vPortExceptionHanlderEntry() - which is itself defined
-in portasm.S. */
-void vPortExceptionHandler( void *pvExceptionID );
-extern void vPortExceptionHandlerEntry( void *pvExceptionID );
-
-/*-----------------------------------------------------------*/
-
-/* vApplicationExceptionRegisterDump() is a callback function that the
-application can optionally define to receive a populated xPortRegisterDump
-structure.  If the application chooses not to define a version of
-vApplicationExceptionRegisterDump() then this weekly defined default
-implementation will be called instead. */
-extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
-void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
-{
-	( void ) xRegisterDump;
-
-	for( ;; )
-	{
-		portNOP();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExceptionHandler( void *pvExceptionID )
-{
-extern void *pxCurrentTCB;
-
-	/* Fill an xPortRegisterDump structure with the MicroBlaze context as it
-	was immediately before the exception occurrence. */
-
-	/* First fill in the name and handle of the task that was in the Running
-	state when the exception occurred. */
-	xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
-	xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
-
-	configASSERT( pulStackPointerOnFunctionEntry );
-
-	/* Obtain the values of registers that were stacked prior to this function
-	being called, and may have changed since they were stacked. */
-	xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
-	xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
-	xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
-	xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
-	xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
-	xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
-	xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
-	xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
-	xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
-	xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
-	xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
-	xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
-	xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
-	xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
-
-	/* Obtain the value of all other registers. */
-	xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
-	xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
-	xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
-	xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
-	xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
-	xRegisterDump.ulR20 = mfgpr( R20 );
-	xRegisterDump.ulR21 = mfgpr( R21 );
-	xRegisterDump.ulR22 = mfgpr( R22 );
-	xRegisterDump.ulR23 = mfgpr( R23 );
-	xRegisterDump.ulR24 = mfgpr( R24 );
-	xRegisterDump.ulR25 = mfgpr( R25 );
-	xRegisterDump.ulR26 = mfgpr( R26 );
-	xRegisterDump.ulR27 = mfgpr( R27 );
-	xRegisterDump.ulR28 = mfgpr( R28 );
-	xRegisterDump.ulR29 = mfgpr( R29 );
-	xRegisterDump.ulR30 = mfgpr( R30 );
-	xRegisterDump.ulR31 = mfgpr( R31 );
-	xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
-	xRegisterDump.ulEAR = mfear();
-	xRegisterDump.ulESR = mfesr();
-	xRegisterDump.ulEDR = mfedr();
-
-	/* Move the saved program counter back to the instruction that was executed
-	when the exception occurred.  This is only valid for certain types of
-	exception. */
-	xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
-
-	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
-	{
-		xRegisterDump.ulFSR = mffsr();
-	}
-	#else
-	{
-		xRegisterDump.ulFSR = 0UL;
-	}
-	#endif
-
-	/* Also fill in a string that describes what type of exception this is.
-	The string uses the same ID names as defined in the MicroBlaze standard
-	library exception header files. */
-	switch( ( uint32_t ) pvExceptionID )
-	{
-		case XEXC_ID_FSL :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
-				break;
-
-		case XEXC_ID_UNALIGNED_ACCESS :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
-				break;
-
-		case XEXC_ID_ILLEGAL_OPCODE :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
-				break;
-
-		case XEXC_ID_M_AXI_I_EXCEPTION :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
-				break;
-
-		case XEXC_ID_M_AXI_D_EXCEPTION :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
-				break;
-
-		case XEXC_ID_DIV_BY_ZERO :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
-				break;
-
-		case XEXC_ID_STACK_VIOLATION :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
-				break;
-
-		#if( XPAR_MICROBLAZE_USE_FPU != 0 )
-
-			case XEXC_ID_FPU :
-						xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
-						break;
-
-		#endif /* XPAR_MICROBLAZE_USE_FPU */
-	}
-
-	/* vApplicationExceptionRegisterDump() is a callback function that the
-	application can optionally define to receive the populated xPortRegisterDump
-	structure.  If the application chooses not to define a version of
-	vApplicationExceptionRegisterDump() then the weekly defined default
-	implementation within this file will be called instead. */
-	vApplicationExceptionRegisterDump( &xRegisterDump );
-
-	/* Must not attempt to leave this function! */
-	for( ;; )
-	{
-		portNOP();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExceptionsInstallHandlers( void )
-{
-static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
-
-	if( ulHandlersAlreadyInstalled == pdFALSE )
-	{
-		ulHandlersAlreadyInstalled = pdTRUE;
-
-		#if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
-			microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
-		#endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
-
-		#if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
-		#endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
-		#endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
-		#endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
-		#endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
-		#endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
-		#endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
-		#endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
-		#endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
-
-		microblaze_enable_exceptions();
-	}
-}
-
-/* Exclude the entire file if the MicroBlaze is not configured to handle
-exceptions, or the application defined configuration item
-configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
-#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portasm.S b/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portasm.S
deleted file mode 100755
index c603041..0000000
--- a/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portasm.S
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/* Xilinx library includes. */
-#include "microblaze_exceptions_g.h"
-#include "xparameters.h"
-
-/* The context is oversized to allow functions called from the ISR to write
-back into the caller stack. */
-#if( XPAR_MICROBLAZE_USE_FPU != 0 )
-	#define portCONTEXT_SIZE 136
-	#define portMINUS_CONTEXT_SIZE -136
-#else
-	#define portCONTEXT_SIZE 132
-	#define portMINUS_CONTEXT_SIZE -132
-#endif
-
-/* Offsets from the stack pointer at which saved registers are placed. */
-#define portR31_OFFSET	4
-#define portR30_OFFSET	8
-#define portR29_OFFSET	12
-#define portR28_OFFSET	16
-#define portR27_OFFSET	20
-#define portR26_OFFSET	24
-#define portR25_OFFSET	28
-#define portR24_OFFSET	32
-#define portR23_OFFSET	36
-#define portR22_OFFSET	40
-#define portR21_OFFSET	44
-#define portR20_OFFSET	48
-#define portR19_OFFSET	52
-#define portR18_OFFSET	56
-#define portR17_OFFSET	60
-#define portR16_OFFSET	64
-#define portR15_OFFSET	68
-#define portR14_OFFSET	72
-#define portR13_OFFSET	76
-#define portR12_OFFSET	80
-#define portR11_OFFSET	84
-#define portR10_OFFSET	88
-#define portR9_OFFSET	92
-#define portR8_OFFSET	96
-#define portR7_OFFSET	100
-#define portR6_OFFSET	104
-#define portR5_OFFSET	108
-#define portR4_OFFSET	112
-#define portR3_OFFSET	116
-#define portR2_OFFSET	120
-#define portCRITICAL_NESTING_OFFSET 124
-#define portMSR_OFFSET 128
-#define portFSR_OFFSET 132
-
-	.extern pxCurrentTCB
-	.extern XIntc_DeviceInterruptHandler
-	.extern vTaskSwitchContext
-	.extern uxCriticalNesting
-	.extern pulISRStack
-	.extern ulTaskSwitchRequested
-	.extern vPortExceptionHandler
-	.extern pulStackPointerOnFunctionEntry
-
-	.global _interrupt_handler
-	.global VPortYieldASM
-	.global vPortStartFirstTask
-	.global vPortExceptionHandlerEntry
-
-
-.macro portSAVE_CONTEXT
-
-	/* Make room for the context on the stack. */
-	addik r1, r1, portMINUS_CONTEXT_SIZE
-
-	/* Stack general registers. */
-	swi r31, r1, portR31_OFFSET
-	swi r30, r1, portR30_OFFSET
-	swi r29, r1, portR29_OFFSET
-	swi r28, r1, portR28_OFFSET
-	swi r27, r1, portR27_OFFSET
-	swi r26, r1, portR26_OFFSET
-	swi r25, r1, portR25_OFFSET
-	swi r24, r1, portR24_OFFSET
-	swi r23, r1, portR23_OFFSET
-	swi r22, r1, portR22_OFFSET
-	swi r21, r1, portR21_OFFSET
-	swi r20, r1, portR20_OFFSET
-	swi r19, r1, portR19_OFFSET
-	swi r18, r1, portR18_OFFSET
-	swi r17, r1, portR17_OFFSET
-	swi r16, r1, portR16_OFFSET
-	swi r15, r1, portR15_OFFSET
-	/* R14 is saved later as it needs adjustment if a yield is performed. */
-	swi r13, r1, portR13_OFFSET
-	swi r12, r1, portR12_OFFSET
-	swi r11, r1, portR11_OFFSET
-	swi r10, r1, portR10_OFFSET
-	swi r9, r1, portR9_OFFSET
-	swi r8, r1, portR8_OFFSET
-	swi r7, r1, portR7_OFFSET
-	swi r6, r1, portR6_OFFSET
-	swi r5, r1, portR5_OFFSET
-	swi r4, r1, portR4_OFFSET
-	swi r3, r1, portR3_OFFSET
-	swi r2, r1, portR2_OFFSET
-
-	/* Stack the critical section nesting value. */
-	lwi r18, r0, uxCriticalNesting
-	swi r18, r1, portCRITICAL_NESTING_OFFSET
-
-	/* Stack MSR. */
-	mfs r18, rmsr
-	swi r18, r1, portMSR_OFFSET
-
-	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
-		/* Stack FSR. */
-		mfs r18, rfsr
-		swi r18, r1, portFSR_OFFSET
-	#endif
-
-	/* Save the top of stack value to the TCB. */
-	lwi r3, r0, pxCurrentTCB
-	sw	r1, r0, r3
-
-	.endm
-
-.macro portRESTORE_CONTEXT
-
-	/* Load the top of stack value from the TCB. */
-	lwi r18, r0, pxCurrentTCB
-	lw	r1, r0, r18
-
-	/* Restore the general registers. */
-	lwi r31, r1, portR31_OFFSET
-	lwi r30, r1, portR30_OFFSET
-	lwi r29, r1, portR29_OFFSET
-	lwi r28, r1, portR28_OFFSET
-	lwi r27, r1, portR27_OFFSET
-	lwi r26, r1, portR26_OFFSET
-	lwi r25, r1, portR25_OFFSET
-	lwi r24, r1, portR24_OFFSET
-	lwi r23, r1, portR23_OFFSET
-	lwi r22, r1, portR22_OFFSET
-	lwi r21, r1, portR21_OFFSET
-	lwi r20, r1, portR20_OFFSET
-	lwi r19, r1, portR19_OFFSET
-	lwi r17, r1, portR17_OFFSET
-	lwi r16, r1, portR16_OFFSET
-	lwi r15, r1, portR15_OFFSET
-	lwi r14, r1, portR14_OFFSET
-	lwi r13, r1, portR13_OFFSET
-	lwi r12, r1, portR12_OFFSET
-	lwi r11, r1, portR11_OFFSET
-	lwi r10, r1, portR10_OFFSET
-	lwi r9, r1, portR9_OFFSET
-	lwi r8, r1, portR8_OFFSET
-	lwi r7, r1, portR7_OFFSET
-	lwi r6, r1, portR6_OFFSET
-	lwi r5, r1, portR5_OFFSET
-	lwi r4, r1, portR4_OFFSET
-	lwi r3, r1, portR3_OFFSET
-	lwi r2, r1, portR2_OFFSET
-
-	/* Reload the rmsr from the stack. */
-	lwi r18, r1, portMSR_OFFSET
-	mts rmsr, r18
-
-	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
-		/* Reload the FSR from the stack. */
-		lwi r18, r1, portFSR_OFFSET
-		mts rfsr, r18
-	#endif
-
-	/* Load the critical nesting value. */
-	lwi r18, r1, portCRITICAL_NESTING_OFFSET
-	swi r18, r0, uxCriticalNesting
-
-	/* Test the critical nesting value.  If it is non zero then the task last
-	exited the running state using a yield.  If it is zero, then the task
-	last exited the running state through an interrupt. */
-	xori r18, r18, 0
-	bnei r18, exit_from_yield
-
-	/* r18 was being used as a temporary.  Now restore its true value from the
-	stack. */
-	lwi r18, r1, portR18_OFFSET
-
-	/* Remove the stack frame. */
-	addik r1, r1, portCONTEXT_SIZE
-
-	/* Return using rtid so interrupts are re-enabled as this function is
-	exited. */
-	rtid r14, 0
-	or r0, r0, r0
-
-	.endm
-
-/* This function is used to exit portRESTORE_CONTEXT() if the task being
-returned to last left the Running state by calling taskYIELD() (rather than
-being preempted by an interrupt). */
-	.text
-	.align  4
-exit_from_yield:
-
-	/* r18 was being used as a temporary.  Now restore its true value from the
-	stack. */
-	lwi r18, r1, portR18_OFFSET
-
-	/* Remove the stack frame. */
-	addik r1, r1, portCONTEXT_SIZE
-
-	/* Return to the task. */
-	rtsd r14, 0
-	or r0, r0, r0
-
-
-	.text
-	.align  4
-_interrupt_handler:
-
-	portSAVE_CONTEXT
-
-	/* Stack the return address. */
-	swi r14, r1, portR14_OFFSET
-
-	/* Switch to the ISR stack. */
-	lwi r1, r0, pulISRStack
-
-	/* The parameter to the interrupt handler. */
-	ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE
-
-	/* Execute any pending interrupts. */
-	bralid r15, XIntc_DeviceInterruptHandler
-	or r0, r0, r0
-
-	/* See if a new task should be selected to execute. */
-	lwi r18, r0, ulTaskSwitchRequested
-	or r18, r18, r0
-
-	/* If ulTaskSwitchRequested is already zero, then jump straight to
-	restoring the task that is already in the Running state. */
-	beqi r18, task_switch_not_requested
-
-	/* Set ulTaskSwitchRequested back to zero as a task switch is about to be
-	performed. */
-	swi r0, r0, ulTaskSwitchRequested
-
-	/* ulTaskSwitchRequested was not 0 when tested.  Select the next task to
-	execute. */
-	bralid r15, vTaskSwitchContext
-	or r0, r0, r0
-
-task_switch_not_requested:
-
-	/* Restore the context of the next task scheduled to execute. */
-	portRESTORE_CONTEXT
-
-
-	.text
-	.align  4
-VPortYieldASM:
-
-	portSAVE_CONTEXT
-
-	/* Modify the return address so a return is done to the instruction after
-	the call to VPortYieldASM. */
-	addi r14, r14, 8
-	swi r14, r1, portR14_OFFSET
-
-	/* Switch to use the ISR stack. */
-	lwi r1, r0, pulISRStack
-
-	/* Select the next task to execute. */
-	bralid r15, vTaskSwitchContext
-	or r0, r0, r0
-
-	/* Restore the context of the next task scheduled to execute. */
-	portRESTORE_CONTEXT
-
-	.text
-	.align  4
-vPortStartFirstTask:
-
-	portRESTORE_CONTEXT
-
-
-
-#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
-
-	.text
-	.align 4
-vPortExceptionHandlerEntry:
-
-	/* Take a copy of the stack pointer before vPortExecptionHandler is called,
-	storing its value prior to the function stack frame being created. */
-	swi r1, r0, pulStackPointerOnFunctionEntry
-	bralid r15, vPortExceptionHandler
-	or r0, r0, r0
-
-#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portmacro.h b/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portmacro.h
deleted file mode 100755
index a00cc89..0000000
--- a/FreeRTOS/Source/portable/GCC/MicroBlazeV8/portmacro.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* BSP includes. */
-#include 
-#include 
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros and functions. */
-void microblaze_disable_interrupts( void );
-void microblaze_enable_interrupts( void );
-#define portDISABLE_INTERRUPTS()	microblaze_disable_interrupts()
-#define portENABLE_INTERRUPTS()		microblaze_enable_interrupts()
-/*-----------------------------------------------------------*/
-
-/* Critical section macros. */
-void vPortEnterCritical( void );
-void vPortExitCritical( void );
-#define portENTER_CRITICAL()		{																\
-										extern volatile UBaseType_t uxCriticalNesting;				\
-										microblaze_disable_interrupts();							\
-										uxCriticalNesting++;										\
-									}
-
-#define portEXIT_CRITICAL()			{																\
-										extern volatile UBaseType_t uxCriticalNesting;				\
-										/* Interrupts are disabled, so we can */					\
-										/* access the variable directly. */							\
-										uxCriticalNesting--;										\
-										if( uxCriticalNesting == 0 )								\
-										{															\
-											/* The nesting has unwound and we 						\
-											can enable interrupts again. */							\
-											portENABLE_INTERRUPTS();								\
-										}															\
-									}
-
-/*-----------------------------------------------------------*/
-
-/* The yield macro maps directly to the vPortYield() function. */
-void vPortYield( void );
-#define portYIELD() vPortYield()
-
-/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
-sets a flag to say that a yield has been requested.  The interrupt exit code
-then checks this flag, and calls vTaskSwitchContext() before restoring a task
-context, if the flag is not false.  This is done to prevent multiple calls to
-vTaskSwitchContext() being made from a single interrupt, as a single interrupt
-can result in multiple peripherals being serviced. */
-extern volatile uint32_t ulTaskSwitchRequested;
-#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
-
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-
-	/* Generic helper function. */
-	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-	{
-	uint8_t ucReturn;
-
-		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
-		return ucReturn;
-	}
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			4
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()					asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-/* The following structure is used by the FreeRTOS exception handler.  It is
-filled with the MicroBlaze context as it was at the time the exception occurred.
-This is done as an aid to debugging exception occurrences. */
-typedef struct PORT_REGISTER_DUMP
-{
-	/* The following structure members hold the values of the MicroBlaze
-	registers at the time the exception was raised. */
-	uint32_t ulR1_SP;
-	uint32_t ulR2_small_data_area;
-	uint32_t ulR3;
-	uint32_t ulR4;
-	uint32_t ulR5;
-	uint32_t ulR6;
-	uint32_t ulR7;
-	uint32_t ulR8;
-	uint32_t ulR9;
-	uint32_t ulR10;
-	uint32_t ulR11;
-	uint32_t ulR12;
-	uint32_t ulR13_read_write_small_data_area;
-	uint32_t ulR14_return_address_from_interrupt;
-	uint32_t ulR15_return_address_from_subroutine;
-	uint32_t ulR16_return_address_from_trap;
-	uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
-	uint32_t ulR18;
-	uint32_t ulR19;
-	uint32_t ulR20;
-	uint32_t ulR21;
-	uint32_t ulR22;
-	uint32_t ulR23;
-	uint32_t ulR24;
-	uint32_t ulR25;
-	uint32_t ulR26;
-	uint32_t ulR27;
-	uint32_t ulR28;
-	uint32_t ulR29;
-	uint32_t ulR30;
-	uint32_t ulR31;
-	uint32_t ulPC;
-	uint32_t ulESR;
-	uint32_t ulMSR;
-	uint32_t ulEAR;
-	uint32_t ulFSR;
-	uint32_t ulEDR;
-
-	/* A human readable description of the exception cause.  The strings used
-	are the same as the #define constant names found in the
-	microblaze_exceptions_i.h header file */
-	int8_t *pcExceptionCause;
-
-	/* The human readable name of the task that was running at the time the
-	exception occurred.  This is the name that was given to the task when the
-	task was created using the FreeRTOS xTaskCreate() API function. */
-	char *pcCurrentTaskName;
-
-	/* The handle of the task that was running a the time the exception
-	occurred. */
-	void * xCurrentTaskHandle;
-
-} xPortRegisterDump;
-
-
-/*
- * Installs pxHandler as the interrupt handler for the peripheral specified by
- * the ucInterruptID parameter.
- *
- * ucInterruptID:
- *
- * The ID of the peripheral that will have pxHandler assigned as its interrupt
- * handler.  Peripheral IDs are defined in the xparameters.h header file, which
- * is itself part of the BSP project.  For example, in the official demo
- * application for this port, xparameters.h defines the following IDs for the
- * four possible interrupt sources:
- *
- * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
- * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
- * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
- * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
- *
- *
- * pxHandler:
- *
- * A pointer to the interrupt handler function itself.  This must be a void
- * function that takes a (void *) parameter.
- *
- *
- * pvCallBackRef:
- *
- * The parameter passed into the handler function.  In many cases this will not
- * be used and can be NULL.  Some times it is used to pass in a reference to
- * the peripheral instance variable, so it can be accessed from inside the
- * handler function.
- *
- *
- * pdPASS is returned if the function executes successfully.  Any other value
- * being returned indicates that the function did not execute correctly.
- */
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
-
-
-/*
- * Enables the interrupt, within the interrupt controller, for the peripheral
- * specified by the ucInterruptID parameter.
- *
- * ucInterruptID:
- *
- * The ID of the peripheral that will have its interrupt enabled in the
- * interrupt controller.  Peripheral IDs are defined in the xparameters.h header
- * file, which is itself part of the BSP project.  For example, in the official
- * demo application for this port, xparameters.h defines the following IDs for
- * the four possible interrupt sources:
- *
- * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
- * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
- * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
- * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
- *
- */
-void vPortEnableInterrupt( uint8_t ucInterruptID );
-
-/*
- * Disables the interrupt, within the interrupt controller, for the peripheral
- * specified by the ucInterruptID parameter.
- *
- * ucInterruptID:
- *
- * The ID of the peripheral that will have its interrupt disabled in the
- * interrupt controller.  Peripheral IDs are defined in the xparameters.h header
- * file, which is itself part of the BSP project.  For example, in the official
- * demo application for this port, xparameters.h defines the following IDs for
- * the four possible interrupt sources:
- *
- * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
- * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
- * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
- * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
- *
- */
-void vPortDisableInterrupt( uint8_t ucInterruptID );
-
-/*
- * This is an application defined callback function used to install the tick
- * interrupt handler.  It is provided as an application callback because the
- * kernel will run on lots of different MicroBlaze and FPGA configurations - not
- * all of which will have the same timer peripherals defined or available.  This
- * example uses the AXI Timer 0.  If that is available on your hardware platform
- * then this example callback implementation should not require modification.
- * The name of the interrupt handler that should be installed is vPortTickISR(),
- * which the function below declares as an extern.
- */
-void vApplicationSetupTimerInterrupt( void );
-
-/*
- * This is an application defined callback function used to clear whichever
- * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback
- * function - in this case the interrupt generated by the AXI timer.  It is
- * provided as an application callback because the kernel will run on lots of
- * different MicroBlaze and FPGA configurations - not all of which will have the
- * same timer peripherals defined or available.  This example uses the AXI Timer 0.
- * If that is available on your hardware platform then this example callback
- * implementation should not require modification provided the example definition
- * of vApplicationSetupTimerInterrupt() is also not modified.
- */
-void vApplicationClearTimerInterrupt( void );
-
-/*
- * vPortExceptionsInstallHandlers() is only available when the MicroBlaze
- * is configured to include exception functionality, and
- * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h.
- *
- * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler
- * for every possible exception cause.
- *
- * vPortExceptionsInstallHandlers() can be called explicitly from application
- * code.  After that is done, the default FreeRTOS exception handler that will
- * have been installed can be replaced for any specific exception cause by using
- * the standard Xilinx library function microblaze_register_exception_handler().
- *
- * If vPortExceptionsInstallHandlers() is not called explicitly by the
- * application, it will be called automatically by the kernel the first time
- * xPortInstallInterruptHandler() is called.  At that time, any exception
- * handlers that may have already been installed will be replaced.
- *
- * See the description of vApplicationExceptionRegisterDump() for information
- * on the processing performed by the FreeRTOS exception handler.
- */
-void vPortExceptionsInstallHandlers( void );
-
-/*
- * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined
- * in portmacro.h) with the MicroBlaze context, as it was at the time the
- * exception occurred.  The exception handler then calls
- * vApplicationExceptionRegisterDump(), passing in the completed
- * xPortRegisterDump structure as its parameter.
- *
- * The FreeRTOS kernel provides its own implementation of
- * vApplicationExceptionRegisterDump(), but the kernel provided implementation
- * is declared as being 'weak'.  The weak definition allows the application
- * writer to provide their own implementation, should they wish to use the
- * register dump information.  For example, an implementation could be provided
- * that wrote the register dump data to a display, or a UART port.
- */
-void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c b/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c
deleted file mode 100755
index 5d8d7f4..0000000
--- a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port.c
+++ /dev/null
@@ -1,460 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MicroBlaze port.
- *----------------------------------------------------------*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Standard includes. */
-#include 
-
-/* Hardware includes. */
-#include 
-#include 
-#include 
-
-/* Tasks are started with a critical section nesting of 0 - however, prior to
-the scheduler being commenced interrupts should not be enabled, so the critical
-nesting variable is initialised to a non-zero value. */
-#define portINITIAL_NESTING_VALUE	( 0xff )
-
-/* The bit within the MSR register that enabled/disables interrupts and
-exceptions respectively. */
-#define portMSR_IE					( 0x02U )
-#define portMSR_EE					( 0x100U )
-
-/* If the floating point unit is included in the MicroBlaze build, then the
-FSR register is saved as part of the task context.  portINITIAL_FSR is the value
-given to the FSR register when the initial context is set up for a task being
-created. */
-#define portINITIAL_FSR				( 0U )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the interrupt controller instance.
- */
-static int32_t prvInitialiseInterruptController( void );
-
-/* Ensure the interrupt controller instance variable is initialised before it is
- * used, and that the initialisation only happens once.
- */
-static int32_t prvEnsureInterruptControllerIsInitialised( void );
-
-/*-----------------------------------------------------------*/
-
-/* Counts the nesting depth of calls to portENTER_CRITICAL().  Each task
-maintains its own count, so this variable is saved as part of the task
-context. */
-volatile UBaseType_t uxCriticalNesting = portINITIAL_NESTING_VALUE;
-
-/* This port uses a separate stack for interrupts.  This prevents the stack of
-every task needing to be large enough to hold an entire interrupt stack on top
-of the task stack. */
-uint32_t *pulISRStack;
-
-/* If an interrupt requests a context switch, then ulTaskSwitchRequested will
-get set to 1.  ulTaskSwitchRequested is inspected just before the main interrupt
-handler exits.  If, at that time, ulTaskSwitchRequested is set to 1, the kernel
-will call vTaskSwitchContext() to ensure the task that runs immediately after
-the interrupt exists is the highest priority task that is able to run.  This is
-an unusual mechanism, but is used for this port because a single interrupt can
-cause the servicing of multiple peripherals - and it is inefficient to call
-vTaskSwitchContext() multiple times as each peripheral is serviced. */
-volatile uint32_t ulTaskSwitchRequested = 0UL;
-
-/* The instance of the interrupt controller used by this port.  This is required
-by the Xilinx library API functions. */
-static XIntc xInterruptControllerInstance;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been made.
- *
- * See the portable.h header file.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-extern void *_SDA2_BASE_, *_SDA_BASE_;
-const uint32_t ulR2 = ( uint32_t ) &_SDA2_BASE_;
-const uint32_t ulR13 = ( uint32_t ) &_SDA_BASE_;
-extern void _start1( void );
-
-	/* Place a few bytes of known values on the bottom of the stack.
-	This is essential for the Microblaze port and these lines must
-	not be omitted. */
-	*pxTopOfStack = ( StackType_t ) 0x00000000;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00000000;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00000000;
-	pxTopOfStack--;
-
-	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
-		/* The FSR value placed in the initial task context is just 0. */
-		*pxTopOfStack = portINITIAL_FSR;
-		pxTopOfStack--;
-	#endif
-
-	/* The MSR value placed in the initial task context should have interrupts
-	disabled.  Each task will enable interrupts automatically when it enters
-	the running state for the first time. */
-	*pxTopOfStack = mfmsr() & ~portMSR_IE;
-
-	#if( MICROBLAZE_EXCEPTIONS_ENABLED == 1 )
-	{
-		/* Ensure exceptions are enabled for the task. */
-		*pxTopOfStack |= portMSR_EE;
-	}
-	#endif
-
-	pxTopOfStack--;
-
-	/* First stack an initial value for the critical section nesting.  This
-	is initialised to zero. */
-	*pxTopOfStack = ( StackType_t ) 0x00;
-
-	/* R0 is always zero. */
-	/* R1 is the SP. */
-
-	/* Place an initial value for all the general purpose registers. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) ulR2;	/* R2 - read only small data area. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3 - return values and temporaries. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4 - return values and temporaries. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pvParameters;/* R5 contains the function call parameters. */
-
-	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06;	/* R6 - other parameters and temporaries. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07;	/* R7 - other parameters and temporaries. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) NULL;	/* R8 - other parameters and temporaries. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09;	/* R9 - other parameters and temporaries. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x0a;	/* R10 - other parameters and temporaries. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x0b;	/* R11 - temporaries. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x0c;	/* R12 - temporaries. */
-		pxTopOfStack--;
-	#else
-		pxTopOfStack-= 8;
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) ulR13;	/* R13 - read/write small data area. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;	/* R14 - return address for interrupt. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) _start1;	/* R15 - return address for subroutine. */
-
-	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10;	/* R16 - return address for trap (debugger). */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11;	/* R17 - return address for exceptions, if configured. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12;	/* R18 - reserved for assembler and compiler temporaries. */
-		pxTopOfStack--;
-	#else
-		pxTopOfStack -= 4;
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) 0x00;	/* R19 - must be saved across function calls. Callee-save.  Seems to be interpreted as the frame pointer. */
-
-	#ifdef portPRE_LOAD_STACK_FOR_DEBUGGING
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x14;	/* R20 - reserved for storing a pointer to the Global Offset Table (GOT) in Position Independent Code (PIC). Non-volatile in non-PIC code. Must be saved across function calls. Callee-save.  Not used by FreeRTOS. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x15;	/* R21 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x16;	/* R22 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x17;	/* R23 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x18;	/* R24 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x19;	/* R25 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x1a;	/* R26 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x1b;	/* R27 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x1c;	/* R28 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x1d;	/* R29 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x1e;	/* R30 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x1f;	/* R31 - must be saved across function calls. Callee-save. */
-		pxTopOfStack--;
-	#else
-		pxTopOfStack -= 13;
-	#endif
-
-	/* Return a pointer to the top of the stack that has been generated so this
-	can	be stored in the task control block for the task. */
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void ( vPortStartFirstTask )( void );
-extern uint32_t _stack[];
-
-	/* Setup the hardware to generate the tick.  Interrupts are disabled when
-	this function is called.
-
-	This port uses an application defined callback function to install the tick
-	interrupt handler because the kernel will run on lots of different
-	MicroBlaze and FPGA configurations - not all of	which will have the same
-	timer peripherals defined or available.  An example definition of
-	vApplicationSetupTimerInterrupt() is provided in the official demo
-	application that accompanies this port. */
-	vApplicationSetupTimerInterrupt();
-
-	/* Reuse the stack from main() as the stack for the interrupts/exceptions. */
-	pulISRStack = ( uint32_t * ) _stack;
-
-	/* Ensure there is enough space for the functions called from the interrupt
-	service routines to write back into the stack frame of the caller. */
-	pulISRStack -= 2;
-
-	/* Restore the context of the first task that is going to run.  From here
-	on, the created tasks will be executing. */
-	vPortStartFirstTask();
-
-	/* Should not get here as the tasks are now running! */
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch called by portYIELD or taskYIELD.
- */
-void vPortYield( void )
-{
-extern void VPortYieldASM( void );
-
-	/* Perform the context switch in a critical section to assure it is
-	not interrupted by the tick ISR.  It is not a problem to do this as
-	each task maintains its own interrupt status. */
-	portENTER_CRITICAL();
-	{
-		/* Jump directly to the yield function to ensure there is no
-		compiler generated prologue code. */
-		asm volatile (	"bralid r14, VPortYieldASM		\n\t" \
-						"or r0, r0, r0					\n\t" );
-	}
-	portEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnableInterrupt( uint8_t ucInterruptID )
-{
-int32_t lReturn;
-
-	/* An API function is provided to enable an interrupt in the interrupt
-	controller because the interrupt controller instance variable is private
-	to this file. */
-	lReturn = prvEnsureInterruptControllerIsInitialised();
-	if( lReturn == pdPASS )
-	{
-		/* Critical section protects read/modify/writer operation inside
-		XIntc_Enable(). */
-		portENTER_CRITICAL();
-		{
-			XIntc_Enable( &xInterruptControllerInstance, ucInterruptID );
-		}
-		portEXIT_CRITICAL();
-	}
-
-	configASSERT( lReturn );
-}
-/*-----------------------------------------------------------*/
-
-void vPortDisableInterrupt( uint8_t ucInterruptID )
-{
-int32_t lReturn;
-
-	/* An API function is provided to disable an interrupt in the interrupt
-	controller because the interrupt controller instance variable is private
-	to this file. */
-	lReturn = prvEnsureInterruptControllerIsInitialised();
-
-	if( lReturn == pdPASS )
-	{
-		XIntc_Disable( &xInterruptControllerInstance, ucInterruptID );
-	}
-
-	configASSERT( lReturn );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
-{
-int32_t lReturn;
-
-	/* An API function is provided to install an interrupt handler because the
-	interrupt controller instance variable is private to this file. */
-
-	lReturn = prvEnsureInterruptControllerIsInitialised();
-
-	if( lReturn == pdPASS )
-	{
-		lReturn = XIntc_Connect( &xInterruptControllerInstance, ucInterruptID, pxHandler, pvCallBackRef );
-	}
-
-	if( lReturn == XST_SUCCESS )
-	{
-		lReturn = pdPASS;
-	}
-
-	configASSERT( lReturn == pdPASS );
-
-	return lReturn;
-}
-/*-----------------------------------------------------------*/
-
-static int32_t prvEnsureInterruptControllerIsInitialised( void )
-{
-static int32_t lInterruptControllerInitialised = pdFALSE;
-int32_t lReturn;
-
-	/* Ensure the interrupt controller instance variable is initialised before
-	it is used, and that the initialisation only happens once. */
-	if( lInterruptControllerInitialised != pdTRUE )
-	{
-		lReturn = prvInitialiseInterruptController();
-
-		if( lReturn == pdPASS )
-		{
-			lInterruptControllerInitialised = pdTRUE;
-		}
-	}
-	else
-	{
-		lReturn = pdPASS;
-	}
-
-	return lReturn;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Handler for the timer interrupt.  This is the handler that the application
- * defined callback function vApplicationSetupTimerInterrupt() should install.
- */
-void vPortTickISR( void *pvUnused )
-{
-extern void vApplicationClearTimerInterrupt( void );
-
-	/* Ensure the unused parameter does not generate a compiler warning. */
-	( void ) pvUnused;
-
-	/* This port uses an application defined callback function to clear the tick
-	interrupt because the kernel will run on lots of different MicroBlaze and
-	FPGA configurations - not all of which will have the same timer peripherals
-	defined or available.  An example definition of
-	vApplicationClearTimerInterrupt() is provided in the official demo
-	application that accompanies this port. */
-	vApplicationClearTimerInterrupt();
-
-	/* Increment the RTOS tick - this might cause a task to unblock. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		/* Force vTaskSwitchContext() to be called as the interrupt exits. */
-		ulTaskSwitchRequested = 1;
-	}
-}
-/*-----------------------------------------------------------*/
-
-static int32_t prvInitialiseInterruptController( void )
-{
-int32_t lStatus;
-
-	lStatus = XIntc_Initialize( &xInterruptControllerInstance, configINTERRUPT_CONTROLLER_TO_USE );
-
-	if( lStatus == XST_SUCCESS )
-	{
-		/* Initialise the exception table. */
-		Xil_ExceptionInit();
-
-	    /* Service all pending interrupts each time the handler is entered. */
-	    XIntc_SetIntrSvcOption( xInterruptControllerInstance.BaseAddress, XIN_SVC_ALL_ISRS_OPTION );
-
-	    /* Install exception handlers if the MicroBlaze is configured to handle
-	    exceptions, and the application defined constant
-	    configINSTALL_EXCEPTION_HANDLERS is set to 1. */
-		#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
-	    {
-	    	vPortExceptionsInstallHandlers();
-	    }
-		#endif /* MICROBLAZE_EXCEPTIONS_ENABLED */
-
-		/* Start the interrupt controller.  Interrupts are enabled when the
-		scheduler starts. */
-		lStatus = XIntc_Start( &xInterruptControllerInstance, XIN_REAL_MODE );
-
-		if( lStatus == XST_SUCCESS )
-		{
-			lStatus = pdPASS;
-		}
-		else
-		{
-			lStatus = pdFAIL;
-		}
-	}
-
-	configASSERT( lStatus == pdPASS );
-
-	return lStatus;
-}
-/*-----------------------------------------------------------*/
-
-
diff --git a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port_exceptions.c b/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port_exceptions.c
deleted file mode 100755
index 2b1cb28..0000000
--- a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/port_exceptions.c
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Hardware includes. */
-#include 
-#include 
-
-/* The Xilinx library defined exception entry point stacks a number of
-registers.  These definitions are offsets from the stack pointer to the various
-stacked register values. */
-#define portexR3_STACK_OFFSET	4
-#define portexR4_STACK_OFFSET	5
-#define portexR5_STACK_OFFSET	6
-#define portexR6_STACK_OFFSET	7
-#define portexR7_STACK_OFFSET	8
-#define portexR8_STACK_OFFSET	9
-#define portexR9_STACK_OFFSET	10
-#define portexR10_STACK_OFFSET	11
-#define portexR11_STACK_OFFSET	12
-#define portexR12_STACK_OFFSET	13
-#define portexR15_STACK_OFFSET	16
-#define portexR18_STACK_OFFSET  19
-#define portexMSR_STACK_OFFSET	20
-#define portexR19_STACK_OFFSET  -1
-
-/* This is defined to equal the size, in bytes, of the stack frame generated by
-the Xilinx standard library exception entry point.  It is required to determine
-the stack pointer value prior to the exception being entered. */
-#define portexASM_HANDLER_STACK_FRAME_SIZE 84UL
-
-/* The number of bytes a MicroBlaze instruction consumes. */
-#define portexINSTRUCTION_SIZE	4
-
-/* Exclude this entire file if the MicroBlaze is not configured to handle
-exceptions, or the application defined configuration constant
-configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
-#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
-
-/* This variable is set in the exception entry code, before
-vPortExceptionHandler is called. */
-uint32_t *pulStackPointerOnFunctionEntry = NULL;
-
-/* This is the structure that is filled with the MicroBlaze context as it
-existed immediately prior to the exception occurrence.  A pointer to this
-structure is passed into the vApplicationExceptionRegisterDump() callback
-function, if one is defined. */
-static xPortRegisterDump xRegisterDump;
-
-/* This is the FreeRTOS exception handler that is installed for all exception
-types.  It is called from vPortExceptionHanlderEntry() - which is itself defined
-in portasm.S. */
-void vPortExceptionHandler( void *pvExceptionID );
-extern void vPortExceptionHandlerEntry( void *pvExceptionID );
-
-/*-----------------------------------------------------------*/
-
-/* vApplicationExceptionRegisterDump() is a callback function that the
-application can optionally define to receive a populated xPortRegisterDump
-structure.  If the application chooses not to define a version of
-vApplicationExceptionRegisterDump() then this weekly defined default
-implementation will be called instead. */
-extern void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump ) __attribute__((weak));
-void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump )
-{
-	( void ) xRegisterDump;
-
-	for( ;; )
-	{
-		portNOP();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExceptionHandler( void *pvExceptionID )
-{
-extern void *pxCurrentTCB;
-
-	/* Fill an xPortRegisterDump structure with the MicroBlaze context as it
-	was immediately before the exception occurrence. */
-
-	/* First fill in the name and handle of the task that was in the Running
-	state when the exception occurred. */
-	xRegisterDump.xCurrentTaskHandle = pxCurrentTCB;
-	xRegisterDump.pcCurrentTaskName = pcTaskGetName( NULL );
-
-	configASSERT( pulStackPointerOnFunctionEntry );
-
-	/* Obtain the values of registers that were stacked prior to this function
-	being called, and may have changed since they were stacked. */
-	xRegisterDump.ulR3 = pulStackPointerOnFunctionEntry[ portexR3_STACK_OFFSET ];
-	xRegisterDump.ulR4 = pulStackPointerOnFunctionEntry[ portexR4_STACK_OFFSET ];
-	xRegisterDump.ulR5 = pulStackPointerOnFunctionEntry[ portexR5_STACK_OFFSET ];
-	xRegisterDump.ulR6 = pulStackPointerOnFunctionEntry[ portexR6_STACK_OFFSET ];
-	xRegisterDump.ulR7 = pulStackPointerOnFunctionEntry[ portexR7_STACK_OFFSET ];
-	xRegisterDump.ulR8 = pulStackPointerOnFunctionEntry[ portexR8_STACK_OFFSET ];
-	xRegisterDump.ulR9 = pulStackPointerOnFunctionEntry[ portexR9_STACK_OFFSET ];
-	xRegisterDump.ulR10 = pulStackPointerOnFunctionEntry[ portexR10_STACK_OFFSET ];
-	xRegisterDump.ulR11 = pulStackPointerOnFunctionEntry[ portexR11_STACK_OFFSET ];
-	xRegisterDump.ulR12 = pulStackPointerOnFunctionEntry[ portexR12_STACK_OFFSET ];
-	xRegisterDump.ulR15_return_address_from_subroutine = pulStackPointerOnFunctionEntry[ portexR15_STACK_OFFSET ];
-	xRegisterDump.ulR18 = pulStackPointerOnFunctionEntry[ portexR18_STACK_OFFSET ];
-	xRegisterDump.ulR19 = pulStackPointerOnFunctionEntry[ portexR19_STACK_OFFSET ];
-	xRegisterDump.ulMSR = pulStackPointerOnFunctionEntry[ portexMSR_STACK_OFFSET ];
-
-	/* Obtain the value of all other registers. */
-	xRegisterDump.ulR2_small_data_area = mfgpr( R2 );
-	xRegisterDump.ulR13_read_write_small_data_area = mfgpr( R13 );
-	xRegisterDump.ulR14_return_address_from_interrupt = mfgpr( R14 );
-	xRegisterDump.ulR16_return_address_from_trap = mfgpr( R16 );
-	xRegisterDump.ulR17_return_address_from_exceptions = mfgpr( R17 );
-	xRegisterDump.ulR20 = mfgpr( R20 );
-	xRegisterDump.ulR21 = mfgpr( R21 );
-	xRegisterDump.ulR22 = mfgpr( R22 );
-	xRegisterDump.ulR23 = mfgpr( R23 );
-	xRegisterDump.ulR24 = mfgpr( R24 );
-	xRegisterDump.ulR25 = mfgpr( R25 );
-	xRegisterDump.ulR26 = mfgpr( R26 );
-	xRegisterDump.ulR27 = mfgpr( R27 );
-	xRegisterDump.ulR28 = mfgpr( R28 );
-	xRegisterDump.ulR29 = mfgpr( R29 );
-	xRegisterDump.ulR30 = mfgpr( R30 );
-	xRegisterDump.ulR31 = mfgpr( R31 );
-	xRegisterDump.ulR1_SP = ( ( uint32_t ) pulStackPointerOnFunctionEntry ) + portexASM_HANDLER_STACK_FRAME_SIZE;
-	xRegisterDump.ulEAR = mfear();
-	xRegisterDump.ulESR = mfesr();
-	xRegisterDump.ulEDR = mfedr();
-
-	/* Move the saved program counter back to the instruction that was executed
-	when the exception occurred.  This is only valid for certain types of
-	exception. */
-	xRegisterDump.ulPC = xRegisterDump.ulR17_return_address_from_exceptions - portexINSTRUCTION_SIZE;
-
-	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
-	{
-		xRegisterDump.ulFSR = mffsr();
-	}
-	#else
-	{
-		xRegisterDump.ulFSR = 0UL;
-	}
-	#endif
-
-	/* Also fill in a string that describes what type of exception this is.
-	The string uses the same ID names as defined in the MicroBlaze standard
-	library exception header files. */
-	switch( ( uint32_t ) pvExceptionID )
-	{
-		case XEXC_ID_FSL :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FSL";
-				break;
-
-		case XEXC_ID_UNALIGNED_ACCESS :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_UNALIGNED_ACCESS";
-				break;
-
-		case XEXC_ID_ILLEGAL_OPCODE :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_ILLEGAL_OPCODE";
-				break;
-
-		case XEXC_ID_M_AXI_I_EXCEPTION :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_I_EXCEPTION or XEXC_ID_IPLB_EXCEPTION";
-				break;
-
-		case XEXC_ID_M_AXI_D_EXCEPTION :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_M_AXI_D_EXCEPTION or XEXC_ID_DPLB_EXCEPTION";
-				break;
-
-		case XEXC_ID_DIV_BY_ZERO :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_DIV_BY_ZERO";
-				break;
-
-		case XEXC_ID_STACK_VIOLATION :
-				xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_STACK_VIOLATION or XEXC_ID_MMU";
-				break;
-
-		#if( XPAR_MICROBLAZE_USE_FPU != 0 )
-
-			case XEXC_ID_FPU :
-						xRegisterDump.pcExceptionCause = ( int8_t * const ) "XEXC_ID_FPU see ulFSR value";
-						break;
-
-		#endif /* XPAR_MICROBLAZE_USE_FPU */
-	}
-
-	/* vApplicationExceptionRegisterDump() is a callback function that the
-	application can optionally define to receive the populated xPortRegisterDump
-	structure.  If the application chooses not to define a version of
-	vApplicationExceptionRegisterDump() then the weekly defined default
-	implementation within this file will be called instead. */
-	vApplicationExceptionRegisterDump( &xRegisterDump );
-
-	/* Must not attempt to leave this function! */
-	for( ;; )
-	{
-		portNOP();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExceptionsInstallHandlers( void )
-{
-static uint32_t ulHandlersAlreadyInstalled = pdFALSE;
-
-	if( ulHandlersAlreadyInstalled == pdFALSE )
-	{
-		ulHandlersAlreadyInstalled = pdTRUE;
-
-		#if XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS == 1
-			microblaze_register_exception_handler( XEXC_ID_UNALIGNED_ACCESS, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_UNALIGNED_ACCESS );
-		#endif /* XPAR_MICROBLAZE_UNALIGNED_EXCEPTIONS*/
-
-		#if XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_ILLEGAL_OPCODE, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_ILLEGAL_OPCODE );
-		#endif /* XPAR_MICROBLAZE_ILL_OPCODE_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_M_AXI_I_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_I_EXCEPTION );
-		#endif /* XPAR_MICROBLAZE_M_AXI_I_BUS_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_M_AXI_D_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_M_AXI_D_EXCEPTION );
-		#endif /* XPAR_MICROBLAZE_M_AXI_D_BUS_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_IPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_IPLB_EXCEPTION );
-		#endif /* XPAR_MICROBLAZE_IPLB_BUS_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_DPLB_EXCEPTION, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DPLB_EXCEPTION );
-		#endif /* XPAR_MICROBLAZE_DPLB_BUS_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_DIV_BY_ZERO, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_DIV_BY_ZERO );
-		#endif /* XPAR_MICROBLAZE_DIV_ZERO_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_FPU_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_FPU, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FPU );
-		#endif /* XPAR_MICROBLAZE_FPU_EXCEPTION */
-
-		#if XPAR_MICROBLAZE_FSL_EXCEPTION == 1
-			microblaze_register_exception_handler( XEXC_ID_FSL, vPortExceptionHandlerEntry, ( void * ) XEXC_ID_FSL );
-		#endif /* XPAR_MICROBLAZE_FSL_EXCEPTION */
-
-		microblaze_enable_exceptions();
-	}
-}
-
-/* Exclude the entire file if the MicroBlaze is not configured to handle
-exceptions, or the application defined configuration item
-configINSTALL_EXCEPTION_HANDLERS is not set to 1. */
-#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portasm.S b/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portasm.S
deleted file mode 100755
index c603041..0000000
--- a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portasm.S
+++ /dev/null
@@ -1,328 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/* Xilinx library includes. */
-#include "microblaze_exceptions_g.h"
-#include "xparameters.h"
-
-/* The context is oversized to allow functions called from the ISR to write
-back into the caller stack. */
-#if( XPAR_MICROBLAZE_USE_FPU != 0 )
-	#define portCONTEXT_SIZE 136
-	#define portMINUS_CONTEXT_SIZE -136
-#else
-	#define portCONTEXT_SIZE 132
-	#define portMINUS_CONTEXT_SIZE -132
-#endif
-
-/* Offsets from the stack pointer at which saved registers are placed. */
-#define portR31_OFFSET	4
-#define portR30_OFFSET	8
-#define portR29_OFFSET	12
-#define portR28_OFFSET	16
-#define portR27_OFFSET	20
-#define portR26_OFFSET	24
-#define portR25_OFFSET	28
-#define portR24_OFFSET	32
-#define portR23_OFFSET	36
-#define portR22_OFFSET	40
-#define portR21_OFFSET	44
-#define portR20_OFFSET	48
-#define portR19_OFFSET	52
-#define portR18_OFFSET	56
-#define portR17_OFFSET	60
-#define portR16_OFFSET	64
-#define portR15_OFFSET	68
-#define portR14_OFFSET	72
-#define portR13_OFFSET	76
-#define portR12_OFFSET	80
-#define portR11_OFFSET	84
-#define portR10_OFFSET	88
-#define portR9_OFFSET	92
-#define portR8_OFFSET	96
-#define portR7_OFFSET	100
-#define portR6_OFFSET	104
-#define portR5_OFFSET	108
-#define portR4_OFFSET	112
-#define portR3_OFFSET	116
-#define portR2_OFFSET	120
-#define portCRITICAL_NESTING_OFFSET 124
-#define portMSR_OFFSET 128
-#define portFSR_OFFSET 132
-
-	.extern pxCurrentTCB
-	.extern XIntc_DeviceInterruptHandler
-	.extern vTaskSwitchContext
-	.extern uxCriticalNesting
-	.extern pulISRStack
-	.extern ulTaskSwitchRequested
-	.extern vPortExceptionHandler
-	.extern pulStackPointerOnFunctionEntry
-
-	.global _interrupt_handler
-	.global VPortYieldASM
-	.global vPortStartFirstTask
-	.global vPortExceptionHandlerEntry
-
-
-.macro portSAVE_CONTEXT
-
-	/* Make room for the context on the stack. */
-	addik r1, r1, portMINUS_CONTEXT_SIZE
-
-	/* Stack general registers. */
-	swi r31, r1, portR31_OFFSET
-	swi r30, r1, portR30_OFFSET
-	swi r29, r1, portR29_OFFSET
-	swi r28, r1, portR28_OFFSET
-	swi r27, r1, portR27_OFFSET
-	swi r26, r1, portR26_OFFSET
-	swi r25, r1, portR25_OFFSET
-	swi r24, r1, portR24_OFFSET
-	swi r23, r1, portR23_OFFSET
-	swi r22, r1, portR22_OFFSET
-	swi r21, r1, portR21_OFFSET
-	swi r20, r1, portR20_OFFSET
-	swi r19, r1, portR19_OFFSET
-	swi r18, r1, portR18_OFFSET
-	swi r17, r1, portR17_OFFSET
-	swi r16, r1, portR16_OFFSET
-	swi r15, r1, portR15_OFFSET
-	/* R14 is saved later as it needs adjustment if a yield is performed. */
-	swi r13, r1, portR13_OFFSET
-	swi r12, r1, portR12_OFFSET
-	swi r11, r1, portR11_OFFSET
-	swi r10, r1, portR10_OFFSET
-	swi r9, r1, portR9_OFFSET
-	swi r8, r1, portR8_OFFSET
-	swi r7, r1, portR7_OFFSET
-	swi r6, r1, portR6_OFFSET
-	swi r5, r1, portR5_OFFSET
-	swi r4, r1, portR4_OFFSET
-	swi r3, r1, portR3_OFFSET
-	swi r2, r1, portR2_OFFSET
-
-	/* Stack the critical section nesting value. */
-	lwi r18, r0, uxCriticalNesting
-	swi r18, r1, portCRITICAL_NESTING_OFFSET
-
-	/* Stack MSR. */
-	mfs r18, rmsr
-	swi r18, r1, portMSR_OFFSET
-
-	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
-		/* Stack FSR. */
-		mfs r18, rfsr
-		swi r18, r1, portFSR_OFFSET
-	#endif
-
-	/* Save the top of stack value to the TCB. */
-	lwi r3, r0, pxCurrentTCB
-	sw	r1, r0, r3
-
-	.endm
-
-.macro portRESTORE_CONTEXT
-
-	/* Load the top of stack value from the TCB. */
-	lwi r18, r0, pxCurrentTCB
-	lw	r1, r0, r18
-
-	/* Restore the general registers. */
-	lwi r31, r1, portR31_OFFSET
-	lwi r30, r1, portR30_OFFSET
-	lwi r29, r1, portR29_OFFSET
-	lwi r28, r1, portR28_OFFSET
-	lwi r27, r1, portR27_OFFSET
-	lwi r26, r1, portR26_OFFSET
-	lwi r25, r1, portR25_OFFSET
-	lwi r24, r1, portR24_OFFSET
-	lwi r23, r1, portR23_OFFSET
-	lwi r22, r1, portR22_OFFSET
-	lwi r21, r1, portR21_OFFSET
-	lwi r20, r1, portR20_OFFSET
-	lwi r19, r1, portR19_OFFSET
-	lwi r17, r1, portR17_OFFSET
-	lwi r16, r1, portR16_OFFSET
-	lwi r15, r1, portR15_OFFSET
-	lwi r14, r1, portR14_OFFSET
-	lwi r13, r1, portR13_OFFSET
-	lwi r12, r1, portR12_OFFSET
-	lwi r11, r1, portR11_OFFSET
-	lwi r10, r1, portR10_OFFSET
-	lwi r9, r1, portR9_OFFSET
-	lwi r8, r1, portR8_OFFSET
-	lwi r7, r1, portR7_OFFSET
-	lwi r6, r1, portR6_OFFSET
-	lwi r5, r1, portR5_OFFSET
-	lwi r4, r1, portR4_OFFSET
-	lwi r3, r1, portR3_OFFSET
-	lwi r2, r1, portR2_OFFSET
-
-	/* Reload the rmsr from the stack. */
-	lwi r18, r1, portMSR_OFFSET
-	mts rmsr, r18
-
-	#if( XPAR_MICROBLAZE_USE_FPU != 0 )
-		/* Reload the FSR from the stack. */
-		lwi r18, r1, portFSR_OFFSET
-		mts rfsr, r18
-	#endif
-
-	/* Load the critical nesting value. */
-	lwi r18, r1, portCRITICAL_NESTING_OFFSET
-	swi r18, r0, uxCriticalNesting
-
-	/* Test the critical nesting value.  If it is non zero then the task last
-	exited the running state using a yield.  If it is zero, then the task
-	last exited the running state through an interrupt. */
-	xori r18, r18, 0
-	bnei r18, exit_from_yield
-
-	/* r18 was being used as a temporary.  Now restore its true value from the
-	stack. */
-	lwi r18, r1, portR18_OFFSET
-
-	/* Remove the stack frame. */
-	addik r1, r1, portCONTEXT_SIZE
-
-	/* Return using rtid so interrupts are re-enabled as this function is
-	exited. */
-	rtid r14, 0
-	or r0, r0, r0
-
-	.endm
-
-/* This function is used to exit portRESTORE_CONTEXT() if the task being
-returned to last left the Running state by calling taskYIELD() (rather than
-being preempted by an interrupt). */
-	.text
-	.align  4
-exit_from_yield:
-
-	/* r18 was being used as a temporary.  Now restore its true value from the
-	stack. */
-	lwi r18, r1, portR18_OFFSET
-
-	/* Remove the stack frame. */
-	addik r1, r1, portCONTEXT_SIZE
-
-	/* Return to the task. */
-	rtsd r14, 0
-	or r0, r0, r0
-
-
-	.text
-	.align  4
-_interrupt_handler:
-
-	portSAVE_CONTEXT
-
-	/* Stack the return address. */
-	swi r14, r1, portR14_OFFSET
-
-	/* Switch to the ISR stack. */
-	lwi r1, r0, pulISRStack
-
-	/* The parameter to the interrupt handler. */
-	ori r5, r0, configINTERRUPT_CONTROLLER_TO_USE
-
-	/* Execute any pending interrupts. */
-	bralid r15, XIntc_DeviceInterruptHandler
-	or r0, r0, r0
-
-	/* See if a new task should be selected to execute. */
-	lwi r18, r0, ulTaskSwitchRequested
-	or r18, r18, r0
-
-	/* If ulTaskSwitchRequested is already zero, then jump straight to
-	restoring the task that is already in the Running state. */
-	beqi r18, task_switch_not_requested
-
-	/* Set ulTaskSwitchRequested back to zero as a task switch is about to be
-	performed. */
-	swi r0, r0, ulTaskSwitchRequested
-
-	/* ulTaskSwitchRequested was not 0 when tested.  Select the next task to
-	execute. */
-	bralid r15, vTaskSwitchContext
-	or r0, r0, r0
-
-task_switch_not_requested:
-
-	/* Restore the context of the next task scheduled to execute. */
-	portRESTORE_CONTEXT
-
-
-	.text
-	.align  4
-VPortYieldASM:
-
-	portSAVE_CONTEXT
-
-	/* Modify the return address so a return is done to the instruction after
-	the call to VPortYieldASM. */
-	addi r14, r14, 8
-	swi r14, r1, portR14_OFFSET
-
-	/* Switch to use the ISR stack. */
-	lwi r1, r0, pulISRStack
-
-	/* Select the next task to execute. */
-	bralid r15, vTaskSwitchContext
-	or r0, r0, r0
-
-	/* Restore the context of the next task scheduled to execute. */
-	portRESTORE_CONTEXT
-
-	.text
-	.align  4
-vPortStartFirstTask:
-
-	portRESTORE_CONTEXT
-
-
-
-#if ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 )
-
-	.text
-	.align 4
-vPortExceptionHandlerEntry:
-
-	/* Take a copy of the stack pointer before vPortExecptionHandler is called,
-	storing its value prior to the function stack frame being created. */
-	swi r1, r0, pulStackPointerOnFunctionEntry
-	bralid r15, vPortExceptionHandler
-	or r0, r0, r0
-
-#endif /* ( MICROBLAZE_EXCEPTIONS_ENABLED == 1 ) && ( configINSTALL_EXCEPTION_HANDLERS == 1 ) */
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portmacro.h b/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portmacro.h
deleted file mode 100755
index a00cc89..0000000
--- a/FreeRTOS/Source/portable/GCC/MicroBlazeV9/portmacro.h
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* BSP includes. */
-#include 
-#include 
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros and functions. */
-void microblaze_disable_interrupts( void );
-void microblaze_enable_interrupts( void );
-#define portDISABLE_INTERRUPTS()	microblaze_disable_interrupts()
-#define portENABLE_INTERRUPTS()		microblaze_enable_interrupts()
-/*-----------------------------------------------------------*/
-
-/* Critical section macros. */
-void vPortEnterCritical( void );
-void vPortExitCritical( void );
-#define portENTER_CRITICAL()		{																\
-										extern volatile UBaseType_t uxCriticalNesting;				\
-										microblaze_disable_interrupts();							\
-										uxCriticalNesting++;										\
-									}
-
-#define portEXIT_CRITICAL()			{																\
-										extern volatile UBaseType_t uxCriticalNesting;				\
-										/* Interrupts are disabled, so we can */					\
-										/* access the variable directly. */							\
-										uxCriticalNesting--;										\
-										if( uxCriticalNesting == 0 )								\
-										{															\
-											/* The nesting has unwound and we 						\
-											can enable interrupts again. */							\
-											portENABLE_INTERRUPTS();								\
-										}															\
-									}
-
-/*-----------------------------------------------------------*/
-
-/* The yield macro maps directly to the vPortYield() function. */
-void vPortYield( void );
-#define portYIELD() vPortYield()
-
-/* portYIELD_FROM_ISR() does not directly call vTaskSwitchContext(), but instead
-sets a flag to say that a yield has been requested.  The interrupt exit code
-then checks this flag, and calls vTaskSwitchContext() before restoring a task
-context, if the flag is not false.  This is done to prevent multiple calls to
-vTaskSwitchContext() being made from a single interrupt, as a single interrupt
-can result in multiple peripherals being serviced. */
-extern volatile uint32_t ulTaskSwitchRequested;
-#define portYIELD_FROM_ISR( x ) if( ( x ) != pdFALSE ) ulTaskSwitchRequested = 1
-
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-
-	/* Generic helper function. */
-	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-	{
-	uint8_t ucReturn;
-
-		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
-		return ucReturn;
-	}
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			4
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()					asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-/* The following structure is used by the FreeRTOS exception handler.  It is
-filled with the MicroBlaze context as it was at the time the exception occurred.
-This is done as an aid to debugging exception occurrences. */
-typedef struct PORT_REGISTER_DUMP
-{
-	/* The following structure members hold the values of the MicroBlaze
-	registers at the time the exception was raised. */
-	uint32_t ulR1_SP;
-	uint32_t ulR2_small_data_area;
-	uint32_t ulR3;
-	uint32_t ulR4;
-	uint32_t ulR5;
-	uint32_t ulR6;
-	uint32_t ulR7;
-	uint32_t ulR8;
-	uint32_t ulR9;
-	uint32_t ulR10;
-	uint32_t ulR11;
-	uint32_t ulR12;
-	uint32_t ulR13_read_write_small_data_area;
-	uint32_t ulR14_return_address_from_interrupt;
-	uint32_t ulR15_return_address_from_subroutine;
-	uint32_t ulR16_return_address_from_trap;
-	uint32_t ulR17_return_address_from_exceptions; /* The exception entry code will copy the BTR into R17 if the exception occurred in the delay slot of a branch instruction. */
-	uint32_t ulR18;
-	uint32_t ulR19;
-	uint32_t ulR20;
-	uint32_t ulR21;
-	uint32_t ulR22;
-	uint32_t ulR23;
-	uint32_t ulR24;
-	uint32_t ulR25;
-	uint32_t ulR26;
-	uint32_t ulR27;
-	uint32_t ulR28;
-	uint32_t ulR29;
-	uint32_t ulR30;
-	uint32_t ulR31;
-	uint32_t ulPC;
-	uint32_t ulESR;
-	uint32_t ulMSR;
-	uint32_t ulEAR;
-	uint32_t ulFSR;
-	uint32_t ulEDR;
-
-	/* A human readable description of the exception cause.  The strings used
-	are the same as the #define constant names found in the
-	microblaze_exceptions_i.h header file */
-	int8_t *pcExceptionCause;
-
-	/* The human readable name of the task that was running at the time the
-	exception occurred.  This is the name that was given to the task when the
-	task was created using the FreeRTOS xTaskCreate() API function. */
-	char *pcCurrentTaskName;
-
-	/* The handle of the task that was running a the time the exception
-	occurred. */
-	void * xCurrentTaskHandle;
-
-} xPortRegisterDump;
-
-
-/*
- * Installs pxHandler as the interrupt handler for the peripheral specified by
- * the ucInterruptID parameter.
- *
- * ucInterruptID:
- *
- * The ID of the peripheral that will have pxHandler assigned as its interrupt
- * handler.  Peripheral IDs are defined in the xparameters.h header file, which
- * is itself part of the BSP project.  For example, in the official demo
- * application for this port, xparameters.h defines the following IDs for the
- * four possible interrupt sources:
- *
- * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
- * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
- * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
- * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
- *
- *
- * pxHandler:
- *
- * A pointer to the interrupt handler function itself.  This must be a void
- * function that takes a (void *) parameter.
- *
- *
- * pvCallBackRef:
- *
- * The parameter passed into the handler function.  In many cases this will not
- * be used and can be NULL.  Some times it is used to pass in a reference to
- * the peripheral instance variable, so it can be accessed from inside the
- * handler function.
- *
- *
- * pdPASS is returned if the function executes successfully.  Any other value
- * being returned indicates that the function did not execute correctly.
- */
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
-
-
-/*
- * Enables the interrupt, within the interrupt controller, for the peripheral
- * specified by the ucInterruptID parameter.
- *
- * ucInterruptID:
- *
- * The ID of the peripheral that will have its interrupt enabled in the
- * interrupt controller.  Peripheral IDs are defined in the xparameters.h header
- * file, which is itself part of the BSP project.  For example, in the official
- * demo application for this port, xparameters.h defines the following IDs for
- * the four possible interrupt sources:
- *
- * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
- * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
- * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
- * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
- *
- */
-void vPortEnableInterrupt( uint8_t ucInterruptID );
-
-/*
- * Disables the interrupt, within the interrupt controller, for the peripheral
- * specified by the ucInterruptID parameter.
- *
- * ucInterruptID:
- *
- * The ID of the peripheral that will have its interrupt disabled in the
- * interrupt controller.  Peripheral IDs are defined in the xparameters.h header
- * file, which is itself part of the BSP project.  For example, in the official
- * demo application for this port, xparameters.h defines the following IDs for
- * the four possible interrupt sources:
- *
- * XPAR_INTC_0_UARTLITE_1_VEC_ID  -  for the UARTlite peripheral.
- * XPAR_INTC_0_TMRCTR_0_VEC_ID    -  for the AXI Timer 0 peripheral.
- * XPAR_INTC_0_EMACLITE_0_VEC_ID  -  for the Ethernet lite peripheral.
- * XPAR_INTC_0_GPIO_1_VEC_ID      -  for the button inputs.
- *
- */
-void vPortDisableInterrupt( uint8_t ucInterruptID );
-
-/*
- * This is an application defined callback function used to install the tick
- * interrupt handler.  It is provided as an application callback because the
- * kernel will run on lots of different MicroBlaze and FPGA configurations - not
- * all of which will have the same timer peripherals defined or available.  This
- * example uses the AXI Timer 0.  If that is available on your hardware platform
- * then this example callback implementation should not require modification.
- * The name of the interrupt handler that should be installed is vPortTickISR(),
- * which the function below declares as an extern.
- */
-void vApplicationSetupTimerInterrupt( void );
-
-/*
- * This is an application defined callback function used to clear whichever
- * interrupt was installed by the the vApplicationSetupTimerInterrupt() callback
- * function - in this case the interrupt generated by the AXI timer.  It is
- * provided as an application callback because the kernel will run on lots of
- * different MicroBlaze and FPGA configurations - not all of which will have the
- * same timer peripherals defined or available.  This example uses the AXI Timer 0.
- * If that is available on your hardware platform then this example callback
- * implementation should not require modification provided the example definition
- * of vApplicationSetupTimerInterrupt() is also not modified.
- */
-void vApplicationClearTimerInterrupt( void );
-
-/*
- * vPortExceptionsInstallHandlers() is only available when the MicroBlaze
- * is configured to include exception functionality, and
- * configINSTALL_EXCEPTION_HANDLERS is set to 1 in FreeRTOSConfig.h.
- *
- * vPortExceptionsInstallHandlers() installs the FreeRTOS exception handler
- * for every possible exception cause.
- *
- * vPortExceptionsInstallHandlers() can be called explicitly from application
- * code.  After that is done, the default FreeRTOS exception handler that will
- * have been installed can be replaced for any specific exception cause by using
- * the standard Xilinx library function microblaze_register_exception_handler().
- *
- * If vPortExceptionsInstallHandlers() is not called explicitly by the
- * application, it will be called automatically by the kernel the first time
- * xPortInstallInterruptHandler() is called.  At that time, any exception
- * handlers that may have already been installed will be replaced.
- *
- * See the description of vApplicationExceptionRegisterDump() for information
- * on the processing performed by the FreeRTOS exception handler.
- */
-void vPortExceptionsInstallHandlers( void );
-
-/*
- * The FreeRTOS exception handler fills an xPortRegisterDump structure (defined
- * in portmacro.h) with the MicroBlaze context, as it was at the time the
- * exception occurred.  The exception handler then calls
- * vApplicationExceptionRegisterDump(), passing in the completed
- * xPortRegisterDump structure as its parameter.
- *
- * The FreeRTOS kernel provides its own implementation of
- * vApplicationExceptionRegisterDump(), but the kernel provided implementation
- * is declared as being 'weak'.  The weak definition allows the application
- * writer to provide their own implementation, should they wish to use the
- * register dump information.  For example, an implementation could be provided
- * that wrote the register dump data to a display, or a UART port.
- */
-void vApplicationExceptionRegisterDump( xPortRegisterDump *xRegisterDump );
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/NiosII/port.c b/FreeRTOS/Source/portable/GCC/NiosII/port.c
deleted file mode 100755
index 5aeebe4..0000000
--- a/FreeRTOS/Source/portable/GCC/NiosII/port.c
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the NIOS2 port.
- *----------------------------------------------------------*/
-
-/* Standard Includes. */
-#include 
-#include 
-
-/* Altera includes. */
-#include "sys/alt_irq.h"
-#include "altera_avalon_timer_regs.h"
-#include "priv/alt_irq_table.h"
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Interrupts are enabled. */
-#define portINITIAL_ESTATUS     ( StackType_t ) 0x01 
-
-/*-----------------------------------------------------------*/
-
-/* 
- * Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * Call back for the alarm function.
- */
-void vPortSysTickHandler( void * context, alt_u32 id );
-
-/*-----------------------------------------------------------*/
-
-static void prvReadGp( uint32_t *ulValue )
-{
-	asm( "stw gp, (%0)" :: "r"(ulValue) );
-}
-/*-----------------------------------------------------------*/
-
-/* 
- * See header file for description. 
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{    
-StackType_t *pxFramePointer = pxTopOfStack - 1;
-StackType_t xGlobalPointer;
-
-    prvReadGp( &xGlobalPointer ); 
-
-    /* End of stack marker. */
-    *pxTopOfStack = 0xdeadbeef;
-    pxTopOfStack--;
-    
-    *pxTopOfStack = ( StackType_t ) pxFramePointer; 
-    pxTopOfStack--;
-    
-    *pxTopOfStack = xGlobalPointer; 
-    
-    /* Space for R23 to R16. */
-    pxTopOfStack -= 9;
-
-    *pxTopOfStack = ( StackType_t ) pxCode; 
-    pxTopOfStack--;
-
-    *pxTopOfStack = portINITIAL_ESTATUS; 
-
-    /* Space for R15 to R5. */    
-    pxTopOfStack -= 12;
-    
-    *pxTopOfStack = ( StackType_t ) pvParameters; 
-
-    /* Space for R3 to R1, muldiv and RA. */
-    pxTopOfStack -= 5;
-    
-    return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-/* 
- * See header file for description. 
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-	
-	/* Start the first task. */
-    asm volatile (  " movia r2, restore_sp_from_pxCurrentTCB        \n"
-                    " jmp r2                                          " );
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the NIOS2 port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-void prvSetupTimerInterrupt( void )
-{
-	/* Try to register the interrupt handler. */
-	if ( -EINVAL == alt_irq_register( SYS_CLK_IRQ, 0x0, vPortSysTickHandler ) )
-	{ 
-		/* Failed to install the Interrupt Handler. */
-		asm( "break" );
-	}
-	else
-	{
-		/* Configure SysTick to interrupt at the requested rate. */
-		IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_STOP_MSK );
-		IOWR_ALTERA_AVALON_TIMER_PERIODL( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) & 0xFFFF );
-		IOWR_ALTERA_AVALON_TIMER_PERIODH( SYS_CLK_BASE, ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) >> 16 );
-		IOWR_ALTERA_AVALON_TIMER_CONTROL( SYS_CLK_BASE, ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | ALTERA_AVALON_TIMER_CONTROL_START_MSK | ALTERA_AVALON_TIMER_CONTROL_ITO_MSK );	
-	} 
-
-	/* Clear any already pending interrupts generated by the Timer. */
-	IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSysTickHandler( void * context, alt_u32 id )
-{
-	/* Increment the kernel tick. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-        vTaskSwitchContext();
-	}
-		
-	/* Clear the interrupt. */
-	IOWR_ALTERA_AVALON_TIMER_STATUS( SYS_CLK_BASE, ~ALTERA_AVALON_TIMER_STATUS_TO_MSK );
-}
-/*-----------------------------------------------------------*/
-
-/** This function is a re-implementation of the Altera provided function.
- * The function is re-implemented to prevent it from enabling an interrupt
- * when it is registered. Interrupts should only be enabled after the FreeRTOS.org
- * kernel has its scheduler started so that contexts are saved and switched 
- * correctly.
- */
-int alt_irq_register( alt_u32 id, void* context, void (*handler)(void*, alt_u32) )
-{
-	int rc = -EINVAL;  
-	alt_irq_context status;
-
-	if (id < ALT_NIRQ)
-	{
-		/* 
-		 * interrupts are disabled while the handler tables are updated to ensure
-		 * that an interrupt doesn't occur while the tables are in an inconsistent
-		 * state.
-		 */
-	
-		status = alt_irq_disable_all ();
-	
-		alt_irq[id].handler = handler;
-		alt_irq[id].context = context;
-	
-		rc = (handler) ? alt_irq_enable (id): alt_irq_disable (id);
-	
-		/* alt_irq_enable_all(status); This line is removed to prevent the interrupt from being immediately enabled. */
-	}
-    
-	return rc; 
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/GCC/NiosII/port_asm.S b/FreeRTOS/Source/portable/GCC/NiosII/port_asm.S
deleted file mode 100755
index f34514b..0000000
--- a/FreeRTOS/Source/portable/GCC/NiosII/port_asm.S
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-.extern		vTaskSwitchContext
-	
-.set noat
-
-# Exported to start the first task.
-.globl restore_sp_from_pxCurrentTCB		
-	
-# Entry point for exceptions.
-.section .exceptions.entry, "xa"		
-
-# Save the entire context of a task.
-save_context:
-	addi	ea, ea, -4			# Point to the next instruction.
-	addi	sp,	sp, -116		# Create space on the stack.
-	stw		ra, 0(sp)
-								# Leave a gap for muldiv 0
-	stw		at, 8(sp)		 
-	stw		r2, 12(sp)
-	stw		r3, 16(sp)
-	stw		r4, 20(sp)
-	stw		r5, 24(sp) 
-	stw		r6, 28(sp) 
-	stw		r7, 32(sp) 
-	stw		r8, 36(sp) 
-	stw		r9, 40(sp) 
-	stw		r10, 44(sp)
-	stw		r11, 48(sp)
-	stw		r12, 52(sp)
-	stw		r13, 56(sp)
-	stw		r14, 60(sp)
-	stw		r15, 64(sp)
-	rdctl	r5, estatus 		# Save the eStatus
-	stw		r5, 68(sp)
-	stw		ea, 72(sp)			# Save the PC
-	stw		r16, 76(sp)			# Save the remaining registers
-	stw		r17, 80(sp)
-	stw		r18, 84(sp)
-	stw		r19, 88(sp)
-	stw		r20, 92(sp)
-	stw		r21, 96(sp)
-	stw		r22, 100(sp)
-	stw		r23, 104(sp)
-	stw		gp, 108(sp)
-	stw		fp, 112(sp)
-
-save_sp_to_pxCurrentTCB:
-	movia	et, pxCurrentTCB	# Load the address of the pxCurrentTCB pointer
-	ldw		et, (et)			# Load the value of the pxCurrentTCB pointer
-	stw		sp, (et)			# Store the stack pointer into the top of the TCB
-	
-	.section .exceptions.irqtest, "xa"	
-hw_irq_test:
-	/*
-     * Test to see if the exception was a software exception or caused 
-     * by an external interrupt, and vector accordingly.
-     */
-    rdctl	r4, ipending		# Load the Pending Interrupts indication
-	rdctl	r5, estatus 		# Load the eStatus (enabled interrupts).
-    andi	r2, r5, 1			# Are interrupts enabled globally.
-    beq		r2, zero, soft_exceptions		# Interrupts are not enabled.
-    beq		r4, zero, soft_exceptions		# There are no interrupts triggered.
-
-	.section .exceptions.irqhandler, "xa"
-hw_irq_handler:
-	call	alt_irq_handler					# Call the alt_irq_handler to deliver to the registered interrupt handler.
-
-    .section .exceptions.irqreturn, "xa"
-restore_sp_from_pxCurrentTCB:
-	movia	et, pxCurrentTCB		# Load the address of the pxCurrentTCB pointer
-	ldw		et, (et)				# Load the value of the pxCurrentTCB pointer
-	ldw		sp, (et)				# Load the stack pointer with the top value of the TCB
-
-restore_context:
-	ldw		ra, 0(sp)		# Restore the registers.
-							# Leave a gap for muldiv 0.
-	ldw		at, 8(sp)
-	ldw		r2, 12(sp)
-	ldw		r3, 16(sp)
-	ldw		r4, 20(sp)
-	ldw		r5, 24(sp) 
-	ldw		r6, 28(sp) 
-	ldw		r7, 32(sp) 
-	ldw		r8, 36(sp) 
-	ldw		r9, 40(sp) 
-	ldw		r10, 44(sp)
-	ldw		r11, 48(sp)
-	ldw		r12, 52(sp)
-	ldw		r13, 56(sp)
-	ldw		r14, 60(sp)
-	ldw		r15, 64(sp)
-	ldw		et, 68(sp)		# Load the eStatus
-	wrctl	estatus, et 	# Write the eStatus
-	ldw		ea, 72(sp)		# Load the Program Counter
-	ldw		r16, 76(sp)
-	ldw		r17, 80(sp)
-	ldw		r18, 84(sp)
-	ldw		r19, 88(sp)
-	ldw		r20, 92(sp)
-	ldw		r21, 96(sp)
-	ldw		r22, 100(sp)
-	ldw		r23, 104(sp)
-	ldw		gp, 108(sp)
-	ldw		fp, 112(sp)
-	addi	sp,	sp, 116		# Release stack space
-
-    eret					# Return to address ea, loading eStatus into Status.
-   
-	.section .exceptions.soft, "xa"
-soft_exceptions:
-	ldw		et, 0(ea)				# Load the instruction where the interrupt occured.
-	movhi	at, %hi(0x003B683A)		# Load the registers with the trap instruction code
-	ori		at, at, %lo(0x003B683A)
-   	cmpne	et, et, at				# Compare the trap instruction code to the last excuted instruction
-  	beq		et, r0, call_scheduler	# its a trap so switchcontext
-  	break							# This is an un-implemented instruction or muldiv problem.
-  	br		restore_context			# its something else
-
-call_scheduler:
-	addi	ea, ea, 4						# A trap was called, increment the program counter so it is not called again.
-	stw		ea, 72(sp)						# Save the new program counter to the context.
-	call	vTaskSwitchContext				# Pick the next context.
-	br		restore_sp_from_pxCurrentTCB	# Switch in the task context and restore. 
diff --git a/FreeRTOS/Source/portable/GCC/NiosII/portmacro.h b/FreeRTOS/Source/portable/GCC/NiosII/portmacro.h
deleted file mode 100755
index 632a92c..0000000
--- a/FreeRTOS/Source/portable/GCC/NiosII/portmacro.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include "sys/alt_irq.h"
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH				( -1 )
-#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT				4
-#define portNOP()                   	asm volatile ( "NOP" )
-#define portCRITICAL_NESTING_IN_TCB		1
-/*-----------------------------------------------------------*/
-
-extern void vTaskSwitchContext( void );
-#define portYIELD()									asm volatile ( "trap" );
-#define portEND_SWITCHING_ISR( xSwitchRequired ) 	if( xSwitchRequired ) 	vTaskSwitchContext()
-
-
-/* Include the port_asm.S file where the Context saving/restoring is defined. */
-__asm__( "\n\t.globl	save_context" );
-
-/*-----------------------------------------------------------*/
-
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()	alt_irq_disable_all()
-#define portENABLE_INTERRUPTS()		alt_irq_enable_all( 0x01 );
-#define portENTER_CRITICAL()        vTaskEnterCritical()
-#define portEXIT_CRITICAL()         vTaskExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/FPU_Macros.h b/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/FPU_Macros.h
deleted file mode 100755
index 4b1ca84..0000000
--- a/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/FPU_Macros.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* When switching out a task, if the task tag contains a buffer address then
-save the flop context into the buffer. */
-#define traceTASK_SWITCHED_OUT()											\
-	if( pxCurrentTCB->pxTaskTag != NULL )									\
-	{																		\
-		extern void vPortSaveFPURegisters( void * );						\
-		vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );	\
-	}
-
-/* When switching in a task, if the task tag contains a buffer address then
-load the flop context from the buffer. */
-#define traceTASK_SWITCHED_IN()												\
-	if( pxCurrentTCB->pxTaskTag != NULL )									\
-	{																		\
-		extern void vPortRestoreFPURegisters( void * );						\
-		vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );	\
-	}
-
diff --git a/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/port.c b/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/port.c
deleted file mode 100755
index e3fc58b..0000000
--- a/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/port.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PPC405 port.
- *----------------------------------------------------------*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "xtime_l.h"
-#include "xintc.h"
-#include "xintc_i.h"
-
-/*-----------------------------------------------------------*/
-
-/* Definitions to set the initial MSR of each task. */
-#define portCRITICAL_INTERRUPT_ENABLE	( 1UL << 17UL )
-#define portEXTERNAL_INTERRUPT_ENABLE	( 1UL << 15UL )
-#define portMACHINE_CHECK_ENABLE		( 1UL << 12UL )
-
-#if configUSE_FPU == 1
-	#define portAPU_PRESENT				( 1UL << 25UL )
-	#define portFCM_FPU_PRESENT			( 1UL << 13UL )
-#else
-	#define portAPU_PRESENT				( 0UL )
-	#define portFCM_FPU_PRESENT			( 0UL )
-#endif
-
-#define portINITIAL_MSR		( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
-
-
-extern const unsigned _SDA_BASE_;
-extern const unsigned _SDA2_BASE_;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the system timer to generate the tick interrupt.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * The handler for the tick interrupt - defined in portasm.s.
- */
-extern void vPortTickISR( void );
-
-/*
- * The handler for the yield function - defined in portasm.s.
- */
-extern void vPortYield( void );
-
-/*
- * Function to start the scheduler running by starting the highest
- * priority task that has thus far been created.
- */
-extern void vPortStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/* Structure used to hold the state of the interrupt controller. */
-static XIntc xInterruptController;
-
-/*-----------------------------------------------------------*/
-
-/* 
- * Initialise the stack of a task to look exactly as if the task had been
- * interrupted.
- * 
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Place a known value at the bottom of the stack for debugging. */
-	*pxTopOfStack = 0xDEADBEEF;
-	pxTopOfStack--;
-
-	/* EABI stack frame. */
-	pxTopOfStack -= 20;	/* Previous backchain and LR, R31 to R4 inclusive. */
-
-	/* Parameters in R13. */
-	*pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
-	pxTopOfStack -= 10;
-
-	/* Parameters in R3. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;
-	pxTopOfStack--;
-
-	/* Parameters in R2. */
-	*pxTopOfStack = ( StackType_t ) &_SDA2_BASE_;	/* address of the second small data area */
-	pxTopOfStack--;
-
-	/* R1 is the stack pointer so is omitted. */
-
-	*pxTopOfStack = 0x10000001UL;;	/* R0. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x00000000UL;	/* USPRG0. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x00000000UL;	/* CR. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x00000000UL;	/* XER. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x00000000UL;	/* CTR. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) vPortEndScheduler;	/* LR. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_MSR;/* SRR1. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x00000000UL;/* Backchain. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	prvSetupTimerInterrupt();
-	XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
-	vPortStartFirstTask();
-
-	/* Should not get here as the tasks are now running! */
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented. */
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Hardware initialisation to generate the RTOS tick.   
- */
-static void prvSetupTimerInterrupt( void )
-{
-const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
-
-	XTime_PITClearInterrupt();
-	XTime_FITClearInterrupt();
-	XTime_WDTClearInterrupt();
-	XTime_WDTDisableInterrupt();
-	XTime_FITDisableInterrupt();
-
-	XExc_RegisterHandler( XEXC_ID_PIT_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
-
-	XTime_PITEnableAutoReload();
-	XTime_PITSetInterval( ulInterval );
-	XTime_PITEnableInterrupt();
-}
-/*-----------------------------------------------------------*/
-
-void vPortISRHandler( void *pvNullDoNotUse )
-{
-uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
-BaseType_t xInterruptNumber;
-XIntc_Config *pxInterruptController;
-XIntc_VectorTableEntry *pxTable;
-
-	/* Just to remove compiler warning. */
-	( void ) pvNullDoNotUse;	
-
-	/* Get the configuration by using the device ID - in this case it is
-	assumed that only one interrupt controller is being used. */
-	pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
-  
-	/* Which interrupts are pending? */
-	ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
-  
-	for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
-	{
-		if( ulInterruptStatus & 0x01UL )
-		{
-			/* Clear the pending interrupt. */
-			XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
-
-			/* Call the registered handler. */
-			pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
-			pxTable->Handler( pxTable->CallBackRef );
-		}
-        
-		/* Check the next interrupt. */
-		ulInterruptMask <<= 0x01UL;
-		ulInterruptStatus >>= 0x01UL;
-
-		/* Have we serviced all interrupts? */
-		if( ulInterruptStatus == 0UL )
-		{
-			break;
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetupInterruptController( void )
-{
-extern void vPortISRWrapper( void );
-
-	/* Perform all library calls necessary to initialise the exception table
-	and interrupt controller.  This assumes only one interrupt controller is in
-	use. */
-	XExc_mDisableExceptions( XEXC_NON_CRITICAL );
-	XExc_Init();
-
-	/* The library functions save the context - we then jump to a wrapper to
-	save the stack into the TCB.  The wrapper then calls the handler defined
-	above. */
-	XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
-	XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
-	XIntc_Start( &xInterruptController, XIN_REAL_MODE );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
-{
-BaseType_t xReturn = pdFAIL;
-
-	/* This function is defined here so the scope of xInterruptController can
-	remain within this file. */
-
-	if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
-	{
-		XIntc_Enable( &xInterruptController, ucInterruptID );
-		xReturn = pdPASS;
-	}
-
-	return xReturn;		
-}
diff --git a/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portasm.S b/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portasm.S
deleted file mode 100755
index ebd74e3..0000000
--- a/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portasm.S
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include "FreeRTOSConfig.h"
-
-	.extern pxCurrentTCB
-	.extern vTaskSwitchContext
-	.extern xTaskIncrementTick
-	.extern vPortISRHandler
-
-	.global vPortStartFirstTask
-	.global vPortYield
-	.global vPortTickISR
-	.global vPortISRWrapper
-	.global vPortSaveFPURegisters
-	.global vPortRestoreFPURegisters
-
-.set	BChainField, 0
-.set	NextLRField, BChainField + 4
-.set	MSRField,    NextLRField + 4
-.set	PCField,     MSRField    + 4
-.set	LRField,     PCField     + 4
-.set	CTRField,    LRField     + 4
-.set	XERField,    CTRField    + 4
-.set	CRField,     XERField    + 4
-.set	USPRG0Field, CRField     + 4
-.set	r0Field,     USPRG0Field + 4
-.set	r2Field,     r0Field     + 4
-.set	r3r31Field,  r2Field     + 4
-.set	IFrameSize,  r3r31Field  + ( ( 31 - 3 ) + 1 ) * 4
-
-
-.macro portSAVE_STACK_POINTER_AND_LR
-
-	/* Get the address of the TCB. */
-	xor		R0, R0, R0
-	addis	R2, R0, pxCurrentTCB@ha
-	lwz		R2,	pxCurrentTCB@l( R2 )
-
-	/* Store the stack pointer into the TCB */
-	stw		SP,	0( R2 )
-
-	/* Save the link register */
-	stwu	R1, -24( R1 )
-	mflr	R0
-	stw		R31, 20( R1 )
-	stw		R0, 28( R1 )
-	mr		R31, r1
-
-.endm
-
-.macro portRESTORE_STACK_POINTER_AND_LR
-
-	/* Restore the link register */
-	lwz		R11, 0( R1 )
-	lwz		R0, 4( R11 )
-	mtlr	R0
-	lwz		R31, -4( R11 )
-	mr		R1, R11
-
-	/* Get the address of the TCB. */
-	xor		R0, R0, R0
-	addis   SP, R0, pxCurrentTCB@ha
-	lwz		SP,	pxCurrentTCB@l( R1 )
-
-	/* Get the task stack pointer from the TCB. */
-	lwz		SP, 0( SP )
-
-.endm
-
-
-vPortStartFirstTask:
-
-	/* Get the address of the TCB. */
-	xor		R0, R0, R0
-    addis   SP, R0, pxCurrentTCB@ha
-    lwz		SP,	pxCurrentTCB@l( SP )
-
-	/* Get the task stack pointer from the TCB. */
-	lwz		SP, 0( SP )
-	
-	/* Restore MSR register to SRR1. */
-	lwz		R0, MSRField(R1)
-	mtsrr1	R0
-	
-	/* Restore current PC location to SRR0. */
-	lwz		R0, PCField(R1)
-	mtsrr0	R0
-
-	/* Save  USPRG0 register */
-	lwz		R0, USPRG0Field(R1)
-	mtspr	0x100,R0
-	
-	/* Restore Condition register */
-	lwz		R0, CRField(R1)
-	mtcr	R0
-	
-	/* Restore Fixed Point Exception register */
-	lwz		R0, XERField(R1)
-	mtxer	R0
-	
-	/* Restore Counter register */
-	lwz		R0, CTRField(R1)
-	mtctr	R0
-	
-	/* Restore Link register */
-	lwz		R0, LRField(R1)
-	mtlr	R0
-	
-	/* Restore remaining GPR registers. */
-	lmw	R3,r3r31Field(R1)
-	
-	/* Restore r0 and r2. */
-	lwz		R0, r0Field(R1)
-	lwz		R2, r2Field(R1)
-	
-	/* Remove frame from stack */
-	addi	R1,R1,IFrameSize
-
-	/* Return into the first task */
-	rfi
-
-
-
-vPortYield:
-
-	portSAVE_STACK_POINTER_AND_LR
-	bl vTaskSwitchContext
-	portRESTORE_STACK_POINTER_AND_LR
-	blr
-
-vPortTickISR:
-
-	portSAVE_STACK_POINTER_AND_LR
-	bl xTaskIncrementTick
-	
-	#if configUSE_PREEMPTION == 1
-		bl vTaskSwitchContext
-	#endif
-
-	/* Clear the interrupt */
-	lis		R0, 2048
-	mttsr	R0
-
-	portRESTORE_STACK_POINTER_AND_LR
-	blr
-
-vPortISRWrapper:
-
-	portSAVE_STACK_POINTER_AND_LR
-	bl vPortISRHandler
-	portRESTORE_STACK_POINTER_AND_LR
-	blr
-
-#if configUSE_FPU == 1
-
-vPortSaveFPURegisters:
-
-	/* Enable APU and mark FPU as present. */
-	mfmsr	r0
-	xor		r30, r30, r30
-	oris	r30, r30, 512
-	ori		r30, r30, 8192
-	or		r0, r0, r30
-	mtmsr	r0
-
-#ifdef USE_DP_FPU
-
-	/* Buffer address is in r3.  Save each flop register into an offset from
-	this buffer address. */
-	stfd	f0, 0(r3)
-	stfd	f1, 8(r3)
-	stfd	f2, 16(r3)
-	stfd	f3, 24(r3)
-	stfd	f4, 32(r3)
-	stfd	f5, 40(r3)
-	stfd	f6, 48(r3)
-	stfd	f7, 56(r3)
-	stfd	f8, 64(r3)
-	stfd	f9, 72(r3)
-	stfd	f10, 80(r3)
-	stfd	f11, 88(r3)
-	stfd	f12, 96(r3)
-	stfd	f13, 104(r3)
-	stfd	f14, 112(r3)
-	stfd	f15, 120(r3)
-	stfd	f16, 128(r3)
-	stfd	f17, 136(r3)
-	stfd	f18, 144(r3)
-	stfd	f19, 152(r3)
-	stfd	f20, 160(r3)
-	stfd	f21, 168(r3)
-	stfd	f22, 176(r3)
-	stfd	f23, 184(r3)
-	stfd	f24, 192(r3)
-	stfd	f25, 200(r3)
-	stfd	f26, 208(r3)
-	stfd	f27, 216(r3)
-	stfd	f28, 224(r3)
-	stfd	f29, 232(r3)
-	stfd	f30, 240(r3)
-	stfd	f31, 248(r3)	
-	
-	/* Also save the FPSCR. */
-	mffs	f31
-	stfs	f31, 256(r3)
-
-#else
-
-	/* Buffer address is in r3.  Save each flop register into an offset from
-	this buffer address. */
-	stfs	f0, 0(r3)
-	stfs	f1, 4(r3)
-	stfs	f2, 8(r3)
-	stfs	f3, 12(r3)
-	stfs	f4, 16(r3)
-	stfs	f5, 20(r3)
-	stfs	f6, 24(r3)
-	stfs	f7, 28(r3)
-	stfs	f8, 32(r3)
-	stfs	f9, 36(r3)
-	stfs	f10, 40(r3)
-	stfs	f11, 44(r3)
-	stfs	f12, 48(r3)
-	stfs	f13, 52(r3)
-	stfs	f14, 56(r3)
-	stfs	f15, 60(r3)
-	stfs	f16, 64(r3)
-	stfs	f17, 68(r3)
-	stfs	f18, 72(r3)
-	stfs	f19, 76(r3)
-	stfs	f20, 80(r3)
-	stfs	f21, 84(r3)
-	stfs	f22, 88(r3)
-	stfs	f23, 92(r3)
-	stfs	f24, 96(r3)
-	stfs	f25, 100(r3)
-	stfs	f26, 104(r3)
-	stfs	f27, 108(r3)
-	stfs	f28, 112(r3)
-	stfs	f29, 116(r3)
-	stfs	f30, 120(r3)
-	stfs	f31, 124(r3)
-	
-	/* Also save the FPSCR. */
-	mffs	f31
-	stfs	f31, 128(r3)
-	
-#endif
-
-	blr
-
-#endif /* configUSE_FPU. */
-
-
-#if configUSE_FPU == 1
-
-vPortRestoreFPURegisters:
-
-	/* Enable APU and mark FPU as present. */
-	mfmsr	r0
-	xor		r30, r30, r30
-	oris	r30, r30, 512
-	ori		r30, r30, 8192
-	or		r0, r0, r30
-	mtmsr	r0
-
-#ifdef USE_DP_FPU
-
-	/* Buffer address is in r3.  Restore each flop register from an offset
-	into this buffer. 
-	
-	First the FPSCR. */
-	lfs		f31, 256(r3)
-	mtfsf	f31, 7
-
-	lfd		f0, 0(r3)
-	lfd	    f1, 8(r3)
-	lfd		f2, 16(r3)
-	lfd		f3, 24(r3)
-	lfd		f4, 32(r3)
-	lfd		f5, 40(r3)
-	lfd		f6, 48(r3)
-	lfd		f7, 56(r3)
-	lfd		f8, 64(r3)
-	lfd		f9, 72(r3)
-	lfd		f10, 80(r3)
-	lfd		f11, 88(r3)
-	lfd		f12, 96(r3)
-	lfd		f13, 104(r3)
-	lfd		f14, 112(r3)
-	lfd		f15, 120(r3)
-	lfd		f16, 128(r3)
-	lfd		f17, 136(r3)
-	lfd		f18, 144(r3)
-	lfd		f19, 152(r3)
-	lfd		f20, 160(r3)
-	lfd		f21, 168(r3)
-	lfd		f22, 176(r3)
-	lfd		f23, 184(r3)
-	lfd		f24, 192(r3)
-	lfd		f25, 200(r3)
-	lfd		f26, 208(r3)
-	lfd		f27, 216(r3)
-	lfd		f28, 224(r3)
-	lfd		f29, 232(r3)
-	lfd		f30, 240(r3)
-	lfd		f31, 248(r3)
-
-#else
-
-	/* Buffer address is in r3.  Restore each flop register from an offset
-	into this buffer. 
-	
-	First the FPSCR. */
-	lfs		f31, 128(r3)
-	mtfsf	f31, 7
-
-	lfs		f0, 0(r3)
-	lfs		f1, 4(r3)
-	lfs		f2, 8(r3)
-	lfs		f3, 12(r3)
-	lfs		f4, 16(r3)
-	lfs		f5, 20(r3)
-	lfs		f6, 24(r3)
-	lfs		f7, 28(r3)
-	lfs		f8, 32(r3)
-	lfs		f9, 36(r3)
-	lfs		f10, 40(r3)
-	lfs		f11, 44(r3)
-	lfs		f12, 48(r3)
-	lfs		f13, 52(r3)
-	lfs		f14, 56(r3)
-	lfs		f15, 60(r3)
-	lfs		f16, 64(r3)
-	lfs		f17, 68(r3)
-	lfs		f18, 72(r3)
-	lfs		f19, 76(r3)
-	lfs		f20, 80(r3)
-	lfs		f21, 84(r3)
-	lfs		f22, 88(r3)
-	lfs		f23, 92(r3)
-	lfs		f24, 96(r3)
-	lfs		f25, 100(r3)
-	lfs		f26, 104(r3)
-	lfs		f27, 108(r3)
-	lfs		f28, 112(r3)
-	lfs		f29, 116(r3)
-	lfs		f30, 120(r3)
-	lfs		f31, 124(r3)
-
-#endif
-
-	blr
-
-#endif /* configUSE_FPU. */
-
-
diff --git a/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portmacro.h b/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portmacro.h
deleted file mode 100755
index 171140e..0000000
--- a/FreeRTOS/Source/portable/GCC/PPC405_Xilinx/portmacro.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#include "xexception_l.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* This port uses the critical nesting count from the TCB rather than
-maintaining a separate value and then saving this value in the task stack. */
-#define portCRITICAL_NESTING_IN_TCB		1
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS()		XExc_mDisableExceptions( XEXC_NON_CRITICAL );
-#define portENABLE_INTERRUPTS()			XExc_mEnableExceptions( XEXC_NON_CRITICAL );
-
-/*-----------------------------------------------------------*/
-
-/* Critical section macros. */
-void vTaskEnterCritical( void );
-void vTaskExitCritical( void );
-#define portENTER_CRITICAL()			vTaskEnterCritical()
-#define portEXIT_CRITICAL()				vTaskExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-void vPortYield( void );
-#define portYIELD() asm volatile ( "SC \n\t NOP" )
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			8
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()					asm volatile ( "NOP" )
-
-/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
-#define portNO_FLOP_REGISTERS_TO_SAVE  ( 32 + 1 )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-/* Port specific interrupt handling functions. */
-void vPortSetupInterruptController( void );
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h b/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h
deleted file mode 100755
index 4b1ca84..0000000
--- a/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/FPU_Macros.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* When switching out a task, if the task tag contains a buffer address then
-save the flop context into the buffer. */
-#define traceTASK_SWITCHED_OUT()											\
-	if( pxCurrentTCB->pxTaskTag != NULL )									\
-	{																		\
-		extern void vPortSaveFPURegisters( void * );						\
-		vPortSaveFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );	\
-	}
-
-/* When switching in a task, if the task tag contains a buffer address then
-load the flop context from the buffer. */
-#define traceTASK_SWITCHED_IN()												\
-	if( pxCurrentTCB->pxTaskTag != NULL )									\
-	{																		\
-		extern void vPortRestoreFPURegisters( void * );						\
-		vPortRestoreFPURegisters( ( void * ) ( pxCurrentTCB->pxTaskTag ) );	\
-	}
-
diff --git a/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/port.c b/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/port.c
deleted file mode 100755
index 105bff1..0000000
--- a/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/port.c
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PPC440 port.
- *----------------------------------------------------------*/
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "xtime_l.h"
-#include "xintc.h"
-#include "xintc_i.h"
-
-/*-----------------------------------------------------------*/
-
-/* Definitions to set the initial MSR of each task. */
-#define portCRITICAL_INTERRUPT_ENABLE	( 1UL << 17UL )
-#define portEXTERNAL_INTERRUPT_ENABLE	( 1UL << 15UL )
-#define portMACHINE_CHECK_ENABLE		( 1UL << 12UL )
-
-#if configUSE_FPU == 1
-	#define portAPU_PRESENT				( 1UL << 25UL )
-	#define portFCM_FPU_PRESENT			( 1UL << 13UL )
-#else
-	#define portAPU_PRESENT				( 0UL )
-	#define portFCM_FPU_PRESENT			( 0UL )
-#endif
-
-#define portINITIAL_MSR		( portCRITICAL_INTERRUPT_ENABLE | portEXTERNAL_INTERRUPT_ENABLE | portMACHINE_CHECK_ENABLE | portAPU_PRESENT | portFCM_FPU_PRESENT )
-
-
-extern const unsigned _SDA_BASE_;
-extern const unsigned _SDA2_BASE_;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the system timer to generate the tick interrupt.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * The handler for the tick interrupt - defined in portasm.s.
- */
-extern void vPortTickISR( void );
-
-/*
- * The handler for the yield function - defined in portasm.s.
- */
-extern void vPortYield( void );
-
-/*
- * Function to start the scheduler running by starting the highest
- * priority task that has thus far been created.
- */
-extern void vPortStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/* Structure used to hold the state of the interrupt controller. */
-static XIntc xInterruptController;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if the task had been
- * interrupted.
- *
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Place a known value at the bottom of the stack for debugging. */
-	*pxTopOfStack = 0xDEADBEEF;
-	pxTopOfStack--;
-
-	/* EABI stack frame. */
-	pxTopOfStack -= 20;	/* Previous backchain and LR, R31 to R4 inclusive. */
-
-	/* Parameters in R13. */
-	*pxTopOfStack = ( StackType_t ) &_SDA_BASE_; /* address of the first small data area */
-	pxTopOfStack -= 10;
-
-	/* Parameters in R3. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;
-	pxTopOfStack--;
-
-	/* Parameters in R2. */
-	*pxTopOfStack = ( StackType_t ) &_SDA2_BASE_;	/* address of the second small data area */
-	pxTopOfStack--;
-
-	/* R1 is the stack pointer so is omitted. */
-
-	*pxTopOfStack = 0x10000001UL;;	/* R0. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x00000000UL;	/* USPRG0. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x00000000UL;	/* CR. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x00000000UL;	/* XER. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x00000000UL;	/* CTR. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) vPortEndScheduler;	/* LR. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode; /* SRR0. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_MSR;/* SRR1. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) vPortEndScheduler;/* Next LR. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x00000000UL;/* Backchain. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	prvSetupTimerInterrupt();
-	XExc_RegisterHandler( XEXC_ID_SYSTEM_CALL, ( XExceptionHandler ) vPortYield, ( void * ) 0 );
-	vPortStartFirstTask();
-
-	/* Should not get here as the tasks are now running! */
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented. */
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Hardware initialisation to generate the RTOS tick.
- */
-static void prvSetupTimerInterrupt( void )
-{
-const uint32_t ulInterval = ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL );
-
-	XTime_DECClearInterrupt();
-	XTime_FITClearInterrupt();
-	XTime_WDTClearInterrupt();
-	XTime_WDTDisableInterrupt();
-	XTime_FITDisableInterrupt();
-
-	XExc_RegisterHandler( XEXC_ID_DEC_INT, ( XExceptionHandler ) vPortTickISR, ( void * ) 0 );
-
-	XTime_DECEnableAutoReload();
-	XTime_DECSetInterval( ulInterval );
-	XTime_DECEnableInterrupt();
-}
-/*-----------------------------------------------------------*/
-
-void vPortISRHandler( void *pvNullDoNotUse )
-{
-uint32_t ulInterruptStatus, ulInterruptMask = 1UL;
-BaseType_t xInterruptNumber;
-XIntc_Config *pxInterruptController;
-XIntc_VectorTableEntry *pxTable;
-
-	/* Just to remove compiler warning. */
-	( void ) pvNullDoNotUse;
-
-	/* Get the configuration by using the device ID - in this case it is
-	assumed that only one interrupt controller is being used. */
-	pxInterruptController = &XIntc_ConfigTable[ XPAR_XPS_INTC_0_DEVICE_ID ];
-
-	/* Which interrupts are pending? */
-	ulInterruptStatus = XIntc_mGetIntrStatus( pxInterruptController->BaseAddress );
-
-	for( xInterruptNumber = 0; xInterruptNumber < XPAR_INTC_MAX_NUM_INTR_INPUTS; xInterruptNumber++ )
-	{
-		if( ulInterruptStatus & 0x01UL )
-		{
-			/* Clear the pending interrupt. */
-			XIntc_mAckIntr( pxInterruptController->BaseAddress, ulInterruptMask );
-
-			/* Call the registered handler. */
-			pxTable = &( pxInterruptController->HandlerTable[ xInterruptNumber ] );
-			pxTable->Handler( pxTable->CallBackRef );
-		}
-
-		/* Check the next interrupt. */
-		ulInterruptMask <<= 0x01UL;
-		ulInterruptStatus >>= 0x01UL;
-
-		/* Have we serviced all interrupts? */
-		if( ulInterruptStatus == 0UL )
-		{
-			break;
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetupInterruptController( void )
-{
-extern void vPortISRWrapper( void );
-
-	/* Perform all library calls necessary to initialise the exception table
-	and interrupt controller.  This assumes only one interrupt controller is in
-	use. */
-	XExc_mDisableExceptions( XEXC_NON_CRITICAL );
-	XExc_Init();
-
-	/* The library functions save the context - we then jump to a wrapper to
-	save the stack into the TCB.  The wrapper then calls the handler defined
-	above. */
-	XExc_RegisterHandler( XEXC_ID_NON_CRITICAL_INT, ( XExceptionHandler ) vPortISRWrapper, NULL );
-	XIntc_Initialize( &xInterruptController, XPAR_XPS_INTC_0_DEVICE_ID );
-	XIntc_Start( &xInterruptController, XIN_REAL_MODE );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef )
-{
-BaseType_t xReturn = pdFAIL;
-
-	/* This function is defined here so the scope of xInterruptController can
-	remain within this file. */
-
-	if( XST_SUCCESS == XIntc_Connect( &xInterruptController, ucInterruptID, pxHandler, pvCallBackRef ) )
-	{
-		XIntc_Enable( &xInterruptController, ucInterruptID );
-		xReturn = pdPASS;
-	}
-
-	return xReturn;
-}
diff --git a/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portasm.S b/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portasm.S
deleted file mode 100755
index ebd74e3..0000000
--- a/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portasm.S
+++ /dev/null
@@ -1,382 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include "FreeRTOSConfig.h"
-
-	.extern pxCurrentTCB
-	.extern vTaskSwitchContext
-	.extern xTaskIncrementTick
-	.extern vPortISRHandler
-
-	.global vPortStartFirstTask
-	.global vPortYield
-	.global vPortTickISR
-	.global vPortISRWrapper
-	.global vPortSaveFPURegisters
-	.global vPortRestoreFPURegisters
-
-.set	BChainField, 0
-.set	NextLRField, BChainField + 4
-.set	MSRField,    NextLRField + 4
-.set	PCField,     MSRField    + 4
-.set	LRField,     PCField     + 4
-.set	CTRField,    LRField     + 4
-.set	XERField,    CTRField    + 4
-.set	CRField,     XERField    + 4
-.set	USPRG0Field, CRField     + 4
-.set	r0Field,     USPRG0Field + 4
-.set	r2Field,     r0Field     + 4
-.set	r3r31Field,  r2Field     + 4
-.set	IFrameSize,  r3r31Field  + ( ( 31 - 3 ) + 1 ) * 4
-
-
-.macro portSAVE_STACK_POINTER_AND_LR
-
-	/* Get the address of the TCB. */
-	xor		R0, R0, R0
-	addis	R2, R0, pxCurrentTCB@ha
-	lwz		R2,	pxCurrentTCB@l( R2 )
-
-	/* Store the stack pointer into the TCB */
-	stw		SP,	0( R2 )
-
-	/* Save the link register */
-	stwu	R1, -24( R1 )
-	mflr	R0
-	stw		R31, 20( R1 )
-	stw		R0, 28( R1 )
-	mr		R31, r1
-
-.endm
-
-.macro portRESTORE_STACK_POINTER_AND_LR
-
-	/* Restore the link register */
-	lwz		R11, 0( R1 )
-	lwz		R0, 4( R11 )
-	mtlr	R0
-	lwz		R31, -4( R11 )
-	mr		R1, R11
-
-	/* Get the address of the TCB. */
-	xor		R0, R0, R0
-	addis   SP, R0, pxCurrentTCB@ha
-	lwz		SP,	pxCurrentTCB@l( R1 )
-
-	/* Get the task stack pointer from the TCB. */
-	lwz		SP, 0( SP )
-
-.endm
-
-
-vPortStartFirstTask:
-
-	/* Get the address of the TCB. */
-	xor		R0, R0, R0
-    addis   SP, R0, pxCurrentTCB@ha
-    lwz		SP,	pxCurrentTCB@l( SP )
-
-	/* Get the task stack pointer from the TCB. */
-	lwz		SP, 0( SP )
-	
-	/* Restore MSR register to SRR1. */
-	lwz		R0, MSRField(R1)
-	mtsrr1	R0
-	
-	/* Restore current PC location to SRR0. */
-	lwz		R0, PCField(R1)
-	mtsrr0	R0
-
-	/* Save  USPRG0 register */
-	lwz		R0, USPRG0Field(R1)
-	mtspr	0x100,R0
-	
-	/* Restore Condition register */
-	lwz		R0, CRField(R1)
-	mtcr	R0
-	
-	/* Restore Fixed Point Exception register */
-	lwz		R0, XERField(R1)
-	mtxer	R0
-	
-	/* Restore Counter register */
-	lwz		R0, CTRField(R1)
-	mtctr	R0
-	
-	/* Restore Link register */
-	lwz		R0, LRField(R1)
-	mtlr	R0
-	
-	/* Restore remaining GPR registers. */
-	lmw	R3,r3r31Field(R1)
-	
-	/* Restore r0 and r2. */
-	lwz		R0, r0Field(R1)
-	lwz		R2, r2Field(R1)
-	
-	/* Remove frame from stack */
-	addi	R1,R1,IFrameSize
-
-	/* Return into the first task */
-	rfi
-
-
-
-vPortYield:
-
-	portSAVE_STACK_POINTER_AND_LR
-	bl vTaskSwitchContext
-	portRESTORE_STACK_POINTER_AND_LR
-	blr
-
-vPortTickISR:
-
-	portSAVE_STACK_POINTER_AND_LR
-	bl xTaskIncrementTick
-	
-	#if configUSE_PREEMPTION == 1
-		bl vTaskSwitchContext
-	#endif
-
-	/* Clear the interrupt */
-	lis		R0, 2048
-	mttsr	R0
-
-	portRESTORE_STACK_POINTER_AND_LR
-	blr
-
-vPortISRWrapper:
-
-	portSAVE_STACK_POINTER_AND_LR
-	bl vPortISRHandler
-	portRESTORE_STACK_POINTER_AND_LR
-	blr
-
-#if configUSE_FPU == 1
-
-vPortSaveFPURegisters:
-
-	/* Enable APU and mark FPU as present. */
-	mfmsr	r0
-	xor		r30, r30, r30
-	oris	r30, r30, 512
-	ori		r30, r30, 8192
-	or		r0, r0, r30
-	mtmsr	r0
-
-#ifdef USE_DP_FPU
-
-	/* Buffer address is in r3.  Save each flop register into an offset from
-	this buffer address. */
-	stfd	f0, 0(r3)
-	stfd	f1, 8(r3)
-	stfd	f2, 16(r3)
-	stfd	f3, 24(r3)
-	stfd	f4, 32(r3)
-	stfd	f5, 40(r3)
-	stfd	f6, 48(r3)
-	stfd	f7, 56(r3)
-	stfd	f8, 64(r3)
-	stfd	f9, 72(r3)
-	stfd	f10, 80(r3)
-	stfd	f11, 88(r3)
-	stfd	f12, 96(r3)
-	stfd	f13, 104(r3)
-	stfd	f14, 112(r3)
-	stfd	f15, 120(r3)
-	stfd	f16, 128(r3)
-	stfd	f17, 136(r3)
-	stfd	f18, 144(r3)
-	stfd	f19, 152(r3)
-	stfd	f20, 160(r3)
-	stfd	f21, 168(r3)
-	stfd	f22, 176(r3)
-	stfd	f23, 184(r3)
-	stfd	f24, 192(r3)
-	stfd	f25, 200(r3)
-	stfd	f26, 208(r3)
-	stfd	f27, 216(r3)
-	stfd	f28, 224(r3)
-	stfd	f29, 232(r3)
-	stfd	f30, 240(r3)
-	stfd	f31, 248(r3)	
-	
-	/* Also save the FPSCR. */
-	mffs	f31
-	stfs	f31, 256(r3)
-
-#else
-
-	/* Buffer address is in r3.  Save each flop register into an offset from
-	this buffer address. */
-	stfs	f0, 0(r3)
-	stfs	f1, 4(r3)
-	stfs	f2, 8(r3)
-	stfs	f3, 12(r3)
-	stfs	f4, 16(r3)
-	stfs	f5, 20(r3)
-	stfs	f6, 24(r3)
-	stfs	f7, 28(r3)
-	stfs	f8, 32(r3)
-	stfs	f9, 36(r3)
-	stfs	f10, 40(r3)
-	stfs	f11, 44(r3)
-	stfs	f12, 48(r3)
-	stfs	f13, 52(r3)
-	stfs	f14, 56(r3)
-	stfs	f15, 60(r3)
-	stfs	f16, 64(r3)
-	stfs	f17, 68(r3)
-	stfs	f18, 72(r3)
-	stfs	f19, 76(r3)
-	stfs	f20, 80(r3)
-	stfs	f21, 84(r3)
-	stfs	f22, 88(r3)
-	stfs	f23, 92(r3)
-	stfs	f24, 96(r3)
-	stfs	f25, 100(r3)
-	stfs	f26, 104(r3)
-	stfs	f27, 108(r3)
-	stfs	f28, 112(r3)
-	stfs	f29, 116(r3)
-	stfs	f30, 120(r3)
-	stfs	f31, 124(r3)
-	
-	/* Also save the FPSCR. */
-	mffs	f31
-	stfs	f31, 128(r3)
-	
-#endif
-
-	blr
-
-#endif /* configUSE_FPU. */
-
-
-#if configUSE_FPU == 1
-
-vPortRestoreFPURegisters:
-
-	/* Enable APU and mark FPU as present. */
-	mfmsr	r0
-	xor		r30, r30, r30
-	oris	r30, r30, 512
-	ori		r30, r30, 8192
-	or		r0, r0, r30
-	mtmsr	r0
-
-#ifdef USE_DP_FPU
-
-	/* Buffer address is in r3.  Restore each flop register from an offset
-	into this buffer. 
-	
-	First the FPSCR. */
-	lfs		f31, 256(r3)
-	mtfsf	f31, 7
-
-	lfd		f0, 0(r3)
-	lfd	    f1, 8(r3)
-	lfd		f2, 16(r3)
-	lfd		f3, 24(r3)
-	lfd		f4, 32(r3)
-	lfd		f5, 40(r3)
-	lfd		f6, 48(r3)
-	lfd		f7, 56(r3)
-	lfd		f8, 64(r3)
-	lfd		f9, 72(r3)
-	lfd		f10, 80(r3)
-	lfd		f11, 88(r3)
-	lfd		f12, 96(r3)
-	lfd		f13, 104(r3)
-	lfd		f14, 112(r3)
-	lfd		f15, 120(r3)
-	lfd		f16, 128(r3)
-	lfd		f17, 136(r3)
-	lfd		f18, 144(r3)
-	lfd		f19, 152(r3)
-	lfd		f20, 160(r3)
-	lfd		f21, 168(r3)
-	lfd		f22, 176(r3)
-	lfd		f23, 184(r3)
-	lfd		f24, 192(r3)
-	lfd		f25, 200(r3)
-	lfd		f26, 208(r3)
-	lfd		f27, 216(r3)
-	lfd		f28, 224(r3)
-	lfd		f29, 232(r3)
-	lfd		f30, 240(r3)
-	lfd		f31, 248(r3)
-
-#else
-
-	/* Buffer address is in r3.  Restore each flop register from an offset
-	into this buffer. 
-	
-	First the FPSCR. */
-	lfs		f31, 128(r3)
-	mtfsf	f31, 7
-
-	lfs		f0, 0(r3)
-	lfs		f1, 4(r3)
-	lfs		f2, 8(r3)
-	lfs		f3, 12(r3)
-	lfs		f4, 16(r3)
-	lfs		f5, 20(r3)
-	lfs		f6, 24(r3)
-	lfs		f7, 28(r3)
-	lfs		f8, 32(r3)
-	lfs		f9, 36(r3)
-	lfs		f10, 40(r3)
-	lfs		f11, 44(r3)
-	lfs		f12, 48(r3)
-	lfs		f13, 52(r3)
-	lfs		f14, 56(r3)
-	lfs		f15, 60(r3)
-	lfs		f16, 64(r3)
-	lfs		f17, 68(r3)
-	lfs		f18, 72(r3)
-	lfs		f19, 76(r3)
-	lfs		f20, 80(r3)
-	lfs		f21, 84(r3)
-	lfs		f22, 88(r3)
-	lfs		f23, 92(r3)
-	lfs		f24, 96(r3)
-	lfs		f25, 100(r3)
-	lfs		f26, 104(r3)
-	lfs		f27, 108(r3)
-	lfs		f28, 112(r3)
-	lfs		f29, 116(r3)
-	lfs		f30, 120(r3)
-	lfs		f31, 124(r3)
-
-#endif
-
-	blr
-
-#endif /* configUSE_FPU. */
-
-
diff --git a/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portmacro.h b/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portmacro.h
deleted file mode 100755
index 171140e..0000000
--- a/FreeRTOS/Source/portable/GCC/PPC440_Xilinx/portmacro.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#include "xexception_l.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* This port uses the critical nesting count from the TCB rather than
-maintaining a separate value and then saving this value in the task stack. */
-#define portCRITICAL_NESTING_IN_TCB		1
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS()		XExc_mDisableExceptions( XEXC_NON_CRITICAL );
-#define portENABLE_INTERRUPTS()			XExc_mEnableExceptions( XEXC_NON_CRITICAL );
-
-/*-----------------------------------------------------------*/
-
-/* Critical section macros. */
-void vTaskEnterCritical( void );
-void vTaskExitCritical( void );
-#define portENTER_CRITICAL()			vTaskEnterCritical()
-#define portEXIT_CRITICAL()				vTaskExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-void vPortYield( void );
-#define portYIELD() asm volatile ( "SC \n\t NOP" )
-#define portYIELD_FROM_ISR() vTaskSwitchContext()
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			8
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()					asm volatile ( "NOP" )
-
-/* There are 32 * 32bit floating point regieters, plus the FPSCR to save. */
-#define portNO_FLOP_REGISTERS_TO_SAVE  ( 32 + 1 )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-/* Port specific interrupt handling functions. */
-void vPortSetupInterruptController( void );
-BaseType_t xPortInstallInterruptHandler( uint8_t ucInterruptID, XInterruptHandler pxHandler, void *pvCallBackRef );
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/Documentation.url b/FreeRTOS/Source/portable/GCC/RISC-V/Documentation.url
deleted file mode 100755
index 6d32fd8..0000000
--- a/FreeRTOS/Source/portable/GCC/RISC-V/Documentation.url
+++ /dev/null
@@ -1,5 +0,0 @@
-[{000214A0-0000-0000-C000-000000000046}]
-Prop3=19,11
-[InternetShortcut]
-IDList=
-URL=https://freertos.org/Using-FreeRTOS-on-RISC-V.html
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
deleted file mode 100755
index ef95484..0000000
--- a/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and t
-
- o permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * The FreeRTOS kernel's RISC-V port is split between the the code that is
- * common across all currently supported RISC-V chips (implementations of the
- * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
- *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
- *   is common to all currently supported RISC-V chips.  There is only one
- *   portASM.S file because the same file is built for all RISC-V target chips.
- *
- * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
- *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
- *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
- *   as there are multiple RISC-V chip implementations.
- *
- * !!!NOTE!!!
- * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
- * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
- * compiler's!) include path.  For example, if the chip in use includes a core
- * local interrupter (CLINT) and does not include any chip specific register
- * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
- *
- */
-
-/*
- * This freertos_risc_v_chip_specific_extensions.h is for use with Pulpino Ri5cy
- * devices, developed and tested using the Vega board RV32M1RM.
- */
-
-#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
-#define __FREERTOS_RISC_V_EXTENSIONS_H__
-
-#define portasmHAS_CLINT 0
-
-/* Constants to define the additional registers found on the Pulpino RI5KY. */
-#define lpstart0 	0x7b0
-#define lpend0 		0x7b1
-#define lpcount0 	0x7b2
-#define lpstart1 	0x7b4
-#define lpend1 		0x7b5
-#define lpcount1 	0x7b6
-
-/* Six additional registers to save and restore, as per the #defines above. */
-#define portasmADDITIONAL_CONTEXT_SIZE 6 /* Must be even number on 32-bit cores. */
-
-/* Save additional registers found on the Pulpino. */
-.macro portasmSAVE_ADDITIONAL_REGISTERS
-	addi sp, sp, -(portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE) /* Make room for the additional registers. */
-	csrr t0, lpstart0							 /* Load additional registers into accessible temporary registers. */
-	csrr t1, lpend0
-	csrr t2, lpcount0
-	csrr t3, lpstart1
-	csrr t4, lpend1
-	csrr t5, lpcount1
-	sw t0, 1 * portWORD_SIZE( sp )
-	sw t1, 2 * portWORD_SIZE( sp )
-	sw t2, 3 * portWORD_SIZE( sp )
-	sw t3, 4 * portWORD_SIZE( sp )
-	sw t4, 5 * portWORD_SIZE( sp )
-	sw t5, 6 * portWORD_SIZE( sp )
-	.endm
-
-/* Restore the additional registers found on the Pulpino. */
-.macro portasmRESTORE_ADDITIONAL_REGISTERS
-	lw t0, 1 * portWORD_SIZE( sp )			/* Load additional registers into accessible temporary registers. */
-	lw t1, 2 * portWORD_SIZE( sp )
-	lw t2, 3 * portWORD_SIZE( sp )
-	lw t3, 4 * portWORD_SIZE( sp )
-	lw t4, 5 * portWORD_SIZE( sp )
-	lw t5, 6 * portWORD_SIZE( sp )
-	csrw lpstart0, t0
-	csrw lpend0, t1
-	csrw lpcount0, t2
-	csrw lpstart1, t3
-	csrw lpend1, t4
-	csrw lpcount1, t5
-	addi sp, sp, (portasmADDITIONAL_CONTEXT_SIZE * portWORD_SIZE )/* Remove space added for additional registers. */
-	.endm
-
-#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
deleted file mode 100755
index b3562ab..0000000
--- a/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * The FreeRTOS kernel's RISC-V port is split between the the code that is
- * common across all currently supported RISC-V chips (implementations of the
- * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
- *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
- *   is common to all currently supported RISC-V chips.  There is only one
- *   portASM.S file because the same file is built for all RISC-V target chips.
- *
- * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
- *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
- *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
- *   as there are multiple RISC-V chip implementations.
- *
- * !!!NOTE!!!
- * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
- * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
- * compiler's!) include path.  For example, if the chip in use includes a core
- * local interrupter (CLINT) and does not include any chip specific register
- * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
- *
- */
-
-
-#ifndef __FREERTOS_RISC_V_EXTENSIONS_H__
-#define __FREERTOS_RISC_V_EXTENSIONS_H__
-
-#define portasmHAS_CLINT 1
-#define portasmADDITIONAL_CONTEXT_SIZE 0 /* Must be even number on 32-bit cores. */
-
-.macro portasmSAVE_ADDITIONAL_REGISTERS
-	/* No additional registers to save, so this macro does nothing. */
-	.endm
-
-/* Restore the additional registers found on the Pulpino. */
-.macro portasmRESTORE_ADDITIONAL_REGISTERS
-	/* No additional registers to restore, so this macro does nothing. */
-	.endm
-
-#endif /* __FREERTOS_RISC_V_EXTENSIONS_H__ */
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/readme.txt b/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
deleted file mode 100755
index b24c0b9..0000000
--- a/FreeRTOS/Source/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * The FreeRTOS kernel's RISC-V port is split between the the code that is
- * common across all currently supported RISC-V chips (implementations of the
- * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
- *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
- *   is common to all currently supported RISC-V chips.  There is only one
- *   portASM.S file because the same file is built for all RISC-V target chips.
- *
- * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
- *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
- *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
- *   as there are multiple RISC-V chip implementations.
- *
- * !!!NOTE!!!
- * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
- * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
- * compiler's!) include path.  For example, if the chip in use includes a core
- * local interrupter (CLINT) and does not include any chip specific register
- * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
- *
- */
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/port.c b/FreeRTOS/Source/portable/GCC/RISC-V/port.c
deleted file mode 100755
index 3a35de3..0000000
--- a/FreeRTOS/Source/portable/GCC/RISC-V/port.c
+++ /dev/null
@@ -1,189 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the RISC-V RV32 port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "portmacro.h"
-
-#ifndef configCLINT_BASE_ADDRESS
-	#warning configCLINT_BASE_ADDRESS must be defined in FreeRTOSConfig.h.  If the target chip includes a Core Local Interrupter (CLINT) then set configCLINT_BASE_ADDRESS to the CLINT base address.  Otherwise set configCLINT_BASE_ADDRESS to 0.
-#endif
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/* The stack used by interrupt service routines.  Set configISR_STACK_SIZE_WORDS
-to use a statically allocated array as the interrupt stack.  Alternative leave
-configISR_STACK_SIZE_WORDS undefined and update the linker script so that a
-linker variable names __freertos_irq_stack_top has the same value as the top
-of the stack used by main.  Using the linker script method will repurpose the
-stack that was used by main before the scheduler was started for use as the
-interrupt stack after the scheduler has started. */
-#ifdef configISR_STACK_SIZE_WORDS
-	static __attribute__ ((aligned(16))) StackType_t xISRStack[ configISR_STACK_SIZE_WORDS ] = { 0 };
-	const StackType_t xISRStackTop = ( StackType_t ) &( xISRStack[ ( configISR_STACK_SIZE_WORDS & ~portBYTE_ALIGNMENT_MASK ) - 1 ] );
-#else
-	extern const uint32_t __freertos_irq_stack_top[];
-	const StackType_t xISRStackTop = ( StackType_t ) __freertos_irq_stack_top;
-#endif
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void ) __attribute__(( weak ));
-
-/*-----------------------------------------------------------*/
-
-/* Used to program the machine timer compare register. */
-uint64_t ullNextTime = 0ULL;
-const uint64_t *pullNextTime = &ullNextTime;
-const size_t uxTimerIncrementsForOneTick = ( size_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ); /* Assumes increment won't go over 32-bits. */
-volatile uint64_t * const pullMachineTimerCompareRegister = ( volatile uint64_t * const ) ( configCLINT_BASE_ADDRESS + 0x4000 );
-
-/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
-stack checking.  A problem in the ISR stack will trigger an assert, not call the
-stack overflow hook function (because the stack overflow hook is specific to a
-task stack, not the ISR stack). */
-#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
-	#warning This path not tested, or even compiled yet.
-	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
-	the task stacks, and so will legitimately appear in many positions within
-	the ISR stack. */
-	#define portISR_STACK_FILL_BYTE	0xee
-
-	static const uint8_t ucExpectedStackBytes[] = {
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };	\
-
-	#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else
-	/* Define the function away. */
-	#define portCHECK_ISR_STACK()
-#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
-
-/*-----------------------------------------------------------*/
-
-#if( configCLINT_BASE_ADDRESS != 0 )
-
-	void vPortSetupTimerInterrupt( void )
-	{
-	uint32_t ulCurrentTimeHigh, ulCurrentTimeLow;
-	volatile uint32_t * const pulTimeHigh = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFFC );
-	volatile uint32_t * const pulTimeLow = ( volatile uint32_t * const ) ( configCLINT_BASE_ADDRESS + 0xBFF8 );
-
-		do
-		{
-			ulCurrentTimeHigh = *pulTimeHigh;
-			ulCurrentTimeLow = *pulTimeLow;
-		} while( ulCurrentTimeHigh != *pulTimeHigh );
-
-		ullNextTime = ( uint64_t ) ulCurrentTimeHigh;
-		ullNextTime <<= 32ULL;
-		ullNextTime |= ( uint64_t ) ulCurrentTimeLow;
-		ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
-		*pullMachineTimerCompareRegister = ullNextTime;
-
-		/* Prepare the time to use after the next tick interrupt. */
-		ullNextTime += ( uint64_t ) uxTimerIncrementsForOneTick;
-	}
-
-#endif /* ( configCLINT_BASE_ADDRESS != 0 ) */
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void xPortStartFirstTask( void );
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t mtvec = 0;
-
-		/* Check the least significant two bits of mtvec are 00 - indicating
-		single vector mode. */
-		__asm volatile( "csrr %0, mtvec" : "=r"( mtvec ) );
-		configASSERT( ( mtvec & 0x03UL ) == 0 );
-
-		/* Check alignment of the interrupt stack - which is the same as the
-		stack that was being used by main() prior to the scheduler being
-		started. */
-		configASSERT( ( xISRStackTop & portBYTE_ALIGNMENT_MASK ) == 0 );
-	}
-	#endif /* configASSERT_DEFINED */
-
-	/* If there is a CLINT then it is ok to use the default implementation
-	in this file, otherwise vPortSetupTimerInterrupt() must be implemented to
-	configure whichever clock is to be used to generate the tick interrupt. */
-	vPortSetupTimerInterrupt();
-
-	#if( configCLINT_BASE_ADDRESS != 0 )
-	{
-		/* Enable mtime and external interrupts.  1<<7 for timer interrupt, 1<<11
-		for external interrupt.  _RB_ What happens here when mtime is not present as
-		with pulpino? */
-		__asm volatile( "csrs mie, %0" :: "r"(0x880) );
-	}
-	#else
-	{
-		/* Enable external interrupts. */
-		__asm volatile( "csrs mie, %0" :: "r"(0x800) );
-	}
-	#endif /* configCLINT_BASE_ADDRESS */
-
-	xPortStartFirstTask();
-
-	/* Should not get here as after calling xPortStartFirstTask() only tasks
-	should be executing. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented. */
-	for( ;; );
-}
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S b/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
deleted file mode 100755
index 7974f7e..0000000
--- a/FreeRTOS/Source/portable/GCC/RISC-V/portASM.S
+++ /dev/null
@@ -1,420 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * The FreeRTOS kernel's RISC-V port is split between the the code that is
- * common across all currently supported RISC-V chips (implementations of the
- * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
- *
- * + The code that is common to all RISC-V chips is implemented in
- *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one
- *   portASM.S file because the same file is used no matter which RISC-V chip is
- *   in use.
- *
- * + The code that tailors the kernel's RISC-V port to a specific RISC-V
- *   chip is implemented in freertos_risc_v_chip_specific_extensions.h.  There
- *   is one freertos_risc_v_chip_specific_extensions.h that can be used with any
- *   RISC-V chip that both includes a standard CLINT and does not add to the
- *   base set of RISC-V registers.  There are additional
- *   freertos_risc_v_chip_specific_extensions.h files for RISC-V implementations
- *   that do not include a standard CLINT or do add to the base set of RISC-V
- *   registers.
- *
- * CARE MUST BE TAKEN TO INCLDUE THE CORRECT
- * freertos_risc_v_chip_specific_extensions.h HEADER FILE FOR THE CHIP
- * IN USE.  To include the correct freertos_risc_v_chip_specific_extensions.h
- * header file ensure the path to the correct header file is in the assembler's
- * include path.
- *
- * This freertos_risc_v_chip_specific_extensions.h is for use on RISC-V chips
- * that include a standard CLINT and do not add to the base set of RISC-V
- * registers.
- *
- */
-#if __riscv_xlen == 64
-	#define portWORD_SIZE 8
-	#define store_x sd
-	#define load_x ld
-#elif __riscv_xlen == 32
-	#define store_x sw
-	#define load_x lw
-	#define portWORD_SIZE 4
-#else
-	#error Assembler did not define __riscv_xlen
-#endif
-
-#include "freertos_risc_v_chip_specific_extensions.h"
-
-/* Check the freertos_risc_v_chip_specific_extensions.h and/or command line
-definitions. */
-#ifndef portasmHAS_CLINT
-	#error freertos_risc_v_chip_specific_extensions.h must define portasmHAS_CLINT to either 1 (CLINT present) or 0 (clint not present).
-#endif
-
-#ifndef portasmHANDLE_INTERRUPT
-	#error portasmHANDLE_INTERRUPT must be defined to the function to be called to handle external/peripheral interrupts.  portasmHANDLE_INTERRUPT can be defined on the assmbler command line or in the appropriate freertos_risc_v_chip_specific_extensions.h header file.
-#endif
-
-/* Only the standard core registers are stored by default.  Any additional
-registers must be saved by the portasmSAVE_ADDITIONAL_REGISTERS and
-portasmRESTORE_ADDITIONAL_REGISTERS macros - which can be defined in a chip
-specific version of freertos_risc_v_chip_specific_extensions.h.  See the notes
-at the top of this file. */
-#define portCONTEXT_SIZE ( 30 * portWORD_SIZE )
-
-.global xPortStartFirstTask
-.global freertos_risc_v_trap_handler
-.global pxPortInitialiseStack
-.extern pxCurrentTCB
-.extern ulPortTrapHandler
-.extern vTaskSwitchContext
-.extern Timer_IRQHandler
-.extern pullMachineTimerCompareRegister
-.extern pullNextTime
-.extern uxTimerIncrementsForOneTick /* size_t type so 32-bit on 32-bit core and 64-bits on 64-bit core. */
-.extern xISRStackTop
-
-/*-----------------------------------------------------------*/
-
-.align 8
-.func
-freertos_risc_v_trap_handler:
-	addi sp, sp, -portCONTEXT_SIZE
-	store_x x1, 1 * portWORD_SIZE( sp )
-	store_x x5, 2 * portWORD_SIZE( sp )
-	store_x x6, 3 * portWORD_SIZE( sp )
-	store_x x7, 4 * portWORD_SIZE( sp )
-	store_x x8, 5 * portWORD_SIZE( sp )
-	store_x x9, 6 * portWORD_SIZE( sp )
-	store_x x10, 7 * portWORD_SIZE( sp )
-	store_x x11, 8 * portWORD_SIZE( sp )
-	store_x x12, 9 * portWORD_SIZE( sp )
-	store_x x13, 10 * portWORD_SIZE( sp )
-	store_x x14, 11 * portWORD_SIZE( sp )
-	store_x x15, 12 * portWORD_SIZE( sp )
-	store_x x16, 13 * portWORD_SIZE( sp )
-	store_x x17, 14 * portWORD_SIZE( sp )
-	store_x x18, 15 * portWORD_SIZE( sp )
-	store_x x19, 16 * portWORD_SIZE( sp )
-	store_x x20, 17 * portWORD_SIZE( sp )
-	store_x x21, 18 * portWORD_SIZE( sp )
-	store_x x22, 19 * portWORD_SIZE( sp )
-	store_x x23, 20 * portWORD_SIZE( sp )
-	store_x x24, 21 * portWORD_SIZE( sp )
-	store_x x25, 22 * portWORD_SIZE( sp )
-	store_x x26, 23 * portWORD_SIZE( sp )
-	store_x x27, 24 * portWORD_SIZE( sp )
-	store_x x28, 25 * portWORD_SIZE( sp )
-	store_x x29, 26 * portWORD_SIZE( sp )
-	store_x x30, 27 * portWORD_SIZE( sp )
-	store_x x31, 28 * portWORD_SIZE( sp )
-
-	csrr t0, mstatus					/* Required for MPIE bit. */
-	store_x t0, 29 * portWORD_SIZE( sp )
-
-	portasmSAVE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to save any registers unique to the RISC-V implementation. */
-
-	load_x  t0, pxCurrentTCB			/* Load pxCurrentTCB. */
-	store_x  sp, 0( t0 )				/* Write sp to first TCB member. */
-
-	csrr a0, mcause
-	csrr a1, mepc
-
-test_if_asynchronous:
-	srli a2, a0, __riscv_xlen - 1		/* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
-	beq a2, x0, handle_synchronous		/* Branch past interrupt handing if not asynchronous. */
-	store_x a1, 0( sp )					/* Asynch so save unmodified exception return address. */
-
-handle_asynchronous:
-
-#if( portasmHAS_CLINT != 0 )
-
-	test_if_mtimer:						/* If there is a CLINT then the mtimer is used to generate the tick interrupt. */
-
-		addi t0, x0, 1
-
-		slli t0, t0, __riscv_xlen - 1   /* LSB is already set, shift into MSB.  Shift 31 on 32-bit or 63 on 64-bit cores. */
-		addi t1, t0, 7					/* 0x8000[]0007 == machine timer interrupt. */
-		bne a0, t1, test_if_external_interrupt
-
-		load_x t0, pullMachineTimerCompareRegister  /* Load address of compare register into t0. */
-		load_x t1, pullNextTime  		/* Load the address of ullNextTime into t1. */
-
-		#if( __riscv_xlen == 32 )
-
-			/* Update the 64-bit mtimer compare match value in two 32-bit writes. */
-			lw t2, 0(t1)				/* Load the low word of ullNextTime into t2. */
-			lw t3, 4(t1)				/* Load the high word of ullNextTime into t3. */
-			sw t2, 0(t0)				/* Store low word of ullNextTime into compare register. */
-			sw t3, 4(t0)				/* Store high word of ullNextTime into compare register. */
-			lw t0, uxTimerIncrementsForOneTick	/* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
-			add t4, t0, t2				/* Add the low word of ullNextTime to the timer increments for one tick (assumes timer increment for one tick fits in 32-bits). */
-			sltu t5, t4, t2				/* See if the sum of low words overflowed (what about the zero case?). */
-			add t6, t3, t5				/* Add overflow to high word of ullNextTime. */
-			sw t4, 0(t1)				/* Store new low word of ullNextTime. */
-			sw t6, 4(t1)				/* Store new high word of ullNextTime. */
-
-		#endif /* __riscv_xlen == 32 */
-
-		#if( __riscv_xlen == 64 )
-
-			/* Update the 64-bit mtimer compare match value. */
-			ld t2, 0(t1)			 	/* Load ullNextTime into t2. */
-			sd t2, 0(t0)				/* Store ullNextTime into compare register. */
-			ld t0, uxTimerIncrementsForOneTick  /* Load the value of ullTimerIncrementForOneTick into t0 (could this be optimized by storing in an array next to pullNextTime?). */
-			add t4, t0, t2				/* Add ullNextTime to the timer increments for one tick. */
-			sd t4, 0(t1)				/* Store ullNextTime. */
-
-		#endif /* __riscv_xlen == 64 */
-
-		load_x sp, xISRStackTop			/* Switch to ISR stack before function call. */
-		jal xTaskIncrementTick
-		beqz a0, processed_source		/* Don't switch context if incrementing tick didn't unblock a task. */
-		jal vTaskSwitchContext
-		j processed_source
-
-	test_if_external_interrupt:			/* If there is a CLINT and the mtimer interrupt is not pending then check to see if an external interrupt is pending. */
-		addi t1, t1, 4					/* 0x80000007 + 4 = 0x8000000b == Machine external interrupt. */
-		bne a0, t1, as_yet_unhandled	/* Something as yet unhandled. */
-
-#endif /* portasmHAS_CLINT */
-
-	load_x sp, xISRStackTop				/* Switch to ISR stack before function call. */
-	jal portasmHANDLE_INTERRUPT			/* Jump to the interrupt handler if there is no CLINT or if there is a CLINT and it has been determined that an external interrupt is pending. */
-	j processed_source
-
-handle_synchronous:
-	addi a1, a1, 4						/* Synchronous so updated exception return address to the instruction after the instruction that generated the exeption. */
-	store_x a1, 0( sp )					/* Save updated exception return address. */
-
-test_if_environment_call:
-	li t0, 11 							/* 11 == environment call. */
-	bne a0, t0, is_exception			/* Not an M environment call, so some other exception. */
-	load_x sp, xISRStackTop				/* Switch to ISR stack before function call. */
-	jal vTaskSwitchContext
-	j processed_source
-
-is_exception:
-	ebreak
-	j is_exception
-
-as_yet_unhandled:
-	ebreak
-	j as_yet_unhandled
-
-processed_source:
-	load_x  t1, pxCurrentTCB			/* Load pxCurrentTCB. */
-	load_x  sp, 0( t1 )				 	/* Read sp from first TCB member. */
-
-	/* Load mret with the address of the next instruction in the task to run next. */
-	load_x t0, 0( sp )
-	csrw mepc, t0
-
-	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
-
-	/* Load mstatus with the interrupt enable bits used by the task. */
-	load_x  t0, 29 * portWORD_SIZE( sp )
-	csrw mstatus, t0						/* Required for MPIE bit. */
-
-	load_x  x1, 1 * portWORD_SIZE( sp )
-	load_x  x5, 2 * portWORD_SIZE( sp )		/* t0 */
-	load_x  x6, 3 * portWORD_SIZE( sp )		/* t1 */
-	load_x  x7, 4 * portWORD_SIZE( sp )		/* t2 */
-	load_x  x8, 5 * portWORD_SIZE( sp )		/* s0/fp */
-	load_x  x9, 6 * portWORD_SIZE( sp )		/* s1 */
-	load_x  x10, 7 * portWORD_SIZE( sp )	/* a0 */
-	load_x  x11, 8 * portWORD_SIZE( sp )	/* a1 */
-	load_x  x12, 9 * portWORD_SIZE( sp )	/* a2 */
-	load_x  x13, 10 * portWORD_SIZE( sp )	/* a3 */
-	load_x  x14, 11 * portWORD_SIZE( sp )	/* a4 */
-	load_x  x15, 12 * portWORD_SIZE( sp )	/* a5 */
-	load_x  x16, 13 * portWORD_SIZE( sp )	/* a6 */
-	load_x  x17, 14 * portWORD_SIZE( sp )	/* a7 */
-	load_x  x18, 15 * portWORD_SIZE( sp )	/* s2 */
-	load_x  x19, 16 * portWORD_SIZE( sp )	/* s3 */
-	load_x  x20, 17 * portWORD_SIZE( sp )	/* s4 */
-	load_x  x21, 18 * portWORD_SIZE( sp )	/* s5 */
-	load_x  x22, 19 * portWORD_SIZE( sp )	/* s6 */
-	load_x  x23, 20 * portWORD_SIZE( sp )	/* s7 */
-	load_x  x24, 21 * portWORD_SIZE( sp )	/* s8 */
-	load_x  x25, 22 * portWORD_SIZE( sp )	/* s9 */
-	load_x  x26, 23 * portWORD_SIZE( sp )	/* s10 */
-	load_x  x27, 24 * portWORD_SIZE( sp )	/* s11 */
-	load_x  x28, 25 * portWORD_SIZE( sp )	/* t3 */
-	load_x  x29, 26 * portWORD_SIZE( sp )	/* t4 */
-	load_x  x30, 27 * portWORD_SIZE( sp )	/* t5 */
-	load_x  x31, 28 * portWORD_SIZE( sp )	/* t6 */
-	addi sp, sp, portCONTEXT_SIZE
-
-	mret
-	.endfunc
-/*-----------------------------------------------------------*/
-
-.align 8
-.func
-xPortStartFirstTask:
-
-#if( portasmHAS_CLINT != 0 )
-	/* If there is a clint then interrupts can branch directly to the FreeRTOS
-	trap handler.  Otherwise the interrupt controller will need to be configured
-	outside of this file. */
-	la t0, freertos_risc_v_trap_handler
-	csrw mtvec, t0
-#endif /* portasmHAS_CLILNT */
-
-	load_x  sp, pxCurrentTCB			/* Load pxCurrentTCB. */
-	load_x  sp, 0( sp )				 	/* Read sp from first TCB member. */
-
-	load_x  x1, 0( sp ) /* Note for starting the scheduler the exception return address is used as the function return address. */
-
-	portasmRESTORE_ADDITIONAL_REGISTERS	/* Defined in freertos_risc_v_chip_specific_extensions.h to restore any registers unique to the RISC-V implementation. */
-
-	load_x  t0, 29 * portWORD_SIZE( sp )	/* mstatus */
-	csrrw  x0, mstatus, t0					/* Interrupts enabled from here! */
-
-	load_x  x5, 2 * portWORD_SIZE( sp )		/* t0 */
-	load_x  x6, 3 * portWORD_SIZE( sp )		/* t1 */
-	load_x  x7, 4 * portWORD_SIZE( sp )		/* t2 */
-	load_x  x8, 5 * portWORD_SIZE( sp )		/* s0/fp */
-	load_x  x9, 6 * portWORD_SIZE( sp )		/* s1 */
-	load_x  x10, 7 * portWORD_SIZE( sp )	/* a0 */
-	load_x  x11, 8 * portWORD_SIZE( sp )	/* a1 */
-	load_x  x12, 9 * portWORD_SIZE( sp )	/* a2 */
-	load_x  x13, 10 * portWORD_SIZE( sp )	/* a3 */
-	load_x  x14, 11 * portWORD_SIZE( sp )	/* a4 */
-	load_x  x15, 12 * portWORD_SIZE( sp )	/* a5 */
-	load_x  x16, 13 * portWORD_SIZE( sp )	/* a6 */
-	load_x  x17, 14 * portWORD_SIZE( sp )	/* a7 */
-	load_x  x18, 15 * portWORD_SIZE( sp )	/* s2 */
-	load_x  x19, 16 * portWORD_SIZE( sp )	/* s3 */
-	load_x  x20, 17 * portWORD_SIZE( sp )	/* s4 */
-	load_x  x21, 18 * portWORD_SIZE( sp )	/* s5 */
-	load_x  x22, 19 * portWORD_SIZE( sp )	/* s6 */
-	load_x  x23, 20 * portWORD_SIZE( sp )	/* s7 */
-	load_x  x24, 21 * portWORD_SIZE( sp )	/* s8 */
-	load_x  x25, 22 * portWORD_SIZE( sp )	/* s9 */
-	load_x  x26, 23 * portWORD_SIZE( sp )	/* s10 */
-	load_x  x27, 24 * portWORD_SIZE( sp )	/* s11 */
-	load_x  x28, 25 * portWORD_SIZE( sp )	/* t3 */
-	load_x  x29, 26 * portWORD_SIZE( sp )	/* t4 */
-	load_x  x30, 27 * portWORD_SIZE( sp )	/* t5 */
-	load_x  x31, 28 * portWORD_SIZE( sp )	/* t6 */
-	addi	sp, sp, portCONTEXT_SIZE
-	ret
-	.endfunc
-/*-----------------------------------------------------------*/
-
-/*
- * Unlike other ports pxPortInitialiseStack() is written in assembly code as it
- * needs access to the portasmADDITIONAL_CONTEXT_SIZE constant.  The prototype
- * for the function is as per the other ports:
- * StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters );
- *
- * As per the standard RISC-V ABI pxTopcOfStack is passed in in a0, pxCode in
- * a1, and pvParameters in a2.  The new top of stack is passed out in a0.
- *
- * RISC-V maps registers to ABI names as follows (X1 to X31 integer registers
- * for the 'I' profile, X1 to X15 for the 'E' profile, currently I assumed).
- *
- * Register		ABI Name	Description						Saver
- * x0			zero		Hard-wired zero					-
- * x1			ra			Return address					Caller
- * x2			sp			Stack pointer					Callee
- * x3			gp			Global pointer					-
- * x4			tp			Thread pointer					-
- * x5-7			t0-2		Temporaries						Caller
- * x8			s0/fp		Saved register/Frame pointer	Callee
- * x9			s1			Saved register					Callee
- * x10-11		a0-1		Function Arguments/return values Caller
- * x12-17		a2-7		Function arguments				Caller
- * x18-27		s2-11		Saved registers					Callee
- * x28-31		t3-6		Temporaries						Caller
- *
- * The RISC-V context is saved t FreeRTOS tasks in the following stack frame,
- * where the global and thread pointers are currently assumed to be constant so
- * are not saved:
- *
- * mstatus
- * x31
- * x30
- * x29
- * x28
- * x27
- * x26
- * x25
- * x24
- * x23
- * x22
- * x21
- * x20
- * x19
- * x18
- * x17
- * x16
- * x15
- * x14
- * x13
- * x12
- * x11
- * pvParameters
- * x9
- * x8
- * x7
- * x6
- * x5
- * portTASK_RETURN_ADDRESS
- * [chip specific registers go here]
- * pxCode
- */
-.align 8
-.func
-pxPortInitialiseStack:
-
-	csrr t0, mstatus					/* Obtain current mstatus value. */
-	addi t1, x0, 0x188					/* Generate the value 0x1880, which are the MPIE and MPP bits to set in mstatus. */
-	slli t1, t1, 4
-	or t0, t0, t1						/* Set MPIE and MPP bits in mstatus value. */
-
-	addi a0, a0, -portWORD_SIZE
-	store_x t0, 0(a0)					/* mstatus onto the stack. */
-	addi a0, a0, -(22 * portWORD_SIZE)	/* Space for registers x11-x31. */
-	store_x a2, 0(a0)					/* Task parameters (pvParameters parameter) goes into register X10/a0 on the stack. */
-	addi a0, a0, -(6 * portWORD_SIZE)	/* Space for registers x5-x9. */
-	store_x x0, 0(a0)					/* Return address onto the stack, could be portTASK_RETURN_ADDRESS */
-	addi t0, x0, portasmADDITIONAL_CONTEXT_SIZE /* The number of chip specific additional registers. */
-chip_specific_stack_frame:				/* First add any chip specific registers to the stack frame being created. */
-	beq t0, x0, 1f						/* No more chip specific registers to save. */
-	addi a0, a0, -portWORD_SIZE			/* Make space for chip specific register. */
-	store_x x0, 0(a0)					/* Give the chip specific register an initial value of zero. */
-	addi t0, t0, -1						/* Decrement the count of chip specific registers remaining. */
-	j chip_specific_stack_frame			/* Until no more chip specific registers. */
-1:
-	addi a0, a0, -portWORD_SIZE
-	store_x a1, 0(a0)					/* mret value (pxCode parameter) onto the stack. */
-	ret
-	.endfunc
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h b/FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h
deleted file mode 100755
index 61ac5c8..0000000
--- a/FreeRTOS/Source/portable/GCC/RISC-V/portmacro.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#if __riscv_xlen == 64
-	#define portSTACK_TYPE			uint64_t
-	#define portBASE_TYPE			int64_t
-	#define portUBASE_TYPE			uint64_t
-	#define portMAX_DELAY 			( TickType_t ) 0xffffffffffffffffUL
-	#define portPOINTER_SIZE_TYPE 	uint64_t
-#elif __riscv_xlen == 32
-	#define portSTACK_TYPE	uint32_t
-	#define portBASE_TYPE	int32_t
-	#define portUBASE_TYPE	uint32_t
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#else
-	#error Assembler did not define __riscv_xlen
-#endif
-
-
-typedef portSTACK_TYPE StackType_t;
-typedef portBASE_TYPE BaseType_t;
-typedef portUBASE_TYPE UBaseType_t;
-typedef portUBASE_TYPE TickType_t;
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#ifdef __riscv64
-	#error This is the RV32 port that has not yet been adapted for 64.
-	#define portBYTE_ALIGNMENT			16
-#else
-	#define portBYTE_ALIGNMENT 8
-#endif
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
-extern void vTaskSwitchContext( void );
-#define portYIELD() __asm volatile( "ecall" );
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vTaskSwitchContext()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-
-/* Critical section management. */
-#define portCRITICAL_NESTING_IN_TCB					1
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-
-#define portSET_INTERRUPT_MASK_FROM_ISR() 0
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
-#define portDISABLE_INTERRUPTS()	__asm volatile( "csrc mstatus, 8" )
-#define portENABLE_INTERRUPTS()		__asm volatile( "csrs mstatus, 8" )
-#define portENTER_CRITICAL()	vTaskEnterCritical()
-#define portEXIT_CRITICAL()		vTaskExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - __builtin_clz( uxReadyPriorities ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-/*-----------------------------------------------------------*/
-
-#define portNOP() __asm volatile 	( " nop " )
-
-#define portINLINE	__inline
-
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE inline __attribute__(( always_inline))
-#endif
-
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/RISC-V/readme.txt b/FreeRTOS/Source/portable/GCC/RISC-V/readme.txt
deleted file mode 100755
index b24c0b9..0000000
--- a/FreeRTOS/Source/portable/GCC/RISC-V/readme.txt
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * The FreeRTOS kernel's RISC-V port is split between the the code that is
- * common across all currently supported RISC-V chips (implementations of the
- * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
- *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
- *   is common to all currently supported RISC-V chips.  There is only one
- *   portASM.S file because the same file is built for all RISC-V target chips.
- *
- * + Header files called freertos_risc_v_chip_specific_extensions.h contain the
- *   code that tailors the FreeRTOS kernel's RISC-V port to a specific RISC-V
- *   chip.  There are multiple freertos_risc_v_chip_specific_extensions.h files
- *   as there are multiple RISC-V chip implementations.
- *
- * !!!NOTE!!!
- * TAKE CARE TO INCLUDE THE CORRECT freertos_risc_v_chip_specific_extensions.h
- * HEADER FILE FOR THE CHIP IN USE.  This is done using the assembler's (not the
- * compiler's!) include path.  For example, if the chip in use includes a core
- * local interrupter (CLINT) and does not include any chip specific register
- * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
- *
- */
diff --git a/FreeRTOS/Source/portable/GCC/RL78/isr_support.h b/FreeRTOS/Source/portable/GCC/RL78/isr_support.h
deleted file mode 100755
index 1a32cf3..0000000
--- a/FreeRTOS/Source/portable/GCC/RL78/isr_support.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Variables used by scheduler */
-	.extern    _pxCurrentTCB
-	.extern    _usCriticalNesting
-
-/*
- * portSAVE_CONTEXT MACRO
- * Saves the context of the general purpose registers, CS and ES (only in far
- * memory mode) registers the usCriticalNesting Value and the Stack Pointer
- * of the active Task onto the task stack
- */
-	.macro portSAVE_CONTEXT
-
-	SEL 	RB0
-
-	/* Save AX Register to stack. */
-	PUSH	AX
-	PUSH	HL
-	/* Save CS register. */
-	MOV 	A, CS
-	XCH		A, X
-	/* Save ES register. */
-	MOV		A, ES
-	PUSH	AX
-	/* Save the remaining general purpose registers from bank 0. */
-	PUSH	DE
-	PUSH	BC
-	/* Save the other register banks - only necessary in the GCC port. */
-	SEL		RB1
-	PUSH	AX
-	PUSH	BC
-	PUSH	DE
-	PUSH	HL
-	SEL		RB2
-	PUSH	AX
-	PUSH	BC
-	PUSH	DE
-	PUSH	HL
-	/* Registers in bank 3 are for ISR use only so don't need saving. */
-	SEL		RB0
-	/* Save the usCriticalNesting value. */
-	MOVW	AX, !_usCriticalNesting
-	PUSH	AX
-	/* Save the Stack pointer. */
-	MOVW	AX, !_pxCurrentTCB
-	MOVW	HL, AX
-	MOVW	AX, SP
-	MOVW	[HL], AX
-	/* Switch stack pointers. */
-	movw sp,#_stack /* Set stack pointer */
-
-	.endm
-
-
-/*
- * portRESTORE_CONTEXT MACRO
- * Restores the task Stack Pointer then use this to restore usCriticalNesting,
- * general purpose registers and the CS and ES (only in far memory mode)
- * of the selected task from the task stack
- */
-.macro portRESTORE_CONTEXT MACRO
-	SEL		RB0
-	/* Restore the Stack pointer. */
-	MOVW	AX, !_pxCurrentTCB
-	MOVW	HL, AX
-	MOVW	AX, [HL]
-	MOVW	SP, AX
-	/* Restore usCriticalNesting value. */
-	POP		AX
-	MOVW	!_usCriticalNesting, AX
-	/* Restore the alternative register banks - only necessary in the GCC
-	port.  Register bank 3 is dedicated for interrupts use so is not saved or
-	restored. */
-	SEL		RB2
-	POP		HL
-	POP		DE
-	POP		BC
-	POP		AX
-	SEL		RB1
-	POP		HL
-	POP		DE
-	POP		BC
-	POP		AX
-	SEL		RB0
-	/* Restore the necessary general purpose registers. */
-	POP		BC
-	POP		DE
-	/* Restore the ES register. */
-	POP		AX
-	MOV		ES, A
-	/* Restore the CS register. */
-	XCH		A, X
-	MOV		CS, A
-	/* Restore general purpose register HL. */
-	POP		HL
-	/* Restore AX. */
-	POP		AX
-
-	.endm
-
diff --git a/FreeRTOS/Source/portable/GCC/RL78/port.c b/FreeRTOS/Source/portable/GCC/RL78/port.c
deleted file mode 100755
index 906b5da..0000000
--- a/FreeRTOS/Source/portable/GCC/RL78/port.c
+++ /dev/null
@@ -1,211 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* The critical nesting value is initialised to a non zero value to ensure
-interrupts don't accidentally become enabled before the scheduler is started. */
-#define portINITIAL_CRITICAL_NESTING  ( ( uint16_t ) 10 )
-
-/* Initial PSW value allocated to a newly created task.
- *   11000110
- *   ||||||||-------------- Fill byte
- *   |||||||--------------- Carry Flag cleared
- *   |||||----------------- In-service priority Flags set to low level
- *   ||||------------------ Register bank Select 0 Flag cleared
- *   |||------------------- Auxiliary Carry Flag cleared
- *   ||-------------------- Register bank Select 1 Flag cleared
- *   |--------------------- Zero Flag set
- *   ---------------------- Global Interrupt Flag set (enabled)
- */
-#define portPSW		  ( 0xc6UL )
-
-/* Each task maintains a count of the critical section nesting depth.  Each time
-a critical section is entered the count is incremented.  Each time a critical
-section is exited the count is decremented - with interrupts only being
-re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as that could cause problems during the startup
-sequence. */
-volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Sets up the periodic ISR used for the RTOS tick.
- */
-__attribute__((weak)) void vApplicationSetupTimerInterrupt( void );
-
-/*
- * Starts the scheduler by loading the context of the first task to run.
- * (defined in portasm.S).
- */
-extern void vPortStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint32_t *pulLocal;
-
-	/* Stack type and pointers to the stack type are both 2 bytes. */
-
-	/* Parameters are passed in on the stack, and written using a 32bit value
-	hence a space is left for the second two bytes. */
-	pxTopOfStack--;
-
-	/* Write in the parameter value. */
-	pulLocal =  ( uint32_t * ) pxTopOfStack;
-	*pulLocal = ( StackType_t ) pvParameters;
-	pxTopOfStack--;
-
-	/* The return address, leaving space for the first two bytes of	the
-	32-bit value. */
-	pxTopOfStack--;
-	pulLocal = ( uint32_t * ) pxTopOfStack;
-	*pulLocal = ( uint32_t ) 0;
-	pxTopOfStack--;
-
-	/* The start address / PSW value is also written in as a 32bit value,
-	so leave a space for the second two bytes. */
-	pxTopOfStack--;
-
-	/* Task function start address combined with the PSW. */
-	pulLocal = ( uint32_t * ) pxTopOfStack;
-	*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
-	pxTopOfStack--;
-
-	/* An initial value for the AX register. */
-	*pxTopOfStack = ( StackType_t ) 0x1111;
-	pxTopOfStack--;
-
-	/* An initial value for the HL register. */
-	*pxTopOfStack = ( StackType_t ) 0x2222;
-	pxTopOfStack--;
-
-	/* CS and ES registers. */
-	*pxTopOfStack = ( StackType_t ) 0x0F00;
-	pxTopOfStack--;
-
-	/* The remaining general purpose registers bank 0 (DE and BC) and the other
-	two register banks...register bank 3 is dedicated for use by interrupts so
-	is not saved as part of the task context. */
-	pxTopOfStack -= 10;
-
-	/* Finally the critical section nesting count is set to zero when the task
-	first starts. */
-	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
-
-	/* Return a pointer to the top of the stack that has beene generated so it
-	can	be stored in the task control block for the task. */
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-portBASE_TYPE xPortStartScheduler( void )
-{
-	/* Setup the hardware to generate the tick.  Interrupts are disabled when
-	this function is called. */
-	vApplicationSetupTimerInterrupt();
-
-	/* Restore the context of the first task that is going to run. */
-	vPortStartFirstTask();
-
-	/* Execution should not reach here as the tasks are now running! */
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the RL78 port will get stopped. */
-}
-/*-----------------------------------------------------------*/
-
-__attribute__((weak)) void vApplicationSetupTimerInterrupt( void )
-{
-const uint16_t usClockHz = 15000UL; /* Internal clock. */
-const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
-
-	/* Use the internal 15K clock. */
-	OSMC = ( unsigned char ) 0x16;
-
-	#ifdef RTCEN
-	{
-		/* Supply the interval timer clock. */
-		RTCEN = ( unsigned char ) 1U;
-
-		/* Disable INTIT interrupt. */
-		ITMK = ( unsigned char ) 1;
-
-		/* Disable ITMC operation. */
-		ITMC = ( unsigned char ) 0x0000;
-
-		/* Clear INIT interrupt. */
-		ITIF = ( unsigned char ) 0;
-
-		/* Set interval and enable interrupt operation. */
-		ITMC = usCompareMatch | 0x8000U;
-
-		/* Enable INTIT interrupt. */
-		ITMK = ( unsigned char ) 0;
-	}
-	#endif
-
-	#ifdef TMKAEN
-	{
-		/* Supply the interval timer clock. */
-		TMKAEN = ( unsigned char ) 1U;
-
-		/* Disable INTIT interrupt. */
-		TMKAMK = ( unsigned char ) 1;
-
-		/* Disable ITMC operation. */
-		ITMC = ( unsigned char ) 0x0000;
-
-		/* Clear INIT interrupt. */
-		TMKAIF = ( unsigned char ) 0;
-
-		/* Set interval and enable interrupt operation. */
-		ITMC = usCompareMatch | 0x8000U;
-
-		/* Enable INTIT interrupt. */
-		TMKAMK = ( unsigned char ) 0;
-	}
-	#endif
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/GCC/RL78/portasm.S b/FreeRTOS/Source/portable/GCC/RL78/portasm.S
deleted file mode 100755
index 17c0013..0000000
--- a/FreeRTOS/Source/portable/GCC/RL78/portasm.S
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include "FreeRTOSConfig.h"
-#include "ISR_Support.h"
-
-	.global    _vPortYield
-	.global    _vPortStartFirstTask
-	.global    _vPortTickISR
-
-	.extern    _vTaskSwitchContext
-	.extern    _xTaskIncrementTick
-
-	.text
-	.align 2
-
-/* FreeRTOS yield handler.  This is installed as the BRK software interrupt
-handler. */
-_vPortYield:
-	/* Save the context of the current task. */
-	portSAVE_CONTEXT
-	/* Call the scheduler to select the next task. */
-	call      !!_vTaskSwitchContext
-	/* Restore the context of the next task to run. */
-	portRESTORE_CONTEXT
-	retb
-
-
-/* Starts the scheduler by restoring the context of the task that will execute
-first. */
-	.align 2
-_vPortStartFirstTask:
-	/* Restore the context of whichever task will execute first. */
-	portRESTORE_CONTEXT
-	/* An interrupt stack frame is used so the task is started using RETI. */
-	reti
-
-/* FreeRTOS tick handler.  This is installed as the interval timer interrupt
-handler. */
-	.align 2
-_vPortTickISR:
-
-	/* Save the context of the currently executing task. */
-	portSAVE_CONTEXT
-	/* Call the RTOS tick function. */
-	call      !!_xTaskIncrementTick
-#if configUSE_PREEMPTION == 1
-	/* Select the next task to run. */
-	call      !!_vTaskSwitchContext
-#endif
-	/* Retore the context of whichever task will run next. */
-	portRESTORE_CONTEXT
-	reti
-
-	.end
-
diff --git a/FreeRTOS/Source/portable/GCC/RL78/portmacro.h b/FreeRTOS/Source/portable/GCC/RL78/portmacro.h
deleted file mode 100755
index 4e15678..0000000
--- a/FreeRTOS/Source/portable/GCC/RL78/portmacro.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE	uint16_t
-#define portBASE_TYPE   short
-#define portPOINTER_SIZE_TYPE uint16_t
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() __asm volatile ( "DI" )
-#define portENABLE_INTERRUPTS()	 __asm volatile ( "EI" )
-/*-----------------------------------------------------------*/
-
-/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING		( ( unsigned short ) 0 )
-
-#define portENTER_CRITICAL()													\
-{																				\
-extern volatile uint16_t usCriticalNesting;										\
-																				\
-	portDISABLE_INTERRUPTS();													\
-																				\
-	/* Now interrupts are disabled ulCriticalNesting can be accessed */			\
-	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
-	/* times portENTER_CRITICAL() has been called. */							\
-	usCriticalNesting++;														\
-}
-
-#define portEXIT_CRITICAL()														\
-{																				\
-extern volatile uint16_t usCriticalNesting;										\
-																				\
-	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
-	{																			\
-		/* Decrement the nesting count as we are leaving a critical section. */	\
-		usCriticalNesting--;													\
-																				\
-		/* If the nesting level has reached zero then interrupts should be */	\
-		/* re-enabled. */														\
-		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
-		{																		\
-			portENABLE_INTERRUPTS();											\
-		}																		\
-	}																			\
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-#define portYIELD() 	__asm volatile ( "BRK" )
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
-#define portNOP()	__asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Hardwware specifics. */
-#define portBYTE_ALIGNMENT	2
-#define portSTACK_GROWTH	( -1 )
-#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/RX100/port.c b/FreeRTOS/Source/portable/GCC/RX100/port.c
deleted file mode 100755
index b5c8d7d..0000000
--- a/FreeRTOS/Source/portable/GCC/RX100/port.c
+++ /dev/null
@@ -1,674 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
-
-/* Standard C includes. */
-#include "limits.h"
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#include "iodefine.h"
-
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
-
-/* The peripheral clock is divided by this value before being supplying the
-CMT. */
-#if ( configUSE_TICKLESS_IDLE == 0 )
-	/* If tickless idle is not used then the divisor can be fixed. */
-	#define portCLOCK_DIVISOR	8UL
-#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
-	#define portCLOCK_DIVISOR	512UL
-#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
-	#define portCLOCK_DIVISOR	128UL
-#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
-	#define portCLOCK_DIVISOR	32UL
-#else
-	#define portCLOCK_DIVISOR	8UL
-#endif
-
-/* These macros allow a critical section to be added around the call to
-xTaskIncrementTick(), which is only ever called from interrupts at the kernel
-priority - ie a known priority.  Therefore these local macros are a slight
-optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
-which would require the old IPL to be read first and stored in a local variable. */
-#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
-
-/* Keys required to lock and unlock access to certain system registers
-respectively. */
-#define portUNLOCK_KEY		0xA50B
-#define portLOCK_KEY		0xA500
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-static void prvStartFirstTask( void ) __attribute__((naked));
-
-/*
- * Software interrupt handler.  Performs the actual context switch (saving and
- * restoring of registers).  Written in asm code as direct register access is
- * required.
- */
-void vPortSoftwareInterruptISR( void ) __attribute__((naked));
-
-/*
- * The tick interrupt handler.
- */
-void vPortTickISR( void ) __attribute__((interrupt));
-
-/*
- * Sets up the periodic ISR used for the RTOS tick using the CMT.
- * The application writer can define configSETUP_TICK_INTERRUPT() (in
- * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
- * in place of prvSetupTimerInterrupt().
- */
-static void prvSetupTimerInterrupt( void );
-#ifndef configSETUP_TICK_INTERRUPT
-	/* The user has not provided their own tick interrupt configuration so use
-    the definition in this file (which uses the interval timer). */
-	#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
-#endif /* configSETUP_TICK_INTERRUPT */
-
-/*
- * Called after the sleep mode registers have been configured, prvSleep()
- * executes the pre and post sleep macros, and actually calls the wait
- * instruction.
- */
-#if configUSE_TICKLESS_IDLE == 1
-	static void prvSleep( TickType_t xExpectedIdleTime );
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*-----------------------------------------------------------*/
-
-/* Used in the context save and restore code. */
-extern void *pxCurrentTCB;
-
-/* Calculate how many clock increments make up a single tick period. */
-static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
-
-#if configUSE_TICKLESS_IDLE == 1
-
-	/* Holds the maximum number of ticks that can be suppressed - which is
-	basically how far into the future an interrupt can be generated. Set
-	during initialisation.  This is the maximum possible value that the
-	compare match register can hold divided by ulMatchValueForOneTick. */
-	static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
-
-	/* Flag set from the tick interrupt to allow the sleep processing to know if
-	sleep mode was exited because of a tick interrupt, or an interrupt
-	generated by something else. */
-	static volatile uint32_t ulTickFlag = pdFALSE;
-
-	/* The CMT counter is stopped temporarily each time it is re-programmed.
-	The following constant offsets the CMT counter match value by the number of
-	CMT	counts that would typically be missed while the counter was stopped to
-	compensate for the lost time.  The large difference between the divided CMT
-	clock and the CPU clock means it is likely ulStoppedTimerCompensation will
-	equal zero - and be optimised away. */
-	static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
-
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Offset to end up on 8 byte boundary. */
-	pxTopOfStack--;
-
-	/* R0 is not included as it is the stack pointer. */
-	*pxTopOfStack = 0x00;
-	pxTopOfStack--;
-    *pxTopOfStack = 0x00;
-	pxTopOfStack--;
- 	*pxTopOfStack = portINITIAL_PSW;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;
-
-	/* When debugging it can be useful if every register is set to a known
-	value.  Otherwise code space can be saved by just setting the registers
-	that need to be set. */
-	#ifdef USE_FULL_REGISTER_INITIALISATION
-	{
-		pxTopOfStack--;
-		*pxTopOfStack = 0x12345678;	/* r15. */
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaabbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xdddddddd;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xcccccccc;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xbbbbbbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaaaaaa;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x99999999;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x88888888;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x77777777;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x66666666;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x55555555;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x44444444;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x33333333;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x22222222;
-		pxTopOfStack--;
-	}
-	#else
-	{
-		/* Leave space for the registers that will get popped from the stack
-		when the task first starts executing. */
-		pxTopOfStack -= 15;
-	}
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x12345678; /* Accumulator. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x87654321; /* Accumulator. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Use pxCurrentTCB just so it does not get optimised away. */
-	if( pxCurrentTCB != NULL )
-	{
-		/* Call an application function to set up the timer that will generate
-		the tick interrupt.  This way the application can decide which
-		peripheral to use.  If tickless mode is used then the default
-		implementation defined in this file (which uses CMT0) should not be
-		overridden. */
-		configSETUP_TICK_INTERRUPT();
-
-		/* Enable the software interrupt. */
-		_IEN( _ICU_SWINT ) = 1;
-
-		/* Ensure the software interrupt is clear. */
-		_IR( _ICU_SWINT ) = 0;
-
-		/* Ensure the software interrupt is set to the kernel priority. */
-		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
-		/* Start the first task. */
-		prvStartFirstTask();
-	}
-
-	/* Execution should not reach here as the tasks are now running!
-	prvSetupTimerInterrupt() is called here to prevent the compiler outputting
-	a warning about a statically declared function not being referenced in the
-	case that the application writer has provided their own tick interrupt
-	configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
-	their own routine will be called in place of prvSetupTimerInterrupt()). */
-	prvSetupTimerInterrupt();
-
-	/* Should not get here. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( pxCurrentTCB == NULL );
-}
-/*-----------------------------------------------------------*/
-
-static void prvStartFirstTask( void )
-{
-	__asm volatile
-	(
-		/* When starting the scheduler there is nothing that needs moving to the
-		interrupt stack because the function is not called from an interrupt.
-		Just ensure the current stack is the user stack. */
-		"SETPSW		U						\n" \
-
-		/* Obtain the location of the stack associated with which ever task
-		pxCurrentTCB is currently pointing to. */
-		"MOV.L		#_pxCurrentTCB, R15		\n" \
-		"MOV.L		[R15], R15				\n" \
-		"MOV.L		[R15], R0				\n" \
-
-		/* Restore the registers from the stack of the task pointed to by
-		pxCurrentTCB. */
-	    "POP		R15						\n" \
-
-		/* Accumulator low 32 bits. */
-	    "MVTACLO	R15 					\n" \
-	    "POP		R15						\n" \
-
-		/* Accumulator high 32 bits. */
-	    "MVTACHI	R15 					\n" \
-
-		/* R1 to R15 - R0 is not included as it is the SP. */
-	    "POPM		R1-R15 					\n" \
-
-		/* This pops the remaining registers. */
-	    "RTE								\n" \
-	    "NOP								\n" \
-	    "NOP								\n"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortSoftwareInterruptISR( void )
-{
-	__asm volatile
-	(
-		/* Re-enable interrupts. */
-		"SETPSW		I							\n" \
-
-		/* Move the data that was automatically pushed onto the interrupt stack when
-		the interrupt occurred from the interrupt stack to the user stack.
-
-		R15 is saved before it is clobbered. */
-		"PUSH.L		R15							\n" \
-
-		/* Read the user stack pointer. */
-		"MVFC		USP, R15					\n" \
-
-		/* Move the address down to the data being moved. */
-		"SUB		#12, R15					\n" \
-		"MVTC		R15, USP					\n" \
-
-		/* Copy the data across, R15, then PC, then PSW. */
-		"MOV.L		[ R0 ], [ R15 ]				\n" \
-		"MOV.L 		4[ R0 ], 4[ R15 ]			\n" \
-		"MOV.L		8[ R0 ], 8[ R15 ]			\n" \
-
-		/* Move the interrupt stack pointer to its new correct position. */
-		"ADD		#12, R0						\n" \
-
-		/* All the rest of the registers are saved directly to the user stack. */
-		"SETPSW		U							\n" \
-
-		/* Save the rest of the general registers (R15 has been saved already). */
-		"PUSHM		R1-R14						\n" \
-
-		/* Save the accumulator. */
-		"MVFACHI 	R15							\n" \
-		"PUSH.L		R15							\n" \
-
-		/* Middle word. */
-		"MVFACMI	R15							\n" \
-
-		/* Shifted left as it is restored to the low order word. */
-		"SHLL		#16, R15					\n" \
-		"PUSH.L		R15							\n" \
-
-		/* Save the stack pointer to the TCB. */
-		"MOV.L		#_pxCurrentTCB, R15			\n" \
-		"MOV.L		[ R15 ], R15				\n" \
-		"MOV.L		R0, [ R15 ]					\n" \
-
-		/* Ensure the interrupt mask is set to the syscall priority while the kernel
-		structures are being accessed. */
-		"MVTIPL		%0 							\n" \
-
-		/* Select the next task to run. */
-		"BSR.A		_vTaskSwitchContext			\n" \
-
-		/* Reset the interrupt mask as no more data structure access is required. */
-		"MVTIPL		%1							\n" \
-
-		/* Load the stack pointer of the task that is now selected as the Running
-		state task from its TCB. */
-		"MOV.L		#_pxCurrentTCB,R15			\n" \
-		"MOV.L		[ R15 ], R15				\n" \
-		"MOV.L		[ R15 ], R0					\n" \
-
-		/* Restore the context of the new task.  The PSW (Program Status Word) and
-		PC will be popped by the RTE instruction. */
-		"POP		R15							\n" \
-		"MVTACLO 	R15							\n" \
-		"POP		R15							\n" \
-		"MVTACHI 	R15							\n" \
-		"POPM		R1-R15						\n" \
-		"RTE									\n" \
-		"NOP									\n" \
-		"NOP									  "
-		:: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vPortTickISR( void )
-{
-	/* Re-enabled interrupts. */
-	__asm volatile( "SETPSW	I" );
-
-	/* Increment the tick, and perform any processing the new tick value
-	necessitates.  Ensure IPL is at the max syscall value first. */
-	portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			taskYIELD();
-		}
-	}
-	portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
-
-	#if configUSE_TICKLESS_IDLE == 1
-	{
-		/* The CPU woke because of a tick. */
-		ulTickFlag = pdTRUE;
-
-		/* If this is the first tick since exiting tickless mode then the CMT
-		compare match value needs resetting. */
-		CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
-	}
-	#endif
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortGetIPL( void )
-{
-	__asm volatile
-	(
-		"MVFC	PSW, R1			\n"	\
-		"SHLR	#24, R1			\n"	\
-		"RTS					  "
-	);
-
-	/* This will never get executed, but keeps the compiler from complaining. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetIPL( uint32_t ulNewIPL )
-{
-	__asm volatile
-	(
-		"PUSH	R5				\n" \
-		"MVFC	PSW, R5			\n"	\
-		"SHLL	#24, R1			\n" \
-		"AND	#-0F000001H, R5 \n" \
-		"OR		R1, R5			\n" \
-		"MVTC	R5, PSW			\n" \
-		"POP	R5				\n" \
-		"RTS					  "
-	 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-	/* Unlock. */
-	SYSTEM.PRCR.WORD = portUNLOCK_KEY;
-
-	/* Enable CMT0. */
-	MSTP( CMT0 ) = 0;
-
-	/* Lock again. */
-	SYSTEM.PRCR.WORD = portLOCK_KEY;
-
-	/* Interrupt on compare match. */
-	CMT0.CMCR.BIT.CMIE = 1;
-
-	/* Set the compare match value. */
-	CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
-
-	/* Divide the PCLK. */
-	#if portCLOCK_DIVISOR == 512
-	{
-		CMT0.CMCR.BIT.CKS = 3;
-	}
-	#elif portCLOCK_DIVISOR == 128
-	{
-		CMT0.CMCR.BIT.CKS = 2;
-	}
-	#elif portCLOCK_DIVISOR == 32
-	{
-		CMT0.CMCR.BIT.CKS = 1;
-	}
-	#elif portCLOCK_DIVISOR == 8
-	{
-		CMT0.CMCR.BIT.CKS = 0;
-	}
-	#else
-	{
-		#error Invalid portCLOCK_DIVISOR setting
-	}
-	#endif
-
-	/* Enable the interrupt... */
-	_IEN( _CMT0_CMI0 ) = 1;
-
-	/* ...and set its priority to the application defined kernel priority. */
-	_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
-
-	/* Start the timer. */
-	CMT.CMSTR0.BIT.STR0 = 1;
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_TICKLESS_IDLE == 1
-
-	static void prvSleep( TickType_t xExpectedIdleTime )
-	{
-		/* Allow the application to define some pre-sleep processing. */
-		configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
-
-		/* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
-		means the application defined code has already executed the WAIT
-		instruction. */
-		if( xExpectedIdleTime > 0 )
-		{
-			__asm volatile( "WAIT" );
-		}
-
-		/* Allow the application to define some post sleep processing. */
-		configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-#if configUSE_TICKLESS_IDLE == 1
-
-	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
-	eSleepModeStatus eSleepAction;
-
-		/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
-
-		/* Make sure the CMT reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Calculate the reload value required to wait xExpectedIdleTime tick
-		periods. */
-		ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
-		if( ulMatchValue > ulStoppedTimerCompensation )
-		{
-			/* Compensate for the fact that the CMT is going to be stopped
-			momentarily. */
-			ulMatchValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Stop the CMT momentarily.  The time the CMT is stopped for is
-		accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		CMT.CMSTR0.BIT.STR0 = 0;
-		while( CMT.CMSTR0.BIT.STR0 == 1 )
-		{
-			/* Nothing to do here. */
-		}
-
-		/* Critical section using the global interrupt bit as the i bit is
-		automatically reset by the WAIT instruction. */
-		__asm volatile( "CLRPSW i" );
-
-		/* The tick flag is set to false before sleeping.  If it is true when
-		sleep mode is exited then sleep mode was probably exited because the
-		tick was suppressed for the entire xExpectedIdleTime period. */
-		ulTickFlag = pdFALSE;
-
-		/* If a context switch is pending then abandon the low power entry as
-		the context switch might have been pended by an external interrupt that
-		requires processing. */
-		eSleepAction = eTaskConfirmSleepModeStatus();
-		if( eSleepAction == eAbortSleep )
-		{
-			/* Restart tick. */
-			CMT.CMSTR0.BIT.STR0 = 1;
-			__asm volatile( "SETPSW i" );
-		}
-		else if( eSleepAction == eNoTasksWaitingTimeout )
-		{
-		    /* Protection off. */
-		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
-
-		    /* Ready for software standby with all clocks stopped. */
-			SYSTEM.SBYCR.BIT.SSBY = 1;
-
-		    /* Protection on. */
-		    SYSTEM.PRCR.WORD = portLOCK_KEY;
-
-			/* Sleep until something happens.  Calling prvSleep() will
-			automatically reset the i bit in the PSW. */
-			prvSleep( xExpectedIdleTime );
-
-			/* Restart the CMT. */
-			CMT.CMSTR0.BIT.STR0 = 1;
-		}
-		else
-		{
-		    /* Protection off. */
-		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
-
-		    /* Ready for deep sleep mode. */
-			SYSTEM.MSTPCRC.BIT.DSLPE = 1;
-			SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
-			SYSTEM.SBYCR.BIT.SSBY = 0;
-
-		    /* Protection on. */
-		    SYSTEM.PRCR.WORD = portLOCK_KEY;
-
-		    /* Adjust the match value to take into account that the current
-			time slice is already partially complete. */
-			ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
-			CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-
-			/* Restart the CMT to count up to the new match value. */
-			CMT0.CMCNT = 0;
-			CMT.CMSTR0.BIT.STR0 = 1;
-
-			/* Sleep until something happens.  Calling prvSleep() will
-			automatically reset the i bit in the PSW. */
-			prvSleep( xExpectedIdleTime );
-
-			/* Stop CMT.  Again, the time the SysTick is stopped for is
-			accounted for as best it can be, but using the tickless mode will
-			inevitably result in some tiny drift of the time maintained by the
-			kernel with	respect to calendar time. */
-			CMT.CMSTR0.BIT.STR0 = 0;
-			while( CMT.CMSTR0.BIT.STR0 == 1 )
-			{
-				/* Nothing to do here. */
-			}
-
-			ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
-
-			if( ulTickFlag != pdFALSE )
-			{
-				/* The tick interrupt has already executed, although because
-				this function is called with the scheduler suspended the actual
-				tick processing will not occur until after this function has
-				exited.  Reset the match value with whatever remains of this
-				tick period. */
-				ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
-				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-
-				/* The tick interrupt handler will already have pended the tick
-				processing in the kernel.  As the pending tick will be
-				processed as soon as this function exits, the tick value
-				maintained by the tick is stepped forward by one less than the
-				time spent sleeping.  The actual stepping of the tick appears
-				later in this function. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				How	many complete tick periods passed while the processor was
-				sleeping? */
-				ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
-
-				/* The match value is set to whatever fraction of a single tick
-				period remains. */
-				ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
-				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-			}
-
-			/* Restart the CMT so it runs up to the match value.  The match value
-			will get set to the value required to generate exactly one tick period
-			the next time the CMT interrupt executes. */
-			CMT0.CMCNT = 0;
-			CMT.CMSTR0.BIT.STR0 = 1;
-
-			/* Wind the tick forward by the number of tick periods that the CPU
-			remained in a low power state. */
-			vTaskStepTick( ulCompleteTickPeriods );
-		}
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-
diff --git a/FreeRTOS/Source/portable/GCC/RX100/portmacro.h b/FreeRTOS/Source/portable/GCC/RX100/portmacro.h
deleted file mode 100755
index 7365139..0000000
--- a/FreeRTOS/Source/portable/GCC/RX100/portmacro.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
-#define portSTACK_GROWTH			-1
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()					__asm volatile( "NOP" )
-
-/* Save clobbered register, set ITU SWINR (at address 0x872E0), read the value
-back to ensure it is set before continuing, then restore the clobbered
-register. */
-#define portYIELD()							\
-	__asm volatile							\
-	(										\
-		"MOV.L #0x872E0, r5			\n\t"	\
-		"MOV.B #1, [r5]				\n\t"	\
-		"MOV.L [r5], r5				\n\t"	\
-		::: "r5"							\
-	)
-
-#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) { portYIELD(); }
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	#0" )
-#ifdef configASSERT
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-	#define portDISABLE_INTERRUPTS() 	if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#else
-	#define portDISABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()	vTaskEnterCritical()
-#define portEXIT_CRITICAL()		vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-uint32_t ulPortGetIPL( void ) __attribute__((naked));
-void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
-
-/* Tickless idle/low power functionality. */
-#if configUSE_TICKLESS_IDLE == 1
-	#ifndef portSUPPRESS_TICKS_AND_SLEEP
-		extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-		#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-	#endif
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/RX600/port.c b/FreeRTOS/Source/portable/GCC/RX600/port.c
deleted file mode 100755
index 43c098b..0000000
--- a/FreeRTOS/Source/portable/GCC/RX600/port.c
+++ /dev/null
@@ -1,358 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#include "iodefine.h"
-
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
-
-/* These macros allow a critical section to be added around the call to
-xTaskIncrementTick(), which is only ever called from interrupts at the kernel
-priority - ie a known priority.  Therefore these local macros are a slight
-optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
-which would require the old IPL to be read first and stored in a local variable. */
-#define portDISABLE_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#define portENABLE_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-static void prvStartFirstTask( void ) __attribute__((naked));
-
-/*
- * Software interrupt handler.  Performs the actual context switch (saving and
- * restoring of registers).  Written in asm code as direct register access is
- * required.
- */
-void vSoftwareInterruptISR( void ) __attribute__((naked));
-
-/*
- * The tick interrupt handler.
- */
-void vTickISR( void ) __attribute__((interrupt));
-
-/*-----------------------------------------------------------*/
-
-extern void *pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* R0 is not included as it is the stack pointer. */
-
-	*pxTopOfStack = 0x00;
-	pxTopOfStack--;
- 	*pxTopOfStack = portINITIAL_PSW;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;
-
-	/* When debugging it can be useful if every register is set to a known
-	value.  Otherwise code space can be saved by just setting the registers
-	that need to be set. */
-	#ifdef USE_FULL_REGISTER_INITIALISATION
-	{
-		pxTopOfStack--;
-		*pxTopOfStack = 0xffffffff;	/* r15. */
-		pxTopOfStack--;
-		*pxTopOfStack = 0xeeeeeeee;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xdddddddd;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xcccccccc;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xbbbbbbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaaaaaa;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x99999999;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x88888888;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x77777777;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x66666666;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x55555555;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x44444444;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x33333333;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x22222222;
-		pxTopOfStack--;
-	}
-	#else
-	{
-		pxTopOfStack -= 15;
-	}
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_FPSW;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x12345678; /* Accumulator. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x87654321; /* Accumulator. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vApplicationSetupTimerInterrupt( void );
-
-	/* Use pxCurrentTCB just so it does not get optimised away. */
-	if( pxCurrentTCB != NULL )
-	{
-		/* Call an application function to set up the timer that will generate the
-		tick interrupt.  This way the application can decide which peripheral to
-		use.  A demo application is provided to show a suitable example. */
-		vApplicationSetupTimerInterrupt();
-
-		/* Enable the software interrupt. */
-		_IEN( _ICU_SWINT ) = 1;
-
-		/* Ensure the software interrupt is clear. */
-		_IR( _ICU_SWINT ) = 0;
-
-		/* Ensure the software interrupt is set to the kernel priority. */
-		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
-		/* Start the first task. */
-		prvStartFirstTask();
-	}
-
-	/* Should not get here. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( pxCurrentTCB == NULL );
-}
-/*-----------------------------------------------------------*/
-
-static void prvStartFirstTask( void )
-{
-	__asm volatile
-	(
-		/* When starting the scheduler there is nothing that needs moving to the
-		interrupt stack because the function is not called from an interrupt.
-		Just ensure the current stack is the user stack. */
-		"SETPSW		U						\n" \
-
-		/* Obtain the location of the stack associated with which ever task
-		pxCurrentTCB is currently pointing to. */
-		"MOV.L		#_pxCurrentTCB, R15		\n" \
-		"MOV.L		[R15], R15				\n" \
-		"MOV.L		[R15], R0				\n" \
-
-		/* Restore the registers from the stack of the task pointed to by
-		pxCurrentTCB. */
-	    "POP		R15						\n" \
-
-		/* Accumulator low 32 bits. */
-	    "MVTACLO	R15 					\n" \
-	    "POP		R15						\n" \
-
-		/* Accumulator high 32 bits. */
-	    "MVTACHI	R15 					\n" \
-	    "POP		R15						\n" \
-
-		/* Floating point status word. */
-	    "MVTC		R15, FPSW 				\n" \
-
-		/* R1 to R15 - R0 is not included as it is the SP. */
-	    "POPM		R1-R15 					\n" \
-
-		/* This pops the remaining registers. */
-	    "RTE								\n" \
-	    "NOP								\n" \
-	    "NOP								\n"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vSoftwareInterruptISR( void )
-{
-	__asm volatile
-	(
-		/* Re-enable interrupts. */
-		"SETPSW		I							\n" \
-
-		/* Move the data that was automatically pushed onto the interrupt stack when
-		the interrupt occurred from the interrupt stack to the user stack.
-
-		R15 is saved before it is clobbered. */
-		"PUSH.L		R15							\n" \
-
-		/* Read the user stack pointer. */
-		"MVFC		USP, R15					\n" \
-
-		/* Move the address down to the data being moved. */
-		"SUB		#12, R15					\n" \
-		"MVTC		R15, USP					\n" \
-
-		/* Copy the data across, R15, then PC, then PSW. */
-		"MOV.L		[ R0 ], [ R15 ]				\n" \
-		"MOV.L 		4[ R0 ], 4[ R15 ]			\n" \
-		"MOV.L		8[ R0 ], 8[ R15 ]			\n" \
-
-		/* Move the interrupt stack pointer to its new correct position. */
-		"ADD		#12, R0						\n" \
-
-		/* All the rest of the registers are saved directly to the user stack. */
-		"SETPSW		U							\n" \
-
-		/* Save the rest of the general registers (R15 has been saved already). */
-		"PUSHM		R1-R14						\n" \
-
-		/* Save the FPSW and accumulator. */
-		"MVFC		FPSW, R15					\n" \
-		"PUSH.L		R15							\n" \
-		"MVFACHI 	R15							\n" \
-		"PUSH.L		R15							\n" \
-
-		/* Middle word. */
-		"MVFACMI	R15							\n" \
-
-		/* Shifted left as it is restored to the low order word. */
-		"SHLL		#16, R15					\n" \
-		"PUSH.L		R15							\n" \
-
-		/* Save the stack pointer to the TCB. */
-		"MOV.L		#_pxCurrentTCB, R15			\n" \
-		"MOV.L		[ R15 ], R15				\n" \
-		"MOV.L		R0, [ R15 ]					\n" \
-
-		/* Ensure the interrupt mask is set to the syscall priority while the kernel
-		structures are being accessed. */
-		"MVTIPL		%0 							\n" \
-
-		/* Select the next task to run. */
-		"BSR.A		_vTaskSwitchContext			\n" \
-
-		/* Reset the interrupt mask as no more data structure access is required. */
-		"MVTIPL		%1							\n" \
-
-		/* Load the stack pointer of the task that is now selected as the Running
-		state task from its TCB. */
-		"MOV.L		#_pxCurrentTCB,R15			\n" \
-		"MOV.L		[ R15 ], R15				\n" \
-		"MOV.L		[ R15 ], R0					\n" \
-
-		/* Restore the context of the new task.  The PSW (Program Status Word) and
-		PC will be popped by the RTE instruction. */
-		"POP		R15							\n" \
-		"MVTACLO 	R15							\n" \
-		"POP		R15							\n" \
-		"MVTACHI 	R15							\n" \
-		"POP		R15							\n" \
-		"MVTC		R15, FPSW					\n" \
-		"POPM		R1-R15						\n" \
-		"RTE									\n" \
-		"NOP									\n" \
-		"NOP									  "
-		:: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vTickISR( void )
-{
-	/* Re-enabled interrupts. */
-	__asm volatile( "SETPSW	I" );
-
-	/* Increment the tick, and perform any processing the new tick value
-	necessitates.  Ensure IPL is at the max syscall value first. */
-	portDISABLE_INTERRUPTS_FROM_KERNEL_ISR();
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			taskYIELD();
-		}
-	}
-	portENABLE_INTERRUPTS_FROM_KERNEL_ISR();
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortGetIPL( void )
-{
-	__asm volatile
-	(
-		"MVFC	PSW, R1			\n"	\
-		"SHLR	#24, R1			\n"	\
-		"RTS					  "
-	);
-
-	/* This will never get executed, but keeps the compiler from complaining. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetIPL( uint32_t ulNewIPL )
-{
-	__asm volatile
-	(
-		"PUSH	R5				\n" \
-		"MVFC	PSW, R5			\n"	\
-		"SHLL	#24, R1			\n" \
-		"AND	#-0F000001H, R5 \n" \
-		"OR		R1, R5			\n" \
-		"MVTC	R5, PSW			\n" \
-		"POP	R5				\n" \
-		"RTS					  "
-	 );
-}
diff --git a/FreeRTOS/Source/portable/GCC/RX600/portmacro.h b/FreeRTOS/Source/portable/GCC/RX600/portmacro.h
deleted file mode 100755
index f2cd558..0000000
--- a/FreeRTOS/Source/portable/GCC/RX600/portmacro.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
-#define portSTACK_GROWTH			-1
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()					__asm volatile( "NOP" )
-
-/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
-where portITU_SWINTR is the location of the software interrupt register
-(0x000872E0).  Don't rely on the assembler to select a register, so instead
-save and restore clobbered registers manually. */
-#define portYIELD()							\
-	__asm volatile 							\
-	(										\
-		"PUSH.L	R10					\n"		\
-		"MOV.L	#0x872E0, R10		\n"		\
-		"MOV.B	#0x1, [R10]			\n"		\
-		"MOV.L	[R10], R10			\n"		\
-		"POP	R10					\n"		\
-	)
-
-#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	#0" )
-#ifdef configASSERT
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-	#define portDISABLE_INTERRUPTS() 	if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#else
-	#define portDISABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()	vTaskEnterCritical()
-#define portEXIT_CRITICAL()		vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-uint32_t ulPortGetIPL( void ) __attribute__((naked));
-void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/RX600v2/port.c b/FreeRTOS/Source/portable/GCC/RX600v2/port.c
deleted file mode 100755
index dfd0a69..0000000
--- a/FreeRTOS/Source/portable/GCC/RX600v2/port.c
+++ /dev/null
@@ -1,407 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#include "iodefine.h"
-
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
-
-/* These macros allow a critical section to be added around the call to
-xTaskIncrementTick(), which is only ever called from interrupts at the kernel
-priority - ie a known priority.  Therefore these local macros are a slight
-optimisation compared to calling the global SET/CLEAR_INTERRUPT_MASK macros,
-which would require the old IPL to be read first and stored in a local variable. */
-#define portMASK_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#define portUNMASK_INTERRUPTS_FROM_KERNEL_ISR() 	__asm volatile ( "MVTIPL	%0" ::"i"(configKERNEL_INTERRUPT_PRIORITY) )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-static void prvStartFirstTask( void ) __attribute__((naked));
-
-/*
- * Software interrupt handler.  Performs the actual context switch (saving and
- * restoring of registers).  Written in asm code as direct register access is
- * required.
- */
-void vSoftwareInterruptISR( void ) __attribute__((naked));
-
-/*
- * The tick interrupt handler.
- */
-void vTickISR( void ) __attribute__((interrupt));
-
-/*-----------------------------------------------------------*/
-
-extern void *pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* R0 is not included as it is the stack pointer. */
-
-	*pxTopOfStack = 0x00;
-	pxTopOfStack--;
- 	*pxTopOfStack = portINITIAL_PSW;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;
-
-	/* When debugging it can be useful if every register is set to a known
-	value.  Otherwise code space can be saved by just setting the registers
-	that need to be set. */
-	#ifdef USE_FULL_REGISTER_INITIALISATION
-	{
-		pxTopOfStack--;
-		*pxTopOfStack = 0xffffffff;	/* r15. */
-		pxTopOfStack--;
-		*pxTopOfStack = 0xeeeeeeee;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xdddddddd;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xcccccccc;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xbbbbbbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaaaaaa;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x99999999;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x88888888;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x77777777;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x66666666;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x55555555;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x44444444;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x33333333;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x22222222;
-		pxTopOfStack--;
-	}
-	#else
-	{
-		pxTopOfStack -= 15;
-	}
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_FPSW;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x11111111; /* Accumulator 0. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x22222222; /* Accumulator 0. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x33333333; /* Accumulator 0. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x44444444; /* Accumulator 1. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x55555555; /* Accumulator 1. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x66666666; /* Accumulator 1. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vApplicationSetupTimerInterrupt( void );
-
-	/* Use pxCurrentTCB just so it does not get optimised away. */
-	if( pxCurrentTCB != NULL )
-	{
-		/* Call an application function to set up the timer that will generate the
-		tick interrupt.  This way the application can decide which peripheral to
-		use.  A demo application is provided to show a suitable example. */
-		vApplicationSetupTimerInterrupt();
-
-		/* Enable the software interrupt. */
-		_IEN( _ICU_SWINT ) = 1;
-
-		/* Ensure the software interrupt is clear. */
-		_IR( _ICU_SWINT ) = 0;
-
-		/* Ensure the software interrupt is set to the kernel priority. */
-		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
-		/* Start the first task. */
-		prvStartFirstTask();
-	}
-
-	/* Should not get here. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( pxCurrentTCB == NULL );
-}
-/*-----------------------------------------------------------*/
-
-static void prvStartFirstTask( void )
-{
-	__asm volatile
-	(
-		/* When starting the scheduler there is nothing that needs moving to the
-		interrupt stack because the function is not called from an interrupt.
-		Just ensure the current stack is the user stack. */
-		"SETPSW		U						\n" \
-
-		/* Obtain the location of the stack associated with which ever task
-		pxCurrentTCB is currently pointing to. */
-		"MOV.L		#_pxCurrentTCB, R15		\n" \
-		"MOV.L		[R15], R15				\n" \
-		"MOV.L		[R15], R0				\n" \
-
-		/* Restore the registers from the stack of the task pointed to by
-		pxCurrentTCB. */
-	    "POP		R15						\n" \
-
-		/* Accumulator low 32 bits. */
-	    "MVTACLO	R15, A0					\n" \
-	    "POP		R15						\n" \
-
-	    /* Accumulator high 32 bits. */
-	    "MVTACHI	R15, A0					\n" \
-	    "POP		R15						\n" \
-
-	    /* Accumulator guard. */
-	    "MVTACGU	R15, A0					\n" \
-	    "POP		R15						\n" \
-
-	    /* Accumulator low 32 bits. */
-	    "MVTACLO	R15, A1					\n" \
-	    "POP		R15						\n" \
-
-	    /* Accumulator high 32 bits. */
-	    "MVTACHI	R15, A1					\n" \
-	    "POP		R15						\n" \
-
-	    /* Accumulator guard. */
-	    "MVTACGU	R15, A1					\n" \
-	    "POP		R15						\n" \
-
-		/* Floating point status word. */
-	    "MVTC		R15, FPSW 				\n" \
-
-		/* R1 to R15 - R0 is not included as it is the SP. */
-	    "POPM		R1-R15 					\n" \
-
-		/* This pops the remaining registers. */
-	    "RTE								\n" \
-	    "NOP								\n" \
-	    "NOP								\n"
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vSoftwareInterruptISR( void )
-{
-	__asm volatile
-	(
-		/* Re-enable interrupts. */
-		"SETPSW		I							\n" \
-
-		/* Move the data that was automatically pushed onto the interrupt stack when
-		the interrupt occurred from the interrupt stack to the user stack.
-
-		R15 is saved before it is clobbered. */
-		"PUSH.L		R15							\n" \
-
-		/* Read the user stack pointer. */
-		"MVFC		USP, R15					\n" \
-
-		/* Move the address down to the data being moved. */
-		"SUB		#12, R15					\n" \
-		"MVTC		R15, USP					\n" \
-
-		/* Copy the data across, R15, then PC, then PSW. */
-		"MOV.L		[ R0 ], [ R15 ]				\n" \
-		"MOV.L 		4[ R0 ], 4[ R15 ]			\n" \
-		"MOV.L		8[ R0 ], 8[ R15 ]			\n" \
-
-		/* Move the interrupt stack pointer to its new correct position. */
-		"ADD		#12, R0						\n" \
-
-		/* All the rest of the registers are saved directly to the user stack. */
-		"SETPSW		U							\n" \
-
-		/* Save the rest of the general registers (R15 has been saved already). */
-		"PUSHM		R1-R14						\n" \
-
-		/* Save the FPSW and accumulator. */
-		"MVFC		FPSW, R15					\n" \
-		"PUSH.L		R15							\n" \
-		"MVFACGU	#0, A1, R15					\n" \
-		"PUSH.L		R15							\n" \
-		"MVFACHI	#0, A1, R15					\n" \
-		"PUSH.L		R15							\n" \
-		/* Low order word. */
-		"MVFACLO	#0, A1, R15					\n" \
-		"PUSH.L		R15							\n" \
-		"MVFACGU	#0, A0, R15					\n" \
-		"PUSH.L		R15							\n" \
-		"MVFACHI	#0, A0, R15					\n" \
-		"PUSH.L		R15							\n" \
-		/* Low order word. */
-		"MVFACLO	#0, A0, R15					\n" \
-		"PUSH.L		R15							\n" \
-
-		/* Save the stack pointer to the TCB. */
-		"MOV.L		#_pxCurrentTCB, R15			\n" \
-		"MOV.L		[ R15 ], R15				\n" \
-		"MOV.L		R0, [ R15 ]					\n" \
-
-		/* Ensure the interrupt mask is set to the syscall priority while the kernel
-		structures are being accessed. */
-		"MVTIPL		%0 							\n" \
-
-		/* Select the next task to run. */
-		"BSR.A		_vTaskSwitchContext			\n" \
-
-		/* Reset the interrupt mask as no more data structure access is required. */
-		"MVTIPL		%1							\n" \
-
-		/* Load the stack pointer of the task that is now selected as the Running
-		state task from its TCB. */
-		"MOV.L		#_pxCurrentTCB,R15			\n" \
-		"MOV.L		[ R15 ], R15				\n" \
-		"MOV.L		[ R15 ], R0					\n" \
-
-		/* Restore the context of the new task.  The PSW (Program Status Word) and
-		PC will be popped by the RTE instruction. */
-	    "POP		R15							\n" \
-
-	    /* Accumulator low 32 bits. */
-	    "MVTACLO	R15, A0						\n" \
-	    "POP		R15							\n" \
-
-	    /* Accumulator high 32 bits. */
-	    "MVTACHI	R15, A0						\n" \
-	    "POP		R15							\n" \
-
-	    /* Accumulator guard. */
-	    "MVTACGU	R15, A0						\n" \
-	    "POP		R15							\n" \
-
-	    /* Accumulator low 32 bits. */
-	    "MVTACLO	R15, A1						\n" \
-	    "POP		R15							\n" \
-
-	    /* Accumulator high 32 bits. */
-	    "MVTACHI	R15, A1						\n" \
-	    "POP		R15							\n" \
-
-	    /* Accumulator guard. */
-	    "MVTACGU	R15, A1						\n" \
-		"POP		R15							\n" \
-		"MVTC		R15, FPSW					\n" \
-		"POPM		R1-R15						\n" \
-		"RTE									\n" \
-		"NOP									\n" \
-		"NOP									  "
-		:: "i"(configMAX_SYSCALL_INTERRUPT_PRIORITY), "i"(configKERNEL_INTERRUPT_PRIORITY)
-	);
-}
-/*-----------------------------------------------------------*/
-
-void vTickISR( void )
-{
-	/* Re-enabled interrupts. */
-	__asm volatile( "SETPSW	I" );
-
-	/* Increment the tick, and perform any processing the new tick value
-	necessitates.  Ensure IPL is at the max syscall value first. */
-	portMASK_INTERRUPTS_FROM_KERNEL_ISR();
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			taskYIELD();
-		}
-	}
-	portUNMASK_INTERRUPTS_FROM_KERNEL_ISR();
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortGetIPL( void )
-{
-	__asm volatile
-	(
-		"MVFC	PSW, R1			\n"	\
-		"SHLR	#24, R1			\n"	\
-		"RTS					  "
-	);
-
-	/* This will never get executed, but keeps the compiler from complaining. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetIPL( uint32_t ulNewIPL )
-{
-	__asm volatile
-	(
-		"PUSH	R5				\n" \
-		"MVFC	PSW, R5			\n"	\
-		"SHLL	#24, R1			\n" \
-		"AND	#-0F000001H, R5 \n" \
-		"OR		R1, R5			\n" \
-		"MVTC	R5, PSW			\n" \
-		"POP	R5				\n" \
-		"RTS					  "
-	 );
-}
diff --git a/FreeRTOS/Source/portable/GCC/RX600v2/portmacro.h b/FreeRTOS/Source/portable/GCC/RX600v2/portmacro.h
deleted file mode 100755
index f2cd558..0000000
--- a/FreeRTOS/Source/portable/GCC/RX600v2/portmacro.h
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
-#define portSTACK_GROWTH			-1
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()					__asm volatile( "NOP" )
-
-/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
-where portITU_SWINTR is the location of the software interrupt register
-(0x000872E0).  Don't rely on the assembler to select a register, so instead
-save and restore clobbered registers manually. */
-#define portYIELD()							\
-	__asm volatile 							\
-	(										\
-		"PUSH.L	R10					\n"		\
-		"MOV.L	#0x872E0, R10		\n"		\
-		"MOV.B	#0x1, [R10]			\n"		\
-		"MOV.L	[R10], R10			\n"		\
-		"POP	R10					\n"		\
-	)
-
-#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	#0" )
-#ifdef configASSERT
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( ulPortGetIPL() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-	#define portDISABLE_INTERRUPTS() 	if( ulPortGetIPL() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#else
-	#define portDISABLE_INTERRUPTS() 	__asm volatile ( "MVTIPL	%0" ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY) )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()	vTaskEnterCritical()
-#define portEXIT_CRITICAL()		vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-uint32_t ulPortGetIPL( void ) __attribute__((naked));
-void vPortSetIPL( uint32_t ulNewIPL ) __attribute__((naked));
-#define portSET_INTERRUPT_MASK_FROM_ISR() ulPortGetIPL(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) vPortSetIPL( uxSavedInterruptStatus )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/STR75x/port.c b/FreeRTOS/Source/portable/GCC/STR75x/port.c
deleted file mode 100755
index f085ace..0000000
--- a/FreeRTOS/Source/portable/GCC/STR75x/port.c
+++ /dev/null
@@ -1,197 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ST STR75x ARM7
- * port.
- *----------------------------------------------------------*/
-
-/* Library includes. */
-#include "75x_tb.h"
-#include "75x_eic.h"
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
-
-/* Prescale used on the timer clock when calculating the tick period. */
-#define portPRESCALE 20
-
-
-/*-----------------------------------------------------------*/
-
-/* Setup the TB to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
-	pxOriginalTOS = pxTopOfStack;
-
-	/* To ensure asserts in tasks.c don't fail, although in this case the assert
-	is not really required. */
-	pxTopOfStack--;
-
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* First on the stack is the return address - which in this case is the
-	start of the task.  The offset is added to make the return address appear
-	as it would within an IRQ ISR. */
-	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;	
-
-	/* When the task starts is will expect to find the function parameter in
-	R0. */
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The status register is set for system mode, with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	#ifdef THUMB_INTERWORK
-	{
-		/* We want the task to start in thumb mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-	#endif
-
-	pxTopOfStack--;
-
-	/* Interrupt flags cannot always be stored on the stack and will
-	instead be stored in a variable, which is then saved as part of the
-	tasks context. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-
-	return pxTopOfStack;	
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortISRStartFirstTask( void );
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task. */
-	vPortISRStartFirstTask();	
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the ARM port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-EIC_IRQInitTypeDef  EIC_IRQInitStructure;	
-TB_InitTypeDef      TB_InitStructure;
-
-	/* Setup the EIC for the TB. */
-	EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
-	EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
-	EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
-	EIC_IRQInit(&EIC_IRQInitStructure);
-	
-	/* Setup the TB for the generation of the tick interrupt. */
-	TB_InitStructure.TB_Mode = TB_Mode_Timing;
-	TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
-	TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
-	TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
-	TB_Init(&TB_InitStructure);
-	
-	/* Enable TB Update interrupt */
-	TB_ITConfig(TB_IT_Update, ENABLE);
-
-	/* Clear TB Update interrupt pending bit */
-	TB_ClearITPendingBit(TB_IT_Update);
-
-	/* Enable TB */
-	TB_Cmd(ENABLE);
-}
-/*-----------------------------------------------------------*/
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/STR75x/portISR.c b/FreeRTOS/Source/portable/GCC/STR75x/portISR.c
deleted file mode 100755
index 92b6884..0000000
--- a/FreeRTOS/Source/portable/GCC/STR75x/portISR.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*-----------------------------------------------------------
- * Components that can be compiled to either ARM or THUMB mode are
- * contained in port.c  The ISR routines, which can only be compiled
- * to ARM mode, are contained in this file.
- *----------------------------------------------------------*/
-
-/*
-*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
-
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/*-----------------------------------------------------------*/
-
-/* 
- * The scheduler can only be started from ARM mode, hence the inclusion of this
- * function here.
- */
-void vPortISRStartFirstTask( void );
-/*-----------------------------------------------------------*/
-
-void vPortISRStartFirstTask( void )
-{
-	/* Simply start the scheduler.  This is included here as it can only be
-	called from ARM mode. */
-	asm volatile (														\
-	"LDR		R0, =pxCurrentTCB								\n\t"	\
-	"LDR		R0, [R0]										\n\t"	\
-	"LDR		LR, [R0]										\n\t"	\
-																		\
-	/* The critical nesting depth is the first item on the stack. */	\
-	/* Load it into the ulCriticalNesting variable. */					\
-	"LDR		R0, =ulCriticalNesting							\n\t"	\
-	"LDMFD	LR!, {R1}											\n\t"	\
-	"STR		R1, [R0]										\n\t"	\
-																		\
-	/* Get the SPSR from the stack. */									\
-	"LDMFD	LR!, {R0}											\n\t"	\
-	"MSR		SPSR, R0										\n\t"	\
-																		\
-	/* Restore all system mode registers for the task. */				\
-	"LDMFD	LR, {R0-R14}^										\n\t"	\
-	"NOP														\n\t"	\
-																		\
-	/* Restore the return address. */									\
-	"LDR		LR, [LR, #+60]									\n\t"	\
-																		\
-	/* And return - correcting the offset in the LR to obtain the */	\
-	/* correct address. */												\
-	"SUBS PC, LR, #4											\n\t"	\
-	);																	
-}
-/*-----------------------------------------------------------*/
-
-void vPortTickISR( void )
-{
-	/* Increment the RTOS tick count, then look for the highest priority 
-	task that is ready to run. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{	
-		vTaskSwitchContext();
-	}
-			
-	/* Ready for the next interrupt. */
-	TB_ClearITPendingBit( TB_IT_Update );	
-}
-
-/*-----------------------------------------------------------*/
-
-/*
- * The interrupt management utilities can only be called from ARM mode.  When
- * THUMB_INTERWORK is defined the utilities are defined as functions here to
- * ensure a switch to ARM mode.  When THUMB_INTERWORK is not defined then
- * the utilities are defined as macros in portmacro.h - as per other ports.
- */
-#ifdef THUMB_INTERWORK
-
-	void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-	void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
-	void vPortDisableInterruptsFromThumb( void )
-	{
-		asm volatile ( 
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/
-			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.						*/
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/
-			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
-			"BX		R14" );					/* Return back to thumb.					*/
-	}
-			
-	void vPortEnableInterruptsFromThumb( void )
-	{
-		asm volatile ( 
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.									*/	
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.								*/	
-			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.							*/	
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.				*/	
-			"LDMIA	SP!, {R0}		\n\t"	/* Pop R0.									*/
-			"BX		R14" );					/* Return back to thumb.					*/
-	}
-
-#endif /* THUMB_INTERWORK */
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
-	asm volatile ( 
-		"STMDB	SP!, {R0}			\n\t"	/* Push R0.								*/
-		"MRS	R0, CPSR			\n\t"	/* Get CPSR.							*/
-		"ORR	R0, R0, #0xC0		\n\t"	/* Disable IRQ, FIQ.					*/
-		"MSR	CPSR, R0			\n\t"	/* Write back modified value.			*/
-		"LDMIA	SP!, {R0}" );				/* Pop R0.								*/
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed 
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as we are leaving a critical section. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then interrupts should be
-		re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Enable interrupts as per portEXIT_CRITICAL().					*/
-			asm volatile ( 
-				"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	
-				"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	
-				"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	
-				"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	
-				"LDMIA	SP!, {R0}" );			/* Pop R0.						*/
-		}
-	}
-}
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/GCC/STR75x/portmacro.h b/FreeRTOS/Source/portable/GCC/STR75x/portmacro.h
deleted file mode 100755
index 26a777a..0000000
--- a/FreeRTOS/Source/portable/GCC/STR75x/portmacro.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-#define portYIELD()					asm volatile ( "SWI 0" )
-#define portNOP()					asm volatile ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-/*
- * The interrupt management utilities can only be called from ARM mode.  When
- * THUMB_INTERWORK is defined the utilities are defined as functions in
- * portISR.c to ensure a switch to ARM mode.  When THUMB_INTERWORK is not
- * defined then the utilities are defined as macros here - as per other ports.
- */
-
-#ifdef THUMB_INTERWORK
-
-	extern void vPortDisableInterruptsFromThumb( void ) __attribute__ ((naked));
-	extern void vPortEnableInterruptsFromThumb( void ) __attribute__ ((naked));
-
-	#define portDISABLE_INTERRUPTS()	vPortDisableInterruptsFromThumb()
-	#define portENABLE_INTERRUPTS()		vPortEnableInterruptsFromThumb()
-
-#else
-
-	#define portDISABLE_INTERRUPTS()											\
-		asm volatile (															\
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
-			"ORR	R0, R0, #0xC0	\n\t"	/* Disable IRQ, FIQ.			*/	\
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
-			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
-
-	#define portENABLE_INTERRUPTS()												\
-		asm volatile (															\
-			"STMDB	SP!, {R0}		\n\t"	/* Push R0.						*/	\
-			"MRS	R0, CPSR		\n\t"	/* Get CPSR.					*/	\
-			"BIC	R0, R0, #0xC0	\n\t"	/* Enable IRQ, FIQ.				*/	\
-			"MSR	CPSR, R0		\n\t"	/* Write back modified value.	*/	\
-			"LDMIA	SP!, {R0}			" )	/* Pop R0.						*/
-
-#endif /* THUMB_INTERWORK */
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL()		vPortEnterCritical();
-#define portEXIT_CRITICAL()			vPortExitCritical();
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
-{													\
-extern void vTaskSwitchContext( void );				\
-													\
-	if( xSwitchRequired ) 							\
-	{												\
-		vTaskSwitchContext();						\
-	}												\
-}
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
-
diff --git a/FreeRTOS/Source/portable/GCC/TriCore_1782/port.c b/FreeRTOS/Source/portable/GCC/TriCore_1782/port.c
deleted file mode 100755
index 91661c3..0000000
--- a/FreeRTOS/Source/portable/GCC/TriCore_1782/port.c
+++ /dev/null
@@ -1,541 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-#include 
-
-/* TriCore specific includes. */
-#include 
-#include 
-#include 
-#include 
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "list.h"
-
-#if configCHECK_FOR_STACK_OVERFLOW > 0
-	#error "Stack checking cannot be used with this port, as, unlike most ports, the pxTopOfStack member of the TCB is consumed CSA.  CSA starvation, loosely equivalent to stack overflow, will result in a trap exception."
-	/* The stack pointer is accessible using portCSA_TO_ADDRESS( portCSA_TO_ADDRESS( pxCurrentTCB->pxTopOfStack )[ 0 ] )[ 2 ]; */
-#endif /* configCHECK_FOR_STACK_OVERFLOW */
-
-
-/*-----------------------------------------------------------*/
-
-/* System register Definitions. */
-#define portSYSTEM_PROGRAM_STATUS_WORD					( 0x000008FFUL ) /* Supervisor Mode, MPU Register Set 0 and Call Depth Counting disabled. */
-#define portINITIAL_PRIVILEGED_PROGRAM_STATUS_WORD		( 0x000014FFUL ) /* IO Level 1, MPU Register Set 1 and Call Depth Counting disabled. */
-#define portINITIAL_UNPRIVILEGED_PROGRAM_STATUS_WORD	( 0x000010FFUL ) /* IO Level 0, MPU Register Set 1 and Call Depth Counting disabled. */
-#define portINITIAL_PCXI_UPPER_CONTEXT_WORD				( 0x00C00000UL ) /* The lower 20 bits identify the CSA address. */
-#define portINITIAL_SYSCON								( 0x00000000UL ) /* MPU Disable. */
-
-/* CSA manipulation macros. */
-#define portCSA_FCX_MASK					( 0x000FFFFFUL )
-
-/* OS Interrupt and Trap mechanisms. */
-#define portRESTORE_PSW_MASK				( ~( 0x000000FFUL ) )
-#define portSYSCALL_TRAP					( 6 )
-
-/* Each CSA contains 16 words of data. */
-#define portNUM_WORDS_IN_CSA				( 16 )
-
-/* The interrupt enable bit in the PCP_SRC register. */
-#define portENABLE_CPU_INTERRUPT 			( 1U << 12U )
-/*-----------------------------------------------------------*/
-
-/*
- * Perform any hardware configuration necessary to generate the tick interrupt.
- */
-static void prvSystemTickHandler( int ) __attribute__((longcall));
-static void prvSetupTimerInterrupt( void );
-
-/*
- * Trap handler for yields.
- */
-static void prvTrapYield( int iTrapIdentification );
-
-/*
- * Priority 1 interrupt handler for yields pended from an interrupt.
- */
-static void prvInterruptYield( int iTrapIdentification );
-
-/*-----------------------------------------------------------*/
-
-/* This reference is required by the save/restore context macros. */
-extern volatile uint32_t *pxCurrentTCB;
-
-/* Precalculate the compare match value at compile time. */
-static const uint32_t ulCompareMatchValue = ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ );
-
-/*-----------------------------------------------------------*/
-
-StackType_t *pxPortInitialiseStack( StackType_t * pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint32_t *pulUpperCSA = NULL;
-uint32_t *pulLowerCSA = NULL;
-
-	/* 16 Address Registers (4 Address registers are global), 16 Data
-	Registers, and 3 System Registers.
-
-	There are 3 registers that track the CSAs.
-		FCX points to the head of globally free set of CSAs.
-		PCX for the task needs to point to Lower->Upper->NULL arrangement.
-		LCX points to the last free CSA so that corrective action can be taken.
-
-	Need two CSAs to store the context of a task.
-		The upper context contains D8-D15, A10-A15, PSW and PCXI->NULL.
-		The lower context contains D0-D7, A2-A7, A11 and PCXI->UpperContext.
-		The pxCurrentTCB->pxTopOfStack points to the Lower Context RSLCX matching the initial BISR.
-		The Lower Context points to the Upper Context ready for the return from the interrupt handler.
-
-	 The Real stack pointer for the task is stored in the A10 which is restored
-	 with the upper context. */
-
-	/* Have to disable interrupts here because the CSAs are going to be
-	manipulated. */
-	portENTER_CRITICAL();
-	{
-		/* DSync to ensure that buffering is not a problem. */
-		_dsync();
-
-		/* Consume two free CSAs. */
-		pulLowerCSA = portCSA_TO_ADDRESS( __MFCR( $FCX ) );
-		if( NULL != pulLowerCSA )
-		{
-			/* The Lower Links to the Upper. */
-			pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[ 0 ] );
-		}
-
-		/* Check that we have successfully reserved two CSAs. */
-		if( ( NULL != pulLowerCSA ) && ( NULL != pulUpperCSA ) )
-		{
-			/* Remove the two consumed CSAs from the free CSA list. */
-			_disable();
-			_dsync();
-			_mtcr( $FCX, pulUpperCSA[ 0 ] );
-			_isync();
-			_enable();
-		}
-		else
-		{
-			/* Simply trigger a context list depletion trap. */
-			_svlcx();
-		}
-	}
-	portEXIT_CRITICAL();
-
-	/* Clear the upper CSA. */
-	memset( pulUpperCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
-
-	/* Upper Context. */
-	pulUpperCSA[ 2 ] = ( uint32_t )pxTopOfStack;		/* A10;	Stack Return aka Stack Pointer */
-	pulUpperCSA[ 1 ] = portSYSTEM_PROGRAM_STATUS_WORD;		/* PSW	*/
-
-	/* Clear the lower CSA. */
-	memset( pulLowerCSA, 0, portNUM_WORDS_IN_CSA * sizeof( uint32_t ) );
-
-	/* Lower Context. */
-	pulLowerCSA[ 8 ] = ( uint32_t ) pvParameters;		/* A4;	Address Type Parameter Register	*/
-	pulLowerCSA[ 1 ] = ( uint32_t ) pxCode;			/* A11;	Return Address aka RA */
-
-	/* PCXI pointing to the Upper context. */
-	pulLowerCSA[ 0 ] = ( portINITIAL_PCXI_UPPER_CONTEXT_WORD | ( uint32_t ) portADDRESS_TO_CSA( pulUpperCSA ) );
-
-	/* Save the link to the CSA in the top of stack. */
-	pxTopOfStack = (uint32_t * ) portADDRESS_TO_CSA( pulLowerCSA );
-
-	/* DSync to ensure that buffering is not a problem. */
-	_dsync();
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-int32_t xPortStartScheduler( void )
-{
-extern void vTrapInstallHandlers( void );
-uint32_t ulMFCR = 0UL;
-uint32_t *pulUpperCSA = NULL;
-uint32_t *pulLowerCSA = NULL;
-
-	/* Interrupts at or below configMAX_SYSCALL_INTERRUPT_PRIORITY are disable
-	when this function is called. */
-
-	/* Set-up the timer interrupt. */
-	prvSetupTimerInterrupt();
-
-	/* Install the Trap Handlers. */
-	vTrapInstallHandlers();
-
-	/* Install the Syscall Handler for yield calls. */
-	if( 0 == _install_trap_handler( portSYSCALL_TRAP, prvTrapYield ) )
-	{
-		/* Failed to install the yield handler, force an assert. */
-		configASSERT( ( ( volatile void * ) NULL ) );
-	}
-
-	/* Enable then install the priority 1 interrupt for pending context
-	switches from an ISR.  See mod_SRC in the TriCore manual. */
-	CPU_SRC0.reg = 	( portENABLE_CPU_INTERRUPT ) | ( configKERNEL_YIELD_PRIORITY );
-	if( 0 == _install_int_handler( configKERNEL_YIELD_PRIORITY, prvInterruptYield, 0 ) )
-	{
-		/* Failed to install the yield handler, force an assert. */
-		configASSERT( ( ( volatile void * ) NULL ) );
-	}
-
-	_disable();
-
-	/* Load the initial SYSCON. */
-	_mtcr( $SYSCON, portINITIAL_SYSCON );
-	_isync();
-
-	/* ENDINIT has already been applied in the 'cstart.c' code. */
-
-	/* Clear the PSW.CDC to enable the use of an RFE without it generating an
-	exception because this code is not genuinely in an exception. */
-	ulMFCR = __MFCR( $PSW );
-	ulMFCR &= portRESTORE_PSW_MASK;
-	_dsync();
-	_mtcr( $PSW, ulMFCR );
-	_isync();
-
-	/* Finally, perform the equivalent of a portRESTORE_CONTEXT() */
-	pulLowerCSA = portCSA_TO_ADDRESS( ( *pxCurrentTCB ) );
-	pulUpperCSA = portCSA_TO_ADDRESS( pulLowerCSA[0] );
-	_dsync();
-	_mtcr( $PCXI, *pxCurrentTCB );
-	_isync();
-	_nop();
-	_rslcx();
-	_nop();
-
-	/* Return to the first task selected to execute. */
-	__asm volatile( "rfe" );
-
-	/* Will not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-	/* Set-up the clock divider. */
-	unlock_wdtcon();
-	{
-		/* Wait until access to Endint protected register is enabled. */
-		while( 0 != ( WDT_CON0.reg & 0x1UL ) );
-
-		/* RMC == 1 so STM Clock == FPI */
-		STM_CLC.reg = ( 1UL << 8 );
-	}
-	lock_wdtcon();
-
-    /* Determine how many bits are used without changing other bits in the CMCON register. */
-	STM_CMCON.reg &= ~( 0x1fUL );
-	STM_CMCON.reg |= ( 0x1fUL - __CLZ( configPERIPHERAL_CLOCK_HZ / configTICK_RATE_HZ ) );
-
-	/* Take into account the current time so a tick doesn't happen immediately. */
-	STM_CMP0.reg = ulCompareMatchValue + STM_TIM0.reg;
-
-	if( 0 != _install_int_handler( configKERNEL_INTERRUPT_PRIORITY, prvSystemTickHandler, 0 ) )
-	{
-		/* Set-up the interrupt. */
-		STM_SRC0.reg = ( configKERNEL_INTERRUPT_PRIORITY | 0x00005000UL );
-
-		/* Enable the Interrupt. */
-		STM_ISRR.reg &= ~( 0x03UL );
-		STM_ISRR.reg |= 0x1UL;
-		STM_ISRR.reg &= ~( 0x07UL );
-		STM_ICR.reg |= 0x1UL;
-	}
-	else
-	{
-		/* Failed to install the Tick Interrupt. */
-		configASSERT( ( ( volatile void * ) NULL ) );
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvSystemTickHandler( int iArg )
-{
-uint32_t ulSavedInterruptMask;
-uint32_t *pxUpperCSA = NULL;
-uint32_t xUpperCSA = 0UL;
-extern volatile uint32_t *pxCurrentTCB;
-int32_t lYieldRequired;
-
-	/* Just to avoid compiler warnings about unused parameters. */
-	( void ) iArg;
-
-	/* Clear the interrupt source. */
-	STM_ISRR.reg = 1UL;
-
-	/* Reload the Compare Match register for X ticks into the future.
-
-	If critical section or interrupt nesting budgets are exceeded, then
-	it is possible that the calculated next compare match value is in the
-	past.  If this occurs (unlikely), it is possible that the resulting
-	time slippage will exceed a single tick period.  Any adverse effect of
-	this is time bounded by the fact that only the first n bits of the 56 bit
-	STM timer are being used for a compare match, so another compare match
-	will occur after an overflow in just those n bits (not the entire 56 bits).
-	As an example, if the peripheral clock is 75MHz, and the tick rate is 1KHz,
-	a missed tick could result in the next tick interrupt occurring within a
-	time that is 1.7 times the desired period.  The fact that this is greater
-	than a single tick period is an effect of using a timer that cannot be
-	automatically reset, in hardware, by the occurrence of a tick interrupt.
-	Changing the tick source to a timer that has an automatic reset on compare
-	match (such as a GPTA timer) will reduce the maximum possible additional
-	period to exactly 1 times the desired period. */
-	STM_CMP0.reg += ulCompareMatchValue;
-
-	/* Kernel API calls require Critical Sections. */
-	ulSavedInterruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the Tick. */
-		lYieldRequired = xTaskIncrementTick();
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulSavedInterruptMask );
-
-	if( lYieldRequired != pdFALSE )
-	{
-		/* Save the context of a task.
-		The upper context is automatically saved when entering a trap or interrupt.
-		Need to save the lower context as well and copy the PCXI CSA ID into
-		pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
-		TCB of a task.
-
-		Call vTaskSwitchContext to select the next task, note that this changes the
-		value of pxCurrentTCB so that it needs to be reloaded.
-
-		Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
-		that has just been switched in.
-
-		Load the context of the task.
-		Need to restore the lower context by loading the CSA from
-		pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
-		In the Interrupt handler post-amble, RSLCX will restore the lower context
-		of the task. RFE will restore the upper context of the task, jump to the
-		return address and restore the previous state of interrupts being
-		enabled/disabled. */
-		_disable();
-		_dsync();
-		xUpperCSA = __MFCR( $PCXI );
-		pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
-		*pxCurrentTCB = pxUpperCSA[ 0 ];
-		vTaskSwitchContext();
-		pxUpperCSA[ 0 ] = *pxCurrentTCB;
-		CPU_SRC0.bits.SETR = 0;
-		_isync();
-	}
-}
-/*-----------------------------------------------------------*/
-
-/*
- * When a task is deleted, it is yielded permanently until the IDLE task
- * has an opportunity to reclaim the memory that that task was using.
- * Typically, the memory used by a task is the TCB and Stack but in the
- * TriCore this includes the CSAs that were consumed as part of the Call
- * Stack. These CSAs can only be returned to the Globally Free Pool when
- * they are not part of the current Call Stack, hence, delaying the
- * reclamation until the IDLE task is freeing the task's other resources.
- * This function uses the head of the linked list of CSAs (from when the
- * task yielded for the last time) and finds the tail (the very bottom of
- * the call stack) and inserts this list at the head of the Free list,
- * attaching the existing Free List to the tail of the reclaimed call stack.
- *
- * NOTE: the IDLE task needs processing time to complete this function
- * and in heavily loaded systems, the Free CSAs may be consumed faster
- * than they can be freed assuming that tasks are being spawned and
- * deleted frequently.
- */
-void vPortReclaimCSA( uint32_t *pxTCB )
-{
-uint32_t pxHeadCSA, pxTailCSA, pxFreeCSA;
-uint32_t *pulNextCSA;
-
-	/* A pointer to the first CSA in the list of CSAs consumed by the task is
-	stored in the first element of the tasks TCB structure (where the stack
-	pointer would be on a traditional stack based architecture). */
-	pxHeadCSA = ( *pxTCB ) & portCSA_FCX_MASK;
-
-	/* Mask off everything in the CSA link field other than the address.  If
-	the	address is NULL, then the CSA is not linking anywhere and there is
-	nothing	to do. */
-	pxTailCSA = pxHeadCSA;
-
-	/* Convert the link value to contain just a raw address and store this
-	in a local variable. */
-	pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
-
-	/* Iterate over the CSAs that were consumed as part of the task.  The
-	first field in the CSA is the pointer to then next CSA.  Mask off
-	everything in the pointer to the next CSA, other than the link address.
-	If this is NULL, then the CSA currently being pointed to is the last in
-	the chain. */
-	while( 0UL != ( pulNextCSA[ 0 ] & portCSA_FCX_MASK ) )
-	{
-		/* Clear all bits of the pointer to the next in the chain, other
-		than the address bits themselves. */
-		pulNextCSA[ 0 ] = pulNextCSA[ 0 ] & portCSA_FCX_MASK;
-
-		/* Move the pointer to point to the next CSA in the list. */
-		pxTailCSA = pulNextCSA[ 0 ];
-
-		/* Update the local pointer to the CSA. */
-		pulNextCSA = portCSA_TO_ADDRESS( pxTailCSA );
-	}
-
-	_disable();
-	{
-		/* Look up the current free CSA head. */
-		_dsync();
-		pxFreeCSA = __MFCR( $FCX );
-
-		/* Join the current Free onto the Tail of what is being reclaimed. */
-		portCSA_TO_ADDRESS( pxTailCSA )[ 0 ] = pxFreeCSA;
-
-		/* Move the head of the reclaimed into the Free. */
-		_dsync();
-		_mtcr( $FCX, pxHeadCSA );
-		_isync();
-	}
-	_enable();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Nothing to do. Unlikely to want to end. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvTrapYield( int iTrapIdentification )
-{
-uint32_t *pxUpperCSA = NULL;
-uint32_t xUpperCSA = 0UL;
-extern volatile uint32_t *pxCurrentTCB;
-
-	switch( iTrapIdentification )
-	{
-		case portSYSCALL_TASK_YIELD:
-			/* Save the context of a task.
-			The upper context is automatically saved when entering a trap or interrupt.
-			Need to save the lower context as well and copy the PCXI CSA ID into
-			pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
-			TCB of a task.
-
-			Call vTaskSwitchContext to select the next task, note that this changes the
-			value of pxCurrentTCB so that it needs to be reloaded.
-
-			Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
-			that has just been switched in.
-
-			Load the context of the task.
-			Need to restore the lower context by loading the CSA from
-			pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
-			In the Interrupt handler post-amble, RSLCX will restore the lower context
-			of the task. RFE will restore the upper context of the task, jump to the
-			return address and restore the previous state of interrupts being
-			enabled/disabled. */
-			_disable();
-			_dsync();
-			xUpperCSA = __MFCR( $PCXI );
-			pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
-			*pxCurrentTCB = pxUpperCSA[ 0 ];
-			vTaskSwitchContext();
-			pxUpperCSA[ 0 ] = *pxCurrentTCB;
-			CPU_SRC0.bits.SETR = 0;
-			_isync();
-			break;
-
-		default:
-			/* Unimplemented trap called. */
-			configASSERT( ( ( volatile void * ) NULL ) );
-			break;
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvInterruptYield( int iId )
-{
-uint32_t *pxUpperCSA = NULL;
-uint32_t xUpperCSA = 0UL;
-extern volatile uint32_t *pxCurrentTCB;
-
-	/* Just to remove compiler warnings. */
-	( void ) iId;
-
-	/* Save the context of a task.
-	The upper context is automatically saved when entering a trap or interrupt.
-	Need to save the lower context as well and copy the PCXI CSA ID into
-	pxCurrentTCB->pxTopOfStack. Only Lower Context CSA IDs may be saved to the
-	TCB of a task.
-
-	Call vTaskSwitchContext to select the next task, note that this changes the
-	value of pxCurrentTCB so that it needs to be reloaded.
-
-	Call vPortSetMPURegisterSetOne to change the MPU mapping for the task
-	that has just been switched in.
-
-	Load the context of the task.
-	Need to restore the lower context by loading the CSA from
-	pxCurrentTCB->pxTopOfStack into PCXI (effectively changing the call stack).
-	In the Interrupt handler post-amble, RSLCX will restore the lower context
-	of the task. RFE will restore the upper context of the task, jump to the
-	return address and restore the previous state of interrupts being
-	enabled/disabled. */
-	_disable();
-	_dsync();
-	xUpperCSA = __MFCR( $PCXI );
-	pxUpperCSA = portCSA_TO_ADDRESS( xUpperCSA );
-	*pxCurrentTCB = pxUpperCSA[ 0 ];
-	vTaskSwitchContext();
-	pxUpperCSA[ 0 ] = *pxCurrentTCB;
-	CPU_SRC0.bits.SETR = 0;
-	_isync();
-}
-/*-----------------------------------------------------------*/
-
-uint32_t uxPortSetInterruptMaskFromISR( void )
-{
-uint32_t uxReturn = 0UL;
-
-	_disable();
-	uxReturn = __MFCR( $ICR );
-	_mtcr( $ICR, ( ( uxReturn & ~portCCPN_MASK ) | configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
-	_isync();
-	_enable();
-
-	/* Return just the interrupt mask bits. */
-	return ( uxReturn & portCCPN_MASK );
-}
-/*-----------------------------------------------------------*/
-
-
diff --git a/FreeRTOS/Source/portable/GCC/TriCore_1782/portmacro.h b/FreeRTOS/Source/portable/GCC/TriCore_1782/portmacro.h
deleted file mode 100755
index 6e335e8..0000000
--- a/FreeRTOS/Source/portable/GCC/TriCore_1782/portmacro.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* System Includes. */
-#include 
-#include 
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*---------------------------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH							( -1 )
-#define portTICK_PERIOD_MS							( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT							4
-#define portNOP()									__asm volatile( " nop " )
-#define portCRITICAL_NESTING_IN_TCB					1
-#define portRESTORE_FIRST_TASK_PRIORITY_LEVEL		1
-
-
-/*---------------------------------------------------------------------------*/
-
-typedef struct MPU_SETTINGS { uint32_t ulNotUsed; } xMPU_SETTINGS;
-
-/* Define away the instruction from the Restore Context Macro. */
-#define portPRIVILEGE_BIT							0x0UL
-
-#define portCCPN_MASK						( 0x000000FFUL )
-
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()			vTaskEnterCritical()
-#define portEXIT_CRITICAL()				vTaskExitCritical()
-/*---------------------------------------------------------------------------*/
-
-/* CSA Manipulation. */
-#define portCSA_TO_ADDRESS( pCSA )			( ( uint32_t * )( ( ( ( pCSA ) & 0x000F0000 ) << 12 ) | ( ( ( pCSA ) & 0x0000FFFF ) << 6 ) ) )
-#define portADDRESS_TO_CSA( pAddress )		( ( uint32_t )( ( ( ( (uint32_t)( pAddress ) ) & 0xF0000000 ) >> 12 ) | ( ( ( uint32_t )( pAddress ) & 0x003FFFC0 ) >> 6 ) ) )
-/*---------------------------------------------------------------------------*/
-
-#define portYIELD()								_syscall( 0 )
-/* Port Restore is implicit in the platform when the function is returned from the original PSW is automatically replaced. */
-#define portSYSCALL_TASK_YIELD					0
-#define portSYSCALL_RAISE_PRIORITY				1
-/*---------------------------------------------------------------------------*/
-
-/* Critical section management. */
-
-/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-#define portDISABLE_INTERRUPTS()	{																									\
-										uint32_t ulICR;																			\
-										_disable();																						\
-										ulICR = __MFCR( $ICR ); 		/* Get current ICR value. */										\
-										ulICR &= ~portCCPN_MASK;	/* Clear down mask bits. */											\
-										ulICR |= configMAX_SYSCALL_INTERRUPT_PRIORITY; /* Set mask bits to required priority mask. */	\
-										_mtcr( $ICR, ulICR );		/* Write back updated ICR. */										\
-										_isync();																						\
-										_enable();																						\
-									}
-
-/* Clear ICR.CCPN to allow all interrupt priorities. */
-#define portENABLE_INTERRUPTS()		{																	\
-										uint32_t ulICR;											\
-										_disable();														\
-										ulICR = __MFCR( $ICR );		/* Get current ICR value. */		\
-										ulICR &= ~portCCPN_MASK;	/* Clear down mask bits. */			\
-										_mtcr( $ICR, ulICR );		/* Write back updated ICR. */		\
-										_isync();														\
-										_enable();														\
-									}
-
-/* Set ICR.CCPN to uxSavedMaskValue. */
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedMaskValue ) 	{																						\
-																	uint32_t ulICR;																\
-																	_disable();																			\
-																	ulICR = __MFCR( $ICR );		/* Get current ICR value. */							\
-																	ulICR &= ~portCCPN_MASK;	/* Clear down mask bits. */								\
-																	ulICR |= uxSavedMaskValue;	/* Set mask bits to previously saved mask value. */		\
-																	_mtcr( $ICR, ulICR );		/* Write back updated ICR. */							\
-																	_isync();																			\
-																	_enable();																			\
-																}
-
-
-/* Set ICR.CCPN to configMAX_SYSCALL_INTERRUPT_PRIORITY */
-extern uint32_t uxPortSetInterruptMaskFromISR( void );
-#define portSET_INTERRUPT_MASK_FROM_ISR() 	uxPortSetInterruptMaskFromISR()
-
-/* Pend a priority 1 interrupt, which will take care of the context switch. */
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) 		if( xHigherPriorityTaskWoken != pdFALSE ) {	CPU_SRC0.bits.SETR = 1; _isync(); }
-
-/*---------------------------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*---------------------------------------------------------------------------*/
-
-/*
- * Port specific clean up macro required to free the CSAs that were consumed by
- * a task that has since been deleted.
- */
-void vPortReclaimCSA( uint32_t *pxTCB );
-#define portCLEAN_UP_TCB( pxTCB )		vPortReclaimCSA( ( uint32_t * ) ( pxTCB ) )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c b/FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c
deleted file mode 100755
index 530b4f0..0000000
--- a/FreeRTOS/Source/portable/GCC/TriCore_1782/porttrap.c
+++ /dev/null
@@ -1,281 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Kernel includes. */
-#include "FreeRTOS.h"
-
-/* Machine includes */
-#include 
-#include 
-#include 
-/*---------------------------------------------------------------------------*/
-
-/*
- * This reference is required by the Save/Restore Context Macros.
- */
-extern volatile uint32_t *pxCurrentTCB;
-/*-----------------------------------------------------------*/
-
-/*
- * This file contains base definitions for all of the possible traps in the system.
- * It is suggested to provide implementations for all of the traps but for
- * the time being they simply trigger a DEBUG instruction so that it is easy
- * to see what caused a particular trap.
- *
- * Trap Class 6, the SYSCALL, is used exclusively by the operating system.
- */
-
-/* The Trap Classes. */
-#define portMMU_TRAP										0
-#define portIPT_TRAP										1
-#define portIE_TRAP											2
-#define portCM_TRAP											3
-#define portSBP_TRAP										4
-#define portASSERT_TRAP										5
-#define portNMI_TRAP										7
-
-/* MMU Trap Identifications. */
-#define portTIN_MMU_VIRTUAL_ADDRESS_FILL					0
-#define portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION				1
-
-/* Internal Protection Trap Identifications. */
-#define portTIN_IPT_PRIVILIGED_INSTRUCTION					1
-#define portTIN_IPT_MEMORY_PROTECTION_READ					2
-#define portTIN_IPT_MEMORY_PROTECTION_WRITE					3
-#define portTIN_IPT_MEMORY_PROTECTION_EXECUTION				4
-#define portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS		5
-#define portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS			6
-#define portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION	7
-
-/* Instruction Error Trap Identifications. */
-#define portTIN_IE_ILLEGAL_OPCODE							1
-#define portTIN_IE_UNIMPLEMENTED_OPCODE						2
-#define portTIN_IE_INVALID_OPERAND							3
-#define portTIN_IE_DATA_ADDRESS_ALIGNMENT					4
-#define portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS				5
-
-/* Context Management Trap Identifications. */
-#define portTIN_CM_FREE_CONTEXT_LIST_DEPLETION				1
-#define portTIN_CM_CALL_DEPTH_OVERFLOW						2
-#define portTIN_CM_CALL_DEPTH_UNDEFLOW						3
-#define portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW				4
-#define portTIN_CM_CALL_STACK_UNDERFLOW						5
-#define portTIN_CM_CONTEXT_TYPE								6
-#define portTIN_CM_NESTING_ERROR							7
-
-/* System Bus and Peripherals Trap Identifications. */
-#define portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR			1
-#define portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR			2
-#define portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR			3
-#define portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR		4
-#define portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR			5
-#define portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR				6
-
-/* Assertion Trap Identifications. */
-#define portTIN_ASSERT_ARITHMETIC_OVERFLOW					1
-#define portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW			2
-
-/* Non-maskable Interrupt Trap Identifications. */
-#define portTIN_NMI_NON_MASKABLE_INTERRUPT					0
-/*---------------------------------------------------------------------------*/
-
-void vMMUTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-void vInternalProtectionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-void vInstructionErrorTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-void vContextManagementTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-void vSystemBusAndPeripheralsTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-void vAssertionTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-void vNonMaskableInterruptTrap( int iTrapIdentification ) __attribute__( ( longcall, weak ) );
-/*---------------------------------------------------------------------------*/
-
-void vTrapInstallHandlers( void )
-{
-	if( 0 == _install_trap_handler ( portMMU_TRAP, vMMUTrap ) )
-	{
-		_debug();
-	}
-
-	if( 0 == _install_trap_handler ( portIPT_TRAP, vInternalProtectionTrap ) )
-	{
-		_debug();
-	}
-
-	if( 0 == _install_trap_handler ( portIE_TRAP, vInstructionErrorTrap ) )
-	{
-		_debug();
-	}
-
-	if( 0 == _install_trap_handler ( portCM_TRAP, vContextManagementTrap ) )
-	{
-		_debug();
-	}
-
-	if( 0 == _install_trap_handler ( portSBP_TRAP, vSystemBusAndPeripheralsTrap ) )
-	{
-		_debug();
-	}
-
-	if( 0 == _install_trap_handler ( portASSERT_TRAP, vAssertionTrap ) )
-	{
-		_debug();
-	}
-
-	if( 0 == _install_trap_handler ( portNMI_TRAP, vNonMaskableInterruptTrap ) )
-	{
-		_debug();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vMMUTrap( int iTrapIdentification )
-{
-	switch( iTrapIdentification )
-	{
-	case portTIN_MMU_VIRTUAL_ADDRESS_FILL:
-	case portTIN_MMU_VIRTUAL_ADDRESS_PROTECTION:
-	default:
-		_debug();
-		break;
-	}
-}
-/*---------------------------------------------------------------------------*/
-
-void vInternalProtectionTrap( int iTrapIdentification )
-{
-	/* Deliberate fall through to default. */
-	switch( iTrapIdentification )
-	{
-		case portTIN_IPT_PRIVILIGED_INSTRUCTION:
-			/* Instruction is not allowed at current execution level, eg DISABLE at User-0. */
-
-		case portTIN_IPT_MEMORY_PROTECTION_READ:
-			/* Load word using invalid address. */
-			
-		case portTIN_IPT_MEMORY_PROTECTION_WRITE:
-			/* Store Word using invalid address. */
-			
-		case portTIN_IPT_MEMORY_PROTECTION_EXECUTION:
-			/* PC jumped to an address outside of the valid range. */
-			
-		case portTIN_IPT_MEMORY_PROTECTION_PERIPHERAL_ACCESS:
-			/* Access to a peripheral denied at current execution level. */
-			
-		case portTIN_IPT_MEMORY_PROTECTION_NULL_ADDRESS:
-			/* NULL Pointer. */
-			
-		case portTIN_IPT_MEMORY_PROTECTION_GLOBAL_REGISTER_WRITE_PROTECTION:
-			/* Tried to modify a global address pointer register. */
-			
-		default:
-		
-			pxCurrentTCB[ 0 ] = __MFCR( $PCXI );
-			_debug();
-			break;
-	}
-}
-/*---------------------------------------------------------------------------*/
-
-void vInstructionErrorTrap( int iTrapIdentification )
-{
-	/* Deliberate fall through to default. */
-	switch( iTrapIdentification )
-	{
-		case portTIN_IE_ILLEGAL_OPCODE:
-		case portTIN_IE_UNIMPLEMENTED_OPCODE:
-		case portTIN_IE_INVALID_OPERAND:
-		case portTIN_IE_DATA_ADDRESS_ALIGNMENT:
-		case portTIN_IE_INVALID_LOCAL_MEMORY_ADDRESS:
-		default:
-			_debug();
-			break;
-	}
-}
-/*---------------------------------------------------------------------------*/
-
-void vContextManagementTrap( int iTrapIdentification )
-{
-	/* Deliberate fall through to default. */
-	switch( iTrapIdentification )
-	{
-		case portTIN_CM_FREE_CONTEXT_LIST_DEPLETION:
-		case portTIN_CM_CALL_DEPTH_OVERFLOW:
-		case portTIN_CM_CALL_DEPTH_UNDEFLOW:
-		case portTIN_CM_FREE_CONTEXT_LIST_UNDERFLOW:
-		case portTIN_CM_CALL_STACK_UNDERFLOW:
-		case portTIN_CM_CONTEXT_TYPE:
-		case portTIN_CM_NESTING_ERROR:
-		default:
-			_debug();
-			break;
-	}
-}
-/*---------------------------------------------------------------------------*/
-
-void vSystemBusAndPeripheralsTrap( int iTrapIdentification )
-{
-	/* Deliberate fall through to default. */
-	switch( iTrapIdentification )
-	{
-		case portTIN_SBP_PROGRAM_FETCH_SYNCHRONOUS_ERROR:
-		case portTIN_SBP_DATA_ACCESS_SYNCHRONOUS_ERROR:
-		case portTIN_SBP_DATA_ACCESS_ASYNCHRONOUS_ERROR:
-		case portTIN_SBP_COPROCESSOR_TRAP_ASYNCHRONOUS_ERROR:
-		case portTIN_SBP_PROGRAM_MEMORY_INTEGRITY_ERROR:
-		case portTIN_SBP_DATA_MEMORY_INTEGRITY_ERROR:
-		default:
-			_debug();
-			break;
-	}
-}
-/*---------------------------------------------------------------------------*/
-
-void vAssertionTrap( int iTrapIdentification )
-{
-	/* Deliberate fall through to default. */
-	switch( iTrapIdentification )
-	{
-		case portTIN_ASSERT_ARITHMETIC_OVERFLOW:
-		case portTIN_ASSERT_STICKY_ARITHMETIC_OVERFLOW:
-		default:
-			_debug();
-			break;
-	}
-}
-/*---------------------------------------------------------------------------*/
-
-void vNonMaskableInterruptTrap( int iTrapIdentification )
-{
-	/* Deliberate fall through to default. */
-	switch( iTrapIdentification )
-	{
-		case portTIN_NMI_NON_MASKABLE_INTERRUPT:
-		default:
-			_debug();
-			break;
-	}
-}
-/*---------------------------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/GCC/nrf52840-dk/port.c b/FreeRTOS/Source/portable/GCC/nrf52840-dk/port.c
deleted file mode 100755
index 5b5b4f1..0000000
--- a/FreeRTOS/Source/portable/GCC/nrf52840-dk/port.c
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-void vPortStartFirstTask( void ) __attribute__ (( naked ));
-
-/*
- * Exception handlers.
- */
-void vPortSVCHandler( void ) __attribute__ (( naked ));
-void xPortPendSVHandler( void ) __attribute__ (( naked ));
-
-
-/*-----------------------------------------------------------*/
-
-void vPortStartFirstTask( void )
-{
-    __asm volatile(
-#if defined(__SES_ARM)
-                    " ldr r0, =_vectors \n"     /* Locate the stack using _vectors table. */
-#else
-                    " ldr r0, =__isr_vector \n" /* Locate the stack using __isr_vector table. */
-#endif
-                    " ldr r0, [r0]          \n"
-                    " msr msp, r0           \n" /* Set the msp back to the start of the stack. */
-                    " cpsie i               \n" /* Globally enable interrupts. */
-                    " cpsie f               \n"
-                    " dsb                   \n"
-                    " isb                   \n"
-#ifdef SOFTDEVICE_PRESENT
-                    /* Block kernel interrupts only (PendSV) before calling SVC */
-                    " mov r0, %0            \n"
-                    " msr basepri, r0       \n"
-#endif
-                    " svc 0                 \n" /* System call to start first task. */
-                    "                       \n"
-                    " .align 2              \n"
-#ifdef SOFTDEVICE_PRESENT
-                    ::"i"(configKERNEL_INTERRUPT_PRIORITY  << (8 - configPRIO_BITS))
-#endif
-                );
-}
-
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
-    __asm volatile (
-                    "   ldr r3, =pxCurrentTCB           \n" /* Restore the context. */
-                    "   ldr r1, [r3]                    \n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
-                    "   ldr r0, [r1]                    \n" /* The first item in pxCurrentTCB is the task top of stack. */
-                    "   ldmia r0!, {r4-r11, r14}        \n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
-                    "   msr psp, r0                     \n" /* Restore the task stack pointer. */
-                    "   isb                             \n"
-                    "   mov r0, #0                      \n"
-                    "   msr basepri, r0                 \n"
-                    "   bx r14                          \n"
-                    "                                   \n"
-                    "   .align 2                        \n"
-                );
-}
-
-/*-----------------------------------------------------------*/
-
-void xPortPendSVHandler( void )
-{
-    /* This is a naked function. */
-
-    __asm volatile
-    (
-    "   mrs r0, psp                         \n"
-    "   isb                                 \n"
-    "                                       \n"
-    "   ldr r3, =pxCurrentTCB               \n" /* Get the location of the current TCB. */
-    "   ldr r2, [r3]                        \n"
-    "                                       \n"
-    "   tst r14, #0x10                      \n" /* Is the task using the FPU context?  If so, push high vfp registers. */
-    "   it eq                               \n"
-    "   vstmdbeq r0!, {s16-s31}             \n"
-    "                                       \n"
-    "   stmdb r0!, {r4-r11, r14}            \n" /* Save the core registers. */
-    "                                       \n"
-    "   str r0, [r2]                        \n" /* Save the new top of stack into the first member of the TCB. */
-    "                                       \n"
-    "   stmdb sp!, {r3}                     \n"
-    "   mov r0, %0                          \n"
-    "   msr basepri, r0                     \n"
-    "   dsb                                 \n"
-    "   isb                                 \n"
-    "   bl vTaskSwitchContext               \n"
-    "   mov r0, #0                          \n"
-    "   msr basepri, r0                     \n"
-    "   ldmia sp!, {r3}                     \n"
-    "                                       \n"
-    "   ldr r1, [r3]                        \n" /* The first item in pxCurrentTCB is the task top of stack. */
-    "   ldr r0, [r1]                        \n"
-    "                                       \n"
-    "   ldmia r0!, {r4-r11, r14}            \n" /* Pop the core registers. */
-    "                                       \n"
-    "   tst r14, #0x10                      \n" /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
-    "   it eq                               \n"
-    "   vldmiaeq r0!, {s16-s31}             \n"
-    "                                       \n"
-    "   msr psp, r0                         \n"
-    "   isb                                 \n"
-    "                                       \n"
-    "                                       \n"
-    "   bx r14                              \n"
-    "                                       \n"
-    "   .align 2                            \n"
-    ::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY  << (8 - configPRIO_BITS))
-    );
-}
diff --git a/FreeRTOS/Source/portable/GCC/nrf52840-dk/port_cmsis.c b/FreeRTOS/Source/portable/GCC/nrf52840-dk/port_cmsis.c
deleted file mode 100755
index 2fbec43..0000000
--- a/FreeRTOS/Source/portable/GCC/nrf52840-dk/port_cmsis.c
+++ /dev/null
@@ -1,357 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#ifdef SOFTDEVICE_PRESENT
-#include "nrf_soc.h"
-#include "app_util.h"
-#include "app_util_platform.h"
-#endif
-
-#if !(__FPU_USED) && !(__LINT__)
-    #error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
-    #error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0. See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-#endif
-
-/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
-r0p1 port. */
-#define portCORTEX_M4_r0p1_ID               ( 0x410FC241UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER     ( 16 )
-#define portMAX_8_BIT_VALUE                 ( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE                 ( ( uint8_t ) 0x80 )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR                    (((xPSR_Type){.b.T = 1}).w)
-#define portINITIAL_EXEC_RETURN             ( 0xfffffffd )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case is messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-    #define portTASK_RETURN_ADDRESS configTASK_RETURN_ADDRESS
-#else
-    #define portTASK_RETURN_ADDRESS prvTaskExitError
-#endif
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0;
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-extern void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortSysTickHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-extern void vPortStartFirstTask( void );
-
-/*
- * Function to enable the VFP.
- */
-static void vPortEnableVFP( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
-     static uint8_t ucMaxSysCallPriority = 0;
-     static uint32_t ulMaxPRIGROUPValue = 0;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-    /* Simulate the stack frame as it would be created by a context switch
-    interrupt. */
-
-    /* Offset added to account for the way the MCU uses the stack on entry/exit
-    of interrupts, and to ensure alignment. */
-    pxTopOfStack--;
-
-    *pxTopOfStack = portINITIAL_XPSR;   /* xPSR */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) pxCode; /* PC */
-    pxTopOfStack--;
-    *pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;    /* LR */
-
-    /* Save code space by skipping register initialisation. */
-    pxTopOfStack -= 5;  /* R12, R3, R2 and R1. */
-    *pxTopOfStack = ( StackType_t ) pvParameters;   /* R0 */
-
-    /* A save method is being used that requires each task to maintain its
-    own exec return value. */
-    pxTopOfStack--;
-    *pxTopOfStack = portINITIAL_EXEC_RETURN;
-
-    pxTopOfStack -= 8;  /* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-    return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-    /* A function that implements a task must not exit or attempt to return to
-    its caller as there is nothing to return to.  If a task wants to exit it
-    should instead call vTaskDelete( NULL ).
-
-    Artificially force an assert() to be triggered if configASSERT() is
-    defined, then stop here so application writers can catch the error. */
-    configASSERT( uxCriticalNesting == ~0UL );
-    portDISABLE_INTERRUPTS();
-    for ( ;; );
-}
-
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-    /* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-    See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-    configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
-    /* This port is designed for nRF52, this is Cortex-M4 r0p1. */
-    configASSERT( SCB->CPUID == portCORTEX_M4_r0p1_ID );
-
-    #if ( configASSERT_DEFINED == 1 )
-    {
-        volatile uint32_t ulOriginalPriority;
-        volatile uint8_t * const pucFirstUserPriorityRegister = &NVIC->IP[0];
-        volatile uint8_t ucMaxPriorityValue;
-
-        /* Determine the maximum priority from which ISR safe FreeRTOS API
-        functions can be called.  ISR safe functions are those that end in
-        "FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-        ensure interrupt entry is as fast and simple as possible.
-
-        Save the interrupt priority value that is about to be clobbered. */
-        ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-        /* Determine the number of priority bits available.  First write to all
-        possible bits. */
-        *pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-        /* Read the value back to see how many bits stuck. */
-        ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-        /* Use the same mask on the maximum system call priority. */
-        ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-        /* Calculate the maximum acceptable priority group value for the number
-        of bits read back. */
-        ulMaxPRIGROUPValue = SCB_AIRCR_PRIGROUP_Msk >> SCB_AIRCR_PRIGROUP_Pos;
-        while ( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-        {
-            ulMaxPRIGROUPValue--;
-            ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-        }
-
-        /* Remove any bits that are more than actually existing. */
-        ulMaxPRIGROUPValue &= SCB_AIRCR_PRIGROUP_Msk >> SCB_AIRCR_PRIGROUP_Pos;
-
-        /* Restore the clobbered interrupt priority register to its original
-        value. */
-        *pucFirstUserPriorityRegister = ulOriginalPriority;
-    }
-    #endif /* conifgASSERT_DEFINED */
-
-    /* Make PendSV the lowest priority interrupts. */
-    NVIC_SetPriority(PendSV_IRQn, configKERNEL_INTERRUPT_PRIORITY);
-
-    /* Start the timer that generates the tick ISR.  Interrupts are disabled
-    here already. */
-    vPortSetupTimerInterrupt();
-
-    /* Initialise the critical nesting count ready for the first task. */
-    uxCriticalNesting = 0;
-
-    /* Ensure the VFP is enabled - it should be anyway. */
-    vPortEnableVFP();
-
-    /* Lazy save always. */
-    FPU->FPCCR |= FPU_FPCCR_ASPEN_Msk | FPU_FPCCR_LSPEN_Msk;
-
-    /* Finally this port requires SEVONPEND to be active */
-    SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
-
-    /* Start the first task. */
-    vPortStartFirstTask();
-
-    /* Should never get here as the tasks will now be executing!  Call the task
-    exit error function to prevent compiler warnings about a static function
-    not being called in the case that the application writer overrides this
-    functionality by defining configTASK_RETURN_ADDRESS. */
-    prvTaskExitError();
-
-    /* Should not get here! */
-    return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-    /* Not implemented in ports where there is nothing to return to.
-    Artificially force an assert. */
-    configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-    portDISABLE_INTERRUPTS();
-    uxCriticalNesting++;
-
-    /* This is not the interrupt safe version of the enter critical function so
-    assert() if it is being called from an interrupt context.  Only API
-    functions that end in "FromISR" can be used in an interrupt.  Only assert if
-    the critical nesting count is 1 to protect against recursive calls if the
-    assert function also uses a critical section. */
-    if ( uxCriticalNesting == 1 )
-    {
-        configASSERT( ( SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk ) == 0 );
-    }
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-    configASSERT( uxCriticalNesting );
-    uxCriticalNesting--;
-    if ( uxCriticalNesting == 0 )
-    {
-        portENABLE_INTERRUPTS();
-    }
-}
-
-/*-----------------------------------------------------------*/
-
-/* This is a naked function. */
-static void vPortEnableVFP( void )
-{
-    SCB->CPACR |= 0xf << 20;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configASSERT_DEFINED == 1 )
-
-    void vPortValidateInterruptPriority( void )
-    {
-    uint32_t ulCurrentInterrupt;
-    uint8_t ucCurrentPriority;
-    IPSR_Type ipsr;
-
-        /* Obtain the number of the currently executing interrupt. */
-        ipsr.w = __get_IPSR();
-        ulCurrentInterrupt = ipsr.b.ISR;
-
-        /* Is the interrupt number a user defined interrupt? */
-        if ( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-        {
-            /* Look up the interrupt's priority. */
-            ucCurrentPriority = NVIC->IP[ ulCurrentInterrupt - portFIRST_USER_INTERRUPT_NUMBER ];
-
-            /* The following assertion will fail if a service routine (ISR) for
-            an interrupt that has been assigned a priority above
-            configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-            function.  ISR safe FreeRTOS API functions must *only* be called
-            from interrupts that have been assigned a priority at or below
-            configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-            Numerically low interrupt priority numbers represent logically high
-            interrupt priorities, therefore the priority of the interrupt must
-            be set to a value equal to or numerically *higher* than
-            configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-            Interrupts that use the FreeRTOS API must not be left at their
-            default priority of zero as that is the highest possible priority,
-            which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-            and therefore also guaranteed to be invalid.
-
-            FreeRTOS maintains separate thread and ISR API functions to ensure
-            interrupt entry is as fast and simple as possible.
-
-            The following links provide detailed information:
-            http://www.freertos.org/RTOS-Cortex-M3-M4.html
-            http://www.freertos.org/FAQHelp.html */
-            configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-        }
-
-        /* Priority grouping:  The interrupt controller (NVIC) allows the bits
-        that define each interrupt's priority to be split between bits that
-        define the interrupt's pre-emption priority bits and bits that define
-        the interrupt's sub-priority.  For simplicity all bits must be defined
-        to be pre-emption priority bits.  The following assertion will fail if
-        this is not the case (if some bits represent a sub-priority).
-
-        If the application only uses CMSIS libraries for interrupt
-        configuration then the correct setting can be achieved on all Cortex-M
-        devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-        scheduler.  Note however that some vendor specific peripheral libraries
-        assume a non-zero priority group setting, in which cases using a value
-        of zero will result in unpredicable behaviour. */
-        configASSERT( NVIC_GetPriorityGrouping() <= ulMaxPRIGROUPValue );
-    }
-
-#endif /* configASSERT_DEFINED */
diff --git a/FreeRTOS/Source/portable/GCC/nrf52840-dk/port_cmsis_systick.c b/FreeRTOS/Source/portable/GCC/nrf52840-dk/port_cmsis_systick.c
deleted file mode 100755
index aa3ba8c..0000000
--- a/FreeRTOS/Source/portable/GCC/nrf52840-dk/port_cmsis_systick.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "app_util.h"
-
-#ifdef SOFTDEVICE_PRESENT
-#include "nrf_soc.h"
-#include "nrf_sdh.h"
-#include "app_error.h"
-#include "app_util_platform.h"
-#endif
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- * CMSIS compatible layer to menage SysTick ticking source.
- *----------------------------------------------------------*/
-
-#if configTICK_SOURCE == FREERTOS_USE_SYSTICK
-
-
-#ifndef configSYSTICK_CLOCK_HZ
-    #define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-    /* Ensure the SysTick is clocked at the same frequency as the core. */
-    #define portNVIC_SYSTICK_CLK_BIT    ( SysTick_CTRL_CLKSOURCE_Msk )
-#else
-    /* The way the SysTick is clocked is not modified in case it is not the same
-    as the core. */
-    #define portNVIC_SYSTICK_CLK_BIT    ( 0 )
-#endif
-
-
-#if configUSE_TICKLESS_IDLE == 1
-    #error SysTick port for RF52 does not support tickless idle. Use RTC mode instead.
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-    /* The SysTick runs at the lowest interrupt priority, so when this interrupt
-    executes all interrupts must be unmasked.  There is therefore no need to
-    save and then restore the interrupt mask value as its value is already
-    known. */
-    ( void ) portSET_INTERRUPT_MASK_FROM_ISR();
-    {
-        /* Increment the RTOS tick. */
-        if ( xTaskIncrementTick() != pdFALSE )
-        {
-            /* A context switch is required.  Context switching is performed in
-            the PendSV interrupt.  Pend the PendSV interrupt. */
-            SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
-            __SEV();
-        }
-    }
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( 0 );
-}
-
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-void vPortSetupTimerInterrupt( void )
-{
-    /* Set interrupt priority */
-    NVIC_SetPriority(SysTick_IRQn, configKERNEL_INTERRUPT_PRIORITY);
-    /* Configure SysTick to interrupt at the requested rate. */
-    SysTick->LOAD = ROUNDED_DIV(configSYSTICK_CLOCK_HZ, configTICK_RATE_HZ) - 1UL;
-    SysTick->CTRL = ( portNVIC_SYSTICK_CLK_BIT | SysTick_CTRL_TICKINT_Msk | SysTick_CTRL_ENABLE_Msk );
-}
-
-/*-----------------------------------------------------------*/
-
-#elif configTICK_SOURCE == FREERTOS_USE_RTC
-
-#if configUSE_16_BIT_TICKS == 1
-#error This port does not support 16 bit ticks.
-#endif
-
-#include "nrf_rtc.h"
-#include "nrf_drv_clock.h"
-
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-#if configUSE_TICKLESS_IDLE == 1
-    nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);
-#endif
-
-    BaseType_t switch_req = pdFALSE;
-    uint32_t isrstate = portSET_INTERRUPT_MASK_FROM_ISR();
-
-    uint32_t systick_counter = nrf_rtc_counter_get(portNRF_RTC_REG);
-    nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_TICK);
-
-    if (configUSE_DISABLE_TICK_AUTO_CORRECTION_DEBUG == 0)
-    {
-        /* check FreeRTOSConfig.h file for more details on configUSE_DISABLE_TICK_AUTO_CORRECTION_DEBUG */
-        TickType_t diff;
-        diff = (systick_counter - xTaskGetTickCount()) & portNRF_RTC_MAXTICKS;
-
-        /* At most 1 step if scheduler is suspended - the xTaskIncrementTick
-         * would return the tick state from the moment when suspend function was called. */
-        if ((diff > 1) && (xTaskGetSchedulerState() != taskSCHEDULER_RUNNING))
-        {
-            diff = 1;
-        }
-        while ((diff--) > 0)
-        {
-            switch_req |= xTaskIncrementTick();
-        }
-    }
-    else
-    {
-        switch_req = xTaskIncrementTick();
-    }
-
-    /* Increment the RTOS tick as usual which checks if there is a need for rescheduling */
-    if ( switch_req != pdFALSE )
-    {
-        /* A context switch is required.  Context switching is performed in
-        the PendSV interrupt.  Pend the PendSV interrupt. */
-        SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;
-        __SEV();
-    }
-
-    portCLEAR_INTERRUPT_MASK_FROM_ISR( isrstate );
-}
-
-/*
- * Setup the RTC time to generate the tick interrupts at the required
- * frequency.
- */
-void vPortSetupTimerInterrupt( void )
-{
-    /* Request LF clock */
-    nrf_drv_clock_lfclk_request(NULL);
-
-    /* Configure SysTick to interrupt at the requested rate. */
-    nrf_rtc_prescaler_set(portNRF_RTC_REG, portNRF_RTC_PRESCALER);
-    nrf_rtc_int_enable   (portNRF_RTC_REG, RTC_INTENSET_TICK_Msk);
-    nrf_rtc_task_trigger (portNRF_RTC_REG, NRF_RTC_TASK_CLEAR);
-    nrf_rtc_task_trigger (portNRF_RTC_REG, NRF_RTC_TASK_START);
-    nrf_rtc_event_enable(portNRF_RTC_REG, RTC_EVTEN_OVRFLW_Msk);
-
-    NVIC_SetPriority(portNRF_RTC_IRQn, configKERNEL_INTERRUPT_PRIORITY);
-    NVIC_EnableIRQ(portNRF_RTC_IRQn);
-}
-
-#if configUSE_TICKLESS_IDLE == 1
-
-void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-{
-    /*
-     * Implementation note:
-     *
-     * To help debugging the option configUSE_TICKLESS_IDLE_SIMPLE_DEBUG was presented.
-     * This option would make sure that even if program execution was stopped inside
-     * this function no more than expected number of ticks would be skipped.
-     *
-     * Normally RTC works all the time even if firmware execution was stopped
-     * and that may lead to skipping too much of ticks.
-     */
-    TickType_t enterTime;
-
-    /* Make sure the SysTick reload value does not overflow the counter. */
-    if ( xExpectedIdleTime > portNRF_RTC_MAXTICKS - configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
-    {
-        xExpectedIdleTime = portNRF_RTC_MAXTICKS - configEXPECTED_IDLE_TIME_BEFORE_SLEEP;
-    }
-    /* Block all the interrupts globally */
-#ifdef SOFTDEVICE_PRESENT
-    do{
-        uint8_t dummy = 0;
-        uint32_t err_code = sd_nvic_critical_region_enter(&dummy);
-        APP_ERROR_CHECK(err_code);
-    }while (0);
-#else
-    __disable_irq();
-#endif
-
-    enterTime = nrf_rtc_counter_get(portNRF_RTC_REG);
-
-    if ( eTaskConfirmSleepModeStatus() != eAbortSleep )
-    {
-        TickType_t xModifiableIdleTime;
-        TickType_t wakeupTime = (enterTime + xExpectedIdleTime) & portNRF_RTC_MAXTICKS;
-
-        /* Stop tick events */
-        nrf_rtc_int_disable(portNRF_RTC_REG, NRF_RTC_INT_TICK_MASK);
-
-        /* Configure CTC interrupt */
-        nrf_rtc_cc_set(portNRF_RTC_REG, 0, wakeupTime);
-        nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);
-        nrf_rtc_int_enable(portNRF_RTC_REG, NRF_RTC_INT_COMPARE0_MASK);
-
-        __DSB();
-
-        /* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-         * set its parameter to 0 to indicate that its implementation contains
-         * its own wait for interrupt or wait for event instruction, and so wfi
-         * should not be executed again.  However, the original expected idle
-         * time variable must remain unmodified, so a copy is taken. */
-        xModifiableIdleTime = xExpectedIdleTime;
-        configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-        if ( xModifiableIdleTime > 0 )
-        {
-#if 0  // With FreeRTOS sd_app_evt_wait increases power consumption with FreeRTOS compared to _WFE (NRFFOSDK-11174)
-#ifdef SOFTDEVICE_PRESENT
-            if (nrf_sdh_is_enabled())
-            {
-                uint32_t err_code = sd_app_evt_wait();
-                APP_ERROR_CHECK(err_code);
-            }
-            else
-#endif
-#endif // (NRFFOSDK-11174)
-            {
-                /* No SD -  we would just block interrupts globally.
-                * BASEPRI cannot be used for that because it would prevent WFE from wake up.
-                */
-                do{
-                    __WFE();
-                } while (0 == (NVIC->ISPR[0] | NVIC->ISPR[1]));
-            }
-        }
-        configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-        nrf_rtc_int_disable(portNRF_RTC_REG, NRF_RTC_INT_COMPARE0_MASK);
-        nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_COMPARE_0);
-
-        /* Correct the system ticks */
-        {
-            TickType_t diff;
-            TickType_t exitTime;
-
-            nrf_rtc_event_clear(portNRF_RTC_REG, NRF_RTC_EVENT_TICK);
-            nrf_rtc_int_enable (portNRF_RTC_REG, NRF_RTC_INT_TICK_MASK);
-
-            exitTime = nrf_rtc_counter_get(portNRF_RTC_REG);
-            diff =  (exitTime - enterTime) & portNRF_RTC_MAXTICKS;
-
-            /* It is important that we clear pending here so that our corrections are latest and in sync with tick_interrupt handler */
-            NVIC_ClearPendingIRQ(portNRF_RTC_IRQn);
-
-            if ((configUSE_TICKLESS_IDLE_SIMPLE_DEBUG) && (diff > xExpectedIdleTime))
-            {
-                diff = xExpectedIdleTime;
-            }
-
-            if (diff > 0)
-            {
-                vTaskStepTick(diff);
-            }
-        }
-    }
-#ifdef SOFTDEVICE_PRESENT
-    uint32_t err_code = sd_nvic_critical_region_exit(0);
-    APP_ERROR_CHECK(err_code);
-#else
-    __enable_irq();
-#endif
-}
-
-#endif // configUSE_TICKLESS_IDLE
-
-#else // configTICK_SOURCE
-    #error  Unsupported configTICK_SOURCE value
-#endif // configTICK_SOURCE == FREERTOS_USE_SYSTICK
diff --git a/FreeRTOS/Source/portable/GCC/nrf52840-dk/portmacro.h b/FreeRTOS/Source/portable/GCC/nrf52840-dk/portmacro.h
deleted file mode 100755
index 3458498..0000000
--- a/FreeRTOS/Source/portable/GCC/nrf52840-dk/portmacro.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#include "portmacro_cmsis.h"
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/nrf52840-dk/portmacro_cmsis.h b/FreeRTOS/Source/portable/GCC/nrf52840-dk/portmacro_cmsis.h
deleted file mode 100755
index 3d2dee5..0000000
--- a/FreeRTOS/Source/portable/GCC/nrf52840-dk/portmacro_cmsis.h
+++ /dev/null
@@ -1,187 +0,0 @@
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_CMSIS_H
-#define PORTMACRO_CMSIS_H
-#include "app_util.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if ( configUSE_16_BIT_TICKS == 1 )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS          ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT          8
-
-/* RTC register */
-#define portNRF_RTC_REG        NRF_RTC1
-/* IRQn used by the selected RTC */
-#define portNRF_RTC_IRQn       RTC1_IRQn
-/* Constants required to manipulate the NVIC. */
-#define portNRF_RTC_PRESCALER  ( (uint32_t) (ROUNDED_DIV(configSYSTICK_CLOCK_HZ, configTICK_RATE_HZ) - 1) )
-/* Maximum RTC ticks */
-#define portNRF_RTC_MAXTICKS   ((1U<<24)-1U)
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD() do                                                          \
-{                                                                               \
-    /* Set a PendSV to request a context switch. */                             \
-    SCB->ICSR = SCB_ICSR_PENDSVSET_Msk;                                         \
-    __SEV();                                                                    \
-    /* Barriers are normally not required but do ensure the code is completely  \
-    within the specified behaviour for the architecture. */                     \
-    __DSB();                                                                    \
-    __ISB();                                                                    \
-}while (0)
-
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if ( (xSwitchRequired) != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portSET_INTERRUPT_MASK_FROM_ISR()       ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    vPortSetBASEPRI(x)
-#define portDISABLE_INTERRUPTS()                vPortRaiseBASEPRI()
-#define portENABLE_INTERRUPTS()                 vPortSetBASEPRI(0)
-#define portENTER_CRITICAL()                    vPortEnterCritical()
-#define portEXIT_CRITICAL()                     vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-    /* Count leading zeros helper. */
-    #define ucPortCountLeadingZeros( bits ) __CLZ( bits )
-
-    /* Check the configuration. */
-    #if ( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-    #endif
-
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-    /*-----------------------------------------------------------*/
-
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-    void vPortValidateInterruptPriority( void );
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()  vPortValidateInterruptPriority()
-#endif
-
-/*-----------------------------------------------------------*/
-
-#define vPortSetBASEPRI( ulNewMaskValue ) __set_BASEPRI(ulNewMaskValue)
-
-/*-----------------------------------------------------------*/
-
-#define vPortRaiseBASEPRI( ) vPortSetBASEPRI(configMAX_SYSCALL_INTERRUPT_PRIORITY << (8 - configPRIO_BITS))
-
-/*-----------------------------------------------------------*/
-
-__STATIC_INLINE uint32_t ulPortRaiseBASEPRI( void )
-{
-    uint32_t ulOriginalBASEPRI = __get_BASEPRI();
-    vPortRaiseBASEPRI();
-    return ulOriginalBASEPRI;
-}
-
-/*-----------------------------------------------------------*/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_CMSIS_H */
-
diff --git a/FreeRTOS/Source/portable/GCC/stubs/port.c b/FreeRTOS/Source/portable/GCC/stubs/port.c
deleted file mode 100755
index 58c048a..0000000
--- a/FreeRTOS/Source/portable/GCC/stubs/port.c
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	( void ) pxTopOfStack;
-	( void ) pxCode;
-	( void ) pvParameters;
-
-	return ( StackType_t * ) NULL;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Do not implement. */
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/GCC/stubs/portmacro.h b/FreeRTOS/Source/portable/GCC/stubs/portmacro.h
deleted file mode 100755
index 15274c8..0000000
--- a/FreeRTOS/Source/portable/GCC/stubs/portmacro.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Type definitions. */
-#define portSTACK_TYPE	uint32_t
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			Fix Me
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD() 	Fix Me
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-#define portSET_INTERRUPT_MASK_FROM_ISR()		Fix Me
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	Fix Me
-#define portDISABLE_INTERRUPTS()				Fix Me
-#define portENABLE_INTERRUPTS()					Fix Me
-#define portENTER_CRITICAL()					Fix Me
-#define portEXIT_CRITICAL()						Fix me
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/78K0R/ISR_Support.h b/FreeRTOS/Source/portable/IAR/78K0R/ISR_Support.h
deleted file mode 100755
index 791b50e..0000000
--- a/FreeRTOS/Source/portable/IAR/78K0R/ISR_Support.h
+++ /dev/null
@@ -1,82 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-#include "FreeRTOSConfig.h"
-
-; Variables used by scheduler
-;------------------------------------------------------------------------------
-	EXTERN    pxCurrentTCB
-	EXTERN    usCriticalNesting
-
-;------------------------------------------------------------------------------
-;   portSAVE_CONTEXT MACRO
-;   Saves the context of the general purpose registers, CS and ES (only in far
-;	memory mode) registers the usCriticalNesting Value and the Stack Pointer
-;   of the active Task onto the task stack
-;------------------------------------------------------------------------------
-portSAVE_CONTEXT MACRO
-
-	PUSH      AX                    ; Save AX Register to stack.
-	PUSH      HL
-	MOV       A, CS                 ; Save CS register.
-	XCH       A, X
-	MOV       A, ES                 ; Save ES register.
-	PUSH      AX
-	PUSH      DE                    ; Save the remaining general purpose registers.
-	PUSH      BC
-	MOVW      AX, usCriticalNesting ; Save the usCriticalNesting value.
-	PUSH      AX
-	MOVW      AX, pxCurrentTCB 	    ; Save the Stack pointer.
-	MOVW      HL, AX
-	MOVW      AX, SP
-	MOVW      [HL], AX
-	ENDM
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   portRESTORE_CONTEXT MACRO
-;   Restores the task Stack Pointer then use this to restore usCriticalNesting,
-;   general purpose registers and the CS and ES (only in far memory mode)
-;   of the selected task from the task stack
-;------------------------------------------------------------------------------
-portRESTORE_CONTEXT MACRO
-	MOVW      AX, pxCurrentTCB	    ; Restore the Stack pointer.
-	MOVW      HL, AX
-	MOVW      AX, [HL]
-	MOVW      SP, AX
-	POP	      AX	                ; Restore usCriticalNesting value.
-	MOVW      usCriticalNesting, AX
-	POP	      BC                    ; Restore the necessary general purpose registers.
-	POP	      DE
-	POP       AX                    ; Restore the ES register.
-	MOV       ES, A
-	XCH       A, X                  ; Restore the CS register.
-	MOV       CS, A
-	POP       HL                    ; Restore general purpose register HL.
-	POP       AX                    ; Restore AX.
-	ENDM
-;------------------------------------------------------------------------------
diff --git a/FreeRTOS/Source/portable/IAR/78K0R/port.c b/FreeRTOS/Source/portable/IAR/78K0R/port.c
deleted file mode 100755
index 30e9631..0000000
--- a/FreeRTOS/Source/portable/IAR/78K0R/port.c
+++ /dev/null
@@ -1,225 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* The critical nesting value is initialised to a non zero value to ensure
-interrupts don't accidentally become enabled before the scheduler is started. */
-#define portINITIAL_CRITICAL_NESTING  (( uint16_t ) 10)
-
-/* Initial PSW value allocated to a newly created task.
- *   1100011000000000
- *   ||||||||-------------- Fill byte
- *   |||||||--------------- Carry Flag cleared
- *   |||||----------------- In-service priority Flags set to low level
- *   ||||------------------ Register bank Select 0 Flag cleared
- *   |||------------------- Auxiliary Carry Flag cleared
- *   ||-------------------- Register bank Select 1 Flag cleared
- *   |--------------------- Zero Flag set
- *   ---------------------- Global Interrupt Flag set (enabled)
- */
-#define portPSW		  (0xc6UL)
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/* Most ports implement critical sections by placing the interrupt flags on
-the stack before disabling interrupts.  Exiting the critical section is then
-simply a case of popping the flags from the stack.  As 78K0 IAR does not use
-a frame pointer this cannot be done as modifying the stack will clobber all
-the stack variables.  Instead each task maintains a count of the critical
-section nesting depth.  Each time a critical section is entered the count is
-incremented.  Each time a critical section is left the count is decremented -
-with interrupts only being re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as this will cause problems during the startup
-sequence. */
-volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
-/*-----------------------------------------------------------*/
-
-/*
- * Sets up the periodic ISR used for the RTOS tick.
- */
-static void prvSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint32_t *pulLocal;
-
-	#if configMEMORY_MODE == 1
-	{
-		/* Parameters are passed in on the stack, and written using a 32bit value
-		hence a space is left for the second two bytes. */
-		pxTopOfStack--;
-
-		/* Write in the parameter value. */
-		pulLocal =  ( uint32_t * ) pxTopOfStack;
-		*pulLocal = ( uint32_t ) pvParameters;
-		pxTopOfStack--;
-
-		/* These values are just spacers.  The return address of the function
-		would normally be written here. */
-		*pxTopOfStack = ( StackType_t ) 0xcdcd;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0xcdcd;
-		pxTopOfStack--;
-
-		/* The start address / PSW value is also written in as a 32bit value,
-		so leave a space for the second two bytes. */
-		pxTopOfStack--;
-	
-		/* Task function start address combined with the PSW. */
-		pulLocal = ( uint32_t * ) pxTopOfStack;
-		*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
-		pxTopOfStack--;
-
-		/* An initial value for the AX register. */
-		*pxTopOfStack = ( StackType_t ) 0x1111;
-		pxTopOfStack--;
-	}
-	#else
-	{
-		/* Task function address is written to the stack first.  As it is
-		written as a 32bit value a space is left on the stack for the second
-		two bytes. */
-		pxTopOfStack--;
-
-		/* Task function start address combined with the PSW. */
-		pulLocal = ( uint32_t * ) pxTopOfStack;
-		*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
-		pxTopOfStack--;
-
-		/* The parameter is passed in AX. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;
-		pxTopOfStack--;
-	}
-	#endif
-
-	/* An initial value for the HL register. */
-	*pxTopOfStack = ( StackType_t ) 0x2222;
-	pxTopOfStack--;
-
-	/* CS and ES registers. */
-	*pxTopOfStack = ( StackType_t ) 0x0F00;
-	pxTopOfStack--;
-
-	/* Finally the remaining general purpose registers DE and BC */
-	*pxTopOfStack = ( StackType_t ) 0xDEDE;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xBCBC;
-	pxTopOfStack--;
-
-	/* Finally the critical section nesting count is set to zero when the task
-	first starts. */
-	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
-
-	/* Return a pointer to the top of the stack we have generated so this can
-	be stored in the task control block for the task. */
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Setup the hardware to generate the tick.  Interrupts are disabled when
-	this function is called. */
-	prvSetupTimerInterrupt();
-
-	/* Restore the context of the first task that is going to run. */
-	vPortStart();
-
-	/* Should not get here as the tasks are now running! */
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the 78K0R port will get stopped.  If required simply
-	disable the tick interrupt here. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-	/* Setup channel 5 of the TAU to generate the tick interrupt. */
-
-	/* First the Timer Array Unit has to be enabled. */
-	TAU0EN = 1;
-
-	/* To configure the Timer Array Unit all Channels have to first be stopped. */
-	TT0 = 0xff;
-
-	/* Interrupt of Timer Array Unit Channel 5 is disabled to set the interrupt
-	priority. */
-	TMMK05 = 1;
-
-	/* Clear Timer Array Unit Channel 5 interrupt flag. */	
-	TMIF05 = 0;
-
-	/* Set Timer Array Unit Channel 5 interrupt priority */
-	TMPR005 = 0;
-	TMPR105 = 0;
-
-	/* Set Timer Array Unit Channel 5 Mode as interval timer. */
-	TMR05 = 0x0000;
-
-	/* Set the compare match value according to the tick rate we want. */
-	TDR05 = ( TickType_t ) ( configCPU_CLOCK_HZ / configTICK_RATE_HZ );
-
-	/* Set Timer Array Unit Channel 5 output mode */
-	TOM0 &= ~0x0020;
-
-	/* Set Timer Array Unit Channel 5 output level */	
-	TOL0 &= ~0x0020;
-
-	/* Set Timer Array Unit Channel 5 output enable */	
-	TOE0 &= ~0x0020;
-
-	/* Interrupt of Timer Array Unit Channel 5 enabled */
-	TMMK05 = 0;
-
-	/* Start Timer Array Unit Channel 5.*/
-	TS0 |= 0x0020;
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/IAR/78K0R/portasm.s26 b/FreeRTOS/Source/portable/IAR/78K0R/portasm.s26
deleted file mode 100755
index 802a71e..0000000
--- a/FreeRTOS/Source/portable/IAR/78K0R/portasm.s26
+++ /dev/null
@@ -1,138 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-#include "ISR_Support.h"
-;------------------------------------------------------------------------------
-
-#if __CORE__ != __78K0R__
-	#error "This file is only for 78K0R Devices"
-#endif
-
-#define CS                    0xFFFFC
-#define ES                    0xFFFFD
-
-; Functions implemented in this file
-;------------------------------------------------------------------------------
-	PUBLIC    vPortYield
-	PUBLIC    vPortStart
-
-; Functions used by scheduler
-;------------------------------------------------------------------------------
-	EXTERN    vTaskSwitchContext
-	EXTERN    xTaskIncrementTick
-
-; Tick ISR Prototype
-;------------------------------------------------------------------------------
-;	EXTERN    ?CL78K0R_V2_L00
-
-	PUBWEAK   `??MD_INTTM05??INTVEC 68`
-	PUBLIC    MD_INTTM05
-
-MD_INTTM05    SYMBOL "MD_INTTM05"
-`??MD_INTTM05??INTVEC 68` SYMBOL "??INTVEC 68", MD_INTTM05
-
-
-
-;------------------------------------------------------------------------------
-;   Yield to another task.  Implemented as a software interrupt.  The return
-;   address and PSW will have been saved to the stack automatically before
-;   this code runs.
-;
-;   Input:  NONE
-;
-;   Call:   CALL    vPortYield
-;
-;   Output: NONE
-;
-;------------------------------------------------------------------------------
-    RSEG CODE:CODE
-vPortYield:
-	portSAVE_CONTEXT		        ; Save the context of the current task.
-	call      vTaskSwitchContext    ; Call the scheduler to select the next task.
-	portRESTORE_CONTEXT		        ; Restore the context of the next task to run.
-	retb
-
-
-;------------------------------------------------------------------------------
-;   Restore the context of the first task that is going to run.
-;
-;   Input:  NONE
-;
-;   Call:   CALL    vPortStart
-;
-;   Output: NONE
-;
-;------------------------------------------------------------------------------
-    RSEG CODE:CODE
-vPortStart:
-	portRESTORE_CONTEXT	            ; Restore the context of whichever task the ...
-	reti					        ; An interrupt stack frame is used so the task
-                                    ; is started using a RETI instruction.
-
-;------------------------------------------------------------------------------
-;   Perform the necessary steps of the Tick Count Increment and Task Switch
-;   depending on the chosen kernel configuration
-;
-;   Input:  NONE
-;
-;   Call:   ISR
-;
-;   Output: NONE
-;
-;------------------------------------------------------------------------------
-
-MD_INTTM05:
-
-	portSAVE_CONTEXT		        ; Save the context of the current task.
-	call      xTaskIncrementTick    ; Call the timer tick function.
-#if configUSE_PREEMPTION == 1
-	call      vTaskSwitchContext    ; Call the scheduler to select the next task.
-#endif
-	portRESTORE_CONTEXT		        ; Restore the context of the next task to run.
-	reti
-
-
-
-;	REQUIRE ?CL78K0R_V2_L00
-	COMMON INTVEC:CODE:ROOT(1)      ; Set ISR location to the Interrupt vector table.
-	ORG 68
-`??MD_INTTM05??INTVEC 68`:
-	DW MD_INTTM05
-
-	COMMON INTVEC:CODE:ROOT(1)      ; Set ISR location to the Interrupt vector table.
-	ORG 126
-`??vPortYield??INTVEC 126`:
-	DW vPortYield
-
-									; Set value for the usCriticalNesting.
-	RSEG NEAR_ID:CONST:SORT:NOROOT(1)
-`?`:
-	DW 10
-
-;#endif
-
-      END
\ No newline at end of file
diff --git a/FreeRTOS/Source/portable/IAR/78K0R/portmacro.h b/FreeRTOS/Source/portable/IAR/78K0R/portmacro.h
deleted file mode 100755
index 956d50f..0000000
--- a/FreeRTOS/Source/portable/IAR/78K0R/portmacro.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-#if (configUSE_16_BIT_TICKS==1)
-	typedef unsigned int TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() __asm ( "DI" )
-#define portENABLE_INTERRUPTS()	 __asm ( "EI" )
-/*-----------------------------------------------------------*/
-
-/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
-
-#define portENTER_CRITICAL()													\
-{																				\
-extern volatile uint16_t usCriticalNesting;							\
-																				\
-	portDISABLE_INTERRUPTS();													\
-																				\
-	/* Now interrupts are disabled ulCriticalNesting can be accessed */			\
-	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
-	/* times portENTER_CRITICAL() has been called. */							\
-	usCriticalNesting++;														\
-}
-
-#define portEXIT_CRITICAL()														\
-{																				\
-extern volatile uint16_t usCriticalNesting;							\
-																				\
-	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
-	{																			\
-		/* Decrement the nesting count as we are leaving a critical section. */	\
-		usCriticalNesting--;													\
-																				\
-		/* If the nesting level has reached zero then interrupts should be */	\
-		/* re-enabled. */														\
-		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
-		{																		\
-			portENABLE_INTERRUPTS();											\
-		}																		\
-	}																			\
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-extern void vPortStart( void );
-#define portYIELD()	__asm( "BRK" )
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
-#define portNOP()	__asm( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Hardwware specifics. */
-#define portBYTE_ALIGNMENT	2
-#define portSTACK_GROWTH	( -1 )
-#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-
-static __interrupt void P0_isr   (void);
-
-/* --------------------------------------------------------------------------*/
-/* Option-bytes and security ID                                              */
-/* --------------------------------------------------------------------------*/
-#define OPT_BYTES_SIZE     4
-#define SECU_ID_SIZE       10
-#define WATCHDOG_DISABLED  0x00
-#define LVI_ENABLED        0xFE
-#define LVI_DISABLED       0xFF
-#define RESERVED_FF        0xFF
-#define OCD_DISABLED       0x04
-#define OCD_ENABLED        0x81
-#define OCD_ENABLED_ERASE  0x80
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
deleted file mode 100755
index ccb32d3..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/port.c
+++ /dev/null
@@ -1,300 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* IAR includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#ifndef configSETUP_TICK_INTERRUPT
-	#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.  A default that uses the PIT is provided in the official demo application.
-#endif
-
-#ifndef configCLEAR_TICK_INTERRUPT
-	#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.  A default that uses the PIT is provided in the official demo application.
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
-
-/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS			( 0x01UL )
-
-/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK			( 0x1F )
-
-/* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE				( 0x10 )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing.  This function is necessarily written in
- * assembly code so is implemented in portASM.s.
- */
-extern void vPortRestoreTaskContext( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero
-then a floating point context must be saved and restored for the task. */
-uint32_t ulPortTaskHasFPUContext = pdFALSE;
-
-/* Set to 1 to pend a context switch from an ISR. */
-uint32_t ulPortYieldRequired = pdFALSE;
-
-/* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
-uint32_t ulPortInterruptNesting = 0UL;
-
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro.
-
-	The fist real value on the stack is the status register, which is set for
-	system mode, with interrupts enabled.  A few NULLs are added first to ensure
-	GDB does not try decoding a non-existent return address. */
-	*pxTopOfStack = NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
-	{
-		/* The task will start in THUMB mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-
-	pxTopOfStack--;
-
-	/* Next the return address, which in this case is the start of the task. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-
-	/* Next all the registers other than the stack pointer. */
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The task will start with a critical nesting count of 0 as interrupts are
-	enabled. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-	pxTopOfStack--;
-
-	/* The task will start without a floating point context.  A task that uses
-	the floating point hardware must call vPortTaskUsesFPU() before executing
-	any floating point instructions. */
-	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( ulPortInterruptNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-uint32_t ulAPSR;
-
-	/* Only continue if the CPU is not in User mode.  The CPU must be in a
-	Privileged mode for the scheduler to start. */
-	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
-	ulAPSR &= portAPSR_MODE_BITS_MASK;
-	configASSERT( ulAPSR != portAPSR_USER_MODE );
-
-	if( ulAPSR != portAPSR_USER_MODE )
-	{
-		/* Start the timer that generates the tick ISR. */
-		configSETUP_TICK_INTERRUPT();
-		vPortRestoreTaskContext();
-	}
-
-	/* Will only get here if vTaskStartScheduler() was called with the CPU in
-	a non-privileged mode or the binary point register was not set to its lowest
-	possible value. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( ulCriticalNesting == 1 )
-	{
-		configASSERT( ulPortInterruptNesting == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as the critical section is being
-		exited. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then all interrupt
-		priorities must be re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Critical nesting has reached zero so all interrupt priorities
-			should be unmasked. */
-			portENABLE_INTERRUPTS();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void FreeRTOS_Tick_Handler( void )
-{
-	portDISABLE_INTERRUPTS();
-
-	/* Increment the RTOS tick. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		ulPortYieldRequired = pdTRUE;
-	}
-
-	portENABLE_INTERRUPTS();
-	configCLEAR_TICK_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortTaskUsesFPU( void )
-{
-uint32_t ulInitialFPSCR = 0;
-
-	/* A task is registering the fact that it needs an FPU context.  Set the
-	FPU flag (which is saved as part of the task context). */
-	ulPortTaskHasFPUContext = pdTRUE;
-
-	/* Initialise the floating point status register. */
-	__asm( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) );
-}
-/*-----------------------------------------------------------*/
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
deleted file mode 100755
index e1e55c7..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.h
+++ /dev/null
@@ -1,113 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	EXTERN	vTaskSwitchContext
-	EXTERN  ulCriticalNesting
-	EXTERN	pxCurrentTCB
-	EXTERN	ulPortTaskHasFPUContext
-	EXTERN  ulAsmAPIPriorityMask
-
-portSAVE_CONTEXT macro
-
-	; Save the LR and SPSR onto the system mode stack before switching to
-	; system mode to save the remaining system mode registers
-	SRSDB	sp!, #SYS_MODE
-	CPS		#SYS_MODE
-	PUSH	{R0-R12, R14}
-
-	; Push the critical nesting count
-	LDR		R2, =ulCriticalNesting
-	LDR		R1, [R2]
-	PUSH	{R1}
-
-	; Does the task have a floating point context that needs saving?  If
-	; ulPortTaskHasFPUContext is 0 then no.
-	LDR		R2, =ulPortTaskHasFPUContext
-	LDR		R3, [R2]
-	CMP		R3, #0
-
-	; Save the floating point context, if any
-	FMRXNE  R1,  FPSCR
-	VPUSHNE {D0-D15}
-#if configFPU_D32 == 1
-	VPUSHNE	{D16-D31}
-#endif ; configFPU_D32
-	PUSHNE	{R1}
-
-	; Save ulPortTaskHasFPUContext itself
-	PUSH	{R3}
-
-	; Save the stack pointer in the TCB
-	LDR		R0, =pxCurrentTCB
-	LDR		R1, [R0]
-	STR		SP, [R1]
-
-	endm
-
-; /**********************************************************************/
-
-portRESTORE_CONTEXT macro
-
-	; Set the SP to point to the stack of the task being restored.
-	LDR		R0, =pxCurrentTCB
-	LDR		R1, [R0]
-	LDR		SP, [R1]
-
-	; Is there a floating point context to restore?  If the restored
-	; ulPortTaskHasFPUContext is zero then no.
-	LDR		R0, =ulPortTaskHasFPUContext
-	POP		{R1}
-	STR		R1, [R0]
-	CMP		R1, #0
-
-	; Restore the floating point context, if any
-	POPNE 	{R0}
-#if configFPU_D32 == 1
-	VPOPNE	{D16-D31}
-#endif ; configFPU_D32
-	VPOPNE	{D0-D15}
-	VMSRNE  FPSCR, R0
-
-	; Restore the critical section nesting depth
-	LDR		R0, =ulCriticalNesting
-	POP		{R1}
-	STR		R1, [R0]
-
-	; Restore all system mode registers other than the SP (which is already
-	; being used)
-	POP		{R0-R12, R14}
-
-	; Return to the task code, loading CPSR on the way.  CPSR has the interrupt
-	; enable bit set appropriately for the task about to execute.
-	RFEIA	sp!
-
-	endm
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
deleted file mode 100755
index f213966..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portASM.s
+++ /dev/null
@@ -1,176 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	INCLUDE FreeRTOSConfig.h
-	INCLUDE portmacro.h
-
-	EXTERN	vTaskSwitchContext
-	EXTERN	ulPortYieldRequired
-	EXTERN	ulPortInterruptNesting
-	EXTERN	vApplicationIRQHandler
-
-	PUBLIC	FreeRTOS_SWI_Handler
-	PUBLIC  FreeRTOS_IRQ_Handler
-	PUBLIC 	vPortRestoreTaskContext
-
-SYS_MODE			EQU		0x1f
-SVC_MODE			EQU		0x13
-IRQ_MODE			EQU		0x12
-
-	SECTION .text:CODE:ROOT(2)
-	ARM
-
-	INCLUDE portASM.h
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; SVC handler is used to yield a task.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-FreeRTOS_SWI_Handler
-
-	PRESERVE8
-
-	; Save the context of the current task and select a new task to run.
-	portSAVE_CONTEXT
-	LDR R0, =vTaskSwitchContext
-	BLX	R0
-	portRESTORE_CONTEXT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; vPortRestoreTaskContext is used to start the scheduler.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortRestoreTaskContext
-
-	PRESERVE8
-
-	; Switch to system mode
-	CPS		#SYS_MODE
-	portRESTORE_CONTEXT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; IRQ interrupt handler used when individual priorities cannot be masked
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-FreeRTOS_IRQ_Handler
-
-	PRESERVE8
-
-	; Return to the interrupted instruction.
-	SUB		lr, lr, #4
-
-	; Push the return address and SPSR
-	PUSH	{lr}
-	MRS		lr, SPSR
-	PUSH	{lr}
-
-	; Change to supervisor mode to allow reentry.
-	CPS		#SVC_MODE
-
-	; Push used registers.
-	PUSH	{r0-r4, r12}
-
-	; Increment nesting count.  r3 holds the address of ulPortInterruptNesting
-	; for future use.  r1 holds the original ulPortInterruptNesting value for
-	; future use.
-	LDR		r3, =ulPortInterruptNesting
-	LDR		r1, [r3]
-	ADD		r4, r1, #1
-	STR		r4, [r3]
-
-	; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
-	; future use.
-	MOV		r2, sp
-	AND		r2, r2, #4
-	SUB		sp, sp, r2
-
-	PUSH	{r0-r4, lr}
-
-	; Call the port part specific handler.
-	LDR		r0, =vApplicationIRQHandler
-	BLX		r0
-	POP		{r0-r4, lr}
-	ADD		sp, sp, r2
-
-	CPSID	i
-
-	; Write to the EOI register.
-	LDR 	r4, =configEOI_ADDRESS
-	STR		r0, [r4]
-
-	; Restore the old nesting count
-	STR		r1, [r3]
-
-	; A context switch is never performed if the nesting count is not 0.
-	CMP		r1, #0
-	BNE		exit_without_switch
-
-	; Did the interrupt request a context switch?  r1 holds the address of
-	; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
-	; use.
-	LDR		r1, =ulPortYieldRequired
-	LDR		r0, [r1]
-	CMP		r0, #0
-	BNE		switch_before_exit
-
-exit_without_switch
-	; No context switch.  Restore used registers, LR_irq and SPSR before
-	; returning.
-	POP		{r0-r4, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	MOVS	PC, LR
-
-switch_before_exit
-	; A context switch is to be performed.  Clear the context switch pending
-	; flag.
-	MOV		r0, #0
-	STR		r0, [r1]
-
-	; Restore used registers, LR-irq and SPSR before saving the context
-	; to the task stack.
-	POP		{r0-r4, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	portSAVE_CONTEXT
-
-	; Call the function that selects the new task to execute.
-	; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
-	; instructions, or 8 byte aligned stack allocated data.  LR does not need
-	; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
-	LDR		r0, =vTaskSwitchContext
-	BLX		r0
-
-	; Restore the context of, and branch to, the task selected to execute next.
-	portRESTORE_CONTEXT
-
-	END
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h
deleted file mode 100755
index f20e19e..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CA5_No_GIC/portmacro.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/* IAR includes. */
-#ifdef __ICCARM__
-
-	#include 
-
-	#ifdef __cplusplus
-		extern "C" {
-	#endif
-
-	/*-----------------------------------------------------------
-	 * Port specific definitions.
-	 *
-	 * The settings in this file configure FreeRTOS correctly for the given hardware
-	 * and compiler.
-	 *
-	 * These settings should not be altered.
-	 *-----------------------------------------------------------
-	 */
-
-	/* Type definitions. */
-	#define portCHAR		char
-	#define portFLOAT		float
-	#define portDOUBLE		double
-	#define portLONG		long
-	#define portSHORT		short
-	#define portSTACK_TYPE	uint32_t
-	#define portBASE_TYPE	long
-
-	typedef portSTACK_TYPE StackType_t;
-	typedef long BaseType_t;
-	typedef unsigned long UBaseType_t;
-
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-
-	/*-----------------------------------------------------------*/
-
-	/* Hardware specifics. */
-	#define portSTACK_GROWTH			( -1 )
-	#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-	#define portBYTE_ALIGNMENT			8
-
-	/*-----------------------------------------------------------*/
-
-	/* Task utilities. */
-
-	/* Called at the end of an ISR that can cause a context switch. */
-	#define portEND_SWITCHING_ISR( xSwitchRequired )\
-	{												\
-	extern uint32_t ulPortYieldRequired;			\
-													\
-		if( xSwitchRequired != pdFALSE )			\
-		{											\
-			ulPortYieldRequired = pdTRUE;			\
-		}											\
-	}
-
-	#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-	#define portYIELD() __asm volatile ( "SWI 0" ); __ISB()
-
-
-	/*-----------------------------------------------------------
-	 * Critical section control
-	 *----------------------------------------------------------*/
-
-	extern void vPortEnterCritical( void );
-	extern void vPortExitCritical( void );
-	extern uint32_t ulPortSetInterruptMask( void );
-	extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-
-	#define portENTER_CRITICAL()		vPortEnterCritical();
-	#define portEXIT_CRITICAL()			vPortExitCritical();
-	#define portDISABLE_INTERRUPTS()	__disable_irq(); __DSB(); __ISB() /* No priority mask register so global disable is used. */
-	#define portENABLE_INTERRUPTS()		__enable_irq()
-	#define portSET_INTERRUPT_MASK_FROM_ISR()		__get_interrupt_state(); __disable_irq() /* No priority mask register so global disable is used. */
-	#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	__set_interrupt_state(x)
-
-	/*-----------------------------------------------------------*/
-
-	/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-	not required for this port but included in case common demo code that uses these
-	macros is used. */
-	#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-	#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
-
-	/* Prototype of the FreeRTOS tick handler.  This must be installed as the
-	handler for whichever peripheral is used to generate the RTOS tick. */
-	void FreeRTOS_Tick_Handler( void );
-
-	/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-	before any floating point instructions are executed. */
-	void vPortTaskUsesFPU( void );
-	#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
-	/* Architecture specific optimisations. */
-	#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-		#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-	#endif
-
-	#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-		/* Store/clear the ready priorities in a bit map. */
-		#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-		#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-		/*-----------------------------------------------------------*/
-
-		#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
-
-	#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-	#define portNOP() __asm volatile( "NOP" )
-
-
-	#ifdef __cplusplus
-		} /* extern C */
-	#endif
-
-	/* Suppress warnings that are generated by the IAR tools, but cannot be
-	fixed in the source code because to do so would cause other compilers to
-	generate warnings. */
-	#pragma diag_suppress=Pe191
-	#pragma diag_suppress=Pa082
-
-#endif /* __ICCARM__ */
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA9/port.c b/FreeRTOS/Source/portable/IAR/ARM_CA9/port.c
deleted file mode 100755
index 83c7587..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CA9/port.c
+++ /dev/null
@@ -1,439 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* IAR includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
-	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
-	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configUNIQUE_INTERRUPT_PRIORITIES
-	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configSETUP_TICK_INTERRUPT
-	#error configSETUP_TICK_INTERRUPT() must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif /* configSETUP_TICK_INTERRUPT */
-
-#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/* In case security extensions are implemented. */
-#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-#endif
-
-#ifndef configCLEAR_TICK_INTERRUPT
-	#define configCLEAR_TICK_INTERRUPT()
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
-
-/* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE				( 0xFFUL )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
-
-/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS			( 0x01UL )
-
-/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
-
-/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK			( 0x1F )
-
-/* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE				( 0x10 )
-
-/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK()											\
-{																			\
-	__disable_irq();														\
-	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;					\
-	__asm(	"DSB		\n"													\
-			"ISB		\n" );												\
-	__enable_irq();															\
-}
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing.  This function is necessarily written in
- * assembly code so is implemented in portASM.s.
- */
-extern void vPortRestoreTaskContext( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero
-then a floating point context must be saved and restored for the task. */
-uint32_t ulPortTaskHasFPUContext = pdFALSE;
-
-/* Set to 1 to pend a context switch from an ISR. */
-uint32_t ulPortYieldRequired = pdFALSE;
-
-/* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
-uint32_t ulPortInterruptNesting = 0UL;
-
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro.
-
-	The fist real value on the stack is the status register, which is set for
-	system mode, with interrupts enabled.  A few NULLs are added first to ensure
-	GDB does not try decoding a non-existent return address. */
-	*pxTopOfStack = NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
-	{
-		/* The task will start in THUMB mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-
-	pxTopOfStack--;
-
-	/* Next the return address, which in this case is the start of the task. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-
-	/* Next all the registers other than the stack pointer. */
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The task will start with a critical nesting count of 0 as interrupts are
-	enabled. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-	pxTopOfStack--;
-
-	/* The task will start without a floating point context.  A task that uses
-	the floating point hardware must call vPortTaskUsesFPU() before executing
-	any floating point instructions. */
-	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( ulPortInterruptNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-uint32_t ulAPSR;
-
-	/* Only continue if the CPU is not in User mode.  The CPU must be in a
-	Privileged mode for the scheduler to start. */
-	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
-	ulAPSR &= portAPSR_MODE_BITS_MASK;
-	configASSERT( ulAPSR != portAPSR_USER_MODE );
-
-	if( ulAPSR != portAPSR_USER_MODE )
-	{
-		/* Only continue if the binary point value is set to its lowest possible
-		setting.  See the comments in vPortValidateInterruptPriority() below for
-		more information. */
-		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
-
-		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
-		{
-			/* Start the timer that generates the tick ISR. */
-			configSETUP_TICK_INTERRUPT();
-
-			__enable_irq();
-			vPortRestoreTaskContext();
-		}
-	}
-
-	/* Will only get here if vTaskStartScheduler() was called with the CPU in
-	a non-privileged mode or the binary point register was not set to its lowest
-	possible value. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 	*/
-	ulPortSetInterruptMask();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-	
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API 
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( ulCriticalNesting == 1 )
-	{
-		configASSERT( ulPortInterruptNesting == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as the critical section is being
-		exited. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then all interrupt
-		priorities must be re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Critical nesting has reached zero so all interrupt priorities
-			should be unmasked. */
-			portCLEAR_INTERRUPT_MASK();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void FreeRTOS_Tick_Handler( void )
-{
-	/* Set interrupt mask before altering scheduler structures.   The tick
-	handler runs at the lowest priority, so interrupts cannot already be masked,
-	so there is no need to save and restore the current mask value. */
-	__disable_irq();
-	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-	__asm(	"DSB		\n"
-			"ISB		\n" );
-	__enable_irq();
-
-	/* Increment the RTOS tick. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		ulPortYieldRequired = pdTRUE;
-	}
-
-	/* Ensure all interrupt priorities are active again. */
-	portCLEAR_INTERRUPT_MASK();
-	configCLEAR_TICK_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortTaskUsesFPU( void )
-{
-uint32_t ulInitialFPSCR = 0;
-
-	/* A task is registering the fact that it needs an FPU context.  Set the
-	FPU flag (which is saved as part of the task context). */
-	ulPortTaskHasFPUContext = pdTRUE;
-
-	/* Initialise the floating point status register. */
-	__asm( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) );
-}
-/*-----------------------------------------------------------*/
-
-void vPortClearInterruptMask( uint32_t ulNewMaskValue )
-{
-	if( ulNewMaskValue == pdFALSE )
-	{
-		portCLEAR_INTERRUPT_MASK();
-	}
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortSetInterruptMask( void )
-{
-uint32_t ulReturn;
-
-	__disable_irq();
-	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
-	{
-		/* Interrupts were already masked. */
-		ulReturn = pdTRUE;
-	}
-	else
-	{
-		ulReturn = pdFALSE;
-		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-		__asm(	"DSB		\n"
-				"ISB		\n" );
-	}
-	__enable_irq();
-
-	return ulReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-		/* The following assertion will fail if a service routine (ISR) for
-		an interrupt that has been assigned a priority above
-		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-		function.  ISR safe FreeRTOS API functions must *only* be called
-		from interrupts that have been assigned a priority at or below
-		configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-		Numerically low interrupt priority numbers represent logically high
-		interrupt priorities, therefore the priority of the interrupt must
-		be set to a value equal to or numerically *higher* than
-		configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-		FreeRTOS maintains separate thread and ISR API functions to ensure
-		interrupt entry is as fast and simple as possible.
-
-		The following links provide detailed information:
-		http://www.freertos.org/RTOS-Cortex-M3-M4.html
-		http://www.freertos.org/FAQHelp.html */
-		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
-
-		/* Priority grouping:  The interrupt controller (GIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		The priority grouping is configured by the GIC's binary point register
-		(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
-		possible value (which may be above 0). */
-		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.h b/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.h
deleted file mode 100755
index eda42ba..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.h
+++ /dev/null
@@ -1,115 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	EXTERN	vTaskSwitchContext
-	EXTERN  ulCriticalNesting
-	EXTERN	pxCurrentTCB
-	EXTERN	ulPortTaskHasFPUContext
-	EXTERN  ulAsmAPIPriorityMask
-
-portSAVE_CONTEXT macro
-
-	; Save the LR and SPSR onto the system mode stack before switching to
-	; system mode to save the remaining system mode registers
-	SRSDB	sp!, #SYS_MODE
-	CPS		#SYS_MODE
-	PUSH	{R0-R12, R14}
-
-	; Push the critical nesting count
-	LDR		R2, =ulCriticalNesting
-	LDR		R1, [R2]
-	PUSH	{R1}
-
-	; Does the task have a floating point context that needs saving?  If
-	; ulPortTaskHasFPUContext is 0 then no.
-	LDR		R2, =ulPortTaskHasFPUContext
-	LDR		R3, [R2]
-	CMP		R3, #0
-
-	; Save the floating point context, if any
-	FMRXNE  R1,  FPSCR
-	VPUSHNE {D0-D15}
-	VPUSHNE	{D16-D31}
-	PUSHNE	{R1}
-
-	; Save ulPortTaskHasFPUContext itself
-	PUSH	{R3}
-
-	; Save the stack pointer in the TCB
-	LDR		R0, =pxCurrentTCB
-	LDR		R1, [R0]
-	STR		SP, [R1]
-
-	endm
-
-; /**********************************************************************/
-
-portRESTORE_CONTEXT macro
-
-	; Set the SP to point to the stack of the task being restored.
-	LDR		R0, =pxCurrentTCB
-	LDR		R1, [R0]
-	LDR		SP, [R1]
-
-	; Is there a floating point context to restore?  If the restored
-	; ulPortTaskHasFPUContext is zero then no.
-	LDR		R0, =ulPortTaskHasFPUContext
-	POP		{R1}
-	STR		R1, [R0]
-	CMP		R1, #0
-
-	; Restore the floating point context, if any
-	POPNE 	{R0}
-	VPOPNE	{D16-D31}
-	VPOPNE	{D0-D15}
-	VMSRNE  FPSCR, R0
-
-	; Restore the critical section nesting depth
-	LDR		R0, =ulCriticalNesting
-	POP		{R1}
-	STR		R1, [R0]
-
-	; Ensure the priority mask is correct for the critical nesting depth
-	LDR		R2, =portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS
-	CMP		R1, #0
-	MOVEQ	R4, #255
-	LDRNE	R4, =( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT )
-	STR		R4, [r2]
-
-	; Restore all system mode registers other than the SP (which is already
-	; being used)
-	POP		{R0-R12, R14}
-
-	; Return to the task code, loading CPSR on the way.
-	RFEIA	sp!
-
-	endm
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s b/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
deleted file mode 100755
index 42f23d8..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CA9/portASM.s
+++ /dev/null
@@ -1,177 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	INCLUDE FreeRTOSConfig.h
-	INCLUDE portmacro.h
-
-	EXTERN	vApplicationIRQHandler
-	EXTERN	vTaskSwitchContext
-	EXTERN	ulPortYieldRequired
-	EXTERN	ulPortInterruptNesting
-
-	PUBLIC	FreeRTOS_SWI_Handler
-	PUBLIC  FreeRTOS_IRQ_Handler
-	PUBLIC 	vPortRestoreTaskContext
-
-SYS_MODE			EQU		0x1f
-SVC_MODE			EQU		0x13
-IRQ_MODE			EQU		0x12
-
-
-	SECTION .text:CODE:ROOT(2)
-	ARM
-
-	INCLUDE portASM.h
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; SVC handler is used to yield a task.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-FreeRTOS_SWI_Handler
-
-	PRESERVE8
-
-	; Save the context of the current task and select a new task to run.
-	portSAVE_CONTEXT
-	LDR R0, =vTaskSwitchContext
-	BLX	R0
-	portRESTORE_CONTEXT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; vPortRestoreTaskContext is used to start the scheduler.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortRestoreTaskContext
-	; Switch to system mode
-	CPS		#SYS_MODE
-	portRESTORE_CONTEXT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; PL390 GIC interrupt handler
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-FreeRTOS_IRQ_Handler
-
-	; Return to the interrupted instruction.
-	SUB		lr, lr, #4
-
-	; Push the return address and SPSR
-	PUSH	{lr}
-	MRS		lr, SPSR
-	PUSH	{lr}
-
-	; Change to supervisor mode to allow reentry.
-	CPS		#SVC_MODE
-
-	; Push used registers.
-	PUSH	{r0-r4, r12}
-
-	; Increment nesting count.  r3 holds the address of ulPortInterruptNesting
-	; for future use.  r1 holds the original ulPortInterruptNesting value for
-	; future use.
-	LDR		r3, =ulPortInterruptNesting
-	LDR		r1, [r3]
-	ADD		r4, r1, #1
-	STR		r4, [r3]
-
-	; Read value from the interrupt acknowledge register, which is stored in r0
-	; for future parameter and interrupt clearing use.
-	LDR 	r2, =portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS
-	LDR		r0, [r2]
-
-	; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
-	; future use.  _RB_ Is this ever necessary if start of stack is 8-byte aligned?
-	MOV		r2, sp
-	AND		r2, r2, #4
-	SUB		sp, sp, r2
-
-	; Call the interrupt handler.  r4 is pushed to maintain alignment.
-	PUSH	{r0-r4, lr}
-	LDR		r1, =vApplicationIRQHandler
-	BLX		r1
-	POP		{r0-r4, lr}
-	ADD		sp, sp, r2
-
-	CPSID	i
-
-	; Write the value read from ICCIAR to ICCEOIR
-	LDR 	r4, =portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS
-	STR		r0, [r4]
-
-	; Restore the old nesting count
-	STR		r1, [r3]
-
-	; A context switch is never performed if the nesting count is not 0
-	CMP		r1, #0
-	BNE		exit_without_switch
-
-	; Did the interrupt request a context switch?  r1 holds the address of
-	; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
-	; use.
-	LDR		r1, =ulPortYieldRequired
-	LDR		r0, [r1]
-	CMP		r0, #0
-	BNE		switch_before_exit
-
-exit_without_switch
-	; No context switch.  Restore used registers, LR_irq and SPSR before
-	; returning.
-	POP		{r0-r4, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	MOVS	PC, LR
-
-switch_before_exit
-	; A context switch is to be performed.  Clear the context switch pending
-	; flag.
-	MOV		r0, #0
-	STR		r0, [r1]
-
-	; Restore used registers, LR-irq and SPSR before saving the context
-	; to the task stack.
-	POP		{r0-r4, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	portSAVE_CONTEXT
-
-	; Call the function that selects the new task to execute.
-	; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
-	; instructions, or 8 byte aligned stack allocated data.  LR does not need
-	; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
-	LDR		r0, =vTaskSwitchContext
-	BLX		r0
-
-	; Restore the context of, and branch to, the task selected to execute next.
-	portRESTORE_CONTEXT
-
-
-	END
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CA9/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CA9/portmacro.h
deleted file mode 100755
index dfa8ff2..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CA9/portmacro.h
+++ /dev/null
@@ -1,209 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/* IAR includes. */
-#ifdef __ICCARM__
-
-	#include 
-
-	#ifdef __cplusplus
-		extern "C" {
-	#endif
-
-	/*-----------------------------------------------------------
-	 * Port specific definitions.
-	 *
-	 * The settings in this file configure FreeRTOS correctly for the given hardware
-	 * and compiler.
-	 *
-	 * These settings should not be altered.
-	 *-----------------------------------------------------------
-	 */
-
-	/* Type definitions. */
-	#define portCHAR		char
-	#define portFLOAT		float
-	#define portDOUBLE		double
-	#define portLONG		long
-	#define portSHORT		short
-	#define portSTACK_TYPE	uint32_t
-	#define portBASE_TYPE	long
-
-	typedef portSTACK_TYPE StackType_t;
-	typedef long BaseType_t;
-	typedef unsigned long UBaseType_t;
-
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-
-	/*-----------------------------------------------------------*/
-
-	/* Hardware specifics. */
-	#define portSTACK_GROWTH			( -1 )
-	#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-	#define portBYTE_ALIGNMENT			8
-
-	/*-----------------------------------------------------------*/
-
-	/* Task utilities. */
-
-	/* Called at the end of an ISR that can cause a context switch. */
-	#define portEND_SWITCHING_ISR( xSwitchRequired )\
-	{												\
-	extern uint32_t ulPortYieldRequired;			\
-													\
-		if( xSwitchRequired != pdFALSE )			\
-		{											\
-			ulPortYieldRequired = pdTRUE;			\
-		}											\
-	}
-
-	#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-	#define portYIELD() __asm( "SWI 0" );
-
-
-	/*-----------------------------------------------------------
-	 * Critical section control
-	 *----------------------------------------------------------*/
-
-	extern void vPortEnterCritical( void );
-	extern void vPortExitCritical( void );
-	extern uint32_t ulPortSetInterruptMask( void );
-	extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-
-	/* These macros do not globally disable/enable interrupts.  They do mask off
-	interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-	#define portENTER_CRITICAL()		vPortEnterCritical();
-	#define portEXIT_CRITICAL()			vPortExitCritical();
-	#define portDISABLE_INTERRUPTS()	ulPortSetInterruptMask()
-	#define portENABLE_INTERRUPTS()		vPortClearInterruptMask( 0 )
-	#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
-	#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
-
-	/*-----------------------------------------------------------*/
-
-	/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-	not required for this port but included in case common demo code that uses these
-	macros is used. */
-	#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-	#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
-
-	/* Prototype of the FreeRTOS tick handler.  This must be installed as the
-	handler for whichever peripheral is used to generate the RTOS tick. */
-	void FreeRTOS_Tick_Handler( void );
-
-	/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-	before any floating point instructions are executed. */
-	void vPortTaskUsesFPU( void );
-	#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
-	#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-	#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
-
-	/* Architecture specific optimisations. */
-	#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-		#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-	#endif
-
-	#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-		/* Store/clear the ready priorities in a bit map. */
-		#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-		#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-		/*-----------------------------------------------------------*/
-
-		#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __CLZ( uxReadyPriorities ) )
-
-	#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-	#ifdef configASSERT
-		void vPortValidateInterruptPriority( void );
-		#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-	#endif /* configASSERT */
-
-	#define portNOP() __asm volatile( "NOP" )
-
-
-	#ifdef __cplusplus
-		} /* extern C */
-	#endif
-
-	/* Suppress warnings that are generated by the IAR tools, but cannot be
-	fixed in the source code because to do so would cause other compilers to
-	generate warnings. */
-	#pragma diag_suppress=Pe191
-	#pragma diag_suppress=Pa082
-
-#endif /* __ICCARM__ */
-
-
-/* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
-#if configUNIQUE_INTERRUPT_PRIORITIES == 16
-	#define portPRIORITY_SHIFT 4
-	#define portMAX_BINARY_POINT_VALUE	3
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
-	#define portPRIORITY_SHIFT 3
-	#define portMAX_BINARY_POINT_VALUE	2
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
-	#define portPRIORITY_SHIFT 2
-	#define portMAX_BINARY_POINT_VALUE	1
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
-	#define portPRIORITY_SHIFT 1
-	#define portMAX_BINARY_POINT_VALUE	0
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
-	#define portPRIORITY_SHIFT 0
-	#define portMAX_BINARY_POINT_VALUE	0
-#else
-	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
-
-/* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET  						( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET 				( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET 					( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET							( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET						( 0x14 )
-
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c b/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c
deleted file mode 100755
index 565c687..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM0/port.c
+++ /dev/null
@@ -1,218 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM0 port.
- *----------------------------------------------------------*/
-
-/* IAR includes. */
-#include "intrinsics.h"
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL			( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD			( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE	( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_SYSPRI2			( ( volatile uint32_t *) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK		0x00000004
-#define portNVIC_SYSTICK_INT		0x00000002
-#define portNVIC_SYSTICK_ENABLE		0x00000001
-#define portMIN_INTERRUPT_PRIORITY	( 255UL )
-#define portNVIC_PENDSV_PRI			( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI		( portMIN_INTERRUPT_PRIORITY << 24UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR			( 0x01000000 )
-
-/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
-defined.  The value 255 should also ensure backward compatibility.
-FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
-#ifndef configKERNEL_INTERRUPT_PRIORITY
-	#define configKERNEL_INTERRUPT_PRIORITY 0
-#endif
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortSysTickHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-extern void vPortStartFirstTask( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-	pxTopOfStack -= 8; /* R11..R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
-	*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Start the first task. */
-	vPortStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortYield( void )
-{
-	/* Set a PendSV to request a context switch. */
-	*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is completely
-	within the specified behaviour for the architecture. */
-	__DSB();
-	__ISB();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-	__DSB();
-	__ISB();
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-static void prvSetupTimerInterrupt( void )
-{
-	/* Stop and reset the SysTick. */
-	*(portNVIC_SYSTICK_CTRL) = 0UL;
-	*(portNVIC_SYSTICK_CURRENT_VALUE) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s b/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s
deleted file mode 100755
index a2e3ce8..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM0/portasm.s
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include 
-
-	RSEG    CODE:CODE(2)
-	thumb
-
-	EXTERN vPortYieldFromISR
-	EXTERN pxCurrentTCB
-	EXTERN vTaskSwitchContext
-
-	PUBLIC vSetMSP
-	PUBLIC xPortPendSVHandler
-	PUBLIC vPortSVCHandler
-	PUBLIC vPortStartFirstTask
-	PUBLIC ulSetInterruptMaskFromISR
-	PUBLIC vClearInterruptMaskFromISR
-
-/*-----------------------------------------------------------*/
-
-vSetMSP
-	msr msp, r0
-	bx lr
-
-/*-----------------------------------------------------------*/
-
-xPortPendSVHandler:
-	mrs r0, psp
-
-	ldr	r3, =pxCurrentTCB	/* Get the location of the current TCB. */
-	ldr	r2, [r3]
-
-	subs r0, r0, #32		/* Make space for the remaining low registers. */
-	str r0, [r2]			/* Save the new top of stack. */
-	stmia r0!, {r4-r7}		/* Store the low registers that are not saved automatically. */
-	mov r4, r8				/* Store the high registers. */
-	mov r5, r9
-	mov r6, r10
-	mov r7, r11
-	stmia r0!, {r4-r7}
-
-	push {r3, r14}
-	cpsid i
-	bl vTaskSwitchContext
-	cpsie i
-	pop {r2, r3}			/* lr goes in r3. r2 now holds tcb pointer. */
-
-	ldr r1, [r2]
-	ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
-	adds r0, r0, #16		/* Move to the high registers. */
-	ldmia r0!, {r4-r7}		/* Pop the high registers. */
-	mov r8, r4
-	mov r9, r5
-	mov r10, r6
-	mov r11, r7
-
-	msr psp, r0				/* Remember the new top of stack for the task. */
-
-	subs r0, r0, #32		/* Go back for the low registers that are not automatically restored. */
-	ldmia r0!, {r4-r7}		/* Pop low registers.  */
-
-	bx r3
-
-/*-----------------------------------------------------------*/
-
-vPortSVCHandler;
-	/* This function is no longer used, but retained for backward
-	compatibility. */
-	bx lr
-
-/*-----------------------------------------------------------*/
-
-vPortStartFirstTask
-	/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
-	table offset register that can be used to locate the initial stack value.
-	Not all M0 parts have the application vector table at address 0. */
-
-	ldr	r3, =pxCurrentTCB	/* Obtain location of pxCurrentTCB. */
-	ldr r1, [r3]
-	ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
-	adds r0, #32			/* Discard everything up to r0. */
-	msr psp, r0				/* This is now the new top of stack to use in the task. */
-	movs r0, #2				/* Switch to the psp stack. */
-	msr CONTROL, r0
-	isb
-	pop {r0-r5}				/* Pop the registers that are saved automatically. */
-	mov lr, r5				/* lr is now in r5. */
-	pop {r3}				/* The return address is now in r3. */
-	pop {r2}				/* Pop and discard the XPSR. */
-	cpsie i					/* The first task has its context and interrupts can be enabled. */
-	bx r3					/* Jump to the user defined task code. */
-
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMaskFromISR
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-
-/*-----------------------------------------------------------*/
-
-vClearInterruptMaskFromISR
-	msr PRIMASK, r0
-	bx lr
-
-	END
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h
deleted file mode 100755
index 44fe318..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM0/portmacro.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
-extern void vPortYield( void );
-#define portNVIC_INT_CTRL			( ( volatile uint32_t *) 0xe000ed04 )
-#define portNVIC_PENDSVSET			0x10000000
-#define portYIELD()					vPortYield()
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) 	*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-
-/* Critical section management. */
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulSetInterruptMaskFromISR( void );
-extern void vClearInterruptMaskFromISR( uint32_t ulMask );
-
-#define portDISABLE_INTERRUPTS()				__asm volatile( "cpsid i" )
-#define portENABLE_INTERRUPTS()					__asm volatile( "cpsie i" )
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vClearInterruptMaskFromISR( x )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#define portNOP()
-
-/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
-the source code because to do so would cause other compilers to generate
-warnings. */
-#pragma diag_suppress=Pa082
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c b/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c
deleted file mode 100755
index bd85a6f..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h b/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
deleted file mode 100755
index 2ecf04e..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s b/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
deleted file mode 100755
index b1a543a..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portasm.s
+++ /dev/null
@@ -1,377 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	EXTERN pxCurrentTCB
-	EXTERN xSecureContext
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-	EXTERN SecureContext_SaveContext
-	EXTERN SecureContext_LoadContext
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vPortAllocateSecureContext
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMaskFromISR
-	PUBLIC vClearInterruptMaskFromISR
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-	PUBLIC vPortFreeSecureContext
-
-#if ( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	movs r1, #1								/* r1 = 1. */
-	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
-	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-	running_privileged:
-		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-		bx lr								/* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	movs r1, #1								/* r1 = 1. */
-	orrs r0, r1								/* r0 = r0 | r1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vPortAllocateSecureContext:
-	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r3, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	movs r5, #1								/* r5 = 1. */
-	bics r4, r5								/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
-	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str  r4, [r2]							/* Program MAIR0. */
-	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	movs r5, #4								/* r5 = 4. */
-	str  r5, [r2]							/* Program RNR = 4. */
-	ldmia r3!, {r6,r7}						/* Read first set of RBAR/RLAR from TCB. */
-	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
-	stmia r4!, {r6,r7}						/* Write first set of RBAR/RLAR registers. */
-	movs r5, #5								/* r5 = 5. */
-	str  r5, [r2]							/* Program RNR = 5. */
-	ldmia r3!, {r6,r7}						/* Read second set of RBAR/RLAR from TCB. */
-	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
-	stmia r4!, {r6,r7}						/* Write second set of RBAR/RLAR registers. */
-	movs r5, #6								/* r5 = 6. */
-	str  r5, [r2]							/* Program RNR = 6. */
-	ldmia r3!, {r6,r7}						/* Read third set of RBAR/RLAR from TCB. */
-	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
-	stmia r4!, {r6,r7}						/* Write third set of RBAR/RLAR registers. */
-	movs r5, #7								/* r5 = 7. */
-	str  r5, [r2]							/* Program RNR = 7. */
-	ldmia r3!, {r6,r7}						/* Read fourth set of RBAR/RLAR from TCB. */
-	ldr  r4, =0xe000ed9c					/* r4 = 0xe000ed9c [Location of RBAR]. */
-	stmia r4!, {r6,r7}						/* Write fourth set of RBAR/RLAR registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	movs r5, #1								/* r5 = 1. */
-	orrs r4, r5								/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	ldr  r5, =xSecureContext
-	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	msr  control, r3						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r4									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	ldr  r4, =xSecureContext
-	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs r0, control							/* Read the CONTROL register. */
-	movs r1, #1								/* r1 = 1. */
-	bics r0, r1								/* Clear the bit 0. */
-	msr control, r0							/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMaskFromISR:
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-/*-----------------------------------------------------------*/
-
-vClearInterruptMaskFromISR:
-	msr PRIMASK, r0
-	bx lr
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	mrs r1, psp								/* Read PSP in r1. */
-	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-
-	cbz r0, save_ns_context					/* No secure context to save. */
-	push {r0-r2, r14}
-	bl SecureContext_SaveContext
-	pop {r0-r3}								/* LR is now in r3. */
-	mov lr, r3								/* LR = r3. */
-	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r2, [r3]							/* Read pxCurrentTCB. */
-#if ( configENABLE_MPU == 1 )
-	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mrs r3, control							/* r3 = CONTROL. */
-	mov r4, lr								/* r4 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-#else /* configENABLE_MPU */
-	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
-#endif /* configENABLE_MPU */
-	b select_next_task
-
-	save_ns_context:
-		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r2, [r3]						/* Read pxCurrentTCB. */
-	#if ( configENABLE_MPU == 1 )
-		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #16					/* r1 = r1 + 16. */
-		stmia r1!, {r4-r7}					/* Store the low registers that are not saved automatically. */
-		mov r4, r8							/* r4 = r8. */
-		mov r5, r9							/* r5 = r9. */
-		mov r6, r10							/* r6 = r10. */
-		mov r7, r11							/* r7 = r11. */
-		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
-		mrs r3, control						/* r3 = CONTROL. */
-		mov r4, lr							/* r4 = LR/EXC_RETURN. */
-		subs r1, r1, #48					/* r1 = r1 - 48. */
-		stmia r1!, {r0, r2-r4}				/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
-		mov r3, lr							/* r3 = LR/EXC_RETURN. */
-		stmia r1!, {r0, r2-r7}				/* Store xSecureContext, PSPLIM, LR and the low registers that are not saved automatically. */
-		mov r4, r8							/* r4 = r8. */
-		mov r5, r9							/* r5 = r9. */
-		mov r6, r10							/* r6 = r10. */
-		mov r7, r11							/* r7 = r11. */
-		stmia r1!, {r4-r7}					/* Store the high registers that are not saved automatically. */
-	#endif /* configENABLE_MPU */
-
-	select_next_task:
-		cpsid i
-		bl vTaskSwitchContext
-		cpsie i
-
-		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r3, [r2]						/* Read pxCurrentTCB. */
-		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-
-	#if ( configENABLE_MPU == 1 )
-		dmb									/* Complete outstanding transfers before disabling MPU. */
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
-		movs r5, #1							/* r5 = 1. */
-		bics r4, r5							/* r4 = r4 & ~r5 i.e. Clear the bit 0 in r4. */
-		str r4, [r2]						/* Disable MPU. */
-
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
-		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-		str r4, [r2]						/* Program MAIR0. */
-		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-		movs r5, #4							/* r5 = 4. */
-		str  r5, [r2]						/* Program RNR = 4. */
-		ldmia r3!, {r6,r7}					/* Read first set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write first set of RBAR/RLAR registers. */
-		movs r5, #5							/* r5 = 5. */
-		str  r5, [r2]						/* Program RNR = 5. */
-		ldmia r3!, {r6,r7}					/* Read second set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write second set of RBAR/RLAR registers. */
-		movs r5, #6							/* r5 = 6. */
-		str  r5, [r2]						/* Program RNR = 6. */
-		ldmia r3!, {r6,r7}					/* Read third set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write third set of RBAR/RLAR registers. */
-		movs r5, #7							/* r5 = 7. */
-		str  r5, [r2]						/* Program RNR = 7. */
-		ldmia r3!, {r6,r7}					/* Read fourth set of RBAR/RLAR from TCB. */
-		ldr  r4, =0xe000ed9c				/* r4 = 0xe000ed9c [Location of RBAR]. */
-		stmia r4!, {r6,r7}					/* Write fourth set of RBAR/RLAR registers. */
-
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
-		movs r5, #1							/* r5 = 1. */
-		orrs r4, r5							/* r4 = r4 | r5 i.e. Set the bit 0 in r4. */
-		str r4, [r2]						/* Enable MPU. */
-		dsb									/* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-
-	#if ( configENABLE_MPU == 1 )
-		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		msr control, r3						/* Restore the CONTROL register value for the task. */
-		mov lr, r4							/* LR = r4. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r4}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r4}
-		mov lr, r4							/* LR = r4. */
-		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-	#else /* configENABLE_MPU */
-		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		mov lr, r3							/* LR = r3. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r3}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r3}
-		mov lr, r3							/* LR = r3. */
-		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-	#endif /* configENABLE_MPU */
-
-	restore_ns_context:
-		adds r1, r1, #16					/* Move to the high registers. */
-		ldmia r1!, {r4-r7}					/* Restore the high registers that are not automatically restored. */
-		mov r8, r4							/* r8 = r4. */
-		mov r9, r5							/* r9 = r5. */
-		mov r10, r6							/* r10 = r6. */
-		mov r11, r7							/* r11 = r7. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		subs r1, r1, #32					/* Go back to the low registers. */
-		ldmia r1!, {r4-r7}					/* Restore the low registers that are not automatically restored. */
-		bx lr
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	movs r0, #4
-	mov r1, lr
-	tst r0, r1
-	beq stacking_used_msp
-	mrs r0, psp
-	b vPortSVCHandler_C
-	stacking_used_msp:
-		mrs r0, msp
-		b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-vPortFreeSecureContext:
-	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
-	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
-	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
-	beq free_secure_context
-	bx lr									/* There is no secure context (xSecureContext is NULL). */
-	free_secure_context:
-		svc 1								/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
-		bx lr								/* Return. */
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
deleted file mode 100755
index 48b0e0b..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23/non_secure/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M23"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c b/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c
deleted file mode 100755
index 53535cd..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief CONTROL value for privileged tasks.
- *
- * Bit[0] - 0 --> Thread mode is privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
-
-/**
- * @brief CONTROL value for un-privileged tasks.
- *
- * Bit[0] - 1 --> Thread mode is un-privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Structure to represent secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first addess of the allocated memory.
- */
-typedef struct SecureContext
-{
-	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
-	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
-	uint8_t *pucStackStart;				/**< First location of the stack memory. */
-} SecureContext_t;
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* No stack for thread mode until a task's context is loaded. */
-		secureportSET_PSPLIM( securecontextNO_STACK );
-		secureportSET_PSP( securecontextNO_STACK );
-
-		#if( configENABLE_MPU == 1 )
-		{
-			/* Configure thread mode to use PSP and to be unprivileged. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-		}
-		#else /* configENABLE_MPU */
-		{
-			/* Configure thread mode to use PSP and to be privileged.. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-		}
-		#endif /* configENABLE_MPU */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
-#else /* configENABLE_MPU */
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
-#endif /* configENABLE_MPU */
-{
-	uint8_t *pucStackMemory = NULL;
-	uint32_t ulIPSR;
-	SecureContextHandle_t xSecureContextHandle = NULL;
-	#if( configENABLE_MPU == 1 )
-		uint32_t *pulCurrentStackPointer = NULL;
-	#endif /* configENABLE_MPU */
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Allocate the context structure. */
-		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
-
-		if( xSecureContextHandle != NULL )
-		{
-			/* Allocate the stack space. */
-			pucStackMemory = pvPortMalloc( ulSecureStackSize );
-
-			if( pucStackMemory != NULL )
-			{
-				/* Since stack grows down, the starting point will be the last
-				 * location. Note that this location is next to the last
-				 * allocated byte because the hardware decrements the stack
-				 * pointer before writing i.e. if stack pointer is 0x2, a push
-				 * operation will decrement the stack pointer to 0x1 and then
-				 * write at 0x1. */
-				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
-
-				/* The stack cannot go beyond this location. This value is
-				 * programmed in the PSPLIM register on context switch.*/
-				xSecureContextHandle->pucStackLimit = pucStackMemory;
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Store the correct CONTROL value for the task on the stack.
-					 * This value is programmed in the CONTROL register on
-					 * context switch. */
-					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
-					pulCurrentStackPointer--;
-					if( ulIsTaskPrivileged )
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-					}
-					else
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-					}
-
-					/* Store the current stack pointer. This value is programmed in
-					 * the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
-				}
-				#else /* configENABLE_MPU */
-				{
-					/* Current SP is set to the starting of the stack. This
-					 * value programmed in the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
-
-				}
-				#endif /* configENABLE_MPU */
-			}
-			else
-			{
-				/* Free the context to avoid memory leak and make sure to return
-				 * NULL to indicate failure. */
-				vPortFree( xSecureContextHandle );
-				xSecureContextHandle = NULL;
-			}
-		}
-	}
-
-	return xSecureContextHandle;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Ensure that valid parameters are passed. */
-		secureportASSERT( xSecureContextHandle != NULL );
-
-		/* Free the stack space. */
-		vPortFree( xSecureContextHandle->pucStackLimit );
-
-		/* Free the context itself. */
-		vPortFree( xSecureContextHandle );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h b/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h
deleted file mode 100755
index e148bff..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_CONTEXT_H__
-#define __SECURE_CONTEXT_H__
-
-/* Standard includes. */
-#include 
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/**
- * @brief PSP value when no task's context is loaded.
- */
-#define securecontextNO_STACK	0x0
-
-/**
- * @brief Opaque handle.
- */
-struct SecureContext;
-typedef struct SecureContext*	SecureContextHandle_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Initializes the secure context management system.
- *
- * PSP is set to NULL and therefore a task must allocate and load a context
- * before calling any secure side function in the thread mode.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureContext_Init( void );
-
-/**
- * @brief Allocates a context on the secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
- * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
- *
- * @return Opaque context handle if context is successfully allocated, NULL
- * otherwise.
- */
-#if( configENABLE_MPU == 1 )
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
-#else /* configENABLE_MPU */
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
-#endif /* configENABLE_MPU */
-
-/**
- * @brief Frees the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the
- * context to be freed.
- */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Loads the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be loaded.
- */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Saves the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be saved.
- */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
-
-#endif /* __SECURE_CONTEXT_H__ */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c b/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c
deleted file mode 100755
index 619db1e..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/* Functions implemented in assembler file. */
-extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
-extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
-{
-	SecureContext_LoadContextAsm( xSecureContextHandle );
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
-{
-	SecureContext_SaveContextAsm( xSecureContextHandle );
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s b/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
deleted file mode 100755
index 65cee0c..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_context_port_asm.s
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-
-	PUBLIC SecureContext_LoadContextAsm
-	PUBLIC SecureContext_SaveContextAsm
-
-#if ( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-/*-----------------------------------------------------------*/
-
-SecureContext_LoadContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-#if ( configENABLE_MPU == 1 )
-	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	msr control, r3							/* CONTROL = r3. */
-#endif /* configENABLE_MPU */
-	msr psplim, r2							/* PSPLIM = r2. */
-	msr psp, r1								/* PSP = r1. */
-
-	load_ctx_therad_mode:
-		bx lr
-/*-----------------------------------------------------------*/
-
-SecureContext_SaveContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	mrs r1, psp								/* r1 = PSP. */
-#if ( configENABLE_MPU == 1 )
-	mrs r2, control							/* r2 = CONTROL. */
-	subs r1, r1, #4							/* Make space for the CONTROL value on the stack. */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	stmia r1!, {r2}							/* Store CONTROL value on the stack. */
-#else /* configENABLE_MPU */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-#endif /* configENABLE_MPU */
-	movs r1, #0								/* r1 = securecontextNO_STACK. */
-	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
-	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-
-	save_ctx_therad_mode:
-		bx lr
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c b/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
deleted file mode 100755
index 60fce5c..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure context heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Total heap size.
- */
-#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
-
-/* No test marker by default. */
-#ifndef mtCOVERAGE_TEST_MARKER
-	#define mtCOVERAGE_TEST_MARKER()
-#endif
-
-/* No tracing by default. */
-#ifndef traceMALLOC
-	#define traceMALLOC( pvReturn, xWantedSize )
-#endif
-
-/* No tracing by default. */
-#ifndef traceFREE
-	#define traceFREE( pv, xBlockSize )
-#endif
-
-/* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
-/*-----------------------------------------------------------*/
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	 * heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#else /* configAPPLICATION_ALLOCATED_HEAP */
-	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/**
- * @brief The linked list structure.
- *
- * This is used to link free blocks in order of their memory address.
- */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
-	size_t xBlockSize;						/**< The size of the free block. */
-} BlockLink_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Called automatically to setup the required heap structures the first
- * time pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/**
- * @brief Inserts a block of memory that is being freed into the correct
- * position in the list of free memory blocks.
- *
- * The block being freed will be merged with the block in front it and/or the
- * block behind it if the memory blocks are adjacent to each other.
- *
- * @param[in] pxBlockToInsert The block being freed.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The size of the structure placed at the beginning of each allocated
- * memory block must by correctly byte aligned.
- */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-
-/**
- * @brief Create a couple of list links to mark the start and end of the list.
- */
-static BlockLink_t xStart, *pxEnd = NULL;
-
-/**
- * @brief Keeps track of the number of free bytes remaining, but says nothing
- * about fragmentation.
- */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-size_t uxAddress;
-size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
-
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	uxAddress = ( size_t ) ucHeap;
-
-	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
-	{
-		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
-		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-	}
-
-	pucAlignedHeap = ( uint8_t * ) uxAddress;
-
-	/* xStart is used to hold a pointer to the first item in the list of free
-	 * blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
-
-	/* pxEnd is used to mark the end of the list of free blocks and is inserted
-	 * at the end of the heap space. */
-	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-	uxAddress -= xHeapStructSize;
-	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-	pxEnd = ( void * ) uxAddress;
-	pxEnd->xBlockSize = 0;
-	pxEnd->pxNextFreeBlock = NULL;
-
-	/* To start with there is a single free block that is sized to take up the
-	 * entire heap space, minus the space taken by pxEnd. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
-	/* Only one block exists - and it covers the entire usable heap space. */
-	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
-{
-BlockLink_t *pxIterator;
-uint8_t *puc;
-
-	/* Iterate through the list until a block is found that has a higher address
-	 * than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
-
-	/* Do the block being inserted, and the block it is being inserted after
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Do the block being inserted, and the block it is being inserted before
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
-
-	/* If the block being inserted plugged a gab, so was merged with the block
-	 * before and the block after, then it's pxNextFreeBlock pointer will have
-	 * already been set, and should not be set here as that would make it point
-	 * to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
-
-	/* If this is the first call to malloc then the heap will require
-	 * initialisation to setup the list of free blocks. */
-	if( pxEnd == NULL )
-	{
-		prvHeapInit();
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Check the requested block size is not so large that the top bit is set.
-	 * The top bit of the block size member of the BlockLink_t structure is used
-	 * to determine who owns the block - the application or the kernel, so it
-	 * must be free. */
-	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-	{
-		/* The wanted size is increased so it can contain a BlockLink_t
-		 * structure in addition to the requested amount of bytes. */
-		if( xWantedSize > 0 )
-		{
-			xWantedSize += xHeapStructSize;
-
-			/* Ensure that blocks are always aligned to the required number of
-			 * bytes. */
-			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
-			{
-				/* Byte alignment required. */
-				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-		{
-			/* Traverse the list from the start (lowest address) block until
-			 * one of adequate size is found. */
-			pxPreviousBlock = &xStart;
-			pxBlock = xStart.pxNextFreeBlock;
-			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-			{
-				pxPreviousBlock = pxBlock;
-				pxBlock = pxBlock->pxNextFreeBlock;
-			}
-
-			/* If the end marker was reached then a block of adequate size was
-			 * not found. */
-			if( pxBlock != pxEnd )
-			{
-				/* Return the memory space pointed to - jumping over the
-				 * BlockLink_t structure at its start. */
-				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-				/* This block is being returned for use so must be taken out
-				 * of the list of free blocks. */
-				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-				/* If the block is larger than required it can be split into
-				 * two. */
-				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
-				{
-					/* This block is to be split into two.  Create a new
-					 * block following the number of bytes requested. The void
-					 * cast is used to prevent byte alignment warnings from the
-					 * compiler. */
-					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-
-					/* Calculate the sizes of two blocks split from the single
-					 * block. */
-					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-					pxBlock->xBlockSize = xWantedSize;
-
-					/* Insert the new block into the list of free blocks. */
-					prvInsertBlockIntoFreeList( pxNewBlockLink );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-				{
-					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* The block is being returned - it is allocated and owned by
-				 * the application and has no "next" block. */
-				pxBlock->xBlockSize |= xBlockAllocatedBit;
-				pxBlock->pxNextFreeBlock = NULL;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	traceMALLOC( pvReturn, xWantedSize );
-
-	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
-
-	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		 * before it. */
-		puc -= xHeapStructSize;
-
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
-
-		/* Check the block is actually allocated. */
-		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
-
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				 * allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-				secureportDISABLE_NON_SECURE_INTERRUPTS();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				secureportENABLE_NON_SECURE_INTERRUPTS();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h b/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
deleted file mode 100755
index 69e4f2a..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_heap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_HEAP_H__
-#define __SECURE_HEAP_H__
-
-/* Standard includes. */
-#include 
-
-/**
- * @brief Allocates memory from heap.
- *
- * @param[in] xWantedSize The size of the memory to be allocated.
- *
- * @return Pointer to the memory region if the allocation is successful, NULL
- * otherwise.
- */
-void *pvPortMalloc( size_t xWantedSize );
-
-/**
- * @brief Frees the previously allocated memory.
- *
- * @param[in] pv Pointer to the memory to be freed.
- */
-void vPortFree( void *pv );
-
-#endif /* __SECURE_HEAP_H__ */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c b/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c
deleted file mode 100755
index c6525f7..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure init includes. */
-#include "secure_init.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS			( 29UL )
-#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS				( 26UL )
-#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
-
-#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS			( 10UL )
-#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS			( 11UL )
-#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
-									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
-									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
-		 * permitted. CP11 should be programmed to the same value as CP10. */
-		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
-
-		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
-		 * that we can enable/disable lazy stacking in port.c file. */
-		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
-
-		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
-		 * registers (S16-S31) are also pushed to stack on exception entry and
-		 * restored on exception return. */
-		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h b/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h
deleted file mode 100755
index 6c5bc71..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_init.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_INIT_H__
-#define __SECURE_INIT_H__
-
-/**
- * @brief De-prioritizes the non-secure exceptions.
- *
- * This is needed to ensure that the non-secure PendSV runs at the lowest
- * priority. Context switch is done in the non-secure PendSV handler.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_DePrioritizeNSExceptions( void );
-
-/**
- * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
- *
- * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
- * Registers are not leaked to the non-secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_EnableNSFPUAccess( void );
-
-#endif /* __SECURE_INIT_H__ */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h b/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
deleted file mode 100755
index 760edab..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23/secure/secure_port_macros.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_PORT_MACROS_H__
-#define __SECURE_PORT_MACROS_H__
-
-/**
- * @brief Byte alignment requirements.
- */
-#define secureportBYTE_ALIGNMENT					8
-#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
-
-/**
- * @brief Macro to declare a function as non-secure callable.
- */
-#if defined( __IAR_SYSTEMS_ICC__ )
-	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
-#else
-	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
-#endif
-
-/**
- * @brief Set the secure PRIMASK value.
- */
-#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Set the non-secure PRIMASK value.
- */
-#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Read the PSP value in the given variable.
- */
-#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
-	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
-
-/**
- * @brief Set the PSP to the given value.
- */
-#define secureportSET_PSP( pucCurrentStackPointer ) \
-	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
-
-/**
- * @brief Set the PSPLIM to the given value.
- */
-#define secureportSET_PSPLIM( pucStackLimit ) \
-	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
-
-/**
- * @brief Set the NonSecure MSP to the given value.
- */
-#define secureportSET_MSP_NS( pucMainStackPointer ) \
-	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
-
-/**
- * @brief Set the CONTROL register to the given value.
- */
-#define secureportSET_CONTROL( ulControl ) \
-	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
-
-/**
- * @brief Read the Interrupt Program Status Register (IPSR) value in the given
- * variable.
- */
-#define secureportREAD_IPSR( ulIPSR ) \
-	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
-
-/**
- * @brief PRIMASK value to enable interrupts.
- */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
-
-/**
- * @brief PRIMASK value to disable interrupts.
- */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
-
-/**
- * @brief Disable secure interrupts.
- */
-#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Disable non-secure interrupts.
- *
- * This effectively disables context switches.
- */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Enable non-secure interrupts.
- */
-#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Assert definition.
- */
-#define secureportASSERT( x )						\
-	if( ( x ) == 0 )								\
-	{												\
-		secureportDISABLE_SECURE_INTERRUPTS();		\
-		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
-		for( ;; );									\
-	}
-
-#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c b/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
deleted file mode 100755
index bd85a6f..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h b/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
deleted file mode 100755
index 2ecf04e..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s b/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
deleted file mode 100755
index 3121df6..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portasm.s
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	EXTERN pxCurrentTCB
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMaskFromISR
-	PUBLIC vClearInterruptMaskFromISR
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-
-#if ( configENABLE_FPU == 1 )
-	#error Cortex-M23 does not have a Floating Point Unit (FPU) and therefore configENABLE_FPU must be set to 0.
-#endif
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	movs r1, #1								/* r1 = 1. */
-	tst r0, r1								/* Perform r0 & r1 (bitwise AND) and update the conditions flag. */
-	beq running_privileged					/* If the result of previous AND operation was 0, branch. */
-	movs r0, #0								/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-	running_privileged:
-		movs r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-		bx lr								/* Return. */
-
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	movs r1, #1								/* r1 = 1. */
-	orrs r0, r1								/* r0 = r0 | r1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r1, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
-	movs r4, #1								/* r4 = 1. */
-	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
-	str r3, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
-	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str  r4, [r2]							/* Program MAIR0. */
-	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	movs r4, #4								/* r4 = 4. */
-	str  r4, [r2]							/* Program RNR = 4. */
-	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
-	movs r4, #5								/* r4 = 5. */
-	str  r4, [r2]							/* Program RNR = 5. */
-	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
-	movs r4, #6								/* r4 = 6. */
-	str  r4, [r2]							/* Program RNR = 6. */
-	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
-	movs r4, #7								/* r4 = 7. */
-	str  r4, [r2]							/* Program RNR = 7. */
-	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
-	movs r4, #1								/* r4 = 1. */
-	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
-	str r3, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	msr  control, r2						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r2									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs  r0, control						/* Read the CONTROL register. */
-	movs r1, #1								/* r1 = 1. */
-	bics r0, r1								/* Clear the bit 0. */
-	msr  control, r0						/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-	nop
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMaskFromISR:
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-/*-----------------------------------------------------------*/
-
-vClearInterruptMaskFromISR:
-	msr PRIMASK, r0
-	bx lr
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	mrs r0, psp								/* Read PSP in r0. */
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-#if ( configENABLE_MPU == 1 )
-	subs r0, r0, #44						/* Make space for PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-	str r0, [r1]							/* Save the new top of stack in TCB. */
-	mrs r1, psplim							/* r1 = PSPLIM. */
-	mrs r2, control							/* r2 = CONTROL. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r0!, {r1-r7}						/* Store on the stack - PSPLIM, CONTROL, LR and low registers that are not automatically saved. */
-	mov r4, r8								/* r4 = r8. */
-	mov r5, r9								/* r5 = r9. */
-	mov r6, r10								/* r6 = r10. */
-	mov r7, r11								/* r7 = r11. */
-	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
-#else /* configENABLE_MPU */
-	subs r0, r0, #40						/* Make space for PSPLIM, LR and the remaining registers on the stack. */
-	str r0, [r1]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r0!, {r2-r7}						/* Store on the stack - PSPLIM, LR and low registers that are not automatically saved. */
-	mov r4, r8								/* r4 = r8. */
-	mov r5, r9								/* r5 = r9. */
-	mov r6, r10								/* r6 = r10. */
-	mov r7, r11								/* r7 = r11. */
-	stmia r0!, {r4-r7}						/* Store the high registers that are not saved automatically. */
-#endif /* configENABLE_MPU */
-
-	cpsid i
-	bl vTaskSwitchContext
-	cpsie i
-
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
-	movs r4, #1								/* r4 = 1. */
-	bics r3, r4								/* r3 = r3 & ~r4 i.e. Clear the bit 0 in r3. */
-	str r3, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr  r4, [r1]							/* r4 = *r1 i.e. r4 = MAIR0. */
-	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str  r4, [r2]							/* Program MAIR0. */
-	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	movs r4, #4								/* r4 = 4. */
-	str  r4, [r2]							/* Program RNR = 4. */
-	ldmia r1!, {r5,r6}						/* Read first set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write first set of RBAR/RLAR registers. */
-	movs r4, #5								/* r4 = 5. */
-	str  r4, [r2]							/* Program RNR = 5. */
-	ldmia r1!, {r5,r6}						/* Read second set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write second set of RBAR/RLAR registers. */
-	movs r4, #6								/* r4 = 6. */
-	str  r4, [r2]							/* Program RNR = 6. */
-	ldmia r1!, {r5,r6}						/* Read third set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write third set of RBAR/RLAR registers. */
-	movs r4, #7								/* r4 = 7. */
-	str  r4, [r2]							/* Program RNR = 7. */
-	ldmia r1!, {r5,r6}						/* Read fourth set of RBAR/RLAR from TCB. */
-	ldr  r3, =0xe000ed9c					/* r3 = 0xe000ed9c [Location of RBAR]. */
-	stmia r3!, {r5,r6}						/* Write fourth set of RBAR/RLAR registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r3, [r2]							/* Read the value of MPU_CTRL. */
-	movs r4, #1								/* r4 = 1. */
-	orrs r3, r4								/* r3 = r3 | r4 i.e. Set the bit 0 in r3. */
-	str r3, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	adds r0, r0, #28						/* Move to the high registers. */
-	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
-	mov r8, r4								/* r8 = r4. */
-	mov r9, r5								/* r9 = r5. */
-	mov r10, r6								/* r10 = r6. */
-	mov r11, r7								/* r11 = r7. */
-	msr psp, r0								/* Remember the new top of stack for the task. */
-	subs r0, r0, #44						/* Move to the starting of the saved context. */
-	ldmia r0!, {r1-r7}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r7 restored. */
-	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
-	msr control, r2							/* Restore the CONTROL register value for the task. */
-	bx r3
-#else /* configENABLE_MPU */
-	adds r0, r0, #24						/* Move to the high registers. */
-	ldmia r0!, {r4-r7}						/* Restore the high registers that are not automatically restored. */
-	mov r8, r4								/* r8 = r4. */
-	mov r9, r5								/* r9 = r5. */
-	mov r10, r6								/* r10 = r6. */
-	mov r11, r7								/* r11 = r7. */
-	msr psp, r0								/* Remember the new top of stack for the task. */
-	subs r0, r0, #40						/* Move to the starting of the saved context. */
-	ldmia r0!, {r2-r7}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r7 restored. */
-	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
-	bx r3
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	movs r0, #4
-	mov r1, lr
-	tst r0, r1
-	beq stacking_used_msp
-	mrs r0, psp
-	b vPortSVCHandler_C
-	stacking_used_msp:
-		mrs r0, msp
-		b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
deleted file mode 100755
index 48b0e0b..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM23_NTZ/non_secure/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M23"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c b/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c
deleted file mode 100755
index bdbfdb7..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM3/port.c
+++ /dev/null
@@ -1,619 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM3 port.
- *----------------------------------------------------------*/
-
-/* IAR includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
-	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
-
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR			( 45UL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
-
-/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
-defined.  The value 255 should also ensure backward compatibility.
-FreeRTOS.org versions prior to V4.3.0 did not include this definition. */
-#ifndef configKERNEL_INTERRUPT_PRIORITY
-	#define configKERNEL_INTERRUPT_PRIORITY 255
-#endif
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortSysTickHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-extern void vPortStartFirstTask( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Start the first task. */
-	vPortStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known. */
-	portDISABLE_INTERRUPTS();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TICKLESS_IDLE == 1 )
-
-	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-	TickType_t xModifiableIdleTime;
-
-		/* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
-		is accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-		/* Calculate the reload value required to wait xExpectedIdleTime
-		tick periods.  -1 is used because this code will execute part way
-		through one of the tick periods. */
-		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-		if( ulReloadValue > ulStoppedTimerCompensation )
-		{
-			ulReloadValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Enter a critical section but don't use the taskENTER_CRITICAL()
-		method as that will mask interrupts that should exit sleep mode. */
-		__disable_interrupt();
-		__DSB();
-		__ISB();
-
-		/* If a context switch is pending or a task is waiting for the scheduler
-		to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-		{
-			/* Restart from whatever is left in the count register to complete
-			this tick period. */
-			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Reset the reload register to the value required for normal tick
-			periods. */
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Re-enable interrupts - see comments above __disable_interrupt()
-			call above. */
-			__enable_interrupt();
-		}
-		else
-		{
-			/* Set the new reload value. */
-			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-			/* Clear the SysTick count flag and set the count value back to
-			zero. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-			set its parameter to 0 to indicate that its implementation contains
-			its own wait for interrupt or wait for event instruction, and so wfi
-			should not be executed again.  However, the original expected idle
-			time variable must remain unmodified, so a copy is taken. */
-			xModifiableIdleTime = xExpectedIdleTime;
-			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-			if( xModifiableIdleTime > 0 )
-			{
-				__DSB();
-				__WFI();
-				__ISB();
-			}
-			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-			/* Re-enable interrupts to allow the interrupt that brought the MCU
-			out of sleep mode to execute immediately.  see comments above
-			__disable_interrupt() call above. */
-			__enable_interrupt();
-			__DSB();
-			__ISB();
-
-			/* Disable interrupts again because the clock is about to be stopped
-			and interrupts that execute while the clock is stopped will increase
-			any slippage between the time maintained by the RTOS and calendar
-			time. */
-			__disable_interrupt();
-			__DSB();
-			__ISB();
-			
-			/* Disable the SysTick clock without reading the 
-			portNVIC_SYSTICK_CTRL_REG register to ensure the
-			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again, 
-			the time the SysTick is stopped for is accounted for as best it can 
-			be, but using the tickless mode will inevitably result in some tiny 
-			drift of the time maintained by the kernel with respect to calendar 
-			time*/
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-			/* Determine if the SysTick clock has already counted to zero and
-			been set back to the current reload value (the reload back being
-			correct for the entire expected idle time) or if the SysTick is yet
-			to count to zero (in which case an interrupt other than the SysTick
-			must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-			{
-				uint32_t ulCalculatedLoadValue;
-
-				/* The tick interrupt is already pending, and the SysTick count
-				reloaded with ulReloadValue.  Reset the
-				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-				period. */
-				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-				/* Don't allow a tiny value, or values that have somehow
-				underflowed because the post sleep hook did something
-				that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-				{
-					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-				}
-
-				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-				/* As the pending tick will be processed as soon as this
-				function exits, the tick value maintained by the tick is stepped
-				forward by one less than the time spent waiting. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				Work out how long the sleep lasted rounded to complete tick
-				periods (not the ulReload value which accounted for part
-				ticks). */
-				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-				/* How many complete tick periods passed while the processor
-				was waiting? */
-				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-				/* The reload value is set to whatever fraction of a single tick
-				period remains. */
-				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-			}
-
-			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-			vTaskStepTick( ulCompleteTickPeriods );
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Exit with interrpts enabled. */
-			__enable_interrupt();
-		}
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__weak void vPortSetupTimerInterrupt( void )
-{
-	/* Calculate the constants required to configure the tick interrupt. */
-	#if( configUSE_TICKLESS_IDLE == 1 )
-	{
-		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-	}
-	#endif /* configUSE_TICKLESS_IDLE */
-
-	/* Stop and clear the SysTick. */
-	portNVIC_SYSTICK_CTRL_REG = 0UL;
-	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		/* Obtain the number of the currently executing interrupt. */
-		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s b/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s
deleted file mode 100755
index fbc278a..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM3/portasm.s
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include 
-
-	RSEG    CODE:CODE(2)
-	thumb
-
-	EXTERN pxCurrentTCB
-	EXTERN vTaskSwitchContext
-
-	PUBLIC xPortPendSVHandler
-	PUBLIC vPortSVCHandler
-	PUBLIC vPortStartFirstTask
-
-
-
-/*-----------------------------------------------------------*/
-
-xPortPendSVHandler:
-	mrs r0, psp
-	isb
-	ldr	r3, =pxCurrentTCB			/* Get the location of the current TCB. */
-	ldr	r2, [r3]
-
-	stmdb r0!, {r4-r11}				/* Save the remaining registers. */
-	str r0, [r2]					/* Save the new top of stack into the first member of the TCB. */
-
-	stmdb sp!, {r3, r14}
-	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-	msr basepri, r0
-	dsb
-	isb
-	bl vTaskSwitchContext
-	mov r0, #0
-	msr basepri, r0
-	ldmia sp!, {r3, r14}
-
-	ldr r1, [r3]
-	ldr r0, [r1]					/* The first item in pxCurrentTCB is the task top of stack. */
-	ldmia r0!, {r4-r11}				/* Pop the registers. */
-	msr psp, r0
-	isb
-	bx r14
-
-
-/*-----------------------------------------------------------*/
-
-vPortSVCHandler:
-	/* Get the location of the current TCB. */
-	ldr	r3, =pxCurrentTCB
-	ldr r1, [r3]
-	ldr r0, [r1]
-	/* Pop the core registers. */
-	ldmia r0!, {r4-r11}
-	msr psp, r0
-	isb
-	mov r0, #0
-	msr	basepri, r0
-	orr r14, r14, #13
-	bx r14
-
-/*-----------------------------------------------------------*/
-
-vPortStartFirstTask
-	/* Use the NVIC offset register to locate the stack. */
-	ldr r0, =0xE000ED08
-	ldr r0, [r0]
-	ldr r0, [r0]
-	/* Set the msp back to the start of the stack. */
-	msr msp, r0
-	/* Call SVC to start the first task, ensuring interrupts are enabled. */
-	cpsie i
-	cpsie f
-	dsb
-	isb
-	svc 0
-
-	END
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
deleted file mode 100755
index 1d69069..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM3/portmacro.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* IAR includes. */
-#include 
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-/* Compiler directives. */
-#define portWEAK_SYMBOL				__attribute__( ( weak ) )
-
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
-#define portYIELD()											\
-{															\
-	/* Set a PendSV to request a context switch. */			\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
-	__DSB();												\
-	__ISB();												\
-}
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()							\
-{															\
-	__set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
-	__DSB();												\
-	__ISB();												\
-}
-
-#define portENABLE_INTERRUPTS()					__set_BASEPRI( 0 )
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()		__get_BASEPRI(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	__set_BASEPRI( x )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-/*-----------------------------------------------------------*/
-
-/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
-the source code because to do so would cause other compilers to generate
-warnings. */
-#pragma diag_suppress=Pe191
-#pragma diag_suppress=Pa082
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c b/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c
deleted file mode 100755
index bd85a6f..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h b/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
deleted file mode 100755
index 2ecf04e..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s b/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
deleted file mode 100755
index e38104c..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portasm.s
+++ /dev/null
@@ -1,326 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	EXTERN pxCurrentTCB
-	EXTERN xSecureContext
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-	EXTERN SecureContext_SaveContext
-	EXTERN SecureContext_LoadContext
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vPortAllocateSecureContext
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMaskFromISR
-	PUBLIC vClearInterruptMaskFromISR
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-	PUBLIC vPortFreeSecureContext
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	ite ne
-	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	orr r0, r0, #1							/* r0 = r0 | 1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vPortAllocateSecureContext:
-	svc 0									/* Secure context is allocated in the supervisor call. portSVC_ALLOCATE_SECURE_CONTEXT = 0. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r3, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r3]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-	ldr  r4, [r3]							/* r4 = *r3 i.e. r4 = MAIR0. */
-	ldr  r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str  r4, [r2]							/* Program MAIR0. */
-	ldr  r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r4, #4								/* r4 = 4. */
-	str  r4, [r2]							/* Program RNR = 4. */
-	adds r3, #4								/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-	ldr  r2, =0xe000ed9c					/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r3!, {r4-r11}						/* Read 4 set of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r4}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = EXC_RETURN. */
-	ldr  r5, =xSecureContext
-	str  r1, [r5]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	msr  control, r3						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r4									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = xSecureContext, r2 = PSPLIM and r3 = EXC_RETURN. */
-	ldr  r4, =xSecureContext
-	str  r1, [r4]							/* Set xSecureContext to this task's value for the same. */
-	msr  psplim, r2							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs  r0, control						/* Read the CONTROL register. */
-	bic r0, r0, #1							/* Clear the bit 0. */
-	msr  control, r0						/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	cpsie f
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMaskFromISR:
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-/*-----------------------------------------------------------*/
-
-vClearInterruptMaskFromISR:
-	msr PRIMASK, r0
-	bx lr
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	mrs r1, psp								/* Read PSP in r1. */
-	ldr r2, =xSecureContext					/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-	ldr r0, [r2]							/* Read xSecureContext - Value of xSecureContext must be in r0 as it is used as a parameter later. */
-
-	cbz r0, save_ns_context					/* No secure context to save. */
-	push {r0-r2, r14}
-	bl SecureContext_SaveContext
-	pop {r0-r3}								/* LR is now in r3. */
-	mov lr, r3								/* LR = r3. */
-	lsls r2, r3, #25						/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-	bpl save_ns_context						/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-	ldr r3, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r2, [r3]							/* Read pxCurrentTCB. */
-#if ( configENABLE_MPU == 1 )
-	subs r1, r1, #16						/* Make space for xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mrs r3, control							/* r3 = CONTROL. */
-	mov r4, lr								/* r4 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-#else /* configENABLE_MPU */
-	subs r1, r1, #12						/* Make space for xSecureContext, PSPLIM and LR on the stack. */
-	str r1, [r2]							/* Save the new top of stack in TCB. */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmia r1!, {r0, r2-r3}					/* Store xSecureContext, PSPLIM and LR on the stack. */
-#endif /* configENABLE_MPU */
-	b select_next_task
-
-	save_ns_context:
-		ldr r3, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r2, [r3]						/* Read pxCurrentTCB. */
-	#if ( configENABLE_FPU == 1 )
-		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-		it eq
-		vstmdbeq r1!, {s16-s31}				/* Store the FPU registers which are not saved automatically. */
-	#endif /* configENABLE_FPU */
-	#if ( configENABLE_MPU == 1 )
-		subs r1, r1, #48					/* Make space for xSecureContext, PSPLIM, CONTROL, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #16					/* r1 = r1 + 16. */
-		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
-		mrs r3, control						/* r3 = CONTROL. */
-		mov r4, lr							/* r4 = LR/EXC_RETURN. */
-		subs r1, r1, #16					/* r1 = r1 - 16. */
-		stm r1, {r0, r2-r4}					/* Store xSecureContext, PSPLIM, CONTROL and LR on the stack. */
-	#else /* configENABLE_MPU */
-		subs r1, r1, #44					/* Make space for xSecureContext, PSPLIM, LR and the remaining registers on the stack. */
-		str r1, [r2]						/* Save the new top of stack in TCB. */
-		adds r1, r1, #12					/* r1 = r1 + 12. */
-		stm r1, {r4-r11}					/* Store the registers that are not saved automatically. */
-		mrs r2, psplim						/* r2 = PSPLIM. */
-		mov r3, lr							/* r3 = LR/EXC_RETURN. */
-		subs r1, r1, #12					/* r1 = r1 - 12. */
-		stmia r1!, {r0, r2-r3}				/* Store xSecureContext, PSPLIM and LR on the stack. */
-	#endif /* configENABLE_MPU */
-
-	select_next_task:
-		cpsid i
-		bl vTaskSwitchContext
-		cpsie i
-
-		ldr r2, =pxCurrentTCB				/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-		ldr r3, [r2]						/* Read pxCurrentTCB. */
-		ldr r1, [r3]						/* The first item in pxCurrentTCB is the task top of stack. r1 now points to the top of stack. */
-
-	#if ( configENABLE_MPU == 1 )
-		dmb									/* Complete outstanding transfers before disabling MPU. */
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
-		bic r4, r4, #1						/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-		str r4, [r2]						/* Disable MPU. */
-
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to MAIR0 in TCB. */
-		ldr r4, [r3]						/* r4 = *r3 i.e. r4 = MAIR0. */
-		ldr r2, =0xe000edc0					/* r2 = 0xe000edc0 [Location of MAIR0]. */
-		str r4, [r2]						/* Program MAIR0. */
-		ldr r2, =0xe000ed98					/* r2 = 0xe000ed98 [Location of RNR]. */
-		movs r4, #4							/* r4 = 4. */
-		str r4, [r2]						/* Program RNR = 4. */
-		adds r3, #4							/* r3 = r3 + 4. r3 now points to first RBAR in TCB. */
-		ldr  r2, =0xe000ed9c				/* r2 = 0xe000ed9c [Location of RBAR]. */
-		ldmia r3!, {r4-r11}					/* Read 4 sets of RBAR/RLAR registers from TCB. */
-		stmia r2!, {r4-r11}					/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-		ldr r2, =0xe000ed94					/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-		ldr r4, [r2]						/* Read the value of MPU_CTRL. */
-		orr r4, r4, #1						/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-		str r4, [r2]						/* Enable MPU. */
-		dsb									/* Force memory writes before continuing. */
-	#endif /* configENABLE_MPU */
-
-	#if ( configENABLE_MPU == 1 )
-		ldmia r1!, {r0, r2-r4}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM, r3 = CONTROL and r4 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		msr control, r3						/* Restore the CONTROL register value for the task. */
-		mov lr, r4							/* LR = r4. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r4}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r4}
-		mov lr, r4							/* LR = r4. */
-		lsls r2, r4, #25					/* r2 = r4 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-	#else /* configENABLE_MPU */
-		ldmia r1!, {r0, r2-r3}				/* Read from stack - r0 = xSecureContext, r2 = PSPLIM and r3 = LR. */
-		msr psplim, r2						/* Restore the PSPLIM register value for the task. */
-		mov lr, r3							/* LR = r3. */
-		ldr r2, =xSecureContext				/* Read the location of xSecureContext i.e. &( xSecureContext ). */
-		str r0, [r2]						/* Restore the task's xSecureContext. */
-		cbz r0, restore_ns_context			/* If there is no secure context for the task, restore the non-secure context. */
-		push {r1,r3}
-		bl SecureContext_LoadContext		/* Restore the secure context. */
-		pop {r1,r3}
-		mov lr, r3							/* LR = r3. */
-		lsls r2, r3, #25					/* r2 = r3 << 25. Bit[6] of EXC_RETURN is 1 if secure stack was used, 0 if non-secure stack was used to store stack frame. */
-		bpl restore_ns_context				/* bpl - branch if positive or zero. If r2 >= 0 ==> Bit[6] in EXC_RETURN is 0 i.e. non-secure stack was used. */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-	#endif /* configENABLE_MPU */
-
-	restore_ns_context:
-		ldmia r1!, {r4-r11}					/* Restore the registers that are not automatically restored. */
-	#if ( configENABLE_FPU == 1 )
-		tst lr, #0x10						/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-		it eq
-		vldmiaeq r1!, {s16-s31}				/* Restore the FPU registers which are not restored automatically. */
-	#endif /* configENABLE_FPU */
-		msr psp, r1							/* Remember the new top of stack for the task. */
-		bx lr
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	tst lr, #4
-	ite eq
-	mrseq r0, msp
-	mrsne r0, psp
-	b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-vPortFreeSecureContext:
-	/* r0 = uint32_t *pulTCB. */
-	ldr r1, [r0]							/* The first item in the TCB is the top of the stack. */
-	ldr r0, [r1]							/* The first item on the stack is the task's xSecureContext. */
-	cmp r0, #0								/* Raise svc if task's xSecureContext is not NULL. */
-	it ne
-	svcne 1									/* Secure context is freed in the supervisor call. portSVC_FREE_SECURE_CONTEXT = 1. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
deleted file mode 100755
index aba3daf..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33/non_secure/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c b/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c
deleted file mode 100755
index 53535cd..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.c
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief CONTROL value for privileged tasks.
- *
- * Bit[0] - 0 --> Thread mode is privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_PRIVILEGED		0x02
-
-/**
- * @brief CONTROL value for un-privileged tasks.
- *
- * Bit[0] - 1 --> Thread mode is un-privileged.
- * Bit[1] - 1 --> Thread mode uses PSP.
- */
-#define securecontextCONTROL_VALUE_UNPRIVILEGED		0x03
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Structure to represent secure context.
- *
- * @note Since stack grows down, pucStackStart is the highest address while
- * pucStackLimit is the first addess of the allocated memory.
- */
-typedef struct SecureContext
-{
-	uint8_t *pucCurrentStackPointer;	/**< Current value of stack pointer (PSP). */
-	uint8_t *pucStackLimit;				/**< Last location of the stack memory (PSPLIM). */
-	uint8_t *pucStackStart;				/**< First location of the stack memory. */
-} SecureContext_t;
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_Init( void )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* No stack for thread mode until a task's context is loaded. */
-		secureportSET_PSPLIM( securecontextNO_STACK );
-		secureportSET_PSP( securecontextNO_STACK );
-
-		#if( configENABLE_MPU == 1 )
-		{
-			/* Configure thread mode to use PSP and to be unprivileged. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_UNPRIVILEGED );
-		}
-		#else /* configENABLE_MPU */
-		{
-			/* Configure thread mode to use PSP and to be privileged.. */
-			secureportSET_CONTROL( securecontextCONTROL_VALUE_PRIVILEGED );
-		}
-		#endif /* configENABLE_MPU */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged )
-#else /* configENABLE_MPU */
-	secureportNON_SECURE_CALLABLE SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize )
-#endif /* configENABLE_MPU */
-{
-	uint8_t *pucStackMemory = NULL;
-	uint32_t ulIPSR;
-	SecureContextHandle_t xSecureContextHandle = NULL;
-	#if( configENABLE_MPU == 1 )
-		uint32_t *pulCurrentStackPointer = NULL;
-	#endif /* configENABLE_MPU */
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Allocate the context structure. */
-		xSecureContextHandle = ( SecureContextHandle_t ) pvPortMalloc( sizeof( SecureContext_t ) );
-
-		if( xSecureContextHandle != NULL )
-		{
-			/* Allocate the stack space. */
-			pucStackMemory = pvPortMalloc( ulSecureStackSize );
-
-			if( pucStackMemory != NULL )
-			{
-				/* Since stack grows down, the starting point will be the last
-				 * location. Note that this location is next to the last
-				 * allocated byte because the hardware decrements the stack
-				 * pointer before writing i.e. if stack pointer is 0x2, a push
-				 * operation will decrement the stack pointer to 0x1 and then
-				 * write at 0x1. */
-				xSecureContextHandle->pucStackStart = pucStackMemory + ulSecureStackSize;
-
-				/* The stack cannot go beyond this location. This value is
-				 * programmed in the PSPLIM register on context switch.*/
-				xSecureContextHandle->pucStackLimit = pucStackMemory;
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Store the correct CONTROL value for the task on the stack.
-					 * This value is programmed in the CONTROL register on
-					 * context switch. */
-					pulCurrentStackPointer = ( uint32_t * ) xSecureContextHandle->pucStackStart;
-					pulCurrentStackPointer--;
-					if( ulIsTaskPrivileged )
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_PRIVILEGED;
-					}
-					else
-					{
-						*( pulCurrentStackPointer ) = securecontextCONTROL_VALUE_UNPRIVILEGED;
-					}
-
-					/* Store the current stack pointer. This value is programmed in
-					 * the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = ( uint8_t * ) pulCurrentStackPointer;
-				}
-				#else /* configENABLE_MPU */
-				{
-					/* Current SP is set to the starting of the stack. This
-					 * value programmed in the PSP register on context switch. */
-					xSecureContextHandle->pucCurrentStackPointer = xSecureContextHandle->pucStackStart;
-
-				}
-				#endif /* configENABLE_MPU */
-			}
-			else
-			{
-				/* Free the context to avoid memory leak and make sure to return
-				 * NULL to indicate failure. */
-				vPortFree( xSecureContextHandle );
-				xSecureContextHandle = NULL;
-			}
-		}
-	}
-
-	return xSecureContextHandle;
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle )
-{
-	uint32_t ulIPSR;
-
-	/* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* Ensure that valid parameters are passed. */
-		secureportASSERT( xSecureContextHandle != NULL );
-
-		/* Free the stack space. */
-		vPortFree( xSecureContextHandle->pucStackLimit );
-
-		/* Free the context itself. */
-		vPortFree( xSecureContextHandle );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h b/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h
deleted file mode 100755
index e148bff..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_CONTEXT_H__
-#define __SECURE_CONTEXT_H__
-
-/* Standard includes. */
-#include 
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-
-/**
- * @brief PSP value when no task's context is loaded.
- */
-#define securecontextNO_STACK	0x0
-
-/**
- * @brief Opaque handle.
- */
-struct SecureContext;
-typedef struct SecureContext*	SecureContextHandle_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Initializes the secure context management system.
- *
- * PSP is set to NULL and therefore a task must allocate and load a context
- * before calling any secure side function in the thread mode.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureContext_Init( void );
-
-/**
- * @brief Allocates a context on the secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] ulSecureStackSize Size of the stack to allocate on secure side.
- * @param[in] ulIsTaskPrivileged 1 if the calling task is privileged, 0 otherwise.
- *
- * @return Opaque context handle if context is successfully allocated, NULL
- * otherwise.
- */
-#if( configENABLE_MPU == 1 )
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize, uint32_t ulIsTaskPrivileged );
-#else /* configENABLE_MPU */
-	SecureContextHandle_t SecureContext_AllocateContext( uint32_t ulSecureStackSize );
-#endif /* configENABLE_MPU */
-
-/**
- * @brief Frees the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the
- * context to be freed.
- */
-void SecureContext_FreeContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Loads the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be loaded.
- */
-void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle );
-
-/**
- * @brief Saves the given context.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- *
- * @param[in] xSecureContextHandle Context handle corresponding to the context
- * to be saved.
- */
-void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle );
-
-#endif /* __SECURE_CONTEXT_H__ */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c b/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c
deleted file mode 100755
index 619db1e..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Secure context includes. */
-#include "secure_context.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/* Functions implemented in assembler file. */
-extern void SecureContext_LoadContextAsm( SecureContextHandle_t xSecureContextHandle );
-extern void SecureContext_SaveContextAsm( SecureContextHandle_t xSecureContextHandle );
-
-secureportNON_SECURE_CALLABLE void SecureContext_LoadContext( SecureContextHandle_t xSecureContextHandle )
-{
-	SecureContext_LoadContextAsm( xSecureContextHandle );
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureContext_SaveContext( SecureContextHandle_t xSecureContextHandle )
-{
-	SecureContext_SaveContextAsm( xSecureContextHandle );
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s b/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
deleted file mode 100755
index 0cbfe6e..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_context_port_asm.s
+++ /dev/null
@@ -1,73 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-
-	PUBLIC SecureContext_LoadContextAsm
-	PUBLIC SecureContext_SaveContextAsm
-/*-----------------------------------------------------------*/
-
-SecureContext_LoadContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, load_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	ldmia r0!, {r1, r2}						/* r1 = xSecureContextHandle->pucCurrentStackPointer, r2 = xSecureContextHandle->pucStackLimit. */
-#if ( configENABLE_MPU == 1 )
-	ldmia r1!, {r3}							/* Read CONTROL register value from task's stack. r3 = CONTROL. */
-	msr control, r3							/* CONTROL = r3. */
-#endif /* configENABLE_MPU */
-	msr psplim, r2							/* PSPLIM = r2. */
-	msr psp, r1								/* PSP = r1. */
-
-	load_ctx_therad_mode:
-		bx lr
-/*-----------------------------------------------------------*/
-
-SecureContext_SaveContextAsm:
-	/* xSecureContextHandle value is in r0. */
-	mrs r1, ipsr							/* r1 = IPSR. */
-	cbz r1, save_ctx_therad_mode			/* Do nothing if the processor is running in the Thread Mode. */
-	mrs r1, psp								/* r1 = PSP. */
-#if ( configENABLE_FPU == 1 )
-	vstmdb r1!, {s0}						/* Trigger the defferred stacking of FPU registers. */
-	vldmia r1!, {s0}						/* Nullify the effect of the pervious statement. */
-#endif /* configENABLE_FPU */
-#if ( configENABLE_MPU == 1 )
-	mrs r2, control							/* r2 = CONTROL. */
-	stmdb r1!, {r2}							/* Store CONTROL value on the stack. */
-#endif /* configENABLE_MPU */
-	str r1, [r0]							/* Save the top of stack in context. xSecureContextHandle->pucCurrentStackPointer = r1. */
-	movs r1, #0								/* r1 = securecontextNO_STACK. */
-	msr psplim, r1							/* PSPLIM = securecontextNO_STACK. */
-	msr psp, r1								/* PSP = securecontextNO_STACK i.e. No stack for thread mode until next task's context is loaded. */
-
-	save_ctx_therad_mode:
-		bx lr
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c b/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
deleted file mode 100755
index 60fce5c..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.c
+++ /dev/null
@@ -1,450 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure context heap includes. */
-#include "secure_heap.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Total heap size.
- */
-#define secureconfigTOTAL_HEAP_SIZE		( ( ( size_t ) ( 10 * 1024 ) ) )
-
-/* No test marker by default. */
-#ifndef mtCOVERAGE_TEST_MARKER
-	#define mtCOVERAGE_TEST_MARKER()
-#endif
-
-/* No tracing by default. */
-#ifndef traceMALLOC
-	#define traceMALLOC( pvReturn, xWantedSize )
-#endif
-
-/* No tracing by default. */
-#ifndef traceFREE
-	#define traceFREE( pv, xBlockSize )
-#endif
-
-/* Block sizes must not get too small. */
-#define secureheapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define secureheapBITS_PER_BYTE			( ( size_t ) 8 )
-/*-----------------------------------------------------------*/
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	 * heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#else /* configAPPLICATION_ALLOCATED_HEAP */
-	static uint8_t ucHeap[ secureconfigTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/**
- * @brief The linked list structure.
- *
- * This is used to link free blocks in order of their memory address.
- */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/**< The next free block in the list. */
-	size_t xBlockSize;						/**< The size of the free block. */
-} BlockLink_t;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Called automatically to setup the required heap structures the first
- * time pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/**
- * @brief Inserts a block of memory that is being freed into the correct
- * position in the list of free memory blocks.
- *
- * The block being freed will be merged with the block in front it and/or the
- * block behind it if the memory blocks are adjacent to each other.
- *
- * @param[in] pxBlockToInsert The block being freed.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
-/*-----------------------------------------------------------*/
-
-/**
- * @brief The size of the structure placed at the beginning of each allocated
- * memory block must by correctly byte aligned.
- */
-static const size_t xHeapStructSize = ( sizeof( BlockLink_t ) + ( ( size_t ) ( secureportBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-
-/**
- * @brief Create a couple of list links to mark the start and end of the list.
- */
-static BlockLink_t xStart, *pxEnd = NULL;
-
-/**
- * @brief Keeps track of the number of free bytes remaining, but says nothing
- * about fragmentation.
- */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/**
- * @brief Gets set to the top bit of an size_t type.
- *
- * When this bit in the xBlockSize member of an BlockLink_t structure is set
- * then the block belongs to the application. When the bit is free the block is
- * still part of the free heap space.
- */
-static size_t xBlockAllocatedBit = 0;
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-size_t uxAddress;
-size_t xTotalHeapSize = secureconfigTOTAL_HEAP_SIZE;
-
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	uxAddress = ( size_t ) ucHeap;
-
-	if( ( uxAddress & secureportBYTE_ALIGNMENT_MASK ) != 0 )
-	{
-		uxAddress += ( secureportBYTE_ALIGNMENT - 1 );
-		uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-	}
-
-	pucAlignedHeap = ( uint8_t * ) uxAddress;
-
-	/* xStart is used to hold a pointer to the first item in the list of free
-	 * blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
-
-	/* pxEnd is used to mark the end of the list of free blocks and is inserted
-	 * at the end of the heap space. */
-	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-	uxAddress -= xHeapStructSize;
-	uxAddress &= ~( ( size_t ) secureportBYTE_ALIGNMENT_MASK );
-	pxEnd = ( void * ) uxAddress;
-	pxEnd->xBlockSize = 0;
-	pxEnd->pxNextFreeBlock = NULL;
-
-	/* To start with there is a single free block that is sized to take up the
-	 * entire heap space, minus the space taken by pxEnd. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
-	/* Only one block exists - and it covers the entire usable heap space. */
-	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * secureheapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
-{
-BlockLink_t *pxIterator;
-uint8_t *puc;
-
-	/* Iterate through the list until a block is found that has a higher address
-	 * than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
-
-	/* Do the block being inserted, and the block it is being inserted after
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Do the block being inserted, and the block it is being inserted before
-	 * make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
-
-	/* If the block being inserted plugged a gab, so was merged with the block
-	 * before and the block after, then it's pxNextFreeBlock pointer will have
-	 * already been set, and should not be set here as that would make it point
-	 * to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
-
-	/* If this is the first call to malloc then the heap will require
-	 * initialisation to setup the list of free blocks. */
-	if( pxEnd == NULL )
-	{
-		prvHeapInit();
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Check the requested block size is not so large that the top bit is set.
-	 * The top bit of the block size member of the BlockLink_t structure is used
-	 * to determine who owns the block - the application or the kernel, so it
-	 * must be free. */
-	if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-	{
-		/* The wanted size is increased so it can contain a BlockLink_t
-		 * structure in addition to the requested amount of bytes. */
-		if( xWantedSize > 0 )
-		{
-			xWantedSize += xHeapStructSize;
-
-			/* Ensure that blocks are always aligned to the required number of
-			 * bytes. */
-			if( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) != 0x00 )
-			{
-				/* Byte alignment required. */
-				xWantedSize += ( secureportBYTE_ALIGNMENT - ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) );
-				secureportASSERT( ( xWantedSize & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-		{
-			/* Traverse the list from the start (lowest address) block until
-			 * one of adequate size is found. */
-			pxPreviousBlock = &xStart;
-			pxBlock = xStart.pxNextFreeBlock;
-			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-			{
-				pxPreviousBlock = pxBlock;
-				pxBlock = pxBlock->pxNextFreeBlock;
-			}
-
-			/* If the end marker was reached then a block of adequate size was
-			 * not found. */
-			if( pxBlock != pxEnd )
-			{
-				/* Return the memory space pointed to - jumping over the
-				 * BlockLink_t structure at its start. */
-				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-				/* This block is being returned for use so must be taken out
-				 * of the list of free blocks. */
-				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-				/* If the block is larger than required it can be split into
-				 * two. */
-				if( ( pxBlock->xBlockSize - xWantedSize ) > secureheapMINIMUM_BLOCK_SIZE )
-				{
-					/* This block is to be split into two.  Create a new
-					 * block following the number of bytes requested. The void
-					 * cast is used to prevent byte alignment warnings from the
-					 * compiler. */
-					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-					secureportASSERT( ( ( ( size_t ) pxNewBlockLink ) & secureportBYTE_ALIGNMENT_MASK ) == 0 );
-
-					/* Calculate the sizes of two blocks split from the single
-					 * block. */
-					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-					pxBlock->xBlockSize = xWantedSize;
-
-					/* Insert the new block into the list of free blocks. */
-					prvInsertBlockIntoFreeList( pxNewBlockLink );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-				if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-				{
-					xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* The block is being returned - it is allocated and owned by
-				 * the application and has no "next" block. */
-				pxBlock->xBlockSize |= xBlockAllocatedBit;
-				pxBlock->pxNextFreeBlock = NULL;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	traceMALLOC( pvReturn, xWantedSize );
-
-	#if( secureconfigUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
-
-	secureportASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) secureportBYTE_ALIGNMENT_MASK ) == 0 );
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		 * before it. */
-		puc -= xHeapStructSize;
-
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
-
-		/* Check the block is actually allocated. */
-		secureportASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		secureportASSERT( pxLink->pxNextFreeBlock == NULL );
-
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				 * allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-				secureportDISABLE_NON_SECURE_INTERRUPTS();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				secureportENABLE_NON_SECURE_INTERRUPTS();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h b/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
deleted file mode 100755
index 69e4f2a..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_heap.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_HEAP_H__
-#define __SECURE_HEAP_H__
-
-/* Standard includes. */
-#include 
-
-/**
- * @brief Allocates memory from heap.
- *
- * @param[in] xWantedSize The size of the memory to be allocated.
- *
- * @return Pointer to the memory region if the allocation is successful, NULL
- * otherwise.
- */
-void *pvPortMalloc( size_t xWantedSize );
-
-/**
- * @brief Frees the previously allocated memory.
- *
- * @param[in] pv Pointer to the memory to be freed.
- */
-void vPortFree( void *pv );
-
-#endif /* __SECURE_HEAP_H__ */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c b/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c
deleted file mode 100755
index c6525f7..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Secure init includes. */
-#include "secure_init.h"
-
-/* Secure port macros. */
-#include "secure_port_macros.h"
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define secureinitSCB_AIRCR					( ( volatile uint32_t * ) 0xe000ed0c )  /* Application Interrupt and Reset Control Register. */
-#define secureinitSCB_AIRCR_VECTKEY_POS		( 16UL )
-#define secureinitSCB_AIRCR_VECTKEY_MASK	( 0xFFFFUL << secureinitSCB_AIRCR_VECTKEY_POS )
-#define secureinitSCB_AIRCR_PRIS_POS		( 14UL )
-#define secureinitSCB_AIRCR_PRIS_MASK		( 1UL << secureinitSCB_AIRCR_PRIS_POS )
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define secureinitFPCCR						( ( volatile uint32_t * ) 0xe000ef34 )  /* Floating Point Context Control Register. */
-#define secureinitFPCCR_LSPENS_POS			( 29UL )
-#define secureinitFPCCR_LSPENS_MASK			( 1UL << secureinitFPCCR_LSPENS_POS )
-#define secureinitFPCCR_TS_POS				( 26UL )
-#define secureinitFPCCR_TS_MASK				( 1UL << secureinitFPCCR_TS_POS )
-
-#define secureinitNSACR						( ( volatile uint32_t * ) 0xe000ed8c )  /* Non-secure Access Control Register. */
-#define secureinitNSACR_CP10_POS			( 10UL )
-#define secureinitNSACR_CP10_MASK			( 1UL << secureinitNSACR_CP10_POS )
-#define secureinitNSACR_CP11_POS			( 11UL )
-#define secureinitNSACR_CP11_MASK			( 1UL << secureinitNSACR_CP11_POS )
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_DePrioritizeNSExceptions( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		*( secureinitSCB_AIRCR ) =	( *( secureinitSCB_AIRCR ) & ~( secureinitSCB_AIRCR_VECTKEY_MASK | secureinitSCB_AIRCR_PRIS_MASK ) ) |
-									( ( 0x05FAUL << secureinitSCB_AIRCR_VECTKEY_POS ) & secureinitSCB_AIRCR_VECTKEY_MASK ) |
-									( ( 0x1UL	<< secureinitSCB_AIRCR_PRIS_POS )	& secureinitSCB_AIRCR_PRIS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
-
-secureportNON_SECURE_CALLABLE void SecureInit_EnableNSFPUAccess( void )
-{
-	uint32_t ulIPSR;
-
-	 /* Read the Interrupt Program Status Register (IPSR) value. */
-	secureportREAD_IPSR( ulIPSR );
-
-	/* Do nothing if the processor is running in the Thread Mode. IPSR is zero
-	 * when the processor is running in the Thread Mode. */
-	if( ulIPSR != 0 )
-	{
-		/* CP10 = 1 ==> Non-secure access to the Floating Point Unit is
-		 * permitted. CP11 should be programmed to the same value as CP10. */
-		*( secureinitNSACR ) |= ( secureinitNSACR_CP10_MASK | secureinitNSACR_CP11_MASK );
-
-		/* LSPENS = 0 ==> LSPEN is writable fron non-secure state. This ensures
-		 * that we can enable/disable lazy stacking in port.c file. */
-		*( secureinitFPCCR ) &= ~ ( secureinitFPCCR_LSPENS_MASK );
-
-		/* TS = 1 ==> Treat FP registers as secure i.e. callee saved FP
-		 * registers (S16-S31) are also pushed to stack on exception entry and
-		 * restored on exception return. */
-		*( secureinitFPCCR ) |= ( secureinitFPCCR_TS_MASK );
-	}
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h b/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h
deleted file mode 100755
index 6c5bc71..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_init.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_INIT_H__
-#define __SECURE_INIT_H__
-
-/**
- * @brief De-prioritizes the non-secure exceptions.
- *
- * This is needed to ensure that the non-secure PendSV runs at the lowest
- * priority. Context switch is done in the non-secure PendSV handler.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_DePrioritizeNSExceptions( void );
-
-/**
- * @brief Sets up the Floating Point Unit (FPU) for Non-Secure access.
- *
- * Also sets FPCCR.TS=1 to ensure that the content of the Floating Point
- * Registers are not leaked to the non-secure side.
- *
- * @note This function must be called in the handler mode. It is no-op if called
- * in the thread mode.
- */
-void SecureInit_EnableNSFPUAccess( void );
-
-#endif /* __SECURE_INIT_H__ */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h b/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
deleted file mode 100755
index 760edab..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33/secure/secure_port_macros.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __SECURE_PORT_MACROS_H__
-#define __SECURE_PORT_MACROS_H__
-
-/**
- * @brief Byte alignment requirements.
- */
-#define secureportBYTE_ALIGNMENT					8
-#define secureportBYTE_ALIGNMENT_MASK				( 0x0007 )
-
-/**
- * @brief Macro to declare a function as non-secure callable.
- */
-#if defined( __IAR_SYSTEMS_ICC__ )
-	#define secureportNON_SECURE_CALLABLE			__cmse_nonsecure_entry __root
-#else
-	#define secureportNON_SECURE_CALLABLE			__attribute__((cmse_nonsecure_entry)) __attribute__((used))
-#endif
-
-/**
- * @brief Set the secure PRIMASK value.
- */
-#define secureportSET_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Set the non-secure PRIMASK value.
- */
-#define secureportSET_NON_SECURE_PRIMASK( ulPrimaskValue ) \
-	__asm volatile ( "msr primask_ns, %0" : : "r" ( ulPrimaskValue ) : "memory" )
-
-/**
- * @brief Read the PSP value in the given variable.
- */
-#define secureportREAD_PSP( pucOutCurrentStackPointer ) \
-	__asm volatile ( "mrs %0, psp"  : "=r" ( pucOutCurrentStackPointer ) )
-
-/**
- * @brief Set the PSP to the given value.
- */
-#define secureportSET_PSP( pucCurrentStackPointer ) \
-	__asm volatile ( "msr psp, %0" : : "r" ( pucCurrentStackPointer ) )
-
-/**
- * @brief Set the PSPLIM to the given value.
- */
-#define secureportSET_PSPLIM( pucStackLimit ) \
-	__asm volatile ( "msr psplim, %0" : : "r" ( pucStackLimit ) )
-
-/**
- * @brief Set the NonSecure MSP to the given value.
- */
-#define secureportSET_MSP_NS( pucMainStackPointer ) \
-	__asm volatile ( "msr msp_ns, %0" : : "r" ( pucMainStackPointer ) )
-
-/**
- * @brief Set the CONTROL register to the given value.
- */
-#define secureportSET_CONTROL( ulControl ) \
-	__asm volatile ( "msr control, %0" : : "r" ( ulControl ) : "memory" )
-
-/**
- * @brief Read the Interrupt Program Status Register (IPSR) value in the given
- * variable.
- */
-#define secureportREAD_IPSR( ulIPSR ) \
-	__asm volatile ( "mrs %0, ipsr"  : "=r" ( ulIPSR ) )
-
-/**
- * @brief PRIMASK value to enable interrupts.
- */
-#define secureportPRIMASK_ENABLE_INTERRUPTS_VAL		0
-
-/**
- * @brief PRIMASK value to disable interrupts.
- */
-#define secureportPRIMASK_DISABLE_INTERRUPTS_VAL	1
-
-/**
- * @brief Disable secure interrupts.
- */
-#define secureportDISABLE_SECURE_INTERRUPTS()		secureportSET_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Disable non-secure interrupts.
- *
- * This effectively disables context switches.
- */
-#define secureportDISABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_DISABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Enable non-secure interrupts.
- */
-#define secureportENABLE_NON_SECURE_INTERRUPTS()	secureportSET_NON_SECURE_PRIMASK( secureportPRIMASK_ENABLE_INTERRUPTS_VAL )
-
-/**
- * @brief Assert definition.
- */
-#define secureportASSERT( x )						\
-	if( ( x ) == 0 )								\
-	{												\
-		secureportDISABLE_SECURE_INTERRUPTS();		\
-		secureportDISABLE_NON_SECURE_INTERRUPTS();	\
-		for( ;; );									\
-	}
-
-#endif /* __SECURE_PORT_MACROS_H__ */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c b/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
deleted file mode 100755
index bd85a6f..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/port.c
+++ /dev/null
@@ -1,899 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
- * all the API functions to use the MPU wrappers. That should only be done when
- * task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/* Portasm includes. */
-#include "portasm.h"
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/* Secure components includes. */
-	#include "secure_context.h"
-	#include "secure_init.h"
-#endif /* configENABLE_TRUSTZONE */
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/**
- * The FreeRTOS Cortex M33 port can be configured to run on the Secure Side only
- * i.e. the processor boots as secure and never jumps to the non-secure side.
- * The Trust Zone support in the port must be disabled in order to run FreeRTOS
- * on the secure side. The following are the valid configuration seetings:
- *
- * 1. Run FreeRTOS on the Secure Side:
- *		configRUN_FREERTOS_SECURE_ONLY = 1 and configENABLE_TRUSTZONE = 0
- *
- * 2. Run FreeRTOS on the Non-Secure Side with Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 1
- *
- * 3. Run FreeRTOS on the Non-Secure Side only i.e. no Secure Side function call support:
- *		configRUN_FREERTOS_SECURE_ONLY = 0 and configENABLE_TRUSTZONE = 0
- */
-#if( ( configRUN_FREERTOS_SECURE_ONLY == 1 ) && ( configENABLE_TRUSTZONE == 1 ) )
-	#error TrustZone needs to be disabled in order to run FreeRTOS on the Secure Side.
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the NVIC.
- */
-#define portNVIC_SYSTICK_CTRL				( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD				( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE		( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL					( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_SYSPRI2					( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK				( 0x00000004 )
-#define portNVIC_SYSTICK_INT				( 0x00000002 )
-#define portNVIC_SYSTICK_ENABLE				( 0x00000001 )
-#define portNVIC_PENDSVSET					( 0x10000000 )
-#define portMIN_INTERRUPT_PRIORITY			( 255UL )
-#define portNVIC_PENDSV_PRI					( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI				( portMIN_INTERRUPT_PRIORITY << 24UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the SCB.
- */
-#define portSCB_SYS_HANDLER_CTRL_STATE_REG	( * ( volatile uint32_t * ) 0xe000ed24 )
-#define portSCB_MEM_FAULT_ENABLE			( 1UL << 16UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the FPU.
- */
-#define portCPACR							( ( volatile uint32_t * ) 0xe000ed88 )	/* Coprocessor Access Control Register. */
-#define portCPACR_CP10_VALUE				( 3UL )
-#define portCPACR_CP11_VALUE				portCPACR_CP10_VALUE
-#define portCPACR_CP10_POS					( 20UL )
-#define portCPACR_CP11_POS					( 22UL )
-
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 )	/* Floating Point Context Control Register. */
-#define portFPCCR_ASPEN_POS					( 31UL )
-#define portFPCCR_ASPEN_MASK				( 1UL << portFPCCR_ASPEN_POS )
-#define portFPCCR_LSPEN_POS					( 30UL )
-#define portFPCCR_LSPEN_MASK				( 1UL << portFPCCR_LSPEN_POS )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to manipulate the MPU.
- */
-#define portMPU_TYPE_REG					( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_CTRL_REG					( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portMPU_RNR_REG						( * ( ( volatile uint32_t * ) 0xe000ed98 ) )
-
-#define portMPU_RBAR_REG					( * ( ( volatile uint32_t * ) 0xe000ed9c ) )
-#define portMPU_RLAR_REG					( * ( ( volatile uint32_t * ) 0xe000eda0 ) )
-
-#define portMPU_RBAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda4 ) )
-#define portMPU_RLAR_A1_REG					( * ( ( volatile uint32_t * ) 0xe000eda8 ) )
-
-#define portMPU_RBAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edac ) )
-#define portMPU_RLAR_A2_REG					( * ( ( volatile uint32_t * ) 0xe000edb0 ) )
-
-#define portMPU_RBAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb4 ) )
-#define portMPU_RLAR_A3_REG					( * ( ( volatile uint32_t * ) 0xe000edb8 ) )
-
-#define portMPU_MAIR0_REG					( * ( ( volatile uint32_t * ) 0xe000edc0 ) )
-#define portMPU_MAIR1_REG					( * ( ( volatile uint32_t * ) 0xe000edc4 ) )
-
-#define portMPU_RBAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-#define portMPU_RLAR_ADDRESS_MASK			( 0xffffffe0 ) /* Must be 32-byte aligned. */
-
-#define portMPU_MAIR_ATTR0_POS				( 0UL )
-#define portMPU_MAIR_ATTR0_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR1_POS				( 8UL )
-#define portMPU_MAIR_ATTR1_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR2_POS				( 16UL )
-#define portMPU_MAIR_ATTR2_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR3_POS				( 24UL )
-#define portMPU_MAIR_ATTR3_MASK				( 0xff000000 )
-
-#define portMPU_MAIR_ATTR4_POS				( 0UL )
-#define portMPU_MAIR_ATTR4_MASK				( 0x000000ff )
-
-#define portMPU_MAIR_ATTR5_POS				( 8UL )
-#define portMPU_MAIR_ATTR5_MASK				( 0x0000ff00 )
-
-#define portMPU_MAIR_ATTR6_POS				( 16UL )
-#define portMPU_MAIR_ATTR6_MASK				( 0x00ff0000 )
-
-#define portMPU_MAIR_ATTR7_POS				( 24UL )
-#define portMPU_MAIR_ATTR7_MASK				( 0xff000000 )
-
-#define portMPU_RLAR_ATTR_INDEX0			( 0UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX1			( 1UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX2			( 2UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX3			( 3UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX4			( 4UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX5			( 5UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX6			( 6UL << 1UL )
-#define portMPU_RLAR_ATTR_INDEX7			( 7UL << 1UL )
-
-#define portMPU_RLAR_REGION_ENABLE			( 1UL )
-
-/* Enable privileged access to unmapped region. */
-#define portMPU_PRIV_BACKGROUND_ENABLE		( 1UL << 2UL )
-
-/* Enable MPU. */
-#define portMPU_ENABLE						( 1UL << 0UL )
-
-/* Expected value of the portMPU_TYPE register. */
-#define portEXPECTED_MPU_TYPE_VALUE			( 8UL << 8UL ) /* 8 regions, unified. */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Constants required to set up the initial stack.
- */
-#define portINITIAL_XPSR					( 0x01000000 )
-
-#if( configRUN_FREERTOS_SECURE_ONLY == 1 )
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         FD
-	 * 1111 1111  1111 1111  1111 1111  1111 1101
-	 *
-	 * Bit[6] - 1 --> The exception was taken from the Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 1 --> The exception was taken to the Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xfffffffd )
-#else
-	/**
-	 * @brief Initial EXC_RETURN value.
-	 *
-	 *     FF         FF         FF         BC
-	 * 1111 1111  1111 1111  1111 1111  1011 1100
-	 *
-	 * Bit[6] - 0 --> The exception was taken from the Non-Secure state.
-	 * Bit[5] - 1 --> Do not skip stacking of additional state context.
-	 * Bit[4] - 1 --> The PE did not allocate space on the stack for FP context.
-	 * Bit[3] - 1 --> Return to the Thread mode.
-	 * Bit[2] - 1 --> Restore registers from the process stack.
-	 * Bit[1] - 0 --> Reserved, 0.
-	 * Bit[0] - 0 --> The exception was taken to the Non-Secure state.
-	 */
-	#define portINITIAL_EXC_RETURN			( 0xffffffbc )
-#endif /* configRUN_FREERTOS_SECURE_ONLY */
-
-/**
- * @brief CONTROL register privileged bit mask.
- *
- * Bit[0] in CONTROL register tells the privilege:
- *  Bit[0] = 0 ==> The task is privileged.
- *  Bit[0] = 1 ==> The task is not privileged.
- */
-#define portCONTROL_PRIVILEGED_MASK			( 1UL << 0UL )
-
-/**
- * @brief Initial CONTROL register values.
- */
-#define portINITIAL_CONTROL_UNPRIVILEGED	( 0x3 )
-#define portINITIAL_CONTROL_PRIVILEGED		( 0x2 )
-
-/**
- * @brief Let the user override the pre-loading of the initial LR with the
- * address of prvTaskExitError() in case it messes up unwinding of the stack
- * in the debugger.
- */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS			configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS			prvTaskExitError
-#endif
-
-/**
- * @brief If portPRELOAD_REGISTERS then registers will be given an initial value
- * when a task is created. This helps in debugging at the cost of code size.
- */
-#define portPRELOAD_REGISTERS				1
-
-/**
- * @brief A task is created without a secure context, and must call
- * portALLOCATE_SECURE_CONTEXT() to give itself a secure context before it makes
- * any secure calls.
- */
-#define portNO_SECURE_CONTEXT				0
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Used to catch tasks that attempt to return from their implementing
- * function.
- */
-static void prvTaskExitError( void );
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Setup the Memory Protection Unit (MPU).
-	 */
-	static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_MPU */
-
-#if( configENABLE_FPU == 1 )
-	/**
-	 * @brief Setup the Floating Point Unit (FPU).
-	 */
-	static void prvSetupFPU( void ) PRIVILEGED_FUNCTION;
-#endif /* configENABLE_FPU */
-
-/**
- * @brief Yield the processor.
- */
-void vPortYield( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enter critical section.
- */
-void vPortEnterCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Exit from critical section.
- */
-void vPortExitCritical( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SysTick handler.
- */
-void SysTick_Handler( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief C part of SVC handler.
- */
-portDONT_DISCARD void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Each task maintains its own interrupt status in the critical nesting
- * variable.
- */
-static volatile uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Saved as part of the task context to indicate which context the
-	 * task is using on the secure side.
-	 */
-	portDONT_DISCARD volatile SecureContextHandle_t xSecureContext = portNO_SECURE_CONTEXT;
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Stop and reset the SysTick. */
-	*( portNVIC_SYSTICK_CTRL ) = 0UL;
-	*( portNVIC_SYSTICK_CURRENT_VALUE ) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*( portNVIC_SYSTICK_LOAD ) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*( portNVIC_SYSTICK_CTRL ) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-volatile uint32_t ulDummy = 0UL;
-
-	/* A function that implements a task must not exit or attempt to return to
-	 * its caller as there is nothing to return to. If a task wants to exit it
-	 * should instead call vTaskDelete( NULL ). Artificially force an assert()
-	 * to be triggered if configASSERT() is defined, then stop here so
-	 * application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-
-	while( ulDummy == 0 )
-	{
-		/* This file calls prvTaskExitError() after the scheduler has been
-		 * started to remove a compiler warning about the function being
-		 * defined but never called.  ulDummy is used purely to quieten other
-		 * warnings about code appearing after this function is called - making
-		 * ulDummy volatile makes the compiler think the function could return
-		 * and therefore not output an 'unreachable code' warning for code that
-		 * appears after it. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	static void prvSetupMPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __privileged_functions_start__;
-		extern uint32_t * __privileged_functions_end__;
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-		extern uint32_t * __unprivileged_flash_start__;
-		extern uint32_t * __unprivileged_flash_end__;
-		extern uint32_t * __privileged_sram_start__;
-		extern uint32_t * __privileged_sram_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __privileged_functions_start__[];
-		extern uint32_t __privileged_functions_end__[];
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-		extern uint32_t __unprivileged_flash_start__[];
-		extern uint32_t __unprivileged_flash_end__[];
-		extern uint32_t __privileged_sram_start__[];
-		extern uint32_t __privileged_sram_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-
-		/* Check that the MPU is present. */
-		if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-		{
-			/* MAIR0 - Index 0. */
-			portMPU_MAIR0_REG |= ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-			/* MAIR0 - Index 1. */
-			portMPU_MAIR0_REG |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-			/* Setup privileged flash as Read Only so that privileged tasks can
-			 * read it but not modify. */
-			portMPU_RNR_REG = portPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_functions_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_functions_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged flash as Read Only by both privileged and
-			 * unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_FLASH_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __unprivileged_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __unprivileged_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup unprivileged syscalls flash as Read Only by both privileged
-			 * and unprivileged tasks. All tasks can read it but no-one can modify. */
-			portMPU_RNR_REG = portUNPRIVILEGED_SYSCALLS_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __syscalls_flash_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_READ_ONLY );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __syscalls_flash_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Setup RAM containing kernel data for privileged access only. */
-			portMPU_RNR_REG = portPRIVILEGED_RAM_REGION;
-			portMPU_RBAR_REG =	( ( ( uint32_t ) __privileged_sram_start__ ) & portMPU_RBAR_ADDRESS_MASK ) |
-								( portMPU_REGION_NON_SHAREABLE ) |
-								( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-								( portMPU_REGION_EXECUTE_NEVER );
-			portMPU_RLAR_REG =	( ( ( uint32_t ) __privileged_sram_end__ ) & portMPU_RLAR_ADDRESS_MASK ) |
-								( portMPU_RLAR_ATTR_INDEX0 ) |
-								( portMPU_RLAR_REGION_ENABLE );
-
-			/* Enable mem fault. */
-			portSCB_SYS_HANDLER_CTRL_STATE_REG |= portSCB_MEM_FAULT_ENABLE;
-
-			/* Enable MPU with privileged background access i.e. unmapped
-			 * regions have privileged access. */
-			portMPU_CTRL_REG |= ( portMPU_PRIV_BACKGROUND_ENABLE | portMPU_ENABLE );
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_FPU == 1 )
-	static void prvSetupFPU( void ) /* PRIVILEGED_FUNCTION */
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			/* Enable non-secure access to the FPU. */
-			SecureInit_EnableNSFPUAccess();
-		}
-		#endif /* configENABLE_TRUSTZONE */
-
-		/* CP10 = 11 ==> Full access to FPU i.e. both privileged and
-		 * unprivileged code should be able to access FPU. CP11 should be
-		 * programmed to the same value as CP10. */
-		*( portCPACR ) |=	(	( portCPACR_CP10_VALUE << portCPACR_CP10_POS ) |
-								( portCPACR_CP11_VALUE << portCPACR_CP11_POS )
-							);
-
-		/* ASPEN = 1 ==> Hardware should automatically preserve floating point
-		 * context on exception entry and restore on exception return.
-		 * LSPEN = 1 ==> Enable lazy context save of FP state. */
-		*( portFPCCR ) |= ( portFPCCR_ASPEN_MASK | portFPCCR_LSPEN_MASK );
-	}
-#endif /* configENABLE_FPU */
-/*-----------------------------------------------------------*/
-
-void vPortYield( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-
-	/* Barriers are normally not required but do ensure the code is
-	 * completely within the specified behaviour for the architecture. */
-	__asm volatile( "dsb" ::: "memory" );
-	__asm volatile( "isb" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void ) /* PRIVILEGED_FUNCTION */
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulCallerStackAddress ) /* PRIVILEGED_FUNCTION portDONT_DISCARD */
-{
-#if( configENABLE_MPU == 1 )
-	#if defined( __ARMCC_VERSION )
-		/* Declaration when these variable are defined in code instead of being
-		 * exported from linker scripts. */
-		extern uint32_t * __syscalls_flash_start__;
-		extern uint32_t * __syscalls_flash_end__;
-	#else
-		/* Declaration when these variable are exported from linker scripts. */
-		extern uint32_t __syscalls_flash_start__[];
-		extern uint32_t __syscalls_flash_end__[];
-	#endif /* defined( __ARMCC_VERSION ) */
-#endif /* configENABLE_MPU */
-
-uint32_t ulPC;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	uint32_t ulR0;
-	#if( configENABLE_MPU == 1 )
-		uint32_t ulControl, ulIsTaskPrivileged;
-	#endif /* configENABLE_MPU */
-#endif /* configENABLE_TRUSTZONE */
-uint8_t ucSVCNumber;
-
-	/* Register are stored on the stack in the following order - R0, R1, R2, R3,
-	 * R12, LR, PC, xPSR. */
-	ulPC = pulCallerStackAddress[ 6 ];
-	ucSVCNumber = ( ( uint8_t *) ulPC )[ -2 ];
-
-	switch( ucSVCNumber )
-	{
-		#if( configENABLE_TRUSTZONE == 1 )
-			case portSVC_ALLOCATE_SECURE_CONTEXT:
-			{
-				/* R0 contains the stack size passed as parameter to the
-				 * vPortAllocateSecureContext function. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				#if( configENABLE_MPU == 1 )
-				{
-					/* Read the CONTROL register value. */
-					__asm volatile ( "mrs %0, control"  : "=r" ( ulControl ) );
-
-					/* The task that raised the SVC is privileged if Bit[0]
-					 * in the CONTROL register is 0. */
-					ulIsTaskPrivileged = ( ( ulControl & portCONTROL_PRIVILEGED_MASK ) == 0 );
-
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0, ulIsTaskPrivileged );
-				}
-				#else
-				{
-					/* Allocate and load a context for the secure task. */
-					xSecureContext = SecureContext_AllocateContext( ulR0 );
-				}
-				#endif /* configENABLE_MPU */
-
-				configASSERT( xSecureContext != NULL );
-				SecureContext_LoadContext( xSecureContext );
-			}
-			break;
-
-			case portSVC_FREE_SECURE_CONTEXT:
-			{
-				/* R0 contains the secure context handle to be freed. */
-				ulR0 = pulCallerStackAddress[ 0 ];
-
-				/* Free the secure context. */
-				SecureContext_FreeContext( ( SecureContextHandle_t ) ulR0 );
-			}
-			break;
-		#endif /* configENABLE_TRUSTZONE */
-
-		case portSVC_START_SCHEDULER:
-		{
-			#if( configENABLE_TRUSTZONE == 1 )
-			{
-				/* De-prioritize the non-secure exceptions so that the
-				 * non-secure pendSV runs at the lowest priority. */
-				SecureInit_DePrioritizeNSExceptions();
-
-				/* Initialize the secure context management system. */
-				SecureContext_Init();
-			}
-			#endif /* configENABLE_TRUSTZONE */
-
-			#if( configENABLE_FPU == 1 )
-			{
-				/* Setup the Floating Point Unit (FPU). */
-				prvSetupFPU();
-			}
-			#endif /* configENABLE_FPU */
-
-			/* Setup the context of the first task so that the first task starts
-			 * executing. */
-			vRestoreContextOfFirstTask();
-		}
-		break;
-
-		#if( configENABLE_MPU == 1 )
-			case portSVC_RAISE_PRIVILEGE:
-			{
-				/* Only raise the privilege, if the svc was raised from any of
-				 * the system calls. */
-				if( ulPC >= ( uint32_t ) __syscalls_flash_start__ &&
-					ulPC <= ( uint32_t ) __syscalls_flash_end__ )
-				{
-					vRaisePrivilege();
-				}
-			}
-			break;
-		#endif /* configENABLE_MPU */
-
-		default:
-		{
-			/* Incorrect SVC call. */
-			configASSERT( pdFALSE );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) /* PRIVILEGED_FUNCTION */
-#else
-	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, StackType_t *pxEndOfStack, TaskFunction_t pxCode, void *pvParameters ) /* PRIVILEGED_FUNCTION */
-#endif /* configENABLE_MPU */
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	 * interrupt. */
-	#if( portPRELOAD_REGISTERS == 0 )
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack -= 5;											/* R12, R3, R2 and R1. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack -= 9;											/* R11..R4, EXC_RETURN. */
-		*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#else /* portPRELOAD_REGISTERS */
-	{
-		pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-		*pxTopOfStack = portINITIAL_XPSR;							/* xPSR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxCode;						/* PC */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x12121212UL;				/* R12 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x03030303UL;				/* R3 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x02020202UL;				/* R2 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x01010101UL;				/* R1 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;				/* R0 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x11111111UL;				/* R11 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x10101010UL;				/* R10 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x09090909UL;				/* R09 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x08080808UL;				/* R08 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x07070707UL;				/* R07 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x06060606UL;				/* R06 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x05050505UL;				/* R05 */
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x04040404UL;				/* R04 */
-		pxTopOfStack--;
-		*pxTopOfStack = portINITIAL_EXC_RETURN;						/* EXC_RETURN */
-
-		#if( configENABLE_MPU == 1 )
-		{
-			pxTopOfStack--;
-			if( xRunPrivileged == pdTRUE )
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_PRIVILEGED;		/* Slot used to hold this task's CONTROL value. */
-			}
-			else
-			{
-				*pxTopOfStack = portINITIAL_CONTROL_UNPRIVILEGED;	/* Slot used to hold this task's CONTROL value. */
-			}
-		}
-		#endif /* configENABLE_MPU */
-
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pxEndOfStack;	/* Slot used to hold this task's PSPLIM value. */
-
-		#if( configENABLE_TRUSTZONE == 1 )
-		{
-			pxTopOfStack--;
-			*pxTopOfStack = portNO_SECURE_CONTEXT;		/* Slot used to hold this task's xSecureContext value. */
-		}
-		#endif /* configENABLE_TRUSTZONE */
-	}
-	#endif /* portPRELOAD_REGISTERS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*( portNVIC_SYSPRI2 ) |= portNVIC_PENDSV_PRI;
-	*( portNVIC_SYSPRI2 ) |= portNVIC_SYSTICK_PRI;
-
-	#if( configENABLE_MPU == 1 )
-	{
-		/* Setup the Memory Protection Unit (MPU). */
-		prvSetupMPU();
-	}
-	#endif /* configENABLE_MPU */
-
-	/* Start the timer that generates the tick ISR. Interrupts are disabled
-	 * here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialize the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Start the first task. */
-	vStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing. Call the task
-	 * exit error function to prevent compiler warnings about a static function
-	 * not being called in the case that the application writer overrides this
-	 * functionality by defining configTASK_RETURN_ADDRESS. Call
-	 * vTaskSwitchContext() so link time optimization does not remove the
-	 * symbol. */
-	vTaskSwitchContext();
-	prvTaskExitError();
-
-	/* Should not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void ) /* PRIVILEGED_FUNCTION */
-{
-	/* Not implemented in ports where there is nothing to return to.
-	 * Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-	{
-	uint32_t ulRegionStartAddress, ulRegionEndAddress, ulRegionNumber;
-	int32_t lIndex = 0;
-
-		/* Setup MAIR0. */
-		xMPUSettings->ulMAIR0 = ( ( portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE << portMPU_MAIR_ATTR0_POS ) & portMPU_MAIR_ATTR0_MASK );
-		xMPUSettings->ulMAIR0 |= ( ( portMPU_DEVICE_MEMORY_nGnRE << portMPU_MAIR_ATTR1_POS ) & portMPU_MAIR_ATTR1_MASK );
-
-		/* This function is called automatically when the task is created - in
-		 * which case the stack region parameters will be valid.  At all other
-		 * times the stack parameters will not be valid and it is assumed that
-		 * the stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			ulRegionStartAddress = ( ( uint32_t ) pxBottomOfStack ) & portMPU_RBAR_ADDRESS_MASK;
-			ulRegionEndAddress = ( uint32_t ) pxBottomOfStack + ( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) - 1;
-			ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRBAR =	( ulRegionStartAddress ) |
-															( portMPU_REGION_NON_SHAREABLE ) |
-															( portMPU_REGION_READ_WRITE ) |
-															( portMPU_REGION_EXECUTE_NEVER );
-
-			xMPUSettings->xRegionsSettings[ 0 ].ulRLAR =	( ulRegionEndAddress ) |
-															( portMPU_RLAR_ATTR_INDEX0 ) |
-															( portMPU_RLAR_REGION_ENABLE );
-		}
-
-		/* User supplied configurable regions. */
-		for( ulRegionNumber = 1; ulRegionNumber <= portNUM_CONFIGURABLE_REGIONS; ulRegionNumber++ )
-		{
-			/* If xRegions is NULL i.e. the task has not specified any MPU
-			 * region, the else part ensures that all the configurable MPU
-			 * regions are invalidated. */
-			if( ( xRegions != NULL ) && ( xRegions[ lIndex ].ulLengthInBytes > 0UL ) )
-			{
-				/* Translate the generic region definition contained in xRegions
-				 * into the ARMv8 specific MPU settings that are then stored in
-				 * xMPUSettings. */
-				ulRegionStartAddress = ( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) & portMPU_RBAR_ADDRESS_MASK;
-				ulRegionEndAddress = ( uint32_t ) xRegions[ lIndex ].pvBaseAddress + xRegions[ lIndex ].ulLengthInBytes - 1;
-				ulRegionEndAddress  &= portMPU_RLAR_ADDRESS_MASK;
-
-				/* Start address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR =	( ulRegionStartAddress ) |
-																			( portMPU_REGION_NON_SHAREABLE );
-
-				/* RO/RW. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_READ_ONLY ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_ONLY );
-				}
-				else
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_READ_WRITE );
-				}
-
-				/* XN. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_EXECUTE_NEVER ) != 0 )
-				{
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR |= ( portMPU_REGION_EXECUTE_NEVER );
-				}
-
-				/* End Address. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR =	( ulRegionEndAddress ) |
-																			( portMPU_RLAR_REGION_ENABLE );
-
-				/* Normal memory/ Device memory. */
-				if( ( xRegions[ lIndex ].ulParameters & tskMPU_REGION_DEVICE_MEMORY ) != 0 )
-				{
-					/* Attr1 in MAIR0 is configured as device memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX1;
-				}
-				else
-				{
-					/* Attr1 in MAIR0 is configured as normal memory. */
-					xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR |= portMPU_RLAR_ATTR_INDEX0;
-				}
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRBAR = 0UL;
-				xMPUSettings->xRegionsSettings[ ulRegionNumber ].ulRLAR = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h b/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
deleted file mode 100755
index 2ecf04e..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef __PORT_ASM_H__
-#define __PORT_ASM_H__
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-
-/* MPU wrappers includes. */
-#include "mpu_wrappers.h"
-
-/**
- * @brief Restore the context of the first task so that the first task starts
- * executing.
- */
-void vRestoreContextOfFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void ) __attribute__ (( naked ));
-
-/**
- * @brief Raises the privilege level by clearing the bit 0 of the CONTROL
- * register.
- *
- * @note This is a privileged function and should only be called from the kenrel
- * code.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vRaisePrivilege( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void ) __attribute__ (( naked ));
-
-/**
- * @brief Starts the first task.
- */
-void vStartFirstTask( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Disables interrupts.
- */
-uint32_t ulSetInterruptMaskFromISR( void ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Enables interrupts.
- */
-void vClearInterruptMaskFromISR( uint32_t ulMask ) __attribute__(( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief PendSV Exception handler.
- */
-void PendSV_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief SVC Handler.
- */
-void SVC_Handler( void ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Allocate a Secure context for the calling task.
- *
- * @param[in] ulSecureStackSize The size of the stack to be allocated on the
- * secure side for the calling task.
- */
-void vPortAllocateSecureContext( uint32_t ulSecureStackSize ) __attribute__ (( naked ));
-
-/**
- * @brief Free the task's secure context.
- *
- * @param[in] pulTCB Pointer to the Task Control Block (TCB) of the task.
- */
-void vPortFreeSecureContext( uint32_t *pulTCB ) __attribute__ (( naked )) PRIVILEGED_FUNCTION;
-
-#endif /* __PORT_ASM_H__ */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s b/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
deleted file mode 100755
index 400755b..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portasm.s
+++ /dev/null
@@ -1,242 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	EXTERN pxCurrentTCB
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-	PUBLIC vRestoreContextOfFirstTask
-	PUBLIC vRaisePrivilege
-	PUBLIC vStartFirstTask
-	PUBLIC ulSetInterruptMaskFromISR
-	PUBLIC vClearInterruptMaskFromISR
-	PUBLIC PendSV_Handler
-	PUBLIC SVC_Handler
-/*-----------------------------------------------------------*/
-
-/*---------------- Unprivileged Functions -------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION .text:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control							/* r0 = CONTROL. */
-	tst r0, #1								/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	ite ne
-	movne r0, #0							/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	moveq r0, #1							/* CONTROL[0]==0. Return true to indicate that the processor is not privileged. */
-	bx lr									/* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control							/* r0 = CONTROL. */
-	orr r0, r0, #1							/* r0 = r0 | 1. */
-	msr control, r0							/* CONTROL = r0. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-/*----------------- Privileged Functions --------------------*/
-
-/*-----------------------------------------------------------*/
-
-	SECTION privileged_functions:CODE:NOROOT(2)
-	THUMB
-/*-----------------------------------------------------------*/
-
-vRestoreContextOfFirstTask:
-	ldr  r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr  r1, [r2]							/* Read pxCurrentTCB. */
-	ldr  r0, [r1]							/* Read top of stack from TCB - The first item in pxCurrentTCB is the task top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
-	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str r3, [r2]							/* Program MAIR0. */
-	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r3, #4								/* r3 = 4. */
-	str r3, [r2]							/* Program RNR = 4. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldm  r0!, {r1-r3}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL and r3 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	msr  control, r2						/* Set this task's CONTROL value. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r3									/* Finally, branch to EXC_RETURN. */
-#else /* configENABLE_MPU */
-	ldm  r0!, {r1-r2}						/* Read from stack - r1 = PSPLIM and r2 = EXC_RETURN. */
-	msr  psplim, r1							/* Set this task's PSPLIM value. */
-	movs r1, #2								/* r1 = 2. */
-	msr  CONTROL, r1						/* Switch to use PSP in the thread mode. */
-	adds r0, #32							/* Discard everything up to r0. */
-	msr  psp, r0							/* This is now the new top of stack to use in the task. */
-	isb
-	bx   r2									/* Finally, branch to EXC_RETURN. */
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-vRaisePrivilege:
-	mrs  r0, control						/* Read the CONTROL register. */
-	bic r0, r0, #1							/* Clear the bit 0. */
-	msr  control, r0						/* Write back the new CONTROL value. */
-	bx lr									/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-vStartFirstTask:
-	ldr r0, =0xe000ed08						/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]							/* Read the VTOR register which gives the address of vector table. */
-	ldr r0, [r0]							/* The first entry in vector table is stack pointer. */
-	msr msp, r0								/* Set the MSP back to the start of the stack. */
-	cpsie i									/* Globally enable interrupts. */
-	cpsie f
-	dsb
-	isb
-	svc 2									/* System call to start the first task. portSVC_START_SCHEDULER = 2. */
-/*-----------------------------------------------------------*/
-
-ulSetInterruptMaskFromISR:
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-/*-----------------------------------------------------------*/
-
-vClearInterruptMaskFromISR:
-	msr PRIMASK, r0
-	bx lr
-/*-----------------------------------------------------------*/
-
-PendSV_Handler:
-	mrs r0, psp								/* Read PSP in r0. */
-#if ( configENABLE_FPU == 1 )
-	tst lr, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	it eq
-	vstmdbeq r0!, {s16-s31}					/* Store the FPU registers which are not saved automatically. */
-#endif /* configENABLE_FPU */
-#if ( configENABLE_MPU == 1 )
-	mrs r1, psplim							/* r1 = PSPLIM. */
-	mrs r2, control							/* r2 = CONTROL. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmdb r0!, {r1-r11}						/* Store on the stack - PSPLIM, CONTROL, LR and registers that are not automatically saved. */
-#else /* configENABLE_MPU */
-	mrs r2, psplim							/* r2 = PSPLIM. */
-	mov r3, lr								/* r3 = LR/EXC_RETURN. */
-	stmdb r0!, {r2-r11}						/* Store on the stack - PSPLIM, LR and registers that are not automatically. */
-#endif /* configENABLE_MPU */
-
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-	str r0, [r1]							/* Save the new top of stack in TCB. */
-
-	cpsid i
-	bl vTaskSwitchContext
-	cpsie i
-
-	ldr r2, =pxCurrentTCB					/* Read the location of pxCurrentTCB i.e. &( pxCurrentTCB ). */
-	ldr r1, [r2]							/* Read pxCurrentTCB. */
-	ldr r0, [r1]							/* The first item in pxCurrentTCB is the task top of stack. r0 now points to the top of stack. */
-
-#if ( configENABLE_MPU == 1 )
-	dmb										/* Complete outstanding transfers before disabling MPU. */
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	bic r4, r4, #1							/* r4 = r4 & ~1 i.e. Clear the bit 0 in r4. */
-	str r4, [r2]							/* Disable MPU. */
-
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to MAIR0 in TCB. */
-	ldr r3, [r1]							/* r3 = *r1 i.e. r3 = MAIR0. */
-	ldr r2, =0xe000edc0						/* r2 = 0xe000edc0 [Location of MAIR0]. */
-	str r3, [r2]							/* Program MAIR0. */
-	ldr r2, =0xe000ed98						/* r2 = 0xe000ed98 [Location of RNR]. */
-	movs r3, #4								/* r3 = 4. */
-	str r3, [r2]							/* Program RNR = 4. */
-	adds r1, #4								/* r1 = r1 + 4. r1 now points to first RBAR in TCB. */
-	ldr r2, =0xe000ed9c						/* r2 = 0xe000ed9c [Location of RBAR]. */
-	ldmia r1!, {r4-r11}						/* Read 4 sets of RBAR/RLAR registers from TCB. */
-	stmia r2!, {r4-r11}						/* Write 4 set of RBAR/RLAR registers using alias registers. */
-
-	ldr r2, =0xe000ed94						/* r2 = 0xe000ed94 [Location of MPU_CTRL]. */
-	ldr r4, [r2]							/* Read the value of MPU_CTRL. */
-	orr r4, r4, #1							/* r4 = r4 | 1 i.e. Set the bit 0 in r4. */
-	str r4, [r2]							/* Enable MPU. */
-	dsb										/* Force memory writes before continuing. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_MPU == 1 )
-	ldmia r0!, {r1-r11}						/* Read from stack - r1 = PSPLIM, r2 = CONTROL, r3 = LR and r4-r11 restored. */
-#else /* configENABLE_MPU */
-	ldmia r0!, {r2-r11}						/* Read from stack - r2 = PSPLIM, r3 = LR and r4-r11 restored. */
-#endif /* configENABLE_MPU */
-
-#if ( configENABLE_FPU == 1 )
-	tst r3, #0x10							/* Test Bit[4] in LR. Bit[4] of EXC_RETURN is 0 if the FPU is in use. */
-	it eq
-	vldmiaeq r0!, {s16-s31}					/* Restore the FPU registers which are not restored automatically. */
-#endif /* configENABLE_FPU */
-
- #if ( configENABLE_MPU == 1 )
-	msr psplim, r1							/* Restore the PSPLIM register value for the task. */
-	msr control, r2							/* Restore the CONTROL register value for the task. */
-#else /* configENABLE_MPU */
-	msr psplim, r2							/* Restore the PSPLIM register value for the task. */
-#endif /* configENABLE_MPU */
-	msr psp, r0								/* Remember the new top of stack for the task. */
-	bx r3
-/*-----------------------------------------------------------*/
-
-SVC_Handler:
-	tst lr, #4
-	ite eq
-	mrseq r0, msp
-	mrsne r0, psp
-	b vPortSVCHandler_C
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
deleted file mode 100755
index aba3daf..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM33_NTZ/non_secure/portmacro.h
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*------------------------------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *------------------------------------------------------------------------------
- */
-
-#ifndef configENABLE_FPU
-	#error configENABLE_FPU must be defined in FreeRTOSConfig.h.  Set configENABLE_FPU to 1 to enable the FPU or 0 to disable the FPU.
-#endif /* configENABLE_FPU */
-
-#ifndef configENABLE_MPU
-	#error configENABLE_MPU must be defined in FreeRTOSConfig.h.  Set configENABLE_MPU to 1 to enable the MPU or 0 to disable the MPU.
-#endif /* configENABLE_MPU */
-
-#ifndef configENABLE_TRUSTZONE
-	#error configENABLE_TRUSTZONE must be defined in FreeRTOSConfig.h.  Set configENABLE_TRUSTZONE to 1 to enable TrustZone or 0 to disable TrustZone.
-#endif /* configENABLE_TRUSTZONE */
-
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Type definitions.
- */
-#define portCHAR											char
-#define portFLOAT											float
-#define portDOUBLE											double
-#define portLONG											long
-#define portSHORT											short
-#define portSTACK_TYPE										uint32_t
-#define portBASE_TYPE										long
-
-typedef portSTACK_TYPE										StackType_t;
-typedef long												BaseType_t;
-typedef unsigned long										UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )					0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	 * not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC							1
-#endif
-/*-----------------------------------------------------------*/
-
-/**
- * Architecture specifics.
- */
-#define portARCH_NAME										"Cortex-M33"
-#define portSTACK_GROWTH									( -1 )
-#define portTICK_PERIOD_MS									( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT									8
-#define portNOP()
-#define portINLINE											__inline
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE								inline __attribute__(( always_inline ))
-#endif
-#define portHAS_STACK_OVERFLOW_CHECKING						1
-#define portDONT_DISCARD									__root
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Extern declarations.
- */
-extern void vPortYield( void ) /* PRIVILEGED_FUNCTION */;
-
-extern void vPortEnterCritical( void ) /* PRIVILEGED_FUNCTION */;
-extern void vPortExitCritical( void ) /* PRIVILEGED_FUNCTION */;
-
-extern uint32_t ulSetInterruptMaskFromISR( void ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-extern void vClearInterruptMaskFromISR( uint32_t ulMask ) /* __attribute__(( naked )) PRIVILEGED_FUNCTION */;
-
-#if( configENABLE_TRUSTZONE == 1 )
-	extern void vPortAllocateSecureContext( uint32_t ulSecureStackSize ); /* __attribute__ (( naked )) */
-	extern void vPortFreeSecureContext( uint32_t *pulTCB ) /* __attribute__ (( naked )) PRIVILEGED_FUNCTION */;
-#endif /* configENABLE_TRUSTZONE */
-
-#if( configENABLE_MPU == 1 )
-	extern BaseType_t xIsPrivileged( void ) /* __attribute__ (( naked )) */;
-	extern void vResetPrivilege( void ) /* __attribute__ (( naked )) */;
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief MPU specific constants.
- */
-#if( configENABLE_MPU == 1 )
-	#define portUSING_MPU_WRAPPERS							1
-	#define portPRIVILEGE_BIT								( 0x80000000UL )
-#else
-	#define portPRIVILEGE_BIT								( 0x0UL )
-#endif /* configENABLE_MPU */
-
-
-/* MPU regions. */
-#define portPRIVILEGED_FLASH_REGION							( 0UL )
-#define portUNPRIVILEGED_FLASH_REGION						( 1UL )
-#define portUNPRIVILEGED_SYSCALLS_REGION					( 2UL )
-#define portPRIVILEGED_RAM_REGION							( 3UL )
-#define portSTACK_REGION									( 4UL )
-#define portFIRST_CONFIGURABLE_REGION						( 5UL )
-#define portLAST_CONFIGURABLE_REGION						( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS						( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS								( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-/* Device memory attributes used in MPU_MAIR registers.
- *
- * 8-bit values encoded as follows:
- *  Bit[7:4] - 0000 - Device Memory
- *  Bit[3:2] - 00 --> Device-nGnRnE
- *				01 --> Device-nGnRE
- *				10 --> Device-nGRE
- *				11 --> Device-GRE
- *  Bit[1:0] - 00, Reserved.
- */
-#define portMPU_DEVICE_MEMORY_nGnRnE						( 0x00 ) /* 0000 0000 */
-#define portMPU_DEVICE_MEMORY_nGnRE							( 0x04 ) /* 0000 0100 */
-#define portMPU_DEVICE_MEMORY_nGRE							( 0x08 ) /* 0000 1000 */
-#define portMPU_DEVICE_MEMORY_GRE							( 0x0C ) /* 0000 1100 */
-
-/* Normal memory attributes used in MPU_MAIR registers. */
-#define portMPU_NORMAL_MEMORY_NON_CACHEABLE					( 0x44 ) /* Non-cacheable. */
-#define portMPU_NORMAL_MEMORY_BUFFERABLE_CACHEABLE			( 0xFF ) /* Non-Transient, Write-back, Read-Allocate and Write-Allocate. */
-
-/* Attributes used in MPU_RBAR registers. */
-#define portMPU_REGION_NON_SHAREABLE						( 0UL << 3UL )
-#define portMPU_REGION_INNER_SHAREABLE						( 1UL << 3UL )
-#define portMPU_REGION_OUTER_SHAREABLE						( 2UL << 3UL )
-
-#define portMPU_REGION_PRIVILEGED_READ_WRITE				( 0UL << 1UL )
-#define portMPU_REGION_READ_WRITE							( 1UL << 1UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY					( 2UL << 1UL )
-#define portMPU_REGION_READ_ONLY							( 3UL << 1UL )
-
-#define portMPU_REGION_EXECUTE_NEVER						( 1UL )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Settings to define an MPU region.
- */
-typedef struct MPURegionSettings
-{
-	uint32_t ulRBAR;	/**< RBAR for the region. */
-	uint32_t ulRLAR;	/**< RLAR for the region. */
-} MPURegionSettings_t;
-
-/**
- * @brief MPU settings as stored in the TCB.
- */
-typedef struct MPU_SETTINGS
-{
-	uint32_t ulMAIR0;	/**< MAIR0 for the task containing attributes for all the 4 per task regions. */
-	MPURegionSettings_t xRegionsSettings[ portTOTAL_NUM_REGIONS ]; /**< Settings for 4 per task regions. */
-} xMPU_SETTINGS;
-/*-----------------------------------------------------------*/
-
-/**
- * @brief SVC numbers.
- */
-#define portSVC_ALLOCATE_SECURE_CONTEXT						0
-#define portSVC_FREE_SECURE_CONTEXT							1
-#define portSVC_START_SCHEDULER								2
-#define portSVC_RAISE_PRIVILEGE								3
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Scheduler utilities.
- */
-#define portYIELD()											vPortYield()
-#define portNVIC_INT_CTRL_REG								( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT								( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired )			if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x )								portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Critical section management.
- */
-#define portSET_INTERRUPT_MASK_FROM_ISR()					ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)				vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()							__asm volatile ( " cpsid i " ::: "memory" )
-#define portENABLE_INTERRUPTS()								__asm volatile ( " cpsie i " ::: "memory" )
-#define portENTER_CRITICAL()								vPortEnterCritical()
-#define portEXIT_CRITICAL()									vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Task function macros as described on the FreeRTOS.org WEB site.
- */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )		void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_TRUSTZONE == 1 )
-	/**
-	 * @brief Allocate a secure context for the task.
-	 *
-	 * Tasks are not created with a secure context. Any task that is going to call
-	 * secure functions must call portALLOCATE_SECURE_CONTEXT() to allocate itself a
-	 * secure context before it calls any secure function.
-	 *
-	 * @param[in] ulSecureStackSize The size of the secure stack to be allocated.
-	 */
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )	vPortAllocateSecureContext( ulSecureStackSize )
-
-	/**
-	 * @brief Called when a task is deleted to delete the task's secure context,
-	 * if it has one.
-	 *
-	 * @param[in] pxTCB The TCB of the task being deleted.
-	 */
-	#define portCLEAN_UP_TCB( pxTCB )							vPortFreeSecureContext( ( uint32_t * ) pxTCB )
-#else
-	#define portALLOCATE_SECURE_CONTEXT( ulSecureStackSize )
-	#define portCLEAN_UP_TCB( pxTCB )
-#endif /* configENABLE_TRUSTZONE */
-/*-----------------------------------------------------------*/
-
-#if( configENABLE_MPU == 1 )
-	/**
-	 * @brief Checks whether or not the processor is privileged.
-	 *
-	 * @return 1 if the processor is already privileged, 0 otherwise.
-	 */
-	#define portIS_PRIVILEGED()									xIsPrivileged()
-
-	/**
-	 * @brief Raise an SVC request to raise privilege.
-	 *
-	 * The SVC handler checks that the SVC was raised from a system call and only
-	 * then it raises the privilege. If this is called from any other place,
-	 * the privilege is not raised.
-	 */
-	#define portRAISE_PRIVILEGE()								__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-	/**
-	 * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
-	 * register.
-	 */
-	#define portRESET_PRIVILEGE()								vResetPrivilege()
-#else
-	#define portIS_PRIVILEGED()
-	#define portRAISE_PRIVILEGE()
-	#define portRESET_PRIVILEGE()
-#endif /* configENABLE_MPU */
-/*-----------------------------------------------------------*/
-
-/**
- * @brief Barriers.
- */
-#define portMEMORY_BARRIER() __asm volatile( "" ::: "memory" )
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c b/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c
deleted file mode 100755
index fd27a15..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM4F/port.c
+++ /dev/null
@@ -1,656 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
-
-/* IAR includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __ARMVFP__
-	#error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
-	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
-
-/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
-r0p1 port. */
-#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
-#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
-#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )
-
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR					( 0x01000000 )
-#define portINITIAL_EXC_RETURN				( 0xfffffffd )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR			( 45UL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortSysTickHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-extern void vPortStartFirstTask( void );
-
-/*
- * Turn the VFP on.
- */
-extern void vPortEnableVFP( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-
-	/* Offset added to account for the way the MCU uses the stack on entry/exit
-	of interrupts, and to ensure alignment. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
-
-	/* Save code space by skipping register initialisation. */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-
-	/* A save method is being used that requires each task to maintain its
-	own exec return value. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
-	/* This port can be used on all revisions of the Cortex-M7 core other than
-	the r0p1 parts.  r0p1 parts should use the port from the
-	/source/portable/GCC/ARM_CM7/r0p1 directory. */
-	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
-	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Ensure the VFP is enabled - it should be anyway. */
-	vPortEnableVFP();
-
-	/* Lazy save always. */
-	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
-	/* Start the first task. */
-	vPortStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known. */
-	portDISABLE_INTERRUPTS();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TICKLESS_IDLE == 1 )
-
-	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-	TickType_t xModifiableIdleTime;
-
-		/* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
-		is accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-		/* Calculate the reload value required to wait xExpectedIdleTime
-		tick periods.  -1 is used because this code will execute part way
-		through one of the tick periods. */
-		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-		if( ulReloadValue > ulStoppedTimerCompensation )
-		{
-			ulReloadValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Enter a critical section but don't use the taskENTER_CRITICAL()
-		method as that will mask interrupts that should exit sleep mode. */
-		__disable_interrupt();
-		__DSB();
-		__ISB();
-
-		/* If a context switch is pending or a task is waiting for the scheduler
-		to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-		{
-			/* Restart from whatever is left in the count register to complete
-			this tick period. */
-			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Reset the reload register to the value required for normal tick
-			periods. */
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Re-enable interrupts - see comments above __disable_interrupt()
-			call above. */
-			__enable_interrupt();
-		}
-		else
-		{
-			/* Set the new reload value. */
-			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-			/* Clear the SysTick count flag and set the count value back to
-			zero. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-			set its parameter to 0 to indicate that its implementation contains
-			its own wait for interrupt or wait for event instruction, and so wfi
-			should not be executed again.  However, the original expected idle
-			time variable must remain unmodified, so a copy is taken. */
-			xModifiableIdleTime = xExpectedIdleTime;
-			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-			if( xModifiableIdleTime > 0 )
-			{
-				__DSB();
-				__WFI();
-				__ISB();
-			}
-			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-			/* Re-enable interrupts to allow the interrupt that brought the MCU
-			out of sleep mode to execute immediately.  see comments above
-			__disable_interrupt() call above. */
-			__enable_interrupt();
-			__DSB();
-			__ISB();
-
-			/* Disable interrupts again because the clock is about to be stopped
-			and interrupts that execute while the clock is stopped will increase
-			any slippage between the time maintained by the RTOS and calendar
-			time. */
-			__disable_interrupt();
-			__DSB();
-			__ISB();
-			
-			/* Disable the SysTick clock without reading the 
-			portNVIC_SYSTICK_CTRL_REG register to ensure the
-			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again, 
-			the time the SysTick is stopped for is accounted for as best it can 
-			be, but using the tickless mode will inevitably result in some tiny 
-			drift of the time maintained by the kernel with respect to calendar 
-			time*/
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-			/* Determine if the SysTick clock has already counted to zero and
-			been set back to the current reload value (the reload back being
-			correct for the entire expected idle time) or if the SysTick is yet
-			to count to zero (in which case an interrupt other than the SysTick
-			must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-			{
-				uint32_t ulCalculatedLoadValue;
-
-				/* The tick interrupt is already pending, and the SysTick count
-				reloaded with ulReloadValue.  Reset the
-				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-				period. */
-				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-				/* Don't allow a tiny value, or values that have somehow
-				underflowed because the post sleep hook did something
-				that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-				{
-					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-				}
-
-				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-				/* As the pending tick will be processed as soon as this
-				function exits, the tick value maintained by the tick is stepped
-				forward by one less than the time spent waiting. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				Work out how long the sleep lasted rounded to complete tick
-				periods (not the ulReload value which accounted for part
-				ticks). */
-				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-				/* How many complete tick periods passed while the processor
-				was waiting? */
-				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-				/* The reload value is set to whatever fraction of a single tick
-				period remains. */
-				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-			}
-
-			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-			vTaskStepTick( ulCompleteTickPeriods );
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Exit with interrpts enabled. */
-			__enable_interrupt();
-		}
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__weak void vPortSetupTimerInterrupt( void )
-{
-	/* Calculate the constants required to configure the tick interrupt. */
-	#if( configUSE_TICKLESS_IDLE == 1 )
-	{
-		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-	}
-	#endif /* configUSE_TICKLESS_IDLE */
-
-	/* Stop and clear the SysTick. */
-	portNVIC_SYSTICK_CTRL_REG = 0UL;
-	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		/* Obtain the number of the currently executing interrupt. */
-		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s b/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
deleted file mode 100755
index da715ae..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM4F/portasm.s
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include 
-
-	RSEG    CODE:CODE(2)
-	thumb
-
-	EXTERN pxCurrentTCB
-	EXTERN vTaskSwitchContext
-
-	PUBLIC xPortPendSVHandler
-	PUBLIC vPortSVCHandler
-	PUBLIC vPortStartFirstTask
-	PUBLIC vPortEnableVFP
-
-
-/*-----------------------------------------------------------*/
-
-xPortPendSVHandler:
-	mrs r0, psp
-	isb
-	/* Get the location of the current TCB. */
-	ldr	r3, =pxCurrentTCB
-	ldr	r2, [r3]
-
-	/* Is the task using the FPU context?  If so, push high vfp registers. */
-	tst r14, #0x10
-	it eq
-	vstmdbeq r0!, {s16-s31}
-
-	/* Save the core registers. */
-	stmdb r0!, {r4-r11, r14}
-
-	/* Save the new top of stack into the first member of the TCB. */
-	str r0, [r2]
-
-	stmdb sp!, {r0, r3}
-	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-	msr basepri, r0
-	dsb
-	isb
-	bl vTaskSwitchContext
-	mov r0, #0
-	msr basepri, r0
-	ldmia sp!, {r0, r3}
-
-	/* The first item in pxCurrentTCB is the task top of stack. */
-	ldr r1, [r3]
-	ldr r0, [r1]
-
-	/* Pop the core registers. */
-	ldmia r0!, {r4-r11, r14}
-
-	/* Is the task using the FPU context?  If so, pop the high vfp registers
-	too. */
-	tst r14, #0x10
-	it eq
-	vldmiaeq r0!, {s16-s31}
-
-	msr psp, r0
-	isb
-	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
-		#if WORKAROUND_PMU_CM001 == 1
-			push { r14 }
-			pop { pc }
-		#endif
-	#endif
-
-	bx r14
-
-
-/*-----------------------------------------------------------*/
-
-vPortSVCHandler:
-	/* Get the location of the current TCB. */
-	ldr	r3, =pxCurrentTCB
-	ldr r1, [r3]
-	ldr r0, [r1]
-	/* Pop the core registers. */
-	ldmia r0!, {r4-r11, r14}
-	msr psp, r0
-	isb
-	mov r0, #0
-	msr	basepri, r0
-	bx r14
-
-/*-----------------------------------------------------------*/
-
-vPortStartFirstTask
-	/* Use the NVIC offset register to locate the stack. */
-	ldr r0, =0xE000ED08
-	ldr r0, [r0]
-	ldr r0, [r0]
-	/* Set the msp back to the start of the stack. */
-	msr msp, r0
-	/* Clear the bit that indicates the FPU is in use in case the FPU was used
-	before the scheduler was started - which would otherwise result in the
-	unnecessary leaving of space in the SVC stack for lazy saving of FPU
-	registers. */
-	mov r0, #0
-	msr control, r0
-	/* Call SVC to start the first task. */
-	cpsie i
-	cpsie f
-	dsb
-	isb
-	svc 0
-
-/*-----------------------------------------------------------*/
-
-vPortEnableVFP:
-	/* The FPU enable bits are in the CPACR. */
-	ldr.w r0, =0xE000ED88
-	ldr	r1, [r0]
-
-	/* Enable CP10 and CP11 coprocessors, then save back. */
-	orr	r1, r1, #( 0xf << 20 )
-	str r1, [r0]
-	bx	r14
-
-
-
-	END
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
deleted file mode 100755
index 08f5d1c..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM4F/portmacro.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* IAR includes. */
-#include 
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD()											\
-{															\
-	/* Set a PendSV to request a context switch. */			\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
-	__DSB();												\
-	__ISB();												\
-}
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()							\
-{															\
-	__set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
-	__DSB();												\
-	__ISB();												\
-}
-
-#define portENABLE_INTERRUPTS()					__set_BASEPRI( 0 )
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()		__get_BASEPRI(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	__set_BASEPRI( x )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-/*-----------------------------------------------------------*/
-
-/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
-the source code because to do so would cause other compilers to generate
-warnings. */
-#pragma diag_suppress=Pe191
-#pragma diag_suppress=Pa082
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/port.c b/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/port.c
deleted file mode 100755
index 81c5a10..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/port.c
+++ /dev/null
@@ -1,747 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
-
-/* IAR includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#warning This is not yet a documented port as it has not been fully tested, so no demo projects that use this port are provided.
-
-#ifndef __ARMVFP__
-	#error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
-	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG				( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG				( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG		( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG					( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
-#define portNVIC_SYSPRI1_REG					( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
-#define portNVIC_SYS_CTRL_STATE_REG				( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
-#define portNVIC_MEM_FAULT_ENABLE				( 1UL << 16UL )
-
-/* Constants required to access and manipulate the MPU. */
-#define portMPU_TYPE_REG						( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_REGION_BASE_ADDRESS_REG			( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
-#define portMPU_REGION_ATTRIBUTE_REG			( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
-#define portMPU_CTRL_REG						( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portEXPECTED_MPU_TYPE_VALUE				( 8UL << 8UL ) /* 8 regions, unified. */
-#define portMPU_ENABLE							( 0x01UL )
-#define portMPU_BACKGROUND_ENABLE				( 1UL << 2UL )
-#define portPRIVILEGED_EXECUTION_START_ADDRESS	( 0UL )
-#define portMPU_REGION_VALID					( 0x10UL )
-#define portMPU_REGION_ENABLE					( 0x01UL )
-#define portPERIPHERALS_START_ADDRESS			0x40000000UL
-#define portPERIPHERALS_END_ADDRESS				0x5FFFFFFFUL
-
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
-
-/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
-r0p1 port. */
-#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
-#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
-#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )
-
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI					( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR					( 0x01000000 )
-#define portINITIAL_EXC_RETURN				( 0xfffffffd )
-#define portINITIAL_CONTROL_IF_UNPRIVILEGED	( 0x03 )
-#define portINITIAL_CONTROL_IF_PRIVILEGED	( 0x02 )
-
-/* Offsets in the stack to the parameters when inside the SVC handler. */
-#define portOFFSET_TO_PC						( 6 )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR			( 45UL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
-
-/*
- * Configure a number of standard MPU regions that are used by all tasks.
- */
-static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Return the smallest MPU region size that a given number of bytes will fit
- * into.  The region size is returned as the value that should be programmed
- * into the region attribute register for that region.
- */
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-extern void vPortStartFirstTask( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Turn the VFP on.
- */
-extern void vPortEnableVFP( void );
-
-/*
- * The C portion of the SVC handler.
- */
-void vPortSVCHandler_C( uint32_t *pulParam );
-
-/*
- * Called from the SVC handler used to start the scheduler.
- */
-extern void vPortRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
-
-/**
- * @brief Calls the port specific code to raise the privilege.
- *
- * @return pdFALSE if privilege was raised, pdTRUE otherwise.
- */
-extern BaseType_t xPortRaisePrivilege( void );
-
-/**
- * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
- * code to reset the privilege, otherwise does nothing.
- */
-extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-
-	/* Offset added to account for the way the MCU uses the stack on entry/exit
-	of interrupts, and to ensure alignment. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0;	/* LR */
-
-	/* Save code space by skipping register initialisation. */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-
-	/* A save method is being used that requires each task to maintain its
-	own exec return value. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-	pxTopOfStack -= 9;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	if( xRunPrivileged == pdTRUE )
-	{
-		*pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
-	}
-	else
-	{
-		*pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
-	}
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler_C( uint32_t *pulParam )
-{
-uint8_t ucSVCNumber;
-
-	/* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
-	xPSR.  The first argument (r0) is pulParam[ 0 ]. */
-	ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
-	switch( ucSVCNumber )
-	{
-		case portSVC_START_SCHEDULER	:	portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
-											vPortRestoreContextOfFirstTask();
-											break;
-
-		case portSVC_YIELD				:	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-											/* Barriers are normally not required
-											but do ensure the code is completely
-											within the specified behaviour for the
-											architecture. */
-											__asm volatile( "dsb" ::: "memory" );
-											__asm volatile( "isb" );
-
-											break;
-
-		case portSVC_RAISE_PRIVILEGE	:	__asm volatile
-											(
-												"	mrs r1, control		\n" /* Obtain current control value. */
-												"	bic r1, r1, #1		\n" /* Set privilege bit. */
-												"	msr control, r1		\n" /* Write back new control value. */
-												::: "r1", "memory"
-											);
-											break;
-
-		default							:	/* Unknown SVC call. */
-											break;
-	}
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
-	/* This port can be used on all revisions of the Cortex-M7 core other than
-	the r0p1 parts.  r0p1 parts should use the port from the
-	/source/portable/GCC/ARM_CM7/r0p1 directory. */
-	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
-	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Configure the regions in the MPU that are common to all tasks. */
-	prvSetupMPU();
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Ensure the VFP is enabled - it should be anyway. */
-	vPortEnableVFP();
-
-	/* Lazy save always. */
-	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
-	/* Start the first task. */
-	vPortStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
- BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	vPortResetPrivilege( xRunningPrivileged );
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	configASSERT( uxCriticalNesting );
-
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known. */
-	portDISABLE_INTERRUPTS();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__weak void vPortSetupTimerInterrupt( void )
-{
-	/* Stop and clear the SysTick. */
-	portNVIC_SYSTICK_CTRL_REG = 0UL;
-	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupMPU( void )
-{
-extern uint32_t __privileged_functions_end__[];
-extern uint32_t __FLASH_segment_start__[];
-extern uint32_t __FLASH_segment_end__[];
-extern uint32_t __privileged_data_start__[];
-extern uint32_t __privileged_data_end__[];
-
-	/* Check the expected MPU is present. */
-	if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-	{
-		/* First setup the entire flash for unprivileged read only access. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
-											( portMPU_REGION_VALID ) |
-											( portUNPRIVILEGED_FLASH_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_ONLY ) |
-										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-										( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
-										( portMPU_REGION_ENABLE );
-
-		/* Setup the first 16K for privileged only access (even though less
-		than 10K is actually being used).  This is where the kernel code is
-		placed. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
-											( portMPU_REGION_VALID ) |
-											( portPRIVILEGED_FLASH_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
-										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-										( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
-										( portMPU_REGION_ENABLE );
-
-		/* Setup the privileged data RAM region.  This is where the kernel data
-		is placed. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
-											( portMPU_REGION_VALID ) |
-											( portPRIVILEGED_RAM_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-										prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
-										( portMPU_REGION_ENABLE );
-
-		/* By default allow everything to access the general peripherals.  The
-		system peripherals and registers are protected. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( portPERIPHERALS_START_ADDRESS ) |
-											( portMPU_REGION_VALID ) |
-											( portGENERAL_PERIPHERALS_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
-										( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
-										( portMPU_REGION_ENABLE );
-
-		/* Enable the memory fault exception. */
-		portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
-
-		/* Enable the MPU with the background region configured. */
-		portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
-	}
-}
-/*-----------------------------------------------------------*/
-
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
-{
-uint32_t ulRegionSize, ulReturnValue = 4;
-
-	/* 32 is the smallest region size, 31 is the largest valid value for
-	ulReturnValue. */
-	for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
-	{
-		if( ulActualSizeInBytes <= ulRegionSize )
-		{
-			break;
-		}
-		else
-		{
-			ulReturnValue++;
-		}
-	}
-
-	/* Shift the code by one before returning so it can be written directly
-	into the the correct bit position of the attribute register. */
-	return ( ulReturnValue << 1UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-{
-extern uint32_t __SRAM_segment_start__[];
-extern uint32_t __SRAM_segment_end__[];
-extern uint32_t __privileged_data_start__[];
-extern uint32_t __privileged_data_end__[];
-int32_t lIndex;
-uint32_t ul;
-
-	if( xRegions == NULL )
-	{
-		/* No MPU regions are specified so allow access to all RAM. */
-		xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
-				( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
-				( portMPU_REGION_VALID ) |
-				( portSTACK_REGION );
-
-		xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
-				( portMPU_REGION_READ_WRITE ) |
-				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-				( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
-				( portMPU_REGION_ENABLE );
-
-		/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
-		just removed the privileged only parameters. */
-		xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
-				( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
-				( portMPU_REGION_VALID ) |
-				( portSTACK_REGION + 1 );
-
-		xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
-				( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-				prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
-				( portMPU_REGION_ENABLE );
-
-		/* Invalidate all other regions. */
-		for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
-		{
-			xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
-			xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
-		}
-	}
-	else
-	{
-		/* This function is called automatically when the task is created - in
-		which case the stack region parameters will be valid.  At all other
-		times the stack parameters will not be valid and it is assumed that the
-		stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
-					( ( uint32_t ) pxBottomOfStack ) |
-					( portMPU_REGION_VALID ) |
-					( portSTACK_REGION ); /* Region number. */
-
-			xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
-					( portMPU_REGION_READ_WRITE ) | /* Read and write. */
-					( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
-					( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-					( portMPU_REGION_ENABLE );
-		}
-
-		lIndex = 0;
-
-		for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
-		{
-			if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
-			{
-				/* Translate the generic region definition contained in
-				xRegions into the CM3 specific MPU settings that are then
-				stored in xMPUSettings. */
-				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
-						( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
-						( portMPU_REGION_VALID ) |
-						( portSTACK_REGION + ul ); /* Region number. */
-
-				xMPUSettings->xRegion[ ul ].ulRegionAttribute =
-						( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
-						( xRegions[ lIndex ].ulParameters ) |
-						( portMPU_REGION_ENABLE );
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
-				xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		/* Obtain the number of the currently executing interrupt. */
-		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s b/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s
deleted file mode 100755
index 37f1a80..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portasm.s
+++ /dev/null
@@ -1,199 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include 
-
-	RSEG    CODE:CODE(2)
-	thumb
-
-	EXTERN pxCurrentTCB
-	EXTERN vTaskSwitchContext
-	EXTERN vPortSVCHandler_C
-
-	PUBLIC xPortPendSVHandler
-	PUBLIC vPortSVCHandler
-	PUBLIC vPortStartFirstTask
-	PUBLIC vPortEnableVFP
-	PUBLIC vPortRestoreContextOfFirstTask
-	PUBLIC xIsPrivileged
-	PUBLIC vResetPrivilege
-
-/*-----------------------------------------------------------*/
-
-xPortPendSVHandler:
-	mrs r0, psp
-	isb
-	/* Get the location of the current TCB. */
-	ldr	r3, =pxCurrentTCB
-	ldr	r2, [r3]
-
-	/* Is the task using the FPU context?  If so, push high vfp registers. */
-	tst r14, #0x10
-	it eq
-	vstmdbeq r0!, {s16-s31}
-
-	/* Save the core registers. */
-	mrs r1, control
-	stmdb r0!, {r1, r4-r11, r14}
-
-	/* Save the new top of stack into the first member of the TCB. */
-	str r0, [r2]
-
-	stmdb sp!, {r0, r3}
-	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-	msr basepri, r0
-	dsb
-	isb
-	bl vTaskSwitchContext
-	mov r0, #0
-	msr basepri, r0
-	ldmia sp!, {r0, r3}
-
-	/* The first item in pxCurrentTCB is the task top of stack. */
-	ldr r1, [r3]
-	ldr r0, [r1]
-	/* Move onto the second item in the TCB... */
-	add r1, r1, #4
-	/* Region Base Address register. */
-	ldr r2, =0xe000ed9c
-	/* Read 4 sets of MPU registers. */
-	ldmia r1!, {r4-r11}
-	/* Write 4 sets of MPU registers. */
-	stmia r2!, {r4-r11}
-	/* Pop the registers that are not automatically saved on exception entry. */
-	ldmia r0!, {r3-r11, r14}
-	msr control, r3
-
-	/* Is the task using the FPU context?  If so, pop the high vfp registers
-	too. */
-	tst r14, #0x10
-	it eq
-	vldmiaeq r0!, {s16-s31}
-
-	msr psp, r0
-	isb
-
-	bx r14
-
-
-/*-----------------------------------------------------------*/
-
-vPortSVCHandler:
-	#ifndef USE_PROCESS_STACK	/* Code should not be required if a main() is using the process stack. */
-		tst lr, #4
-		ite eq
-		mrseq r0, msp
-		mrsne r0, psp
-	#else
-		mrs r0, psp
-	#endif
-		b vPortSVCHandler_C
-
-/*-----------------------------------------------------------*/
-
-vPortStartFirstTask:
-	/* Use the NVIC offset register to locate the stack. */
-	ldr r0, =0xE000ED08
-	ldr r0, [r0]
-	ldr r0, [r0]
-	/* Set the msp back to the start of the stack. */
-	msr msp, r0
-	/* Clear the bit that indicates the FPU is in use in case the FPU was used
-	before the scheduler was started - which would otherwise result in the
-	unnecessary leaving of space in the SVC stack for lazy saving of FPU
-	registers. */
-	mov r0, #0
-	msr control, r0
-	/* Call SVC to start the first task. */
-	cpsie i
-	cpsie f
-	dsb
-	isb
-	svc 0
-
-/*-----------------------------------------------------------*/
-
-vPortRestoreContextOfFirstTask:
-	/* Use the NVIC offset register to locate the stack. */
-	ldr r0, =0xE000ED08
-	ldr r0, [r0]
-	ldr r0, [r0]
-	/* Set the msp back to the start of the stack. */
-	msr msp, r0
-	/* Restore the context. */
-	ldr	r3, =pxCurrentTCB
-	ldr r1, [r3]
-	/* The first item in the TCB is the task top of stack. */
-	ldr r0, [r1]
-	/* Move onto the second item in the TCB... */
-	add r1, r1, #4
-	/* Region Base Address register. */
-	ldr r2, =0xe000ed9c
-	/* Read 4 sets of MPU registers. */
-	ldmia r1!, {r4-r11}
-	/* Write 4 sets of MPU registers. */
-	stmia r2!, {r4-r11}
-	/* Pop the registers that are not automatically saved on exception entry. */
-	ldmia r0!, {r3-r11, r14}
-	msr control, r3
-	/* Restore the task stack pointer. */
-	msr psp, r0
-	mov r0, #0
-	msr	basepri, r0
-	bx r14
-
-/*-----------------------------------------------------------*/
-
-vPortEnableVFP:
-	/* The FPU enable bits are in the CPACR. */
-	ldr.w r0, =0xE000ED88
-	ldr	r1, [r0]
-
-	/* Enable CP10 and CP11 coprocessors, then save back. */
-	orr	r1, r1, #( 0xf << 20 )
-	str r1, [r0]
-	bx	r14
-
-/*-----------------------------------------------------------*/
-
-xIsPrivileged:
-	mrs r0, control		/* r0 = CONTROL. */
-	tst r0, #1			/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	ite ne
-	movne r0, #0		/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	moveq r0, #1		/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	bx lr				/* Return. */
-/*-----------------------------------------------------------*/
-
-vResetPrivilege:
-	mrs r0, control		/* r0 = CONTROL. */
-	orr r0, r0, #1		/* r0 = r0 | 1. */
-	msr control, r0		/* CONTROL = r0. */
-	bx lr				/* Return to the caller. */
-/*-----------------------------------------------------------*/
-
-	END
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h
deleted file mode 100755
index ecdd0cf..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM4F_MPU/portmacro.h
+++ /dev/null
@@ -1,228 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* IAR includes. */
-#include 
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* MPU specific constants. */
-#define portUSING_MPU_WRAPPERS		1
-#define portPRIVILEGE_BIT			( 0x80000000UL )
-
-#define portMPU_REGION_READ_WRITE				( 0x03UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY		( 0x05UL << 24UL )
-#define portMPU_REGION_READ_ONLY				( 0x06UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_WRITE	( 0x01UL << 24UL )
-#define portMPU_REGION_CACHEABLE_BUFFERABLE		( 0x07UL << 16UL )
-#define portMPU_REGION_EXECUTE_NEVER			( 0x01UL << 28UL )
-
-#define portUNPRIVILEGED_FLASH_REGION			( 0UL )
-#define portPRIVILEGED_FLASH_REGION				( 1UL )
-#define portPRIVILEGED_RAM_REGION				( 2UL )
-#define portGENERAL_PERIPHERALS_REGION			( 3UL )
-#define portSTACK_REGION						( 4UL )
-#define portFIRST_CONFIGURABLE_REGION			( 5UL )
-#define portLAST_CONFIGURABLE_REGION			( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS			( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS					( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-#define portSWITCH_TO_USER_MODE() __asm volatile ( " mrs r0, control \n orr r0, r0, #1 \n msr control, r0 " ::: "r0", "memory" )
-
-typedef struct MPU_REGION_REGISTERS
-{
-	uint32_t ulRegionBaseAddress;
-	uint32_t ulRegionAttribute;
-} xMPU_REGION_REGISTERS;
-
-/* Plus 1 to create space for the stack region. */
-typedef struct MPU_SETTINGS
-{
-	xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
-} xMPU_SETTINGS;
-
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-/* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER				0
-#define portSVC_YIELD						1
-#define portSVC_RAISE_PRIVILEGE				2
-
-/* Scheduler utilities. */
-#define portYIELD()				__asm volatile ( "	SVC	%0	\n" :: "i" (portSVC_YIELD) : "memory" )
-#define portYIELD_WITHIN_API()								\
-{															\
-	/* Set a PendSV to request a context switch. */			\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
-	__DSB();												\
-	__ISB();												\
-}
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD_WITHIN_API()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()							\
-{															\
-	__set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
-	__DSB();												\
-	__ISB();												\
-}
-
-#define portENABLE_INTERRUPTS()					__set_BASEPRI( 0 )
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()		__get_BASEPRI(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	__set_BASEPRI( x )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-/*-----------------------------------------------------------*/
-
-extern BaseType_t xIsPrivileged( void );
-extern void vResetPrivilege( void );
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-#define portIS_PRIVILEGED()			xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
-*/
-#define portRAISE_PRIVILEGE()		__asm volatile ( "svc %0 \n" :: "i" ( portSVC_RAISE_PRIVILEGE ) : "memory" );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
-#define portRESET_PRIVILEGE()		vResetPrivilege()
-/*-----------------------------------------------------------*/
-
-/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
-the source code because to do so would cause other compilers to generate
-warnings. */
-#pragma diag_suppress=Pe191
-#pragma diag_suppress=Pa082
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM7/ReadMe.txt b/FreeRTOS/Source/portable/IAR/ARM_CM7/ReadMe.txt
deleted file mode 100755
index 5ecbe81..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM7/ReadMe.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
-The best option depends on the revision of the ARM Cortex-M7 core in use.  The
-revision is specified by an 'r' number, and a 'p' number, so will look something
-like 'r0p1'.  Check the documentation for the microcontroller in use to find the 
-revision of the Cortex-M7 core used in that microcontroller.  If in doubt, use 
-the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
-with all core revisions.
-
-The first option is to use the ARM Cortex-M4F port, and the second option is to
-use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
-
-If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
-used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in 
-the /FreeRTOS/Source/portable/IAR/ARM_CM4F directory.
-
-If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
-Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1
-directory.
\ No newline at end of file
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c b/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c
deleted file mode 100755
index 3a1f873..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/port.c
+++ /dev/null
@@ -1,644 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
-
-/* IAR includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __ARMVFP__
-	#error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#if( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 )
-	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
-
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR					( 0x01000000 )
-#define portINITIAL_EXC_RETURN				( 0xfffffffd )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR			( 45UL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortSysTickHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-extern void vPortStartFirstTask( void );
-
-/*
- * Turn the VFP on.
- */
-extern void vPortEnableVFP( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-
-	/* Offset added to account for the way the MCU uses the stack on entry/exit
-	of interrupts, and to ensure alignment. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
-
-	/* Save code space by skipping register initialisation. */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-
-	/* A save method is being used that requires each task to maintain its
-	own exec return value. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Ensure the VFP is enabled - it should be anyway. */
-	vPortEnableVFP();
-
-	/* Lazy save always. */
-	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
-	/* Start the first task. */
-	vPortStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known. */
-	portDISABLE_INTERRUPTS();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TICKLESS_IDLE == 1 )
-
-	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-	TickType_t xModifiableIdleTime;
-
-		/* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
-		is accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-		/* Calculate the reload value required to wait xExpectedIdleTime
-		tick periods.  -1 is used because this code will execute part way
-		through one of the tick periods. */
-		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-		if( ulReloadValue > ulStoppedTimerCompensation )
-		{
-			ulReloadValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Enter a critical section but don't use the taskENTER_CRITICAL()
-		method as that will mask interrupts that should exit sleep mode. */
-		__disable_interrupt();
-		__DSB();
-		__ISB();
-
-		/* If a context switch is pending or a task is waiting for the scheduler
-		to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-		{
-			/* Restart from whatever is left in the count register to complete
-			this tick period. */
-			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Reset the reload register to the value required for normal tick
-			periods. */
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Re-enable interrupts - see comments above __disable_interrupt()
-			call above. */
-			__enable_interrupt();
-		}
-		else
-		{
-			/* Set the new reload value. */
-			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-			/* Clear the SysTick count flag and set the count value back to
-			zero. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-			set its parameter to 0 to indicate that its implementation contains
-			its own wait for interrupt or wait for event instruction, and so wfi
-			should not be executed again.  However, the original expected idle
-			time variable must remain unmodified, so a copy is taken. */
-			xModifiableIdleTime = xExpectedIdleTime;
-			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-			if( xModifiableIdleTime > 0 )
-			{
-				__DSB();
-				__WFI();
-				__ISB();
-			}
-			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-			/* Re-enable interrupts to allow the interrupt that brought the MCU
-			out of sleep mode to execute immediately.  see comments above
-			__disable_interrupt() call above. */
-			__enable_interrupt();
-			__DSB();
-			__ISB();
-
-			/* Disable interrupts again because the clock is about to be stopped
-			and interrupts that execute while the clock is stopped will increase
-			any slippage between the time maintained by the RTOS and calendar
-			time. */
-			__disable_interrupt();
-			__DSB();
-			__ISB();
-			
-			/* Disable the SysTick clock without reading the 
-			portNVIC_SYSTICK_CTRL_REG register to ensure the
-			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again, 
-			the time the SysTick is stopped for is accounted for as best it can 
-			be, but using the tickless mode will inevitably result in some tiny 
-			drift of the time maintained by the kernel with respect to calendar 
-			time*/
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-			/* Determine if the SysTick clock has already counted to zero and
-			been set back to the current reload value (the reload back being
-			correct for the entire expected idle time) or if the SysTick is yet
-			to count to zero (in which case an interrupt other than the SysTick
-			must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-			{
-				uint32_t ulCalculatedLoadValue;
-
-				/* The tick interrupt is already pending, and the SysTick count
-				reloaded with ulReloadValue.  Reset the
-				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-				period. */
-				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-				/* Don't allow a tiny value, or values that have somehow
-				underflowed because the post sleep hook did something
-				that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-				{
-					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-				}
-
-				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-				/* As the pending tick will be processed as soon as this
-				function exits, the tick value maintained by the tick is stepped
-				forward by one less than the time spent waiting. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				Work out how long the sleep lasted rounded to complete tick
-				periods (not the ulReload value which accounted for part
-				ticks). */
-				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-				/* How many complete tick periods passed while the processor
-				was waiting? */
-				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-				/* The reload value is set to whatever fraction of a single tick
-				period remains. */
-				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-			}
-
-			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-			vTaskStepTick( ulCompleteTickPeriods );
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Exit with interrpts enabled. */
-			__enable_interrupt();
-		}
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-__weak void vPortSetupTimerInterrupt( void )
-{
-	/* Calculate the constants required to configure the tick interrupt. */
-	#if( configUSE_TICKLESS_IDLE == 1 )
-	{
-		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-	}
-	#endif /* configUSE_TICKLESS_IDLE */
-
-	/* Stop and clear the SysTick. */
-	portNVIC_SYSTICK_CTRL_REG = 0UL;
-	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		/* Obtain the number of the currently executing interrupt. */
-		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) :: "memory" );
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s b/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
deleted file mode 100755
index ad8070c..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portasm.s
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include 
-
-	RSEG    CODE:CODE(2)
-	thumb
-
-	EXTERN pxCurrentTCB
-	EXTERN vTaskSwitchContext
-
-	PUBLIC xPortPendSVHandler
-	PUBLIC vPortSVCHandler
-	PUBLIC vPortStartFirstTask
-	PUBLIC vPortEnableVFP
-
-
-/*-----------------------------------------------------------*/
-
-xPortPendSVHandler:
-	mrs r0, psp
-	isb
-	/* Get the location of the current TCB. */
-	ldr	r3, =pxCurrentTCB
-	ldr	r2, [r3]
-
-	/* Is the task using the FPU context?  If so, push high vfp registers. */
-	tst r14, #0x10
-	it eq
-	vstmdbeq r0!, {s16-s31}
-
-	/* Save the core registers. */
-	stmdb r0!, {r4-r11, r14}
-
-	/* Save the new top of stack into the first member of the TCB. */
-	str r0, [r2]
-
-	stmdb sp!, {r0, r3}
-	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-	cpsid i
-	msr basepri, r0
-	dsb
-	isb
-	cpsie i
-	bl vTaskSwitchContext
-	mov r0, #0
-	msr basepri, r0
-	ldmia sp!, {r0, r3}
-
-	/* The first item in pxCurrentTCB is the task top of stack. */
-	ldr r1, [r3]
-	ldr r0, [r1]
-
-	/* Pop the core registers. */
-	ldmia r0!, {r4-r11, r14}
-
-	/* Is the task using the FPU context?  If so, pop the high vfp registers
-	too. */
-	tst r14, #0x10
-	it eq
-	vldmiaeq r0!, {s16-s31}
-
-	msr psp, r0
-	isb
-	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
-		#if WORKAROUND_PMU_CM001 == 1
-			push { r14 }
-			pop { pc }
-		#endif
-	#endif
-
-	bx r14
-
-
-/*-----------------------------------------------------------*/
-
-vPortSVCHandler:
-	/* Get the location of the current TCB. */
-	ldr	r3, =pxCurrentTCB
-	ldr r1, [r3]
-	ldr r0, [r1]
-	/* Pop the core registers. */
-	ldmia r0!, {r4-r11, r14}
-	msr psp, r0
-	isb
-	mov r0, #0
-	msr	basepri, r0
-	bx r14
-
-/*-----------------------------------------------------------*/
-
-vPortStartFirstTask
-	/* Use the NVIC offset register to locate the stack. */
-	ldr r0, =0xE000ED08
-	ldr r0, [r0]
-	ldr r0, [r0]
-	/* Set the msp back to the start of the stack. */
-	msr msp, r0
-	/* Clear the bit that indicates the FPU is in use in case the FPU was used
-	before the scheduler was started - which would otherwise result in the
-	unnecessary leaving of space in the SVC stack for lazy saving of FPU
-	registers. */
-	mov r0, #0
-	msr control, r0
-	/* Call SVC to start the first task. */
-	cpsie i
-	cpsie f
-	dsb
-	isb
-	svc 0
-
-/*-----------------------------------------------------------*/
-
-vPortEnableVFP:
-	/* The FPU enable bits are in the CPACR. */
-	ldr.w r0, =0xE000ED88
-	ldr	r1, [r0]
-
-	/* Enable CP10 and CP11 coprocessors, then save back. */
-	orr	r1, r1, #( 0xf << 20 )
-	str r1, [r0]
-	bx	r14
-
-
-
-	END
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
deleted file mode 100755
index 9f3c261..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CM7/r0p1/portmacro.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* IAR includes. */
-#include 
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD()											\
-{															\
-	/* Set a PendSV to request a context switch. */			\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;			\
-	__DSB();												\
-	__ISB();												\
-}
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 )
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( ( uint32_t ) __CLZ( ( uxReadyPriorities ) ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()							\
-{															\
-	 /* Errata work around. */								\
-	__disable_interrupt();									\
-	__set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY );	\
-	__DSB();												\
-	__ISB();												\
-	__enable_interrupt();									\
-}
-
-#define portENABLE_INTERRUPTS()					__set_BASEPRI( 0 )
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()		__get_BASEPRI(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	__set_BASEPRI( x )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-/*-----------------------------------------------------------*/
-
-/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
-the source code because to do so would cause other compilers to generate
-warnings. */
-#pragma diag_suppress=Pe191
-#pragma diag_suppress=Pa082
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c b/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c
deleted file mode 100755
index 13c8deb..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/port.c
+++ /dev/null
@@ -1,316 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#ifndef configSETUP_TICK_INTERRUPT
-	#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
-#endif
-
-#ifndef configCLEAR_TICK_INTERRUPT
-	#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
-
-/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS			( 0x01UL )
-
-/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK			( 0x1F )
-
-/* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE				( 0x10 )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing.  This function is necessarily written in
- * assembly code so is implemented in portASM.s.
- */
-extern void vPortRestoreTaskContext( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
-volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
-
-/* Set to 1 to pend a context switch from an ISR. */
-volatile uint32_t ulPortYieldRequired = pdFALSE;
-
-/* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
-volatile uint32_t ulPortInterruptNesting = 0UL;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro.
-
-	The fist real value on the stack is the status register, which is set for
-	system mode, with interrupts enabled.  A few NULLs are added first to ensure
-	GDB does not try decoding a non-existent return address. */
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
-	{
-		/* The task will start in THUMB mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-
-	pxTopOfStack--;
-
-	/* Next the return address, which in this case is the start of the task. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-
-	/* Next all the registers other than the stack pointer. */
-	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The task will start with a critical nesting count of 0 as interrupts are
-	enabled. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-	pxTopOfStack--;
-
-	/* The task will start without a floating point context.  A task that uses
-	the floating point hardware must call vPortTaskUsesFPU() before executing
-	any floating point instructions. */
-	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( ulPortInterruptNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-uint32_t ulAPSR;
-
-	/* Only continue if the CPU is not in User mode.  The CPU must be in a
-	Privileged mode for the scheduler to start. */
-	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
-	ulAPSR &= portAPSR_MODE_BITS_MASK;
-	configASSERT( ulAPSR != portAPSR_USER_MODE );
-
-	if( ulAPSR != portAPSR_USER_MODE )
-	{
-		/* Start the timer that generates the tick ISR. */
-		portDISABLE_INTERRUPTS();
-		configSETUP_TICK_INTERRUPT();
-
-		/* Start the first task executing. */
-		vPortRestoreTaskContext();
-	}
-
-	/* Will only get here if vTaskStartScheduler() was called with the CPU in
-	a non-privileged mode or the binary point register was not set to its lowest
-	possible value.  prvTaskExitError() is referenced to prevent a compiler
-	warning about it being defined but not referenced in the case that the user
-	defines their own exit address. */
-	( void ) prvTaskExitError;
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( ulCriticalNesting == 1 )
-	{
-		configASSERT( ulPortInterruptNesting == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as the critical section is being
-		exited. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then all interrupt
-		priorities must be re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Critical nesting has reached zero so all interrupt priorities
-			should be unmasked. */
-			portENABLE_INTERRUPTS();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void FreeRTOS_Tick_Handler( void )
-{
-uint32_t ulInterruptStatus;
-
-	ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-
-	/* Increment the RTOS tick. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		ulPortYieldRequired = pdTRUE;
-	}
-
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
-
-	configCLEAR_TICK_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortTaskUsesFPU( void )
-{
-uint32_t ulInitialFPSCR = 0;
-
-	/* A task is registering the fact that it needs an FPU context.  Set the
-	FPU flag (which is saved as part of the task context). */
-	ulPortTaskHasFPUContext = pdTRUE;
-
-	/* Initialise the floating point status register. */
-	__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) );
-}
-/*-----------------------------------------------------------*/
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s b/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s
deleted file mode 100755
index 9366775..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portASM.s
+++ /dev/null
@@ -1,247 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-#include "FreeRTOSConfig.h"
-
-	SECTION .text:CODE:ROOT(2)
-	arm
-
-	/* Variables and functions. */
-	EXTERN pxCurrentTCB
-	EXTERN vTaskSwitchContext
-	EXTERN vApplicationIRQHandler
-	EXTERN ulPortInterruptNesting
-	EXTERN ulPortTaskHasFPUContext
-	EXTERN ulPortYieldRequired
-	EXTERN ulCriticalNesting
-
-	PUBLIC FreeRTOS_IRQ_Handler
-	PUBLIC FreeRTOS_SVC_Handler
-	PUBLIC vPortRestoreTaskContext
-
-SYS_MODE			EQU		0x1f
-SVC_MODE			EQU		0x13
-IRQ_MODE			EQU		0x12
-
-portSAVE_CONTEXT MACRO
-
-	/* Save the LR and SPSR onto the system mode stack before switching to
-	system mode to save the remaining system mode registers. */
-	SRSDB	sp!, #SYS_MODE
-	CPS		#SYS_MODE
-	PUSH	{R0-R12, R14}
-
-	/* Push the critical nesting count. */
-	LDR		R2, =ulCriticalNesting
-	LDR		R1, [R2]
-	PUSH	{R1}
-
-	/* Does the task have a floating point context that needs saving?  If
-	ulPortTaskHasFPUContext is 0 then no. */
-	LDR		R2, =ulPortTaskHasFPUContext
-	LDR		R3, [R2]
-	CMP		R3, #0
-
-	/* Save the floating point context, if any. */
-	FMRXNE  R1,  FPSCR
-	VPUSHNE {D0-D15}
-#if configFPU_D32 == 1
-	VPUSHNE	{D16-D31}
-#endif /* configFPU_D32 */
-	PUSHNE	{R1}
-
-	/* Save ulPortTaskHasFPUContext itself. */
-	PUSH	{R3}
-
-	/* Save the stack pointer in the TCB. */
-	LDR		R0, =pxCurrentTCB
-	LDR		R1, [R0]
-	STR		SP, [R1]
-
-	ENDM
-
-; /**********************************************************************/
-
-portRESTORE_CONTEXT MACRO
-
-	/* Set the SP to point to the stack of the task being restored. */
-	LDR		R0, =pxCurrentTCB
-	LDR		R1, [R0]
-	LDR		SP, [R1]
-
-	/* Is there a floating point context to restore?  If the restored
-	ulPortTaskHasFPUContext is zero then no. */
-	LDR		R0, =ulPortTaskHasFPUContext
-	POP		{R1}
-	STR		R1, [R0]
-	CMP		R1, #0
-
-	/* Restore the floating point context, if any. */
-	POPNE 	{R0}
-#if configFPU_D32 == 1
-	VPOPNE	{D16-D31}
-#endif /* configFPU_D32 */
-	VPOPNE	{D0-D15}
-	VMSRNE  FPSCR, R0
-
-	/* Restore the critical section nesting depth. */
-	LDR		R0, =ulCriticalNesting
-	POP		{R1}
-	STR		R1, [R0]
-
-	/* Restore all system mode registers other than the SP (which is already
-	being used). */
-	POP		{R0-R12, R14}
-
-	/* Return to the task code, loading CPSR on the way. */
-	RFEIA	sp!
-
-	ENDM
-
-
-
-
-/******************************************************************************
- * SVC handler is used to yield.
- *****************************************************************************/
-FreeRTOS_SVC_Handler:
-	/* Save the context of the current task and select a new task to run. */
-	portSAVE_CONTEXT
-	LDR R0, =vTaskSwitchContext
-	BLX	R0
-	portRESTORE_CONTEXT
-
-
-/******************************************************************************
- * vPortRestoreTaskContext is used to start the scheduler.
- *****************************************************************************/
-vPortRestoreTaskContext:
-	/* Switch to system mode. */
-	CPS		#SYS_MODE
-	portRESTORE_CONTEXT
-
-FreeRTOS_IRQ_Handler:
-	/* Return to the interrupted instruction. */
-	SUB		lr, lr, #4
-
-	/* Push the return address and SPSR. */
-	PUSH	{lr}
-	MRS		lr, SPSR
-	PUSH	{lr}
-
-	/* Change to supervisor mode to allow reentry. */
-	CPS		#SVC_MODE
-
-	/* Push used registers. */
-	PUSH	{r0-r3, r12}
-
-	/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
-	for future use.  r1 holds the original ulPortInterruptNesting value for
-	future use. */
-	LDR		r3, =ulPortInterruptNesting
-	LDR		r1, [r3]
-	ADD		r0, r1, #1
-	STR		r0, [r3]
-
-	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
-	future use. */
-	MOV		r0, sp
-	AND		r2, r0, #4
-	SUB		sp, sp, r2
-
-	/* Call the interrupt handler. */
-	PUSH	{r0-r3, lr}
-	LDR		r1, =vApplicationIRQHandler
-	BLX		r1
-	POP		{r0-r3, lr}
-	ADD		sp, sp, r2
-
-	CPSID	i
-	DSB
-	ISB
-
-	/* Write to the EOI register. */
-	LDR 	r2, =configEOI_ADDRESS
-	STR		r0, [r2]
-
-	/* Restore the old nesting count. */
-	STR		r1, [r3]
-
-	/* A context switch is never performed if the nesting count is not 0. */
-	CMP		r1, #0
-	BNE		exit_without_switch
-
-	/* Did the interrupt request a context switch?  r1 holds the address of
-	ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
-	use. */
-	LDR		r1, =ulPortYieldRequired
-	LDR		r0, [r1]
-	CMP		r0, #0
-	BNE		switch_before_exit
-
-exit_without_switch:
-	/* No context switch.  Restore used registers, LR_irq and SPSR before
-	returning. */
-	POP		{r0-r3, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	MOVS	PC, LR
-
-switch_before_exit:
-	/* A context swtich is to be performed.  Clear the context switch pending
-	flag. */
-	MOV		r0, #0
-	STR		r0, [r1]
-
-	/* Restore used registers, LR-irq and SPSR before saving the context
-	to the task stack. */
-	POP		{r0-r3, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	portSAVE_CONTEXT
-
-	/* Call the function that selects the new task to execute.
-	vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
-	instructions, or 8 byte aligned stack allocated data.  LR does not need
-	saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
-	LDR		R0, =vTaskSwitchContext
-	BLX		R0
-
-	/* Restore the context of, and branch to, the task selected to execute
-	next. */
-	portRESTORE_CONTEXT
-
-	END
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h b/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h
deleted file mode 100755
index 30c877a..0000000
--- a/FreeRTOS/Source/portable/IAR/ARM_CRx_No_GIC/portmacro.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#include 
-
-#ifdef __cplusplus
-	extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{												\
-extern volatile uint32_t ulPortYieldRequired;	\
-												\
-	if( xSwitchRequired != pdFALSE )			\
-	{											\
-		ulPortYieldRequired = pdTRUE;			\
-	}											\
-}
-
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SWI 0		\n"				\
-									 "ISB		  " );
-
-
-/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-extern void vPortInstallFreeRTOSVectorTable( void );
-
-/* The I bit within the CPSR. */
-#define portINTERRUPT_ENABLE_BIT	( 1 << 7 )
-
-/* In the absence of a priority mask register, these functions and macros
-globally enable and disable interrupts. */
-#define portENTER_CRITICAL()		vPortEnterCritical();
-#define portEXIT_CRITICAL()			vPortExitCritical();
-#define portENABLE_INTERRUPTS()		__asm volatile ( "CPSIE i 	\n"	);
-#define portDISABLE_INTERRUPTS()	__asm volatile ( "CPSID i 	\n"		\
-													 "DSB		\n"		\
-													 "ISB		  " );
-#pragma inline
-static inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
-{
-volatile uint32_t ulCPSR;
-
-	__asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) );
-	ulCPSR &= portINTERRUPT_ENABLE_BIT;
-	portDISABLE_INTERRUPTS();
-	return ulCPSR;
-}
-
-#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	if( x == 0 ) portENABLE_INTERRUPTS()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
-
-/* Prototype of the FreeRTOS tick handler.  This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
-void FreeRTOS_Tick_Handler( void );
-
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
-void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __CLZ( uxReadyPriorities ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE inline
-
-/* Suppress warnings that are generated by the IAR tools, but cannot be fixed in
-the source code because to do so would cause other compilers to generate
-warnings. */
-#pragma diag_suppress=Pe191
-#pragma diag_suppress=Pa082
-
-#ifdef __cplusplus
-	} /* extern C */
-#endif
-
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/ATMega323/port.c b/FreeRTOS/Source/portable/IAR/ATMega323/port.c
deleted file mode 100755
index 2bdb430..0000000
--- a/FreeRTOS/Source/portable/IAR/ATMega323/port.c
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include 
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the AVR/IAR port.
- *----------------------------------------------------------*/
-
-/* Start tasks with interrupts enables. */
-#define portFLAGS_INT_ENABLED					( ( StackType_t ) 0x80 )
-
-/* Hardware constants for timer 1. */
-#define portCLEAR_COUNTER_ON_MATCH				( ( uint8_t ) 0x08 )
-#define portPRESCALE_64							( ( uint8_t ) 0x03 )
-#define portCLOCK_PRESCALER						( ( uint32_t ) 64 )
-#define portCOMPARE_MATCH_A_INTERRUPT_ENABLE	( ( uint8_t ) 0x10 )
-
-/* The number of bytes used on the hardware stack by the task start address. */
-#define portBYTES_USED_BY_RETURN_ADDRESS		( 2 )
-/*-----------------------------------------------------------*/
-
-/* Stores the critical section nesting.  This must not be initialised to 0.
-It will be initialised when a task starts. */
-#define portNO_CRITICAL_NESTING					( ( UBaseType_t ) 0 )
-UBaseType_t uxCriticalNesting = 0x50;
-
-
-/*
- * Perform hardware setup to enable ticks from timer 1, compare match A.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * The IAR compiler does not have full support for inline assembler, so
- * these are defined in the portmacro assembler file.
- */
-extern void vPortYieldFromTick( void );
-extern void vPortStart( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint16_t usAddress;
-StackType_t *pxTopOfHardwareStack;
-
-	/* Place a few bytes of known values on the bottom of the stack.
-	This is just useful for debugging. */
-
-	*pxTopOfStack = 0x11;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x22;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x33;
-	pxTopOfStack--;
-
-	/* Remember where the top of the hardware stack is - this is required
-	below. */
-	pxTopOfHardwareStack = pxTopOfStack;
-
-
-	/* Simulate how the stack would look after a call to vPortYield(). */
-
-	/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
-
-
-
-	/* The IAR compiler requires two stacks per task.  First there is the
-	hardware call stack which uses the AVR stack pointer.  Second there is the
-	software stack (local variables, parameter passing, etc.) which uses the
-	AVR Y register.
-
-	This function places both stacks within the memory block passed in as the
-	first parameter.  The hardware stack is placed at the bottom of the memory
-	block.  A gap is then left for the hardware stack to grow.  Next the software
-	stack is placed.  The amount of space between the software and hardware
-	stacks is defined by configCALL_STACK_SIZE.
-
-
-
-	The first part of the stack is the hardware stack.  Place the start
-	address of the task on the hardware stack. */
-	usAddress = ( uint16_t ) pxCode;
-	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
-	pxTopOfStack--;
-
-	usAddress >>= 8;
-	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
-	pxTopOfStack--;
-
-
-	/* Leave enough space for the hardware stack before starting the software
-	stack.  The '- 2' is because we have already used two spaces for the
-	address of the start of the task. */
-	pxTopOfStack -= ( configCALL_STACK_SIZE - 2 );
-
-
-
-	/* Next simulate the stack as if after a call to portSAVE_CONTEXT().
-	portSAVE_CONTEXT places the flags on the stack immediately after r0
-	to ensure the interrupts get disabled as soon as possible, and so ensuring
-	the stack use is minimal should a context switch interrupt occur. */
-	*pxTopOfStack = ( StackType_t ) 0x00;	/* R0 */
-	pxTopOfStack--;
-	*pxTopOfStack = portFLAGS_INT_ENABLED;
-	pxTopOfStack--;
-
-	/* Next place the address of the hardware stack.  This is required so
-	the AVR stack pointer can be restored to point to the hardware stack. */
-	pxTopOfHardwareStack -= portBYTES_USED_BY_RETURN_ADDRESS;
-	usAddress = ( uint16_t ) pxTopOfHardwareStack;
-
-	/* SPL */
-	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
-	pxTopOfStack--;
-
-	/* SPH */
-	usAddress >>= 8;
-	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
-	pxTopOfStack--;
-
-
-
-
-	/* Now the remaining registers. */
-	*pxTopOfStack = ( StackType_t ) 0x01;	/* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x02;	/* R2 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x03;	/* R3 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x04;	/* R4 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x05;	/* R5 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x06;	/* R6 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x07;	/* R7 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x08;	/* R8 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x09;	/* R9 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x10;	/* R10 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x11;	/* R11 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12;	/* R12 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x13;	/* R13 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x14;	/* R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x15;	/* R15 */
-	pxTopOfStack--;
-
-	/* Place the parameter on the stack in the expected location. */
-	usAddress = ( uint16_t ) pvParameters;
-	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
-	pxTopOfStack--;
-
-	usAddress >>= 8;
-	*pxTopOfStack = ( StackType_t ) ( usAddress & ( uint16_t ) 0x00ff );
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0x18;	/* R18 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x19;	/* R19 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x20;	/* R20 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x21;	/* R21 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x22;	/* R22 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x23;	/* R23 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x24;	/* R24 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x25;	/* R25 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x26;	/* R26 X */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x27;	/* R27 */
-	pxTopOfStack--;
-
-	/* The Y register is not stored as it is used as the software stack and
-	gets saved into the task control block. */
-
-	*pxTopOfStack = ( StackType_t ) 0x30;	/* R30 Z */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x031;	/* R31 */
-
-	pxTopOfStack--;
-	*pxTopOfStack = portNO_CRITICAL_NESTING;	/* Critical nesting is zero when the task starts. */
-
-	/*lint +e950 +e611 +e923 */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Setup the hardware to generate the tick. */
-	prvSetupTimerInterrupt();
-
-	/* Restore the context of the first task that is going to run.
-	Normally we would just call portRESTORE_CONTEXT() here, but as the IAR
-	compiler does not fully support inline assembler we have to make a call.*/
-	vPortStart();
-
-	/* Should not get here! */
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the AVR port will get stopped.  If required simply
-	disable the tick interrupt here. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup timer 1 compare match A to generate a tick interrupt.
- */
-static void prvSetupTimerInterrupt( void )
-{
-uint32_t ulCompareMatch;
-uint8_t ucHighByte, ucLowByte;
-
-	/* Using 16bit timer 1 to generate the tick.  Correct fuses must be
-	selected for the configCPU_CLOCK_HZ clock. */
-
-	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-
-	/* We only have 16 bits so have to scale to get our required tick rate. */
-	ulCompareMatch /= portCLOCK_PRESCALER;
-
-	/* Adjust for correct value. */
-	ulCompareMatch -= ( uint32_t ) 1;
-
-	/* Setup compare match value for compare match A.  Interrupts are disabled
-	before this is called so we need not worry here. */
-	ucLowByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
-	ulCompareMatch >>= 8;
-	ucHighByte = ( uint8_t ) ( ulCompareMatch & ( uint32_t ) 0xff );
-	OCR1AH = ucHighByte;
-	OCR1AL = ucLowByte;
-
-	/* Setup clock source and compare match behaviour. */
-	ucLowByte = portCLEAR_COUNTER_ON_MATCH | portPRESCALE_64;
-	TCCR1B = ucLowByte;
-
-	/* Enable the interrupt - this is okay as interrupt are currently globally
-	disabled. */
-	TIMSK |= portCOMPARE_MATCH_A_INTERRUPT_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_PREEMPTION == 1
-
-	/*
-	 * Tick ISR for preemptive scheduler.  We can use a __task attribute as
-	 * the context is saved at the start of vPortYieldFromTick().  The tick
-	 * count is incremented after the context is saved.
-	 */
-	__task void SIG_OUTPUT_COMPARE1A( void )
-	{
-		vPortYieldFromTick();
-		asm( "reti" );
-	}
-
-#else
-
-	/*
-	 * Tick ISR for the cooperative scheduler.  All this does is increment the
-	 * tick count.  We don't need to switch context, this can only be done by
-	 * manual calls to taskYIELD();
-	 *
-	 * THE INTERRUPT VECTOR IS POPULATED IN portmacro.s90.  DO NOT INSTALL
-	 * IT HERE USING THE USUAL PRAGMA.
-	 */
-	__interrupt void SIG_OUTPUT_COMPARE1A( void )
-	{
-		xTaskIncrementTick();
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	uxCriticalNesting--;
-	if( uxCriticalNesting == portNO_CRITICAL_NESTING )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.h b/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.h
deleted file mode 100755
index 822995a..0000000
--- a/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-Changes from V1.2.3
-
-	+ portCPU_CLOSK_HZ definition changed to 8MHz base 10, previously it
-	  base 16.
-*/
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		int
-#define portSTACK_TYPE	uint8_t
-#define portBASE_TYPE	char
-#define portPOINTER_SIZE_TYPE uint16_t
-
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portENTER_CRITICAL()	vPortEnterCritical()
-#define portEXIT_CRITICAL()		vPortExitCritical()
-
-#define portDISABLE_INTERRUPTS()	asm( "cli" )
-#define portENABLE_INTERRUPTS()		asm( "sei" )
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			1
-#define portNOP()					asm( "nop" )
-/*-----------------------------------------------------------*/
-
-/* Kernel utilities. */
-void vPortYield( void );
-#define portYIELD()	vPortYield()
-
-#ifdef IAR_MEGA_AVR
-	#define outb( PORT, VALUE ) PORT = VALUE
-#endif
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
-
diff --git a/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.s90 b/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.s90
deleted file mode 100755
index 0ecf983..0000000
--- a/FreeRTOS/Source/portable/IAR/ATMega323/portmacro.s90
+++ /dev/null
@@ -1,245 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-#include 
-
-; Declare all extern symbols here - including any ISRs that are referenced in
-; the vector table.
-
-; ISR functions
-; -------------
-EXTERN SIG_OUTPUT_COMPARE1A
-EXTERN SIG_UART_RECV
-EXTERN SIG_UART_DATA
-
-
-; Functions used by scheduler
-; ---------------------------
-EXTERN vTaskSwitchContext
-EXTERN pxCurrentTCB
-EXTERN xTaskIncrementTick
-EXTERN uxCriticalNesting
-
-; Functions implemented in this file
-; ----------------------------------
-PUBLIC vPortYield
-PUBLIC vPortYieldFromTick
-PUBLIC vPortStart
-
-
-; Interrupt vector table.
-; -----------------------
-;
-; For simplicity the RTOS tick interrupt routine uses the __task keyword.
-; As the IAR compiler does not permit a function to be declared using both
-; __task and __interrupt, the use of __task necessitates that the interrupt
-; vector table be setup manually.
-;
-; To write an ISR, implement the ISR function using the __interrupt keyword
-; but do not install the interrupt using the "#pragma vector=ABC" method.
-; Instead manually place the name of the ISR in the vector table using an
-; ORG and jmp instruction as demonstrated below.
-; You will also have to add an EXTERN statement at the top of the file.
-
-	ASEG
-
-
-	ORG TIMER1_COMPA_vect				; Vector address
-		jmp SIG_OUTPUT_COMPARE1A		; ISR
-
-	ORG USART_RXC_vect					; Vector address
-		jmp SIG_UART_RECV				; ISR
-
-	ORG USART_UDRE_vect					; Vector address
-		jmp SIG_UART_DATA				; ISR
-
-
-	RSEG CODE
-
-
-
-; Saving and Restoring a Task Context and Task Switching
-; ------------------------------------------------------
-;
-; The IAR compiler does not fully support inline assembler, so saving and
-; restoring a task context has to be written in an asm file.
-;
-; vPortYield() and vPortYieldFromTick() are usually written in C.  Doing
-; so in this case would required calls to be made to portSAVE_CONTEXT() and
-; portRESTORE_CONTEXT().  This is dis-advantageous as the context switch
-; function would require two extra jump and return instructions over the
-; WinAVR equivalent.
-;
-; To avoid this I have opted to implement both vPortYield() and
-; vPortYieldFromTick() in this assembly file.  For convenience
-; portSAVE_CONTEXT and portRESTORE_CONTEXT are implemented as macros.
-
-portSAVE_CONTEXT MACRO
-	st	-y, r0			; First save the r0 register - we need to use this.
-	in	r0, SREG		; Obtain the SREG value so we can disable interrupts...
-	cli					; ... as soon as possible.
-	st	-y, r0			; Store the SREG as it was before we disabled interrupts.
-
-	in	r0, SPL			; Next store the hardware stack pointer.  The IAR...
-	st	-y, r0			; ... compiler uses the hardware stack as a call stack ...
-	in	r0, SPH			; ...  only.
-	st	-y, r0
-
-	st	-y, r1			; Now store the rest of the registers.  Dont store the ...
-	st	-y, r2			; ... the Y register here as it is used as the software
-	st	-y, r3			; stack pointer and will get saved into the TCB.
-	st	-y, r4
-	st	-y, r5
-	st	-y, r6
-	st	-y, r7
-	st	-y, r8
-	st	-y, r9
-	st	-y, r10
-	st	-y, r11
-	st	-y, r12
-	st	-y, r13
-	st	-y, r14
-	st	-y, r15
-	st	-y, r16
-	st	-y, r17
-	st	-y, r18
-	st	-y, r19
-	st	-y, r20
-	st	-y, r21
-	st	-y, r22
-	st	-y, r23
-	st	-y, r24
-	st	-y, r25
-	st	-y, r26
-	st	-y, r27
-	st	-y, r30
-	st	-y, r31
-	lds r0, uxCriticalNesting
-	st	-y, r0					; Store the critical nesting counter.
-
-	lds	r26, pxCurrentTCB		; Finally save the software stack pointer (Y ...
-	lds	r27, pxCurrentTCB + 1	; ... register) into the TCB.
-	st	x+, r28
-	st	x+, r29
-
-	ENDM
-
-
-portRESTORE_CONTEXT MACRO
-	lds	r26, pxCurrentTCB
-	lds	r27, pxCurrentTCB + 1	; Restore the software stack pointer from ...
-	ld	r28, x+					; the TCB into the software stack pointer (...
-	ld	r29, x+					; ... the Y register).
-
-	ld	r0, y+
-	sts	uxCriticalNesting, r0
-	ld	r31, y+					; Restore the registers down to R0.  The Y
-	ld	r30, y+					; register is missing from this list as it
-	ld	r27, y+					; has already been restored.
-	ld	r26, y+
-	ld	r25, y+
-	ld	r24, y+
-	ld	r23, y+
-	ld	r22, y+
-	ld	r21, y+
-	ld	r20, y+
-	ld	r19, y+
-	ld	r18, y+
-	ld	r17, y+
-	ld	r16, y+
-	ld	r15, y+
-	ld	r14, y+
-	ld	r13, y+
-	ld	r12, y+
-	ld	r11, y+
-	ld	r10, y+
-	ld	r9, y+
-	ld	r8, y+
-	ld	r7, y+
-	ld	r6, y+
-	ld	r5, y+
-	ld	r4, y+
-	ld	r3, y+
-	ld	r2, y+
-	ld	r1, y+
-
-	ld	r0, y+					; The next thing on the stack is the ...
-	out	SPH, r0					; ... hardware stack pointer.
-	ld	r0, y+
-	out	SPL, r0
-
-	ld	r0, y+					; Next there is the SREG register.
-	out SREG, r0
-
-	ld	r0, y+					; Finally we have finished with r0, so restore r0.
-
-	ENDM
-
-
-
-; vPortYield() and vPortYieldFromTick()
-; -------------------------------------
-;
-; Manual and preemptive context switch functions respectively.
-; The IAR compiler does not fully support inline assembler,
-; so these are implemented here rather than the more usually
-; place of within port.c.
-
-vPortYield:
-	portSAVE_CONTEXT			; Save the context of the current task.
-	call vTaskSwitchContext		; Call the scheduler.
-	portRESTORE_CONTEXT			; Restore the context of whichever task the ...
-	ret							; ... scheduler decided should run.
-
-vPortYieldFromTick:
-	portSAVE_CONTEXT			; Save the context of the current task.
-	call xTaskIncrementTick		; Call the timer tick function.
-	tst r16
-	breq SkipTaskSwitch
-	call vTaskSwitchContext		; Call the scheduler.
-SkipTaskSwitch:
-	portRESTORE_CONTEXT			; Restore the context of whichever task the ...
-	ret							; ... scheduler decided should run.
-
-; vPortStart()
-; ------------
-;
-; Again due to the lack of inline assembler, this is required
-; to get access to the portRESTORE_CONTEXT macro.
-
-vPortStart:
-	portRESTORE_CONTEXT
-	ret
-
-
-; Just a filler for unused interrupt vectors.
-vNoISR:
-	reti
-
-
-	END
-
diff --git a/FreeRTOS/Source/portable/IAR/AVR32_UC3/exception.s82 b/FreeRTOS/Source/portable/IAR/AVR32_UC3/exception.s82
deleted file mode 100755
index 7bb4e5c..0000000
--- a/FreeRTOS/Source/portable/IAR/AVR32_UC3/exception.s82
+++ /dev/null
@@ -1,310 +0,0 @@
-/*This file is prepared for Doxygen automatic documentation generation.*/
-/*! \file *********************************************************************
- *
- * \brief Exception and interrupt vectors.
- *
- * This file maps all events supported by an AVR32UC.
- *
- * - Compiler:           IAR EWAVR32
- * - Supported devices:  All AVR32UC devices with an INTC module can be used.
- * - AppNote:
- *
- * \author               Atmel Corporation: http://www.atmel.com \n
- *                       Support and FAQ: http://support.atmel.no/
- *
- ******************************************************************************/
-
-/* Copyright (c) 2007, Atmel Corporation All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of ATMEL may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
- * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include 
-#include "intc.h"
-
-
-//! @{
-//! \verbatim
-
-
-// Start of Exception Vector Table.
-
-  // EVBA must be aligned with a power of two strictly greater than the EVBA-
-  // relative offset of the last vector.
-  COMMON  EVTAB:CODE:ROOT(9)
-
-
-  // Force EVBA initialization.
-  EXTERN  ??init_EVBA
-  REQUIRE ??init_EVBA
-
-  // Export symbol.
-  PUBLIC  ??EVBA
-  PUBLIC  _evba
-??EVBA:
-_evba:
-
-        ORG 0x000
-        // Unrecoverable Exception.
-_handle_Unrecoverable_Exception:
-        rjmp $
-
-        ORG 0x004
-        // TLB Multiple Hit: UNUSED IN AVR32UC.
-_handle_TLB_Multiple_Hit:
-        rjmp $
-
-        ORG 0x008
-        // Bus Error Data Fetch.
-_handle_Bus_Error_Data_Fetch:
-        rjmp $
-
-        ORG 0x00C
-         // Bus Error Instruction Fetch.
-_handle_Bus_Error_Instruction_Fetch:
-        rjmp $
-
-        ORG 0x010
-        // NMI.
-_handle_NMI:
-        rjmp $
-
-        ORG 0x014
-        // Instruction Address.
-_handle_Instruction_Address:
-        rjmp $
-
-        ORG 0x018
-        // ITLB Protection.
-_handle_ITLB_Protection:
-        rjmp $
-
-        ORG 0x01C
-        // Breakpoint.
-_handle_Breakpoint:
-        rjmp $
-
-        ORG 0x020
-        // Illegal Opcode.
-_handle_Illegal_Opcode:
-        rjmp $
-
-        ORG 0x024
-        // Unimplemented Instruction.
-_handle_Unimplemented_Instruction:
-        rjmp $
-
-        ORG 0x028
-        // Privilege Violation.
-_handle_Privilege_Violation:
-        rjmp $
-
-        ORG 0x02C
-        // Floating-Point: UNUSED IN AVR32UC.
-_handle_Floating_Point:
-        rjmp $
-
-        ORG 0x030
-        // Coprocessor Absent: UNUSED IN AVR32UC.
-_handle_Coprocessor_Absent:
-        rjmp $
-
-        ORG 0x034
-        // Data Address (Read).
-_handle_Data_Address_Read:
-        rjmp $
-
-        ORG 0x038
-        // Data Address (Write).
-_handle_Data_Address_Write:
-        rjmp $
-
-        ORG 0x03C
-        // DTLB Protection (Read).
-_handle_DTLB_Protection_Read:
-        rjmp $
-
-        ORG 0x040
-        // DTLB Protection (Write).
-_handle_DTLB_Protection_Write:
-        rjmp $
-
-        ORG 0x044
-        // DTLB Modified: UNUSED IN AVR32UC.
-_handle_DTLB_Modified:
-        rjmp $
-
-        ORG 0x050
-        // ITLB Miss: UNUSED IN AVR32UC.
-_handle_ITLB_Miss:
-        rjmp $
-
-        ORG 0x060
-        // DTLB Miss (Read): UNUSED IN AVR32UC.
-_handle_DTLB_Miss_Read:
-        rjmp $
-
-        ORG 0x070
-        // DTLB Miss (Write): UNUSED IN AVR32UC.
-_handle_DTLB_Miss_Write:
-        rjmp $
-
-        ORG 0x100
-        // Supervisor Call.
-_handle_Supervisor_Call:
-        lddpc   pc, __SCALLYield
-
-
-// Interrupt support.
-// The interrupt controller must provide the offset address relative to EVBA.
-// Important note:
-//   All interrupts call a C function named _get_interrupt_handler.
-//   This function will read group and interrupt line number to then return in
-//   R12 a pointer to a user-provided interrupt handler.
-
-  ALIGN 2
-
-_int0:
-  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
-  // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
-  mfsr    r12, AVR32_SR
-  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
-  cp.w    r12, 110b
-  brlo    _int0_normal
-  lddsp   r12, sp[0 * 4]
-  stdsp   sp[6 * 4], r12
-  lddsp   r12, sp[1 * 4]
-  stdsp   sp[7 * 4], r12
-  lddsp   r12, sp[3 * 4]
-  sub     sp, -6 * 4
-  rete
-_int0_normal:
-#endif
-  mov     r12, 0  // Pass the int_lev parameter to the _get_interrupt_handler function.
-  mcall   __get_interrupt_handler
-  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
-  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
-  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-_int1:
-  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
-  // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
-  mfsr    r12, AVR32_SR
-  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
-  cp.w    r12, 110b
-  brlo    _int1_normal
-  lddsp   r12, sp[0 * 4]
-  stdsp   sp[6 * 4], r12
-  lddsp   r12, sp[1 * 4]
-  stdsp   sp[7 * 4], r12
-  lddsp   r12, sp[3 * 4]
-  sub     sp, -6 * 4
-  rete
-_int1_normal:
-#endif
-  mov     r12, 1  // Pass the int_lev parameter to the _get_interrupt_handler function.
-  mcall   __get_interrupt_handler
-  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
-  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
-  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-_int2:
-  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
-  // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
-  mfsr    r12, AVR32_SR
-  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
-  cp.w    r12, 110b
-  brlo    _int2_normal
-  lddsp   r12, sp[0 * 4]
-  stdsp   sp[6 * 4], r12
-  lddsp   r12, sp[1 * 4]
-  stdsp   sp[7 * 4], r12
-  lddsp   r12, sp[3 * 4]
-  sub     sp, -6 * 4
-  rete
-_int2_normal:
-#endif
-  mov     r12, 2  // Pass the int_lev parameter to the _get_interrupt_handler function.
-  mcall   __get_interrupt_handler
-  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
-  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
-  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-_int3:
-  // R8-R12, LR, PC and SR are automatically pushed onto the system stack by the
-  // CPU upon interrupt entry.
-#if 1 // B1832: interrupt stack changed to exception stack if exception is detected.
-  mfsr    r12, AVR32_SR
-  bfextu  r12, r12, AVR32_SR_M0_OFFSET, AVR32_SR_M0_SIZE + AVR32_SR_M1_SIZE + AVR32_SR_M2_SIZE
-  cp.w    r12, 110b
-  brlo    _int3_normal
-  lddsp   r12, sp[0 * 4]
-  stdsp   sp[6 * 4], r12
-  lddsp   r12, sp[1 * 4]
-  stdsp   sp[7 * 4], r12
-  lddsp   r12, sp[3 * 4]
-  sub     sp, -6 * 4
-  rete
-_int3_normal:
-#endif
-  mov     r12, 3  // Pass the int_lev parameter to the _get_interrupt_handler function.
-  mcall   __get_interrupt_handler
-  cp.w    r12, 0  // Get the pointer to the interrupt handler returned by the function.
-  movne   pc, r12 // If this was not a spurious interrupt (R12 != NULL), jump to the handler.
-  rete            // If this was a spurious interrupt (R12 == NULL), return from event handler.
-
-
-// Constant data area.
-
-  ALIGN 2
-
-  // Import symbols.
-  EXTERN  SCALLYield
-  EXTERN  _get_interrupt_handler
-__SCALLYield:
-  DC32  SCALLYield
-__get_interrupt_handler:
-  DC32  _get_interrupt_handler
-
-  // Values to store in the interrupt priority registers for the various interrupt priority levels.
-  // The interrupt priority registers contain the interrupt priority level and
-  // the EVBA-relative interrupt vector offset.
-  PUBLIC  ipr_val
-ipr_val:
-  DC32  (INT0 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int0 - _evba),\
-        (INT1 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int1 - _evba),\
-        (INT2 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int2 - _evba),\
-        (INT3 << AVR32_INTC_IPR0_INTLEV_OFFSET) | (_int3 - _evba)
-
-
-  END
-
-
-//! \endverbatim
-//! @}
diff --git a/FreeRTOS/Source/portable/IAR/AVR32_UC3/port.c b/FreeRTOS/Source/portable/IAR/AVR32_UC3/port.c
deleted file mode 100755
index 983e08f..0000000
--- a/FreeRTOS/Source/portable/IAR/AVR32_UC3/port.c
+++ /dev/null
@@ -1,406 +0,0 @@
-/*This file has been prepared for Doxygen automatic documentation generation.*/
-/*! \file *********************************************************************
- *
- * \brief FreeRTOS port source for AVR32 UC3.
- *
- * - Compiler:           IAR EWAVR32
- * - Supported devices:  All AVR32 devices can be used.
- * - AppNote:
- *
- * \author               Atmel Corporation: http://www.atmel.com \n
- *                       Support and FAQ: http://support.atmel.no/
- *
- *****************************************************************************/
-
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* AVR32 UC3 includes. */
-#include 
-#include 
-#include "gpio.h"
-
-#if configDBG
-	#include "usart.h"
-#endif
-
-#if( configTICK_USE_TC==1 )
-	#include "tc.h"
-#endif
-
-
-/* Constants required to setup the task context. */
-#define portINITIAL_SR            ( ( StackType_t ) 0x00400000 ) /* AVR32 : [M2:M0]=001 I1M=0 I0M=0, GM=0 */
-#define portINSTRUCTION_SIZE      ( ( StackType_t ) 0 )
-
-/* Each task maintains its own critical nesting variable. */
-#define portNO_CRITICAL_NESTING   ( ( uint32_t ) 0 )
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-#if( configTICK_USE_TC==0 )
-	static void prvScheduleNextTick( void );
-#else
-	static void prvClearTcInt( void );
-#endif
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Low-level initialization routine called during startup, before the main
- * function.
- */
-int __low_level_init(void)
-{
-	#if configHEAP_INIT
-		#pragma segment = "HEAP"
-		BaseType_t *pxMem;
-	#endif
-
-	/* Enable exceptions. */
-	ENABLE_ALL_EXCEPTIONS();
-
-	/* Initialize interrupt handling. */
-	INTC_init_interrupts();
-
-	#if configHEAP_INIT
-	{
-		/* Initialize the heap used by malloc. */
-		for( pxMem = __segment_begin( "HEAP" ); pxMem < ( BaseType_t * ) __segment_end( "HEAP" ); )
-		{
-			*pxMem++ = 0xA5A5A5A5;
-		}
-	}
-	#endif
-
-	/* Code section present if and only if the debug trace is activated. */
-	#if configDBG
-	{
-		static const gpio_map_t DBG_USART_GPIO_MAP =
-		{
-			{ configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
-			{ configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
-		};
-
-		static const usart_options_t DBG_USART_OPTIONS =
-		{
-			.baudrate = configDBG_USART_BAUDRATE,
-			.charlength = 8,
-			.paritytype = USART_NO_PARITY,
-			.stopbits = USART_1_STOPBIT,
-			.channelmode = USART_NORMAL_CHMODE
-		};
-
-		/* Initialize the USART used for the debug trace with the configured parameters. */
-		extern volatile avr32_usart_t *volatile stdio_usart_base;
-		stdio_usart_base = configDBG_USART;
-		gpio_enable_module( DBG_USART_GPIO_MAP,
-		                    sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
-		usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);
-	}
-	#endif
-
-	/* Request initialization of data segments. */
-	return 1;
-}
-/*-----------------------------------------------------------*/
-
-/* Added as there is no such function in FreeRTOS. */
-void *pvPortRealloc( void *pv, size_t xWantedSize )
-{
-void *pvReturn;
-
-	vTaskSuspendAll();
-	{
-		pvReturn = realloc( pv, xWantedSize );
-	}
-	xTaskResumeAll();
-
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-/* The cooperative scheduler requires a normal IRQ service routine to
-simply increment the system tick. */
-/* The preemptive scheduler is defined as "naked" as the full context is saved
-on entry as part of the context switch. */
-#pragma shadow_registers = full   // Naked.
-static void vTick( void )
-{
-	/* Save the context of the interrupted task. */
-	portSAVE_CONTEXT_OS_INT();
-
-	#if( configTICK_USE_TC==1 )
-		/* Clear the interrupt flag. */
-		prvClearTcInt();
-	#else
-		/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
-		clock cycles from now. */
-		prvScheduleNextTick();
-	#endif
-
-	/* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
-	calls in a critical section . */
-	portENTER_CRITICAL();
-		xTaskIncrementTick();
-	portEXIT_CRITICAL();
-
-	/* Restore the context of the "elected task". */
-	portRESTORE_CONTEXT_OS_INT();
-}
-/*-----------------------------------------------------------*/
-
-#pragma shadow_registers = full   // Naked.
-void SCALLYield( void )
-{
-	/* Save the context of the interrupted task. */
-	portSAVE_CONTEXT_SCALL();
-	vTaskSwitchContext();
-	portRESTORE_CONTEXT_SCALL();
-}
-/*-----------------------------------------------------------*/
-
-/* The code generated by the GCC compiler uses the stack in different ways at
-different optimisation levels.  The interrupt flags can therefore not always
-be saved to the stack.  Instead the critical section nesting level is stored
-in a variable, which is then saved as part of the stack context. */
-#pragma optimize = no_inline
-void vPortEnterCritical( void )
-{
-	/* Disable interrupts */
-	portDISABLE_INTERRUPTS();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	 directly.  Increment ulCriticalNesting to keep a count of how many times
-	 portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-#pragma optimize = no_inline
-void vPortExitCritical( void )
-{
-	if(ulCriticalNesting > portNO_CRITICAL_NESTING)
-	{
-		ulCriticalNesting--;
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Enable all interrupt/exception. */
-			portENABLE_INTERRUPTS();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* When the task starts, it will expect to find the function parameter in R12. */
-	pxTopOfStack--;
-	*pxTopOfStack-- = ( StackType_t ) 0x08080808;					/* R8 */
-	*pxTopOfStack-- = ( StackType_t ) 0x09090909;					/* R9 */
-	*pxTopOfStack-- = ( StackType_t ) 0x0A0A0A0A;					/* R10 */
-	*pxTopOfStack-- = ( StackType_t ) 0x0B0B0B0B;					/* R11 */
-	*pxTopOfStack-- = ( StackType_t ) pvParameters;					/* R12 */
-	*pxTopOfStack-- = ( StackType_t ) 0xDEADBEEF;					/* R14/LR */
-	*pxTopOfStack-- = ( StackType_t ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
-	*pxTopOfStack-- = ( StackType_t ) portINITIAL_SR;				/* SR */
-	*pxTopOfStack-- = ( StackType_t ) 0xFF0000FF;					/* R0 */
-	*pxTopOfStack-- = ( StackType_t ) 0x01010101;					/* R1 */
-	*pxTopOfStack-- = ( StackType_t ) 0x02020202;					/* R2 */
-	*pxTopOfStack-- = ( StackType_t ) 0x03030303;					/* R3 */
-	*pxTopOfStack-- = ( StackType_t ) 0x04040404;					/* R4 */
-	*pxTopOfStack-- = ( StackType_t ) 0x05050505;					/* R5 */
-	*pxTopOfStack-- = ( StackType_t ) 0x06060606;					/* R6 */
-	*pxTopOfStack-- = ( StackType_t ) 0x07070707;					/* R7 */
-	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_NESTING;			/* ulCriticalNesting */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task. */
-	portRESTORE_CONTEXT();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the AVR32 port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-/* Schedule the COUNT&COMPARE match interrupt in (configCPU_CLOCK_HZ/configTICK_RATE_HZ)
-clock cycles from now. */
-#if( configTICK_USE_TC==0 )
-	static void prvScheduleFirstTick(void)
-	{
-		uint32_t lCycles;
-
-		lCycles = Get_system_register(AVR32_COUNT);
-		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
-		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
-		// generation feature does not get disabled.
-		if(0 == lCycles)
-		{
-			lCycles++;
-		}
-		Set_system_register(AVR32_COMPARE, lCycles);
-	}
-	
-	#pragma optimize = no_inline
-	static void prvScheduleNextTick(void)
-	{
-		uint32_t lCycles, lCount;
-
-		lCycles = Get_system_register(AVR32_COMPARE);
-		lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
-		// If lCycles ends up to be 0, make it 1 so that the COMPARE and exception
-		// generation feature does not get disabled.
-		if(0 == lCycles)
-		{
-			lCycles++;
-		}
-		lCount = Get_system_register(AVR32_COUNT);
-		if( lCycles < lCount )
-		{		// We missed a tick, recover for the next.
-			lCycles += (configCPU_CLOCK_HZ/configTICK_RATE_HZ);
-		}
-		Set_system_register(AVR32_COMPARE, lCycles);
-	}
-#else
-	#pragma optimize = no_inline
-	static void prvClearTcInt(void)
-	{
-		AVR32_TC.channel[configTICK_TC_CHANNEL].sr;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt(void)
-{
-	#if( configTICK_USE_TC==1 )
-
-		volatile avr32_tc_t *tc = &AVR32_TC;
-
-		// Options for waveform genration.
-		tc_waveform_opt_t waveform_opt =
-		{
-		.channel  = configTICK_TC_CHANNEL,             /* Channel selection. */
-
-		.bswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOB. */
-		.beevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOB. */
-		.bcpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOB. */
-		.bcpb     = TC_EVT_EFFECT_NOOP,                /* RB compare effect on TIOB. */
-
-		.aswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOA. */
-		.aeevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOA. */
-		.acpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOA: toggle. */
-		.acpa     = TC_EVT_EFFECT_NOOP,                /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
-
-		.wavsel   = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
-		.enetrg   = FALSE,                             /* External event trigger enable. */
-		.eevt     = 0,                                 /* External event selection. */
-		.eevtedg  = TC_SEL_NO_EDGE,                    /* External event edge selection. */
-		.cpcdis   = FALSE,                             /* Counter disable when RC compare. */
-		.cpcstop  = FALSE,                             /* Counter clock stopped with RC compare. */
-
-		.burst    = FALSE,                             /* Burst signal selection. */
-		.clki     = FALSE,                             /* Clock inversion. */
-		.tcclks   = TC_CLOCK_SOURCE_TC2                /* Internal source clock 2. */
-		};
-
-		tc_interrupt_t tc_interrupt =
-		{
-			.etrgs=0,
-			.ldrbs=0,
-			.ldras=0,
-			.cpcs =1,
-			.cpbs =0,
-			.cpas =0,
-			.lovrs=0,
-			.covfs=0,
-		};
-
-	#endif
-
-	/* Disable all interrupt/exception. */
-	portDISABLE_INTERRUPTS();
-
-	/* Register the compare interrupt handler to the interrupt controller and
-	enable the compare interrupt. */
-
-	#if( configTICK_USE_TC==1 )
-	{
-		INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, INT0);
-
-		/* Initialize the timer/counter. */
-		tc_init_waveform(tc, &waveform_opt);
-
-		/* Set the compare triggers.
-		Remember TC counter is 16-bits, so counting second is not possible!
-		That's why we configure it to count ms. */
-		tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ / 4) / configTICK_RATE_HZ );
-
-		tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
-
-		/* Start the timer/counter. */
-		tc_start(tc, configTICK_TC_CHANNEL);
-	}
-	#else
-	{
-		INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, INT0);
-		prvScheduleFirstTick();
-	}
-	#endif
-}
diff --git a/FreeRTOS/Source/portable/IAR/AVR32_UC3/portmacro.h b/FreeRTOS/Source/portable/IAR/AVR32_UC3/portmacro.h
deleted file mode 100755
index e130404..0000000
--- a/FreeRTOS/Source/portable/IAR/AVR32_UC3/portmacro.h
+++ /dev/null
@@ -1,654 +0,0 @@
-/*This file has been prepared for Doxygen automatic documentation generation.*/
-/*! \file *********************************************************************
- *
- * \brief FreeRTOS port header for AVR32 UC3.
- *
- * - Compiler:           IAR EWAVR32
- * - Supported devices:  All AVR32 devices can be used.
- * - AppNote:
- *
- * \author               Atmel Corporation: http://www.atmel.com \n
- *                       Support and FAQ: http://support.atmel.no/
- *
- *****************************************************************************/
-
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-#include 
-#include "intc.h"
-#include "compiler.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#define TASK_DELAY_MS(x)   ( (x)        /portTICK_PERIOD_MS )
-#define TASK_DELAY_S(x)    ( (x)*1000   /portTICK_PERIOD_MS )
-#define TASK_DELAY_MIN(x)  ( (x)*60*1000/portTICK_PERIOD_MS )
-
-#define configTICK_TC_IRQ             ATPASTE2(AVR32_TC_IRQ, configTICK_TC_CHANNEL)
-
-#if( configUSE_16_BIT_TICKS == 1 )
-  typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-  typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH      ( -1 )
-#define portTICK_PERIOD_MS      ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT       4
-#define portNOP()             {__asm__ __volatile__ ("nop");}
-/*-----------------------------------------------------------*/
-
-
-/*-----------------------------------------------------------*/
-
-/* INTC-specific. */
-#define DISABLE_ALL_EXCEPTIONS()    Disable_global_exception()
-#define ENABLE_ALL_EXCEPTIONS()     Enable_global_exception()
-
-#define DISABLE_ALL_INTERRUPTS()    Disable_global_interrupt()
-#define ENABLE_ALL_INTERRUPTS()     Enable_global_interrupt()
-
-#define DISABLE_INT_LEVEL(int_lev)  Disable_interrupt_level(int_lev)
-#define ENABLE_INT_LEVEL(int_lev)   Enable_interrupt_level(int_lev)
-
-
-/*
- * Debug trace.
- * Activated if and only if configDBG is nonzero.
- * Prints a formatted string to stdout.
- * The current source file name and line number are output with a colon before
- * the formatted string.
- * A carriage return and a linefeed are appended to the output.
- * stdout is redirected to the USART configured by configDBG_USART.
- * The parameters are the same as for the standard printf function.
- * There is no return value.
- * SHALL NOT BE CALLED FROM WITHIN AN INTERRUPT as fputs and printf use malloc,
- * which is interrupt-unsafe with the current __malloc_lock and __malloc_unlock.
- */
-#if configDBG
-	#define portDBG_TRACE(...)												\
-	{																		\
-	  fputs(__FILE__ ":" ASTRINGZ(__LINE__) ": ", stdout);					\
-	  printf(__VA_ARGS__);													\
-	  fputs("\r\n", stdout);												\
-	}
-#else
-	#define portDBG_TRACE(...)
-#endif
-
-
-/* Critical section management. */
-#define portDISABLE_INTERRUPTS()  DISABLE_ALL_INTERRUPTS()
-#define portENABLE_INTERRUPTS()   ENABLE_ALL_INTERRUPTS()
-
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL()      vPortEnterCritical();
-#define portEXIT_CRITICAL()       vPortExitCritical();
-
-
-/* Added as there is no such function in FreeRTOS. */
-extern void *pvPortRealloc( void *pv, size_t xSize );
-/*-----------------------------------------------------------*/
-
-
-/*=============================================================================================*/
-
-/*
- * Restore Context for cases other than INTi.
- */
-#define portRESTORE_CONTEXT()																\
-{																							\
-  extern volatile uint32_t ulCriticalNesting;										\
-  extern volatile void *volatile pxCurrentTCB;												\
-																							\
-  __asm__ __volatile__ (																	\
-    /* Set SP to point to new stack */														\
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")												\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")												\n\t"\
-    "ld.w    r0, r8[0]																		\n\t"\
-    "ld.w    sp, r0[0]																		\n\t"\
-																							\
-    /* Restore ulCriticalNesting variable */												\
-    "ld.w    r0, sp++																		\n\t"\
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")										\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")										\n\t"\
-    "st.w    r8[0], r0																		\n\t"\
-																							\
-    /* Restore R0..R7 */																	\
-    "ldm     sp++, r0-r7																	\n\t"\
-    /* R0-R7 should not be used below this line */											\
-    /* Skip PC and SR (will do it at the end) */											\
-    "sub     sp, -2*4																		\n\t"\
-    /* Restore R8..R12 and LR */															\
-    "ldm     sp++, r8-r12, lr																\n\t"\
-    /* Restore SR */																		\
-    "ld.w    r0, sp[-8*4]																	\n\t" /* R0 is modified, is restored later. */\
-    "mtsr    "ASTRINGZ(AVR32_SR)", r0														\n\t"\
-    /* Restore r0 */																		\
-    "ld.w    r0, sp[-9*4]																	\n\t"\
-    /* Restore PC */																		\
-    "ld.w    pc, sp[-7*4]" /* Get PC from stack - PC is the 7th register saved */			\
-  );																						\
-																							\
-  /* Force import of global symbols from assembly */										\
-  ulCriticalNesting;																		\
-  pxCurrentTCB;																				\
-}
-
-
-/*
- * portSAVE_CONTEXT_INT() and portRESTORE_CONTEXT_INT(): for INT0..3 exceptions.
- * portSAVE_CONTEXT_SCALL() and portRESTORE_CONTEXT_SCALL(): for the scall exception.
- *
- * Had to make different versions because registers saved on the system stack
- * are not the same between INT0..3 exceptions and the scall exception.
- */
-
-// Task context stack layout:
-  // R8  (*)
-  // R9  (*)
-  // R10 (*)
-  // R11 (*)
-  // R12 (*)
-  // R14/LR (*)
-  // R15/PC (*)
-  // SR (*)
-  // R0
-  // R1
-  // R2
-  // R3
-  // R4
-  // R5
-  // R6
-  // R7
-  // ulCriticalNesting
-// (*) automatically done for INT0..INT3, but not for SCALL
-
-/*
- * The ISR used for the scheduler tick depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-#if configUSE_PREEMPTION == 0
-
-/*
- * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
- */
-#define portSAVE_CONTEXT_OS_INT()															\
-{																							\
-  /* Save R0..R7 */																			\
-  __asm__ __volatile__ ("stm     --sp, r0-r7");												\
-																							\
-  /* With the cooperative scheduler, as there is no context switch by interrupt, */			\
-  /* there is also no context save. */														\
-}
-
-/*
- * portRESTORE_CONTEXT_OS_INT() for Tick exception.
- */
-#define portRESTORE_CONTEXT_OS_INT()														\
-{																							\
-  __asm__ __volatile__ (																	\
-    /* Restore R0..R7 */																	\
-    "ldm     sp++, r0-r7																	\n\t"\
-																							\
-    /* With the cooperative scheduler, as there is no context switch by interrupt, */		\
-    /* there is also no context restore. */													\
-    "rete"																					\
-  );																						\
-}
-
-#else
-
-/*
- * portSAVE_CONTEXT_OS_INT() for OS Tick exception.
- */
-#define portSAVE_CONTEXT_OS_INT()																	\
-{																									\
-  extern volatile uint32_t ulCriticalNesting;												\
-  extern volatile void *volatile pxCurrentTCB;														\
-																									\
-  /* When we come here */																			\
-  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */					\
-																									\
-  __asm__ __volatile__ (																			\
-    /* Save R0..R7 */																				\
-    "stm     --sp, r0-r7																			\n\t"\
-																									\
-    /* Save ulCriticalNesting variable  - R0 is overwritten */										\
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
-    "ld.w    r0, r8[0]																				\n\t"\
-    "st.w    --sp, r0																				\n\t"\
-																									\
-    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
-    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
-    /* level and allow other lower interrupt level to occur). */									\
-    /* In this case we don't want to do a task switch because we don't know what the stack */		\
-    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
-    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
-    /* will just be restoring the interrupt handler, no way!!! */									\
-    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
-    "ld.w    r0, sp[9*4]																			\n\t" /* Read SR in stack */\
-    "bfextu  r0, r0, 22, 3																			\n\t" /* Extract the mode bits to R0. */\
-    "cp.w    r0, 1																					\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
-    "brhi    LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)"										\n\t"\
-																									\
-    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */					\
-    /* NOTE: we don't enter a critical section here because all interrupt handlers */				\
-    /* MUST perform a SAVE_CONTEXT/RESTORE_CONTEXT in the same way as */							\
-    /* portSAVE_CONTEXT_OS_INT/port_RESTORE_CONTEXT_OS_INT if they call OS functions. */			\
-    /* => all interrupt handlers must use portENTER_SWITCHING_ISR/portEXIT_SWITCHING_ISR. */		\
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
-    "ld.w    r0, r8[0]																				\n\t"\
-    "st.w    r0[0], sp																				\n"\
-																									\
-    "LABEL_INT_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":"												\
-  );																								\
-}
-
-/*
- * portRESTORE_CONTEXT_OS_INT() for Tick exception.
- */
-#define portRESTORE_CONTEXT_OS_INT()																\
-{																									\
-  extern volatile uint32_t ulCriticalNesting;												\
-  extern volatile void *volatile pxCurrentTCB;														\
-																									\
-  /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */		\
-  /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
-  /* level and allow other lower interrupt level to occur). */										\
-  /* In this case we don't want to do a task switch because we don't know what the stack */			\
-  /* currently looks like (we don't know what the interrupted interrupt handler was doing). */		\
-  /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */			\
-  /* will just be restoring the interrupt handler, no way!!! */										\
-  __asm__ __volatile__ (																			\
-    "ld.w    r0, sp[9*4]																			\n\t" /* Read SR in stack */\
-    "bfextu  r0, r0, 22, 3																			\n\t" /* Extract the mode bits to R0. */\
-    "cp.w    r0, 1																					\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
-    "brhi    LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)										\
-  );																								\
-																									\
-  /* Else */																						\
-  /* because it is here safe, always call vTaskSwitchContext() since an OS tick occurred. */		\
-  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
-  portENTER_CRITICAL();																				\
-  vTaskSwitchContext();																				\
-  portEXIT_CRITICAL();																				\
-																									\
-  /* Restore all registers */																		\
-																									\
-  __asm__ __volatile__ (																			\
-    /* Set SP to point to new stack */																\
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
-    "ld.w    r0, r8[0]																				\n\t"\
-    "ld.w    sp, r0[0]																				\n"\
-																									\
-    "LABEL_INT_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":											\n\t"\
-																									\
-    /* Restore ulCriticalNesting variable */														\
-    "ld.w    r0, sp++																				\n\t"\
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
-    "st.w    r8[0], r0																				\n\t"\
-																									\
-    /* Restore R0..R7 */																			\
-    "ldm     sp++, r0-r7																			\n\t"\
-																									\
-    /* Now, the stack should be R8..R12, LR, PC and SR */											\
-    "rete"																							\
-  );																								\
-																									\
-  /* Force import of global symbols from assembly */												\
-  ulCriticalNesting;																				\
-  pxCurrentTCB;																						\
-}
-
-#endif
-
-
-/*
- * portSAVE_CONTEXT_SCALL() for SupervisorCALL exception.
- *
- * NOTE: taskYIELD()(== SCALL) MUST NOT be called in a mode > supervisor mode.
- *
- */
-#define portSAVE_CONTEXT_SCALL()																	\
-{																									\
-  extern volatile uint32_t ulCriticalNesting;												\
-  extern volatile void *volatile pxCurrentTCB;														\
-																									\
-  /* Warning: the stack layout after SCALL doesn't match the one after an interrupt. */				\
-  /* If SR[M2:M0] == 001 */																			\
-  /*    PC and SR are on the stack.  */																\
-  /* Else (other modes) */																			\
-  /*    Nothing on the stack. */																	\
-																									\
-  /* WARNING NOTE: the else case cannot happen as it is strictly forbidden to call */				\
-  /* vTaskDelay() and vTaskDelayUntil() OS functions (that result in a taskYield()) */				\
-  /* in an interrupt|exception handler. */															\
-																									\
-  __asm__ __volatile__ (																			\
-    /* in order to save R0-R7 */																	\
-    "sub     sp, 6*4																				\n\t"\
-    /* Save R0..R7 */																				\
-    "stm     --sp, r0-r7																			\n\t"\
-																									\
-    /* in order to save R8-R12 and LR */															\
-    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */					\
-    "sub     r7, sp,-16*4																			\n\t"\
-    /* Copy PC and SR in other places in the stack. */												\
-    "ld.w    r0, r7[-2*4]																			\n\t" /* Read SR */\
-    "st.w    r7[-8*4], r0																			\n\t" /* Copy SR */\
-    "ld.w    r0, r7[-1*4]																			\n\t" /* Read PC */\
-    "st.w    r7[-7*4], r0																			\n\t" /* Copy PC */\
-																									\
-    /* Save R8..R12 and LR on the stack. */															\
-    "stm     --r7, r8-r12, lr																		\n\t"\
-																									\
-    /* Arriving here we have the following stack organizations: */									\
-    /* R8..R12, LR, PC, SR, R0..R7. */																\
-																									\
-    /* Now we can finalize the save. */																\
-																									\
-    /* Save ulCriticalNesting variable  - R0 is overwritten */										\
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
-    "ld.w    r0, r8[0]																				\n\t"\
-    "st.w    --sp, r0"																				\
-  );																								\
-																									\
-  /* Disable the its which may cause a context switch (i.e. cause a change of */					\
-  /* pxCurrentTCB). */																				\
-  /* Basically, all accesses to the pxCurrentTCB structure should be put in a */					\
-  /* critical section because it is a global structure. */											\
-  portENTER_CRITICAL();																				\
-																									\
-  /* Store SP in the first member of the structure pointed to by pxCurrentTCB */					\
-  __asm__ __volatile__ (																			\
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
-    "ld.w    r0, r8[0]																				\n\t"\
-    "st.w    r0[0], sp"																				\
-  );																								\
-}
-
-/*
- * portRESTORE_CONTEXT() for SupervisorCALL exception.
- */
-#define portRESTORE_CONTEXT_SCALL()																	\
-{																									\
-  extern volatile uint32_t ulCriticalNesting;												\
-  extern volatile void *volatile pxCurrentTCB;														\
-																									\
-  /* Restore all registers */																		\
-																									\
-  /* Set SP to point to new stack */																\
-  __asm__ __volatile__ (																			\
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
-    "ld.w    r0, r8[0]																				\n\t"\
-    "ld.w    sp, r0[0]"																				\
-  );																								\
-																									\
-  /* Leave pxCurrentTCB variable access critical section */											\
-  portEXIT_CRITICAL();																				\
-																									\
-  __asm__ __volatile__ (																			\
-    /* Restore ulCriticalNesting variable */														\
-    "ld.w    r0, sp++																				\n\t"\
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
-    "st.w    r8[0], r0																				\n\t"\
-																									\
-    /* skip PC and SR */																			\
-    /* do not use SP if interrupts occurs, SP must be left at bottom of stack */					\
-    "sub     r7, sp, -10*4																			\n\t"\
-    /* Restore r8-r12 and LR */																		\
-    "ldm     r7++, r8-r12, lr																		\n\t"\
-																									\
-    /* RETS will take care of the extra PC and SR restore. */										\
-    /* So, we have to prepare the stack for this. */												\
-    "ld.w    r0, r7[-8*4]																			\n\t" /* Read SR */\
-    "st.w    r7[-2*4], r0																			\n\t" /* Copy SR */\
-    "ld.w    r0, r7[-7*4]																			\n\t" /* Read PC */\
-    "st.w    r7[-1*4], r0																			\n\t" /* Copy PC */\
-																									\
-    /* Restore R0..R7 */																			\
-    "ldm     sp++, r0-r7																			\n\t"\
-																									\
-    "sub     sp, -6*4																				\n\t"\
-																									\
-    "rets"																							\
-  );																								\
-																									\
-  /* Force import of global symbols from assembly */												\
-  ulCriticalNesting;																				\
-  pxCurrentTCB;																						\
-}
-
-
-/*
- * The ISR used depends on whether the cooperative or
- * the preemptive scheduler is being used.
- */
-#if configUSE_PREEMPTION == 0
-
-/*
- * ISR entry and exit macros.  These are only required if a task switch
- * is required from the ISR.
- */
-#define portENTER_SWITCHING_ISR()																	\
-{																									\
-  /* Save R0..R7 */																					\
-  __asm__ __volatile__ ("stm     --sp, r0-r7");														\
-																									\
-  /* With the cooperative scheduler, as there is no context switch by interrupt, */					\
-  /* there is also no context save. */																\
-}
-
-/*
- * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
- */
-#define portEXIT_SWITCHING_ISR()																	\
-{																									\
-  __asm__ __volatile__ (																			\
-    /* Restore R0..R7 */																			\
-    "ldm     sp++, r0-r7																			\n\t"\
-																									\
-    /* With the cooperative scheduler, as there is no context switch by interrupt, */				\
-    /* there is also no context restore. */															\
-    "rete"																							\
-  );																								\
-}
-
-#else
-
-/*
- * ISR entry and exit macros.  These are only required if a task switch
- * is required from the ISR.
- */
-#define portENTER_SWITCHING_ISR()																	\
-{																									\
-  extern volatile uint32_t ulCriticalNesting;												\
-  extern volatile void *volatile pxCurrentTCB;														\
-																									\
-  /* When we come here */																			\
-  /* Registers R8..R12, LR, PC and SR had already been pushed to system stack */					\
-																									\
-  __asm__ __volatile__ (																			\
-    /* Save R0..R7 */																				\
-    "stm     --sp, r0-r7																			\n\t"\
-																									\
-    /* Save ulCriticalNesting variable  - R0 is overwritten */										\
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
-    "ld.w    r0, r8[0]																				\n\t"\
-    "st.w    --sp, r0																				\n\t"\
-																									\
-    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
-    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
-    /* level and allow other lower interrupt level to occur). */									\
-    /* In this case we don't want to do a task switch because we don't know what the stack */		\
-    /* currently looks like (we don't know what the interrupted interrupt handler was doing). */	\
-    /* Saving SP in pxCurrentTCB and then later restoring it (thinking restoring the task) */		\
-    /* will just be restoring the interrupt handler, no way!!! */									\
-    /* So, since we won't do a vTaskSwitchContext(), it's of no use to save SP. */					\
-    "ld.w    r0, sp[9*4]																			\n\t" /* Read SR in stack */\
-    "bfextu  r0, r0, 22, 3																			\n\t" /* Extract the mode bits to R0. */\
-    "cp.w    r0, 1																					\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
-    "brhi    LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)"										\n\t"\
-																									\
-    /* Store SP in the first member of the structure pointed to by pxCurrentTCB */					\
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
-    "ld.w    r0, r8[0]																				\n\t"\
-    "st.w    r0[0], sp																				\n"\
-																									\
-    "LABEL_ISR_SKIP_SAVE_CONTEXT_"ASTRINGZ(__LINE__)":"												\
-  );																								\
-}
-
-
-/*
- * Input parameter: in R12, boolean. Perform a vTaskSwitchContext() if 1
- */
-#define portEXIT_SWITCHING_ISR()																	\
-{																									\
-  extern volatile uint32_t ulCriticalNesting;												\
-  extern volatile void *volatile pxCurrentTCB;														\
-																									\
-  __asm__ __volatile__ (																			\
-    /* Check if INT0 or higher were being handled (case where the OS tick interrupted another */	\
-    /* interrupt handler (which was of a higher priority level but decided to lower its priority */	\
-    /* level and allow other lower interrupt level to occur). */									\
-    /* In this case it's of no use to switch context and restore a new SP because we purposedly */	\
-    /* did not previously save SP in its TCB. */													\
-    "ld.w    r0, sp[9*4]																			\n\t" /* Read SR in stack */\
-    "bfextu  r0, r0, 22, 3																			\n\t" /* Extract the mode bits to R0. */\
-    "cp.w    r0, 1																					\n\t" /* Compare the mode bits with supervisor mode(b'001) */\
-    "brhi    LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)"									\n\t"\
-																									\
-    /* If a switch is required then we just need to call */											\
-    /* vTaskSwitchContext() as the context has already been */										\
-    /* saved. */																					\
-    "cp.w    r12, 1																					\n\t" /* Check if Switch context is required. */\
-    "brne    LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":C"										\
-  );																								\
-																									\
-  /* A critical section has to be used here because vTaskSwitchContext handles FreeRTOS linked lists. */\
-  portENTER_CRITICAL();																				\
-  vTaskSwitchContext();																				\
-  portEXIT_CRITICAL();																				\
-																									\
-  __asm__ __volatile__ (																			\
-    "LABEL_ISR_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":												\n\t"\
-    /* Restore the context of which ever task is now the highest */									\
-    /* priority that is ready to run. */															\
-																									\
-    /* Restore all registers */																		\
-																									\
-    /* Set SP to point to new stack */																\
-    "mov     r8, LWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(pxCurrentTCB)")														\n\t"\
-    "ld.w    r0, r8[0]																				\n\t"\
-    "ld.w    sp, r0[0]																				\n"\
-																									\
-    "LABEL_ISR_SKIP_RESTORE_CONTEXT_"ASTRINGZ(__LINE__)":											\n\t"\
-																									\
-    /* Restore ulCriticalNesting variable */														\
-    "ld.w    r0, sp++																				\n\t"\
-    "mov     r8, LWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
-    "orh     r8, HWRD("ASTRINGZ(ulCriticalNesting)")												\n\t"\
-    "st.w    r8[0], r0																				\n\t"\
-																									\
-    /* Restore R0..R7 */																			\
-    "ldm     sp++, r0-r7																			\n\t"\
-																									\
-    /* Now, the stack should be R8..R12, LR, PC and SR  */											\
-    "rete"																							\
-  );																								\
-																									\
-  /* Force import of global symbols from assembly */												\
-  ulCriticalNesting;																				\
-  pxCurrentTCB;																						\
-}
-
-#endif
-
-
-#define portYIELD()                 {__asm__ __volatile__ ("scall");}
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
diff --git a/FreeRTOS/Source/portable/IAR/AVR32_UC3/read.c b/FreeRTOS/Source/portable/IAR/AVR32_UC3/read.c
deleted file mode 100755
index 21a3071..0000000
--- a/FreeRTOS/Source/portable/IAR/AVR32_UC3/read.c
+++ /dev/null
@@ -1,93 +0,0 @@
-/*This file is prepared for Doxygen automatic documentation generation.*/
-/*! \file *********************************************************************
- *
- * \brief System-specific implementation of the \ref __read function used by
-          the standard library.
- *
- * - Compiler:           IAR EWAVR32
- * - Supported devices:  All AVR32 devices with a USART module can be used.
- * - AppNote:
- *
- * \author               Atmel Corporation: http://www.atmel.com \n
- *                       Support and FAQ: http://support.atmel.no/
- *
- ******************************************************************************/
-
-/* Copyright (c) 2007, Atmel Corporation All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of ATMEL may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
- * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include 
-#include 
-#include "usart.h"
-
-
-_STD_BEGIN
-
-
-#pragma module_name = "?__read"
-
-
-extern volatile avr32_usart_t *volatile stdio_usart_base;
-
-
-/*! \brief Reads a number of bytes, at most \a size, into the memory area
- *         pointed to by \a buffer.
- *
- * \param handle File handle to read from.
- * \param buffer Pointer to buffer to write read bytes to.
- * \param size Number of bytes to read.
- *
- * \return The number of bytes read, \c 0 at the end of the file, or
- *         \c _LLIO_ERROR on failure.
- */
-size_t __read(int handle, uint8_t *buffer, size_t size)
-{
-  int nChars = 0;
-
-  // This implementation only reads from stdin.
-  // For all other file handles, it returns failure.
-  if (handle != _LLIO_STDIN)
-  {
-    return _LLIO_ERROR;
-  }
-
-  for (; size > 0; --size)
-  {
-    int c = usart_getchar(stdio_usart_base);
-    if (c < 0)
-      break;
-
-    *buffer++ = c;
-    ++nChars;
-  }
-
-  return nChars;
-}
-
-
-_STD_END
diff --git a/FreeRTOS/Source/portable/IAR/AVR32_UC3/write.c b/FreeRTOS/Source/portable/IAR/AVR32_UC3/write.c
deleted file mode 100755
index aabeb29..0000000
--- a/FreeRTOS/Source/portable/IAR/AVR32_UC3/write.c
+++ /dev/null
@@ -1,103 +0,0 @@
-/*This file is prepared for Doxygen automatic documentation generation.*/
-/*! \file *********************************************************************
- *
- * \brief System-specific implementation of the \ref __write function used by
-          the standard library.
- *
- * - Compiler:           IAR EWAVR32
- * - Supported devices:  All AVR32 devices with a USART module can be used.
- * - AppNote:
- *
- * \author               Atmel Corporation: http://www.atmel.com \n
- *                       Support and FAQ: http://support.atmel.no/
- *
- ******************************************************************************/
-
-/* Copyright (c) 2007, Atmel Corporation All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- * this list of conditions and the following disclaimer.
- *
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- * this list of conditions and the following disclaimer in the documentation
- * and/or other materials provided with the distribution.
- *
- * 3. The name of ATMEL may not be used to endorse or promote products derived
- * from this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
- * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
- * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
- * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include 
-#include 
-#include "usart.h"
-
-
-_STD_BEGIN
-
-
-#pragma module_name = "?__write"
-
-
-//! Pointer to the base of the USART module instance to use for stdio.
-__no_init volatile avr32_usart_t *volatile stdio_usart_base;
-
-
-/*! \brief Writes a number of bytes, at most \a size, from the memory area
- *         pointed to by \a buffer.
- *
- * If \a buffer is zero then \ref __write performs flushing of internal buffers,
- * if any. In this case, \a handle can be \c -1 to indicate that all handles
- * should be flushed.
- *
- * \param handle File handle to write to.
- * \param buffer Pointer to buffer to read bytes to write from.
- * \param size Number of bytes to write.
- *
- * \return The number of bytes written, or \c _LLIO_ERROR on failure.
- */
-size_t __write(int handle, const uint8_t *buffer, size_t size)
-{
-  size_t nChars = 0;
-
-  if (buffer == 0)
-  {
-    // This means that we should flush internal buffers.
-    return 0;
-  }
-
-  // This implementation only writes to stdout and stderr.
-  // For all other file handles, it returns failure.
-  if (handle != _LLIO_STDOUT && handle != _LLIO_STDERR)
-  {
-    return _LLIO_ERROR;
-  }
-
-  for (; size != 0; --size)
-  {
-    if (usart_putchar(stdio_usart_base, *buffer++) < 0)
-    {
-      return _LLIO_ERROR;
-    }
-
-    ++nChars;
-  }
-
-  return nChars;
-}
-
-
-_STD_END
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
deleted file mode 100755
index 233dc07..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64.h
+++ /dev/null
@@ -1,1914 +0,0 @@
-// ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-// ----------------------------------------------------------------------------
-//  The software is delivered "AS IS" without warranty or condition of any
-//  kind, either express, implied or statutory. This includes without
-//  limitation any warranty or condition with respect to merchantability or
-//  fitness for any particular purpose, or against the infringements of
-//  intellectual property rights of others.
-// ----------------------------------------------------------------------------
-// File Name           : AT91SAM7S64.h
-// Object              : AT91SAM7S64 definitions
-// Generated           : AT91 SW Application Group  07/16/2004 (07:43:08)
-// 
-// CVS Reference       : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
-// CVS Reference       : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
-// CVS Reference       : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
-// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug  2 14:45:38 2002//
-// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
-// CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
-// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
-// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
-// CVS Reference       : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
-// CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
-// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov  8 13:26:40 2002//
-// CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb  7 10:30:08 2003//
-// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
-// CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
-// CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-// ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7S64_H
-#define AT91SAM7S64_H
-
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYSC {
-	AT91_REG	 SYSC_AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 SYSC_AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 SYSC_AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 SYSC_AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 SYSC_AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 SYSC_AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 SYSC_AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 SYSC_AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 SYSC_AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 SYSC_AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 SYSC_AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 SYSC_AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 SYSC_AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 SYSC_AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 SYSC_AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 SYSC_AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 SYSC_AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 SYSC_AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	// 
-	AT91_REG	 SYSC_DBGU_CR; 	// Control Register
-	AT91_REG	 SYSC_DBGU_MR; 	// Mode Register
-	AT91_REG	 SYSC_DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 SYSC_DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SYSC_DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 SYSC_DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 SYSC_DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 SYSC_DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 SYSC_DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	// 
-	AT91_REG	 SYSC_DBGU_C1R; 	// Chip ID1 Register
-	AT91_REG	 SYSC_DBGU_C2R; 	// Chip ID2 Register
-	AT91_REG	 SYSC_DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	// 
-	AT91_REG	 SYSC_DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 SYSC_DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 SYSC_DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SYSC_DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 SYSC_DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SYSC_DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SYSC_DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SYSC_DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SYSC_DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SYSC_DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	// 
-	AT91_REG	 SYSC_PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 SYSC_PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 SYSC_PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	// 
-	AT91_REG	 SYSC_PIOA_OER; 	// Output Enable Register
-	AT91_REG	 SYSC_PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 SYSC_PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	// 
-	AT91_REG	 SYSC_PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 SYSC_PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 SYSC_PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	// 
-	AT91_REG	 SYSC_PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 SYSC_PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 SYSC_PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 SYSC_PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 SYSC_PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 SYSC_PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SYSC_PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 SYSC_PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 SYSC_PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 SYSC_PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 SYSC_PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	// 
-	AT91_REG	 SYSC_PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 SYSC_PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 SYSC_PIOA_PPUSR; 	// Pad Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	// 
-	AT91_REG	 SYSC_PIOA_ASR; 	// Select A Register
-	AT91_REG	 SYSC_PIOA_BSR; 	// Select B Register
-	AT91_REG	 SYSC_PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	// 
-	AT91_REG	 SYSC_PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 SYSC_PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 SYSC_PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[469]; 	// 
-	AT91_REG	 SYSC_PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 SYSC_PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 SYSC_PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved13[1]; 	// 
-	AT91_REG	 SYSC_PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 SYSC_PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 SYSC_PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved14[1]; 	// 
-	AT91_REG	 SYSC_PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 SYSC_PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved15[1]; 	// 
-	AT91_REG	 SYSC_PMC_PLLR; 	// PLL Register
-	AT91_REG	 SYSC_PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved16[3]; 	// 
-	AT91_REG	 SYSC_PMC_PCKR[8]; 	// Programmable Clock Register
-	AT91_REG	 SYSC_PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SYSC_PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SYSC_PMC_SR; 	// Status Register
-	AT91_REG	 SYSC_PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved17[36]; 	// 
-	AT91_REG	 SYSC_RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 SYSC_RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 SYSC_RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved18[5]; 	// 
-	AT91_REG	 SYSC_RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 SYSC_RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 SYSC_RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 SYSC_RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 SYSC_PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 SYSC_PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 SYSC_PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 SYSC_PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 SYSC_WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 SYSC_WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 SYSC_WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved19[5]; 	// 
-	AT91_REG	 SYSC_SYSC_VRPM; 	// Voltage Regulator Power Mode Register
-} AT91S_SYSC, *AT91PS_SYSC;
-
-// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- 
-#define AT91C_SYSC_PSTDBY     ((unsigned int) 0x1 <<  0) // (SYSC) Voltage Regulator Power Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       ((unsigned int) 0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    ((unsigned int) 0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	// 
-	AT91_REG	 DBGU_C1R; 	// Chip ID1 Register
-	AT91_REG	 DBGU_C2R; 	// Chip ID2 Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	// 
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pad Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	// 
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	// 
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	// 
-	AT91_REG	 PMC_PCKR[8]; 	// Programmable Clock Register
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-
-// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-#define AT91C_SYSC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_SYSC_ICERST     ((unsigned int) 0x1 <<  1) // (RSTC) ICE Interface Reset
-#define AT91C_SYSC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_SYSC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
-#define AT91C_SYSC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-#define AT91C_SYSC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_SYSC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brown-out Detection Status
-#define AT91C_SYSC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_SYSC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_SYSC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_SYSC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_SYSC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_SYSC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brown-out Reset.
-#define AT91C_SYSC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_SYSC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-#define AT91C_SYSC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_SYSC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_SYSC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_SYSC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-
-// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-#define AT91C_SYSC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_SYSC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_SYSC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_SYSC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-#define AT91C_SYSC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
-// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-#define AT91C_SYSC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-#define AT91C_SYSC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_SYSC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-
-// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-#define AT91C_SYSC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_SYSC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_SYSC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-#define AT91C_SYSC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-#define AT91C_SYSC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_SYSC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-
-// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-#define AT91C_SYSC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
-// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-#define AT91C_SYSC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_SYSC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_SYSC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_SYSC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_SYSC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_SYSC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_SYSC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_SYSC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-#define AT91C_SYSC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_SYSC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[21]; 	// 
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	// 
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	// 
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 SSC_RC0R; 	// Receive Compare 0 Register
-	AT91_REG	 SSC_RC1R; 	// Receive Compare 1 Register
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved2[44]; 	// 
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG         ((unsigned int) 0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
-#define 	AT91C_SSC_CKG_NONE                 ((unsigned int) 0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define 	AT91C_SSC_CKG_LOW                  ((unsigned int) 0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define 	AT91C_SSC_CKG_HIGH                 ((unsigned int) 0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STOP        ((unsigned int) 0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTOUT      ((unsigned int) 0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
-#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0         ((unsigned int) 0x1 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_CP1         ((unsigned int) 0x1 <<  9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	// 
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 US_XXR; 	// XON_XOFF Register
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved1[44]; 	// 
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (USART) Reset Status Bits
-#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 TWI_SMR; 	// Slave Mode Register
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved0[3]; 	// 
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
-
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SVEN        ((unsigned int) 0x1 <<  4) // (TWI) TWI Slave Transfer Enabled
-#define AT91C_TWI_SVDIS       ((unsigned int) 0x1 <<  5) // (TWI) TWI Slave Transfer Disabled
-#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
-#define AT91C_TWI_SADR        ((unsigned int) 0x7F << 16) // (TWI) Slave Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_SVREAD      ((unsigned int) 0x1 <<  3) // (TWI) Slave Read
-#define AT91C_TWI_SVACC       ((unsigned int) 0x1 <<  4) // (TWI) Slave Access
-#define AT91C_TWI_GCACC       ((unsigned int) 0x1 <<  5) // (TWI) General Call Access
-#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ARBLST      ((unsigned int) 0x1 <<  9) // (TWI) Arbitration Lost
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_NONE                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_RISING               ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_FALLING              ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_BOTH                 ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
-#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRCS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_ETRGS        ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	// 
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x1 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x1 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x1 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA2                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
-#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	// 
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_PWMC_CH	 PWMC_CH[32]; 	// PWMC Channel 0
-} AT91S_PWMC, *AT91PS_PWMC;
-
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
-#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
-#define AT91C_PWMC_CHID4      ((unsigned int) 0x1 <<  4) // (PWMC) Channel ID 4
-#define AT91C_PWMC_CHID5      ((unsigned int) 0x1 <<  5) // (PWMC) Channel ID 5
-#define AT91C_PWMC_CHID6      ((unsigned int) 0x1 <<  6) // (PWMC) Channel ID 6
-#define AT91C_PWMC_CHID7      ((unsigned int) 0x1 <<  7) // (PWMC) Channel ID 7
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 UDP_CSR[8]; 	// Endpoint Control and Status Register
-	AT91_REG	 UDP_FDR[8]; 	// Endpoint FIFO Data Register
-} AT91S_UDP, *AT91PS_UDP;
-
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  2) // (UDP) Remote Wake Up Enable
-#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_EPINT6      ((unsigned int) 0x1 <<  6) // (UDP) Endpoint 6 Interrupt
-#define AT91C_UDP_EPINT7      ((unsigned int) 0x1 <<  7) // (UDP) Endpoint 7 Interrupt
-#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
-#define AT91C_UDP_EP6         ((unsigned int) 0x1 <<  6) // (UDP) Reset Endpoint 6
-#define AT91C_UDP_EP7         ((unsigned int) 0x1 <<  7) // (UDP) Reset Endpoint 7
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
-// *****************************************************************************
-// ========== Register definition for SYSC peripheral ========== 
-#define AT91C_SYSC_SYSC_VRPM ((AT91_REG *) 	0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register
-// ========== Register definition for AIC peripheral ========== 
-#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-// ========== Register definition for DBGU peripheral ========== 
-#define AT91C_DBGU_C2R  ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID2 Register
-#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_C1R  ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID1 Register
-#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-// ========== Register definition for PDC_DBGU peripheral ========== 
-#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-// ========== Register definition for PIOA peripheral ========== 
-#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pad Pull-up Status Register
-#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-// ========== Register definition for CKGR peripheral ========== 
-#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-// ========== Register definition for PMC peripheral ========== 
-#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-// ========== Register definition for RSTC peripheral ========== 
-#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-// ========== Register definition for RTTC peripheral ========== 
-#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-// ========== Register definition for PITC peripheral ========== 
-#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ========== 
-#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-// ========== Register definition for MC peripheral ========== 
-#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
-#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-// ========== Register definition for PDC_SPI peripheral ========== 
-#define AT91C_SPI_PTCR  ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TNPR  ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-#define AT91C_SPI_RNPR  ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_TPR   ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_RPR   ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_PTSR  ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_TNCR  ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR  ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TCR   ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR   ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI) Receive Counter Register
-// ========== Register definition for SPI peripheral ========== 
-#define AT91C_SPI_CSR   ((AT91_REG *) 	0xFFFE0030) // (SPI) Chip Select Register
-#define AT91C_SPI_IDR   ((AT91_REG *) 	0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_SR    ((AT91_REG *) 	0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_RDR   ((AT91_REG *) 	0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CR    ((AT91_REG *) 	0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_IMR   ((AT91_REG *) 	0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_IER   ((AT91_REG *) 	0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_TDR   ((AT91_REG *) 	0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_MR    ((AT91_REG *) 	0xFFFE0004) // (SPI) Mode Register
-// ========== Register definition for PDC_ADC peripheral ========== 
-#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ========== 
-#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-// ========== Register definition for PDC_SSC peripheral ========== 
-#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-// ========== Register definition for SSC peripheral ========== 
-#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_RC0R  ((AT91_REG *) 	0xFFFD4038) // (SSC) Receive Compare 0 Register
-#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_RC1R  ((AT91_REG *) 	0xFFFD403C) // (SSC) Receive Compare 1 Register
-#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-// ========== Register definition for PDC_US1 peripheral ========== 
-#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-// ========== Register definition for US1 peripheral ========== 
-#define AT91C_US1_XXR   ((AT91_REG *) 	0xFFFC4048) // (US1) XON_XOFF Register
-#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ========== 
-#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-// ========== Register definition for US0 peripheral ========== 
-#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_XXR   ((AT91_REG *) 	0xFFFC0048) // (US0) XON_XOFF Register
-#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-// ========== Register definition for TWI peripheral ========== 
-#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_SMR   ((AT91_REG *) 	0xFFFB8008) // (TWI) Slave Mode Register
-#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-// ========== Register definition for TC2 peripheral ========== 
-#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-// ========== Register definition for TC1 peripheral ========== 
-#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-// ========== Register definition for TC0 peripheral ========== 
-#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-// ========== Register definition for TCB peripheral ========== 
-#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for PWMC_CH3 peripheral ========== 
-#define AT91C_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_CH3_CMR   ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-#define AT91C_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH2 peripheral ========== 
-#define AT91C_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_CH2_CMR   ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ========== 
-#define AT91C_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_CH1_CMR   ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-#define AT91C_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH0 peripheral ========== 
-#define AT91C_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_CH0_CMR   ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-#define AT91C_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-// ========== Register definition for PWMC peripheral ========== 
-#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-// ========== Register definition for UDP peripheral ========== 
-#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_PWM0     ((unsigned int) AT91C_PIO_PA0) //  PWM Channel 0
-#define AT91C_PA0_TIOA0    ((unsigned int) AT91C_PIO_PA0) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_PWM1     ((unsigned int) AT91C_PIO_PA1) //  PWM Channel 1
-#define AT91C_PA1_TIOB0    ((unsigned int) AT91C_PIO_PA1) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_DTXD     ((unsigned int) AT91C_PIO_PA10) //  DBGU Debug Transmit Data
-#define AT91C_PA10_NPCS2    ((unsigned int) AT91C_PIO_PA10) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_NPCS0    ((unsigned int) AT91C_PIO_PA11) //  SPI Peripheral Chip Select 0
-#define AT91C_PA11_PWM0     ((unsigned int) AT91C_PIO_PA11) //  PWM Channel 0
-#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_MISO     ((unsigned int) AT91C_PIO_PA12) //  SPI Master In Slave
-#define AT91C_PA12_PWM1     ((unsigned int) AT91C_PIO_PA12) //  PWM Channel 1
-#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_MOSI     ((unsigned int) AT91C_PIO_PA13) //  SPI Master Out Slave
-#define AT91C_PA13_PWM2     ((unsigned int) AT91C_PIO_PA13) //  PWM Channel 2
-#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPCK     ((unsigned int) AT91C_PIO_PA14) //  SPI Serial Clock
-#define AT91C_PA14_PWM3     ((unsigned int) AT91C_PIO_PA14) //  PWM Channel 3
-#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_TF       ((unsigned int) AT91C_PIO_PA15) //  SSC Transmit Frame Sync
-#define AT91C_PA15_TIOA1    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_TK       ((unsigned int) AT91C_PIO_PA16) //  SSC Transmit Clock
-#define AT91C_PA16_TIOB1    ((unsigned int) AT91C_PIO_PA16) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TD       ((unsigned int) AT91C_PIO_PA17) //  SSC Transmit data
-#define AT91C_PA17_PCK1     ((unsigned int) AT91C_PIO_PA17) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RD       ((unsigned int) AT91C_PIO_PA18) //  SSC Receive Data
-#define AT91C_PA18_PCK2     ((unsigned int) AT91C_PIO_PA18) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_RK       ((unsigned int) AT91C_PIO_PA19) //  SSC Receive Clock
-#define AT91C_PA19_FIQ      ((unsigned int) AT91C_PIO_PA19) //  AIC Fast Interrupt Input
-#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_PWM2     ((unsigned int) AT91C_PIO_PA2) //  PWM Channel 2
-#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_RF       ((unsigned int) AT91C_PIO_PA20) //  SSC Receive Frame Sync
-#define AT91C_PA20_IRQ0     ((unsigned int) AT91C_PIO_PA20) //  External Interrupt 0
-#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RXD1     ((unsigned int) AT91C_PIO_PA21) //  USART 1 Receive Data
-#define AT91C_PA21_PCK1     ((unsigned int) AT91C_PIO_PA21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TXD1     ((unsigned int) AT91C_PIO_PA22) //  USART 1 Transmit Data
-#define AT91C_PA22_NPCS3    ((unsigned int) AT91C_PIO_PA22) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_SCK1     ((unsigned int) AT91C_PIO_PA23) //  USART 1 Serial Clock
-#define AT91C_PA23_PWM0     ((unsigned int) AT91C_PIO_PA23) //  PWM Channel 0
-#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RTS1     ((unsigned int) AT91C_PIO_PA24) //  USART 1 Ready To Send
-#define AT91C_PA24_PWM1     ((unsigned int) AT91C_PIO_PA24) //  PWM Channel 1
-#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_CTS1     ((unsigned int) AT91C_PIO_PA25) //  USART 1 Clear To Send
-#define AT91C_PA25_PWM2     ((unsigned int) AT91C_PIO_PA25) //  PWM Channel 2
-#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_DCD1     ((unsigned int) AT91C_PIO_PA26) //  USART 1 Data Carrier Detect
-#define AT91C_PA26_TIOA2    ((unsigned int) AT91C_PIO_PA26) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DTR1     ((unsigned int) AT91C_PIO_PA27) //  USART 1 Data Terminal ready
-#define AT91C_PA27_TIOB2    ((unsigned int) AT91C_PIO_PA27) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DSR1     ((unsigned int) AT91C_PIO_PA28) //  USART 1 Data Set ready
-#define AT91C_PA28_TCLK1    ((unsigned int) AT91C_PIO_PA28) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_RI1      ((unsigned int) AT91C_PIO_PA29) //  USART 1 Ring Indicator
-#define AT91C_PA29_TCLK2    ((unsigned int) AT91C_PIO_PA29) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_TWD      ((unsigned int) AT91C_PIO_PA3) //  TWI Two-wire Serial Data
-#define AT91C_PA3_NPCS3    ((unsigned int) AT91C_PIO_PA3) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ1     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 1
-#define AT91C_PA30_NPCS2    ((unsigned int) AT91C_PIO_PA30) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA31       ((unsigned int) 1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_NPCS1    ((unsigned int) AT91C_PIO_PA31) //  SPI Peripheral Chip Select 1
-#define AT91C_PA31_PCK2     ((unsigned int) AT91C_PIO_PA31) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_TWCK     ((unsigned int) AT91C_PIO_PA4) //  TWI Two-wire Serial Clock
-#define AT91C_PA4_TCLK0    ((unsigned int) AT91C_PIO_PA4) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD0     ((unsigned int) AT91C_PIO_PA5) //  USART 0 Receive Data
-#define AT91C_PA5_NPCS3    ((unsigned int) AT91C_PIO_PA5) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD0     ((unsigned int) AT91C_PIO_PA6) //  USART 0 Transmit Data
-#define AT91C_PA6_PCK0     ((unsigned int) AT91C_PIO_PA6) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_RTS0     ((unsigned int) AT91C_PIO_PA7) //  USART 0 Ready To Send
-#define AT91C_PA7_PWM3     ((unsigned int) AT91C_PIO_PA7) //  PWM Channel 3
-#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_CTS0     ((unsigned int) AT91C_PIO_PA8) //  USART 0 Clear To Send
-#define AT91C_PA8_ADTRG    ((unsigned int) AT91C_PIO_PA8) //  ADC External Trigger
-#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_DRXD     ((unsigned int) AT91C_PIO_PA9) //  DBGU Debug Receive Data
-#define AT91C_PA9_NPCS1    ((unsigned int) AT91C_PIO_PA9) //  SPI Peripheral Chip Select 1
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
-#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller
-#define AT91C_ID_3_Reserved ((unsigned int)  3) // Reserved
-#define AT91C_ID_ADC    ((unsigned int)  4) // Analog-to-Digital Converter
-#define AT91C_ID_SPI    ((unsigned int)  5) // Serial Peripheral Interface
-#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
-#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
-#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
-#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_15_Reserved ((unsigned int) 15) // Reserved
-#define AT91C_ID_16_Reserved ((unsigned int) 16) // Reserved
-#define AT91C_ID_17_Reserved ((unsigned int) 17) // Reserved
-#define AT91C_ID_18_Reserved ((unsigned int) 18) // Reserved
-#define AT91C_ID_19_Reserved ((unsigned int) 19) // Reserved
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_BASE_SYSC      ((AT91PS_SYSC) 	0xFFFFF000) // (SYSC) Base Address
-#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI   ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI       ((AT91PS_SPI) 	0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00004000) // Internal SRAM size in byte (16 Kbyte)
-#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00010000) // Internal ROM size in byte (64 Kbyte)
-
-#endif
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
deleted file mode 100755
index fe1451a..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7S64_inc.h
+++ /dev/null
@@ -1,1812 +0,0 @@
-// ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-// ----------------------------------------------------------------------------
-//  The software is delivered "AS IS" without warranty or condition of any
-//  kind, either express, implied or statutory. This includes without
-//  limitation any warranty or condition with respect to merchantability or
-//  fitness for any particular purpose, or against the infringements of
-//  intellectual property rights of others.
-// ----------------------------------------------------------------------------
-// File Name           : AT91SAM7S64.h
-// Object              : AT91SAM7S64 definitions
-// Generated           : AT91 SW Application Group  07/16/2004 (07:43:09)
-// 
-// CVS Reference       : /AT91SAM7S64.pl/1.12/Mon Jul 12 13:02:30 2004//
-// CVS Reference       : /SYSC_SAM7Sxx.pl/1.5/Mon Jul 12 16:22:12 2004//
-// CVS Reference       : /MC_SAM02.pl/1.3/Wed Mar 10 08:37:04 2004//
-// CVS Reference       : /UDP_1765B.pl/1.3/Fri Aug  2 14:45:38 2002//
-// CVS Reference       : /AIC_1796B.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
-// CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
-// CVS Reference       : /PIO_1725D.pl/1.1.1.1/Fri Jun 28 09:36:48 2002//
-// CVS Reference       : /DBGU_1754A.pl/1.4/Fri Jan 31 12:18:24 2003//
-// CVS Reference       : /US_1739C.pl/1.2/Mon Jul 12 17:26:24 2004//
-// CVS Reference       : /SPI2.pl/1.2/Fri Oct 17 08:13:40 2003//
-// CVS Reference       : /SSC_1762A.pl/1.2/Fri Nov  8 13:26:40 2002//
-// CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-// CVS Reference       : /TWI_1761B.pl/1.4/Fri Feb  7 10:30:08 2003//
-// CVS Reference       : /PDC_1734B.pl/1.2/Thu Nov 21 16:38:24 2002//
-// CVS Reference       : /ADC_SAM.pl/1.7/Fri Oct 17 08:12:38 2003//
-// CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-// ----------------------------------------------------------------------------
-
-// Hardware register definition
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-// *** Register offset in AT91S_SYSC structure ***
-#define SYSC_AIC_SMR    ( 0) // Source Mode Register
-#define SYSC_AIC_SVR    (128) // Source Vector Register
-#define SYSC_AIC_IVR    (256) // IRQ Vector Register
-#define SYSC_AIC_FVR    (260) // FIQ Vector Register
-#define SYSC_AIC_ISR    (264) // Interrupt Status Register
-#define SYSC_AIC_IPR    (268) // Interrupt Pending Register
-#define SYSC_AIC_IMR    (272) // Interrupt Mask Register
-#define SYSC_AIC_CISR   (276) // Core Interrupt Status Register
-#define SYSC_AIC_IECR   (288) // Interrupt Enable Command Register
-#define SYSC_AIC_IDCR   (292) // Interrupt Disable Command Register
-#define SYSC_AIC_ICCR   (296) // Interrupt Clear Command Register
-#define SYSC_AIC_ISCR   (300) // Interrupt Set Command Register
-#define SYSC_AIC_EOICR  (304) // End of Interrupt Command Register
-#define SYSC_AIC_SPU    (308) // Spurious Vector Register
-#define SYSC_AIC_DCR    (312) // Debug Control Register (Protect)
-#define SYSC_AIC_FFER   (320) // Fast Forcing Enable Register
-#define SYSC_AIC_FFDR   (324) // Fast Forcing Disable Register
-#define SYSC_AIC_FFSR   (328) // Fast Forcing Status Register
-#define SYSC_DBGU_CR    (512) // Control Register
-#define SYSC_DBGU_MR    (516) // Mode Register
-#define SYSC_DBGU_IER   (520) // Interrupt Enable Register
-#define SYSC_DBGU_IDR   (524) // Interrupt Disable Register
-#define SYSC_DBGU_IMR   (528) // Interrupt Mask Register
-#define SYSC_DBGU_CSR   (532) // Channel Status Register
-#define SYSC_DBGU_RHR   (536) // Receiver Holding Register
-#define SYSC_DBGU_THR   (540) // Transmitter Holding Register
-#define SYSC_DBGU_BRGR  (544) // Baud Rate Generator Register
-#define SYSC_DBGU_C1R   (576) // Chip ID1 Register
-#define SYSC_DBGU_C2R   (580) // Chip ID2 Register
-#define SYSC_DBGU_FNTR  (584) // Force NTRST Register
-#define SYSC_DBGU_RPR   (768) // Receive Pointer Register
-#define SYSC_DBGU_RCR   (772) // Receive Counter Register
-#define SYSC_DBGU_TPR   (776) // Transmit Pointer Register
-#define SYSC_DBGU_TCR   (780) // Transmit Counter Register
-#define SYSC_DBGU_RNPR  (784) // Receive Next Pointer Register
-#define SYSC_DBGU_RNCR  (788) // Receive Next Counter Register
-#define SYSC_DBGU_TNPR  (792) // Transmit Next Pointer Register
-#define SYSC_DBGU_TNCR  (796) // Transmit Next Counter Register
-#define SYSC_DBGU_PTCR  (800) // PDC Transfer Control Register
-#define SYSC_DBGU_PTSR  (804) // PDC Transfer Status Register
-#define SYSC_PIOA_PER   (1024) // PIO Enable Register
-#define SYSC_PIOA_PDR   (1028) // PIO Disable Register
-#define SYSC_PIOA_PSR   (1032) // PIO Status Register
-#define SYSC_PIOA_OER   (1040) // Output Enable Register
-#define SYSC_PIOA_ODR   (1044) // Output Disable Registerr
-#define SYSC_PIOA_OSR   (1048) // Output Status Register
-#define SYSC_PIOA_IFER  (1056) // Input Filter Enable Register
-#define SYSC_PIOA_IFDR  (1060) // Input Filter Disable Register
-#define SYSC_PIOA_IFSR  (1064) // Input Filter Status Register
-#define SYSC_PIOA_SODR  (1072) // Set Output Data Register
-#define SYSC_PIOA_CODR  (1076) // Clear Output Data Register
-#define SYSC_PIOA_ODSR  (1080) // Output Data Status Register
-#define SYSC_PIOA_PDSR  (1084) // Pin Data Status Register
-#define SYSC_PIOA_IER   (1088) // Interrupt Enable Register
-#define SYSC_PIOA_IDR   (1092) // Interrupt Disable Register
-#define SYSC_PIOA_IMR   (1096) // Interrupt Mask Register
-#define SYSC_PIOA_ISR   (1100) // Interrupt Status Register
-#define SYSC_PIOA_MDER  (1104) // Multi-driver Enable Register
-#define SYSC_PIOA_MDDR  (1108) // Multi-driver Disable Register
-#define SYSC_PIOA_MDSR  (1112) // Multi-driver Status Register
-#define SYSC_PIOA_PPUDR (1120) // Pull-up Disable Register
-#define SYSC_PIOA_PPUER (1124) // Pull-up Enable Register
-#define SYSC_PIOA_PPUSR (1128) // Pad Pull-up Status Register
-#define SYSC_PIOA_ASR   (1136) // Select A Register
-#define SYSC_PIOA_BSR   (1140) // Select B Register
-#define SYSC_PIOA_ABSR  (1144) // AB Select Status Register
-#define SYSC_PIOA_OWER  (1184) // Output Write Enable Register
-#define SYSC_PIOA_OWDR  (1188) // Output Write Disable Register
-#define SYSC_PIOA_OWSR  (1192) // Output Write Status Register
-#define SYSC_PMC_SCER   (3072) // System Clock Enable Register
-#define SYSC_PMC_SCDR   (3076) // System Clock Disable Register
-#define SYSC_PMC_SCSR   (3080) // System Clock Status Register
-#define SYSC_PMC_PCER   (3088) // Peripheral Clock Enable Register
-#define SYSC_PMC_PCDR   (3092) // Peripheral Clock Disable Register
-#define SYSC_PMC_PCSR   (3096) // Peripheral Clock Status Register
-#define SYSC_PMC_MOR    (3104) // Main Oscillator Register
-#define SYSC_PMC_MCFR   (3108) // Main Clock  Frequency Register
-#define SYSC_PMC_PLLR   (3116) // PLL Register
-#define SYSC_PMC_MCKR   (3120) // Master Clock Register
-#define SYSC_PMC_PCKR   (3136) // Programmable Clock Register
-#define SYSC_PMC_IER    (3168) // Interrupt Enable Register
-#define SYSC_PMC_IDR    (3172) // Interrupt Disable Register
-#define SYSC_PMC_SR     (3176) // Status Register
-#define SYSC_PMC_IMR    (3180) // Interrupt Mask Register
-#define SYSC_RSTC_RCR   (3328) // Reset Control Register
-#define SYSC_RSTC_RSR   (3332) // Reset Status Register
-#define SYSC_RSTC_RMR   (3336) // Reset Mode Register
-#define SYSC_RTTC_RTMR  (3360) // Real-time Mode Register
-#define SYSC_RTTC_RTAR  (3364) // Real-time Alarm Register
-#define SYSC_RTTC_RTVR  (3368) // Real-time Value Register
-#define SYSC_RTTC_RTSR  (3372) // Real-time Status Register
-#define SYSC_PITC_PIMR  (3376) // Period Interval Mode Register
-#define SYSC_PITC_PISR  (3380) // Period Interval Status Register
-#define SYSC_PITC_PIVR  (3384) // Period Interval Value Register
-#define SYSC_PITC_PIIR  (3388) // Period Interval Image Register
-#define SYSC_WDTC_WDCR  (3392) // Watchdog Control Register
-#define SYSC_WDTC_WDMR  (3396) // Watchdog Mode Register
-#define SYSC_WDTC_WDSR  (3400) // Watchdog Status Register
-#define SYSC_SYSC_VRPM  (3424) // Voltage Regulator Power Mode Register
-// -------- VRPM : (SYSC Offset: 0xd60) Voltage Regulator Power Mode Register -------- 
-#define AT91C_SYSC_PSTDBY         (0x1 <<  0) // (SYSC) Voltage Regulator Power Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-// *** Register offset in AT91S_AIC structure ***
-#define AIC_SMR         ( 0) // Source Mode Register
-#define AIC_SVR         (128) // Source Vector Register
-#define AIC_IVR         (256) // IRQ Vector Register
-#define AIC_FVR         (260) // FIQ Vector Register
-#define AIC_ISR         (264) // Interrupt Status Register
-#define AIC_IPR         (268) // Interrupt Pending Register
-#define AIC_IMR         (272) // Interrupt Mask Register
-#define AIC_CISR        (276) // Core Interrupt Status Register
-#define AIC_IECR        (288) // Interrupt Enable Command Register
-#define AIC_IDCR        (292) // Interrupt Disable Command Register
-#define AIC_ICCR        (296) // Interrupt Clear Command Register
-#define AIC_ISCR        (300) // Interrupt Set Command Register
-#define AIC_EOICR       (304) // End of Interrupt Command Register
-#define AIC_SPU         (308) // Spurious Vector Register
-#define AIC_DCR         (312) // Debug Control Register (Protect)
-#define AIC_FFER        (320) // Fast Forcing Enable Register
-#define AIC_FFDR        (324) // Fast Forcing Disable Register
-#define AIC_FFSR        (328) // Fast Forcing Status Register
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE  (0x0 <<  5) // (AIC) Internal Sources Code Label Level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED   (0x1 <<  5) // (AIC) Internal Sources Code Label Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL       (0x2 <<  5) // (AIC) External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE    (0x3 <<  5) // (AIC) External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-// *** Register offset in AT91S_DBGU structure ***
-#define DBGU_CR         ( 0) // Control Register
-#define DBGU_MR         ( 4) // Mode Register
-#define DBGU_IER        ( 8) // Interrupt Enable Register
-#define DBGU_IDR        (12) // Interrupt Disable Register
-#define DBGU_IMR        (16) // Interrupt Mask Register
-#define DBGU_CSR        (20) // Channel Status Register
-#define DBGU_RHR        (24) // Receiver Holding Register
-#define DBGU_THR        (28) // Transmitter Holding Register
-#define DBGU_BRGR       (32) // Baud Rate Generator Register
-#define DBGU_C1R        (64) // Chip ID1 Register
-#define DBGU_C2R        (68) // Chip ID2 Register
-#define DBGU_FNTR       (72) // Force NTRST Register
-#define DBGU_RPR        (256) // Receive Pointer Register
-#define DBGU_RCR        (260) // Receive Counter Register
-#define DBGU_TPR        (264) // Transmit Pointer Register
-#define DBGU_TCR        (268) // Transmit Counter Register
-#define DBGU_RNPR       (272) // Receive Next Pointer Register
-#define DBGU_RNCR       (276) // Receive Next Counter Register
-#define DBGU_TNPR       (280) // Transmit Next Pointer Register
-#define DBGU_TNCR       (284) // Transmit Next Counter Register
-#define DBGU_PTCR       (288) // PDC Transfer Control Register
-#define DBGU_PTSR       (292) // PDC Transfer Status Register
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral Data Controller
-// *****************************************************************************
-// *** Register offset in AT91S_PDC structure ***
-#define PDC_RPR         ( 0) // Receive Pointer Register
-#define PDC_RCR         ( 4) // Receive Counter Register
-#define PDC_TPR         ( 8) // Transmit Pointer Register
-#define PDC_TCR         (12) // Transmit Counter Register
-#define PDC_RNPR        (16) // Receive Next Pointer Register
-#define PDC_RNCR        (20) // Receive Next Counter Register
-#define PDC_TNPR        (24) // Transmit Next Pointer Register
-#define PDC_TNCR        (28) // Transmit Next Counter Register
-#define PDC_PTCR        (32) // PDC Transfer Control Register
-#define PDC_PTSR        (36) // PDC Transfer Status Register
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PIO structure ***
-#define PIO_PER         ( 0) // PIO Enable Register
-#define PIO_PDR         ( 4) // PIO Disable Register
-#define PIO_PSR         ( 8) // PIO Status Register
-#define PIO_OER         (16) // Output Enable Register
-#define PIO_ODR         (20) // Output Disable Registerr
-#define PIO_OSR         (24) // Output Status Register
-#define PIO_IFER        (32) // Input Filter Enable Register
-#define PIO_IFDR        (36) // Input Filter Disable Register
-#define PIO_IFSR        (40) // Input Filter Status Register
-#define PIO_SODR        (48) // Set Output Data Register
-#define PIO_CODR        (52) // Clear Output Data Register
-#define PIO_ODSR        (56) // Output Data Status Register
-#define PIO_PDSR        (60) // Pin Data Status Register
-#define PIO_IER         (64) // Interrupt Enable Register
-#define PIO_IDR         (68) // Interrupt Disable Register
-#define PIO_IMR         (72) // Interrupt Mask Register
-#define PIO_ISR         (76) // Interrupt Status Register
-#define PIO_MDER        (80) // Multi-driver Enable Register
-#define PIO_MDDR        (84) // Multi-driver Disable Register
-#define PIO_MDSR        (88) // Multi-driver Status Register
-#define PIO_PPUDR       (96) // Pull-up Disable Register
-#define PIO_PPUER       (100) // Pull-up Enable Register
-#define PIO_PPUSR       (104) // Pad Pull-up Status Register
-#define PIO_ASR         (112) // Select A Register
-#define PIO_BSR         (116) // Select B Register
-#define PIO_ABSR        (120) // AB Select Status Register
-#define PIO_OWER        (160) // Output Write Enable Register
-#define PIO_OWDR        (164) // Output Write Disable Register
-#define PIO_OWSR        (168) // Output Write Status Register
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-// *** Register offset in AT91S_CKGR structure ***
-#define CKGR_MOR        ( 0) // Main Oscillator Register
-#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
-#define CKGR_PLLR       (12) // PLL Register
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PMC structure ***
-#define PMC_SCER        ( 0) // System Clock Enable Register
-#define PMC_SCDR        ( 4) // System Clock Disable Register
-#define PMC_SCSR        ( 8) // System Clock Status Register
-#define PMC_PCER        (16) // Peripheral Clock Enable Register
-#define PMC_PCDR        (20) // Peripheral Clock Disable Register
-#define PMC_PCSR        (24) // Peripheral Clock Status Register
-#define PMC_MOR         (32) // Main Oscillator Register
-#define PMC_MCFR        (36) // Main Clock  Frequency Register
-#define PMC_PLLR        (44) // PLL Register
-#define PMC_MCKR        (48) // Master Clock Register
-#define PMC_PCKR        (64) // Programmable Clock Register
-#define PMC_IER         (96) // Interrupt Enable Register
-#define PMC_IDR         (100) // Interrupt Disable Register
-#define PMC_SR          (104) // Status Register
-#define PMC_IMR         (108) // Interrupt Mask Register
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_RSTC structure ***
-#define RSTC_RCR        ( 0) // Reset Control Register
-#define RSTC_RSR        ( 4) // Reset Status Register
-#define RSTC_RMR        ( 8) // Reset Mode Register
-// -------- SYSC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-#define AT91C_SYSC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_SYSC_ICERST         (0x1 <<  1) // (RSTC) ICE Interface Reset
-#define AT91C_SYSC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_SYSC_EXTRST         (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_SYSC_KEY            (0xFF << 24) // (RSTC) Password
-// -------- SYSC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-#define AT91C_SYSC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_SYSC_BODSTS         (0x1 <<  1) // (RSTC) Brown-out Detection Status
-#define AT91C_SYSC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_SYSC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_SYSC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_SYSC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_SYSC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_SYSC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brown-out Reset.
-#define AT91C_SYSC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_SYSC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- SYSC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-#define AT91C_SYSC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_SYSC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_SYSC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_SYSC_BODIEN         (0x1 << 16) // (RSTC) Brown-out Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_RTTC structure ***
-#define RTTC_RTMR       ( 0) // Real-time Mode Register
-#define RTTC_RTAR       ( 4) // Real-time Alarm Register
-#define RTTC_RTVR       ( 8) // Real-time Value Register
-#define RTTC_RTSR       (12) // Real-time Status Register
-// -------- SYSC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-#define AT91C_SYSC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_SYSC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_SYSC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_SYSC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- SYSC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-#define AT91C_SYSC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value
-// -------- SYSC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-#define AT91C_SYSC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- SYSC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-#define AT91C_SYSC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_SYSC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PITC structure ***
-#define PITC_PIMR       ( 0) // Period Interval Mode Register
-#define PITC_PISR       ( 4) // Period Interval Status Register
-#define PITC_PIVR       ( 8) // Period Interval Value Register
-#define PITC_PIIR       (12) // Period Interval Image Register
-// -------- SYSC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-#define AT91C_SYSC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_SYSC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_SYSC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- SYSC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-#define AT91C_SYSC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- SYSC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-#define AT91C_SYSC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_SYSC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- SYSC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_WDTC structure ***
-#define WDTC_WDCR       ( 0) // Watchdog Control Register
-#define WDTC_WDMR       ( 4) // Watchdog Mode Register
-#define WDTC_WDSR       ( 8) // Watchdog Status Register
-// -------- SYSC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-#define AT91C_SYSC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
-// -------- SYSC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-#define AT91C_SYSC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_SYSC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_SYSC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_SYSC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_SYSC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_SYSC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_SYSC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_SYSC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- SYSC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-#define AT91C_SYSC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_SYSC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_MC structure ***
-#define MC_RCR          ( 0) // MC Remap Control Register
-#define MC_ASR          ( 4) // MC Abort Status Register
-#define MC_AASR         ( 8) // MC Abort Address Status Register
-#define MC_FMR          (96) // MC Flash Mode Register
-#define MC_FCR          (100) // MC Flash Command Register
-#define MC_FSR          (104) // MC Flash Status Register
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SPI structure ***
-#define SPI_CR          ( 0) // Control Register
-#define SPI_MR          ( 4) // Mode Register
-#define SPI_RDR         ( 8) // Receive Data Register
-#define SPI_TDR         (12) // Transmit Data Register
-#define SPI_SR          (16) // Status Register
-#define SPI_IER         (20) // Interrupt Enable Register
-#define SPI_IDR         (24) // Interrupt Disable Register
-#define SPI_IMR         (28) // Interrupt Mask Register
-#define SPI_CSR         (48) // Chip Select Register
-#define SPI_RPR         (256) // Receive Pointer Register
-#define SPI_RCR         (260) // Receive Counter Register
-#define SPI_TPR         (264) // Transmit Pointer Register
-#define SPI_TCR         (268) // Transmit Counter Register
-#define SPI_RNPR        (272) // Receive Next Pointer Register
-#define SPI_RNCR        (276) // Receive Next Counter Register
-#define SPI_TNPR        (280) // Transmit Next Pointer Register
-#define SPI_TNCR        (284) // Transmit Next Counter Register
-#define SPI_PTCR        (288) // PDC Transfer Control Register
-#define SPI_PTSR        (292) // PDC Transfer Status Register
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT           (0x1 <<  2) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-// *** Register offset in AT91S_ADC structure ***
-#define ADC_CR          ( 0) // ADC Control Register
-#define ADC_MR          ( 4) // ADC Mode Register
-#define ADC_CHER        (16) // ADC Channel Enable Register
-#define ADC_CHDR        (20) // ADC Channel Disable Register
-#define ADC_CHSR        (24) // ADC Channel Status Register
-#define ADC_SR          (28) // ADC Status Register
-#define ADC_LCDR        (32) // ADC Last Converted Data Register
-#define ADC_IER         (36) // ADC Interrupt Enable Register
-#define ADC_IDR         (40) // ADC Interrupt Disable Register
-#define ADC_IMR         (44) // ADC Interrupt Mask Register
-#define ADC_CDR0        (48) // ADC Channel Data Register 0
-#define ADC_CDR1        (52) // ADC Channel Data Register 1
-#define ADC_CDR2        (56) // ADC Channel Data Register 2
-#define ADC_CDR3        (60) // ADC Channel Data Register 3
-#define ADC_CDR4        (64) // ADC Channel Data Register 4
-#define ADC_CDR5        (68) // ADC Channel Data Register 5
-#define ADC_CDR6        (72) // ADC Channel Data Register 6
-#define ADC_CDR7        (76) // ADC Channel Data Register 7
-#define ADC_RPR         (256) // Receive Pointer Register
-#define ADC_RCR         (260) // Receive Counter Register
-#define ADC_TPR         (264) // Transmit Pointer Register
-#define ADC_TCR         (268) // Transmit Counter Register
-#define ADC_RNPR        (272) // Receive Next Pointer Register
-#define ADC_RNCR        (276) // Receive Next Counter Register
-#define ADC_TNPR        (280) // Transmit Next Pointer Register
-#define ADC_TNCR        (284) // Transmit Next Counter Register
-#define ADC_PTCR        (288) // PDC Transfer Control Register
-#define ADC_PTSR        (292) // PDC Transfer Status Register
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SSC structure ***
-#define SSC_CR          ( 0) // Control Register
-#define SSC_CMR         ( 4) // Clock Mode Register
-#define SSC_RCMR        (16) // Receive Clock ModeRegister
-#define SSC_RFMR        (20) // Receive Frame Mode Register
-#define SSC_TCMR        (24) // Transmit Clock Mode Register
-#define SSC_TFMR        (28) // Transmit Frame Mode Register
-#define SSC_RHR         (32) // Receive Holding Register
-#define SSC_THR         (36) // Transmit Holding Register
-#define SSC_RSHR        (48) // Receive Sync Holding Register
-#define SSC_TSHR        (52) // Transmit Sync Holding Register
-#define SSC_RC0R        (56) // Receive Compare 0 Register
-#define SSC_RC1R        (60) // Receive Compare 1 Register
-#define SSC_SR          (64) // Status Register
-#define SSC_IER         (68) // Interrupt Enable Register
-#define SSC_IDR         (72) // Interrupt Disable Register
-#define SSC_IMR         (76) // Interrupt Mask Register
-#define SSC_RPR         (256) // Receive Pointer Register
-#define SSC_RCR         (260) // Receive Counter Register
-#define SSC_TPR         (264) // Transmit Pointer Register
-#define SSC_TCR         (268) // Transmit Counter Register
-#define SSC_RNPR        (272) // Receive Next Pointer Register
-#define SSC_RNCR        (276) // Receive Next Counter Register
-#define SSC_TNPR        (280) // Transmit Next Pointer Register
-#define SSC_TNCR        (284) // Transmit Next Counter Register
-#define SSC_PTCR        (288) // PDC Transfer Control Register
-#define SSC_PTSR        (292) // PDC Transfer Status Register
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_CKG             (0x3 <<  6) // (SSC) Receive/Transmit Clock Gating Selection
-#define 	AT91C_SSC_CKG_NONE                 (0x0 <<  6) // (SSC) Receive/Transmit Clock Gating: None, continuous clock
-#define 	AT91C_SSC_CKG_LOW                  (0x1 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF Low
-#define 	AT91C_SSC_CKG_HIGH                 (0x2 <<  6) // (SSC) Receive/Transmit Clock enabled only if RF High
-#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STOP            (0x1 << 12) // (SSC) Receive Stop Selection
-#define AT91C_SSC_STTOUT          (0x1 << 15) // (SSC) Receive/Transmit Start Output Selection
-#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_CP0             (0x1 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_CP1             (0x1 <<  9) // (SSC) Compare 1
-#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-// *** Register offset in AT91S_USART structure ***
-#define US_CR           ( 0) // Control Register
-#define US_MR           ( 4) // Mode Register
-#define US_IER          ( 8) // Interrupt Enable Register
-#define US_IDR          (12) // Interrupt Disable Register
-#define US_IMR          (16) // Interrupt Mask Register
-#define US_CSR          (20) // Channel Status Register
-#define US_RHR          (24) // Receiver Holding Register
-#define US_THR          (28) // Transmitter Holding Register
-#define US_BRGR         (32) // Baud Rate Generator Register
-#define US_RTOR         (36) // Receiver Time-out Register
-#define US_TTGR         (40) // Transmitter Time-guard Register
-#define US_FIDI         (64) // FI_DI_Ratio Register
-#define US_NER          (68) // Nb Errors Register
-#define US_XXR          (72) // XON_XOFF Register
-#define US_IF           (76) // IRDA_FILTER Register
-#define US_RPR          (256) // Receive Pointer Register
-#define US_RCR          (260) // Receive Counter Register
-#define US_TPR          (264) // Transmit Pointer Register
-#define US_TCR          (268) // Transmit Counter Register
-#define US_RNPR         (272) // Receive Next Pointer Register
-#define US_RNCR         (276) // Receive Next Counter Register
-#define US_TNPR         (280) // Transmit Next Pointer Register
-#define US_TNCR         (284) // Transmit Next Counter Register
-#define US_PTCR         (288) // PDC Transfer Control Register
-#define US_PTSR         (292) // PDC Transfer Status Register
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTSTA           (0x1 <<  8) // (USART) Reset Status Bits
-#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TWI structure ***
-#define TWI_CR          ( 0) // Control Register
-#define TWI_MMR         ( 4) // Master Mode Register
-#define TWI_SMR         ( 8) // Slave Mode Register
-#define TWI_IADR        (12) // Internal Address Register
-#define TWI_CWGR        (16) // Clock Waveform Generator Register
-#define TWI_SR          (32) // Status Register
-#define TWI_IER         (36) // Interrupt Enable Register
-#define TWI_IDR         (40) // Interrupt Disable Register
-#define TWI_IMR         (44) // Interrupt Mask Register
-#define TWI_RHR         (48) // Receive Holding Register
-#define TWI_THR         (52) // Transmit Holding Register
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SVEN            (0x1 <<  4) // (TWI) TWI Slave Transfer Enabled
-#define AT91C_TWI_SVDIS           (0x1 <<  5) // (TWI) TWI Slave Transfer Disabled
-#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
-// -------- TWI_SMR : (TWI Offset: 0x8) TWI Slave Mode Register -------- 
-#define AT91C_TWI_SADR            (0x7F << 16) // (TWI) Slave Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_SVREAD          (0x1 <<  3) // (TWI) Slave Read
-#define AT91C_TWI_SVACC           (0x1 <<  4) // (TWI) Slave Access
-#define AT91C_TWI_GCACC           (0x1 <<  5) // (TWI) General Call Access
-#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
-#define AT91C_TWI_ARBLST          (0x1 <<  9) // (TWI) Arbitration Lost
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TC structure ***
-#define TC_CCR          ( 0) // Channel Control Register
-#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (16) // Counter Value
-#define TC_RA           (20) // Register A
-#define TC_RB           (24) // Register B
-#define TC_RC           (28) // Register C
-#define TC_SR           (32) // Status Register
-#define TC_IER          (36) // Interrupt Enable Register
-#define TC_IDR          (40) // Interrupt Disable Register
-#define TC_IMR          (44) // Interrupt Mask Register
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI             (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST            (0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_LDBDIS           (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_ETRGEDG          (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_ABETRG           (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_NONE                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_RISING               (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_FALLING              (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_BOTH                 (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE             (0x1 << 15) // (TC) 
-#define AT91C_TC_LDRA             (0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRB             (0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRCS            (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_ETRGS            (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TCB structure ***
-#define TCB_TC0         ( 0) // TC Channel 0
-#define TCB_TC1         (64) // TC Channel 1
-#define TCB_TC2         (128) // TC Channel 2
-#define TCB_BCR         (192) // TC Block Control Register
-#define TCB_BMR         (196) // TC Block Mode Register
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-#define AT91C_TCB_TC0XC0S         (0x1 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S         (0x1 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S         (0x1 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA2                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PWMC_CH structure ***
-#define PWMC_CMR        ( 0) // Channel Mode Register
-#define PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
-#define PWMC_CPRDR      ( 8) // Channel Period Register
-#define PWMC_CCNTR      (12) // Channel Counter Register
-#define PWMC_CUPDR      (16) // Channel Update Register
-#define PWMC_Reserved   (20) // Reserved
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) 
-#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PWMC structure ***
-#define PWMC_MR         ( 0) // PWMC Mode Register
-#define PWMC_ENA        ( 4) // PWMC Enable Register
-#define PWMC_DIS        ( 8) // PWMC Disable Register
-#define PWMC_SR         (12) // PWMC Status Register
-#define PWMC_IER        (16) // PWMC Interrupt Enable Register
-#define PWMC_IDR        (20) // PWMC Interrupt Disable Register
-#define PWMC_IMR        (24) // PWMC Interrupt Mask Register
-#define PWMC_ISR        (28) // PWMC Interrupt Status Register
-#define PWMC_VR         (252) // PWMC Version Register
-#define PWMC_CH         (512) // PWMC Channel 0
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) 
-#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) 
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
-#define AT91C_PWMC_CHID4          (0x1 <<  4) // (PWMC) Channel ID 4
-#define AT91C_PWMC_CHID5          (0x1 <<  5) // (PWMC) Channel ID 5
-#define AT91C_PWMC_CHID6          (0x1 <<  6) // (PWMC) Channel ID 6
-#define AT91C_PWMC_CHID7          (0x1 <<  7) // (PWMC) Channel ID 7
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-// *** Register offset in AT91S_UDP structure ***
-#define UDP_NUM         ( 0) // Frame Number Register
-#define UDP_GLBSTATE    ( 4) // Global State Register
-#define UDP_FADDR       ( 8) // Function Address Register
-#define UDP_IER         (16) // Interrupt Enable Register
-#define UDP_IDR         (20) // Interrupt Disable Register
-#define UDP_IMR         (24) // Interrupt Mask Register
-#define UDP_ISR         (28) // Interrupt Status Register
-#define UDP_ICR         (32) // Interrupt Clear Register
-#define UDP_RSTEP       (40) // Reset Endpoint Register
-#define UDP_CSR         (48) // Endpoint Control and Status Register
-#define UDP_FDR         (80) // Endpoint FIFO Data Register
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_RMWUPE          (0x1 <<  2) // (UDP) Remote Wake Up Enable
-#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_EPINT6          (0x1 <<  6) // (UDP) Endpoint 6 Interrupt
-#define AT91C_UDP_EPINT7          (0x1 <<  7) // (UDP) Endpoint 7 Interrupt
-#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
-#define AT91C_UDP_EP6             (0x1 <<  6) // (UDP) Reset Endpoint 6
-#define AT91C_UDP_EP7             (0x1 <<  7) // (UDP) Reset Endpoint 7
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7S64
-// *****************************************************************************
-// ========== Register definition for SYSC peripheral ========== 
-#define AT91C_SYSC_SYSC_VRPM      (0xFFFFFD60) // (SYSC) Voltage Regulator Power Mode Register
-// ========== Register definition for AIC peripheral ========== 
-#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
-#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
-// ========== Register definition for DBGU peripheral ========== 
-#define AT91C_DBGU_C2R            (0xFFFFF244) // (DBGU) Chip ID2 Register
-#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_C1R            (0xFFFFF240) // (DBGU) Chip ID1 Register
-#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
-#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
-// ========== Register definition for PDC_DBGU peripheral ========== 
-#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-// ========== Register definition for PIOA peripheral ========== 
-#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
-#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pad Pull-up Status Register
-#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
-// ========== Register definition for CKGR peripheral ========== 
-#define AT91C_CKGR_PLLR           (0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
-// ========== Register definition for PMC peripheral ========== 
-#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
-#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_MOR             (0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_PLLR            (0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_MCFR            (0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
-// ========== Register definition for RSTC peripheral ========== 
-#define AT91C_RSTC_RSR            (0xFFFFFD04) // (RSTC) Reset Status Register
-#define AT91C_RSTC_RMR            (0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RCR            (0xFFFFFD00) // (RSTC) Reset Control Register
-// ========== Register definition for RTTC peripheral ========== 
-#define AT91C_RTTC_RTSR           (0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTAR           (0xFFFFFD24) // (RTTC) Real-time Alarm Register
-#define AT91C_RTTC_RTVR           (0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTMR           (0xFFFFFD20) // (RTTC) Real-time Mode Register
-// ========== Register definition for PITC peripheral ========== 
-#define AT91C_PITC_PIIR           (0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PISR           (0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIVR           (0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PIMR           (0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ========== 
-#define AT91C_WDTC_WDMR           (0xFFFFFD44) // (WDTC) Watchdog Mode Register
-#define AT91C_WDTC_WDSR           (0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDCR           (0xFFFFFD40) // (WDTC) Watchdog Control Register
-// ========== Register definition for MC peripheral ========== 
-#define AT91C_MC_FCR              (0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_FSR              (0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR              (0xFFFFFF60) // (MC) MC Flash Mode Register
-#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
-// ========== Register definition for PDC_SPI peripheral ========== 
-#define AT91C_SPI_PTCR            (0xFFFE0120) // (PDC_SPI) PDC Transfer Control Register
-#define AT91C_SPI_TNPR            (0xFFFE0118) // (PDC_SPI) Transmit Next Pointer Register
-#define AT91C_SPI_RNPR            (0xFFFE0110) // (PDC_SPI) Receive Next Pointer Register
-#define AT91C_SPI_TPR             (0xFFFE0108) // (PDC_SPI) Transmit Pointer Register
-#define AT91C_SPI_RPR             (0xFFFE0100) // (PDC_SPI) Receive Pointer Register
-#define AT91C_SPI_PTSR            (0xFFFE0124) // (PDC_SPI) PDC Transfer Status Register
-#define AT91C_SPI_TNCR            (0xFFFE011C) // (PDC_SPI) Transmit Next Counter Register
-#define AT91C_SPI_RNCR            (0xFFFE0114) // (PDC_SPI) Receive Next Counter Register
-#define AT91C_SPI_TCR             (0xFFFE010C) // (PDC_SPI) Transmit Counter Register
-#define AT91C_SPI_RCR             (0xFFFE0104) // (PDC_SPI) Receive Counter Register
-// ========== Register definition for SPI peripheral ========== 
-#define AT91C_SPI_CSR             (0xFFFE0030) // (SPI) Chip Select Register
-#define AT91C_SPI_IDR             (0xFFFE0018) // (SPI) Interrupt Disable Register
-#define AT91C_SPI_SR              (0xFFFE0010) // (SPI) Status Register
-#define AT91C_SPI_RDR             (0xFFFE0008) // (SPI) Receive Data Register
-#define AT91C_SPI_CR              (0xFFFE0000) // (SPI) Control Register
-#define AT91C_SPI_IMR             (0xFFFE001C) // (SPI) Interrupt Mask Register
-#define AT91C_SPI_IER             (0xFFFE0014) // (SPI) Interrupt Enable Register
-#define AT91C_SPI_TDR             (0xFFFE000C) // (SPI) Transmit Data Register
-#define AT91C_SPI_MR              (0xFFFE0004) // (SPI) Mode Register
-// ========== Register definition for PDC_ADC peripheral ========== 
-#define AT91C_ADC_PTCR            (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR            (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_RNPR            (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_TPR             (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RPR             (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_PTSR            (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_TNCR            (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNCR            (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_TCR             (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_RCR             (0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ========== 
-#define AT91C_ADC_IMR             (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-#define AT91C_ADC_CDR4            (0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR2            (0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR0            (0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR7            (0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR1            (0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_CDR3            (0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR5            (0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_MR              (0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_CDR6            (0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_CR              (0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CHER            (0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR            (0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_IER             (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_SR              (0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CHDR            (0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_IDR             (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_LCDR            (0xFFFD8020) // (ADC) ADC Last Converted Data Register
-// ========== Register definition for PDC_SSC peripheral ========== 
-#define AT91C_SSC_PTCR            (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TNPR            (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_RNPR            (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TPR             (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_RPR             (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_PTSR            (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-#define AT91C_SSC_TNCR            (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RNCR            (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TCR             (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR             (0xFFFD4104) // (PDC_SSC) Receive Counter Register
-// ========== Register definition for SSC peripheral ========== 
-#define AT91C_SSC_RFMR            (0xFFFD4014) // (SSC) Receive Frame Mode Register
-#define AT91C_SSC_CMR             (0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_IDR             (0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_SR              (0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_RC0R            (0xFFFD4038) // (SSC) Receive Compare 0 Register
-#define AT91C_SSC_RSHR            (0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_RHR             (0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_TCMR            (0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_RCMR            (0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_CR              (0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR             (0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_IER             (0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_RC1R            (0xFFFD403C) // (SSC) Receive Compare 1 Register
-#define AT91C_SSC_TSHR            (0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_THR             (0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_TFMR            (0xFFFD401C) // (SSC) Transmit Frame Mode Register
-// ========== Register definition for PDC_US1 peripheral ========== 
-#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
-// ========== Register definition for US1 peripheral ========== 
-#define AT91C_US1_XXR             (0xFFFC4048) // (US1) XON_XOFF Register
-#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ========== 
-#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
-// ========== Register definition for US0 peripheral ========== 
-#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_XXR             (0xFFFC0048) // (US0) XON_XOFF Register
-#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
-#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
-// ========== Register definition for TWI peripheral ========== 
-#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
-#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_SMR             (0xFFFB8008) // (TWI) Slave Mode Register
-#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
-// ========== Register definition for TC2 peripheral ========== 
-#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
-#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
-// ========== Register definition for TC1 peripheral ========== 
-#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
-#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
-// ========== Register definition for TC0 peripheral ========== 
-#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
-#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
-// ========== Register definition for TCB peripheral ========== 
-#define AT91C_TCB_BMR             (0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR             (0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for PWMC_CH3 peripheral ========== 
-#define AT91C_CH3_CUPDR           (0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_CH3_CPRDR           (0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_CH3_CMR             (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-#define AT91C_CH3_Reserved        (0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_CH3_CCNTR           (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_CH3_CDTYR           (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH2 peripheral ========== 
-#define AT91C_CH2_CUPDR           (0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_CH2_CPRDR           (0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_CH2_CMR             (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_CH2_Reserved        (0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_CH2_CCNTR           (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_CH2_CDTYR           (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ========== 
-#define AT91C_CH1_CUPDR           (0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_CH1_CPRDR           (0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_CH1_CMR             (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-#define AT91C_CH1_Reserved        (0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_CH1_CCNTR           (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_CH1_CDTYR           (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH0 peripheral ========== 
-#define AT91C_CH0_CUPDR           (0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_CH0_CPRDR           (0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_CH0_CMR             (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_CH0_Reserved        (0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_CH0_CCNTR           (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-#define AT91C_CH0_CDTYR           (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-// ========== Register definition for PWMC peripheral ========== 
-#define AT91C_PWMC_VR             (0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR            (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_IDR            (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_SR             (0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_ENA            (0xFFFCC004) // (PWMC) PWMC Enable Register
-#define AT91C_PWMC_IMR            (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR             (0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_DIS            (0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER            (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-// ========== Register definition for UDP peripheral ========== 
-#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
-#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_PWM0            (AT91C_PIO_PA0) //  PWM Channel 0
-#define AT91C_PA0_TIOA0           (AT91C_PIO_PA0) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_PWM1            (AT91C_PIO_PA1) //  PWM Channel 1
-#define AT91C_PA1_TIOB0           (AT91C_PIO_PA1) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_DTXD           (AT91C_PIO_PA10) //  DBGU Debug Transmit Data
-#define AT91C_PA10_NPCS2          (AT91C_PIO_PA10) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_NPCS0          (AT91C_PIO_PA11) //  SPI Peripheral Chip Select 0
-#define AT91C_PA11_PWM0           (AT91C_PIO_PA11) //  PWM Channel 0
-#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_MISO           (AT91C_PIO_PA12) //  SPI Master In Slave
-#define AT91C_PA12_PWM1           (AT91C_PIO_PA12) //  PWM Channel 1
-#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_MOSI           (AT91C_PIO_PA13) //  SPI Master Out Slave
-#define AT91C_PA13_PWM2           (AT91C_PIO_PA13) //  PWM Channel 2
-#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_SPCK           (AT91C_PIO_PA14) //  SPI Serial Clock
-#define AT91C_PA14_PWM3           (AT91C_PIO_PA14) //  PWM Channel 3
-#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_TF             (AT91C_PIO_PA15) //  SSC Transmit Frame Sync
-#define AT91C_PA15_TIOA1          (AT91C_PIO_PA15) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_TK             (AT91C_PIO_PA16) //  SSC Transmit Clock
-#define AT91C_PA16_TIOB1          (AT91C_PIO_PA16) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_TD             (AT91C_PIO_PA17) //  SSC Transmit data
-#define AT91C_PA17_PCK1           (AT91C_PIO_PA17) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_RD             (AT91C_PIO_PA18) //  SSC Receive Data
-#define AT91C_PA18_PCK2           (AT91C_PIO_PA18) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_RK             (AT91C_PIO_PA19) //  SSC Receive Clock
-#define AT91C_PA19_FIQ            (AT91C_PIO_PA19) //  AIC Fast Interrupt Input
-#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_PWM2            (AT91C_PIO_PA2) //  PWM Channel 2
-#define AT91C_PA2_SCK0            (AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_RF             (AT91C_PIO_PA20) //  SSC Receive Frame Sync
-#define AT91C_PA20_IRQ0           (AT91C_PIO_PA20) //  External Interrupt 0
-#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_RXD1           (AT91C_PIO_PA21) //  USART 1 Receive Data
-#define AT91C_PA21_PCK1           (AT91C_PIO_PA21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TXD1           (AT91C_PIO_PA22) //  USART 1 Transmit Data
-#define AT91C_PA22_NPCS3          (AT91C_PIO_PA22) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_SCK1           (AT91C_PIO_PA23) //  USART 1 Serial Clock
-#define AT91C_PA23_PWM0           (AT91C_PIO_PA23) //  PWM Channel 0
-#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RTS1           (AT91C_PIO_PA24) //  USART 1 Ready To Send
-#define AT91C_PA24_PWM1           (AT91C_PIO_PA24) //  PWM Channel 1
-#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_CTS1           (AT91C_PIO_PA25) //  USART 1 Clear To Send
-#define AT91C_PA25_PWM2           (AT91C_PIO_PA25) //  PWM Channel 2
-#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_DCD1           (AT91C_PIO_PA26) //  USART 1 Data Carrier Detect
-#define AT91C_PA26_TIOA2          (AT91C_PIO_PA26) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DTR1           (AT91C_PIO_PA27) //  USART 1 Data Terminal ready
-#define AT91C_PA27_TIOB2          (AT91C_PIO_PA27) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DSR1           (AT91C_PIO_PA28) //  USART 1 Data Set ready
-#define AT91C_PA28_TCLK1          (AT91C_PIO_PA28) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_RI1            (AT91C_PIO_PA29) //  USART 1 Ring Indicator
-#define AT91C_PA29_TCLK2          (AT91C_PIO_PA29) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_TWD             (AT91C_PIO_PA3) //  TWI Two-wire Serial Data
-#define AT91C_PA3_NPCS3           (AT91C_PIO_PA3) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ1           (AT91C_PIO_PA30) //  External Interrupt 1
-#define AT91C_PA30_NPCS2          (AT91C_PIO_PA30) //  SPI Peripheral Chip Select 2
-#define AT91C_PIO_PA31            (1 << 31) // Pin Controlled by PA31
-#define AT91C_PA31_NPCS1          (AT91C_PIO_PA31) //  SPI Peripheral Chip Select 1
-#define AT91C_PA31_PCK2           (AT91C_PIO_PA31) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_TWCK            (AT91C_PIO_PA4) //  TWI Two-wire Serial Clock
-#define AT91C_PA4_TCLK0           (AT91C_PIO_PA4) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD0            (AT91C_PIO_PA5) //  USART 0 Receive Data
-#define AT91C_PA5_NPCS3           (AT91C_PIO_PA5) //  SPI Peripheral Chip Select 3
-#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD0            (AT91C_PIO_PA6) //  USART 0 Transmit Data
-#define AT91C_PA6_PCK0            (AT91C_PIO_PA6) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_RTS0            (AT91C_PIO_PA7) //  USART 0 Ready To Send
-#define AT91C_PA7_PWM3            (AT91C_PIO_PA7) //  PWM Channel 3
-#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_CTS0            (AT91C_PIO_PA8) //  USART 0 Clear To Send
-#define AT91C_PA8_ADTRG           (AT91C_PIO_PA8) //  ADC External Trigger
-#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_DRXD            (AT91C_PIO_PA9) //  DBGU Debug Receive Data
-#define AT91C_PA9_NPCS1           (AT91C_PIO_PA9) //  SPI Peripheral Chip Select 1
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS              ( 1) // System Peripheral
-#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller
-#define AT91C_ID_3_Reserved       ( 3) // Reserved
-#define AT91C_ID_ADC              ( 4) // Analog-to-Digital Converter
-#define AT91C_ID_SPI              ( 5) // Serial Peripheral Interface
-#define AT91C_ID_US0              ( 6) // USART 0
-#define AT91C_ID_US1              ( 7) // USART 1
-#define AT91C_ID_SSC              ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI              ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC             (10) // PWM Controller
-#define AT91C_ID_UDP              (11) // USB Device Port
-#define AT91C_ID_TC0              (12) // Timer Counter 0
-#define AT91C_ID_TC1              (13) // Timer Counter 1
-#define AT91C_ID_TC2              (14) // Timer Counter 2
-#define AT91C_ID_15_Reserved      (15) // Reserved
-#define AT91C_ID_16_Reserved      (16) // Reserved
-#define AT91C_ID_17_Reserved      (17) // Reserved
-#define AT91C_ID_18_Reserved      (18) // Reserved
-#define AT91C_ID_19_Reserved      (19) // Reserved
-#define AT91C_ID_20_Reserved      (20) // Reserved
-#define AT91C_ID_21_Reserved      (21) // Reserved
-#define AT91C_ID_22_Reserved      (22) // Reserved
-#define AT91C_ID_23_Reserved      (23) // Reserved
-#define AT91C_ID_24_Reserved      (24) // Reserved
-#define AT91C_ID_25_Reserved      (25) // Reserved
-#define AT91C_ID_26_Reserved      (26) // Reserved
-#define AT91C_ID_27_Reserved      (27) // Reserved
-#define AT91C_ID_28_Reserved      (28) // Reserved
-#define AT91C_ID_29_Reserved      (29) // Reserved
-#define AT91C_ID_IRQ0             (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1             (31) // Advanced Interrupt Controller (IRQ1)
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_BASE_SYSC           (0xFFFFF000) // (SYSC) Base Address
-#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI        (0xFFFE0100) // (PDC_SPI) Base Address
-#define AT91C_BASE_SPI            (0xFFFE0000) // (SPI) Base Address
-#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7S64
-// *****************************************************************************
-#define AT91C_ISRAM	              (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	         (0x00004000) // Internal SRAM size in byte (16 Kbyte)
-#define AT91C_IFLASH	             (0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE	        (0x00010000) // Internal ROM size in byte (64 Kbyte)
-
-
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
deleted file mode 100755
index ee0cbae..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128.h
+++ /dev/null
@@ -1,2715 +0,0 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7X128.h
-// Object              : AT91SAM7X128 definitions
-// Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
-// 
-// CVS Reference       : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
-// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-//  ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X128_H
-#define AT91SAM7X128_H
-
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	// 
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	// 
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	// 
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	// 
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	// 
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	// 
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	// 
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	// 
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[85]; 	// 
-	AT91_REG	 PIOB_PER; 	// PIO Enable Register
-	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOB_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved13[1]; 	// 
-	AT91_REG	 PIOB_OER; 	// Output Enable Register
-	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOB_OSR; 	// Output Status Register
-	AT91_REG	 Reserved14[1]; 	// 
-	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved15[1]; 	// 
-	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved16[1]; 	// 
-	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved17[1]; 	// 
-	AT91_REG	 PIOB_ASR; 	// Select A Register
-	AT91_REG	 PIOB_BSR; 	// Select B Register
-	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved18[9]; 	// 
-	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved19[341]; 	// 
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved20[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved21[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved22[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved23[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved24[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved25[36]; 	// 
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved26[5]; 	// 
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved27[5]; 	// 
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	// 
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	// 
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	// 
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_VREG {
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
-#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[21]; 	// 
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	// 
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	// 
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	// 
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	// 
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	// 
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	// 
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
-
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
-#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	// 
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
-#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[2]; 	// 
-	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[3]; 	// 
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
-#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
-#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
-#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	// 
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN_MB {
-	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
-	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
-	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
-	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
-	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
-	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
-	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
-	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
-#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
-#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
-#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
-#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN {
-	AT91_REG	 CAN_MR; 	// Mode Register
-	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
-	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
-	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
-	AT91_REG	 CAN_SR; 	// Status Register
-	AT91_REG	 CAN_BR; 	// Baudrate Register
-	AT91_REG	 CAN_TIM; 	// Timer Register
-	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
-	AT91_REG	 CAN_ECR; 	// Error Counter Register
-	AT91_REG	 CAN_TCR; 	// Transfer Command Register
-	AT91_REG	 CAN_ACR; 	// Abort Command Register
-	AT91_REG	 Reserved0[52]; 	// 
-	AT91_REG	 CAN_VR; 	// Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
-	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
-	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
-	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
-	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
-	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
-	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
-	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
-	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
-	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
-	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
-	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
-	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
-	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
-	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
-	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
-#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
-#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
-#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
-#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
-#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
-#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
-#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-typedef struct _AT91S_EMAC {
-	AT91_REG	 EMAC_NCR; 	// Network Control Register
-	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
-	AT91_REG	 EMAC_NSR; 	// Network Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
-	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
-	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
-	AT91_REG	 EMAC_RSR; 	// Receive Status Register
-	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
-	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
-	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
-	AT91_REG	 EMAC_PTR; 	// Pause Time Register
-	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
-	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
-	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
-	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
-	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
-	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
-	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
-	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
-	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
-	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
-	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
-	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
-	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
-	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
-	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
-	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
-	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
-	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
-	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
-	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
-	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
-	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
-	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
-	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
-	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
-	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
-	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
-	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
-	AT91_REG	 Reserved1[13]; 	// 
-	AT91_REG	 EMAC_REV; 	// Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
-#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
-#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
-#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
-#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
-#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
-#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
-#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
-#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
-#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
-#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
-#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
-#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
-#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
-#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
-#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
-#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
-#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
-#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
-#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
-#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
-#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
-#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
-#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
-#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
-#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
-#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
-#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
-#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
-#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
-#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
-#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
-#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
-#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
-#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
-#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
-#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
-#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
-#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
-#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
-#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
-#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	// 
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_AES {
-	AT91_REG	 AES_CR; 	// Control Register
-	AT91_REG	 AES_MR; 	// Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AES_IER; 	// Interrupt Enable Register
-	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
-	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AES_ISR; 	// Interrupt Status Register
-	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
-	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
-	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
-	AT91_REG	 Reserved2[35]; 	// 
-	AT91_REG	 AES_VR; 	// AES Version Register
-	AT91_REG	 AES_RPR; 	// Receive Pointer Register
-	AT91_REG	 AES_RCR; 	// Receive Counter Register
-	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
-	AT91_REG	 AES_TCR; 	// Transmit Counter Register
-	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
-} AT91S_AES, *AT91PS_AES;
-
-// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
-#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
-#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
-#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
-#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
-#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
-#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
-#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
-#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
-#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
-#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
-#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_TDES {
-	AT91_REG	 TDES_CR; 	// Control Register
-	AT91_REG	 TDES_MR; 	// Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
-	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
-	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
-	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
-	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
-	AT91_REG	 Reserved2[2]; 	// 
-	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
-	AT91_REG	 Reserved3[2]; 	// 
-	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
-	AT91_REG	 Reserved4[37]; 	// 
-	AT91_REG	 TDES_VR; 	// TDES Version Register
-	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
-	AT91_REG	 TDES_RCR; 	// Receive Counter Register
-	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
-	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
-} AT91S_TDES, *AT91PS_TDES;
-
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
-#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
-#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
-#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
-#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
-#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
-#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
-#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
-#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
-#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ========== 
-// ========== Register definition for AIC peripheral ========== 
-#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ========== 
-#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ========== 
-#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ========== 
-#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ========== 
-#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ========== 
-#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ========== 
-#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ========== 
-#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ========== 
-#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ========== 
-#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ========== 
-#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ========== 
-#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ========== 
-#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ========== 
-#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ========== 
-#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ========== 
-#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ========== 
-#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ========== 
-#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ========== 
-#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ========== 
-#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ========== 
-#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ========== 
-#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ========== 
-#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ========== 
-#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ========== 
-#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ========== 
-#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ========== 
-#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ========== 
-#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ========== 
-#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ========== 
-#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ========== 
-#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ========== 
-#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ========== 
-#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ========== 
-#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ========== 
-#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ========== 
-#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ========== 
-#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ========== 
-#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ========== 
-#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ========== 
-#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ========== 
-#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ========== 
-#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ========== 
-#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ========== 
-#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ========== 
-#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ========== 
-#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ========== 
-#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ========== 
-#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ========== 
-#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ========== 
-#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
-#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
-#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
-#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
-#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
-#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
-#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
-#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
-#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00008000) // Internal SRAM size in byte (32 Kbyte)
-#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00020000) // Internal ROM size in byte (128 Kbyte)
-
-#endif
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
deleted file mode 100755
index a84760c..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X128_inc.h
+++ /dev/null
@@ -1,2446 +0,0 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7X128.h
-// Object              : AT91SAM7X128 definitions
-// Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
-// 
-// CVS Reference       : /AT91SAM7X128.pl/1.14/Tue May 10 12:12:05 2005//
-// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-//  ----------------------------------------------------------------------------
-
-// Hardware register definition
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-// *** Register offset in AT91S_AIC structure ***
-#define AIC_SMR         ( 0) // Source Mode Register
-#define AIC_SVR         (128) // Source Vector Register
-#define AIC_IVR         (256) // IRQ Vector Register
-#define AIC_FVR         (260) // FIQ Vector Register
-#define AIC_ISR         (264) // Interrupt Status Register
-#define AIC_IPR         (268) // Interrupt Pending Register
-#define AIC_IMR         (272) // Interrupt Mask Register
-#define AIC_CISR        (276) // Core Interrupt Status Register
-#define AIC_IECR        (288) // Interrupt Enable Command Register
-#define AIC_IDCR        (292) // Interrupt Disable Command Register
-#define AIC_ICCR        (296) // Interrupt Clear Command Register
-#define AIC_ISCR        (300) // Interrupt Set Command Register
-#define AIC_EOICR       (304) // End of Interrupt Command Register
-#define AIC_SPU         (308) // Spurious Vector Register
-#define AIC_DCR         (312) // Debug Control Register (Protect)
-#define AIC_FFER        (320) // Fast Forcing Enable Register
-#define AIC_FFDR        (324) // Fast Forcing Disable Register
-#define AIC_FFSR        (328) // Fast Forcing Status Register
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-// *** Register offset in AT91S_PDC structure ***
-#define PDC_RPR         ( 0) // Receive Pointer Register
-#define PDC_RCR         ( 4) // Receive Counter Register
-#define PDC_TPR         ( 8) // Transmit Pointer Register
-#define PDC_TCR         (12) // Transmit Counter Register
-#define PDC_RNPR        (16) // Receive Next Pointer Register
-#define PDC_RNCR        (20) // Receive Next Counter Register
-#define PDC_TNPR        (24) // Transmit Next Pointer Register
-#define PDC_TNCR        (28) // Transmit Next Counter Register
-#define PDC_PTCR        (32) // PDC Transfer Control Register
-#define PDC_PTSR        (36) // PDC Transfer Status Register
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-// *** Register offset in AT91S_DBGU structure ***
-#define DBGU_CR         ( 0) // Control Register
-#define DBGU_MR         ( 4) // Mode Register
-#define DBGU_IER        ( 8) // Interrupt Enable Register
-#define DBGU_IDR        (12) // Interrupt Disable Register
-#define DBGU_IMR        (16) // Interrupt Mask Register
-#define DBGU_CSR        (20) // Channel Status Register
-#define DBGU_RHR        (24) // Receiver Holding Register
-#define DBGU_THR        (28) // Transmitter Holding Register
-#define DBGU_BRGR       (32) // Baud Rate Generator Register
-#define DBGU_CIDR       (64) // Chip ID Register
-#define DBGU_EXID       (68) // Chip ID Extension Register
-#define DBGU_FNTR       (72) // Force NTRST Register
-#define DBGU_RPR        (256) // Receive Pointer Register
-#define DBGU_RCR        (260) // Receive Counter Register
-#define DBGU_TPR        (264) // Transmit Pointer Register
-#define DBGU_TCR        (268) // Transmit Counter Register
-#define DBGU_RNPR       (272) // Receive Next Pointer Register
-#define DBGU_RNCR       (276) // Receive Next Counter Register
-#define DBGU_TNPR       (280) // Transmit Next Pointer Register
-#define DBGU_TNCR       (284) // Transmit Next Counter Register
-#define DBGU_PTCR       (288) // PDC Transfer Control Register
-#define DBGU_PTSR       (292) // PDC Transfer Status Register
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA           (0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PIO structure ***
-#define PIO_PER         ( 0) // PIO Enable Register
-#define PIO_PDR         ( 4) // PIO Disable Register
-#define PIO_PSR         ( 8) // PIO Status Register
-#define PIO_OER         (16) // Output Enable Register
-#define PIO_ODR         (20) // Output Disable Registerr
-#define PIO_OSR         (24) // Output Status Register
-#define PIO_IFER        (32) // Input Filter Enable Register
-#define PIO_IFDR        (36) // Input Filter Disable Register
-#define PIO_IFSR        (40) // Input Filter Status Register
-#define PIO_SODR        (48) // Set Output Data Register
-#define PIO_CODR        (52) // Clear Output Data Register
-#define PIO_ODSR        (56) // Output Data Status Register
-#define PIO_PDSR        (60) // Pin Data Status Register
-#define PIO_IER         (64) // Interrupt Enable Register
-#define PIO_IDR         (68) // Interrupt Disable Register
-#define PIO_IMR         (72) // Interrupt Mask Register
-#define PIO_ISR         (76) // Interrupt Status Register
-#define PIO_MDER        (80) // Multi-driver Enable Register
-#define PIO_MDDR        (84) // Multi-driver Disable Register
-#define PIO_MDSR        (88) // Multi-driver Status Register
-#define PIO_PPUDR       (96) // Pull-up Disable Register
-#define PIO_PPUER       (100) // Pull-up Enable Register
-#define PIO_PPUSR       (104) // Pull-up Status Register
-#define PIO_ASR         (112) // Select A Register
-#define PIO_BSR         (116) // Select B Register
-#define PIO_ABSR        (120) // AB Select Status Register
-#define PIO_OWER        (160) // Output Write Enable Register
-#define PIO_OWDR        (164) // Output Write Disable Register
-#define PIO_OWSR        (168) // Output Write Status Register
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-// *** Register offset in AT91S_CKGR structure ***
-#define CKGR_MOR        ( 0) // Main Oscillator Register
-#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
-#define CKGR_PLLR       (12) // PLL Register
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PMC structure ***
-#define PMC_SCER        ( 0) // System Clock Enable Register
-#define PMC_SCDR        ( 4) // System Clock Disable Register
-#define PMC_SCSR        ( 8) // System Clock Status Register
-#define PMC_PCER        (16) // Peripheral Clock Enable Register
-#define PMC_PCDR        (20) // Peripheral Clock Disable Register
-#define PMC_PCSR        (24) // Peripheral Clock Status Register
-#define PMC_MOR         (32) // Main Oscillator Register
-#define PMC_MCFR        (36) // Main Clock  Frequency Register
-#define PMC_PLLR        (44) // PLL Register
-#define PMC_MCKR        (48) // Master Clock Register
-#define PMC_PCKR        (64) // Programmable Clock Register
-#define PMC_IER         (96) // Interrupt Enable Register
-#define PMC_IDR         (100) // Interrupt Disable Register
-#define PMC_SR          (104) // Status Register
-#define PMC_IMR         (108) // Interrupt Mask Register
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_RSTC structure ***
-#define RSTC_RCR        ( 0) // Reset Control Register
-#define RSTC_RSR        ( 4) // Reset Status Register
-#define RSTC_RMR        ( 8) // Reset Mode Register
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-#define AT91C_RSTC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST         (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY            (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-#define AT91C_RSTC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS         (0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-#define AT91C_RSTC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN         (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_RTTC structure ***
-#define RTTC_RTMR       ( 0) // Real-time Mode Register
-#define RTTC_RTAR       ( 4) // Real-time Alarm Register
-#define RTTC_RTVR       ( 8) // Real-time Value Register
-#define RTTC_RTSR       (12) // Real-time Status Register
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-#define AT91C_RTTC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-#define AT91C_RTTC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-#define AT91C_RTTC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-#define AT91C_RTTC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PITC structure ***
-#define PITC_PIMR       ( 0) // Period Interval Mode Register
-#define PITC_PISR       ( 4) // Period Interval Status Register
-#define PITC_PIVR       ( 8) // Period Interval Value Register
-#define PITC_PIIR       (12) // Period Interval Image Register
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-#define AT91C_PITC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-#define AT91C_PITC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-#define AT91C_PITC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_WDTC structure ***
-#define WDTC_WDCR       ( 0) // Watchdog Control Register
-#define WDTC_WDMR       ( 4) // Watchdog Mode Register
-#define WDTC_WDSR       ( 8) // Watchdog Status Register
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-#define AT91C_WDTC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY            (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-#define AT91C_WDTC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-#define AT91C_WDTC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_VREG structure ***
-#define VREG_MR         ( 0) // Voltage Regulator Mode Register
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
-#define AT91C_VREG_PSTDBY         (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_MC structure ***
-#define MC_RCR          ( 0) // MC Remap Control Register
-#define MC_ASR          ( 4) // MC Abort Status Register
-#define MC_AASR         ( 8) // MC Abort Address Status Register
-#define MC_FMR          (96) // MC Flash Mode Register
-#define MC_FCR          (100) // MC Flash Command Register
-#define MC_FSR          (104) // MC Flash Status Register
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SPI structure ***
-#define SPI_CR          ( 0) // Control Register
-#define SPI_MR          ( 4) // Mode Register
-#define SPI_RDR         ( 8) // Receive Data Register
-#define SPI_TDR         (12) // Transmit Data Register
-#define SPI_SR          (16) // Status Register
-#define SPI_IER         (20) // Interrupt Enable Register
-#define SPI_IDR         (24) // Interrupt Disable Register
-#define SPI_IMR         (28) // Interrupt Mask Register
-#define SPI_CSR         (48) // Chip Select Register
-#define SPI_RPR         (256) // Receive Pointer Register
-#define SPI_RCR         (260) // Receive Counter Register
-#define SPI_TPR         (264) // Transmit Pointer Register
-#define SPI_TCR         (268) // Transmit Counter Register
-#define SPI_RNPR        (272) // Receive Next Pointer Register
-#define SPI_RNCR        (276) // Receive Next Counter Register
-#define SPI_TNPR        (280) // Transmit Next Pointer Register
-#define SPI_TNCR        (284) // Transmit Next Counter Register
-#define SPI_PTCR        (288) // PDC Transfer Control Register
-#define SPI_PTSR        (292) // PDC Transfer Status Register
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT           (0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-// *** Register offset in AT91S_USART structure ***
-#define US_CR           ( 0) // Control Register
-#define US_MR           ( 4) // Mode Register
-#define US_IER          ( 8) // Interrupt Enable Register
-#define US_IDR          (12) // Interrupt Disable Register
-#define US_IMR          (16) // Interrupt Mask Register
-#define US_CSR          (20) // Channel Status Register
-#define US_RHR          (24) // Receiver Holding Register
-#define US_THR          (28) // Transmitter Holding Register
-#define US_BRGR         (32) // Baud Rate Generator Register
-#define US_RTOR         (36) // Receiver Time-out Register
-#define US_TTGR         (40) // Transmitter Time-guard Register
-#define US_FIDI         (64) // FI_DI_Ratio Register
-#define US_NER          (68) // Nb Errors Register
-#define US_IF           (76) // IRDA_FILTER Register
-#define US_RPR          (256) // Receive Pointer Register
-#define US_RCR          (260) // Receive Counter Register
-#define US_TPR          (264) // Transmit Pointer Register
-#define US_TCR          (268) // Transmit Counter Register
-#define US_RNPR         (272) // Receive Next Pointer Register
-#define US_RNCR         (276) // Receive Next Counter Register
-#define US_TNPR         (280) // Transmit Next Pointer Register
-#define US_TNCR         (284) // Transmit Next Counter Register
-#define US_PTCR         (288) // PDC Transfer Control Register
-#define US_PTSR         (292) // PDC Transfer Status Register
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SSC structure ***
-#define SSC_CR          ( 0) // Control Register
-#define SSC_CMR         ( 4) // Clock Mode Register
-#define SSC_RCMR        (16) // Receive Clock ModeRegister
-#define SSC_RFMR        (20) // Receive Frame Mode Register
-#define SSC_TCMR        (24) // Transmit Clock Mode Register
-#define SSC_TFMR        (28) // Transmit Frame Mode Register
-#define SSC_RHR         (32) // Receive Holding Register
-#define SSC_THR         (36) // Transmit Holding Register
-#define SSC_RSHR        (48) // Receive Sync Holding Register
-#define SSC_TSHR        (52) // Transmit Sync Holding Register
-#define SSC_SR          (64) // Status Register
-#define SSC_IER         (68) // Interrupt Enable Register
-#define SSC_IDR         (72) // Interrupt Disable Register
-#define SSC_IMR         (76) // Interrupt Mask Register
-#define SSC_RPR         (256) // Receive Pointer Register
-#define SSC_RCR         (260) // Receive Counter Register
-#define SSC_TPR         (264) // Transmit Pointer Register
-#define SSC_TCR         (268) // Transmit Counter Register
-#define SSC_RNPR        (272) // Receive Next Pointer Register
-#define SSC_RNCR        (276) // Receive Next Counter Register
-#define SSC_TNPR        (280) // Transmit Next Pointer Register
-#define SSC_TNCR        (284) // Transmit Next Counter Register
-#define SSC_PTCR        (288) // PDC Transfer Control Register
-#define SSC_PTSR        (292) // PDC Transfer Status Register
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TWI structure ***
-#define TWI_CR          ( 0) // Control Register
-#define TWI_MMR         ( 4) // Master Mode Register
-#define TWI_IADR        (12) // Internal Address Register
-#define TWI_CWGR        (16) // Clock Waveform Generator Register
-#define TWI_SR          (32) // Status Register
-#define TWI_IER         (36) // Interrupt Enable Register
-#define TWI_IDR         (40) // Interrupt Disable Register
-#define TWI_IMR         (44) // Interrupt Mask Register
-#define TWI_RHR         (48) // Receive Holding Register
-#define TWI_THR         (52) // Transmit Holding Register
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PWMC_CH structure ***
-#define PWMC_CMR        ( 0) // Channel Mode Register
-#define PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
-#define PWMC_CPRDR      ( 8) // Channel Period Register
-#define PWMC_CCNTR      (12) // Channel Counter Register
-#define PWMC_CUPDR      (16) // Channel Update Register
-#define PWMC_Reserved   (20) // Reserved
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) 
-#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PWMC structure ***
-#define PWMC_MR         ( 0) // PWMC Mode Register
-#define PWMC_ENA        ( 4) // PWMC Enable Register
-#define PWMC_DIS        ( 8) // PWMC Disable Register
-#define PWMC_SR         (12) // PWMC Status Register
-#define PWMC_IER        (16) // PWMC Interrupt Enable Register
-#define PWMC_IDR        (20) // PWMC Interrupt Disable Register
-#define PWMC_IMR        (24) // PWMC Interrupt Mask Register
-#define PWMC_ISR        (28) // PWMC Interrupt Status Register
-#define PWMC_VR         (252) // PWMC Version Register
-#define PWMC_CH         (512) // PWMC Channel
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) 
-#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) 
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-// *** Register offset in AT91S_UDP structure ***
-#define UDP_NUM         ( 0) // Frame Number Register
-#define UDP_GLBSTATE    ( 4) // Global State Register
-#define UDP_FADDR       ( 8) // Function Address Register
-#define UDP_IER         (16) // Interrupt Enable Register
-#define UDP_IDR         (20) // Interrupt Disable Register
-#define UDP_IMR         (24) // Interrupt Mask Register
-#define UDP_ISR         (28) // Interrupt Status Register
-#define UDP_ICR         (32) // Interrupt Clear Register
-#define UDP_RSTEP       (40) // Reset Endpoint Register
-#define UDP_CSR         (48) // Endpoint Control and Status Register
-#define UDP_FDR         (80) // Endpoint FIFO Data Register
-#define UDP_TXVC        (116) // Transceiver Control Register
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR             (0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE          (0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
-#define AT91C_UDP_TXVDIS          (0x1 <<  8) // (UDP) 
-#define AT91C_UDP_PUON            (0x1 <<  9) // (UDP) Pull-up ON
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TC structure ***
-#define TC_CCR          ( 0) // Channel Control Register
-#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (16) // Counter Value
-#define TC_RA           (20) // Register A
-#define TC_RB           (24) // Register B
-#define TC_RC           (28) // Register C
-#define TC_SR           (32) // Status Register
-#define TC_IER          (36) // Interrupt Enable Register
-#define TC_IDR          (40) // Interrupt Disable Register
-#define TC_IMR          (44) // Interrupt Mask Register
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI             (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST            (0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS           (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG          (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG           (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE             (0x1 << 15) // (TC) 
-#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA             (0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB             (0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS            (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA           (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TCB structure ***
-#define TCB_TC0         ( 0) // TC Channel 0
-#define TCB_TC1         (64) // TC Channel 1
-#define TCB_TC2         (128) // TC Channel 2
-#define TCB_BCR         (192) // TC Block Control Register
-#define TCB_BMR         (196) // TC Block Mode Register
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-#define AT91C_TCB_TC0XC0S         (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S         (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S         (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-// *** Register offset in AT91S_CAN_MB structure ***
-#define CAN_MB_MMR      ( 0) // MailBox Mode Register
-#define CAN_MB_MAM      ( 4) // MailBox Acceptance Mask Register
-#define CAN_MB_MID      ( 8) // MailBox ID Register
-#define CAN_MB_MFID     (12) // MailBox Family ID Register
-#define CAN_MB_MSR      (16) // MailBox Status Register
-#define CAN_MB_MDL      (20) // MailBox Data Low Register
-#define CAN_MB_MDH      (24) // MailBox Data High Register
-#define CAN_MB_MCR      (28) // MailBox Control Register
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
-#define AT91C_CAN_MTIMEMARK       (0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR           (0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT             (0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define 	AT91C_CAN_MOT_DIS                  (0x0 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RX                   (0x1 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RXOVERWRITE          (0x2 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_TX                   (0x3 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_CONSUMER             (0x4 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_PRODUCER             (0x5 << 24) // (CAN_MB) 
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
-#define AT91C_CAN_MIDvB           (0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA           (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE            (0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
-#define AT91C_CAN_MTIMESTAMP      (0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC            (0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR            (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT            (0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY            (0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI             (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
-#define AT91C_CAN_MACR            (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR            (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-// *** Register offset in AT91S_CAN structure ***
-#define CAN_MR          ( 0) // Mode Register
-#define CAN_IER         ( 4) // Interrupt Enable Register
-#define CAN_IDR         ( 8) // Interrupt Disable Register
-#define CAN_IMR         (12) // Interrupt Mask Register
-#define CAN_SR          (16) // Status Register
-#define CAN_BR          (20) // Baudrate Register
-#define CAN_TIM         (24) // Timer Register
-#define CAN_TIMESTP     (28) // Time Stamp Register
-#define CAN_ECR         (32) // Error Counter Register
-#define CAN_TCR         (36) // Transfer Command Register
-#define CAN_ACR         (40) // Abort Command Register
-#define CAN_VR          (252) // Version Register
-#define CAN_MB0         (512) // CAN Mailbox 0
-#define CAN_MB1         (544) // CAN Mailbox 1
-#define CAN_MB2         (576) // CAN Mailbox 2
-#define CAN_MB3         (608) // CAN Mailbox 3
-#define CAN_MB4         (640) // CAN Mailbox 4
-#define CAN_MB5         (672) // CAN Mailbox 5
-#define CAN_MB6         (704) // CAN Mailbox 6
-#define CAN_MB7         (736) // CAN Mailbox 7
-#define CAN_MB8         (768) // CAN Mailbox 8
-#define CAN_MB9         (800) // CAN Mailbox 9
-#define CAN_MB10        (832) // CAN Mailbox 10
-#define CAN_MB11        (864) // CAN Mailbox 11
-#define CAN_MB12        (896) // CAN Mailbox 12
-#define CAN_MB13        (928) // CAN Mailbox 13
-#define CAN_MB14        (960) // CAN Mailbox 14
-#define CAN_MB15        (992) // CAN Mailbox 15
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
-#define AT91C_CAN_CANEN           (0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM             (0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM             (0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL             (0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF            (0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM             (0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ          (0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT            (0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
-#define AT91C_CAN_MB0             (0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1             (0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2             (0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3             (0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4             (0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5             (0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6             (0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7             (0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8             (0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9             (0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10            (0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11            (0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12            (0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13            (0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14            (0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15            (0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA            (0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN            (0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP            (0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF            (0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP           (0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP          (0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF            (0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP            (0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR            (0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR            (0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR            (0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR            (0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR            (0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
-#define AT91C_CAN_RBSY            (0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY            (0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY            (0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
-#define AT91C_CAN_PHASE2          (0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1          (0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG          (0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC            (0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP             (0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP             (0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
-#define AT91C_CAN_TIMER           (0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
-#define AT91C_CAN_REC             (0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC             (0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
-#define AT91C_CAN_TIMRST          (0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-// *** Register offset in AT91S_EMAC structure ***
-#define EMAC_NCR        ( 0) // Network Control Register
-#define EMAC_NCFGR      ( 4) // Network Configuration Register
-#define EMAC_NSR        ( 8) // Network Status Register
-#define EMAC_TSR        (20) // Transmit Status Register
-#define EMAC_RBQP       (24) // Receive Buffer Queue Pointer
-#define EMAC_TBQP       (28) // Transmit Buffer Queue Pointer
-#define EMAC_RSR        (32) // Receive Status Register
-#define EMAC_ISR        (36) // Interrupt Status Register
-#define EMAC_IER        (40) // Interrupt Enable Register
-#define EMAC_IDR        (44) // Interrupt Disable Register
-#define EMAC_IMR        (48) // Interrupt Mask Register
-#define EMAC_MAN        (52) // PHY Maintenance Register
-#define EMAC_PTR        (56) // Pause Time Register
-#define EMAC_PFR        (60) // Pause Frames received Register
-#define EMAC_FTO        (64) // Frames Transmitted OK Register
-#define EMAC_SCF        (68) // Single Collision Frame Register
-#define EMAC_MCF        (72) // Multiple Collision Frame Register
-#define EMAC_FRO        (76) // Frames Received OK Register
-#define EMAC_FCSE       (80) // Frame Check Sequence Error Register
-#define EMAC_ALE        (84) // Alignment Error Register
-#define EMAC_DTF        (88) // Deferred Transmission Frame Register
-#define EMAC_LCOL       (92) // Late Collision Register
-#define EMAC_ECOL       (96) // Excessive Collision Register
-#define EMAC_TUND       (100) // Transmit Underrun Error Register
-#define EMAC_CSE        (104) // Carrier Sense Error Register
-#define EMAC_RRE        (108) // Receive Ressource Error Register
-#define EMAC_ROV        (112) // Receive Overrun Errors Register
-#define EMAC_RSE        (116) // Receive Symbol Errors Register
-#define EMAC_ELE        (120) // Excessive Length Errors Register
-#define EMAC_RJA        (124) // Receive Jabbers Register
-#define EMAC_USF        (128) // Undersize Frames Register
-#define EMAC_STE        (132) // SQE Test Error Register
-#define EMAC_RLE        (136) // Receive Length Field Mismatch Register
-#define EMAC_TPF        (140) // Transmitted Pause Frames Register
-#define EMAC_HRB        (144) // Hash Address Bottom[31:0]
-#define EMAC_HRT        (148) // Hash Address Top[63:32]
-#define EMAC_SA1L       (152) // Specific Address 1 Bottom, First 4 bytes
-#define EMAC_SA1H       (156) // Specific Address 1 Top, Last 2 bytes
-#define EMAC_SA2L       (160) // Specific Address 2 Bottom, First 4 bytes
-#define EMAC_SA2H       (164) // Specific Address 2 Top, Last 2 bytes
-#define EMAC_SA3L       (168) // Specific Address 3 Bottom, First 4 bytes
-#define EMAC_SA3H       (172) // Specific Address 3 Top, Last 2 bytes
-#define EMAC_SA4L       (176) // Specific Address 4 Bottom, First 4 bytes
-#define EMAC_SA4H       (180) // Specific Address 4 Top, Last 2 bytes
-#define EMAC_TID        (184) // Type ID Checking Register
-#define EMAC_TPQ        (188) // Transmit Pause Quantum Register
-#define EMAC_USRIO      (192) // USER Input/Output Register
-#define EMAC_WOL        (196) // Wake On LAN Register
-#define EMAC_REV        (252) // Revision Register
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
-#define AT91C_EMAC_LB             (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB            (0x1 <<  1) // (EMAC) Loopback local. 
-#define AT91C_EMAC_RE             (0x1 <<  2) // (EMAC) Receive enable. 
-#define AT91C_EMAC_TE             (0x1 <<  3) // (EMAC) Transmit enable. 
-#define AT91C_EMAC_MPE            (0x1 <<  4) // (EMAC) Management port enable. 
-#define AT91C_EMAC_CLRSTAT        (0x1 <<  5) // (EMAC) Clear statistics registers. 
-#define AT91C_EMAC_INCSTAT        (0x1 <<  6) // (EMAC) Increment statistics registers. 
-#define AT91C_EMAC_WESTAT         (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
-#define AT91C_EMAC_BP             (0x1 <<  8) // (EMAC) Back pressure. 
-#define AT91C_EMAC_TSTART         (0x1 <<  9) // (EMAC) Start Transmission. 
-#define AT91C_EMAC_THALT          (0x1 << 10) // (EMAC) Transmission Halt. 
-#define AT91C_EMAC_TPFR           (0x1 << 11) // (EMAC) Transmit pause frame 
-#define AT91C_EMAC_TZQ            (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
-#define AT91C_EMAC_SPD            (0x1 <<  0) // (EMAC) Speed. 
-#define AT91C_EMAC_FD             (0x1 <<  1) // (EMAC) Full duplex. 
-#define AT91C_EMAC_JFRAME         (0x1 <<  3) // (EMAC) Jumbo Frames. 
-#define AT91C_EMAC_CAF            (0x1 <<  4) // (EMAC) Copy all frames. 
-#define AT91C_EMAC_NBC            (0x1 <<  5) // (EMAC) No broadcast. 
-#define AT91C_EMAC_MTI            (0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI            (0x1 <<  7) // (EMAC) Unicast hash enable. 
-#define AT91C_EMAC_BIG            (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
-#define AT91C_EMAC_EAE            (0x1 <<  9) // (EMAC) External address match enable. 
-#define AT91C_EMAC_CLK            (0x3 << 10) // (EMAC) 
-#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
-#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
-#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
-#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY            (0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PAE            (0x1 << 13) // (EMAC) 
-#define AT91C_EMAC_RBOF           (0x3 << 14) // (EMAC) 
-#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE           (0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS          (0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD          (0x1 << 18) // (EMAC) 
-#define AT91C_EMAC_IRXFCS         (0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
-#define AT91C_EMAC_LINKR          (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_MDIO           (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_IDLE           (0x1 <<  2) // (EMAC) 
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
-#define AT91C_EMAC_UBR            (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_COL            (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RLES           (0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TGO            (0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX            (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP           (0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_UND            (0x1 <<  6) // (EMAC) 
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-#define AT91C_EMAC_BNA            (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_REC            (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_OVR            (0x1 <<  2) // (EMAC) 
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-#define AT91C_EMAC_MFD            (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_RCOMP          (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RXUBR          (0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TXUBR          (0x1 <<  3) // (EMAC) 
-#define AT91C_EMAC_TUNDR          (0x1 <<  4) // (EMAC) 
-#define AT91C_EMAC_RLEX           (0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_TXERR          (0x1 <<  6) // (EMAC) 
-#define AT91C_EMAC_TCOMP          (0x1 <<  7) // (EMAC) 
-#define AT91C_EMAC_LINK           (0x1 <<  9) // (EMAC) 
-#define AT91C_EMAC_ROVR           (0x1 << 10) // (EMAC) 
-#define AT91C_EMAC_HRESP          (0x1 << 11) // (EMAC) 
-#define AT91C_EMAC_PFRE           (0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PTZ            (0x1 << 13) // (EMAC) 
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-#define AT91C_EMAC_DATA           (0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_CODE           (0x3 << 16) // (EMAC) 
-#define AT91C_EMAC_REGA           (0x1F << 18) // (EMAC) 
-#define AT91C_EMAC_PHYA           (0x1F << 23) // (EMAC) 
-#define AT91C_EMAC_RW             (0x3 << 28) // (EMAC) 
-#define AT91C_EMAC_SOF            (0x3 << 30) // (EMAC) 
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
-#define AT91C_EMAC_RMII           (0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
-#define AT91C_EMAC_IP             (0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG            (0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP            (0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1            (0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
-#define AT91C_EMAC_REVREF         (0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_PARTREF        (0xFFFF << 16) // (EMAC) 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-// *** Register offset in AT91S_ADC structure ***
-#define ADC_CR          ( 0) // ADC Control Register
-#define ADC_MR          ( 4) // ADC Mode Register
-#define ADC_CHER        (16) // ADC Channel Enable Register
-#define ADC_CHDR        (20) // ADC Channel Disable Register
-#define ADC_CHSR        (24) // ADC Channel Status Register
-#define ADC_SR          (28) // ADC Status Register
-#define ADC_LCDR        (32) // ADC Last Converted Data Register
-#define ADC_IER         (36) // ADC Interrupt Enable Register
-#define ADC_IDR         (40) // ADC Interrupt Disable Register
-#define ADC_IMR         (44) // ADC Interrupt Mask Register
-#define ADC_CDR0        (48) // ADC Channel Data Register 0
-#define ADC_CDR1        (52) // ADC Channel Data Register 1
-#define ADC_CDR2        (56) // ADC Channel Data Register 2
-#define ADC_CDR3        (60) // ADC Channel Data Register 3
-#define ADC_CDR4        (64) // ADC Channel Data Register 4
-#define ADC_CDR5        (68) // ADC Channel Data Register 5
-#define ADC_CDR6        (72) // ADC Channel Data Register 6
-#define ADC_CDR7        (76) // ADC Channel Data Register 7
-#define ADC_RPR         (256) // Receive Pointer Register
-#define ADC_RCR         (260) // Receive Counter Register
-#define ADC_TPR         (264) // Transmit Pointer Register
-#define ADC_TCR         (268) // Transmit Counter Register
-#define ADC_RNPR        (272) // Receive Next Pointer Register
-#define ADC_RNCR        (276) // Receive Next Counter Register
-#define ADC_TNPR        (280) // Transmit Next Pointer Register
-#define ADC_TNCR        (284) // Transmit Next Counter Register
-#define ADC_PTCR        (288) // PDC Transfer Control Register
-#define ADC_PTSR        (292) // PDC Transfer Status Register
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-// *** Register offset in AT91S_AES structure ***
-#define AES_CR          ( 0) // Control Register
-#define AES_MR          ( 4) // Mode Register
-#define AES_IER         (16) // Interrupt Enable Register
-#define AES_IDR         (20) // Interrupt Disable Register
-#define AES_IMR         (24) // Interrupt Mask Register
-#define AES_ISR         (28) // Interrupt Status Register
-#define AES_KEYWxR      (32) // Key Word x Register
-#define AES_IDATAxR     (64) // Input Data x Register
-#define AES_ODATAxR     (80) // Output Data x Register
-#define AES_IVxR        (96) // Initialization Vector x Register
-#define AES_VR          (252) // AES Version Register
-#define AES_RPR         (256) // Receive Pointer Register
-#define AES_RCR         (260) // Receive Counter Register
-#define AES_TPR         (264) // Transmit Pointer Register
-#define AES_TCR         (268) // Transmit Counter Register
-#define AES_RNPR        (272) // Receive Next Pointer Register
-#define AES_RNCR        (276) // Receive Next Counter Register
-#define AES_TNPR        (280) // Transmit Next Pointer Register
-#define AES_TNCR        (284) // Transmit Next Counter Register
-#define AES_PTCR        (288) // PDC Transfer Control Register
-#define AES_PTSR        (292) // PDC Transfer Status Register
-// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
-#define AT91C_AES_START           (0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST           (0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED        (0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
-#define AT91C_AES_CIPHER          (0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY         (0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD            (0x3 <<  8) // (AES) Start Mode
-#define 	AT91C_AES_SMOD_MANUAL               (0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define 	AT91C_AES_SMOD_AUTO                 (0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define 	AT91C_AES_SMOD_PDC                  (0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD           (0x7 << 12) // (AES) Operation Mode
-#define 	AT91C_AES_OPMOD_ECB                  (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define 	AT91C_AES_OPMOD_CBC                  (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define 	AT91C_AES_OPMOD_OFB                  (0x2 << 12) // (AES) OFB Output Feedback mode.
-#define 	AT91C_AES_OPMOD_CFB                  (0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define 	AT91C_AES_OPMOD_CTR                  (0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD             (0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS            (0x7 << 16) // (AES) Cipher Feedback Data Size
-#define 	AT91C_AES_CFBS_128_BIT              (0x0 << 16) // (AES) 128-bit.
-#define 	AT91C_AES_CFBS_64_BIT               (0x1 << 16) // (AES) 64-bit.
-#define 	AT91C_AES_CFBS_32_BIT               (0x2 << 16) // (AES) 32-bit.
-#define 	AT91C_AES_CFBS_16_BIT               (0x3 << 16) // (AES) 16-bit.
-#define 	AT91C_AES_CFBS_8_BIT                (0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY            (0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE           (0x1F << 24) // (AES) Countermeasure Type
-#define 	AT91C_AES_CTYPE_TYPE1_EN             (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE2_EN             (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE3_EN             (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE4_EN             (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE5_EN             (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_AES_DATRDY          (0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX           (0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX           (0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF          (0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE          (0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD            (0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_AES_URAT            (0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define 	AT91C_AES_URAT_WO_REG_READ          (0x5 << 12) // (AES) Write-only register read access.
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-// *** Register offset in AT91S_TDES structure ***
-#define TDES_CR         ( 0) // Control Register
-#define TDES_MR         ( 4) // Mode Register
-#define TDES_IER        (16) // Interrupt Enable Register
-#define TDES_IDR        (20) // Interrupt Disable Register
-#define TDES_IMR        (24) // Interrupt Mask Register
-#define TDES_ISR        (28) // Interrupt Status Register
-#define TDES_KEY1WxR    (32) // Key 1 Word x Register
-#define TDES_KEY2WxR    (40) // Key 2 Word x Register
-#define TDES_KEY3WxR    (48) // Key 3 Word x Register
-#define TDES_IDATAxR    (64) // Input Data x Register
-#define TDES_ODATAxR    (80) // Output Data x Register
-#define TDES_IVxR       (96) // Initialization Vector x Register
-#define TDES_VR         (252) // TDES Version Register
-#define TDES_RPR        (256) // Receive Pointer Register
-#define TDES_RCR        (260) // Receive Counter Register
-#define TDES_TPR        (264) // Transmit Pointer Register
-#define TDES_TCR        (268) // Transmit Counter Register
-#define TDES_RNPR       (272) // Receive Next Pointer Register
-#define TDES_RNCR       (276) // Receive Next Counter Register
-#define TDES_TNPR       (280) // Transmit Next Pointer Register
-#define TDES_TNCR       (284) // Transmit Next Counter Register
-#define TDES_PTCR       (288) // PDC Transfer Control Register
-#define TDES_PTSR       (292) // PDC Transfer Status Register
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
-#define AT91C_TDES_START          (0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST          (0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
-#define AT91C_TDES_CIPHER         (0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD        (0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD         (0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD           (0x3 <<  8) // (TDES) Start Mode
-#define 	AT91C_TDES_SMOD_MANUAL               (0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define 	AT91C_TDES_SMOD_AUTO                 (0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define 	AT91C_TDES_SMOD_PDC                  (0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD          (0x3 << 12) // (TDES) Operation Mode
-#define 	AT91C_TDES_OPMOD_ECB                  (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define 	AT91C_TDES_OPMOD_CBC                  (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define 	AT91C_TDES_OPMOD_OFB                  (0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define 	AT91C_TDES_OPMOD_CFB                  (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD            (0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS           (0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define 	AT91C_TDES_CFBS_64_BIT               (0x0 << 16) // (TDES) 64-bit.
-#define 	AT91C_TDES_CFBS_32_BIT               (0x1 << 16) // (TDES) 32-bit.
-#define 	AT91C_TDES_CFBS_16_BIT               (0x2 << 16) // (TDES) 16-bit.
-#define 	AT91C_TDES_CFBS_8_BIT                (0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_TDES_DATRDY         (0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX          (0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX          (0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF         (0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE         (0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD           (0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_TDES_URAT           (0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
-#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
-#define 	AT91C_TDES_URAT_WO_REG_READ          (0x3 << 12) // (TDES) Write-only register read access.
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X128
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ========== 
-// ========== Register definition for AIC peripheral ========== 
-#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ========== 
-#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ========== 
-#define AT91C_DBGU_EXID           (0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR           (0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ========== 
-#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ========== 
-#define AT91C_PIOB_OWDR           (0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER           (0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR          (0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR            (0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR            (0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR          (0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR            (0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER            (0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR           (0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER           (0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR           (0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR           (0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR           (0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR            (0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR           (0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR            (0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR            (0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR           (0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER          (0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR           (0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR            (0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR           (0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR            (0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR           (0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER           (0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR            (0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR           (0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER            (0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER            (0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ========== 
-#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR           (0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ========== 
-#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR             (0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR            (0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR            (0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ========== 
-#define AT91C_RSTC_RCR            (0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR            (0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR            (0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ========== 
-#define AT91C_RTTC_RTSR           (0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR           (0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR           (0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR           (0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ========== 
-#define AT91C_PITC_PIVR           (0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR           (0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR           (0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR           (0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ========== 
-#define AT91C_WDTC_WDCR           (0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR           (0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR           (0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ========== 
-#define AT91C_VREG_MR             (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ========== 
-#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR              (0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR              (0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR              (0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ========== 
-#define AT91C_SPI1_PTCR           (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR            (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR           (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR            (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR           (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR            (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR            (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR           (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR           (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR           (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ========== 
-#define AT91C_SPI1_IMR            (0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER            (0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR             (0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR            (0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR            (0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR             (0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR            (0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR             (0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR            (0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ========== 
-#define AT91C_SPI0_PTCR           (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR            (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR            (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR            (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR           (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR           (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR            (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR           (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR           (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR           (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ========== 
-#define AT91C_SPI0_IER            (0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR             (0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR            (0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR             (0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR             (0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR            (0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR            (0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR            (0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR            (0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ========== 
-#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ========== 
-#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ========== 
-#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ========== 
-#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ========== 
-#define AT91C_SSC_TNCR            (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR             (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR            (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR             (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR            (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR             (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR             (0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR            (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR            (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR            (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ========== 
-#define AT91C_SSC_RHR             (0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR            (0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR            (0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR             (0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR             (0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR            (0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER             (0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR            (0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR              (0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR             (0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR            (0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR              (0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR             (0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR            (0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ========== 
-#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ========== 
-#define AT91C_PWMC_CH3_CUPDR      (0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved   (0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR      (0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR      (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR      (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR        (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ========== 
-#define AT91C_PWMC_CH2_Reserved   (0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR        (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR      (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR      (0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR      (0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR      (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ========== 
-#define AT91C_PWMC_CH1_Reserved   (0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR      (0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR      (0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR      (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR      (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR        (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ========== 
-#define AT91C_PWMC_CH0_Reserved   (0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR      (0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR      (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR        (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR      (0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR      (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ========== 
-#define AT91C_PWMC_IDR            (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS            (0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER            (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR             (0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR            (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR             (0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR            (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR             (0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA            (0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ========== 
-#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC            (0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ========== 
-#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ========== 
-#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ========== 
-#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ========== 
-#define AT91C_TCB_BMR             (0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR             (0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ========== 
-#define AT91C_CAN_MB0_MDL         (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM         (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR         (0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID         (0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR         (0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID        (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH         (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR         (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ========== 
-#define AT91C_CAN_MB1_MDL         (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID         (0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR         (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR         (0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM         (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH         (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR         (0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID        (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ========== 
-#define AT91C_CAN_MB2_MCR         (0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH         (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID         (0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL         (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR         (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM         (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID        (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR         (0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ========== 
-#define AT91C_CAN_MB3_MFID        (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM         (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID         (0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR         (0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR         (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR         (0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL         (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH         (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ========== 
-#define AT91C_CAN_MB4_MID         (0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR         (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH         (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID        (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR         (0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR         (0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL         (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM         (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ========== 
-#define AT91C_CAN_MB5_MSR         (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR         (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID        (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH         (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID         (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR         (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL         (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM         (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ========== 
-#define AT91C_CAN_MB6_MFID        (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID         (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM         (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR         (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL         (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR         (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH         (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR         (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ========== 
-#define AT91C_CAN_MB7_MCR         (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH         (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID        (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL         (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID         (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR         (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM         (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR         (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ========== 
-#define AT91C_CAN_TCR             (0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR             (0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER             (0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR             (0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP         (0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR              (0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR             (0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR             (0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM             (0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR              (0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR              (0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR              (0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ========== 
-#define AT91C_EMAC_ISR            (0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H           (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L           (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE            (0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL           (0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE            (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL            (0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF            (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND           (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR            (0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L           (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR            (0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L           (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR            (0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR            (0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE            (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL           (0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID            (0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB            (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP           (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO          (0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR            (0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H           (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV            (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE            (0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA            (0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP           (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF            (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR          (0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT            (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF            (0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE           (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ            (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN            (0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO            (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV            (0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR            (0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF            (0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR            (0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF            (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR            (0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L           (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO            (0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER            (0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H           (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE            (0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H           (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE            (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE            (0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ========== 
-#define AT91C_ADC_PTSR            (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR            (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR            (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR            (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR            (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR            (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR             (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR             (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR             (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR             (0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ========== 
-#define AT91C_ADC_CDR2            (0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3            (0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0            (0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5            (0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR            (0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR              (0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4            (0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1            (0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR            (0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR             (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR              (0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7            (0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6            (0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER             (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER            (0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR            (0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR              (0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR             (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ========== 
-#define AT91C_AES_TPR             (0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR            (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR            (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR            (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR             (0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR             (0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR            (0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR            (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR             (0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR            (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ========== 
-#define AT91C_AES_IVxR            (0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR              (0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR              (0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR         (0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR         (0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR              (0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR             (0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR             (0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER             (0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR          (0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR             (0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ========== 
-#define AT91C_TDES_RNCR           (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR            (0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR            (0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR           (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR           (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR            (0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR           (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR            (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR           (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR           (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ========== 
-#define AT91C_TDES_KEY2WxR        (0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR        (0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR            (0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR             (0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR           (0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR        (0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR            (0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR             (0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR             (0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER            (0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR            (0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR        (0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR        (0xFFFA8020) // (TDES) Key 1 Word x Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0            (AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0            (AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD            (AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK           (AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00         (AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01         (AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1           (AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02         (AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1           (AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03         (AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2          (AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0          (AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0          (AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0          (AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX          (AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0            (AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11          (AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX          (AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF             (AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10         (AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK             (AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1          (AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD             (AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1          (AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD             (AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1          (AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK             (AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11         (AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF             (AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12         (AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD           (AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3           (AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD           (AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ            (AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13         (AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0            (AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12          (AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0           (AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2           (AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0            (AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13          (AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1            (AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1            (AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1            (AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01          (AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1            (AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02          (AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1            (AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03          (AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0             (1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK    (AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0            (AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1             (1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN           (AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10            (1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2           (AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11         (AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11            (1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3           (AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12         (AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12            (1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER          (AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0          (AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13            (1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2           (AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01         (AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14            (1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3           (AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02         (AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15            (1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV          (AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16            (1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL           (AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13         (AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17            (1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK          (AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03         (AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18            (1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100          (AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG          (AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19            (1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0           (AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1          (AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2             (1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0            (AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20            (1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1           (AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0           (AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21            (1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2           (AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1           (AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22            (1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3           (AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2           (AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23            (1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0          (AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1           (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24            (1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0          (AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1           (AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25            (1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1          (AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1           (AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26            (1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1          (AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1            (AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27            (1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2          (AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0           (AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28            (1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2          (AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1           (AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29            (1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1           (AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2           (AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3             (1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1            (AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30            (1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2           (AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3           (AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4             (1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV     (AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5             (1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0            (AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6             (1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1            (AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7             (1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER           (AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8             (1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC            (AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9             (1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO           (AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS              ( 1) // System Peripheral
-#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB             ( 3) // Parallel IO Controller B
-#define AT91C_ID_SPI0             ( 4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1             ( 5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0              ( 6) // USART 0
-#define AT91C_ID_US1              ( 7) // USART 1
-#define AT91C_ID_SSC              ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI              ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC             (10) // PWM Controller
-#define AT91C_ID_UDP              (11) // USB Device Port
-#define AT91C_ID_TC0              (12) // Timer Counter 0
-#define AT91C_ID_TC1              (13) // Timer Counter 1
-#define AT91C_ID_TC2              (14) // Timer Counter 2
-#define AT91C_ID_CAN              (15) // Control Area Network Controller
-#define AT91C_ID_EMAC             (16) // Ethernet MAC
-#define AT91C_ID_ADC              (17) // Analog-to-Digital Converter
-#define AT91C_ID_AES              (18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES             (19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved      (20) // Reserved
-#define AT91C_ID_21_Reserved      (21) // Reserved
-#define AT91C_ID_22_Reserved      (22) // Reserved
-#define AT91C_ID_23_Reserved      (23) // Reserved
-#define AT91C_ID_24_Reserved      (24) // Reserved
-#define AT91C_ID_25_Reserved      (25) // Reserved
-#define AT91C_ID_26_Reserved      (26) // Reserved
-#define AT91C_ID_27_Reserved      (27) // Reserved
-#define AT91C_ID_28_Reserved      (28) // Reserved
-#define AT91C_ID_29_Reserved      (29) // Reserved
-#define AT91C_ID_IRQ0             (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1             (31) // Advanced Interrupt Controller (IRQ1)
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_BASE_SYS            (0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB           (0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG           (0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1       (0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1           (0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0       (0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0           (0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0        (0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1        (0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2        (0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3        (0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4        (0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5        (0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6        (0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7        (0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN            (0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC           (0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES        (0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES            (0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES       (0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES           (0xFFFA8000) // (TDES) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X128
-// *****************************************************************************
-#define AT91C_ISRAM	              (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	         (0x00008000) // Internal SRAM size in byte (32 Kbyte)
-#define AT91C_IFLASH	             (0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE	        (0x00020000) // Internal ROM size in byte (128 Kbyte)
-
-
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
deleted file mode 100755
index 733d2f5..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256.h
+++ /dev/null
@@ -1,2715 +0,0 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7X256.h
-// Object              : AT91SAM7X256 definitions
-// Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-// 
-// CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
-// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-//  ----------------------------------------------------------------------------
-
-#ifndef AT91SAM7X256_H
-#define AT91SAM7X256_H
-
-typedef volatile unsigned int AT91_REG;// Hardware register definition
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-typedef struct _AT91S_SYS {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-	AT91_REG	 Reserved2[45]; 	// 
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved3[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved4[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-	AT91_REG	 Reserved5[54]; 	// 
-	AT91_REG	 PIOA_PER; 	// PIO Enable Register
-	AT91_REG	 PIOA_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOA_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved6[1]; 	// 
-	AT91_REG	 PIOA_OER; 	// Output Enable Register
-	AT91_REG	 PIOA_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOA_OSR; 	// Output Status Register
-	AT91_REG	 Reserved7[1]; 	// 
-	AT91_REG	 PIOA_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOA_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOA_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved8[1]; 	// 
-	AT91_REG	 PIOA_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOA_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOA_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOA_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOA_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOA_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOA_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOA_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOA_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOA_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOA_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved9[1]; 	// 
-	AT91_REG	 PIOA_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOA_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOA_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved10[1]; 	// 
-	AT91_REG	 PIOA_ASR; 	// Select A Register
-	AT91_REG	 PIOA_BSR; 	// Select B Register
-	AT91_REG	 PIOA_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved11[9]; 	// 
-	AT91_REG	 PIOA_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOA_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOA_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved12[85]; 	// 
-	AT91_REG	 PIOB_PER; 	// PIO Enable Register
-	AT91_REG	 PIOB_PDR; 	// PIO Disable Register
-	AT91_REG	 PIOB_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved13[1]; 	// 
-	AT91_REG	 PIOB_OER; 	// Output Enable Register
-	AT91_REG	 PIOB_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIOB_OSR; 	// Output Status Register
-	AT91_REG	 Reserved14[1]; 	// 
-	AT91_REG	 PIOB_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIOB_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIOB_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved15[1]; 	// 
-	AT91_REG	 PIOB_SODR; 	// Set Output Data Register
-	AT91_REG	 PIOB_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIOB_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIOB_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIOB_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIOB_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIOB_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIOB_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIOB_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIOB_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIOB_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved16[1]; 	// 
-	AT91_REG	 PIOB_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIOB_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIOB_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved17[1]; 	// 
-	AT91_REG	 PIOB_ASR; 	// Select A Register
-	AT91_REG	 PIOB_BSR; 	// Select B Register
-	AT91_REG	 PIOB_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved18[9]; 	// 
-	AT91_REG	 PIOB_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIOB_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIOB_OWSR; 	// Output Write Status Register
-	AT91_REG	 Reserved19[341]; 	// 
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved20[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved21[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved22[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved23[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved24[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved25[36]; 	// 
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-	AT91_REG	 Reserved26[5]; 	// 
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-	AT91_REG	 Reserved27[5]; 	// 
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_SYS, *AT91PS_SYS;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-typedef struct _AT91S_AIC {
-	AT91_REG	 AIC_SMR[32]; 	// Source Mode Register
-	AT91_REG	 AIC_SVR[32]; 	// Source Vector Register
-	AT91_REG	 AIC_IVR; 	// IRQ Vector Register
-	AT91_REG	 AIC_FVR; 	// FIQ Vector Register
-	AT91_REG	 AIC_ISR; 	// Interrupt Status Register
-	AT91_REG	 AIC_IPR; 	// Interrupt Pending Register
-	AT91_REG	 AIC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AIC_CISR; 	// Core Interrupt Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AIC_IECR; 	// Interrupt Enable Command Register
-	AT91_REG	 AIC_IDCR; 	// Interrupt Disable Command Register
-	AT91_REG	 AIC_ICCR; 	// Interrupt Clear Command Register
-	AT91_REG	 AIC_ISCR; 	// Interrupt Set Command Register
-	AT91_REG	 AIC_EOICR; 	// End of Interrupt Command Register
-	AT91_REG	 AIC_SPU; 	// Spurious Vector Register
-	AT91_REG	 AIC_DCR; 	// Debug Control Register (Protect)
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 AIC_FFER; 	// Fast Forcing Enable Register
-	AT91_REG	 AIC_FFDR; 	// Fast Forcing Disable Register
-	AT91_REG	 AIC_FFSR; 	// Fast Forcing Status Register
-} AT91S_AIC, *AT91PS_AIC;
-
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#define AT91C_AIC_PRIOR       ((unsigned int) 0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               ((unsigned int) 0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              ((unsigned int) 0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE     ((unsigned int) 0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       ((unsigned int) 0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        ((unsigned int) 0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    ((unsigned int) 0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           ((unsigned int) 0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        ((unsigned int) 0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-#define AT91C_AIC_NFIQ        ((unsigned int) 0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ        ((unsigned int) 0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-#define AT91C_AIC_DCR_PROT    ((unsigned int) 0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK    ((unsigned int) 0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-typedef struct _AT91S_PDC {
-	AT91_REG	 PDC_RPR; 	// Receive Pointer Register
-	AT91_REG	 PDC_RCR; 	// Receive Counter Register
-	AT91_REG	 PDC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 PDC_TCR; 	// Transmit Counter Register
-	AT91_REG	 PDC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 PDC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 PDC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 PDC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 PDC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 PDC_PTSR; 	// PDC Transfer Status Register
-} AT91S_PDC, *AT91PS_PDC;
-
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-#define AT91C_PDC_RXTEN       ((unsigned int) 0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS      ((unsigned int) 0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN       ((unsigned int) 0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS      ((unsigned int) 0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-typedef struct _AT91S_DBGU {
-	AT91_REG	 DBGU_CR; 	// Control Register
-	AT91_REG	 DBGU_MR; 	// Mode Register
-	AT91_REG	 DBGU_IER; 	// Interrupt Enable Register
-	AT91_REG	 DBGU_IDR; 	// Interrupt Disable Register
-	AT91_REG	 DBGU_IMR; 	// Interrupt Mask Register
-	AT91_REG	 DBGU_CSR; 	// Channel Status Register
-	AT91_REG	 DBGU_RHR; 	// Receiver Holding Register
-	AT91_REG	 DBGU_THR; 	// Transmitter Holding Register
-	AT91_REG	 DBGU_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 Reserved0[7]; 	// 
-	AT91_REG	 DBGU_CIDR; 	// Chip ID Register
-	AT91_REG	 DBGU_EXID; 	// Chip ID Extension Register
-	AT91_REG	 DBGU_FNTR; 	// Force NTRST Register
-	AT91_REG	 Reserved1[45]; 	// 
-	AT91_REG	 DBGU_RPR; 	// Receive Pointer Register
-	AT91_REG	 DBGU_RCR; 	// Receive Counter Register
-	AT91_REG	 DBGU_TPR; 	// Transmit Pointer Register
-	AT91_REG	 DBGU_TCR; 	// Transmit Counter Register
-	AT91_REG	 DBGU_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 DBGU_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 DBGU_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 DBGU_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 DBGU_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 DBGU_PTSR; 	// PDC Transfer Status Register
-} AT91S_DBGU, *AT91PS_DBGU;
-
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTRX        ((unsigned int) 0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX        ((unsigned int) 0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN         ((unsigned int) 0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS        ((unsigned int) 0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN         ((unsigned int) 0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS        ((unsigned int) 0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA       ((unsigned int) 0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_PAR          ((unsigned int) 0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 ((unsigned int) 0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  ((unsigned int) 0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                ((unsigned int) 0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 ((unsigned int) 0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 ((unsigned int) 0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           ((unsigned int) 0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE       ((unsigned int) 0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               ((unsigned int) 0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 ((unsigned int) 0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                ((unsigned int) 0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               ((unsigned int) 0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXRDY        ((unsigned int) 0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY        ((unsigned int) 0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX        ((unsigned int) 0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX        ((unsigned int) 0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE         ((unsigned int) 0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME        ((unsigned int) 0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE         ((unsigned int) 0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY      ((unsigned int) 0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE       ((unsigned int) 0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF       ((unsigned int) 0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX      ((unsigned int) 0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX      ((unsigned int) 0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-#define AT91C_US_FORCE_NTRST  ((unsigned int) 0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-typedef struct _AT91S_PIO {
-	AT91_REG	 PIO_PER; 	// PIO Enable Register
-	AT91_REG	 PIO_PDR; 	// PIO Disable Register
-	AT91_REG	 PIO_PSR; 	// PIO Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PIO_OER; 	// Output Enable Register
-	AT91_REG	 PIO_ODR; 	// Output Disable Registerr
-	AT91_REG	 PIO_OSR; 	// Output Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PIO_IFER; 	// Input Filter Enable Register
-	AT91_REG	 PIO_IFDR; 	// Input Filter Disable Register
-	AT91_REG	 PIO_IFSR; 	// Input Filter Status Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PIO_SODR; 	// Set Output Data Register
-	AT91_REG	 PIO_CODR; 	// Clear Output Data Register
-	AT91_REG	 PIO_ODSR; 	// Output Data Status Register
-	AT91_REG	 PIO_PDSR; 	// Pin Data Status Register
-	AT91_REG	 PIO_IER; 	// Interrupt Enable Register
-	AT91_REG	 PIO_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PIO_IMR; 	// Interrupt Mask Register
-	AT91_REG	 PIO_ISR; 	// Interrupt Status Register
-	AT91_REG	 PIO_MDER; 	// Multi-driver Enable Register
-	AT91_REG	 PIO_MDDR; 	// Multi-driver Disable Register
-	AT91_REG	 PIO_MDSR; 	// Multi-driver Status Register
-	AT91_REG	 Reserved3[1]; 	// 
-	AT91_REG	 PIO_PPUDR; 	// Pull-up Disable Register
-	AT91_REG	 PIO_PPUER; 	// Pull-up Enable Register
-	AT91_REG	 PIO_PPUSR; 	// Pull-up Status Register
-	AT91_REG	 Reserved4[1]; 	// 
-	AT91_REG	 PIO_ASR; 	// Select A Register
-	AT91_REG	 PIO_BSR; 	// Select B Register
-	AT91_REG	 PIO_ABSR; 	// AB Select Status Register
-	AT91_REG	 Reserved5[9]; 	// 
-	AT91_REG	 PIO_OWER; 	// Output Write Enable Register
-	AT91_REG	 PIO_OWDR; 	// Output Write Disable Register
-	AT91_REG	 PIO_OWSR; 	// Output Write Status Register
-} AT91S_PIO, *AT91PS_PIO;
-
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-typedef struct _AT91S_CKGR {
-	AT91_REG	 CKGR_MOR; 	// Main Oscillator Register
-	AT91_REG	 CKGR_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 CKGR_PLLR; 	// PLL Register
-} AT91S_CKGR, *AT91PS_CKGR;
-
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-#define AT91C_CKGR_MOSCEN     ((unsigned int) 0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS  ((unsigned int) 0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT    ((unsigned int) 0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-#define AT91C_CKGR_MAINF      ((unsigned int) 0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY    ((unsigned int) 0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-#define AT91C_CKGR_DIV        ((unsigned int) 0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    ((unsigned int) 0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               ((unsigned int) 0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT   ((unsigned int) 0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT        ((unsigned int) 0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    ((unsigned int) 0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    ((unsigned int) 0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    ((unsigned int) 0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    ((unsigned int) 0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL        ((unsigned int) 0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV     ((unsigned int) 0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    ((unsigned int) 0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    ((unsigned int) 0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    ((unsigned int) 0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-typedef struct _AT91S_PMC {
-	AT91_REG	 PMC_SCER; 	// System Clock Enable Register
-	AT91_REG	 PMC_SCDR; 	// System Clock Disable Register
-	AT91_REG	 PMC_SCSR; 	// System Clock Status Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 PMC_PCER; 	// Peripheral Clock Enable Register
-	AT91_REG	 PMC_PCDR; 	// Peripheral Clock Disable Register
-	AT91_REG	 PMC_PCSR; 	// Peripheral Clock Status Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 PMC_MOR; 	// Main Oscillator Register
-	AT91_REG	 PMC_MCFR; 	// Main Clock  Frequency Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 PMC_PLLR; 	// PLL Register
-	AT91_REG	 PMC_MCKR; 	// Master Clock Register
-	AT91_REG	 Reserved3[3]; 	// 
-	AT91_REG	 PMC_PCKR[4]; 	// Programmable Clock Register
-	AT91_REG	 Reserved4[4]; 	// 
-	AT91_REG	 PMC_IER; 	// Interrupt Enable Register
-	AT91_REG	 PMC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 PMC_SR; 	// Status Register
-	AT91_REG	 PMC_IMR; 	// Interrupt Mask Register
-} AT91S_PMC, *AT91PS_PMC;
-
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-#define AT91C_PMC_PCK         ((unsigned int) 0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP         ((unsigned int) 0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0        ((unsigned int) 0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1        ((unsigned int) 0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2        ((unsigned int) 0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3        ((unsigned int) 0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-#define AT91C_PMC_CSS         ((unsigned int) 0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             ((unsigned int) 0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             ((unsigned int) 0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              ((unsigned int) 0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES        ((unsigned int) 0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  ((unsigned int) 0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                ((unsigned int) 0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                ((unsigned int) 0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                ((unsigned int) 0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               ((unsigned int) 0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               ((unsigned int) 0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               ((unsigned int) 0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-#define AT91C_PMC_MOSCS       ((unsigned int) 0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK        ((unsigned int) 0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY      ((unsigned int) 0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY     ((unsigned int) 0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY     ((unsigned int) 0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY     ((unsigned int) 0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY     ((unsigned int) 0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RSTC {
-	AT91_REG	 RSTC_RCR; 	// Reset Control Register
-	AT91_REG	 RSTC_RSR; 	// Reset Status Register
-	AT91_REG	 RSTC_RMR; 	// Reset Mode Register
-} AT91S_RSTC, *AT91PS_RSTC;
-
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-#define AT91C_RSTC_PROCRST    ((unsigned int) 0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST     ((unsigned int) 0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST     ((unsigned int) 0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY        ((unsigned int) 0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-#define AT91C_RSTC_URSTS      ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS     ((unsigned int) 0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP     ((unsigned int) 0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              ((unsigned int) 0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               ((unsigned int) 0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             ((unsigned int) 0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             ((unsigned int) 0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 ((unsigned int) 0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             ((unsigned int) 0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL      ((unsigned int) 0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP      ((unsigned int) 0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-#define AT91C_RSTC_URSTEN     ((unsigned int) 0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN    ((unsigned int) 0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL      ((unsigned int) 0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN     ((unsigned int) 0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_RTTC {
-	AT91_REG	 RTTC_RTMR; 	// Real-time Mode Register
-	AT91_REG	 RTTC_RTAR; 	// Real-time Alarm Register
-	AT91_REG	 RTTC_RTVR; 	// Real-time Value Register
-	AT91_REG	 RTTC_RTSR; 	// Real-time Status Register
-} AT91S_RTTC, *AT91PS_RTTC;
-
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-#define AT91C_RTTC_RTPRES     ((unsigned int) 0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN     ((unsigned int) 0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN  ((unsigned int) 0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST     ((unsigned int) 0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-#define AT91C_RTTC_ALMV       ((unsigned int) 0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-#define AT91C_RTTC_CRTV       ((unsigned int) 0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-#define AT91C_RTTC_ALMS       ((unsigned int) 0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC     ((unsigned int) 0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PITC {
-	AT91_REG	 PITC_PIMR; 	// Period Interval Mode Register
-	AT91_REG	 PITC_PISR; 	// Period Interval Status Register
-	AT91_REG	 PITC_PIVR; 	// Period Interval Value Register
-	AT91_REG	 PITC_PIIR; 	// Period Interval Image Register
-} AT91S_PITC, *AT91PS_PITC;
-
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-#define AT91C_PITC_PIV        ((unsigned int) 0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN      ((unsigned int) 0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN     ((unsigned int) 0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-#define AT91C_PITC_PITS       ((unsigned int) 0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-#define AT91C_PITC_CPIV       ((unsigned int) 0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT      ((unsigned int) 0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_WDTC {
-	AT91_REG	 WDTC_WDCR; 	// Watchdog Control Register
-	AT91_REG	 WDTC_WDMR; 	// Watchdog Mode Register
-	AT91_REG	 WDTC_WDSR; 	// Watchdog Status Register
-} AT91S_WDTC, *AT91PS_WDTC;
-
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-#define AT91C_WDTC_WDRSTT     ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY        ((unsigned int) 0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-#define AT91C_WDTC_WDV        ((unsigned int) 0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN     ((unsigned int) 0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN    ((unsigned int) 0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC    ((unsigned int) 0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS      ((unsigned int) 0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD        ((unsigned int) 0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT   ((unsigned int) 0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT  ((unsigned int) 0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-#define AT91C_WDTC_WDUNF      ((unsigned int) 0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR      ((unsigned int) 0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_VREG {
-	AT91_REG	 VREG_MR; 	// Voltage Regulator Mode Register
-} AT91S_VREG, *AT91PS_VREG;
-
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
-#define AT91C_VREG_PSTDBY     ((unsigned int) 0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_MC {
-	AT91_REG	 MC_RCR; 	// MC Remap Control Register
-	AT91_REG	 MC_ASR; 	// MC Abort Status Register
-	AT91_REG	 MC_AASR; 	// MC Abort Address Status Register
-	AT91_REG	 Reserved0[21]; 	// 
-	AT91_REG	 MC_FMR; 	// MC Flash Mode Register
-	AT91_REG	 MC_FCR; 	// MC Flash Command Register
-	AT91_REG	 MC_FSR; 	// MC Flash Status Register
-} AT91S_MC, *AT91PS_MC;
-
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-#define AT91C_MC_RCB          ((unsigned int) 0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-#define AT91C_MC_UNDADD       ((unsigned int) 0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD       ((unsigned int) 0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ        ((unsigned int) 0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 ((unsigned int) 0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                ((unsigned int) 0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 ((unsigned int) 0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP       ((unsigned int) 0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                ((unsigned int) 0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                ((unsigned int) 0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                ((unsigned int) 0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0         ((unsigned int) 0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1         ((unsigned int) 0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0       ((unsigned int) 0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1       ((unsigned int) 0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-#define AT91C_MC_FRDY         ((unsigned int) 0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE        ((unsigned int) 0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE        ((unsigned int) 0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP         ((unsigned int) 0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS          ((unsigned int) 0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 ((unsigned int) 0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 ((unsigned int) 0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 ((unsigned int) 0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 ((unsigned int) 0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN         ((unsigned int) 0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-#define AT91C_MC_FCMD         ((unsigned int) 0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           ((unsigned int) 0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 ((unsigned int) 0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        ((unsigned int) 0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               ((unsigned int) 0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            ((unsigned int) 0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           ((unsigned int) 0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           ((unsigned int) 0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         ((unsigned int) 0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN        ((unsigned int) 0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY          ((unsigned int) 0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-#define AT91C_MC_SECURITY     ((unsigned int) 0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0       ((unsigned int) 0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1       ((unsigned int) 0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2       ((unsigned int) 0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3       ((unsigned int) 0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4       ((unsigned int) 0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5       ((unsigned int) 0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6       ((unsigned int) 0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7       ((unsigned int) 0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0       ((unsigned int) 0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1       ((unsigned int) 0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2       ((unsigned int) 0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3       ((unsigned int) 0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4       ((unsigned int) 0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5       ((unsigned int) 0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6       ((unsigned int) 0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7       ((unsigned int) 0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8       ((unsigned int) 0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9       ((unsigned int) 0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10      ((unsigned int) 0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11      ((unsigned int) 0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12      ((unsigned int) 0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13      ((unsigned int) 0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14      ((unsigned int) 0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15      ((unsigned int) 0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-typedef struct _AT91S_SPI {
-	AT91_REG	 SPI_CR; 	// Control Register
-	AT91_REG	 SPI_MR; 	// Mode Register
-	AT91_REG	 SPI_RDR; 	// Receive Data Register
-	AT91_REG	 SPI_TDR; 	// Transmit Data Register
-	AT91_REG	 SPI_SR; 	// Status Register
-	AT91_REG	 SPI_IER; 	// Interrupt Enable Register
-	AT91_REG	 SPI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SPI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91_REG	 SPI_CSR[4]; 	// Chip Select Register
-	AT91_REG	 Reserved1[48]; 	// 
-	AT91_REG	 SPI_RPR; 	// Receive Pointer Register
-	AT91_REG	 SPI_RCR; 	// Receive Counter Register
-	AT91_REG	 SPI_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SPI_TCR; 	// Transmit Counter Register
-	AT91_REG	 SPI_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SPI_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SPI_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SPI_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SPI_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SPI_PTSR; 	// PDC Transfer Status Register
-} AT91S_SPI, *AT91PS_SPI;
-
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-#define AT91C_SPI_SPIEN       ((unsigned int) 0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS      ((unsigned int) 0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST       ((unsigned int) 0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER    ((unsigned int) 0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-#define AT91C_SPI_MSTR        ((unsigned int) 0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS          ((unsigned int) 0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                ((unsigned int) 0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             ((unsigned int) 0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC      ((unsigned int) 0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV        ((unsigned int) 0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS     ((unsigned int) 0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB         ((unsigned int) 0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS         ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-#define AT91C_SPI_RD          ((unsigned int) 0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-#define AT91C_SPI_TD          ((unsigned int) 0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS        ((unsigned int) 0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-#define AT91C_SPI_RDRF        ((unsigned int) 0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE        ((unsigned int) 0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF        ((unsigned int) 0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES       ((unsigned int) 0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX       ((unsigned int) 0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX       ((unsigned int) 0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF      ((unsigned int) 0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE      ((unsigned int) 0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR        ((unsigned int) 0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY     ((unsigned int) 0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS      ((unsigned int) 0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-#define AT91C_SPI_CPOL        ((unsigned int) 0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA       ((unsigned int) 0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT       ((unsigned int) 0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS        ((unsigned int) 0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    ((unsigned int) 0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    ((unsigned int) 0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   ((unsigned int) 0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   ((unsigned int) 0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   ((unsigned int) 0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   ((unsigned int) 0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   ((unsigned int) 0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   ((unsigned int) 0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   ((unsigned int) 0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR        ((unsigned int) 0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS       ((unsigned int) 0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT      ((unsigned int) 0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-typedef struct _AT91S_USART {
-	AT91_REG	 US_CR; 	// Control Register
-	AT91_REG	 US_MR; 	// Mode Register
-	AT91_REG	 US_IER; 	// Interrupt Enable Register
-	AT91_REG	 US_IDR; 	// Interrupt Disable Register
-	AT91_REG	 US_IMR; 	// Interrupt Mask Register
-	AT91_REG	 US_CSR; 	// Channel Status Register
-	AT91_REG	 US_RHR; 	// Receiver Holding Register
-	AT91_REG	 US_THR; 	// Transmitter Holding Register
-	AT91_REG	 US_BRGR; 	// Baud Rate Generator Register
-	AT91_REG	 US_RTOR; 	// Receiver Time-out Register
-	AT91_REG	 US_TTGR; 	// Transmitter Time-guard Register
-	AT91_REG	 Reserved0[5]; 	// 
-	AT91_REG	 US_FIDI; 	// FI_DI_Ratio Register
-	AT91_REG	 US_NER; 	// Nb Errors Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 US_IF; 	// IRDA_FILTER Register
-	AT91_REG	 Reserved2[44]; 	// 
-	AT91_REG	 US_RPR; 	// Receive Pointer Register
-	AT91_REG	 US_RCR; 	// Receive Counter Register
-	AT91_REG	 US_TPR; 	// Transmit Pointer Register
-	AT91_REG	 US_TCR; 	// Transmit Counter Register
-	AT91_REG	 US_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 US_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 US_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 US_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 US_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 US_PTSR; 	// PDC Transfer Status Register
-} AT91S_USART, *AT91PS_USART;
-
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_STTBRK       ((unsigned int) 0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK       ((unsigned int) 0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO        ((unsigned int) 0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA        ((unsigned int) 0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT        ((unsigned int) 0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK      ((unsigned int) 0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO        ((unsigned int) 0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN        ((unsigned int) 0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS       ((unsigned int) 0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN        ((unsigned int) 0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS       ((unsigned int) 0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_USMODE       ((unsigned int) 0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               ((unsigned int) 0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                ((unsigned int) 0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                ((unsigned int) 0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                ((unsigned int) 0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            ((unsigned int) 0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            ((unsigned int) 0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 ((unsigned int) 0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                ((unsigned int) 0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS         ((unsigned int) 0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                ((unsigned int) 0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                ((unsigned int) 0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 ((unsigned int) 0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  ((unsigned int) 0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL         ((unsigned int) 0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               ((unsigned int) 0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               ((unsigned int) 0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               ((unsigned int) 0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               ((unsigned int) 0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC         ((unsigned int) 0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP       ((unsigned int) 0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                ((unsigned int) 0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               ((unsigned int) 0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                ((unsigned int) 0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF         ((unsigned int) 0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9        ((unsigned int) 0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO         ((unsigned int) 0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER         ((unsigned int) 0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK        ((unsigned int) 0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK       ((unsigned int) 0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER     ((unsigned int) 0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER       ((unsigned int) 0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXBRK        ((unsigned int) 0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT      ((unsigned int) 0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION    ((unsigned int) 0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK         ((unsigned int) 0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC         ((unsigned int) 0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC        ((unsigned int) 0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC        ((unsigned int) 0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC        ((unsigned int) 0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-#define AT91C_US_RI           ((unsigned int) 0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR          ((unsigned int) 0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD          ((unsigned int) 0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS          ((unsigned int) 0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_SSC {
-	AT91_REG	 SSC_CR; 	// Control Register
-	AT91_REG	 SSC_CMR; 	// Clock Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 SSC_RCMR; 	// Receive Clock ModeRegister
-	AT91_REG	 SSC_RFMR; 	// Receive Frame Mode Register
-	AT91_REG	 SSC_TCMR; 	// Transmit Clock Mode Register
-	AT91_REG	 SSC_TFMR; 	// Transmit Frame Mode Register
-	AT91_REG	 SSC_RHR; 	// Receive Holding Register
-	AT91_REG	 SSC_THR; 	// Transmit Holding Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 SSC_RSHR; 	// Receive Sync Holding Register
-	AT91_REG	 SSC_TSHR; 	// Transmit Sync Holding Register
-	AT91_REG	 Reserved2[2]; 	// 
-	AT91_REG	 SSC_SR; 	// Status Register
-	AT91_REG	 SSC_IER; 	// Interrupt Enable Register
-	AT91_REG	 SSC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 SSC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 Reserved3[44]; 	// 
-	AT91_REG	 SSC_RPR; 	// Receive Pointer Register
-	AT91_REG	 SSC_RCR; 	// Receive Counter Register
-	AT91_REG	 SSC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 SSC_TCR; 	// Transmit Counter Register
-	AT91_REG	 SSC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 SSC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 SSC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 SSC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 SSC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 SSC_PTSR; 	// PDC Transfer Status Register
-} AT91S_SSC, *AT91PS_SSC;
-
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-#define AT91C_SSC_RXEN        ((unsigned int) 0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS       ((unsigned int) 0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN        ((unsigned int) 0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS       ((unsigned int) 0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST       ((unsigned int) 0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-#define AT91C_SSC_CKS         ((unsigned int) 0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  ((unsigned int) 0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   ((unsigned int) 0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   ((unsigned int) 0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO         ((unsigned int) 0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 ((unsigned int) 0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            ((unsigned int) 0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              ((unsigned int) 0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI         ((unsigned int) 0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START       ((unsigned int) 0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            ((unsigned int) 0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   ((unsigned int) 0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               ((unsigned int) 0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              ((unsigned int) 0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              ((unsigned int) 0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              ((unsigned int) 0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             ((unsigned int) 0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              ((unsigned int) 0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    ((unsigned int) 0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY      ((unsigned int) 0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD      ((unsigned int) 0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-#define AT91C_SSC_DATLEN      ((unsigned int) 0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP        ((unsigned int) 0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF        ((unsigned int) 0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB       ((unsigned int) 0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN       ((unsigned int) 0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS        ((unsigned int) 0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 ((unsigned int) 0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             ((unsigned int) 0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             ((unsigned int) 0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  ((unsigned int) 0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 ((unsigned int) 0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               ((unsigned int) 0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE      ((unsigned int) 0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-#define AT91C_SSC_DATDEF      ((unsigned int) 0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN       ((unsigned int) 0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-#define AT91C_SSC_TXRDY       ((unsigned int) 0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY     ((unsigned int) 0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX       ((unsigned int) 0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE      ((unsigned int) 0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY       ((unsigned int) 0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN       ((unsigned int) 0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX       ((unsigned int) 0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF      ((unsigned int) 0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN       ((unsigned int) 0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN       ((unsigned int) 0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA       ((unsigned int) 0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA       ((unsigned int) 0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-typedef struct _AT91S_TWI {
-	AT91_REG	 TWI_CR; 	// Control Register
-	AT91_REG	 TWI_MMR; 	// Master Mode Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 TWI_IADR; 	// Internal Address Register
-	AT91_REG	 TWI_CWGR; 	// Clock Waveform Generator Register
-	AT91_REG	 Reserved1[3]; 	// 
-	AT91_REG	 TWI_SR; 	// Status Register
-	AT91_REG	 TWI_IER; 	// Interrupt Enable Register
-	AT91_REG	 TWI_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TWI_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TWI_RHR; 	// Receive Holding Register
-	AT91_REG	 TWI_THR; 	// Transmit Holding Register
-} AT91S_TWI, *AT91PS_TWI;
-
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-#define AT91C_TWI_START       ((unsigned int) 0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP        ((unsigned int) 0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN        ((unsigned int) 0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS       ((unsigned int) 0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST       ((unsigned int) 0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-#define AT91C_TWI_IADRSZ      ((unsigned int) 0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   ((unsigned int) 0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               ((unsigned int) 0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               ((unsigned int) 0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               ((unsigned int) 0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD       ((unsigned int) 0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR        ((unsigned int) 0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-#define AT91C_TWI_CLDIV       ((unsigned int) 0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV       ((unsigned int) 0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV       ((unsigned int) 0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-#define AT91C_TWI_TXCOMP      ((unsigned int) 0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY       ((unsigned int) 0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY       ((unsigned int) 0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE        ((unsigned int) 0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE        ((unsigned int) 0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK        ((unsigned int) 0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC_CH {
-	AT91_REG	 PWMC_CMR; 	// Channel Mode Register
-	AT91_REG	 PWMC_CDTYR; 	// Channel Duty Cycle Register
-	AT91_REG	 PWMC_CPRDR; 	// Channel Period Register
-	AT91_REG	 PWMC_CCNTR; 	// Channel Counter Register
-	AT91_REG	 PWMC_CUPDR; 	// Channel Update Register
-	AT91_REG	 PWMC_Reserved[3]; 	// Reserved
-} AT91S_PWMC_CH, *AT91PS_PWMC_CH;
-
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-#define AT91C_PWMC_CPRE       ((unsigned int) 0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  ((unsigned int) 0x0) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKA                 ((unsigned int) 0xB) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKB                 ((unsigned int) 0xC) // (PWMC_CH) 
-#define AT91C_PWMC_CALG       ((unsigned int) 0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL       ((unsigned int) 0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD        ((unsigned int) 0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-#define AT91C_PWMC_CDTY       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-#define AT91C_PWMC_CPRD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-#define AT91C_PWMC_CCNT       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-#define AT91C_PWMC_CUPD       ((unsigned int) 0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-typedef struct _AT91S_PWMC {
-	AT91_REG	 PWMC_MR; 	// PWMC Mode Register
-	AT91_REG	 PWMC_ENA; 	// PWMC Enable Register
-	AT91_REG	 PWMC_DIS; 	// PWMC Disable Register
-	AT91_REG	 PWMC_SR; 	// PWMC Status Register
-	AT91_REG	 PWMC_IER; 	// PWMC Interrupt Enable Register
-	AT91_REG	 PWMC_IDR; 	// PWMC Interrupt Disable Register
-	AT91_REG	 PWMC_IMR; 	// PWMC Interrupt Mask Register
-	AT91_REG	 PWMC_ISR; 	// PWMC Interrupt Status Register
-	AT91_REG	 Reserved0[55]; 	// 
-	AT91_REG	 PWMC_VR; 	// PWMC Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_PWMC_CH	 PWMC_CH[4]; 	// PWMC Channel
-} AT91S_PWMC, *AT91PS_PWMC;
-
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-#define AT91C_PWMC_DIVA       ((unsigned int) 0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA       ((unsigned int) 0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  ((unsigned int) 0x0 <<  8) // (PWMC) 
-#define AT91C_PWMC_DIVB       ((unsigned int) 0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB       ((unsigned int) 0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  ((unsigned int) 0x0 << 24) // (PWMC) 
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-#define AT91C_PWMC_CHID0      ((unsigned int) 0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1      ((unsigned int) 0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2      ((unsigned int) 0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3      ((unsigned int) 0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-typedef struct _AT91S_UDP {
-	AT91_REG	 UDP_NUM; 	// Frame Number Register
-	AT91_REG	 UDP_GLBSTATE; 	// Global State Register
-	AT91_REG	 UDP_FADDR; 	// Function Address Register
-	AT91_REG	 Reserved0[1]; 	// 
-	AT91_REG	 UDP_IER; 	// Interrupt Enable Register
-	AT91_REG	 UDP_IDR; 	// Interrupt Disable Register
-	AT91_REG	 UDP_IMR; 	// Interrupt Mask Register
-	AT91_REG	 UDP_ISR; 	// Interrupt Status Register
-	AT91_REG	 UDP_ICR; 	// Interrupt Clear Register
-	AT91_REG	 Reserved1[1]; 	// 
-	AT91_REG	 UDP_RSTEP; 	// Reset Endpoint Register
-	AT91_REG	 Reserved2[1]; 	// 
-	AT91_REG	 UDP_CSR[6]; 	// Endpoint Control and Status Register
-	AT91_REG	 Reserved3[2]; 	// 
-	AT91_REG	 UDP_FDR[6]; 	// Endpoint FIFO Data Register
-	AT91_REG	 Reserved4[3]; 	// 
-	AT91_REG	 UDP_TXVC; 	// Transceiver Control Register
-} AT91S_UDP, *AT91PS_UDP;
-
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-#define AT91C_UDP_FRM_NUM     ((unsigned int) 0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR     ((unsigned int) 0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK      ((unsigned int) 0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-#define AT91C_UDP_FADDEN      ((unsigned int) 0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG       ((unsigned int) 0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR         ((unsigned int) 0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR     ((unsigned int) 0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE      ((unsigned int) 0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-#define AT91C_UDP_FADD        ((unsigned int) 0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN         ((unsigned int) 0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-#define AT91C_UDP_EPINT0      ((unsigned int) 0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1      ((unsigned int) 0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2      ((unsigned int) 0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3      ((unsigned int) 0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4      ((unsigned int) 0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5      ((unsigned int) 0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP      ((unsigned int) 0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM       ((unsigned int) 0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM      ((unsigned int) 0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT      ((unsigned int) 0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP      ((unsigned int) 0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-#define AT91C_UDP_ENDBUSRES   ((unsigned int) 0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-#define AT91C_UDP_EP0         ((unsigned int) 0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1         ((unsigned int) 0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2         ((unsigned int) 0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3         ((unsigned int) 0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4         ((unsigned int) 0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5         ((unsigned int) 0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-#define AT91C_UDP_TXCOMP      ((unsigned int) 0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0 ((unsigned int) 0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP     ((unsigned int) 0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR    ((unsigned int) 0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY    ((unsigned int) 0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL  ((unsigned int) 0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1 ((unsigned int) 0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR         ((unsigned int) 0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE      ((unsigned int) 0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 ((unsigned int) 0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              ((unsigned int) 0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             ((unsigned int) 0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              ((unsigned int) 0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               ((unsigned int) 0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              ((unsigned int) 0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               ((unsigned int) 0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE       ((unsigned int) 0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS       ((unsigned int) 0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT   ((unsigned int) 0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
-#define AT91C_UDP_TXVDIS      ((unsigned int) 0x1 <<  8) // (UDP) 
-#define AT91C_UDP_PUON        ((unsigned int) 0x1 <<  9) // (UDP) Pull-up ON
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-typedef struct _AT91S_TC {
-	AT91_REG	 TC_CCR; 	// Channel Control Register
-	AT91_REG	 TC_CMR; 	// Channel Mode Register (Capture Mode / Waveform Mode)
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TC_CV; 	// Counter Value
-	AT91_REG	 TC_RA; 	// Register A
-	AT91_REG	 TC_RB; 	// Register B
-	AT91_REG	 TC_RC; 	// Register C
-	AT91_REG	 TC_SR; 	// Status Register
-	AT91_REG	 TC_IER; 	// Interrupt Enable Register
-	AT91_REG	 TC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TC_IMR; 	// Interrupt Mask Register
-} AT91S_TC, *AT91PS_TC;
-
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-#define AT91C_TC_CLKEN        ((unsigned int) 0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS       ((unsigned int) 0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG        ((unsigned int) 0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-#define AT91C_TC_CLKS         ((unsigned int) 0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     ((unsigned int) 0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     ((unsigned int) 0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     ((unsigned int) 0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     ((unsigned int) 0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     ((unsigned int) 0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  ((unsigned int) 0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  ((unsigned int) 0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  ((unsigned int) 0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI         ((unsigned int) 0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST        ((unsigned int) 0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 ((unsigned int) 0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  ((unsigned int) 0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  ((unsigned int) 0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  ((unsigned int) 0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP      ((unsigned int) 0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS       ((unsigned int) 0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG      ((unsigned int) 0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG      ((unsigned int) 0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 ((unsigned int) 0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               ((unsigned int) 0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              ((unsigned int) 0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 ((unsigned int) 0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT         ((unsigned int) 0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 ((unsigned int) 0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  ((unsigned int) 0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  ((unsigned int) 0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  ((unsigned int) 0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG       ((unsigned int) 0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG       ((unsigned int) 0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL      ((unsigned int) 0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   ((unsigned int) 0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               ((unsigned int) 0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              ((unsigned int) 0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          ((unsigned int) 0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG       ((unsigned int) 0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE         ((unsigned int) 0x1 << 15) // (TC) 
-#define AT91C_TC_ACPA         ((unsigned int) 0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  ((unsigned int) 0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                ((unsigned int) 0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               ((unsigned int) 0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA         ((unsigned int) 0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 ((unsigned int) 0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               ((unsigned int) 0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              ((unsigned int) 0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 ((unsigned int) 0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC         ((unsigned int) 0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 ((unsigned int) 0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  ((unsigned int) 0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                ((unsigned int) 0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               ((unsigned int) 0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB         ((unsigned int) 0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 ((unsigned int) 0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               ((unsigned int) 0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              ((unsigned int) 0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 ((unsigned int) 0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT        ((unsigned int) 0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 ((unsigned int) 0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  ((unsigned int) 0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                ((unsigned int) 0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               ((unsigned int) 0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG       ((unsigned int) 0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 ((unsigned int) 0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  ((unsigned int) 0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                ((unsigned int) 0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               ((unsigned int) 0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB         ((unsigned int) 0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 ((unsigned int) 0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  ((unsigned int) 0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                ((unsigned int) 0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               ((unsigned int) 0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC         ((unsigned int) 0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 ((unsigned int) 0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  ((unsigned int) 0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                ((unsigned int) 0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               ((unsigned int) 0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT        ((unsigned int) 0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 ((unsigned int) 0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  ((unsigned int) 0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                ((unsigned int) 0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               ((unsigned int) 0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG       ((unsigned int) 0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 ((unsigned int) 0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  ((unsigned int) 0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                ((unsigned int) 0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               ((unsigned int) 0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-#define AT91C_TC_COVFS        ((unsigned int) 0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS        ((unsigned int) 0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS         ((unsigned int) 0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS         ((unsigned int) 0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS         ((unsigned int) 0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS        ((unsigned int) 0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS        ((unsigned int) 0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS        ((unsigned int) 0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA       ((unsigned int) 0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA        ((unsigned int) 0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB        ((unsigned int) 0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-typedef struct _AT91S_TCB {
-	AT91S_TC	 TCB_TC0; 	// TC Channel 0
-	AT91_REG	 Reserved0[4]; 	// 
-	AT91S_TC	 TCB_TC1; 	// TC Channel 1
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91S_TC	 TCB_TC2; 	// TC Channel 2
-	AT91_REG	 Reserved2[4]; 	// 
-	AT91_REG	 TCB_BCR; 	// TC Block Control Register
-	AT91_REG	 TCB_BMR; 	// TC Block Mode Register
-} AT91S_TCB, *AT91PS_TCB;
-
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-#define AT91C_TCB_SYNC        ((unsigned int) 0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-#define AT91C_TCB_TC0XC0S     ((unsigned int) 0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                ((unsigned int) 0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 ((unsigned int) 0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                ((unsigned int) 0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                ((unsigned int) 0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S     ((unsigned int) 0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                ((unsigned int) 0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 ((unsigned int) 0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                ((unsigned int) 0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                ((unsigned int) 0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S     ((unsigned int) 0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                ((unsigned int) 0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 ((unsigned int) 0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                ((unsigned int) 0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                ((unsigned int) 0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN_MB {
-	AT91_REG	 CAN_MB_MMR; 	// MailBox Mode Register
-	AT91_REG	 CAN_MB_MAM; 	// MailBox Acceptance Mask Register
-	AT91_REG	 CAN_MB_MID; 	// MailBox ID Register
-	AT91_REG	 CAN_MB_MFID; 	// MailBox Family ID Register
-	AT91_REG	 CAN_MB_MSR; 	// MailBox Status Register
-	AT91_REG	 CAN_MB_MDL; 	// MailBox Data Low Register
-	AT91_REG	 CAN_MB_MDH; 	// MailBox Data High Register
-	AT91_REG	 CAN_MB_MCR; 	// MailBox Control Register
-} AT91S_CAN_MB, *AT91PS_CAN_MB;
-
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
-#define AT91C_CAN_MTIMEMARK   ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR       ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT         ((unsigned int) 0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define 	AT91C_CAN_MOT_DIS                  ((unsigned int) 0x0 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RX                   ((unsigned int) 0x1 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RXOVERWRITE          ((unsigned int) 0x2 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_TX                   ((unsigned int) 0x3 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_CONSUMER             ((unsigned int) 0x4 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_PRODUCER             ((unsigned int) 0x5 << 24) // (CAN_MB) 
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
-#define AT91C_CAN_MIDvB       ((unsigned int) 0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA       ((unsigned int) 0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE        ((unsigned int) 0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
-#define AT91C_CAN_MTIMESTAMP  ((unsigned int) 0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC        ((unsigned int) 0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR        ((unsigned int) 0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT        ((unsigned int) 0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI         ((unsigned int) 0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
-#define AT91C_CAN_MACR        ((unsigned int) 0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR        ((unsigned int) 0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-typedef struct _AT91S_CAN {
-	AT91_REG	 CAN_MR; 	// Mode Register
-	AT91_REG	 CAN_IER; 	// Interrupt Enable Register
-	AT91_REG	 CAN_IDR; 	// Interrupt Disable Register
-	AT91_REG	 CAN_IMR; 	// Interrupt Mask Register
-	AT91_REG	 CAN_SR; 	// Status Register
-	AT91_REG	 CAN_BR; 	// Baudrate Register
-	AT91_REG	 CAN_TIM; 	// Timer Register
-	AT91_REG	 CAN_TIMESTP; 	// Time Stamp Register
-	AT91_REG	 CAN_ECR; 	// Error Counter Register
-	AT91_REG	 CAN_TCR; 	// Transfer Command Register
-	AT91_REG	 CAN_ACR; 	// Abort Command Register
-	AT91_REG	 Reserved0[52]; 	// 
-	AT91_REG	 CAN_VR; 	// Version Register
-	AT91_REG	 Reserved1[64]; 	// 
-	AT91S_CAN_MB	 CAN_MB0; 	// CAN Mailbox 0
-	AT91S_CAN_MB	 CAN_MB1; 	// CAN Mailbox 1
-	AT91S_CAN_MB	 CAN_MB2; 	// CAN Mailbox 2
-	AT91S_CAN_MB	 CAN_MB3; 	// CAN Mailbox 3
-	AT91S_CAN_MB	 CAN_MB4; 	// CAN Mailbox 4
-	AT91S_CAN_MB	 CAN_MB5; 	// CAN Mailbox 5
-	AT91S_CAN_MB	 CAN_MB6; 	// CAN Mailbox 6
-	AT91S_CAN_MB	 CAN_MB7; 	// CAN Mailbox 7
-	AT91S_CAN_MB	 CAN_MB8; 	// CAN Mailbox 8
-	AT91S_CAN_MB	 CAN_MB9; 	// CAN Mailbox 9
-	AT91S_CAN_MB	 CAN_MB10; 	// CAN Mailbox 10
-	AT91S_CAN_MB	 CAN_MB11; 	// CAN Mailbox 11
-	AT91S_CAN_MB	 CAN_MB12; 	// CAN Mailbox 12
-	AT91S_CAN_MB	 CAN_MB13; 	// CAN Mailbox 13
-	AT91S_CAN_MB	 CAN_MB14; 	// CAN Mailbox 14
-	AT91S_CAN_MB	 CAN_MB15; 	// CAN Mailbox 15
-} AT91S_CAN, *AT91PS_CAN;
-
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
-#define AT91C_CAN_CANEN       ((unsigned int) 0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM         ((unsigned int) 0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM         ((unsigned int) 0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL         ((unsigned int) 0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF        ((unsigned int) 0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM         ((unsigned int) 0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ      ((unsigned int) 0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT        ((unsigned int) 0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
-#define AT91C_CAN_MB0         ((unsigned int) 0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1         ((unsigned int) 0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2         ((unsigned int) 0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3         ((unsigned int) 0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4         ((unsigned int) 0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5         ((unsigned int) 0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6         ((unsigned int) 0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7         ((unsigned int) 0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8         ((unsigned int) 0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9         ((unsigned int) 0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10        ((unsigned int) 0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11        ((unsigned int) 0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12        ((unsigned int) 0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13        ((unsigned int) 0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14        ((unsigned int) 0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15        ((unsigned int) 0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA        ((unsigned int) 0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN        ((unsigned int) 0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP        ((unsigned int) 0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF        ((unsigned int) 0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP       ((unsigned int) 0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP      ((unsigned int) 0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF        ((unsigned int) 0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP        ((unsigned int) 0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR        ((unsigned int) 0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR        ((unsigned int) 0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR        ((unsigned int) 0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR        ((unsigned int) 0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR        ((unsigned int) 0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
-#define AT91C_CAN_RBSY        ((unsigned int) 0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY        ((unsigned int) 0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY        ((unsigned int) 0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
-#define AT91C_CAN_PHASE2      ((unsigned int) 0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1      ((unsigned int) 0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG      ((unsigned int) 0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC        ((unsigned int) 0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP         ((unsigned int) 0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP         ((unsigned int) 0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
-#define AT91C_CAN_TIMER       ((unsigned int) 0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
-#define AT91C_CAN_REC         ((unsigned int) 0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC         ((unsigned int) 0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
-#define AT91C_CAN_TIMRST      ((unsigned int) 0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-typedef struct _AT91S_EMAC {
-	AT91_REG	 EMAC_NCR; 	// Network Control Register
-	AT91_REG	 EMAC_NCFGR; 	// Network Configuration Register
-	AT91_REG	 EMAC_NSR; 	// Network Status Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 EMAC_TSR; 	// Transmit Status Register
-	AT91_REG	 EMAC_RBQP; 	// Receive Buffer Queue Pointer
-	AT91_REG	 EMAC_TBQP; 	// Transmit Buffer Queue Pointer
-	AT91_REG	 EMAC_RSR; 	// Receive Status Register
-	AT91_REG	 EMAC_ISR; 	// Interrupt Status Register
-	AT91_REG	 EMAC_IER; 	// Interrupt Enable Register
-	AT91_REG	 EMAC_IDR; 	// Interrupt Disable Register
-	AT91_REG	 EMAC_IMR; 	// Interrupt Mask Register
-	AT91_REG	 EMAC_MAN; 	// PHY Maintenance Register
-	AT91_REG	 EMAC_PTR; 	// Pause Time Register
-	AT91_REG	 EMAC_PFR; 	// Pause Frames received Register
-	AT91_REG	 EMAC_FTO; 	// Frames Transmitted OK Register
-	AT91_REG	 EMAC_SCF; 	// Single Collision Frame Register
-	AT91_REG	 EMAC_MCF; 	// Multiple Collision Frame Register
-	AT91_REG	 EMAC_FRO; 	// Frames Received OK Register
-	AT91_REG	 EMAC_FCSE; 	// Frame Check Sequence Error Register
-	AT91_REG	 EMAC_ALE; 	// Alignment Error Register
-	AT91_REG	 EMAC_DTF; 	// Deferred Transmission Frame Register
-	AT91_REG	 EMAC_LCOL; 	// Late Collision Register
-	AT91_REG	 EMAC_ECOL; 	// Excessive Collision Register
-	AT91_REG	 EMAC_TUND; 	// Transmit Underrun Error Register
-	AT91_REG	 EMAC_CSE; 	// Carrier Sense Error Register
-	AT91_REG	 EMAC_RRE; 	// Receive Ressource Error Register
-	AT91_REG	 EMAC_ROV; 	// Receive Overrun Errors Register
-	AT91_REG	 EMAC_RSE; 	// Receive Symbol Errors Register
-	AT91_REG	 EMAC_ELE; 	// Excessive Length Errors Register
-	AT91_REG	 EMAC_RJA; 	// Receive Jabbers Register
-	AT91_REG	 EMAC_USF; 	// Undersize Frames Register
-	AT91_REG	 EMAC_STE; 	// SQE Test Error Register
-	AT91_REG	 EMAC_RLE; 	// Receive Length Field Mismatch Register
-	AT91_REG	 EMAC_TPF; 	// Transmitted Pause Frames Register
-	AT91_REG	 EMAC_HRB; 	// Hash Address Bottom[31:0]
-	AT91_REG	 EMAC_HRT; 	// Hash Address Top[63:32]
-	AT91_REG	 EMAC_SA1L; 	// Specific Address 1 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA1H; 	// Specific Address 1 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA2L; 	// Specific Address 2 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA2H; 	// Specific Address 2 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA3L; 	// Specific Address 3 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA3H; 	// Specific Address 3 Top, Last 2 bytes
-	AT91_REG	 EMAC_SA4L; 	// Specific Address 4 Bottom, First 4 bytes
-	AT91_REG	 EMAC_SA4H; 	// Specific Address 4 Top, Last 2 bytes
-	AT91_REG	 EMAC_TID; 	// Type ID Checking Register
-	AT91_REG	 EMAC_TPQ; 	// Transmit Pause Quantum Register
-	AT91_REG	 EMAC_USRIO; 	// USER Input/Output Register
-	AT91_REG	 EMAC_WOL; 	// Wake On LAN Register
-	AT91_REG	 Reserved1[13]; 	// 
-	AT91_REG	 EMAC_REV; 	// Revision Register
-} AT91S_EMAC, *AT91PS_EMAC;
-
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
-#define AT91C_EMAC_LB         ((unsigned int) 0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB        ((unsigned int) 0x1 <<  1) // (EMAC) Loopback local. 
-#define AT91C_EMAC_RE         ((unsigned int) 0x1 <<  2) // (EMAC) Receive enable. 
-#define AT91C_EMAC_TE         ((unsigned int) 0x1 <<  3) // (EMAC) Transmit enable. 
-#define AT91C_EMAC_MPE        ((unsigned int) 0x1 <<  4) // (EMAC) Management port enable. 
-#define AT91C_EMAC_CLRSTAT    ((unsigned int) 0x1 <<  5) // (EMAC) Clear statistics registers. 
-#define AT91C_EMAC_INCSTAT    ((unsigned int) 0x1 <<  6) // (EMAC) Increment statistics registers. 
-#define AT91C_EMAC_WESTAT     ((unsigned int) 0x1 <<  7) // (EMAC) Write enable for statistics registers. 
-#define AT91C_EMAC_BP         ((unsigned int) 0x1 <<  8) // (EMAC) Back pressure. 
-#define AT91C_EMAC_TSTART     ((unsigned int) 0x1 <<  9) // (EMAC) Start Transmission. 
-#define AT91C_EMAC_THALT      ((unsigned int) 0x1 << 10) // (EMAC) Transmission Halt. 
-#define AT91C_EMAC_TPFR       ((unsigned int) 0x1 << 11) // (EMAC) Transmit pause frame 
-#define AT91C_EMAC_TZQ        ((unsigned int) 0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
-#define AT91C_EMAC_SPD        ((unsigned int) 0x1 <<  0) // (EMAC) Speed. 
-#define AT91C_EMAC_FD         ((unsigned int) 0x1 <<  1) // (EMAC) Full duplex. 
-#define AT91C_EMAC_JFRAME     ((unsigned int) 0x1 <<  3) // (EMAC) Jumbo Frames. 
-#define AT91C_EMAC_CAF        ((unsigned int) 0x1 <<  4) // (EMAC) Copy all frames. 
-#define AT91C_EMAC_NBC        ((unsigned int) 0x1 <<  5) // (EMAC) No broadcast. 
-#define AT91C_EMAC_MTI        ((unsigned int) 0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI        ((unsigned int) 0x1 <<  7) // (EMAC) Unicast hash enable. 
-#define AT91C_EMAC_BIG        ((unsigned int) 0x1 <<  8) // (EMAC) Receive 1522 bytes. 
-#define AT91C_EMAC_EAE        ((unsigned int) 0x1 <<  9) // (EMAC) External address match enable. 
-#define AT91C_EMAC_CLK        ((unsigned int) 0x3 << 10) // (EMAC) 
-#define 	AT91C_EMAC_CLK_HCLK_8               ((unsigned int) 0x0 << 10) // (EMAC) HCLK divided by 8
-#define 	AT91C_EMAC_CLK_HCLK_16              ((unsigned int) 0x1 << 10) // (EMAC) HCLK divided by 16
-#define 	AT91C_EMAC_CLK_HCLK_32              ((unsigned int) 0x2 << 10) // (EMAC) HCLK divided by 32
-#define 	AT91C_EMAC_CLK_HCLK_64              ((unsigned int) 0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY        ((unsigned int) 0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PAE        ((unsigned int) 0x1 << 13) // (EMAC) 
-#define AT91C_EMAC_RBOF       ((unsigned int) 0x3 << 14) // (EMAC) 
-#define 	AT91C_EMAC_RBOF_OFFSET_0             ((unsigned int) 0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_1             ((unsigned int) 0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_2             ((unsigned int) 0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_3             ((unsigned int) 0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE       ((unsigned int) 0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS      ((unsigned int) 0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD      ((unsigned int) 0x1 << 18) // (EMAC) 
-#define AT91C_EMAC_IRXFCS     ((unsigned int) 0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
-#define AT91C_EMAC_LINKR      ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_MDIO       ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_IDLE       ((unsigned int) 0x1 <<  2) // (EMAC) 
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
-#define AT91C_EMAC_UBR        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_COL        ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RLES       ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TGO        ((unsigned int) 0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX        ((unsigned int) 0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_UND        ((unsigned int) 0x1 <<  6) // (EMAC) 
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-#define AT91C_EMAC_BNA        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_REC        ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_OVR        ((unsigned int) 0x1 <<  2) // (EMAC) 
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-#define AT91C_EMAC_MFD        ((unsigned int) 0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_RCOMP      ((unsigned int) 0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RXUBR      ((unsigned int) 0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TXUBR      ((unsigned int) 0x1 <<  3) // (EMAC) 
-#define AT91C_EMAC_TUNDR      ((unsigned int) 0x1 <<  4) // (EMAC) 
-#define AT91C_EMAC_RLEX       ((unsigned int) 0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_TXERR      ((unsigned int) 0x1 <<  6) // (EMAC) 
-#define AT91C_EMAC_TCOMP      ((unsigned int) 0x1 <<  7) // (EMAC) 
-#define AT91C_EMAC_LINK       ((unsigned int) 0x1 <<  9) // (EMAC) 
-#define AT91C_EMAC_ROVR       ((unsigned int) 0x1 << 10) // (EMAC) 
-#define AT91C_EMAC_HRESP      ((unsigned int) 0x1 << 11) // (EMAC) 
-#define AT91C_EMAC_PFRE       ((unsigned int) 0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PTZ        ((unsigned int) 0x1 << 13) // (EMAC) 
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-#define AT91C_EMAC_DATA       ((unsigned int) 0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_CODE       ((unsigned int) 0x3 << 16) // (EMAC) 
-#define AT91C_EMAC_REGA       ((unsigned int) 0x1F << 18) // (EMAC) 
-#define AT91C_EMAC_PHYA       ((unsigned int) 0x1F << 23) // (EMAC) 
-#define AT91C_EMAC_RW         ((unsigned int) 0x3 << 28) // (EMAC) 
-#define AT91C_EMAC_SOF        ((unsigned int) 0x3 << 30) // (EMAC) 
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
-#define AT91C_EMAC_RMII       ((unsigned int) 0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
-#define AT91C_EMAC_IP         ((unsigned int) 0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG        ((unsigned int) 0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP        ((unsigned int) 0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1        ((unsigned int) 0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
-#define AT91C_EMAC_REVREF     ((unsigned int) 0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_PARTREF    ((unsigned int) 0xFFFF << 16) // (EMAC) 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-typedef struct _AT91S_ADC {
-	AT91_REG	 ADC_CR; 	// ADC Control Register
-	AT91_REG	 ADC_MR; 	// ADC Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 ADC_CHER; 	// ADC Channel Enable Register
-	AT91_REG	 ADC_CHDR; 	// ADC Channel Disable Register
-	AT91_REG	 ADC_CHSR; 	// ADC Channel Status Register
-	AT91_REG	 ADC_SR; 	// ADC Status Register
-	AT91_REG	 ADC_LCDR; 	// ADC Last Converted Data Register
-	AT91_REG	 ADC_IER; 	// ADC Interrupt Enable Register
-	AT91_REG	 ADC_IDR; 	// ADC Interrupt Disable Register
-	AT91_REG	 ADC_IMR; 	// ADC Interrupt Mask Register
-	AT91_REG	 ADC_CDR0; 	// ADC Channel Data Register 0
-	AT91_REG	 ADC_CDR1; 	// ADC Channel Data Register 1
-	AT91_REG	 ADC_CDR2; 	// ADC Channel Data Register 2
-	AT91_REG	 ADC_CDR3; 	// ADC Channel Data Register 3
-	AT91_REG	 ADC_CDR4; 	// ADC Channel Data Register 4
-	AT91_REG	 ADC_CDR5; 	// ADC Channel Data Register 5
-	AT91_REG	 ADC_CDR6; 	// ADC Channel Data Register 6
-	AT91_REG	 ADC_CDR7; 	// ADC Channel Data Register 7
-	AT91_REG	 Reserved1[44]; 	// 
-	AT91_REG	 ADC_RPR; 	// Receive Pointer Register
-	AT91_REG	 ADC_RCR; 	// Receive Counter Register
-	AT91_REG	 ADC_TPR; 	// Transmit Pointer Register
-	AT91_REG	 ADC_TCR; 	// Transmit Counter Register
-	AT91_REG	 ADC_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 ADC_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 ADC_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 ADC_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 ADC_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 ADC_PTSR; 	// PDC Transfer Status Register
-} AT91S_ADC, *AT91PS_ADC;
-
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-#define AT91C_ADC_SWRST       ((unsigned int) 0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START       ((unsigned int) 0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-#define AT91C_ADC_TRGEN       ((unsigned int) 0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  ((unsigned int) 0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   ((unsigned int) 0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL      ((unsigned int) 0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                ((unsigned int) 0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                ((unsigned int) 0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                ((unsigned int) 0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                ((unsigned int) 0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                ((unsigned int) 0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                ((unsigned int) 0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  ((unsigned int) 0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES      ((unsigned int) 0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               ((unsigned int) 0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                ((unsigned int) 0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP       ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          ((unsigned int) 0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 ((unsigned int) 0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL     ((unsigned int) 0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP     ((unsigned int) 0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM       ((unsigned int) 0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-#define AT91C_ADC_CH0         ((unsigned int) 0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1         ((unsigned int) 0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2         ((unsigned int) 0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3         ((unsigned int) 0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4         ((unsigned int) 0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5         ((unsigned int) 0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6         ((unsigned int) 0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7         ((unsigned int) 0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-#define AT91C_ADC_EOC0        ((unsigned int) 0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1        ((unsigned int) 0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2        ((unsigned int) 0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3        ((unsigned int) 0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4        ((unsigned int) 0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5        ((unsigned int) 0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6        ((unsigned int) 0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7        ((unsigned int) 0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0       ((unsigned int) 0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1       ((unsigned int) 0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2       ((unsigned int) 0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3       ((unsigned int) 0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4       ((unsigned int) 0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5       ((unsigned int) 0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6       ((unsigned int) 0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7       ((unsigned int) 0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY        ((unsigned int) 0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE       ((unsigned int) 0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX       ((unsigned int) 0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF      ((unsigned int) 0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-#define AT91C_ADC_LDATA       ((unsigned int) 0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-#define AT91C_ADC_DATA        ((unsigned int) 0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_AES {
-	AT91_REG	 AES_CR; 	// Control Register
-	AT91_REG	 AES_MR; 	// Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 AES_IER; 	// Interrupt Enable Register
-	AT91_REG	 AES_IDR; 	// Interrupt Disable Register
-	AT91_REG	 AES_IMR; 	// Interrupt Mask Register
-	AT91_REG	 AES_ISR; 	// Interrupt Status Register
-	AT91_REG	 AES_KEYWxR[4]; 	// Key Word x Register
-	AT91_REG	 Reserved1[4]; 	// 
-	AT91_REG	 AES_IDATAxR[4]; 	// Input Data x Register
-	AT91_REG	 AES_ODATAxR[4]; 	// Output Data x Register
-	AT91_REG	 AES_IVxR[4]; 	// Initialization Vector x Register
-	AT91_REG	 Reserved2[35]; 	// 
-	AT91_REG	 AES_VR; 	// AES Version Register
-	AT91_REG	 AES_RPR; 	// Receive Pointer Register
-	AT91_REG	 AES_RCR; 	// Receive Counter Register
-	AT91_REG	 AES_TPR; 	// Transmit Pointer Register
-	AT91_REG	 AES_TCR; 	// Transmit Counter Register
-	AT91_REG	 AES_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 AES_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 AES_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 AES_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 AES_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 AES_PTSR; 	// PDC Transfer Status Register
-} AT91S_AES, *AT91PS_AES;
-
-// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
-#define AT91C_AES_START       ((unsigned int) 0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST       ((unsigned int) 0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED    ((unsigned int) 0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
-#define AT91C_AES_CIPHER      ((unsigned int) 0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY     ((unsigned int) 0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD        ((unsigned int) 0x3 <<  8) // (AES) Start Mode
-#define 	AT91C_AES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define 	AT91C_AES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define 	AT91C_AES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD       ((unsigned int) 0x7 << 12) // (AES) Operation Mode
-#define 	AT91C_AES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define 	AT91C_AES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define 	AT91C_AES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (AES) OFB Output Feedback mode.
-#define 	AT91C_AES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define 	AT91C_AES_OPMOD_CTR                  ((unsigned int) 0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD         ((unsigned int) 0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS        ((unsigned int) 0x7 << 16) // (AES) Cipher Feedback Data Size
-#define 	AT91C_AES_CFBS_128_BIT              ((unsigned int) 0x0 << 16) // (AES) 128-bit.
-#define 	AT91C_AES_CFBS_64_BIT               ((unsigned int) 0x1 << 16) // (AES) 64-bit.
-#define 	AT91C_AES_CFBS_32_BIT               ((unsigned int) 0x2 << 16) // (AES) 32-bit.
-#define 	AT91C_AES_CFBS_16_BIT               ((unsigned int) 0x3 << 16) // (AES) 16-bit.
-#define 	AT91C_AES_CFBS_8_BIT                ((unsigned int) 0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY        ((unsigned int) 0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE       ((unsigned int) 0x1F << 24) // (AES) Countermeasure Type
-#define 	AT91C_AES_CTYPE_TYPE1_EN             ((unsigned int) 0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE2_EN             ((unsigned int) 0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE3_EN             ((unsigned int) 0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE4_EN             ((unsigned int) 0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE5_EN             ((unsigned int) 0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_AES_DATRDY      ((unsigned int) 0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX       ((unsigned int) 0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX       ((unsigned int) 0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF      ((unsigned int) 0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE      ((unsigned int) 0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD        ((unsigned int) 0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_AES_URAT        ((unsigned int) 0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (AES) Output data register read during the data processing.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (AES) Mode register written during the data processing.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  ((unsigned int) 0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY ((unsigned int) 0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define 	AT91C_AES_URAT_WO_REG_READ          ((unsigned int) 0x5 << 12) // (AES) Write-only register read access.
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-typedef struct _AT91S_TDES {
-	AT91_REG	 TDES_CR; 	// Control Register
-	AT91_REG	 TDES_MR; 	// Mode Register
-	AT91_REG	 Reserved0[2]; 	// 
-	AT91_REG	 TDES_IER; 	// Interrupt Enable Register
-	AT91_REG	 TDES_IDR; 	// Interrupt Disable Register
-	AT91_REG	 TDES_IMR; 	// Interrupt Mask Register
-	AT91_REG	 TDES_ISR; 	// Interrupt Status Register
-	AT91_REG	 TDES_KEY1WxR[2]; 	// Key 1 Word x Register
-	AT91_REG	 TDES_KEY2WxR[2]; 	// Key 2 Word x Register
-	AT91_REG	 TDES_KEY3WxR[2]; 	// Key 3 Word x Register
-	AT91_REG	 Reserved1[2]; 	// 
-	AT91_REG	 TDES_IDATAxR[2]; 	// Input Data x Register
-	AT91_REG	 Reserved2[2]; 	// 
-	AT91_REG	 TDES_ODATAxR[2]; 	// Output Data x Register
-	AT91_REG	 Reserved3[2]; 	// 
-	AT91_REG	 TDES_IVxR[2]; 	// Initialization Vector x Register
-	AT91_REG	 Reserved4[37]; 	// 
-	AT91_REG	 TDES_VR; 	// TDES Version Register
-	AT91_REG	 TDES_RPR; 	// Receive Pointer Register
-	AT91_REG	 TDES_RCR; 	// Receive Counter Register
-	AT91_REG	 TDES_TPR; 	// Transmit Pointer Register
-	AT91_REG	 TDES_TCR; 	// Transmit Counter Register
-	AT91_REG	 TDES_RNPR; 	// Receive Next Pointer Register
-	AT91_REG	 TDES_RNCR; 	// Receive Next Counter Register
-	AT91_REG	 TDES_TNPR; 	// Transmit Next Pointer Register
-	AT91_REG	 TDES_TNCR; 	// Transmit Next Counter Register
-	AT91_REG	 TDES_PTCR; 	// PDC Transfer Control Register
-	AT91_REG	 TDES_PTSR; 	// PDC Transfer Status Register
-} AT91S_TDES, *AT91PS_TDES;
-
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
-#define AT91C_TDES_START      ((unsigned int) 0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST      ((unsigned int) 0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
-#define AT91C_TDES_CIPHER     ((unsigned int) 0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD    ((unsigned int) 0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD     ((unsigned int) 0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD       ((unsigned int) 0x3 <<  8) // (TDES) Start Mode
-#define 	AT91C_TDES_SMOD_MANUAL               ((unsigned int) 0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define 	AT91C_TDES_SMOD_AUTO                 ((unsigned int) 0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define 	AT91C_TDES_SMOD_PDC                  ((unsigned int) 0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD      ((unsigned int) 0x3 << 12) // (TDES) Operation Mode
-#define 	AT91C_TDES_OPMOD_ECB                  ((unsigned int) 0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define 	AT91C_TDES_OPMOD_CBC                  ((unsigned int) 0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define 	AT91C_TDES_OPMOD_OFB                  ((unsigned int) 0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define 	AT91C_TDES_OPMOD_CFB                  ((unsigned int) 0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD        ((unsigned int) 0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS       ((unsigned int) 0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define 	AT91C_TDES_CFBS_64_BIT               ((unsigned int) 0x0 << 16) // (TDES) 64-bit.
-#define 	AT91C_TDES_CFBS_32_BIT               ((unsigned int) 0x1 << 16) // (TDES) 32-bit.
-#define 	AT91C_TDES_CFBS_16_BIT               ((unsigned int) 0x2 << 16) // (TDES) 16-bit.
-#define 	AT91C_TDES_CFBS_8_BIT                ((unsigned int) 0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_TDES_DATRDY     ((unsigned int) 0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX      ((unsigned int) 0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX      ((unsigned int) 0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF     ((unsigned int) 0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE     ((unsigned int) 0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD       ((unsigned int) 0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_TDES_URAT       ((unsigned int) 0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC ((unsigned int) 0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC ((unsigned int) 0x1 << 12) // (TDES) Output data register read during the data processing.
-#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC ((unsigned int) 0x2 << 12) // (TDES) Mode register written during the data processing.
-#define 	AT91C_TDES_URAT_WO_REG_READ          ((unsigned int) 0x3 << 12) // (TDES) Write-only register read access.
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ========== 
-// ========== Register definition for AIC peripheral ========== 
-#define AT91C_AIC_IVR   ((AT91_REG *) 	0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR   ((AT91_REG *) 	0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR   ((AT91_REG *) 	0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR   ((AT91_REG *) 	0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR ((AT91_REG *) 	0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR   ((AT91_REG *) 	0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR  ((AT91_REG *) 	0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR  ((AT91_REG *) 	0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR   ((AT91_REG *) 	0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR   ((AT91_REG *) 	0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR   ((AT91_REG *) 	0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER  ((AT91_REG *) 	0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR  ((AT91_REG *) 	0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR  ((AT91_REG *) 	0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR  ((AT91_REG *) 	0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR  ((AT91_REG *) 	0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR  ((AT91_REG *) 	0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU   ((AT91_REG *) 	0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ========== 
-#define AT91C_DBGU_TCR  ((AT91_REG *) 	0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR ((AT91_REG *) 	0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR ((AT91_REG *) 	0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR  ((AT91_REG *) 	0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR  ((AT91_REG *) 	0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR  ((AT91_REG *) 	0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR ((AT91_REG *) 	0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR ((AT91_REG *) 	0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR ((AT91_REG *) 	0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR ((AT91_REG *) 	0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ========== 
-#define AT91C_DBGU_EXID ((AT91_REG *) 	0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR ((AT91_REG *) 	0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR  ((AT91_REG *) 	0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR  ((AT91_REG *) 	0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR ((AT91_REG *) 	0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR   ((AT91_REG *) 	0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR  ((AT91_REG *) 	0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR   ((AT91_REG *) 	0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR ((AT91_REG *) 	0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR  ((AT91_REG *) 	0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR  ((AT91_REG *) 	0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER  ((AT91_REG *) 	0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ========== 
-#define AT91C_PIOA_ODR  ((AT91_REG *) 	0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR ((AT91_REG *) 	0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR  ((AT91_REG *) 	0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR ((AT91_REG *) 	0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER  ((AT91_REG *) 	0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR ((AT91_REG *) 	0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR  ((AT91_REG *) 	0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER  ((AT91_REG *) 	0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR ((AT91_REG *) 	0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR ((AT91_REG *) 	0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR ((AT91_REG *) 	0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR  ((AT91_REG *) 	0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR ((AT91_REG *) 	0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR ((AT91_REG *) 	0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR ((AT91_REG *) 	0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR  ((AT91_REG *) 	0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER ((AT91_REG *) 	0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER ((AT91_REG *) 	0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR ((AT91_REG *) 	0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER ((AT91_REG *) 	0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR  ((AT91_REG *) 	0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR  ((AT91_REG *) 	0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR ((AT91_REG *) 	0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR ((AT91_REG *) 	0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER ((AT91_REG *) 	0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR  ((AT91_REG *) 	0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR ((AT91_REG *) 	0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER  ((AT91_REG *) 	0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR  ((AT91_REG *) 	0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ========== 
-#define AT91C_PIOB_OWDR ((AT91_REG *) 	0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER ((AT91_REG *) 	0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR ((AT91_REG *) 	0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR  ((AT91_REG *) 	0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR  ((AT91_REG *) 	0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR ((AT91_REG *) 	0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR  ((AT91_REG *) 	0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER  ((AT91_REG *) 	0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR ((AT91_REG *) 	0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER ((AT91_REG *) 	0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR ((AT91_REG *) 	0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR ((AT91_REG *) 	0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR ((AT91_REG *) 	0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR  ((AT91_REG *) 	0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR ((AT91_REG *) 	0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR  ((AT91_REG *) 	0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR  ((AT91_REG *) 	0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR ((AT91_REG *) 	0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER ((AT91_REG *) 	0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR ((AT91_REG *) 	0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR  ((AT91_REG *) 	0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR ((AT91_REG *) 	0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR  ((AT91_REG *) 	0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR ((AT91_REG *) 	0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER ((AT91_REG *) 	0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR  ((AT91_REG *) 	0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR ((AT91_REG *) 	0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER  ((AT91_REG *) 	0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER  ((AT91_REG *) 	0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ========== 
-#define AT91C_CKGR_MOR  ((AT91_REG *) 	0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR ((AT91_REG *) 	0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR ((AT91_REG *) 	0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ========== 
-#define AT91C_PMC_IDR   ((AT91_REG *) 	0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR   ((AT91_REG *) 	0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR  ((AT91_REG *) 	0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER  ((AT91_REG *) 	0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR  ((AT91_REG *) 	0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR  ((AT91_REG *) 	0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR  ((AT91_REG *) 	0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR  ((AT91_REG *) 	0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR  ((AT91_REG *) 	0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR  ((AT91_REG *) 	0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR  ((AT91_REG *) 	0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER  ((AT91_REG *) 	0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR   ((AT91_REG *) 	0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER   ((AT91_REG *) 	0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR    ((AT91_REG *) 	0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ========== 
-#define AT91C_RSTC_RCR  ((AT91_REG *) 	0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR  ((AT91_REG *) 	0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR  ((AT91_REG *) 	0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ========== 
-#define AT91C_RTTC_RTSR ((AT91_REG *) 	0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR ((AT91_REG *) 	0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR ((AT91_REG *) 	0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR ((AT91_REG *) 	0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ========== 
-#define AT91C_PITC_PIVR ((AT91_REG *) 	0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR ((AT91_REG *) 	0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR ((AT91_REG *) 	0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR ((AT91_REG *) 	0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ========== 
-#define AT91C_WDTC_WDCR ((AT91_REG *) 	0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR ((AT91_REG *) 	0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR ((AT91_REG *) 	0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ========== 
-#define AT91C_VREG_MR   ((AT91_REG *) 	0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ========== 
-#define AT91C_MC_ASR    ((AT91_REG *) 	0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR    ((AT91_REG *) 	0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR    ((AT91_REG *) 	0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR   ((AT91_REG *) 	0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR    ((AT91_REG *) 	0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR    ((AT91_REG *) 	0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ========== 
-#define AT91C_SPI1_PTCR ((AT91_REG *) 	0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR  ((AT91_REG *) 	0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR ((AT91_REG *) 	0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR  ((AT91_REG *) 	0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR ((AT91_REG *) 	0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR  ((AT91_REG *) 	0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR  ((AT91_REG *) 	0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR ((AT91_REG *) 	0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR ((AT91_REG *) 	0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR ((AT91_REG *) 	0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ========== 
-#define AT91C_SPI1_IMR  ((AT91_REG *) 	0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER  ((AT91_REG *) 	0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR   ((AT91_REG *) 	0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR  ((AT91_REG *) 	0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR  ((AT91_REG *) 	0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR   ((AT91_REG *) 	0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR  ((AT91_REG *) 	0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR   ((AT91_REG *) 	0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR  ((AT91_REG *) 	0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ========== 
-#define AT91C_SPI0_PTCR ((AT91_REG *) 	0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR  ((AT91_REG *) 	0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR  ((AT91_REG *) 	0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR  ((AT91_REG *) 	0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR ((AT91_REG *) 	0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR ((AT91_REG *) 	0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR  ((AT91_REG *) 	0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR ((AT91_REG *) 	0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR ((AT91_REG *) 	0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR ((AT91_REG *) 	0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ========== 
-#define AT91C_SPI0_IER  ((AT91_REG *) 	0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR   ((AT91_REG *) 	0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR  ((AT91_REG *) 	0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR   ((AT91_REG *) 	0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR   ((AT91_REG *) 	0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR  ((AT91_REG *) 	0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR  ((AT91_REG *) 	0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR  ((AT91_REG *) 	0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR  ((AT91_REG *) 	0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ========== 
-#define AT91C_US1_RNCR  ((AT91_REG *) 	0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR  ((AT91_REG *) 	0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR   ((AT91_REG *) 	0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR  ((AT91_REG *) 	0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR  ((AT91_REG *) 	0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR   ((AT91_REG *) 	0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR  ((AT91_REG *) 	0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR   ((AT91_REG *) 	0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR  ((AT91_REG *) 	0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR   ((AT91_REG *) 	0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ========== 
-#define AT91C_US1_IF    ((AT91_REG *) 	0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER   ((AT91_REG *) 	0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR  ((AT91_REG *) 	0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR   ((AT91_REG *) 	0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR   ((AT91_REG *) 	0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER   ((AT91_REG *) 	0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR   ((AT91_REG *) 	0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR  ((AT91_REG *) 	0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR   ((AT91_REG *) 	0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR  ((AT91_REG *) 	0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR   ((AT91_REG *) 	0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI  ((AT91_REG *) 	0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR    ((AT91_REG *) 	0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR    ((AT91_REG *) 	0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ========== 
-#define AT91C_US0_TNPR  ((AT91_REG *) 	0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR  ((AT91_REG *) 	0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR   ((AT91_REG *) 	0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR  ((AT91_REG *) 	0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR  ((AT91_REG *) 	0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR  ((AT91_REG *) 	0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR   ((AT91_REG *) 	0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR   ((AT91_REG *) 	0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR   ((AT91_REG *) 	0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR  ((AT91_REG *) 	0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ========== 
-#define AT91C_US0_BRGR  ((AT91_REG *) 	0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER   ((AT91_REG *) 	0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR    ((AT91_REG *) 	0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR   ((AT91_REG *) 	0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI  ((AT91_REG *) 	0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR  ((AT91_REG *) 	0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR    ((AT91_REG *) 	0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR  ((AT91_REG *) 	0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR   ((AT91_REG *) 	0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR   ((AT91_REG *) 	0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR   ((AT91_REG *) 	0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR   ((AT91_REG *) 	0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF    ((AT91_REG *) 	0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER   ((AT91_REG *) 	0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ========== 
-#define AT91C_SSC_TNCR  ((AT91_REG *) 	0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR   ((AT91_REG *) 	0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR  ((AT91_REG *) 	0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR   ((AT91_REG *) 	0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR  ((AT91_REG *) 	0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR   ((AT91_REG *) 	0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR   ((AT91_REG *) 	0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR  ((AT91_REG *) 	0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR  ((AT91_REG *) 	0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR  ((AT91_REG *) 	0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ========== 
-#define AT91C_SSC_RHR   ((AT91_REG *) 	0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR  ((AT91_REG *) 	0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR  ((AT91_REG *) 	0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR   ((AT91_REG *) 	0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR   ((AT91_REG *) 	0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR  ((AT91_REG *) 	0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER   ((AT91_REG *) 	0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR  ((AT91_REG *) 	0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR    ((AT91_REG *) 	0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR   ((AT91_REG *) 	0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR  ((AT91_REG *) 	0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR    ((AT91_REG *) 	0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR   ((AT91_REG *) 	0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR  ((AT91_REG *) 	0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ========== 
-#define AT91C_TWI_IER   ((AT91_REG *) 	0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR    ((AT91_REG *) 	0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR    ((AT91_REG *) 	0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR   ((AT91_REG *) 	0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR   ((AT91_REG *) 	0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR   ((AT91_REG *) 	0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR  ((AT91_REG *) 	0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR   ((AT91_REG *) 	0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR  ((AT91_REG *) 	0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR   ((AT91_REG *) 	0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ========== 
-#define AT91C_PWMC_CH3_CUPDR ((AT91_REG *) 	0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved ((AT91_REG *) 	0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR ((AT91_REG *) 	0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR ((AT91_REG *) 	0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR ((AT91_REG *) 	0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR ((AT91_REG *) 	0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ========== 
-#define AT91C_PWMC_CH2_Reserved ((AT91_REG *) 	0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR ((AT91_REG *) 	0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR ((AT91_REG *) 	0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR ((AT91_REG *) 	0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR ((AT91_REG *) 	0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR ((AT91_REG *) 	0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ========== 
-#define AT91C_PWMC_CH1_Reserved ((AT91_REG *) 	0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR ((AT91_REG *) 	0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR ((AT91_REG *) 	0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR ((AT91_REG *) 	0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR ((AT91_REG *) 	0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR ((AT91_REG *) 	0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ========== 
-#define AT91C_PWMC_CH0_Reserved ((AT91_REG *) 	0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR ((AT91_REG *) 	0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR ((AT91_REG *) 	0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR ((AT91_REG *) 	0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR ((AT91_REG *) 	0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR ((AT91_REG *) 	0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ========== 
-#define AT91C_PWMC_IDR  ((AT91_REG *) 	0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS  ((AT91_REG *) 	0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER  ((AT91_REG *) 	0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR   ((AT91_REG *) 	0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR  ((AT91_REG *) 	0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR   ((AT91_REG *) 	0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR  ((AT91_REG *) 	0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR   ((AT91_REG *) 	0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA  ((AT91_REG *) 	0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ========== 
-#define AT91C_UDP_IMR   ((AT91_REG *) 	0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR ((AT91_REG *) 	0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM   ((AT91_REG *) 	0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR   ((AT91_REG *) 	0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR   ((AT91_REG *) 	0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR   ((AT91_REG *) 	0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR   ((AT91_REG *) 	0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR   ((AT91_REG *) 	0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP ((AT91_REG *) 	0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC  ((AT91_REG *) 	0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE ((AT91_REG *) 	0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER   ((AT91_REG *) 	0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ========== 
-#define AT91C_TC0_SR    ((AT91_REG *) 	0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC    ((AT91_REG *) 	0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB    ((AT91_REG *) 	0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR   ((AT91_REG *) 	0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR   ((AT91_REG *) 	0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER   ((AT91_REG *) 	0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA    ((AT91_REG *) 	0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR   ((AT91_REG *) 	0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV    ((AT91_REG *) 	0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR   ((AT91_REG *) 	0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ========== 
-#define AT91C_TC1_RB    ((AT91_REG *) 	0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR   ((AT91_REG *) 	0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER   ((AT91_REG *) 	0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR   ((AT91_REG *) 	0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR    ((AT91_REG *) 	0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR   ((AT91_REG *) 	0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA    ((AT91_REG *) 	0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC    ((AT91_REG *) 	0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR   ((AT91_REG *) 	0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV    ((AT91_REG *) 	0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ========== 
-#define AT91C_TC2_CMR   ((AT91_REG *) 	0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR   ((AT91_REG *) 	0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV    ((AT91_REG *) 	0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA    ((AT91_REG *) 	0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB    ((AT91_REG *) 	0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR   ((AT91_REG *) 	0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR   ((AT91_REG *) 	0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC    ((AT91_REG *) 	0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER   ((AT91_REG *) 	0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR    ((AT91_REG *) 	0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ========== 
-#define AT91C_TCB_BMR   ((AT91_REG *) 	0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR   ((AT91_REG *) 	0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ========== 
-#define AT91C_CAN_MB0_MDL ((AT91_REG *) 	0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM ((AT91_REG *) 	0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR ((AT91_REG *) 	0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID ((AT91_REG *) 	0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR ((AT91_REG *) 	0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID ((AT91_REG *) 	0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH ((AT91_REG *) 	0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR ((AT91_REG *) 	0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ========== 
-#define AT91C_CAN_MB1_MDL ((AT91_REG *) 	0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID ((AT91_REG *) 	0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR ((AT91_REG *) 	0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR ((AT91_REG *) 	0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM ((AT91_REG *) 	0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH ((AT91_REG *) 	0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR ((AT91_REG *) 	0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID ((AT91_REG *) 	0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ========== 
-#define AT91C_CAN_MB2_MCR ((AT91_REG *) 	0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH ((AT91_REG *) 	0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID ((AT91_REG *) 	0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL ((AT91_REG *) 	0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR ((AT91_REG *) 	0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM ((AT91_REG *) 	0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID ((AT91_REG *) 	0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR ((AT91_REG *) 	0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ========== 
-#define AT91C_CAN_MB3_MFID ((AT91_REG *) 	0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM ((AT91_REG *) 	0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID ((AT91_REG *) 	0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR ((AT91_REG *) 	0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR ((AT91_REG *) 	0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR ((AT91_REG *) 	0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL ((AT91_REG *) 	0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH ((AT91_REG *) 	0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ========== 
-#define AT91C_CAN_MB4_MID ((AT91_REG *) 	0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR ((AT91_REG *) 	0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH ((AT91_REG *) 	0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID ((AT91_REG *) 	0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR ((AT91_REG *) 	0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR ((AT91_REG *) 	0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL ((AT91_REG *) 	0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM ((AT91_REG *) 	0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ========== 
-#define AT91C_CAN_MB5_MSR ((AT91_REG *) 	0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR ((AT91_REG *) 	0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID ((AT91_REG *) 	0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH ((AT91_REG *) 	0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID ((AT91_REG *) 	0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR ((AT91_REG *) 	0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL ((AT91_REG *) 	0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM ((AT91_REG *) 	0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ========== 
-#define AT91C_CAN_MB6_MFID ((AT91_REG *) 	0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID ((AT91_REG *) 	0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM ((AT91_REG *) 	0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR ((AT91_REG *) 	0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL ((AT91_REG *) 	0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR ((AT91_REG *) 	0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH ((AT91_REG *) 	0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR ((AT91_REG *) 	0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ========== 
-#define AT91C_CAN_MB7_MCR ((AT91_REG *) 	0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH ((AT91_REG *) 	0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID ((AT91_REG *) 	0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL ((AT91_REG *) 	0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID ((AT91_REG *) 	0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR ((AT91_REG *) 	0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM ((AT91_REG *) 	0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR ((AT91_REG *) 	0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ========== 
-#define AT91C_CAN_TCR   ((AT91_REG *) 	0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR   ((AT91_REG *) 	0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER   ((AT91_REG *) 	0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR   ((AT91_REG *) 	0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP ((AT91_REG *) 	0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR    ((AT91_REG *) 	0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR   ((AT91_REG *) 	0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR   ((AT91_REG *) 	0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM   ((AT91_REG *) 	0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR    ((AT91_REG *) 	0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR    ((AT91_REG *) 	0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR    ((AT91_REG *) 	0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ========== 
-#define AT91C_EMAC_ISR  ((AT91_REG *) 	0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H ((AT91_REG *) 	0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L ((AT91_REG *) 	0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE  ((AT91_REG *) 	0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL ((AT91_REG *) 	0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE  ((AT91_REG *) 	0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL  ((AT91_REG *) 	0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF  ((AT91_REG *) 	0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND ((AT91_REG *) 	0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR  ((AT91_REG *) 	0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L ((AT91_REG *) 	0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR  ((AT91_REG *) 	0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L ((AT91_REG *) 	0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR  ((AT91_REG *) 	0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR  ((AT91_REG *) 	0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE  ((AT91_REG *) 	0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL ((AT91_REG *) 	0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID  ((AT91_REG *) 	0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB  ((AT91_REG *) 	0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP ((AT91_REG *) 	0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO ((AT91_REG *) 	0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR  ((AT91_REG *) 	0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H ((AT91_REG *) 	0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV  ((AT91_REG *) 	0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE  ((AT91_REG *) 	0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA  ((AT91_REG *) 	0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP ((AT91_REG *) 	0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF  ((AT91_REG *) 	0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR ((AT91_REG *) 	0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT  ((AT91_REG *) 	0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF  ((AT91_REG *) 	0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE ((AT91_REG *) 	0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ  ((AT91_REG *) 	0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN  ((AT91_REG *) 	0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO  ((AT91_REG *) 	0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV  ((AT91_REG *) 	0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR  ((AT91_REG *) 	0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF  ((AT91_REG *) 	0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR  ((AT91_REG *) 	0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF  ((AT91_REG *) 	0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR  ((AT91_REG *) 	0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L ((AT91_REG *) 	0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO  ((AT91_REG *) 	0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER  ((AT91_REG *) 	0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H ((AT91_REG *) 	0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE  ((AT91_REG *) 	0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H ((AT91_REG *) 	0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE  ((AT91_REG *) 	0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE  ((AT91_REG *) 	0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ========== 
-#define AT91C_ADC_PTSR  ((AT91_REG *) 	0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR  ((AT91_REG *) 	0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR  ((AT91_REG *) 	0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR  ((AT91_REG *) 	0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR  ((AT91_REG *) 	0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR  ((AT91_REG *) 	0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR   ((AT91_REG *) 	0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR   ((AT91_REG *) 	0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR   ((AT91_REG *) 	0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR   ((AT91_REG *) 	0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ========== 
-#define AT91C_ADC_CDR2  ((AT91_REG *) 	0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3  ((AT91_REG *) 	0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0  ((AT91_REG *) 	0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5  ((AT91_REG *) 	0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR  ((AT91_REG *) 	0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR    ((AT91_REG *) 	0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4  ((AT91_REG *) 	0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1  ((AT91_REG *) 	0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR  ((AT91_REG *) 	0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR   ((AT91_REG *) 	0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR    ((AT91_REG *) 	0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7  ((AT91_REG *) 	0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6  ((AT91_REG *) 	0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER   ((AT91_REG *) 	0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER  ((AT91_REG *) 	0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR  ((AT91_REG *) 	0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR    ((AT91_REG *) 	0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR   ((AT91_REG *) 	0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ========== 
-#define AT91C_AES_TPR   ((AT91_REG *) 	0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR  ((AT91_REG *) 	0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR  ((AT91_REG *) 	0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR  ((AT91_REG *) 	0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR   ((AT91_REG *) 	0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR   ((AT91_REG *) 	0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR  ((AT91_REG *) 	0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR  ((AT91_REG *) 	0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR   ((AT91_REG *) 	0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR  ((AT91_REG *) 	0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ========== 
-#define AT91C_AES_IVxR  ((AT91_REG *) 	0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR    ((AT91_REG *) 	0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR    ((AT91_REG *) 	0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR ((AT91_REG *) 	0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR ((AT91_REG *) 	0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR    ((AT91_REG *) 	0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR   ((AT91_REG *) 	0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR   ((AT91_REG *) 	0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER   ((AT91_REG *) 	0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR ((AT91_REG *) 	0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR   ((AT91_REG *) 	0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ========== 
-#define AT91C_TDES_RNCR ((AT91_REG *) 	0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR  ((AT91_REG *) 	0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR  ((AT91_REG *) 	0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR ((AT91_REG *) 	0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR ((AT91_REG *) 	0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR  ((AT91_REG *) 	0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR ((AT91_REG *) 	0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR  ((AT91_REG *) 	0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR ((AT91_REG *) 	0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR ((AT91_REG *) 	0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ========== 
-#define AT91C_TDES_KEY2WxR ((AT91_REG *) 	0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR ((AT91_REG *) 	0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR  ((AT91_REG *) 	0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR   ((AT91_REG *) 	0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR ((AT91_REG *) 	0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR ((AT91_REG *) 	0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR  ((AT91_REG *) 	0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR   ((AT91_REG *) 	0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR   ((AT91_REG *) 	0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER  ((AT91_REG *) 	0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR  ((AT91_REG *) 	0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR ((AT91_REG *) 	0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR ((AT91_REG *) 	0xFFFA8020) // (TDES) Key 1 Word x Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0        ((unsigned int) 1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0     ((unsigned int) AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1        ((unsigned int) 1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0     ((unsigned int) AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10       ((unsigned int) 1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD      ((unsigned int) AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11       ((unsigned int) 1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK     ((unsigned int) AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12       ((unsigned int) 1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00   ((unsigned int) AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13       ((unsigned int) 1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01   ((unsigned int) AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1     ((unsigned int) AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14       ((unsigned int) 1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02   ((unsigned int) AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1     ((unsigned int) AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15       ((unsigned int) 1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03   ((unsigned int) AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2    ((unsigned int) AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16       ((unsigned int) 1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0    ((unsigned int) AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17       ((unsigned int) 1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0    ((unsigned int) AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18       ((unsigned int) 1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0    ((unsigned int) AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19       ((unsigned int) 1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX    ((unsigned int) AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2        ((unsigned int) 1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0     ((unsigned int) AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11   ((unsigned int) AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20       ((unsigned int) 1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX    ((unsigned int) AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21       ((unsigned int) 1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF       ((unsigned int) AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10   ((unsigned int) AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22       ((unsigned int) 1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK       ((unsigned int) AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1    ((unsigned int) AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23       ((unsigned int) 1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD       ((unsigned int) AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1    ((unsigned int) AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24       ((unsigned int) 1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD       ((unsigned int) AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1    ((unsigned int) AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25       ((unsigned int) 1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK       ((unsigned int) AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11   ((unsigned int) AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26       ((unsigned int) 1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF       ((unsigned int) AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12   ((unsigned int) AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27       ((unsigned int) 1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD     ((unsigned int) AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3     ((unsigned int) AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28       ((unsigned int) 1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD     ((unsigned int) AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29       ((unsigned int) 1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ      ((unsigned int) AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13   ((unsigned int) AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3        ((unsigned int) 1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0     ((unsigned int) AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12   ((unsigned int) AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30       ((unsigned int) 1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0     ((unsigned int) AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2     ((unsigned int) AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4        ((unsigned int) 1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0     ((unsigned int) AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13   ((unsigned int) AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5        ((unsigned int) 1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1     ((unsigned int) AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6        ((unsigned int) 1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1     ((unsigned int) AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7        ((unsigned int) 1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1     ((unsigned int) AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01   ((unsigned int) AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8        ((unsigned int) 1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1     ((unsigned int) AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02   ((unsigned int) AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9        ((unsigned int) 1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1     ((unsigned int) AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03   ((unsigned int) AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0        ((unsigned int) 1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK ((unsigned int) AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0     ((unsigned int) AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1        ((unsigned int) 1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN    ((unsigned int) AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10       ((unsigned int) 1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2     ((unsigned int) AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11   ((unsigned int) AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11       ((unsigned int) 1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3     ((unsigned int) AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12   ((unsigned int) AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12       ((unsigned int) 1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER    ((unsigned int) AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0    ((unsigned int) AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13       ((unsigned int) 1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2     ((unsigned int) AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01   ((unsigned int) AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14       ((unsigned int) 1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3     ((unsigned int) AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02   ((unsigned int) AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15       ((unsigned int) 1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV    ((unsigned int) AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16       ((unsigned int) 1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL     ((unsigned int) AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13   ((unsigned int) AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17       ((unsigned int) 1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK    ((unsigned int) AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03   ((unsigned int) AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18       ((unsigned int) 1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100    ((unsigned int) AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG    ((unsigned int) AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19       ((unsigned int) 1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0     ((unsigned int) AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1    ((unsigned int) AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2        ((unsigned int) 1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0     ((unsigned int) AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20       ((unsigned int) 1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1     ((unsigned int) AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0     ((unsigned int) AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21       ((unsigned int) 1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2     ((unsigned int) AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1     ((unsigned int) AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22       ((unsigned int) 1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3     ((unsigned int) AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2     ((unsigned int) AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23       ((unsigned int) 1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0    ((unsigned int) AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1     ((unsigned int) AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24       ((unsigned int) 1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0    ((unsigned int) AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1     ((unsigned int) AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25       ((unsigned int) 1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1    ((unsigned int) AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1     ((unsigned int) AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26       ((unsigned int) 1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1    ((unsigned int) AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1      ((unsigned int) AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27       ((unsigned int) 1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2    ((unsigned int) AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0     ((unsigned int) AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28       ((unsigned int) 1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2    ((unsigned int) AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1     ((unsigned int) AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29       ((unsigned int) 1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1     ((unsigned int) AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2     ((unsigned int) AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3        ((unsigned int) 1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1     ((unsigned int) AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30       ((unsigned int) 1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2     ((unsigned int) AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3     ((unsigned int) AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4        ((unsigned int) 1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV ((unsigned int) AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5        ((unsigned int) 1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0     ((unsigned int) AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6        ((unsigned int) 1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1     ((unsigned int) AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7        ((unsigned int) 1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER    ((unsigned int) AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8        ((unsigned int) 1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC     ((unsigned int) AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9        ((unsigned int) 1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO    ((unsigned int) AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ    ((unsigned int)  0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS    ((unsigned int)  1) // System Peripheral
-#define AT91C_ID_PIOA   ((unsigned int)  2) // Parallel IO Controller A
-#define AT91C_ID_PIOB   ((unsigned int)  3) // Parallel IO Controller B
-#define AT91C_ID_SPI0   ((unsigned int)  4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1   ((unsigned int)  5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0    ((unsigned int)  6) // USART 0
-#define AT91C_ID_US1    ((unsigned int)  7) // USART 1
-#define AT91C_ID_SSC    ((unsigned int)  8) // Serial Synchronous Controller
-#define AT91C_ID_TWI    ((unsigned int)  9) // Two-Wire Interface
-#define AT91C_ID_PWMC   ((unsigned int) 10) // PWM Controller
-#define AT91C_ID_UDP    ((unsigned int) 11) // USB Device Port
-#define AT91C_ID_TC0    ((unsigned int) 12) // Timer Counter 0
-#define AT91C_ID_TC1    ((unsigned int) 13) // Timer Counter 1
-#define AT91C_ID_TC2    ((unsigned int) 14) // Timer Counter 2
-#define AT91C_ID_CAN    ((unsigned int) 15) // Control Area Network Controller
-#define AT91C_ID_EMAC   ((unsigned int) 16) // Ethernet MAC
-#define AT91C_ID_ADC    ((unsigned int) 17) // Analog-to-Digital Converter
-#define AT91C_ID_AES    ((unsigned int) 18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES   ((unsigned int) 19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved ((unsigned int) 20) // Reserved
-#define AT91C_ID_21_Reserved ((unsigned int) 21) // Reserved
-#define AT91C_ID_22_Reserved ((unsigned int) 22) // Reserved
-#define AT91C_ID_23_Reserved ((unsigned int) 23) // Reserved
-#define AT91C_ID_24_Reserved ((unsigned int) 24) // Reserved
-#define AT91C_ID_25_Reserved ((unsigned int) 25) // Reserved
-#define AT91C_ID_26_Reserved ((unsigned int) 26) // Reserved
-#define AT91C_ID_27_Reserved ((unsigned int) 27) // Reserved
-#define AT91C_ID_28_Reserved ((unsigned int) 28) // Reserved
-#define AT91C_ID_29_Reserved ((unsigned int) 29) // Reserved
-#define AT91C_ID_IRQ0   ((unsigned int) 30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1   ((unsigned int) 31) // Advanced Interrupt Controller (IRQ1)
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS       ((AT91PS_SYS) 	0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC       ((AT91PS_AIC) 	0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU  ((AT91PS_PDC) 	0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU      ((AT91PS_DBGU) 	0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA      ((AT91PS_PIO) 	0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB      ((AT91PS_PIO) 	0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR      ((AT91PS_CKGR) 	0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC       ((AT91PS_PMC) 	0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC      ((AT91PS_RSTC) 	0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC      ((AT91PS_RTTC) 	0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC      ((AT91PS_PITC) 	0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC      ((AT91PS_WDTC) 	0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG      ((AT91PS_VREG) 	0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC        ((AT91PS_MC) 	0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1  ((AT91PS_PDC) 	0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1      ((AT91PS_SPI) 	0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0  ((AT91PS_PDC) 	0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0      ((AT91PS_SPI) 	0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1   ((AT91PS_PDC) 	0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1       ((AT91PS_USART) 	0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0   ((AT91PS_PDC) 	0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0       ((AT91PS_USART) 	0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC   ((AT91PS_PDC) 	0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC       ((AT91PS_SSC) 	0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI       ((AT91PS_TWI) 	0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3  ((AT91PS_PWMC_CH) 	0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2  ((AT91PS_PWMC_CH) 	0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1  ((AT91PS_PWMC_CH) 	0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0  ((AT91PS_PWMC_CH) 	0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC      ((AT91PS_PWMC) 	0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP       ((AT91PS_UDP) 	0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0       ((AT91PS_TC) 	0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1       ((AT91PS_TC) 	0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2       ((AT91PS_TC) 	0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB       ((AT91PS_TCB) 	0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0   ((AT91PS_CAN_MB) 	0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1   ((AT91PS_CAN_MB) 	0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2   ((AT91PS_CAN_MB) 	0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3   ((AT91PS_CAN_MB) 	0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4   ((AT91PS_CAN_MB) 	0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5   ((AT91PS_CAN_MB) 	0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6   ((AT91PS_CAN_MB) 	0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7   ((AT91PS_CAN_MB) 	0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN       ((AT91PS_CAN) 	0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC      ((AT91PS_EMAC) 	0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC   ((AT91PS_PDC) 	0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC       ((AT91PS_ADC) 	0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES   ((AT91PS_PDC) 	0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES       ((AT91PS_AES) 	0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES  ((AT91PS_PDC) 	0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES      ((AT91PS_TDES) 	0xFFFA8000) // (TDES) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ISRAM	 ((char *) 	0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	 ((unsigned int) 0x00010000) // Internal SRAM size in byte (64 Kbyte)
-#define AT91C_IFLASH	 ((char *) 	0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE	 ((unsigned int) 0x00040000) // Internal ROM size in byte (256 Kbyte)
-
-#endif
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
deleted file mode 100755
index 194ce4e..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/AT91SAM7X256_inc.h
+++ /dev/null
@@ -1,2446 +0,0 @@
-//  ----------------------------------------------------------------------------
-//          ATMEL Microcontroller Software Support  -  ROUSSET  -
-//  ----------------------------------------------------------------------------
-//  DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//  IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//  MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//  DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//  OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//  LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//  NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//  EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//  ----------------------------------------------------------------------------
-// File Name           : AT91SAM7X256.h
-// Object              : AT91SAM7X256 definitions
-// Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-// 
-// CVS Reference       : /AT91SAM7X256.pl/1.11/Tue May 10 12:15:32 2005//
-// CVS Reference       : /SYS_SAM7X.pl/1.3/Tue Feb  1 17:01:43 2005//
-// CVS Reference       : /MC_SAM7X.pl/1.2/Fri May 20 14:13:04 2005//
-// CVS Reference       : /PMC_SAM7X.pl/1.4/Tue Feb  8 13:58:10 2005//
-// CVS Reference       : /RSTC_SAM7X.pl/1.1/Tue Feb  1 16:16:26 2005//
-// CVS Reference       : /UDP_SAM7X.pl/1.1/Tue May 10 11:35:35 2005//
-// CVS Reference       : /PWM_SAM7X.pl/1.1/Tue May 10 11:53:07 2005//
-// CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:01:30 2005//
-// CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:18:28 2005//
-// CVS Reference       : /RTTC_6081A.pl/1.2/Tue Nov  9 14:43:58 2004//
-// CVS Reference       : /PITC_6079A.pl/1.2/Tue Nov  9 14:43:56 2004//
-// CVS Reference       : /WDTC_6080A.pl/1.3/Tue Nov  9 14:44:00 2004//
-// CVS Reference       : /VREG_6085B.pl/1.1/Tue Feb  1 16:05:48 2005//
-// CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 08:48:54 2005//
-// CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:15:32 2005//
-// CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:08:59 2005//
-// CVS Reference       : /US_6089C.pl/1.1/Mon Jul 12 18:23:26 2004//
-// CVS Reference       : /SSC_6078A.pl/1.1/Tue Jul 13 07:45:40 2004//
-// CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 07:38:06 2004//
-// CVS Reference       : /TC_6082A.pl/1.7/Fri Mar 11 12:52:17 2005//
-// CVS Reference       : /CAN_6019B.pl/1.1/Tue Mar  8 12:42:22 2005//
-// CVS Reference       : /EMACB_6119A.pl/1.5/Thu Feb  3 15:52:04 2005//
-// CVS Reference       : /ADC_6051C.pl/1.1/Fri Oct 17 09:12:38 2003//
-// CVS Reference       : /AES_6149A.pl/1.10/Mon Feb  7 09:44:25 2005//
-// CVS Reference       : /DES3_6150A.pl/1.1/Mon Jan 17 08:34:31 2005//
-//  ----------------------------------------------------------------------------
-
-// Hardware register definition
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR System Peripherals
-// *****************************************************************************
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced Interrupt Controller
-// *****************************************************************************
-// *** Register offset in AT91S_AIC structure ***
-#define AIC_SMR         ( 0) // Source Mode Register
-#define AIC_SVR         (128) // Source Vector Register
-#define AIC_IVR         (256) // IRQ Vector Register
-#define AIC_FVR         (260) // FIQ Vector Register
-#define AIC_ISR         (264) // Interrupt Status Register
-#define AIC_IPR         (268) // Interrupt Pending Register
-#define AIC_IMR         (272) // Interrupt Mask Register
-#define AIC_CISR        (276) // Core Interrupt Status Register
-#define AIC_IECR        (288) // Interrupt Enable Command Register
-#define AIC_IDCR        (292) // Interrupt Disable Command Register
-#define AIC_ICCR        (296) // Interrupt Clear Command Register
-#define AIC_ISCR        (300) // Interrupt Set Command Register
-#define AIC_EOICR       (304) // End of Interrupt Command Register
-#define AIC_SPU         (308) // Spurious Vector Register
-#define AIC_DCR         (312) // Debug Control Register (Protect)
-#define AIC_FFER        (320) // Fast Forcing Enable Register
-#define AIC_FFDR        (324) // Fast Forcing Disable Register
-#define AIC_FFSR        (328) // Fast Forcing Status Register
-// -------- AIC_SMR : (AIC Offset: 0x0) Control Register -------- 
-#define AT91C_AIC_PRIOR           (0x7 <<  0) // (AIC) Priority Level
-#define 	AT91C_AIC_PRIOR_LOWEST               (0x0) // (AIC) Lowest priority level
-#define 	AT91C_AIC_PRIOR_HIGHEST              (0x7) // (AIC) Highest priority level
-#define AT91C_AIC_SRCTYPE         (0x3 <<  5) // (AIC) Interrupt Source Type
-#define 	AT91C_AIC_SRCTYPE_INT_HIGH_LEVEL       (0x0 <<  5) // (AIC) Internal Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_EXT_LOW_LEVEL        (0x0 <<  5) // (AIC) External Sources Code Label Low-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_INT_POSITIVE_EDGE    (0x1 <<  5) // (AIC) Internal Sources Code Label Positive Edge triggered
-#define 	AT91C_AIC_SRCTYPE_EXT_NEGATIVE_EDGE    (0x1 <<  5) // (AIC) External Sources Code Label Negative Edge triggered
-#define 	AT91C_AIC_SRCTYPE_HIGH_LEVEL           (0x2 <<  5) // (AIC) Internal Or External Sources Code Label High-level Sensitive
-#define 	AT91C_AIC_SRCTYPE_POSITIVE_EDGE        (0x3 <<  5) // (AIC) Internal Or External Sources Code Label Positive Edge triggered
-// -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register -------- 
-#define AT91C_AIC_NFIQ            (0x1 <<  0) // (AIC) NFIQ Status
-#define AT91C_AIC_NIRQ            (0x1 <<  1) // (AIC) NIRQ Status
-// -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) -------- 
-#define AT91C_AIC_DCR_PROT        (0x1 <<  0) // (AIC) Protection Mode
-#define AT91C_AIC_DCR_GMSK        (0x1 <<  1) // (AIC) General Mask
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Peripheral DMA Controller
-// *****************************************************************************
-// *** Register offset in AT91S_PDC structure ***
-#define PDC_RPR         ( 0) // Receive Pointer Register
-#define PDC_RCR         ( 4) // Receive Counter Register
-#define PDC_TPR         ( 8) // Transmit Pointer Register
-#define PDC_TCR         (12) // Transmit Counter Register
-#define PDC_RNPR        (16) // Receive Next Pointer Register
-#define PDC_RNCR        (20) // Receive Next Counter Register
-#define PDC_TNPR        (24) // Transmit Next Pointer Register
-#define PDC_TNCR        (28) // Transmit Next Counter Register
-#define PDC_PTCR        (32) // PDC Transfer Control Register
-#define PDC_PTSR        (36) // PDC Transfer Status Register
-// -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register -------- 
-#define AT91C_PDC_RXTEN           (0x1 <<  0) // (PDC) Receiver Transfer Enable
-#define AT91C_PDC_RXTDIS          (0x1 <<  1) // (PDC) Receiver Transfer Disable
-#define AT91C_PDC_TXTEN           (0x1 <<  8) // (PDC) Transmitter Transfer Enable
-#define AT91C_PDC_TXTDIS          (0x1 <<  9) // (PDC) Transmitter Transfer Disable
-// -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Debug Unit
-// *****************************************************************************
-// *** Register offset in AT91S_DBGU structure ***
-#define DBGU_CR         ( 0) // Control Register
-#define DBGU_MR         ( 4) // Mode Register
-#define DBGU_IER        ( 8) // Interrupt Enable Register
-#define DBGU_IDR        (12) // Interrupt Disable Register
-#define DBGU_IMR        (16) // Interrupt Mask Register
-#define DBGU_CSR        (20) // Channel Status Register
-#define DBGU_RHR        (24) // Receiver Holding Register
-#define DBGU_THR        (28) // Transmitter Holding Register
-#define DBGU_BRGR       (32) // Baud Rate Generator Register
-#define DBGU_CIDR       (64) // Chip ID Register
-#define DBGU_EXID       (68) // Chip ID Extension Register
-#define DBGU_FNTR       (72) // Force NTRST Register
-#define DBGU_RPR        (256) // Receive Pointer Register
-#define DBGU_RCR        (260) // Receive Counter Register
-#define DBGU_TPR        (264) // Transmit Pointer Register
-#define DBGU_TCR        (268) // Transmit Counter Register
-#define DBGU_RNPR       (272) // Receive Next Pointer Register
-#define DBGU_RNCR       (276) // Receive Next Counter Register
-#define DBGU_TNPR       (280) // Transmit Next Pointer Register
-#define DBGU_TNCR       (284) // Transmit Next Counter Register
-#define DBGU_PTCR       (288) // PDC Transfer Control Register
-#define DBGU_PTSR       (292) // PDC Transfer Status Register
-// -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_RSTRX            (0x1 <<  2) // (DBGU) Reset Receiver
-#define AT91C_US_RSTTX            (0x1 <<  3) // (DBGU) Reset Transmitter
-#define AT91C_US_RXEN             (0x1 <<  4) // (DBGU) Receiver Enable
-#define AT91C_US_RXDIS            (0x1 <<  5) // (DBGU) Receiver Disable
-#define AT91C_US_TXEN             (0x1 <<  6) // (DBGU) Transmitter Enable
-#define AT91C_US_TXDIS            (0x1 <<  7) // (DBGU) Transmitter Disable
-#define AT91C_US_RSTSTA           (0x1 <<  8) // (DBGU) Reset Status Bits
-// -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_PAR              (0x7 <<  9) // (DBGU) Parity type
-#define 	AT91C_US_PAR_EVEN                 (0x0 <<  9) // (DBGU) Even Parity
-#define 	AT91C_US_PAR_ODD                  (0x1 <<  9) // (DBGU) Odd Parity
-#define 	AT91C_US_PAR_SPACE                (0x2 <<  9) // (DBGU) Parity forced to 0 (Space)
-#define 	AT91C_US_PAR_MARK                 (0x3 <<  9) // (DBGU) Parity forced to 1 (Mark)
-#define 	AT91C_US_PAR_NONE                 (0x4 <<  9) // (DBGU) No Parity
-#define 	AT91C_US_PAR_MULTI_DROP           (0x6 <<  9) // (DBGU) Multi-drop mode
-#define AT91C_US_CHMODE           (0x3 << 14) // (DBGU) Channel Mode
-#define 	AT91C_US_CHMODE_NORMAL               (0x0 << 14) // (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
-#define 	AT91C_US_CHMODE_AUTO                 (0x1 << 14) // (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
-#define 	AT91C_US_CHMODE_LOCAL                (0x2 << 14) // (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
-#define 	AT91C_US_CHMODE_REMOTE               (0x3 << 14) // (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
-// -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXRDY            (0x1 <<  0) // (DBGU) RXRDY Interrupt
-#define AT91C_US_TXRDY            (0x1 <<  1) // (DBGU) TXRDY Interrupt
-#define AT91C_US_ENDRX            (0x1 <<  3) // (DBGU) End of Receive Transfer Interrupt
-#define AT91C_US_ENDTX            (0x1 <<  4) // (DBGU) End of Transmit Interrupt
-#define AT91C_US_OVRE             (0x1 <<  5) // (DBGU) Overrun Interrupt
-#define AT91C_US_FRAME            (0x1 <<  6) // (DBGU) Framing Error Interrupt
-#define AT91C_US_PARE             (0x1 <<  7) // (DBGU) Parity Error Interrupt
-#define AT91C_US_TXEMPTY          (0x1 <<  9) // (DBGU) TXEMPTY Interrupt
-#define AT91C_US_TXBUFE           (0x1 << 11) // (DBGU) TXBUFE Interrupt
-#define AT91C_US_RXBUFF           (0x1 << 12) // (DBGU) RXBUFF Interrupt
-#define AT91C_US_COMM_TX          (0x1 << 30) // (DBGU) COMM_TX Interrupt
-#define AT91C_US_COMM_RX          (0x1 << 31) // (DBGU) COMM_RX Interrupt
-// -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register -------- 
-// -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register -------- 
-#define AT91C_US_FORCE_NTRST      (0x1 <<  0) // (DBGU) Force NTRST in JTAG
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Parallel Input Output Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PIO structure ***
-#define PIO_PER         ( 0) // PIO Enable Register
-#define PIO_PDR         ( 4) // PIO Disable Register
-#define PIO_PSR         ( 8) // PIO Status Register
-#define PIO_OER         (16) // Output Enable Register
-#define PIO_ODR         (20) // Output Disable Registerr
-#define PIO_OSR         (24) // Output Status Register
-#define PIO_IFER        (32) // Input Filter Enable Register
-#define PIO_IFDR        (36) // Input Filter Disable Register
-#define PIO_IFSR        (40) // Input Filter Status Register
-#define PIO_SODR        (48) // Set Output Data Register
-#define PIO_CODR        (52) // Clear Output Data Register
-#define PIO_ODSR        (56) // Output Data Status Register
-#define PIO_PDSR        (60) // Pin Data Status Register
-#define PIO_IER         (64) // Interrupt Enable Register
-#define PIO_IDR         (68) // Interrupt Disable Register
-#define PIO_IMR         (72) // Interrupt Mask Register
-#define PIO_ISR         (76) // Interrupt Status Register
-#define PIO_MDER        (80) // Multi-driver Enable Register
-#define PIO_MDDR        (84) // Multi-driver Disable Register
-#define PIO_MDSR        (88) // Multi-driver Status Register
-#define PIO_PPUDR       (96) // Pull-up Disable Register
-#define PIO_PPUER       (100) // Pull-up Enable Register
-#define PIO_PPUSR       (104) // Pull-up Status Register
-#define PIO_ASR         (112) // Select A Register
-#define PIO_BSR         (116) // Select B Register
-#define PIO_ABSR        (120) // AB Select Status Register
-#define PIO_OWER        (160) // Output Write Enable Register
-#define PIO_OWDR        (164) // Output Write Disable Register
-#define PIO_OWSR        (168) // Output Write Status Register
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Clock Generator Controler
-// *****************************************************************************
-// *** Register offset in AT91S_CKGR structure ***
-#define CKGR_MOR        ( 0) // Main Oscillator Register
-#define CKGR_MCFR       ( 4) // Main Clock  Frequency Register
-#define CKGR_PLLR       (12) // PLL Register
-// -------- CKGR_MOR : (CKGR Offset: 0x0) Main Oscillator Register -------- 
-#define AT91C_CKGR_MOSCEN         (0x1 <<  0) // (CKGR) Main Oscillator Enable
-#define AT91C_CKGR_OSCBYPASS      (0x1 <<  1) // (CKGR) Main Oscillator Bypass
-#define AT91C_CKGR_OSCOUNT        (0xFF <<  8) // (CKGR) Main Oscillator Start-up Time
-// -------- CKGR_MCFR : (CKGR Offset: 0x4) Main Clock Frequency Register -------- 
-#define AT91C_CKGR_MAINF          (0xFFFF <<  0) // (CKGR) Main Clock Frequency
-#define AT91C_CKGR_MAINRDY        (0x1 << 16) // (CKGR) Main Clock Ready
-// -------- CKGR_PLLR : (CKGR Offset: 0xc) PLL B Register -------- 
-#define AT91C_CKGR_DIV            (0xFF <<  0) // (CKGR) Divider Selected
-#define 	AT91C_CKGR_DIV_0                    (0x0) // (CKGR) Divider output is 0
-#define 	AT91C_CKGR_DIV_BYPASS               (0x1) // (CKGR) Divider is bypassed
-#define AT91C_CKGR_PLLCOUNT       (0x3F <<  8) // (CKGR) PLL Counter
-#define AT91C_CKGR_OUT            (0x3 << 14) // (CKGR) PLL Output Frequency Range
-#define 	AT91C_CKGR_OUT_0                    (0x0 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_1                    (0x1 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_2                    (0x2 << 14) // (CKGR) Please refer to the PLL datasheet
-#define 	AT91C_CKGR_OUT_3                    (0x3 << 14) // (CKGR) Please refer to the PLL datasheet
-#define AT91C_CKGR_MUL            (0x7FF << 16) // (CKGR) PLL Multiplier
-#define AT91C_CKGR_USBDIV         (0x3 << 28) // (CKGR) Divider for USB Clocks
-#define 	AT91C_CKGR_USBDIV_0                    (0x0 << 28) // (CKGR) Divider output is PLL clock output
-#define 	AT91C_CKGR_USBDIV_1                    (0x1 << 28) // (CKGR) Divider output is PLL clock output divided by 2
-#define 	AT91C_CKGR_USBDIV_2                    (0x2 << 28) // (CKGR) Divider output is PLL clock output divided by 4
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Power Management Controler
-// *****************************************************************************
-// *** Register offset in AT91S_PMC structure ***
-#define PMC_SCER        ( 0) // System Clock Enable Register
-#define PMC_SCDR        ( 4) // System Clock Disable Register
-#define PMC_SCSR        ( 8) // System Clock Status Register
-#define PMC_PCER        (16) // Peripheral Clock Enable Register
-#define PMC_PCDR        (20) // Peripheral Clock Disable Register
-#define PMC_PCSR        (24) // Peripheral Clock Status Register
-#define PMC_MOR         (32) // Main Oscillator Register
-#define PMC_MCFR        (36) // Main Clock  Frequency Register
-#define PMC_PLLR        (44) // PLL Register
-#define PMC_MCKR        (48) // Master Clock Register
-#define PMC_PCKR        (64) // Programmable Clock Register
-#define PMC_IER         (96) // Interrupt Enable Register
-#define PMC_IDR         (100) // Interrupt Disable Register
-#define PMC_SR          (104) // Status Register
-#define PMC_IMR         (108) // Interrupt Mask Register
-// -------- PMC_SCER : (PMC Offset: 0x0) System Clock Enable Register -------- 
-#define AT91C_PMC_PCK             (0x1 <<  0) // (PMC) Processor Clock
-#define AT91C_PMC_UDP             (0x1 <<  7) // (PMC) USB Device Port Clock
-#define AT91C_PMC_PCK0            (0x1 <<  8) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK1            (0x1 <<  9) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK2            (0x1 << 10) // (PMC) Programmable Clock Output
-#define AT91C_PMC_PCK3            (0x1 << 11) // (PMC) Programmable Clock Output
-// -------- PMC_SCDR : (PMC Offset: 0x4) System Clock Disable Register -------- 
-// -------- PMC_SCSR : (PMC Offset: 0x8) System Clock Status Register -------- 
-// -------- CKGR_MOR : (PMC Offset: 0x20) Main Oscillator Register -------- 
-// -------- CKGR_MCFR : (PMC Offset: 0x24) Main Clock Frequency Register -------- 
-// -------- CKGR_PLLR : (PMC Offset: 0x2c) PLL B Register -------- 
-// -------- PMC_MCKR : (PMC Offset: 0x30) Master Clock Register -------- 
-#define AT91C_PMC_CSS             (0x3 <<  0) // (PMC) Programmable Clock Selection
-#define 	AT91C_PMC_CSS_SLOW_CLK             (0x0) // (PMC) Slow Clock is selected
-#define 	AT91C_PMC_CSS_MAIN_CLK             (0x1) // (PMC) Main Clock is selected
-#define 	AT91C_PMC_CSS_PLL_CLK              (0x3) // (PMC) Clock from PLL is selected
-#define AT91C_PMC_PRES            (0x7 <<  2) // (PMC) Programmable Clock Prescaler
-#define 	AT91C_PMC_PRES_CLK                  (0x0 <<  2) // (PMC) Selected clock
-#define 	AT91C_PMC_PRES_CLK_2                (0x1 <<  2) // (PMC) Selected clock divided by 2
-#define 	AT91C_PMC_PRES_CLK_4                (0x2 <<  2) // (PMC) Selected clock divided by 4
-#define 	AT91C_PMC_PRES_CLK_8                (0x3 <<  2) // (PMC) Selected clock divided by 8
-#define 	AT91C_PMC_PRES_CLK_16               (0x4 <<  2) // (PMC) Selected clock divided by 16
-#define 	AT91C_PMC_PRES_CLK_32               (0x5 <<  2) // (PMC) Selected clock divided by 32
-#define 	AT91C_PMC_PRES_CLK_64               (0x6 <<  2) // (PMC) Selected clock divided by 64
-// -------- PMC_PCKR : (PMC Offset: 0x40) Programmable Clock Register -------- 
-// -------- PMC_IER : (PMC Offset: 0x60) PMC Interrupt Enable Register -------- 
-#define AT91C_PMC_MOSCS           (0x1 <<  0) // (PMC) MOSC Status/Enable/Disable/Mask
-#define AT91C_PMC_LOCK            (0x1 <<  2) // (PMC) PLL Status/Enable/Disable/Mask
-#define AT91C_PMC_MCKRDY          (0x1 <<  3) // (PMC) MCK_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK0RDY         (0x1 <<  8) // (PMC) PCK0_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK1RDY         (0x1 <<  9) // (PMC) PCK1_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK2RDY         (0x1 << 10) // (PMC) PCK2_RDY Status/Enable/Disable/Mask
-#define AT91C_PMC_PCK3RDY         (0x1 << 11) // (PMC) PCK3_RDY Status/Enable/Disable/Mask
-// -------- PMC_IDR : (PMC Offset: 0x64) PMC Interrupt Disable Register -------- 
-// -------- PMC_SR : (PMC Offset: 0x68) PMC Status Register -------- 
-// -------- PMC_IMR : (PMC Offset: 0x6c) PMC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Reset Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_RSTC structure ***
-#define RSTC_RCR        ( 0) // Reset Control Register
-#define RSTC_RSR        ( 4) // Reset Status Register
-#define RSTC_RMR        ( 8) // Reset Mode Register
-// -------- RSTC_RCR : (RSTC Offset: 0x0) Reset Control Register -------- 
-#define AT91C_RSTC_PROCRST        (0x1 <<  0) // (RSTC) Processor Reset
-#define AT91C_RSTC_PERRST         (0x1 <<  2) // (RSTC) Peripheral Reset
-#define AT91C_RSTC_EXTRST         (0x1 <<  3) // (RSTC) External Reset
-#define AT91C_RSTC_KEY            (0xFF << 24) // (RSTC) Password
-// -------- RSTC_RSR : (RSTC Offset: 0x4) Reset Status Register -------- 
-#define AT91C_RSTC_URSTS          (0x1 <<  0) // (RSTC) User Reset Status
-#define AT91C_RSTC_BODSTS         (0x1 <<  1) // (RSTC) Brownout Detection Status
-#define AT91C_RSTC_RSTTYP         (0x7 <<  8) // (RSTC) Reset Type
-#define 	AT91C_RSTC_RSTTYP_POWERUP              (0x0 <<  8) // (RSTC) Power-up Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WAKEUP               (0x1 <<  8) // (RSTC) WakeUp Reset. VDDCORE rising.
-#define 	AT91C_RSTC_RSTTYP_WATCHDOG             (0x2 <<  8) // (RSTC) Watchdog Reset. Watchdog overflow occured.
-#define 	AT91C_RSTC_RSTTYP_SOFTWARE             (0x3 <<  8) // (RSTC) Software Reset. Processor reset required by the software.
-#define 	AT91C_RSTC_RSTTYP_USER                 (0x4 <<  8) // (RSTC) User Reset. NRST pin detected low.
-#define 	AT91C_RSTC_RSTTYP_BROWNOUT             (0x5 <<  8) // (RSTC) Brownout Reset occured.
-#define AT91C_RSTC_NRSTL          (0x1 << 16) // (RSTC) NRST pin level
-#define AT91C_RSTC_SRCMP          (0x1 << 17) // (RSTC) Software Reset Command in Progress.
-// -------- RSTC_RMR : (RSTC Offset: 0x8) Reset Mode Register -------- 
-#define AT91C_RSTC_URSTEN         (0x1 <<  0) // (RSTC) User Reset Enable
-#define AT91C_RSTC_URSTIEN        (0x1 <<  4) // (RSTC) User Reset Interrupt Enable
-#define AT91C_RSTC_ERSTL          (0xF <<  8) // (RSTC) User Reset Enable
-#define AT91C_RSTC_BODIEN         (0x1 << 16) // (RSTC) Brownout Detection Interrupt Enable
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Real Time Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_RTTC structure ***
-#define RTTC_RTMR       ( 0) // Real-time Mode Register
-#define RTTC_RTAR       ( 4) // Real-time Alarm Register
-#define RTTC_RTVR       ( 8) // Real-time Value Register
-#define RTTC_RTSR       (12) // Real-time Status Register
-// -------- RTTC_RTMR : (RTTC Offset: 0x0) Real-time Mode Register -------- 
-#define AT91C_RTTC_RTPRES         (0xFFFF <<  0) // (RTTC) Real-time Timer Prescaler Value
-#define AT91C_RTTC_ALMIEN         (0x1 << 16) // (RTTC) Alarm Interrupt Enable
-#define AT91C_RTTC_RTTINCIEN      (0x1 << 17) // (RTTC) Real Time Timer Increment Interrupt Enable
-#define AT91C_RTTC_RTTRST         (0x1 << 18) // (RTTC) Real Time Timer Restart
-// -------- RTTC_RTAR : (RTTC Offset: 0x4) Real-time Alarm Register -------- 
-#define AT91C_RTTC_ALMV           (0x0 <<  0) // (RTTC) Alarm Value
-// -------- RTTC_RTVR : (RTTC Offset: 0x8) Current Real-time Value Register -------- 
-#define AT91C_RTTC_CRTV           (0x0 <<  0) // (RTTC) Current Real-time Value
-// -------- RTTC_RTSR : (RTTC Offset: 0xc) Real-time Status Register -------- 
-#define AT91C_RTTC_ALMS           (0x1 <<  0) // (RTTC) Real-time Alarm Status
-#define AT91C_RTTC_RTTINC         (0x1 <<  1) // (RTTC) Real-time Timer Increment
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Periodic Interval Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PITC structure ***
-#define PITC_PIMR       ( 0) // Period Interval Mode Register
-#define PITC_PISR       ( 4) // Period Interval Status Register
-#define PITC_PIVR       ( 8) // Period Interval Value Register
-#define PITC_PIIR       (12) // Period Interval Image Register
-// -------- PITC_PIMR : (PITC Offset: 0x0) Periodic Interval Mode Register -------- 
-#define AT91C_PITC_PIV            (0xFFFFF <<  0) // (PITC) Periodic Interval Value
-#define AT91C_PITC_PITEN          (0x1 << 24) // (PITC) Periodic Interval Timer Enabled
-#define AT91C_PITC_PITIEN         (0x1 << 25) // (PITC) Periodic Interval Timer Interrupt Enable
-// -------- PITC_PISR : (PITC Offset: 0x4) Periodic Interval Status Register -------- 
-#define AT91C_PITC_PITS           (0x1 <<  0) // (PITC) Periodic Interval Timer Status
-// -------- PITC_PIVR : (PITC Offset: 0x8) Periodic Interval Value Register -------- 
-#define AT91C_PITC_CPIV           (0xFFFFF <<  0) // (PITC) Current Periodic Interval Value
-#define AT91C_PITC_PICNT          (0xFFF << 20) // (PITC) Periodic Interval Counter
-// -------- PITC_PIIR : (PITC Offset: 0xc) Periodic Interval Image Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Watchdog Timer Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_WDTC structure ***
-#define WDTC_WDCR       ( 0) // Watchdog Control Register
-#define WDTC_WDMR       ( 4) // Watchdog Mode Register
-#define WDTC_WDSR       ( 8) // Watchdog Status Register
-// -------- WDTC_WDCR : (WDTC Offset: 0x0) Periodic Interval Image Register -------- 
-#define AT91C_WDTC_WDRSTT         (0x1 <<  0) // (WDTC) Watchdog Restart
-#define AT91C_WDTC_KEY            (0xFF << 24) // (WDTC) Watchdog KEY Password
-// -------- WDTC_WDMR : (WDTC Offset: 0x4) Watchdog Mode Register -------- 
-#define AT91C_WDTC_WDV            (0xFFF <<  0) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDFIEN         (0x1 << 12) // (WDTC) Watchdog Fault Interrupt Enable
-#define AT91C_WDTC_WDRSTEN        (0x1 << 13) // (WDTC) Watchdog Reset Enable
-#define AT91C_WDTC_WDRPROC        (0x1 << 14) // (WDTC) Watchdog Timer Restart
-#define AT91C_WDTC_WDDIS          (0x1 << 15) // (WDTC) Watchdog Disable
-#define AT91C_WDTC_WDD            (0xFFF << 16) // (WDTC) Watchdog Delta Value
-#define AT91C_WDTC_WDDBGHLT       (0x1 << 28) // (WDTC) Watchdog Debug Halt
-#define AT91C_WDTC_WDIDLEHLT      (0x1 << 29) // (WDTC) Watchdog Idle Halt
-// -------- WDTC_WDSR : (WDTC Offset: 0x8) Watchdog Status Register -------- 
-#define AT91C_WDTC_WDUNF          (0x1 <<  0) // (WDTC) Watchdog Underflow
-#define AT91C_WDTC_WDERR          (0x1 <<  1) // (WDTC) Watchdog Error
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Voltage Regulator Mode Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_VREG structure ***
-#define VREG_MR         ( 0) // Voltage Regulator Mode Register
-// -------- VREG_MR : (VREG Offset: 0x0) Voltage Regulator Mode Register -------- 
-#define AT91C_VREG_PSTDBY         (0x1 <<  0) // (VREG) Voltage Regulator Power Standby Mode
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Memory Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_MC structure ***
-#define MC_RCR          ( 0) // MC Remap Control Register
-#define MC_ASR          ( 4) // MC Abort Status Register
-#define MC_AASR         ( 8) // MC Abort Address Status Register
-#define MC_FMR          (96) // MC Flash Mode Register
-#define MC_FCR          (100) // MC Flash Command Register
-#define MC_FSR          (104) // MC Flash Status Register
-// -------- MC_RCR : (MC Offset: 0x0) MC Remap Control Register -------- 
-#define AT91C_MC_RCB              (0x1 <<  0) // (MC) Remap Command Bit
-// -------- MC_ASR : (MC Offset: 0x4) MC Abort Status Register -------- 
-#define AT91C_MC_UNDADD           (0x1 <<  0) // (MC) Undefined Addess Abort Status
-#define AT91C_MC_MISADD           (0x1 <<  1) // (MC) Misaligned Addess Abort Status
-#define AT91C_MC_ABTSZ            (0x3 <<  8) // (MC) Abort Size Status
-#define 	AT91C_MC_ABTSZ_BYTE                 (0x0 <<  8) // (MC) Byte
-#define 	AT91C_MC_ABTSZ_HWORD                (0x1 <<  8) // (MC) Half-word
-#define 	AT91C_MC_ABTSZ_WORD                 (0x2 <<  8) // (MC) Word
-#define AT91C_MC_ABTTYP           (0x3 << 10) // (MC) Abort Type Status
-#define 	AT91C_MC_ABTTYP_DATAR                (0x0 << 10) // (MC) Data Read
-#define 	AT91C_MC_ABTTYP_DATAW                (0x1 << 10) // (MC) Data Write
-#define 	AT91C_MC_ABTTYP_FETCH                (0x2 << 10) // (MC) Code Fetch
-#define AT91C_MC_MST0             (0x1 << 16) // (MC) Master 0 Abort Source
-#define AT91C_MC_MST1             (0x1 << 17) // (MC) Master 1 Abort Source
-#define AT91C_MC_SVMST0           (0x1 << 24) // (MC) Saved Master 0 Abort Source
-#define AT91C_MC_SVMST1           (0x1 << 25) // (MC) Saved Master 1 Abort Source
-// -------- MC_FMR : (MC Offset: 0x60) MC Flash Mode Register -------- 
-#define AT91C_MC_FRDY             (0x1 <<  0) // (MC) Flash Ready
-#define AT91C_MC_LOCKE            (0x1 <<  2) // (MC) Lock Error
-#define AT91C_MC_PROGE            (0x1 <<  3) // (MC) Programming Error
-#define AT91C_MC_NEBP             (0x1 <<  7) // (MC) No Erase Before Programming
-#define AT91C_MC_FWS              (0x3 <<  8) // (MC) Flash Wait State
-#define 	AT91C_MC_FWS_0FWS                 (0x0 <<  8) // (MC) 1 cycle for Read, 2 for Write operations
-#define 	AT91C_MC_FWS_1FWS                 (0x1 <<  8) // (MC) 2 cycles for Read, 3 for Write operations
-#define 	AT91C_MC_FWS_2FWS                 (0x2 <<  8) // (MC) 3 cycles for Read, 4 for Write operations
-#define 	AT91C_MC_FWS_3FWS                 (0x3 <<  8) // (MC) 4 cycles for Read, 4 for Write operations
-#define AT91C_MC_FMCN             (0xFF << 16) // (MC) Flash Microsecond Cycle Number
-// -------- MC_FCR : (MC Offset: 0x64) MC Flash Command Register -------- 
-#define AT91C_MC_FCMD             (0xF <<  0) // (MC) Flash Command
-#define 	AT91C_MC_FCMD_START_PROG           (0x1) // (MC) Starts the programming of th epage specified by PAGEN.
-#define 	AT91C_MC_FCMD_LOCK                 (0x2) // (MC) Starts a lock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_PROG_AND_LOCK        (0x3) // (MC) The lock sequence automatically happens after the programming sequence is completed.
-#define 	AT91C_MC_FCMD_UNLOCK               (0x4) // (MC) Starts an unlock sequence of the sector defined by the bits 4 to 7 of the field PAGEN.
-#define 	AT91C_MC_FCMD_ERASE_ALL            (0x8) // (MC) Starts the erase of the entire flash.If at least a page is locked, the command is cancelled.
-#define 	AT91C_MC_FCMD_SET_GP_NVM           (0xB) // (MC) Set General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_CLR_GP_NVM           (0xD) // (MC) Clear General Purpose NVM bits.
-#define 	AT91C_MC_FCMD_SET_SECURITY         (0xF) // (MC) Set Security Bit.
-#define AT91C_MC_PAGEN            (0x3FF <<  8) // (MC) Page Number
-#define AT91C_MC_KEY              (0xFF << 24) // (MC) Writing Protect Key
-// -------- MC_FSR : (MC Offset: 0x68) MC Flash Command Register -------- 
-#define AT91C_MC_SECURITY         (0x1 <<  4) // (MC) Security Bit Status
-#define AT91C_MC_GPNVM0           (0x1 <<  8) // (MC) Sector 0 Lock Status
-#define AT91C_MC_GPNVM1           (0x1 <<  9) // (MC) Sector 1 Lock Status
-#define AT91C_MC_GPNVM2           (0x1 << 10) // (MC) Sector 2 Lock Status
-#define AT91C_MC_GPNVM3           (0x1 << 11) // (MC) Sector 3 Lock Status
-#define AT91C_MC_GPNVM4           (0x1 << 12) // (MC) Sector 4 Lock Status
-#define AT91C_MC_GPNVM5           (0x1 << 13) // (MC) Sector 5 Lock Status
-#define AT91C_MC_GPNVM6           (0x1 << 14) // (MC) Sector 6 Lock Status
-#define AT91C_MC_GPNVM7           (0x1 << 15) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS0           (0x1 << 16) // (MC) Sector 0 Lock Status
-#define AT91C_MC_LOCKS1           (0x1 << 17) // (MC) Sector 1 Lock Status
-#define AT91C_MC_LOCKS2           (0x1 << 18) // (MC) Sector 2 Lock Status
-#define AT91C_MC_LOCKS3           (0x1 << 19) // (MC) Sector 3 Lock Status
-#define AT91C_MC_LOCKS4           (0x1 << 20) // (MC) Sector 4 Lock Status
-#define AT91C_MC_LOCKS5           (0x1 << 21) // (MC) Sector 5 Lock Status
-#define AT91C_MC_LOCKS6           (0x1 << 22) // (MC) Sector 6 Lock Status
-#define AT91C_MC_LOCKS7           (0x1 << 23) // (MC) Sector 7 Lock Status
-#define AT91C_MC_LOCKS8           (0x1 << 24) // (MC) Sector 8 Lock Status
-#define AT91C_MC_LOCKS9           (0x1 << 25) // (MC) Sector 9 Lock Status
-#define AT91C_MC_LOCKS10          (0x1 << 26) // (MC) Sector 10 Lock Status
-#define AT91C_MC_LOCKS11          (0x1 << 27) // (MC) Sector 11 Lock Status
-#define AT91C_MC_LOCKS12          (0x1 << 28) // (MC) Sector 12 Lock Status
-#define AT91C_MC_LOCKS13          (0x1 << 29) // (MC) Sector 13 Lock Status
-#define AT91C_MC_LOCKS14          (0x1 << 30) // (MC) Sector 14 Lock Status
-#define AT91C_MC_LOCKS15          (0x1 << 31) // (MC) Sector 15 Lock Status
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Serial Parallel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SPI structure ***
-#define SPI_CR          ( 0) // Control Register
-#define SPI_MR          ( 4) // Mode Register
-#define SPI_RDR         ( 8) // Receive Data Register
-#define SPI_TDR         (12) // Transmit Data Register
-#define SPI_SR          (16) // Status Register
-#define SPI_IER         (20) // Interrupt Enable Register
-#define SPI_IDR         (24) // Interrupt Disable Register
-#define SPI_IMR         (28) // Interrupt Mask Register
-#define SPI_CSR         (48) // Chip Select Register
-#define SPI_RPR         (256) // Receive Pointer Register
-#define SPI_RCR         (260) // Receive Counter Register
-#define SPI_TPR         (264) // Transmit Pointer Register
-#define SPI_TCR         (268) // Transmit Counter Register
-#define SPI_RNPR        (272) // Receive Next Pointer Register
-#define SPI_RNCR        (276) // Receive Next Counter Register
-#define SPI_TNPR        (280) // Transmit Next Pointer Register
-#define SPI_TNCR        (284) // Transmit Next Counter Register
-#define SPI_PTCR        (288) // PDC Transfer Control Register
-#define SPI_PTSR        (292) // PDC Transfer Status Register
-// -------- SPI_CR : (SPI Offset: 0x0) SPI Control Register -------- 
-#define AT91C_SPI_SPIEN           (0x1 <<  0) // (SPI) SPI Enable
-#define AT91C_SPI_SPIDIS          (0x1 <<  1) // (SPI) SPI Disable
-#define AT91C_SPI_SWRST           (0x1 <<  7) // (SPI) SPI Software reset
-#define AT91C_SPI_LASTXFER        (0x1 << 24) // (SPI) SPI Last Transfer
-// -------- SPI_MR : (SPI Offset: 0x4) SPI Mode Register -------- 
-#define AT91C_SPI_MSTR            (0x1 <<  0) // (SPI) Master/Slave Mode
-#define AT91C_SPI_PS              (0x1 <<  1) // (SPI) Peripheral Select
-#define 	AT91C_SPI_PS_FIXED                (0x0 <<  1) // (SPI) Fixed Peripheral Select
-#define 	AT91C_SPI_PS_VARIABLE             (0x1 <<  1) // (SPI) Variable Peripheral Select
-#define AT91C_SPI_PCSDEC          (0x1 <<  2) // (SPI) Chip Select Decode
-#define AT91C_SPI_FDIV            (0x1 <<  3) // (SPI) Clock Selection
-#define AT91C_SPI_MODFDIS         (0x1 <<  4) // (SPI) Mode Fault Detection
-#define AT91C_SPI_LLB             (0x1 <<  7) // (SPI) Clock Selection
-#define AT91C_SPI_PCS             (0xF << 16) // (SPI) Peripheral Chip Select
-#define AT91C_SPI_DLYBCS          (0xFF << 24) // (SPI) Delay Between Chip Selects
-// -------- SPI_RDR : (SPI Offset: 0x8) Receive Data Register -------- 
-#define AT91C_SPI_RD              (0xFFFF <<  0) // (SPI) Receive Data
-#define AT91C_SPI_RPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_TDR : (SPI Offset: 0xc) Transmit Data Register -------- 
-#define AT91C_SPI_TD              (0xFFFF <<  0) // (SPI) Transmit Data
-#define AT91C_SPI_TPCS            (0xF << 16) // (SPI) Peripheral Chip Select Status
-// -------- SPI_SR : (SPI Offset: 0x10) Status Register -------- 
-#define AT91C_SPI_RDRF            (0x1 <<  0) // (SPI) Receive Data Register Full
-#define AT91C_SPI_TDRE            (0x1 <<  1) // (SPI) Transmit Data Register Empty
-#define AT91C_SPI_MODF            (0x1 <<  2) // (SPI) Mode Fault Error
-#define AT91C_SPI_OVRES           (0x1 <<  3) // (SPI) Overrun Error Status
-#define AT91C_SPI_ENDRX           (0x1 <<  4) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_ENDTX           (0x1 <<  5) // (SPI) End of Receiver Transfer
-#define AT91C_SPI_RXBUFF          (0x1 <<  6) // (SPI) RXBUFF Interrupt
-#define AT91C_SPI_TXBUFE          (0x1 <<  7) // (SPI) TXBUFE Interrupt
-#define AT91C_SPI_NSSR            (0x1 <<  8) // (SPI) NSSR Interrupt
-#define AT91C_SPI_TXEMPTY         (0x1 <<  9) // (SPI) TXEMPTY Interrupt
-#define AT91C_SPI_SPIENS          (0x1 << 16) // (SPI) Enable Status
-// -------- SPI_IER : (SPI Offset: 0x14) Interrupt Enable Register -------- 
-// -------- SPI_IDR : (SPI Offset: 0x18) Interrupt Disable Register -------- 
-// -------- SPI_IMR : (SPI Offset: 0x1c) Interrupt Mask Register -------- 
-// -------- SPI_CSR : (SPI Offset: 0x30) Chip Select Register -------- 
-#define AT91C_SPI_CPOL            (0x1 <<  0) // (SPI) Clock Polarity
-#define AT91C_SPI_NCPHA           (0x1 <<  1) // (SPI) Clock Phase
-#define AT91C_SPI_CSAAT           (0x1 <<  3) // (SPI) Chip Select Active After Transfer
-#define AT91C_SPI_BITS            (0xF <<  4) // (SPI) Bits Per Transfer
-#define 	AT91C_SPI_BITS_8                    (0x0 <<  4) // (SPI) 8 Bits Per transfer
-#define 	AT91C_SPI_BITS_9                    (0x1 <<  4) // (SPI) 9 Bits Per transfer
-#define 	AT91C_SPI_BITS_10                   (0x2 <<  4) // (SPI) 10 Bits Per transfer
-#define 	AT91C_SPI_BITS_11                   (0x3 <<  4) // (SPI) 11 Bits Per transfer
-#define 	AT91C_SPI_BITS_12                   (0x4 <<  4) // (SPI) 12 Bits Per transfer
-#define 	AT91C_SPI_BITS_13                   (0x5 <<  4) // (SPI) 13 Bits Per transfer
-#define 	AT91C_SPI_BITS_14                   (0x6 <<  4) // (SPI) 14 Bits Per transfer
-#define 	AT91C_SPI_BITS_15                   (0x7 <<  4) // (SPI) 15 Bits Per transfer
-#define 	AT91C_SPI_BITS_16                   (0x8 <<  4) // (SPI) 16 Bits Per transfer
-#define AT91C_SPI_SCBR            (0xFF <<  8) // (SPI) Serial Clock Baud Rate
-#define AT91C_SPI_DLYBS           (0xFF << 16) // (SPI) Delay Before SPCK
-#define AT91C_SPI_DLYBCT          (0xFF << 24) // (SPI) Delay Between Consecutive Transfers
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Usart
-// *****************************************************************************
-// *** Register offset in AT91S_USART structure ***
-#define US_CR           ( 0) // Control Register
-#define US_MR           ( 4) // Mode Register
-#define US_IER          ( 8) // Interrupt Enable Register
-#define US_IDR          (12) // Interrupt Disable Register
-#define US_IMR          (16) // Interrupt Mask Register
-#define US_CSR          (20) // Channel Status Register
-#define US_RHR          (24) // Receiver Holding Register
-#define US_THR          (28) // Transmitter Holding Register
-#define US_BRGR         (32) // Baud Rate Generator Register
-#define US_RTOR         (36) // Receiver Time-out Register
-#define US_TTGR         (40) // Transmitter Time-guard Register
-#define US_FIDI         (64) // FI_DI_Ratio Register
-#define US_NER          (68) // Nb Errors Register
-#define US_IF           (76) // IRDA_FILTER Register
-#define US_RPR          (256) // Receive Pointer Register
-#define US_RCR          (260) // Receive Counter Register
-#define US_TPR          (264) // Transmit Pointer Register
-#define US_TCR          (268) // Transmit Counter Register
-#define US_RNPR         (272) // Receive Next Pointer Register
-#define US_RNCR         (276) // Receive Next Counter Register
-#define US_TNPR         (280) // Transmit Next Pointer Register
-#define US_TNCR         (284) // Transmit Next Counter Register
-#define US_PTCR         (288) // PDC Transfer Control Register
-#define US_PTSR         (292) // PDC Transfer Status Register
-// -------- US_CR : (USART Offset: 0x0) Debug Unit Control Register -------- 
-#define AT91C_US_STTBRK           (0x1 <<  9) // (USART) Start Break
-#define AT91C_US_STPBRK           (0x1 << 10) // (USART) Stop Break
-#define AT91C_US_STTTO            (0x1 << 11) // (USART) Start Time-out
-#define AT91C_US_SENDA            (0x1 << 12) // (USART) Send Address
-#define AT91C_US_RSTIT            (0x1 << 13) // (USART) Reset Iterations
-#define AT91C_US_RSTNACK          (0x1 << 14) // (USART) Reset Non Acknowledge
-#define AT91C_US_RETTO            (0x1 << 15) // (USART) Rearm Time-out
-#define AT91C_US_DTREN            (0x1 << 16) // (USART) Data Terminal ready Enable
-#define AT91C_US_DTRDIS           (0x1 << 17) // (USART) Data Terminal ready Disable
-#define AT91C_US_RTSEN            (0x1 << 18) // (USART) Request to Send enable
-#define AT91C_US_RTSDIS           (0x1 << 19) // (USART) Request to Send Disable
-// -------- US_MR : (USART Offset: 0x4) Debug Unit Mode Register -------- 
-#define AT91C_US_USMODE           (0xF <<  0) // (USART) Usart mode
-#define 	AT91C_US_USMODE_NORMAL               (0x0) // (USART) Normal
-#define 	AT91C_US_USMODE_RS485                (0x1) // (USART) RS485
-#define 	AT91C_US_USMODE_HWHSH                (0x2) // (USART) Hardware Handshaking
-#define 	AT91C_US_USMODE_MODEM                (0x3) // (USART) Modem
-#define 	AT91C_US_USMODE_ISO7816_0            (0x4) // (USART) ISO7816 protocol: T = 0
-#define 	AT91C_US_USMODE_ISO7816_1            (0x6) // (USART) ISO7816 protocol: T = 1
-#define 	AT91C_US_USMODE_IRDA                 (0x8) // (USART) IrDA
-#define 	AT91C_US_USMODE_SWHSH                (0xC) // (USART) Software Handshaking
-#define AT91C_US_CLKS             (0x3 <<  4) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CLKS_CLOCK                (0x0 <<  4) // (USART) Clock
-#define 	AT91C_US_CLKS_FDIV1                (0x1 <<  4) // (USART) fdiv1
-#define 	AT91C_US_CLKS_SLOW                 (0x2 <<  4) // (USART) slow_clock (ARM)
-#define 	AT91C_US_CLKS_EXT                  (0x3 <<  4) // (USART) External (SCK)
-#define AT91C_US_CHRL             (0x3 <<  6) // (USART) Clock Selection (Baud Rate generator Input Clock
-#define 	AT91C_US_CHRL_5_BITS               (0x0 <<  6) // (USART) Character Length: 5 bits
-#define 	AT91C_US_CHRL_6_BITS               (0x1 <<  6) // (USART) Character Length: 6 bits
-#define 	AT91C_US_CHRL_7_BITS               (0x2 <<  6) // (USART) Character Length: 7 bits
-#define 	AT91C_US_CHRL_8_BITS               (0x3 <<  6) // (USART) Character Length: 8 bits
-#define AT91C_US_SYNC             (0x1 <<  8) // (USART) Synchronous Mode Select
-#define AT91C_US_NBSTOP           (0x3 << 12) // (USART) Number of Stop bits
-#define 	AT91C_US_NBSTOP_1_BIT                (0x0 << 12) // (USART) 1 stop bit
-#define 	AT91C_US_NBSTOP_15_BIT               (0x1 << 12) // (USART) Asynchronous (SYNC=0) 2 stop bits Synchronous (SYNC=1) 2 stop bits
-#define 	AT91C_US_NBSTOP_2_BIT                (0x2 << 12) // (USART) 2 stop bits
-#define AT91C_US_MSBF             (0x1 << 16) // (USART) Bit Order
-#define AT91C_US_MODE9            (0x1 << 17) // (USART) 9-bit Character length
-#define AT91C_US_CKLO             (0x1 << 18) // (USART) Clock Output Select
-#define AT91C_US_OVER             (0x1 << 19) // (USART) Over Sampling Mode
-#define AT91C_US_INACK            (0x1 << 20) // (USART) Inhibit Non Acknowledge
-#define AT91C_US_DSNACK           (0x1 << 21) // (USART) Disable Successive NACK
-#define AT91C_US_MAX_ITER         (0x1 << 24) // (USART) Number of Repetitions
-#define AT91C_US_FILTER           (0x1 << 28) // (USART) Receive Line Filter
-// -------- US_IER : (USART Offset: 0x8) Debug Unit Interrupt Enable Register -------- 
-#define AT91C_US_RXBRK            (0x1 <<  2) // (USART) Break Received/End of Break
-#define AT91C_US_TIMEOUT          (0x1 <<  8) // (USART) Receiver Time-out
-#define AT91C_US_ITERATION        (0x1 << 10) // (USART) Max number of Repetitions Reached
-#define AT91C_US_NACK             (0x1 << 13) // (USART) Non Acknowledge
-#define AT91C_US_RIIC             (0x1 << 16) // (USART) Ring INdicator Input Change Flag
-#define AT91C_US_DSRIC            (0x1 << 17) // (USART) Data Set Ready Input Change Flag
-#define AT91C_US_DCDIC            (0x1 << 18) // (USART) Data Carrier Flag
-#define AT91C_US_CTSIC            (0x1 << 19) // (USART) Clear To Send Input Change Flag
-// -------- US_IDR : (USART Offset: 0xc) Debug Unit Interrupt Disable Register -------- 
-// -------- US_IMR : (USART Offset: 0x10) Debug Unit Interrupt Mask Register -------- 
-// -------- US_CSR : (USART Offset: 0x14) Debug Unit Channel Status Register -------- 
-#define AT91C_US_RI               (0x1 << 20) // (USART) Image of RI Input
-#define AT91C_US_DSR              (0x1 << 21) // (USART) Image of DSR Input
-#define AT91C_US_DCD              (0x1 << 22) // (USART) Image of DCD Input
-#define AT91C_US_CTS              (0x1 << 23) // (USART) Image of CTS Input
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Synchronous Serial Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_SSC structure ***
-#define SSC_CR          ( 0) // Control Register
-#define SSC_CMR         ( 4) // Clock Mode Register
-#define SSC_RCMR        (16) // Receive Clock ModeRegister
-#define SSC_RFMR        (20) // Receive Frame Mode Register
-#define SSC_TCMR        (24) // Transmit Clock Mode Register
-#define SSC_TFMR        (28) // Transmit Frame Mode Register
-#define SSC_RHR         (32) // Receive Holding Register
-#define SSC_THR         (36) // Transmit Holding Register
-#define SSC_RSHR        (48) // Receive Sync Holding Register
-#define SSC_TSHR        (52) // Transmit Sync Holding Register
-#define SSC_SR          (64) // Status Register
-#define SSC_IER         (68) // Interrupt Enable Register
-#define SSC_IDR         (72) // Interrupt Disable Register
-#define SSC_IMR         (76) // Interrupt Mask Register
-#define SSC_RPR         (256) // Receive Pointer Register
-#define SSC_RCR         (260) // Receive Counter Register
-#define SSC_TPR         (264) // Transmit Pointer Register
-#define SSC_TCR         (268) // Transmit Counter Register
-#define SSC_RNPR        (272) // Receive Next Pointer Register
-#define SSC_RNCR        (276) // Receive Next Counter Register
-#define SSC_TNPR        (280) // Transmit Next Pointer Register
-#define SSC_TNCR        (284) // Transmit Next Counter Register
-#define SSC_PTCR        (288) // PDC Transfer Control Register
-#define SSC_PTSR        (292) // PDC Transfer Status Register
-// -------- SSC_CR : (SSC Offset: 0x0) SSC Control Register -------- 
-#define AT91C_SSC_RXEN            (0x1 <<  0) // (SSC) Receive Enable
-#define AT91C_SSC_RXDIS           (0x1 <<  1) // (SSC) Receive Disable
-#define AT91C_SSC_TXEN            (0x1 <<  8) // (SSC) Transmit Enable
-#define AT91C_SSC_TXDIS           (0x1 <<  9) // (SSC) Transmit Disable
-#define AT91C_SSC_SWRST           (0x1 << 15) // (SSC) Software Reset
-// -------- SSC_RCMR : (SSC Offset: 0x10) SSC Receive Clock Mode Register -------- 
-#define AT91C_SSC_CKS             (0x3 <<  0) // (SSC) Receive/Transmit Clock Selection
-#define 	AT91C_SSC_CKS_DIV                  (0x0) // (SSC) Divided Clock
-#define 	AT91C_SSC_CKS_TK                   (0x1) // (SSC) TK Clock signal
-#define 	AT91C_SSC_CKS_RK                   (0x2) // (SSC) RK pin
-#define AT91C_SSC_CKO             (0x7 <<  2) // (SSC) Receive/Transmit Clock Output Mode Selection
-#define 	AT91C_SSC_CKO_NONE                 (0x0 <<  2) // (SSC) Receive/Transmit Clock Output Mode: None RK pin: Input-only
-#define 	AT91C_SSC_CKO_CONTINOUS            (0x1 <<  2) // (SSC) Continuous Receive/Transmit Clock RK pin: Output
-#define 	AT91C_SSC_CKO_DATA_TX              (0x2 <<  2) // (SSC) Receive/Transmit Clock only during data transfers RK pin: Output
-#define AT91C_SSC_CKI             (0x1 <<  5) // (SSC) Receive/Transmit Clock Inversion
-#define AT91C_SSC_START           (0xF <<  8) // (SSC) Receive/Transmit Start Selection
-#define 	AT91C_SSC_START_CONTINOUS            (0x0 <<  8) // (SSC) Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data.
-#define 	AT91C_SSC_START_TX                   (0x1 <<  8) // (SSC) Transmit/Receive start
-#define 	AT91C_SSC_START_LOW_RF               (0x2 <<  8) // (SSC) Detection of a low level on RF input
-#define 	AT91C_SSC_START_HIGH_RF              (0x3 <<  8) // (SSC) Detection of a high level on RF input
-#define 	AT91C_SSC_START_FALL_RF              (0x4 <<  8) // (SSC) Detection of a falling edge on RF input
-#define 	AT91C_SSC_START_RISE_RF              (0x5 <<  8) // (SSC) Detection of a rising edge on RF input
-#define 	AT91C_SSC_START_LEVEL_RF             (0x6 <<  8) // (SSC) Detection of any level change on RF input
-#define 	AT91C_SSC_START_EDGE_RF              (0x7 <<  8) // (SSC) Detection of any edge on RF input
-#define 	AT91C_SSC_START_0                    (0x8 <<  8) // (SSC) Compare 0
-#define AT91C_SSC_STTDLY          (0xFF << 16) // (SSC) Receive/Transmit Start Delay
-#define AT91C_SSC_PERIOD          (0xFF << 24) // (SSC) Receive/Transmit Period Divider Selection
-// -------- SSC_RFMR : (SSC Offset: 0x14) SSC Receive Frame Mode Register -------- 
-#define AT91C_SSC_DATLEN          (0x1F <<  0) // (SSC) Data Length
-#define AT91C_SSC_LOOP            (0x1 <<  5) // (SSC) Loop Mode
-#define AT91C_SSC_MSBF            (0x1 <<  7) // (SSC) Most Significant Bit First
-#define AT91C_SSC_DATNB           (0xF <<  8) // (SSC) Data Number per Frame
-#define AT91C_SSC_FSLEN           (0xF << 16) // (SSC) Receive/Transmit Frame Sync length
-#define AT91C_SSC_FSOS            (0x7 << 20) // (SSC) Receive/Transmit Frame Sync Output Selection
-#define 	AT91C_SSC_FSOS_NONE                 (0x0 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: None RK pin Input-only
-#define 	AT91C_SSC_FSOS_NEGATIVE             (0x1 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Negative Pulse
-#define 	AT91C_SSC_FSOS_POSITIVE             (0x2 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Positive Pulse
-#define 	AT91C_SSC_FSOS_LOW                  (0x3 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver Low during data transfer
-#define 	AT91C_SSC_FSOS_HIGH                 (0x4 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Driver High during data transfer
-#define 	AT91C_SSC_FSOS_TOGGLE               (0x5 << 20) // (SSC) Selected Receive/Transmit Frame Sync Signal: Toggling at each start of data transfer
-#define AT91C_SSC_FSEDGE          (0x1 << 24) // (SSC) Frame Sync Edge Detection
-// -------- SSC_TCMR : (SSC Offset: 0x18) SSC Transmit Clock Mode Register -------- 
-// -------- SSC_TFMR : (SSC Offset: 0x1c) SSC Transmit Frame Mode Register -------- 
-#define AT91C_SSC_DATDEF          (0x1 <<  5) // (SSC) Data Default Value
-#define AT91C_SSC_FSDEN           (0x1 << 23) // (SSC) Frame Sync Data Enable
-// -------- SSC_SR : (SSC Offset: 0x40) SSC Status Register -------- 
-#define AT91C_SSC_TXRDY           (0x1 <<  0) // (SSC) Transmit Ready
-#define AT91C_SSC_TXEMPTY         (0x1 <<  1) // (SSC) Transmit Empty
-#define AT91C_SSC_ENDTX           (0x1 <<  2) // (SSC) End Of Transmission
-#define AT91C_SSC_TXBUFE          (0x1 <<  3) // (SSC) Transmit Buffer Empty
-#define AT91C_SSC_RXRDY           (0x1 <<  4) // (SSC) Receive Ready
-#define AT91C_SSC_OVRUN           (0x1 <<  5) // (SSC) Receive Overrun
-#define AT91C_SSC_ENDRX           (0x1 <<  6) // (SSC) End of Reception
-#define AT91C_SSC_RXBUFF          (0x1 <<  7) // (SSC) Receive Buffer Full
-#define AT91C_SSC_TXSYN           (0x1 << 10) // (SSC) Transmit Sync
-#define AT91C_SSC_RXSYN           (0x1 << 11) // (SSC) Receive Sync
-#define AT91C_SSC_TXENA           (0x1 << 16) // (SSC) Transmit Enable
-#define AT91C_SSC_RXENA           (0x1 << 17) // (SSC) Receive Enable
-// -------- SSC_IER : (SSC Offset: 0x44) SSC Interrupt Enable Register -------- 
-// -------- SSC_IDR : (SSC Offset: 0x48) SSC Interrupt Disable Register -------- 
-// -------- SSC_IMR : (SSC Offset: 0x4c) SSC Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Two-wire Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TWI structure ***
-#define TWI_CR          ( 0) // Control Register
-#define TWI_MMR         ( 4) // Master Mode Register
-#define TWI_IADR        (12) // Internal Address Register
-#define TWI_CWGR        (16) // Clock Waveform Generator Register
-#define TWI_SR          (32) // Status Register
-#define TWI_IER         (36) // Interrupt Enable Register
-#define TWI_IDR         (40) // Interrupt Disable Register
-#define TWI_IMR         (44) // Interrupt Mask Register
-#define TWI_RHR         (48) // Receive Holding Register
-#define TWI_THR         (52) // Transmit Holding Register
-// -------- TWI_CR : (TWI Offset: 0x0) TWI Control Register -------- 
-#define AT91C_TWI_START           (0x1 <<  0) // (TWI) Send a START Condition
-#define AT91C_TWI_STOP            (0x1 <<  1) // (TWI) Send a STOP Condition
-#define AT91C_TWI_MSEN            (0x1 <<  2) // (TWI) TWI Master Transfer Enabled
-#define AT91C_TWI_MSDIS           (0x1 <<  3) // (TWI) TWI Master Transfer Disabled
-#define AT91C_TWI_SWRST           (0x1 <<  7) // (TWI) Software Reset
-// -------- TWI_MMR : (TWI Offset: 0x4) TWI Master Mode Register -------- 
-#define AT91C_TWI_IADRSZ          (0x3 <<  8) // (TWI) Internal Device Address Size
-#define 	AT91C_TWI_IADRSZ_NO                   (0x0 <<  8) // (TWI) No internal device address
-#define 	AT91C_TWI_IADRSZ_1_BYTE               (0x1 <<  8) // (TWI) One-byte internal device address
-#define 	AT91C_TWI_IADRSZ_2_BYTE               (0x2 <<  8) // (TWI) Two-byte internal device address
-#define 	AT91C_TWI_IADRSZ_3_BYTE               (0x3 <<  8) // (TWI) Three-byte internal device address
-#define AT91C_TWI_MREAD           (0x1 << 12) // (TWI) Master Read Direction
-#define AT91C_TWI_DADR            (0x7F << 16) // (TWI) Device Address
-// -------- TWI_CWGR : (TWI Offset: 0x10) TWI Clock Waveform Generator Register -------- 
-#define AT91C_TWI_CLDIV           (0xFF <<  0) // (TWI) Clock Low Divider
-#define AT91C_TWI_CHDIV           (0xFF <<  8) // (TWI) Clock High Divider
-#define AT91C_TWI_CKDIV           (0x7 << 16) // (TWI) Clock Divider
-// -------- TWI_SR : (TWI Offset: 0x20) TWI Status Register -------- 
-#define AT91C_TWI_TXCOMP          (0x1 <<  0) // (TWI) Transmission Completed
-#define AT91C_TWI_RXRDY           (0x1 <<  1) // (TWI) Receive holding register ReaDY
-#define AT91C_TWI_TXRDY           (0x1 <<  2) // (TWI) Transmit holding register ReaDY
-#define AT91C_TWI_OVRE            (0x1 <<  6) // (TWI) Overrun Error
-#define AT91C_TWI_UNRE            (0x1 <<  7) // (TWI) Underrun Error
-#define AT91C_TWI_NACK            (0x1 <<  8) // (TWI) Not Acknowledged
-// -------- TWI_IER : (TWI Offset: 0x24) TWI Interrupt Enable Register -------- 
-// -------- TWI_IDR : (TWI Offset: 0x28) TWI Interrupt Disable Register -------- 
-// -------- TWI_IMR : (TWI Offset: 0x2c) TWI Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR PWMC Channel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PWMC_CH structure ***
-#define PWMC_CMR        ( 0) // Channel Mode Register
-#define PWMC_CDTYR      ( 4) // Channel Duty Cycle Register
-#define PWMC_CPRDR      ( 8) // Channel Period Register
-#define PWMC_CCNTR      (12) // Channel Counter Register
-#define PWMC_CUPDR      (16) // Channel Update Register
-#define PWMC_Reserved   (20) // Reserved
-// -------- PWMC_CMR : (PWMC_CH Offset: 0x0) PWMC Channel Mode Register -------- 
-#define AT91C_PWMC_CPRE           (0xF <<  0) // (PWMC_CH) Channel Pre-scaler : PWMC_CLKx
-#define 	AT91C_PWMC_CPRE_MCK                  (0x0) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKA                 (0xB) // (PWMC_CH) 
-#define 	AT91C_PWMC_CPRE_MCKB                 (0xC) // (PWMC_CH) 
-#define AT91C_PWMC_CALG           (0x1 <<  8) // (PWMC_CH) Channel Alignment
-#define AT91C_PWMC_CPOL           (0x1 <<  9) // (PWMC_CH) Channel Polarity
-#define AT91C_PWMC_CPD            (0x1 << 10) // (PWMC_CH) Channel Update Period
-// -------- PWMC_CDTYR : (PWMC_CH Offset: 0x4) PWMC Channel Duty Cycle Register -------- 
-#define AT91C_PWMC_CDTY           (0x0 <<  0) // (PWMC_CH) Channel Duty Cycle
-// -------- PWMC_CPRDR : (PWMC_CH Offset: 0x8) PWMC Channel Period Register -------- 
-#define AT91C_PWMC_CPRD           (0x0 <<  0) // (PWMC_CH) Channel Period
-// -------- PWMC_CCNTR : (PWMC_CH Offset: 0xc) PWMC Channel Counter Register -------- 
-#define AT91C_PWMC_CCNT           (0x0 <<  0) // (PWMC_CH) Channel Counter
-// -------- PWMC_CUPDR : (PWMC_CH Offset: 0x10) PWMC Channel Update Register -------- 
-#define AT91C_PWMC_CUPD           (0x0 <<  0) // (PWMC_CH) Channel Update
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Pulse Width Modulation Controller Interface
-// *****************************************************************************
-// *** Register offset in AT91S_PWMC structure ***
-#define PWMC_MR         ( 0) // PWMC Mode Register
-#define PWMC_ENA        ( 4) // PWMC Enable Register
-#define PWMC_DIS        ( 8) // PWMC Disable Register
-#define PWMC_SR         (12) // PWMC Status Register
-#define PWMC_IER        (16) // PWMC Interrupt Enable Register
-#define PWMC_IDR        (20) // PWMC Interrupt Disable Register
-#define PWMC_IMR        (24) // PWMC Interrupt Mask Register
-#define PWMC_ISR        (28) // PWMC Interrupt Status Register
-#define PWMC_VR         (252) // PWMC Version Register
-#define PWMC_CH         (512) // PWMC Channel
-// -------- PWMC_MR : (PWMC Offset: 0x0) PWMC Mode Register -------- 
-#define AT91C_PWMC_DIVA           (0xFF <<  0) // (PWMC) CLKA divide factor.
-#define AT91C_PWMC_PREA           (0xF <<  8) // (PWMC) Divider Input Clock Prescaler A
-#define 	AT91C_PWMC_PREA_MCK                  (0x0 <<  8) // (PWMC) 
-#define AT91C_PWMC_DIVB           (0xFF << 16) // (PWMC) CLKB divide factor.
-#define AT91C_PWMC_PREB           (0xF << 24) // (PWMC) Divider Input Clock Prescaler B
-#define 	AT91C_PWMC_PREB_MCK                  (0x0 << 24) // (PWMC) 
-// -------- PWMC_ENA : (PWMC Offset: 0x4) PWMC Enable Register -------- 
-#define AT91C_PWMC_CHID0          (0x1 <<  0) // (PWMC) Channel ID 0
-#define AT91C_PWMC_CHID1          (0x1 <<  1) // (PWMC) Channel ID 1
-#define AT91C_PWMC_CHID2          (0x1 <<  2) // (PWMC) Channel ID 2
-#define AT91C_PWMC_CHID3          (0x1 <<  3) // (PWMC) Channel ID 3
-// -------- PWMC_DIS : (PWMC Offset: 0x8) PWMC Disable Register -------- 
-// -------- PWMC_SR : (PWMC Offset: 0xc) PWMC Status Register -------- 
-// -------- PWMC_IER : (PWMC Offset: 0x10) PWMC Interrupt Enable Register -------- 
-// -------- PWMC_IDR : (PWMC Offset: 0x14) PWMC Interrupt Disable Register -------- 
-// -------- PWMC_IMR : (PWMC Offset: 0x18) PWMC Interrupt Mask Register -------- 
-// -------- PWMC_ISR : (PWMC Offset: 0x1c) PWMC Interrupt Status Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR USB Device Interface
-// *****************************************************************************
-// *** Register offset in AT91S_UDP structure ***
-#define UDP_NUM         ( 0) // Frame Number Register
-#define UDP_GLBSTATE    ( 4) // Global State Register
-#define UDP_FADDR       ( 8) // Function Address Register
-#define UDP_IER         (16) // Interrupt Enable Register
-#define UDP_IDR         (20) // Interrupt Disable Register
-#define UDP_IMR         (24) // Interrupt Mask Register
-#define UDP_ISR         (28) // Interrupt Status Register
-#define UDP_ICR         (32) // Interrupt Clear Register
-#define UDP_RSTEP       (40) // Reset Endpoint Register
-#define UDP_CSR         (48) // Endpoint Control and Status Register
-#define UDP_FDR         (80) // Endpoint FIFO Data Register
-#define UDP_TXVC        (116) // Transceiver Control Register
-// -------- UDP_FRM_NUM : (UDP Offset: 0x0) USB Frame Number Register -------- 
-#define AT91C_UDP_FRM_NUM         (0x7FF <<  0) // (UDP) Frame Number as Defined in the Packet Field Formats
-#define AT91C_UDP_FRM_ERR         (0x1 << 16) // (UDP) Frame Error
-#define AT91C_UDP_FRM_OK          (0x1 << 17) // (UDP) Frame OK
-// -------- UDP_GLB_STATE : (UDP Offset: 0x4) USB Global State Register -------- 
-#define AT91C_UDP_FADDEN          (0x1 <<  0) // (UDP) Function Address Enable
-#define AT91C_UDP_CONFG           (0x1 <<  1) // (UDP) Configured
-#define AT91C_UDP_ESR             (0x1 <<  2) // (UDP) Enable Send Resume
-#define AT91C_UDP_RSMINPR         (0x1 <<  3) // (UDP) A Resume Has Been Sent to the Host
-#define AT91C_UDP_RMWUPE          (0x1 <<  4) // (UDP) Remote Wake Up Enable
-// -------- UDP_FADDR : (UDP Offset: 0x8) USB Function Address Register -------- 
-#define AT91C_UDP_FADD            (0xFF <<  0) // (UDP) Function Address Value
-#define AT91C_UDP_FEN             (0x1 <<  8) // (UDP) Function Enable
-// -------- UDP_IER : (UDP Offset: 0x10) USB Interrupt Enable Register -------- 
-#define AT91C_UDP_EPINT0          (0x1 <<  0) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT1          (0x1 <<  1) // (UDP) Endpoint 0 Interrupt
-#define AT91C_UDP_EPINT2          (0x1 <<  2) // (UDP) Endpoint 2 Interrupt
-#define AT91C_UDP_EPINT3          (0x1 <<  3) // (UDP) Endpoint 3 Interrupt
-#define AT91C_UDP_EPINT4          (0x1 <<  4) // (UDP) Endpoint 4 Interrupt
-#define AT91C_UDP_EPINT5          (0x1 <<  5) // (UDP) Endpoint 5 Interrupt
-#define AT91C_UDP_RXSUSP          (0x1 <<  8) // (UDP) USB Suspend Interrupt
-#define AT91C_UDP_RXRSM           (0x1 <<  9) // (UDP) USB Resume Interrupt
-#define AT91C_UDP_EXTRSM          (0x1 << 10) // (UDP) USB External Resume Interrupt
-#define AT91C_UDP_SOFINT          (0x1 << 11) // (UDP) USB Start Of frame Interrupt
-#define AT91C_UDP_WAKEUP          (0x1 << 13) // (UDP) USB Resume Interrupt
-// -------- UDP_IDR : (UDP Offset: 0x14) USB Interrupt Disable Register -------- 
-// -------- UDP_IMR : (UDP Offset: 0x18) USB Interrupt Mask Register -------- 
-// -------- UDP_ISR : (UDP Offset: 0x1c) USB Interrupt Status Register -------- 
-#define AT91C_UDP_ENDBUSRES       (0x1 << 12) // (UDP) USB End Of Bus Reset Interrupt
-// -------- UDP_ICR : (UDP Offset: 0x20) USB Interrupt Clear Register -------- 
-// -------- UDP_RST_EP : (UDP Offset: 0x28) USB Reset Endpoint Register -------- 
-#define AT91C_UDP_EP0             (0x1 <<  0) // (UDP) Reset Endpoint 0
-#define AT91C_UDP_EP1             (0x1 <<  1) // (UDP) Reset Endpoint 1
-#define AT91C_UDP_EP2             (0x1 <<  2) // (UDP) Reset Endpoint 2
-#define AT91C_UDP_EP3             (0x1 <<  3) // (UDP) Reset Endpoint 3
-#define AT91C_UDP_EP4             (0x1 <<  4) // (UDP) Reset Endpoint 4
-#define AT91C_UDP_EP5             (0x1 <<  5) // (UDP) Reset Endpoint 5
-// -------- UDP_CSR : (UDP Offset: 0x30) USB Endpoint Control and Status Register -------- 
-#define AT91C_UDP_TXCOMP          (0x1 <<  0) // (UDP) Generates an IN packet with data previously written in the DPR
-#define AT91C_UDP_RX_DATA_BK0     (0x1 <<  1) // (UDP) Receive Data Bank 0
-#define AT91C_UDP_RXSETUP         (0x1 <<  2) // (UDP) Sends STALL to the Host (Control endpoints)
-#define AT91C_UDP_ISOERROR        (0x1 <<  3) // (UDP) Isochronous error (Isochronous endpoints)
-#define AT91C_UDP_TXPKTRDY        (0x1 <<  4) // (UDP) Transmit Packet Ready
-#define AT91C_UDP_FORCESTALL      (0x1 <<  5) // (UDP) Force Stall (used by Control, Bulk and Isochronous endpoints).
-#define AT91C_UDP_RX_DATA_BK1     (0x1 <<  6) // (UDP) Receive Data Bank 1 (only used by endpoints with ping-pong attributes).
-#define AT91C_UDP_DIR             (0x1 <<  7) // (UDP) Transfer Direction
-#define AT91C_UDP_EPTYPE          (0x7 <<  8) // (UDP) Endpoint type
-#define 	AT91C_UDP_EPTYPE_CTRL                 (0x0 <<  8) // (UDP) Control
-#define 	AT91C_UDP_EPTYPE_ISO_OUT              (0x1 <<  8) // (UDP) Isochronous OUT
-#define 	AT91C_UDP_EPTYPE_BULK_OUT             (0x2 <<  8) // (UDP) Bulk OUT
-#define 	AT91C_UDP_EPTYPE_INT_OUT              (0x3 <<  8) // (UDP) Interrupt OUT
-#define 	AT91C_UDP_EPTYPE_ISO_IN               (0x5 <<  8) // (UDP) Isochronous IN
-#define 	AT91C_UDP_EPTYPE_BULK_IN              (0x6 <<  8) // (UDP) Bulk IN
-#define 	AT91C_UDP_EPTYPE_INT_IN               (0x7 <<  8) // (UDP) Interrupt IN
-#define AT91C_UDP_DTGLE           (0x1 << 11) // (UDP) Data Toggle
-#define AT91C_UDP_EPEDS           (0x1 << 15) // (UDP) Endpoint Enable Disable
-#define AT91C_UDP_RXBYTECNT       (0x7FF << 16) // (UDP) Number Of Bytes Available in the FIFO
-// -------- UDP_TXVC : (UDP Offset: 0x74) Transceiver Control Register -------- 
-#define AT91C_UDP_TXVDIS          (0x1 <<  8) // (UDP) 
-#define AT91C_UDP_PUON            (0x1 <<  9) // (UDP) Pull-up ON
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Channel Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TC structure ***
-#define TC_CCR          ( 0) // Channel Control Register
-#define TC_CMR          ( 4) // Channel Mode Register (Capture Mode / Waveform Mode)
-#define TC_CV           (16) // Counter Value
-#define TC_RA           (20) // Register A
-#define TC_RB           (24) // Register B
-#define TC_RC           (28) // Register C
-#define TC_SR           (32) // Status Register
-#define TC_IER          (36) // Interrupt Enable Register
-#define TC_IDR          (40) // Interrupt Disable Register
-#define TC_IMR          (44) // Interrupt Mask Register
-// -------- TC_CCR : (TC Offset: 0x0) TC Channel Control Register -------- 
-#define AT91C_TC_CLKEN            (0x1 <<  0) // (TC) Counter Clock Enable Command
-#define AT91C_TC_CLKDIS           (0x1 <<  1) // (TC) Counter Clock Disable Command
-#define AT91C_TC_SWTRG            (0x1 <<  2) // (TC) Software Trigger Command
-// -------- TC_CMR : (TC Offset: 0x4) TC Channel Mode Register: Capture Mode / Waveform Mode -------- 
-#define AT91C_TC_CLKS             (0x7 <<  0) // (TC) Clock Selection
-#define 	AT91C_TC_CLKS_TIMER_DIV1_CLOCK     (0x0) // (TC) Clock selected: TIMER_DIV1_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV2_CLOCK     (0x1) // (TC) Clock selected: TIMER_DIV2_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV3_CLOCK     (0x2) // (TC) Clock selected: TIMER_DIV3_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV4_CLOCK     (0x3) // (TC) Clock selected: TIMER_DIV4_CLOCK
-#define 	AT91C_TC_CLKS_TIMER_DIV5_CLOCK     (0x4) // (TC) Clock selected: TIMER_DIV5_CLOCK
-#define 	AT91C_TC_CLKS_XC0                  (0x5) // (TC) Clock selected: XC0
-#define 	AT91C_TC_CLKS_XC1                  (0x6) // (TC) Clock selected: XC1
-#define 	AT91C_TC_CLKS_XC2                  (0x7) // (TC) Clock selected: XC2
-#define AT91C_TC_CLKI             (0x1 <<  3) // (TC) Clock Invert
-#define AT91C_TC_BURST            (0x3 <<  4) // (TC) Burst Signal Selection
-#define 	AT91C_TC_BURST_NONE                 (0x0 <<  4) // (TC) The clock is not gated by an external signal
-#define 	AT91C_TC_BURST_XC0                  (0x1 <<  4) // (TC) XC0 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC1                  (0x2 <<  4) // (TC) XC1 is ANDed with the selected clock
-#define 	AT91C_TC_BURST_XC2                  (0x3 <<  4) // (TC) XC2 is ANDed with the selected clock
-#define AT91C_TC_CPCSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RC Compare
-#define AT91C_TC_LDBSTOP          (0x1 <<  6) // (TC) Counter Clock Stopped with RB Loading
-#define AT91C_TC_CPCDIS           (0x1 <<  7) // (TC) Counter Clock Disable with RC Compare
-#define AT91C_TC_LDBDIS           (0x1 <<  7) // (TC) Counter Clock Disabled with RB Loading
-#define AT91C_TC_ETRGEDG          (0x3 <<  8) // (TC) External Trigger Edge Selection
-#define 	AT91C_TC_ETRGEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_ETRGEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_ETRGEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_ETRGEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVTEDG          (0x3 <<  8) // (TC) External Event Edge Selection
-#define 	AT91C_TC_EEVTEDG_NONE                 (0x0 <<  8) // (TC) Edge: None
-#define 	AT91C_TC_EEVTEDG_RISING               (0x1 <<  8) // (TC) Edge: rising edge
-#define 	AT91C_TC_EEVTEDG_FALLING              (0x2 <<  8) // (TC) Edge: falling edge
-#define 	AT91C_TC_EEVTEDG_BOTH                 (0x3 <<  8) // (TC) Edge: each edge
-#define AT91C_TC_EEVT             (0x3 << 10) // (TC) External Event  Selection
-#define 	AT91C_TC_EEVT_TIOB                 (0x0 << 10) // (TC) Signal selected as external event: TIOB TIOB direction: input
-#define 	AT91C_TC_EEVT_XC0                  (0x1 << 10) // (TC) Signal selected as external event: XC0 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC1                  (0x2 << 10) // (TC) Signal selected as external event: XC1 TIOB direction: output
-#define 	AT91C_TC_EEVT_XC2                  (0x3 << 10) // (TC) Signal selected as external event: XC2 TIOB direction: output
-#define AT91C_TC_ABETRG           (0x1 << 10) // (TC) TIOA or TIOB External Trigger Selection
-#define AT91C_TC_ENETRG           (0x1 << 12) // (TC) External Event Trigger enable
-#define AT91C_TC_WAVESEL          (0x3 << 13) // (TC) Waveform  Selection
-#define 	AT91C_TC_WAVESEL_UP                   (0x0 << 13) // (TC) UP mode without atomatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN               (0x1 << 13) // (TC) UPDOWN mode without automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UP_AUTO              (0x2 << 13) // (TC) UP mode with automatic trigger on RC Compare
-#define 	AT91C_TC_WAVESEL_UPDOWN_AUTO          (0x3 << 13) // (TC) UPDOWN mode with automatic trigger on RC Compare
-#define AT91C_TC_CPCTRG           (0x1 << 14) // (TC) RC Compare Trigger Enable
-#define AT91C_TC_WAVE             (0x1 << 15) // (TC) 
-#define AT91C_TC_ACPA             (0x3 << 16) // (TC) RA Compare Effect on TIOA
-#define 	AT91C_TC_ACPA_NONE                 (0x0 << 16) // (TC) Effect: none
-#define 	AT91C_TC_ACPA_SET                  (0x1 << 16) // (TC) Effect: set
-#define 	AT91C_TC_ACPA_CLEAR                (0x2 << 16) // (TC) Effect: clear
-#define 	AT91C_TC_ACPA_TOGGLE               (0x3 << 16) // (TC) Effect: toggle
-#define AT91C_TC_LDRA             (0x3 << 16) // (TC) RA Loading Selection
-#define 	AT91C_TC_LDRA_NONE                 (0x0 << 16) // (TC) Edge: None
-#define 	AT91C_TC_LDRA_RISING               (0x1 << 16) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRA_FALLING              (0x2 << 16) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRA_BOTH                 (0x3 << 16) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_ACPC             (0x3 << 18) // (TC) RC Compare Effect on TIOA
-#define 	AT91C_TC_ACPC_NONE                 (0x0 << 18) // (TC) Effect: none
-#define 	AT91C_TC_ACPC_SET                  (0x1 << 18) // (TC) Effect: set
-#define 	AT91C_TC_ACPC_CLEAR                (0x2 << 18) // (TC) Effect: clear
-#define 	AT91C_TC_ACPC_TOGGLE               (0x3 << 18) // (TC) Effect: toggle
-#define AT91C_TC_LDRB             (0x3 << 18) // (TC) RB Loading Selection
-#define 	AT91C_TC_LDRB_NONE                 (0x0 << 18) // (TC) Edge: None
-#define 	AT91C_TC_LDRB_RISING               (0x1 << 18) // (TC) Edge: rising edge of TIOA
-#define 	AT91C_TC_LDRB_FALLING              (0x2 << 18) // (TC) Edge: falling edge of TIOA
-#define 	AT91C_TC_LDRB_BOTH                 (0x3 << 18) // (TC) Edge: each edge of TIOA
-#define AT91C_TC_AEEVT            (0x3 << 20) // (TC) External Event Effect on TIOA
-#define 	AT91C_TC_AEEVT_NONE                 (0x0 << 20) // (TC) Effect: none
-#define 	AT91C_TC_AEEVT_SET                  (0x1 << 20) // (TC) Effect: set
-#define 	AT91C_TC_AEEVT_CLEAR                (0x2 << 20) // (TC) Effect: clear
-#define 	AT91C_TC_AEEVT_TOGGLE               (0x3 << 20) // (TC) Effect: toggle
-#define AT91C_TC_ASWTRG           (0x3 << 22) // (TC) Software Trigger Effect on TIOA
-#define 	AT91C_TC_ASWTRG_NONE                 (0x0 << 22) // (TC) Effect: none
-#define 	AT91C_TC_ASWTRG_SET                  (0x1 << 22) // (TC) Effect: set
-#define 	AT91C_TC_ASWTRG_CLEAR                (0x2 << 22) // (TC) Effect: clear
-#define 	AT91C_TC_ASWTRG_TOGGLE               (0x3 << 22) // (TC) Effect: toggle
-#define AT91C_TC_BCPB             (0x3 << 24) // (TC) RB Compare Effect on TIOB
-#define 	AT91C_TC_BCPB_NONE                 (0x0 << 24) // (TC) Effect: none
-#define 	AT91C_TC_BCPB_SET                  (0x1 << 24) // (TC) Effect: set
-#define 	AT91C_TC_BCPB_CLEAR                (0x2 << 24) // (TC) Effect: clear
-#define 	AT91C_TC_BCPB_TOGGLE               (0x3 << 24) // (TC) Effect: toggle
-#define AT91C_TC_BCPC             (0x3 << 26) // (TC) RC Compare Effect on TIOB
-#define 	AT91C_TC_BCPC_NONE                 (0x0 << 26) // (TC) Effect: none
-#define 	AT91C_TC_BCPC_SET                  (0x1 << 26) // (TC) Effect: set
-#define 	AT91C_TC_BCPC_CLEAR                (0x2 << 26) // (TC) Effect: clear
-#define 	AT91C_TC_BCPC_TOGGLE               (0x3 << 26) // (TC) Effect: toggle
-#define AT91C_TC_BEEVT            (0x3 << 28) // (TC) External Event Effect on TIOB
-#define 	AT91C_TC_BEEVT_NONE                 (0x0 << 28) // (TC) Effect: none
-#define 	AT91C_TC_BEEVT_SET                  (0x1 << 28) // (TC) Effect: set
-#define 	AT91C_TC_BEEVT_CLEAR                (0x2 << 28) // (TC) Effect: clear
-#define 	AT91C_TC_BEEVT_TOGGLE               (0x3 << 28) // (TC) Effect: toggle
-#define AT91C_TC_BSWTRG           (0x3 << 30) // (TC) Software Trigger Effect on TIOB
-#define 	AT91C_TC_BSWTRG_NONE                 (0x0 << 30) // (TC) Effect: none
-#define 	AT91C_TC_BSWTRG_SET                  (0x1 << 30) // (TC) Effect: set
-#define 	AT91C_TC_BSWTRG_CLEAR                (0x2 << 30) // (TC) Effect: clear
-#define 	AT91C_TC_BSWTRG_TOGGLE               (0x3 << 30) // (TC) Effect: toggle
-// -------- TC_SR : (TC Offset: 0x20) TC Channel Status Register -------- 
-#define AT91C_TC_COVFS            (0x1 <<  0) // (TC) Counter Overflow
-#define AT91C_TC_LOVRS            (0x1 <<  1) // (TC) Load Overrun
-#define AT91C_TC_CPAS             (0x1 <<  2) // (TC) RA Compare
-#define AT91C_TC_CPBS             (0x1 <<  3) // (TC) RB Compare
-#define AT91C_TC_CPCS             (0x1 <<  4) // (TC) RC Compare
-#define AT91C_TC_LDRAS            (0x1 <<  5) // (TC) RA Loading
-#define AT91C_TC_LDRBS            (0x1 <<  6) // (TC) RB Loading
-#define AT91C_TC_ETRGS            (0x1 <<  7) // (TC) External Trigger
-#define AT91C_TC_CLKSTA           (0x1 << 16) // (TC) Clock Enabling
-#define AT91C_TC_MTIOA            (0x1 << 17) // (TC) TIOA Mirror
-#define AT91C_TC_MTIOB            (0x1 << 18) // (TC) TIOA Mirror
-// -------- TC_IER : (TC Offset: 0x24) TC Channel Interrupt Enable Register -------- 
-// -------- TC_IDR : (TC Offset: 0x28) TC Channel Interrupt Disable Register -------- 
-// -------- TC_IMR : (TC Offset: 0x2c) TC Channel Interrupt Mask Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Timer Counter Interface
-// *****************************************************************************
-// *** Register offset in AT91S_TCB structure ***
-#define TCB_TC0         ( 0) // TC Channel 0
-#define TCB_TC1         (64) // TC Channel 1
-#define TCB_TC2         (128) // TC Channel 2
-#define TCB_BCR         (192) // TC Block Control Register
-#define TCB_BMR         (196) // TC Block Mode Register
-// -------- TCB_BCR : (TCB Offset: 0xc0) TC Block Control Register -------- 
-#define AT91C_TCB_SYNC            (0x1 <<  0) // (TCB) Synchro Command
-// -------- TCB_BMR : (TCB Offset: 0xc4) TC Block Mode Register -------- 
-#define AT91C_TCB_TC0XC0S         (0x3 <<  0) // (TCB) External Clock Signal 0 Selection
-#define 	AT91C_TCB_TC0XC0S_TCLK0                (0x0) // (TCB) TCLK0 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_NONE                 (0x1) // (TCB) None signal connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA1                (0x2) // (TCB) TIOA1 connected to XC0
-#define 	AT91C_TCB_TC0XC0S_TIOA2                (0x3) // (TCB) TIOA2 connected to XC0
-#define AT91C_TCB_TC1XC1S         (0x3 <<  2) // (TCB) External Clock Signal 1 Selection
-#define 	AT91C_TCB_TC1XC1S_TCLK1                (0x0 <<  2) // (TCB) TCLK1 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_NONE                 (0x1 <<  2) // (TCB) None signal connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA0                (0x2 <<  2) // (TCB) TIOA0 connected to XC1
-#define 	AT91C_TCB_TC1XC1S_TIOA2                (0x3 <<  2) // (TCB) TIOA2 connected to XC1
-#define AT91C_TCB_TC2XC2S         (0x3 <<  4) // (TCB) External Clock Signal 2 Selection
-#define 	AT91C_TCB_TC2XC2S_TCLK2                (0x0 <<  4) // (TCB) TCLK2 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_NONE                 (0x1 <<  4) // (TCB) None signal connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA0                (0x2 <<  4) // (TCB) TIOA0 connected to XC2
-#define 	AT91C_TCB_TC2XC2S_TIOA1                (0x3 <<  4) // (TCB) TIOA2 connected to XC2
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network MailBox Interface
-// *****************************************************************************
-// *** Register offset in AT91S_CAN_MB structure ***
-#define CAN_MB_MMR      ( 0) // MailBox Mode Register
-#define CAN_MB_MAM      ( 4) // MailBox Acceptance Mask Register
-#define CAN_MB_MID      ( 8) // MailBox ID Register
-#define CAN_MB_MFID     (12) // MailBox Family ID Register
-#define CAN_MB_MSR      (16) // MailBox Status Register
-#define CAN_MB_MDL      (20) // MailBox Data Low Register
-#define CAN_MB_MDH      (24) // MailBox Data High Register
-#define CAN_MB_MCR      (28) // MailBox Control Register
-// -------- CAN_MMR : (CAN_MB Offset: 0x0) CAN Message Mode Register -------- 
-#define AT91C_CAN_MTIMEMARK       (0xFFFF <<  0) // (CAN_MB) Mailbox Timemark
-#define AT91C_CAN_PRIOR           (0xF << 16) // (CAN_MB) Mailbox Priority
-#define AT91C_CAN_MOT             (0x7 << 24) // (CAN_MB) Mailbox Object Type
-#define 	AT91C_CAN_MOT_DIS                  (0x0 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RX                   (0x1 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_RXOVERWRITE          (0x2 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_TX                   (0x3 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_CONSUMER             (0x4 << 24) // (CAN_MB) 
-#define 	AT91C_CAN_MOT_PRODUCER             (0x5 << 24) // (CAN_MB) 
-// -------- CAN_MAM : (CAN_MB Offset: 0x4) CAN Message Acceptance Mask Register -------- 
-#define AT91C_CAN_MIDvB           (0x3FFFF <<  0) // (CAN_MB) Complementary bits for identifier in extended mode
-#define AT91C_CAN_MIDvA           (0x7FF << 18) // (CAN_MB) Identifier for standard frame mode
-#define AT91C_CAN_MIDE            (0x1 << 29) // (CAN_MB) Identifier Version
-// -------- CAN_MID : (CAN_MB Offset: 0x8) CAN Message ID Register -------- 
-// -------- CAN_MFID : (CAN_MB Offset: 0xc) CAN Message Family ID Register -------- 
-// -------- CAN_MSR : (CAN_MB Offset: 0x10) CAN Message Status Register -------- 
-#define AT91C_CAN_MTIMESTAMP      (0xFFFF <<  0) // (CAN_MB) Timer Value
-#define AT91C_CAN_MDLC            (0xF << 16) // (CAN_MB) Mailbox Data Length Code
-#define AT91C_CAN_MRTR            (0x1 << 20) // (CAN_MB) Mailbox Remote Transmission Request
-#define AT91C_CAN_MABT            (0x1 << 22) // (CAN_MB) Mailbox Message Abort
-#define AT91C_CAN_MRDY            (0x1 << 23) // (CAN_MB) Mailbox Ready
-#define AT91C_CAN_MMI             (0x1 << 24) // (CAN_MB) Mailbox Message Ignored
-// -------- CAN_MDL : (CAN_MB Offset: 0x14) CAN Message Data Low Register -------- 
-// -------- CAN_MDH : (CAN_MB Offset: 0x18) CAN Message Data High Register -------- 
-// -------- CAN_MCR : (CAN_MB Offset: 0x1c) CAN Message Control Register -------- 
-#define AT91C_CAN_MACR            (0x1 << 22) // (CAN_MB) Abort Request for Mailbox
-#define AT91C_CAN_MTCR            (0x1 << 23) // (CAN_MB) Mailbox Transfer Command
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Control Area Network Interface
-// *****************************************************************************
-// *** Register offset in AT91S_CAN structure ***
-#define CAN_MR          ( 0) // Mode Register
-#define CAN_IER         ( 4) // Interrupt Enable Register
-#define CAN_IDR         ( 8) // Interrupt Disable Register
-#define CAN_IMR         (12) // Interrupt Mask Register
-#define CAN_SR          (16) // Status Register
-#define CAN_BR          (20) // Baudrate Register
-#define CAN_TIM         (24) // Timer Register
-#define CAN_TIMESTP     (28) // Time Stamp Register
-#define CAN_ECR         (32) // Error Counter Register
-#define CAN_TCR         (36) // Transfer Command Register
-#define CAN_ACR         (40) // Abort Command Register
-#define CAN_VR          (252) // Version Register
-#define CAN_MB0         (512) // CAN Mailbox 0
-#define CAN_MB1         (544) // CAN Mailbox 1
-#define CAN_MB2         (576) // CAN Mailbox 2
-#define CAN_MB3         (608) // CAN Mailbox 3
-#define CAN_MB4         (640) // CAN Mailbox 4
-#define CAN_MB5         (672) // CAN Mailbox 5
-#define CAN_MB6         (704) // CAN Mailbox 6
-#define CAN_MB7         (736) // CAN Mailbox 7
-#define CAN_MB8         (768) // CAN Mailbox 8
-#define CAN_MB9         (800) // CAN Mailbox 9
-#define CAN_MB10        (832) // CAN Mailbox 10
-#define CAN_MB11        (864) // CAN Mailbox 11
-#define CAN_MB12        (896) // CAN Mailbox 12
-#define CAN_MB13        (928) // CAN Mailbox 13
-#define CAN_MB14        (960) // CAN Mailbox 14
-#define CAN_MB15        (992) // CAN Mailbox 15
-// -------- CAN_MR : (CAN Offset: 0x0) CAN Mode Register -------- 
-#define AT91C_CAN_CANEN           (0x1 <<  0) // (CAN) CAN Controller Enable
-#define AT91C_CAN_LPM             (0x1 <<  1) // (CAN) Disable/Enable Low Power Mode
-#define AT91C_CAN_ABM             (0x1 <<  2) // (CAN) Disable/Enable Autobaud/Listen Mode
-#define AT91C_CAN_OVL             (0x1 <<  3) // (CAN) Disable/Enable Overload Frame
-#define AT91C_CAN_TEOF            (0x1 <<  4) // (CAN) Time Stamp messages at each end of Frame
-#define AT91C_CAN_TTM             (0x1 <<  5) // (CAN) Disable/Enable Time Trigger Mode
-#define AT91C_CAN_TIMFRZ          (0x1 <<  6) // (CAN) Enable Timer Freeze
-#define AT91C_CAN_DRPT            (0x1 <<  7) // (CAN) Disable Repeat
-// -------- CAN_IER : (CAN Offset: 0x4) CAN Interrupt Enable Register -------- 
-#define AT91C_CAN_MB0             (0x1 <<  0) // (CAN) Mailbox 0 Flag
-#define AT91C_CAN_MB1             (0x1 <<  1) // (CAN) Mailbox 1 Flag
-#define AT91C_CAN_MB2             (0x1 <<  2) // (CAN) Mailbox 2 Flag
-#define AT91C_CAN_MB3             (0x1 <<  3) // (CAN) Mailbox 3 Flag
-#define AT91C_CAN_MB4             (0x1 <<  4) // (CAN) Mailbox 4 Flag
-#define AT91C_CAN_MB5             (0x1 <<  5) // (CAN) Mailbox 5 Flag
-#define AT91C_CAN_MB6             (0x1 <<  6) // (CAN) Mailbox 6 Flag
-#define AT91C_CAN_MB7             (0x1 <<  7) // (CAN) Mailbox 7 Flag
-#define AT91C_CAN_MB8             (0x1 <<  8) // (CAN) Mailbox 8 Flag
-#define AT91C_CAN_MB9             (0x1 <<  9) // (CAN) Mailbox 9 Flag
-#define AT91C_CAN_MB10            (0x1 << 10) // (CAN) Mailbox 10 Flag
-#define AT91C_CAN_MB11            (0x1 << 11) // (CAN) Mailbox 11 Flag
-#define AT91C_CAN_MB12            (0x1 << 12) // (CAN) Mailbox 12 Flag
-#define AT91C_CAN_MB13            (0x1 << 13) // (CAN) Mailbox 13 Flag
-#define AT91C_CAN_MB14            (0x1 << 14) // (CAN) Mailbox 14 Flag
-#define AT91C_CAN_MB15            (0x1 << 15) // (CAN) Mailbox 15 Flag
-#define AT91C_CAN_ERRA            (0x1 << 16) // (CAN) Error Active Mode Flag
-#define AT91C_CAN_WARN            (0x1 << 17) // (CAN) Warning Limit Flag
-#define AT91C_CAN_ERRP            (0x1 << 18) // (CAN) Error Passive Mode Flag
-#define AT91C_CAN_BOFF            (0x1 << 19) // (CAN) Bus Off Mode Flag
-#define AT91C_CAN_SLEEP           (0x1 << 20) // (CAN) Sleep Flag
-#define AT91C_CAN_WAKEUP          (0x1 << 21) // (CAN) Wakeup Flag
-#define AT91C_CAN_TOVF            (0x1 << 22) // (CAN) Timer Overflow Flag
-#define AT91C_CAN_TSTP            (0x1 << 23) // (CAN) Timestamp Flag
-#define AT91C_CAN_CERR            (0x1 << 24) // (CAN) CRC Error
-#define AT91C_CAN_SERR            (0x1 << 25) // (CAN) Stuffing Error
-#define AT91C_CAN_AERR            (0x1 << 26) // (CAN) Acknowledgment Error
-#define AT91C_CAN_FERR            (0x1 << 27) // (CAN) Form Error
-#define AT91C_CAN_BERR            (0x1 << 28) // (CAN) Bit Error
-// -------- CAN_IDR : (CAN Offset: 0x8) CAN Interrupt Disable Register -------- 
-// -------- CAN_IMR : (CAN Offset: 0xc) CAN Interrupt Mask Register -------- 
-// -------- CAN_SR : (CAN Offset: 0x10) CAN Status Register -------- 
-#define AT91C_CAN_RBSY            (0x1 << 29) // (CAN) Receiver Busy
-#define AT91C_CAN_TBSY            (0x1 << 30) // (CAN) Transmitter Busy
-#define AT91C_CAN_OVLY            (0x1 << 31) // (CAN) Overload Busy
-// -------- CAN_BR : (CAN Offset: 0x14) CAN Baudrate Register -------- 
-#define AT91C_CAN_PHASE2          (0x7 <<  0) // (CAN) Phase 2 segment
-#define AT91C_CAN_PHASE1          (0x7 <<  4) // (CAN) Phase 1 segment
-#define AT91C_CAN_PROPAG          (0x7 <<  8) // (CAN) Programmation time segment
-#define AT91C_CAN_SYNC            (0x3 << 12) // (CAN) Re-synchronization jump width segment
-#define AT91C_CAN_BRP             (0x7F << 16) // (CAN) Baudrate Prescaler
-#define AT91C_CAN_SMP             (0x1 << 24) // (CAN) Sampling mode
-// -------- CAN_TIM : (CAN Offset: 0x18) CAN Timer Register -------- 
-#define AT91C_CAN_TIMER           (0xFFFF <<  0) // (CAN) Timer field
-// -------- CAN_TIMESTP : (CAN Offset: 0x1c) CAN Timestamp Register -------- 
-// -------- CAN_ECR : (CAN Offset: 0x20) CAN Error Counter Register -------- 
-#define AT91C_CAN_REC             (0xFF <<  0) // (CAN) Receive Error Counter
-#define AT91C_CAN_TEC             (0xFF << 16) // (CAN) Transmit Error Counter
-// -------- CAN_TCR : (CAN Offset: 0x24) CAN Transfer Command Register -------- 
-#define AT91C_CAN_TIMRST          (0x1 << 31) // (CAN) Timer Reset Field
-// -------- CAN_ACR : (CAN Offset: 0x28) CAN Abort Command Register -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Ethernet MAC 10/100
-// *****************************************************************************
-// *** Register offset in AT91S_EMAC structure ***
-#define EMAC_NCR        ( 0) // Network Control Register
-#define EMAC_NCFGR      ( 4) // Network Configuration Register
-#define EMAC_NSR        ( 8) // Network Status Register
-#define EMAC_TSR        (20) // Transmit Status Register
-#define EMAC_RBQP       (24) // Receive Buffer Queue Pointer
-#define EMAC_TBQP       (28) // Transmit Buffer Queue Pointer
-#define EMAC_RSR        (32) // Receive Status Register
-#define EMAC_ISR        (36) // Interrupt Status Register
-#define EMAC_IER        (40) // Interrupt Enable Register
-#define EMAC_IDR        (44) // Interrupt Disable Register
-#define EMAC_IMR        (48) // Interrupt Mask Register
-#define EMAC_MAN        (52) // PHY Maintenance Register
-#define EMAC_PTR        (56) // Pause Time Register
-#define EMAC_PFR        (60) // Pause Frames received Register
-#define EMAC_FTO        (64) // Frames Transmitted OK Register
-#define EMAC_SCF        (68) // Single Collision Frame Register
-#define EMAC_MCF        (72) // Multiple Collision Frame Register
-#define EMAC_FRO        (76) // Frames Received OK Register
-#define EMAC_FCSE       (80) // Frame Check Sequence Error Register
-#define EMAC_ALE        (84) // Alignment Error Register
-#define EMAC_DTF        (88) // Deferred Transmission Frame Register
-#define EMAC_LCOL       (92) // Late Collision Register
-#define EMAC_ECOL       (96) // Excessive Collision Register
-#define EMAC_TUND       (100) // Transmit Underrun Error Register
-#define EMAC_CSE        (104) // Carrier Sense Error Register
-#define EMAC_RRE        (108) // Receive Ressource Error Register
-#define EMAC_ROV        (112) // Receive Overrun Errors Register
-#define EMAC_RSE        (116) // Receive Symbol Errors Register
-#define EMAC_ELE        (120) // Excessive Length Errors Register
-#define EMAC_RJA        (124) // Receive Jabbers Register
-#define EMAC_USF        (128) // Undersize Frames Register
-#define EMAC_STE        (132) // SQE Test Error Register
-#define EMAC_RLE        (136) // Receive Length Field Mismatch Register
-#define EMAC_TPF        (140) // Transmitted Pause Frames Register
-#define EMAC_HRB        (144) // Hash Address Bottom[31:0]
-#define EMAC_HRT        (148) // Hash Address Top[63:32]
-#define EMAC_SA1L       (152) // Specific Address 1 Bottom, First 4 bytes
-#define EMAC_SA1H       (156) // Specific Address 1 Top, Last 2 bytes
-#define EMAC_SA2L       (160) // Specific Address 2 Bottom, First 4 bytes
-#define EMAC_SA2H       (164) // Specific Address 2 Top, Last 2 bytes
-#define EMAC_SA3L       (168) // Specific Address 3 Bottom, First 4 bytes
-#define EMAC_SA3H       (172) // Specific Address 3 Top, Last 2 bytes
-#define EMAC_SA4L       (176) // Specific Address 4 Bottom, First 4 bytes
-#define EMAC_SA4H       (180) // Specific Address 4 Top, Last 2 bytes
-#define EMAC_TID        (184) // Type ID Checking Register
-#define EMAC_TPQ        (188) // Transmit Pause Quantum Register
-#define EMAC_USRIO      (192) // USER Input/Output Register
-#define EMAC_WOL        (196) // Wake On LAN Register
-#define EMAC_REV        (252) // Revision Register
-// -------- EMAC_NCR : (EMAC Offset: 0x0)  -------- 
-#define AT91C_EMAC_LB             (0x1 <<  0) // (EMAC) Loopback. Optional. When set, loopback signal is at high level.
-#define AT91C_EMAC_LLB            (0x1 <<  1) // (EMAC) Loopback local. 
-#define AT91C_EMAC_RE             (0x1 <<  2) // (EMAC) Receive enable. 
-#define AT91C_EMAC_TE             (0x1 <<  3) // (EMAC) Transmit enable. 
-#define AT91C_EMAC_MPE            (0x1 <<  4) // (EMAC) Management port enable. 
-#define AT91C_EMAC_CLRSTAT        (0x1 <<  5) // (EMAC) Clear statistics registers. 
-#define AT91C_EMAC_INCSTAT        (0x1 <<  6) // (EMAC) Increment statistics registers. 
-#define AT91C_EMAC_WESTAT         (0x1 <<  7) // (EMAC) Write enable for statistics registers. 
-#define AT91C_EMAC_BP             (0x1 <<  8) // (EMAC) Back pressure. 
-#define AT91C_EMAC_TSTART         (0x1 <<  9) // (EMAC) Start Transmission. 
-#define AT91C_EMAC_THALT          (0x1 << 10) // (EMAC) Transmission Halt. 
-#define AT91C_EMAC_TPFR           (0x1 << 11) // (EMAC) Transmit pause frame 
-#define AT91C_EMAC_TZQ            (0x1 << 12) // (EMAC) Transmit zero quantum pause frame
-// -------- EMAC_NCFGR : (EMAC Offset: 0x4) Network Configuration Register -------- 
-#define AT91C_EMAC_SPD            (0x1 <<  0) // (EMAC) Speed. 
-#define AT91C_EMAC_FD             (0x1 <<  1) // (EMAC) Full duplex. 
-#define AT91C_EMAC_JFRAME         (0x1 <<  3) // (EMAC) Jumbo Frames. 
-#define AT91C_EMAC_CAF            (0x1 <<  4) // (EMAC) Copy all frames. 
-#define AT91C_EMAC_NBC            (0x1 <<  5) // (EMAC) No broadcast. 
-#define AT91C_EMAC_MTI            (0x1 <<  6) // (EMAC) Multicast hash event enable
-#define AT91C_EMAC_UNI            (0x1 <<  7) // (EMAC) Unicast hash enable. 
-#define AT91C_EMAC_BIG            (0x1 <<  8) // (EMAC) Receive 1522 bytes. 
-#define AT91C_EMAC_EAE            (0x1 <<  9) // (EMAC) External address match enable. 
-#define AT91C_EMAC_CLK            (0x3 << 10) // (EMAC) 
-#define 	AT91C_EMAC_CLK_HCLK_8               (0x0 << 10) // (EMAC) HCLK divided by 8
-#define 	AT91C_EMAC_CLK_HCLK_16              (0x1 << 10) // (EMAC) HCLK divided by 16
-#define 	AT91C_EMAC_CLK_HCLK_32              (0x2 << 10) // (EMAC) HCLK divided by 32
-#define 	AT91C_EMAC_CLK_HCLK_64              (0x3 << 10) // (EMAC) HCLK divided by 64
-#define AT91C_EMAC_RTY            (0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PAE            (0x1 << 13) // (EMAC) 
-#define AT91C_EMAC_RBOF           (0x3 << 14) // (EMAC) 
-#define 	AT91C_EMAC_RBOF_OFFSET_0             (0x0 << 14) // (EMAC) no offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_1             (0x1 << 14) // (EMAC) one byte offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_2             (0x2 << 14) // (EMAC) two bytes offset from start of receive buffer
-#define 	AT91C_EMAC_RBOF_OFFSET_3             (0x3 << 14) // (EMAC) three bytes offset from start of receive buffer
-#define AT91C_EMAC_RLCE           (0x1 << 16) // (EMAC) Receive Length field Checking Enable
-#define AT91C_EMAC_DRFCS          (0x1 << 17) // (EMAC) Discard Receive FCS
-#define AT91C_EMAC_EFRHD          (0x1 << 18) // (EMAC) 
-#define AT91C_EMAC_IRXFCS         (0x1 << 19) // (EMAC) Ignore RX FCS
-// -------- EMAC_NSR : (EMAC Offset: 0x8) Network Status Register -------- 
-#define AT91C_EMAC_LINKR          (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_MDIO           (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_IDLE           (0x1 <<  2) // (EMAC) 
-// -------- EMAC_TSR : (EMAC Offset: 0x14) Transmit Status Register -------- 
-#define AT91C_EMAC_UBR            (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_COL            (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RLES           (0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TGO            (0x1 <<  3) // (EMAC) Transmit Go
-#define AT91C_EMAC_BEX            (0x1 <<  4) // (EMAC) Buffers exhausted mid frame
-#define AT91C_EMAC_COMP           (0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_UND            (0x1 <<  6) // (EMAC) 
-// -------- EMAC_RSR : (EMAC Offset: 0x20) Receive Status Register -------- 
-#define AT91C_EMAC_BNA            (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_REC            (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_OVR            (0x1 <<  2) // (EMAC) 
-// -------- EMAC_ISR : (EMAC Offset: 0x24) Interrupt Status Register -------- 
-#define AT91C_EMAC_MFD            (0x1 <<  0) // (EMAC) 
-#define AT91C_EMAC_RCOMP          (0x1 <<  1) // (EMAC) 
-#define AT91C_EMAC_RXUBR          (0x1 <<  2) // (EMAC) 
-#define AT91C_EMAC_TXUBR          (0x1 <<  3) // (EMAC) 
-#define AT91C_EMAC_TUNDR          (0x1 <<  4) // (EMAC) 
-#define AT91C_EMAC_RLEX           (0x1 <<  5) // (EMAC) 
-#define AT91C_EMAC_TXERR          (0x1 <<  6) // (EMAC) 
-#define AT91C_EMAC_TCOMP          (0x1 <<  7) // (EMAC) 
-#define AT91C_EMAC_LINK           (0x1 <<  9) // (EMAC) 
-#define AT91C_EMAC_ROVR           (0x1 << 10) // (EMAC) 
-#define AT91C_EMAC_HRESP          (0x1 << 11) // (EMAC) 
-#define AT91C_EMAC_PFRE           (0x1 << 12) // (EMAC) 
-#define AT91C_EMAC_PTZ            (0x1 << 13) // (EMAC) 
-// -------- EMAC_IER : (EMAC Offset: 0x28) Interrupt Enable Register -------- 
-// -------- EMAC_IDR : (EMAC Offset: 0x2c) Interrupt Disable Register -------- 
-// -------- EMAC_IMR : (EMAC Offset: 0x30) Interrupt Mask Register -------- 
-// -------- EMAC_MAN : (EMAC Offset: 0x34) PHY Maintenance Register -------- 
-#define AT91C_EMAC_DATA           (0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_CODE           (0x3 << 16) // (EMAC) 
-#define AT91C_EMAC_REGA           (0x1F << 18) // (EMAC) 
-#define AT91C_EMAC_PHYA           (0x1F << 23) // (EMAC) 
-#define AT91C_EMAC_RW             (0x3 << 28) // (EMAC) 
-#define AT91C_EMAC_SOF            (0x3 << 30) // (EMAC) 
-// -------- EMAC_USRIO : (EMAC Offset: 0xc0) USER Input Output Register -------- 
-#define AT91C_EMAC_RMII           (0x1 <<  0) // (EMAC) Reduce MII
-// -------- EMAC_WOL : (EMAC Offset: 0xc4) Wake On LAN Register -------- 
-#define AT91C_EMAC_IP             (0xFFFF <<  0) // (EMAC) ARP request IP address
-#define AT91C_EMAC_MAG            (0x1 << 16) // (EMAC) Magic packet event enable
-#define AT91C_EMAC_ARP            (0x1 << 17) // (EMAC) ARP request event enable
-#define AT91C_EMAC_SA1            (0x1 << 18) // (EMAC) Specific address register 1 event enable
-// -------- EMAC_REV : (EMAC Offset: 0xfc) Revision Register -------- 
-#define AT91C_EMAC_REVREF         (0xFFFF <<  0) // (EMAC) 
-#define AT91C_EMAC_PARTREF        (0xFFFF << 16) // (EMAC) 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Analog to Digital Convertor
-// *****************************************************************************
-// *** Register offset in AT91S_ADC structure ***
-#define ADC_CR          ( 0) // ADC Control Register
-#define ADC_MR          ( 4) // ADC Mode Register
-#define ADC_CHER        (16) // ADC Channel Enable Register
-#define ADC_CHDR        (20) // ADC Channel Disable Register
-#define ADC_CHSR        (24) // ADC Channel Status Register
-#define ADC_SR          (28) // ADC Status Register
-#define ADC_LCDR        (32) // ADC Last Converted Data Register
-#define ADC_IER         (36) // ADC Interrupt Enable Register
-#define ADC_IDR         (40) // ADC Interrupt Disable Register
-#define ADC_IMR         (44) // ADC Interrupt Mask Register
-#define ADC_CDR0        (48) // ADC Channel Data Register 0
-#define ADC_CDR1        (52) // ADC Channel Data Register 1
-#define ADC_CDR2        (56) // ADC Channel Data Register 2
-#define ADC_CDR3        (60) // ADC Channel Data Register 3
-#define ADC_CDR4        (64) // ADC Channel Data Register 4
-#define ADC_CDR5        (68) // ADC Channel Data Register 5
-#define ADC_CDR6        (72) // ADC Channel Data Register 6
-#define ADC_CDR7        (76) // ADC Channel Data Register 7
-#define ADC_RPR         (256) // Receive Pointer Register
-#define ADC_RCR         (260) // Receive Counter Register
-#define ADC_TPR         (264) // Transmit Pointer Register
-#define ADC_TCR         (268) // Transmit Counter Register
-#define ADC_RNPR        (272) // Receive Next Pointer Register
-#define ADC_RNCR        (276) // Receive Next Counter Register
-#define ADC_TNPR        (280) // Transmit Next Pointer Register
-#define ADC_TNCR        (284) // Transmit Next Counter Register
-#define ADC_PTCR        (288) // PDC Transfer Control Register
-#define ADC_PTSR        (292) // PDC Transfer Status Register
-// -------- ADC_CR : (ADC Offset: 0x0) ADC Control Register -------- 
-#define AT91C_ADC_SWRST           (0x1 <<  0) // (ADC) Software Reset
-#define AT91C_ADC_START           (0x1 <<  1) // (ADC) Start Conversion
-// -------- ADC_MR : (ADC Offset: 0x4) ADC Mode Register -------- 
-#define AT91C_ADC_TRGEN           (0x1 <<  0) // (ADC) Trigger Enable
-#define 	AT91C_ADC_TRGEN_DIS                  (0x0) // (ADC) Hradware triggers are disabled. Starting a conversion is only possible by software
-#define 	AT91C_ADC_TRGEN_EN                   (0x1) // (ADC) Hardware trigger selected by TRGSEL field is enabled.
-#define AT91C_ADC_TRGSEL          (0x7 <<  1) // (ADC) Trigger Selection
-#define 	AT91C_ADC_TRGSEL_TIOA0                (0x0 <<  1) // (ADC) Selected TRGSEL = TIAO0
-#define 	AT91C_ADC_TRGSEL_TIOA1                (0x1 <<  1) // (ADC) Selected TRGSEL = TIAO1
-#define 	AT91C_ADC_TRGSEL_TIOA2                (0x2 <<  1) // (ADC) Selected TRGSEL = TIAO2
-#define 	AT91C_ADC_TRGSEL_TIOA3                (0x3 <<  1) // (ADC) Selected TRGSEL = TIAO3
-#define 	AT91C_ADC_TRGSEL_TIOA4                (0x4 <<  1) // (ADC) Selected TRGSEL = TIAO4
-#define 	AT91C_ADC_TRGSEL_TIOA5                (0x5 <<  1) // (ADC) Selected TRGSEL = TIAO5
-#define 	AT91C_ADC_TRGSEL_EXT                  (0x6 <<  1) // (ADC) Selected TRGSEL = External Trigger
-#define AT91C_ADC_LOWRES          (0x1 <<  4) // (ADC) Resolution.
-#define 	AT91C_ADC_LOWRES_10_BIT               (0x0 <<  4) // (ADC) 10-bit resolution
-#define 	AT91C_ADC_LOWRES_8_BIT                (0x1 <<  4) // (ADC) 8-bit resolution
-#define AT91C_ADC_SLEEP           (0x1 <<  5) // (ADC) Sleep Mode
-#define 	AT91C_ADC_SLEEP_NORMAL_MODE          (0x0 <<  5) // (ADC) Normal Mode
-#define 	AT91C_ADC_SLEEP_MODE                 (0x1 <<  5) // (ADC) Sleep Mode
-#define AT91C_ADC_PRESCAL         (0x3F <<  8) // (ADC) Prescaler rate selection
-#define AT91C_ADC_STARTUP         (0x1F << 16) // (ADC) Startup Time
-#define AT91C_ADC_SHTIM           (0xF << 24) // (ADC) Sample & Hold Time
-// -------- 	ADC_CHER : (ADC Offset: 0x10) ADC Channel Enable Register -------- 
-#define AT91C_ADC_CH0             (0x1 <<  0) // (ADC) Channel 0
-#define AT91C_ADC_CH1             (0x1 <<  1) // (ADC) Channel 1
-#define AT91C_ADC_CH2             (0x1 <<  2) // (ADC) Channel 2
-#define AT91C_ADC_CH3             (0x1 <<  3) // (ADC) Channel 3
-#define AT91C_ADC_CH4             (0x1 <<  4) // (ADC) Channel 4
-#define AT91C_ADC_CH5             (0x1 <<  5) // (ADC) Channel 5
-#define AT91C_ADC_CH6             (0x1 <<  6) // (ADC) Channel 6
-#define AT91C_ADC_CH7             (0x1 <<  7) // (ADC) Channel 7
-// -------- 	ADC_CHDR : (ADC Offset: 0x14) ADC Channel Disable Register -------- 
-// -------- 	ADC_CHSR : (ADC Offset: 0x18) ADC Channel Status Register -------- 
-// -------- ADC_SR : (ADC Offset: 0x1c) ADC Status Register -------- 
-#define AT91C_ADC_EOC0            (0x1 <<  0) // (ADC) End of Conversion
-#define AT91C_ADC_EOC1            (0x1 <<  1) // (ADC) End of Conversion
-#define AT91C_ADC_EOC2            (0x1 <<  2) // (ADC) End of Conversion
-#define AT91C_ADC_EOC3            (0x1 <<  3) // (ADC) End of Conversion
-#define AT91C_ADC_EOC4            (0x1 <<  4) // (ADC) End of Conversion
-#define AT91C_ADC_EOC5            (0x1 <<  5) // (ADC) End of Conversion
-#define AT91C_ADC_EOC6            (0x1 <<  6) // (ADC) End of Conversion
-#define AT91C_ADC_EOC7            (0x1 <<  7) // (ADC) End of Conversion
-#define AT91C_ADC_OVRE0           (0x1 <<  8) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE1           (0x1 <<  9) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE2           (0x1 << 10) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE3           (0x1 << 11) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE4           (0x1 << 12) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE5           (0x1 << 13) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE6           (0x1 << 14) // (ADC) Overrun Error
-#define AT91C_ADC_OVRE7           (0x1 << 15) // (ADC) Overrun Error
-#define AT91C_ADC_DRDY            (0x1 << 16) // (ADC) Data Ready
-#define AT91C_ADC_GOVRE           (0x1 << 17) // (ADC) General Overrun
-#define AT91C_ADC_ENDRX           (0x1 << 18) // (ADC) End of Receiver Transfer
-#define AT91C_ADC_RXBUFF          (0x1 << 19) // (ADC) RXBUFF Interrupt
-// -------- ADC_LCDR : (ADC Offset: 0x20) ADC Last Converted Data Register -------- 
-#define AT91C_ADC_LDATA           (0x3FF <<  0) // (ADC) Last Data Converted
-// -------- ADC_IER : (ADC Offset: 0x24) ADC Interrupt Enable Register -------- 
-// -------- ADC_IDR : (ADC Offset: 0x28) ADC Interrupt Disable Register -------- 
-// -------- ADC_IMR : (ADC Offset: 0x2c) ADC Interrupt Mask Register -------- 
-// -------- ADC_CDR0 : (ADC Offset: 0x30) ADC Channel Data Register 0 -------- 
-#define AT91C_ADC_DATA            (0x3FF <<  0) // (ADC) Converted Data
-// -------- ADC_CDR1 : (ADC Offset: 0x34) ADC Channel Data Register 1 -------- 
-// -------- ADC_CDR2 : (ADC Offset: 0x38) ADC Channel Data Register 2 -------- 
-// -------- ADC_CDR3 : (ADC Offset: 0x3c) ADC Channel Data Register 3 -------- 
-// -------- ADC_CDR4 : (ADC Offset: 0x40) ADC Channel Data Register 4 -------- 
-// -------- ADC_CDR5 : (ADC Offset: 0x44) ADC Channel Data Register 5 -------- 
-// -------- ADC_CDR6 : (ADC Offset: 0x48) ADC Channel Data Register 6 -------- 
-// -------- ADC_CDR7 : (ADC Offset: 0x4c) ADC Channel Data Register 7 -------- 
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Advanced  Encryption Standard
-// *****************************************************************************
-// *** Register offset in AT91S_AES structure ***
-#define AES_CR          ( 0) // Control Register
-#define AES_MR          ( 4) // Mode Register
-#define AES_IER         (16) // Interrupt Enable Register
-#define AES_IDR         (20) // Interrupt Disable Register
-#define AES_IMR         (24) // Interrupt Mask Register
-#define AES_ISR         (28) // Interrupt Status Register
-#define AES_KEYWxR      (32) // Key Word x Register
-#define AES_IDATAxR     (64) // Input Data x Register
-#define AES_ODATAxR     (80) // Output Data x Register
-#define AES_IVxR        (96) // Initialization Vector x Register
-#define AES_VR          (252) // AES Version Register
-#define AES_RPR         (256) // Receive Pointer Register
-#define AES_RCR         (260) // Receive Counter Register
-#define AES_TPR         (264) // Transmit Pointer Register
-#define AES_TCR         (268) // Transmit Counter Register
-#define AES_RNPR        (272) // Receive Next Pointer Register
-#define AES_RNCR        (276) // Receive Next Counter Register
-#define AES_TNPR        (280) // Transmit Next Pointer Register
-#define AES_TNCR        (284) // Transmit Next Counter Register
-#define AES_PTCR        (288) // PDC Transfer Control Register
-#define AES_PTSR        (292) // PDC Transfer Status Register
-// -------- AES_CR : (AES Offset: 0x0) Control Register -------- 
-#define AT91C_AES_START           (0x1 <<  0) // (AES) Starts Processing
-#define AT91C_AES_SWRST           (0x1 <<  8) // (AES) Software Reset
-#define AT91C_AES_LOADSEED        (0x1 << 16) // (AES) Random Number Generator Seed Loading
-// -------- AES_MR : (AES Offset: 0x4) Mode Register -------- 
-#define AT91C_AES_CIPHER          (0x1 <<  0) // (AES) Processing Mode
-#define AT91C_AES_PROCDLY         (0xF <<  4) // (AES) Processing Delay
-#define AT91C_AES_SMOD            (0x3 <<  8) // (AES) Start Mode
-#define 	AT91C_AES_SMOD_MANUAL               (0x0 <<  8) // (AES) Manual Mode: The START bit in register AES_CR must be set to begin encryption or decryption.
-#define 	AT91C_AES_SMOD_AUTO                 (0x1 <<  8) // (AES) Auto Mode: no action in AES_CR is necessary (cf datasheet).
-#define 	AT91C_AES_SMOD_PDC                  (0x2 <<  8) // (AES) PDC Mode (cf datasheet).
-#define AT91C_AES_OPMOD           (0x7 << 12) // (AES) Operation Mode
-#define 	AT91C_AES_OPMOD_ECB                  (0x0 << 12) // (AES) ECB Electronic CodeBook mode.
-#define 	AT91C_AES_OPMOD_CBC                  (0x1 << 12) // (AES) CBC Cipher Block Chaining mode.
-#define 	AT91C_AES_OPMOD_OFB                  (0x2 << 12) // (AES) OFB Output Feedback mode.
-#define 	AT91C_AES_OPMOD_CFB                  (0x3 << 12) // (AES) CFB Cipher Feedback mode.
-#define 	AT91C_AES_OPMOD_CTR                  (0x4 << 12) // (AES) CTR Counter mode.
-#define AT91C_AES_LOD             (0x1 << 15) // (AES) Last Output Data Mode
-#define AT91C_AES_CFBS            (0x7 << 16) // (AES) Cipher Feedback Data Size
-#define 	AT91C_AES_CFBS_128_BIT              (0x0 << 16) // (AES) 128-bit.
-#define 	AT91C_AES_CFBS_64_BIT               (0x1 << 16) // (AES) 64-bit.
-#define 	AT91C_AES_CFBS_32_BIT               (0x2 << 16) // (AES) 32-bit.
-#define 	AT91C_AES_CFBS_16_BIT               (0x3 << 16) // (AES) 16-bit.
-#define 	AT91C_AES_CFBS_8_BIT                (0x4 << 16) // (AES) 8-bit.
-#define AT91C_AES_CKEY            (0xF << 20) // (AES) Countermeasure Key
-#define AT91C_AES_CTYPE           (0x1F << 24) // (AES) Countermeasure Type
-#define 	AT91C_AES_CTYPE_TYPE1_EN             (0x1 << 24) // (AES) Countermeasure type 1 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE2_EN             (0x2 << 24) // (AES) Countermeasure type 2 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE3_EN             (0x4 << 24) // (AES) Countermeasure type 3 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE4_EN             (0x8 << 24) // (AES) Countermeasure type 4 is enabled.
-#define 	AT91C_AES_CTYPE_TYPE5_EN             (0x10 << 24) // (AES) Countermeasure type 5 is enabled.
-// -------- AES_IER : (AES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_AES_DATRDY          (0x1 <<  0) // (AES) DATRDY
-#define AT91C_AES_ENDRX           (0x1 <<  1) // (AES) PDC Read Buffer End
-#define AT91C_AES_ENDTX           (0x1 <<  2) // (AES) PDC Write Buffer End
-#define AT91C_AES_RXBUFF          (0x1 <<  3) // (AES) PDC Read Buffer Full
-#define AT91C_AES_TXBUFE          (0x1 <<  4) // (AES) PDC Write Buffer Empty
-#define AT91C_AES_URAD            (0x1 <<  8) // (AES) Unspecified Register Access Detection
-// -------- AES_IDR : (AES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- AES_IMR : (AES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- AES_ISR : (AES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_AES_URAT            (0x7 << 12) // (AES) Unspecified Register Access Type Status
-#define 	AT91C_AES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (AES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (AES) Output data register read during the data processing.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (AES) Mode register written during the data processing.
-#define 	AT91C_AES_URAT_OUT_DAT_READ_SUBKEY  (0x3 << 12) // (AES) Output data register read during the sub-keys generation.
-#define 	AT91C_AES_URAT_MODEREG_WRITE_SUBKEY (0x4 << 12) // (AES) Mode register written during the sub-keys generation.
-#define 	AT91C_AES_URAT_WO_REG_READ          (0x5 << 12) // (AES) Write-only register read access.
-
-// *****************************************************************************
-//              SOFTWARE API DEFINITION  FOR Triple Data Encryption Standard
-// *****************************************************************************
-// *** Register offset in AT91S_TDES structure ***
-#define TDES_CR         ( 0) // Control Register
-#define TDES_MR         ( 4) // Mode Register
-#define TDES_IER        (16) // Interrupt Enable Register
-#define TDES_IDR        (20) // Interrupt Disable Register
-#define TDES_IMR        (24) // Interrupt Mask Register
-#define TDES_ISR        (28) // Interrupt Status Register
-#define TDES_KEY1WxR    (32) // Key 1 Word x Register
-#define TDES_KEY2WxR    (40) // Key 2 Word x Register
-#define TDES_KEY3WxR    (48) // Key 3 Word x Register
-#define TDES_IDATAxR    (64) // Input Data x Register
-#define TDES_ODATAxR    (80) // Output Data x Register
-#define TDES_IVxR       (96) // Initialization Vector x Register
-#define TDES_VR         (252) // TDES Version Register
-#define TDES_RPR        (256) // Receive Pointer Register
-#define TDES_RCR        (260) // Receive Counter Register
-#define TDES_TPR        (264) // Transmit Pointer Register
-#define TDES_TCR        (268) // Transmit Counter Register
-#define TDES_RNPR       (272) // Receive Next Pointer Register
-#define TDES_RNCR       (276) // Receive Next Counter Register
-#define TDES_TNPR       (280) // Transmit Next Pointer Register
-#define TDES_TNCR       (284) // Transmit Next Counter Register
-#define TDES_PTCR       (288) // PDC Transfer Control Register
-#define TDES_PTSR       (292) // PDC Transfer Status Register
-// -------- TDES_CR : (TDES Offset: 0x0) Control Register -------- 
-#define AT91C_TDES_START          (0x1 <<  0) // (TDES) Starts Processing
-#define AT91C_TDES_SWRST          (0x1 <<  8) // (TDES) Software Reset
-// -------- TDES_MR : (TDES Offset: 0x4) Mode Register -------- 
-#define AT91C_TDES_CIPHER         (0x1 <<  0) // (TDES) Processing Mode
-#define AT91C_TDES_TDESMOD        (0x1 <<  1) // (TDES) Single or Triple DES Mode
-#define AT91C_TDES_KEYMOD         (0x1 <<  4) // (TDES) Key Mode
-#define AT91C_TDES_SMOD           (0x3 <<  8) // (TDES) Start Mode
-#define 	AT91C_TDES_SMOD_MANUAL               (0x0 <<  8) // (TDES) Manual Mode: The START bit in register TDES_CR must be set to begin encryption or decryption.
-#define 	AT91C_TDES_SMOD_AUTO                 (0x1 <<  8) // (TDES) Auto Mode: no action in TDES_CR is necessary (cf datasheet).
-#define 	AT91C_TDES_SMOD_PDC                  (0x2 <<  8) // (TDES) PDC Mode (cf datasheet).
-#define AT91C_TDES_OPMOD          (0x3 << 12) // (TDES) Operation Mode
-#define 	AT91C_TDES_OPMOD_ECB                  (0x0 << 12) // (TDES) ECB Electronic CodeBook mode.
-#define 	AT91C_TDES_OPMOD_CBC                  (0x1 << 12) // (TDES) CBC Cipher Block Chaining mode.
-#define 	AT91C_TDES_OPMOD_OFB                  (0x2 << 12) // (TDES) OFB Output Feedback mode.
-#define 	AT91C_TDES_OPMOD_CFB                  (0x3 << 12) // (TDES) CFB Cipher Feedback mode.
-#define AT91C_TDES_LOD            (0x1 << 15) // (TDES) Last Output Data Mode
-#define AT91C_TDES_CFBS           (0x3 << 16) // (TDES) Cipher Feedback Data Size
-#define 	AT91C_TDES_CFBS_64_BIT               (0x0 << 16) // (TDES) 64-bit.
-#define 	AT91C_TDES_CFBS_32_BIT               (0x1 << 16) // (TDES) 32-bit.
-#define 	AT91C_TDES_CFBS_16_BIT               (0x2 << 16) // (TDES) 16-bit.
-#define 	AT91C_TDES_CFBS_8_BIT                (0x3 << 16) // (TDES) 8-bit.
-// -------- TDES_IER : (TDES Offset: 0x10) Interrupt Enable Register -------- 
-#define AT91C_TDES_DATRDY         (0x1 <<  0) // (TDES) DATRDY
-#define AT91C_TDES_ENDRX          (0x1 <<  1) // (TDES) PDC Read Buffer End
-#define AT91C_TDES_ENDTX          (0x1 <<  2) // (TDES) PDC Write Buffer End
-#define AT91C_TDES_RXBUFF         (0x1 <<  3) // (TDES) PDC Read Buffer Full
-#define AT91C_TDES_TXBUFE         (0x1 <<  4) // (TDES) PDC Write Buffer Empty
-#define AT91C_TDES_URAD           (0x1 <<  8) // (TDES) Unspecified Register Access Detection
-// -------- TDES_IDR : (TDES Offset: 0x14) Interrupt Disable Register -------- 
-// -------- TDES_IMR : (TDES Offset: 0x18) Interrupt Mask Register -------- 
-// -------- TDES_ISR : (TDES Offset: 0x1c) Interrupt Status Register -------- 
-#define AT91C_TDES_URAT           (0x3 << 12) // (TDES) Unspecified Register Access Type Status
-#define 	AT91C_TDES_URAT_IN_DAT_WRITE_DATPROC (0x0 << 12) // (TDES) Input data register written during the data processing in PDC mode.
-#define 	AT91C_TDES_URAT_OUT_DAT_READ_DATPROC (0x1 << 12) // (TDES) Output data register read during the data processing.
-#define 	AT91C_TDES_URAT_MODEREG_WRITE_DATPROC (0x2 << 12) // (TDES) Mode register written during the data processing.
-#define 	AT91C_TDES_URAT_WO_REG_READ          (0x3 << 12) // (TDES) Write-only register read access.
-
-// *****************************************************************************
-//               REGISTER ADDRESS DEFINITION FOR AT91SAM7X256
-// *****************************************************************************
-// ========== Register definition for SYS peripheral ========== 
-// ========== Register definition for AIC peripheral ========== 
-#define AT91C_AIC_IVR             (0xFFFFF100) // (AIC) IRQ Vector Register
-#define AT91C_AIC_SMR             (0xFFFFF000) // (AIC) Source Mode Register
-#define AT91C_AIC_FVR             (0xFFFFF104) // (AIC) FIQ Vector Register
-#define AT91C_AIC_DCR             (0xFFFFF138) // (AIC) Debug Control Register (Protect)
-#define AT91C_AIC_EOICR           (0xFFFFF130) // (AIC) End of Interrupt Command Register
-#define AT91C_AIC_SVR             (0xFFFFF080) // (AIC) Source Vector Register
-#define AT91C_AIC_FFSR            (0xFFFFF148) // (AIC) Fast Forcing Status Register
-#define AT91C_AIC_ICCR            (0xFFFFF128) // (AIC) Interrupt Clear Command Register
-#define AT91C_AIC_ISR             (0xFFFFF108) // (AIC) Interrupt Status Register
-#define AT91C_AIC_IMR             (0xFFFFF110) // (AIC) Interrupt Mask Register
-#define AT91C_AIC_IPR             (0xFFFFF10C) // (AIC) Interrupt Pending Register
-#define AT91C_AIC_FFER            (0xFFFFF140) // (AIC) Fast Forcing Enable Register
-#define AT91C_AIC_IECR            (0xFFFFF120) // (AIC) Interrupt Enable Command Register
-#define AT91C_AIC_ISCR            (0xFFFFF12C) // (AIC) Interrupt Set Command Register
-#define AT91C_AIC_FFDR            (0xFFFFF144) // (AIC) Fast Forcing Disable Register
-#define AT91C_AIC_CISR            (0xFFFFF114) // (AIC) Core Interrupt Status Register
-#define AT91C_AIC_IDCR            (0xFFFFF124) // (AIC) Interrupt Disable Command Register
-#define AT91C_AIC_SPU             (0xFFFFF134) // (AIC) Spurious Vector Register
-// ========== Register definition for PDC_DBGU peripheral ========== 
-#define AT91C_DBGU_TCR            (0xFFFFF30C) // (PDC_DBGU) Transmit Counter Register
-#define AT91C_DBGU_RNPR           (0xFFFFF310) // (PDC_DBGU) Receive Next Pointer Register
-#define AT91C_DBGU_TNPR           (0xFFFFF318) // (PDC_DBGU) Transmit Next Pointer Register
-#define AT91C_DBGU_TPR            (0xFFFFF308) // (PDC_DBGU) Transmit Pointer Register
-#define AT91C_DBGU_RPR            (0xFFFFF300) // (PDC_DBGU) Receive Pointer Register
-#define AT91C_DBGU_RCR            (0xFFFFF304) // (PDC_DBGU) Receive Counter Register
-#define AT91C_DBGU_RNCR           (0xFFFFF314) // (PDC_DBGU) Receive Next Counter Register
-#define AT91C_DBGU_PTCR           (0xFFFFF320) // (PDC_DBGU) PDC Transfer Control Register
-#define AT91C_DBGU_PTSR           (0xFFFFF324) // (PDC_DBGU) PDC Transfer Status Register
-#define AT91C_DBGU_TNCR           (0xFFFFF31C) // (PDC_DBGU) Transmit Next Counter Register
-// ========== Register definition for DBGU peripheral ========== 
-#define AT91C_DBGU_EXID           (0xFFFFF244) // (DBGU) Chip ID Extension Register
-#define AT91C_DBGU_BRGR           (0xFFFFF220) // (DBGU) Baud Rate Generator Register
-#define AT91C_DBGU_IDR            (0xFFFFF20C) // (DBGU) Interrupt Disable Register
-#define AT91C_DBGU_CSR            (0xFFFFF214) // (DBGU) Channel Status Register
-#define AT91C_DBGU_CIDR           (0xFFFFF240) // (DBGU) Chip ID Register
-#define AT91C_DBGU_MR             (0xFFFFF204) // (DBGU) Mode Register
-#define AT91C_DBGU_IMR            (0xFFFFF210) // (DBGU) Interrupt Mask Register
-#define AT91C_DBGU_CR             (0xFFFFF200) // (DBGU) Control Register
-#define AT91C_DBGU_FNTR           (0xFFFFF248) // (DBGU) Force NTRST Register
-#define AT91C_DBGU_THR            (0xFFFFF21C) // (DBGU) Transmitter Holding Register
-#define AT91C_DBGU_RHR            (0xFFFFF218) // (DBGU) Receiver Holding Register
-#define AT91C_DBGU_IER            (0xFFFFF208) // (DBGU) Interrupt Enable Register
-// ========== Register definition for PIOA peripheral ========== 
-#define AT91C_PIOA_ODR            (0xFFFFF414) // (PIOA) Output Disable Registerr
-#define AT91C_PIOA_SODR           (0xFFFFF430) // (PIOA) Set Output Data Register
-#define AT91C_PIOA_ISR            (0xFFFFF44C) // (PIOA) Interrupt Status Register
-#define AT91C_PIOA_ABSR           (0xFFFFF478) // (PIOA) AB Select Status Register
-#define AT91C_PIOA_IER            (0xFFFFF440) // (PIOA) Interrupt Enable Register
-#define AT91C_PIOA_PPUDR          (0xFFFFF460) // (PIOA) Pull-up Disable Register
-#define AT91C_PIOA_IMR            (0xFFFFF448) // (PIOA) Interrupt Mask Register
-#define AT91C_PIOA_PER            (0xFFFFF400) // (PIOA) PIO Enable Register
-#define AT91C_PIOA_IFDR           (0xFFFFF424) // (PIOA) Input Filter Disable Register
-#define AT91C_PIOA_OWDR           (0xFFFFF4A4) // (PIOA) Output Write Disable Register
-#define AT91C_PIOA_MDSR           (0xFFFFF458) // (PIOA) Multi-driver Status Register
-#define AT91C_PIOA_IDR            (0xFFFFF444) // (PIOA) Interrupt Disable Register
-#define AT91C_PIOA_ODSR           (0xFFFFF438) // (PIOA) Output Data Status Register
-#define AT91C_PIOA_PPUSR          (0xFFFFF468) // (PIOA) Pull-up Status Register
-#define AT91C_PIOA_OWSR           (0xFFFFF4A8) // (PIOA) Output Write Status Register
-#define AT91C_PIOA_BSR            (0xFFFFF474) // (PIOA) Select B Register
-#define AT91C_PIOA_OWER           (0xFFFFF4A0) // (PIOA) Output Write Enable Register
-#define AT91C_PIOA_IFER           (0xFFFFF420) // (PIOA) Input Filter Enable Register
-#define AT91C_PIOA_PDSR           (0xFFFFF43C) // (PIOA) Pin Data Status Register
-#define AT91C_PIOA_PPUER          (0xFFFFF464) // (PIOA) Pull-up Enable Register
-#define AT91C_PIOA_OSR            (0xFFFFF418) // (PIOA) Output Status Register
-#define AT91C_PIOA_ASR            (0xFFFFF470) // (PIOA) Select A Register
-#define AT91C_PIOA_MDDR           (0xFFFFF454) // (PIOA) Multi-driver Disable Register
-#define AT91C_PIOA_CODR           (0xFFFFF434) // (PIOA) Clear Output Data Register
-#define AT91C_PIOA_MDER           (0xFFFFF450) // (PIOA) Multi-driver Enable Register
-#define AT91C_PIOA_PDR            (0xFFFFF404) // (PIOA) PIO Disable Register
-#define AT91C_PIOA_IFSR           (0xFFFFF428) // (PIOA) Input Filter Status Register
-#define AT91C_PIOA_OER            (0xFFFFF410) // (PIOA) Output Enable Register
-#define AT91C_PIOA_PSR            (0xFFFFF408) // (PIOA) PIO Status Register
-// ========== Register definition for PIOB peripheral ========== 
-#define AT91C_PIOB_OWDR           (0xFFFFF6A4) // (PIOB) Output Write Disable Register
-#define AT91C_PIOB_MDER           (0xFFFFF650) // (PIOB) Multi-driver Enable Register
-#define AT91C_PIOB_PPUSR          (0xFFFFF668) // (PIOB) Pull-up Status Register
-#define AT91C_PIOB_IMR            (0xFFFFF648) // (PIOB) Interrupt Mask Register
-#define AT91C_PIOB_ASR            (0xFFFFF670) // (PIOB) Select A Register
-#define AT91C_PIOB_PPUDR          (0xFFFFF660) // (PIOB) Pull-up Disable Register
-#define AT91C_PIOB_PSR            (0xFFFFF608) // (PIOB) PIO Status Register
-#define AT91C_PIOB_IER            (0xFFFFF640) // (PIOB) Interrupt Enable Register
-#define AT91C_PIOB_CODR           (0xFFFFF634) // (PIOB) Clear Output Data Register
-#define AT91C_PIOB_OWER           (0xFFFFF6A0) // (PIOB) Output Write Enable Register
-#define AT91C_PIOB_ABSR           (0xFFFFF678) // (PIOB) AB Select Status Register
-#define AT91C_PIOB_IFDR           (0xFFFFF624) // (PIOB) Input Filter Disable Register
-#define AT91C_PIOB_PDSR           (0xFFFFF63C) // (PIOB) Pin Data Status Register
-#define AT91C_PIOB_IDR            (0xFFFFF644) // (PIOB) Interrupt Disable Register
-#define AT91C_PIOB_OWSR           (0xFFFFF6A8) // (PIOB) Output Write Status Register
-#define AT91C_PIOB_PDR            (0xFFFFF604) // (PIOB) PIO Disable Register
-#define AT91C_PIOB_ODR            (0xFFFFF614) // (PIOB) Output Disable Registerr
-#define AT91C_PIOB_IFSR           (0xFFFFF628) // (PIOB) Input Filter Status Register
-#define AT91C_PIOB_PPUER          (0xFFFFF664) // (PIOB) Pull-up Enable Register
-#define AT91C_PIOB_SODR           (0xFFFFF630) // (PIOB) Set Output Data Register
-#define AT91C_PIOB_ISR            (0xFFFFF64C) // (PIOB) Interrupt Status Register
-#define AT91C_PIOB_ODSR           (0xFFFFF638) // (PIOB) Output Data Status Register
-#define AT91C_PIOB_OSR            (0xFFFFF618) // (PIOB) Output Status Register
-#define AT91C_PIOB_MDSR           (0xFFFFF658) // (PIOB) Multi-driver Status Register
-#define AT91C_PIOB_IFER           (0xFFFFF620) // (PIOB) Input Filter Enable Register
-#define AT91C_PIOB_BSR            (0xFFFFF674) // (PIOB) Select B Register
-#define AT91C_PIOB_MDDR           (0xFFFFF654) // (PIOB) Multi-driver Disable Register
-#define AT91C_PIOB_OER            (0xFFFFF610) // (PIOB) Output Enable Register
-#define AT91C_PIOB_PER            (0xFFFFF600) // (PIOB) PIO Enable Register
-// ========== Register definition for CKGR peripheral ========== 
-#define AT91C_CKGR_MOR            (0xFFFFFC20) // (CKGR) Main Oscillator Register
-#define AT91C_CKGR_PLLR           (0xFFFFFC2C) // (CKGR) PLL Register
-#define AT91C_CKGR_MCFR           (0xFFFFFC24) // (CKGR) Main Clock  Frequency Register
-// ========== Register definition for PMC peripheral ========== 
-#define AT91C_PMC_IDR             (0xFFFFFC64) // (PMC) Interrupt Disable Register
-#define AT91C_PMC_MOR             (0xFFFFFC20) // (PMC) Main Oscillator Register
-#define AT91C_PMC_PLLR            (0xFFFFFC2C) // (PMC) PLL Register
-#define AT91C_PMC_PCER            (0xFFFFFC10) // (PMC) Peripheral Clock Enable Register
-#define AT91C_PMC_PCKR            (0xFFFFFC40) // (PMC) Programmable Clock Register
-#define AT91C_PMC_MCKR            (0xFFFFFC30) // (PMC) Master Clock Register
-#define AT91C_PMC_SCDR            (0xFFFFFC04) // (PMC) System Clock Disable Register
-#define AT91C_PMC_PCDR            (0xFFFFFC14) // (PMC) Peripheral Clock Disable Register
-#define AT91C_PMC_SCSR            (0xFFFFFC08) // (PMC) System Clock Status Register
-#define AT91C_PMC_PCSR            (0xFFFFFC18) // (PMC) Peripheral Clock Status Register
-#define AT91C_PMC_MCFR            (0xFFFFFC24) // (PMC) Main Clock  Frequency Register
-#define AT91C_PMC_SCER            (0xFFFFFC00) // (PMC) System Clock Enable Register
-#define AT91C_PMC_IMR             (0xFFFFFC6C) // (PMC) Interrupt Mask Register
-#define AT91C_PMC_IER             (0xFFFFFC60) // (PMC) Interrupt Enable Register
-#define AT91C_PMC_SR              (0xFFFFFC68) // (PMC) Status Register
-// ========== Register definition for RSTC peripheral ========== 
-#define AT91C_RSTC_RCR            (0xFFFFFD00) // (RSTC) Reset Control Register
-#define AT91C_RSTC_RMR            (0xFFFFFD08) // (RSTC) Reset Mode Register
-#define AT91C_RSTC_RSR            (0xFFFFFD04) // (RSTC) Reset Status Register
-// ========== Register definition for RTTC peripheral ========== 
-#define AT91C_RTTC_RTSR           (0xFFFFFD2C) // (RTTC) Real-time Status Register
-#define AT91C_RTTC_RTMR           (0xFFFFFD20) // (RTTC) Real-time Mode Register
-#define AT91C_RTTC_RTVR           (0xFFFFFD28) // (RTTC) Real-time Value Register
-#define AT91C_RTTC_RTAR           (0xFFFFFD24) // (RTTC) Real-time Alarm Register
-// ========== Register definition for PITC peripheral ========== 
-#define AT91C_PITC_PIVR           (0xFFFFFD38) // (PITC) Period Interval Value Register
-#define AT91C_PITC_PISR           (0xFFFFFD34) // (PITC) Period Interval Status Register
-#define AT91C_PITC_PIIR           (0xFFFFFD3C) // (PITC) Period Interval Image Register
-#define AT91C_PITC_PIMR           (0xFFFFFD30) // (PITC) Period Interval Mode Register
-// ========== Register definition for WDTC peripheral ========== 
-#define AT91C_WDTC_WDCR           (0xFFFFFD40) // (WDTC) Watchdog Control Register
-#define AT91C_WDTC_WDSR           (0xFFFFFD48) // (WDTC) Watchdog Status Register
-#define AT91C_WDTC_WDMR           (0xFFFFFD44) // (WDTC) Watchdog Mode Register
-// ========== Register definition for VREG peripheral ========== 
-#define AT91C_VREG_MR             (0xFFFFFD60) // (VREG) Voltage Regulator Mode Register
-// ========== Register definition for MC peripheral ========== 
-#define AT91C_MC_ASR              (0xFFFFFF04) // (MC) MC Abort Status Register
-#define AT91C_MC_RCR              (0xFFFFFF00) // (MC) MC Remap Control Register
-#define AT91C_MC_FCR              (0xFFFFFF64) // (MC) MC Flash Command Register
-#define AT91C_MC_AASR             (0xFFFFFF08) // (MC) MC Abort Address Status Register
-#define AT91C_MC_FSR              (0xFFFFFF68) // (MC) MC Flash Status Register
-#define AT91C_MC_FMR              (0xFFFFFF60) // (MC) MC Flash Mode Register
-// ========== Register definition for PDC_SPI1 peripheral ========== 
-#define AT91C_SPI1_PTCR           (0xFFFE4120) // (PDC_SPI1) PDC Transfer Control Register
-#define AT91C_SPI1_RPR            (0xFFFE4100) // (PDC_SPI1) Receive Pointer Register
-#define AT91C_SPI1_TNCR           (0xFFFE411C) // (PDC_SPI1) Transmit Next Counter Register
-#define AT91C_SPI1_TPR            (0xFFFE4108) // (PDC_SPI1) Transmit Pointer Register
-#define AT91C_SPI1_TNPR           (0xFFFE4118) // (PDC_SPI1) Transmit Next Pointer Register
-#define AT91C_SPI1_TCR            (0xFFFE410C) // (PDC_SPI1) Transmit Counter Register
-#define AT91C_SPI1_RCR            (0xFFFE4104) // (PDC_SPI1) Receive Counter Register
-#define AT91C_SPI1_RNPR           (0xFFFE4110) // (PDC_SPI1) Receive Next Pointer Register
-#define AT91C_SPI1_RNCR           (0xFFFE4114) // (PDC_SPI1) Receive Next Counter Register
-#define AT91C_SPI1_PTSR           (0xFFFE4124) // (PDC_SPI1) PDC Transfer Status Register
-// ========== Register definition for SPI1 peripheral ========== 
-#define AT91C_SPI1_IMR            (0xFFFE401C) // (SPI1) Interrupt Mask Register
-#define AT91C_SPI1_IER            (0xFFFE4014) // (SPI1) Interrupt Enable Register
-#define AT91C_SPI1_MR             (0xFFFE4004) // (SPI1) Mode Register
-#define AT91C_SPI1_RDR            (0xFFFE4008) // (SPI1) Receive Data Register
-#define AT91C_SPI1_IDR            (0xFFFE4018) // (SPI1) Interrupt Disable Register
-#define AT91C_SPI1_SR             (0xFFFE4010) // (SPI1) Status Register
-#define AT91C_SPI1_TDR            (0xFFFE400C) // (SPI1) Transmit Data Register
-#define AT91C_SPI1_CR             (0xFFFE4000) // (SPI1) Control Register
-#define AT91C_SPI1_CSR            (0xFFFE4030) // (SPI1) Chip Select Register
-// ========== Register definition for PDC_SPI0 peripheral ========== 
-#define AT91C_SPI0_PTCR           (0xFFFE0120) // (PDC_SPI0) PDC Transfer Control Register
-#define AT91C_SPI0_TPR            (0xFFFE0108) // (PDC_SPI0) Transmit Pointer Register
-#define AT91C_SPI0_TCR            (0xFFFE010C) // (PDC_SPI0) Transmit Counter Register
-#define AT91C_SPI0_RCR            (0xFFFE0104) // (PDC_SPI0) Receive Counter Register
-#define AT91C_SPI0_PTSR           (0xFFFE0124) // (PDC_SPI0) PDC Transfer Status Register
-#define AT91C_SPI0_RNPR           (0xFFFE0110) // (PDC_SPI0) Receive Next Pointer Register
-#define AT91C_SPI0_RPR            (0xFFFE0100) // (PDC_SPI0) Receive Pointer Register
-#define AT91C_SPI0_TNCR           (0xFFFE011C) // (PDC_SPI0) Transmit Next Counter Register
-#define AT91C_SPI0_RNCR           (0xFFFE0114) // (PDC_SPI0) Receive Next Counter Register
-#define AT91C_SPI0_TNPR           (0xFFFE0118) // (PDC_SPI0) Transmit Next Pointer Register
-// ========== Register definition for SPI0 peripheral ========== 
-#define AT91C_SPI0_IER            (0xFFFE0014) // (SPI0) Interrupt Enable Register
-#define AT91C_SPI0_SR             (0xFFFE0010) // (SPI0) Status Register
-#define AT91C_SPI0_IDR            (0xFFFE0018) // (SPI0) Interrupt Disable Register
-#define AT91C_SPI0_CR             (0xFFFE0000) // (SPI0) Control Register
-#define AT91C_SPI0_MR             (0xFFFE0004) // (SPI0) Mode Register
-#define AT91C_SPI0_IMR            (0xFFFE001C) // (SPI0) Interrupt Mask Register
-#define AT91C_SPI0_TDR            (0xFFFE000C) // (SPI0) Transmit Data Register
-#define AT91C_SPI0_RDR            (0xFFFE0008) // (SPI0) Receive Data Register
-#define AT91C_SPI0_CSR            (0xFFFE0030) // (SPI0) Chip Select Register
-// ========== Register definition for PDC_US1 peripheral ========== 
-#define AT91C_US1_RNCR            (0xFFFC4114) // (PDC_US1) Receive Next Counter Register
-#define AT91C_US1_PTCR            (0xFFFC4120) // (PDC_US1) PDC Transfer Control Register
-#define AT91C_US1_TCR             (0xFFFC410C) // (PDC_US1) Transmit Counter Register
-#define AT91C_US1_PTSR            (0xFFFC4124) // (PDC_US1) PDC Transfer Status Register
-#define AT91C_US1_TNPR            (0xFFFC4118) // (PDC_US1) Transmit Next Pointer Register
-#define AT91C_US1_RCR             (0xFFFC4104) // (PDC_US1) Receive Counter Register
-#define AT91C_US1_RNPR            (0xFFFC4110) // (PDC_US1) Receive Next Pointer Register
-#define AT91C_US1_RPR             (0xFFFC4100) // (PDC_US1) Receive Pointer Register
-#define AT91C_US1_TNCR            (0xFFFC411C) // (PDC_US1) Transmit Next Counter Register
-#define AT91C_US1_TPR             (0xFFFC4108) // (PDC_US1) Transmit Pointer Register
-// ========== Register definition for US1 peripheral ========== 
-#define AT91C_US1_IF              (0xFFFC404C) // (US1) IRDA_FILTER Register
-#define AT91C_US1_NER             (0xFFFC4044) // (US1) Nb Errors Register
-#define AT91C_US1_RTOR            (0xFFFC4024) // (US1) Receiver Time-out Register
-#define AT91C_US1_CSR             (0xFFFC4014) // (US1) Channel Status Register
-#define AT91C_US1_IDR             (0xFFFC400C) // (US1) Interrupt Disable Register
-#define AT91C_US1_IER             (0xFFFC4008) // (US1) Interrupt Enable Register
-#define AT91C_US1_THR             (0xFFFC401C) // (US1) Transmitter Holding Register
-#define AT91C_US1_TTGR            (0xFFFC4028) // (US1) Transmitter Time-guard Register
-#define AT91C_US1_RHR             (0xFFFC4018) // (US1) Receiver Holding Register
-#define AT91C_US1_BRGR            (0xFFFC4020) // (US1) Baud Rate Generator Register
-#define AT91C_US1_IMR             (0xFFFC4010) // (US1) Interrupt Mask Register
-#define AT91C_US1_FIDI            (0xFFFC4040) // (US1) FI_DI_Ratio Register
-#define AT91C_US1_CR              (0xFFFC4000) // (US1) Control Register
-#define AT91C_US1_MR              (0xFFFC4004) // (US1) Mode Register
-// ========== Register definition for PDC_US0 peripheral ========== 
-#define AT91C_US0_TNPR            (0xFFFC0118) // (PDC_US0) Transmit Next Pointer Register
-#define AT91C_US0_RNPR            (0xFFFC0110) // (PDC_US0) Receive Next Pointer Register
-#define AT91C_US0_TCR             (0xFFFC010C) // (PDC_US0) Transmit Counter Register
-#define AT91C_US0_PTCR            (0xFFFC0120) // (PDC_US0) PDC Transfer Control Register
-#define AT91C_US0_PTSR            (0xFFFC0124) // (PDC_US0) PDC Transfer Status Register
-#define AT91C_US0_TNCR            (0xFFFC011C) // (PDC_US0) Transmit Next Counter Register
-#define AT91C_US0_TPR             (0xFFFC0108) // (PDC_US0) Transmit Pointer Register
-#define AT91C_US0_RCR             (0xFFFC0104) // (PDC_US0) Receive Counter Register
-#define AT91C_US0_RPR             (0xFFFC0100) // (PDC_US0) Receive Pointer Register
-#define AT91C_US0_RNCR            (0xFFFC0114) // (PDC_US0) Receive Next Counter Register
-// ========== Register definition for US0 peripheral ========== 
-#define AT91C_US0_BRGR            (0xFFFC0020) // (US0) Baud Rate Generator Register
-#define AT91C_US0_NER             (0xFFFC0044) // (US0) Nb Errors Register
-#define AT91C_US0_CR              (0xFFFC0000) // (US0) Control Register
-#define AT91C_US0_IMR             (0xFFFC0010) // (US0) Interrupt Mask Register
-#define AT91C_US0_FIDI            (0xFFFC0040) // (US0) FI_DI_Ratio Register
-#define AT91C_US0_TTGR            (0xFFFC0028) // (US0) Transmitter Time-guard Register
-#define AT91C_US0_MR              (0xFFFC0004) // (US0) Mode Register
-#define AT91C_US0_RTOR            (0xFFFC0024) // (US0) Receiver Time-out Register
-#define AT91C_US0_CSR             (0xFFFC0014) // (US0) Channel Status Register
-#define AT91C_US0_RHR             (0xFFFC0018) // (US0) Receiver Holding Register
-#define AT91C_US0_IDR             (0xFFFC000C) // (US0) Interrupt Disable Register
-#define AT91C_US0_THR             (0xFFFC001C) // (US0) Transmitter Holding Register
-#define AT91C_US0_IF              (0xFFFC004C) // (US0) IRDA_FILTER Register
-#define AT91C_US0_IER             (0xFFFC0008) // (US0) Interrupt Enable Register
-// ========== Register definition for PDC_SSC peripheral ========== 
-#define AT91C_SSC_TNCR            (0xFFFD411C) // (PDC_SSC) Transmit Next Counter Register
-#define AT91C_SSC_RPR             (0xFFFD4100) // (PDC_SSC) Receive Pointer Register
-#define AT91C_SSC_RNCR            (0xFFFD4114) // (PDC_SSC) Receive Next Counter Register
-#define AT91C_SSC_TPR             (0xFFFD4108) // (PDC_SSC) Transmit Pointer Register
-#define AT91C_SSC_PTCR            (0xFFFD4120) // (PDC_SSC) PDC Transfer Control Register
-#define AT91C_SSC_TCR             (0xFFFD410C) // (PDC_SSC) Transmit Counter Register
-#define AT91C_SSC_RCR             (0xFFFD4104) // (PDC_SSC) Receive Counter Register
-#define AT91C_SSC_RNPR            (0xFFFD4110) // (PDC_SSC) Receive Next Pointer Register
-#define AT91C_SSC_TNPR            (0xFFFD4118) // (PDC_SSC) Transmit Next Pointer Register
-#define AT91C_SSC_PTSR            (0xFFFD4124) // (PDC_SSC) PDC Transfer Status Register
-// ========== Register definition for SSC peripheral ========== 
-#define AT91C_SSC_RHR             (0xFFFD4020) // (SSC) Receive Holding Register
-#define AT91C_SSC_RSHR            (0xFFFD4030) // (SSC) Receive Sync Holding Register
-#define AT91C_SSC_TFMR            (0xFFFD401C) // (SSC) Transmit Frame Mode Register
-#define AT91C_SSC_IDR             (0xFFFD4048) // (SSC) Interrupt Disable Register
-#define AT91C_SSC_THR             (0xFFFD4024) // (SSC) Transmit Holding Register
-#define AT91C_SSC_RCMR            (0xFFFD4010) // (SSC) Receive Clock ModeRegister
-#define AT91C_SSC_IER             (0xFFFD4044) // (SSC) Interrupt Enable Register
-#define AT91C_SSC_TSHR            (0xFFFD4034) // (SSC) Transmit Sync Holding Register
-#define AT91C_SSC_SR              (0xFFFD4040) // (SSC) Status Register
-#define AT91C_SSC_CMR             (0xFFFD4004) // (SSC) Clock Mode Register
-#define AT91C_SSC_TCMR            (0xFFFD4018) // (SSC) Transmit Clock Mode Register
-#define AT91C_SSC_CR              (0xFFFD4000) // (SSC) Control Register
-#define AT91C_SSC_IMR             (0xFFFD404C) // (SSC) Interrupt Mask Register
-#define AT91C_SSC_RFMR            (0xFFFD4014) // (SSC) Receive Frame Mode Register
-// ========== Register definition for TWI peripheral ========== 
-#define AT91C_TWI_IER             (0xFFFB8024) // (TWI) Interrupt Enable Register
-#define AT91C_TWI_CR              (0xFFFB8000) // (TWI) Control Register
-#define AT91C_TWI_SR              (0xFFFB8020) // (TWI) Status Register
-#define AT91C_TWI_IMR             (0xFFFB802C) // (TWI) Interrupt Mask Register
-#define AT91C_TWI_THR             (0xFFFB8034) // (TWI) Transmit Holding Register
-#define AT91C_TWI_IDR             (0xFFFB8028) // (TWI) Interrupt Disable Register
-#define AT91C_TWI_IADR            (0xFFFB800C) // (TWI) Internal Address Register
-#define AT91C_TWI_MMR             (0xFFFB8004) // (TWI) Master Mode Register
-#define AT91C_TWI_CWGR            (0xFFFB8010) // (TWI) Clock Waveform Generator Register
-#define AT91C_TWI_RHR             (0xFFFB8030) // (TWI) Receive Holding Register
-// ========== Register definition for PWMC_CH3 peripheral ========== 
-#define AT91C_PWMC_CH3_CUPDR      (0xFFFCC270) // (PWMC_CH3) Channel Update Register
-#define AT91C_PWMC_CH3_Reserved   (0xFFFCC274) // (PWMC_CH3) Reserved
-#define AT91C_PWMC_CH3_CPRDR      (0xFFFCC268) // (PWMC_CH3) Channel Period Register
-#define AT91C_PWMC_CH3_CDTYR      (0xFFFCC264) // (PWMC_CH3) Channel Duty Cycle Register
-#define AT91C_PWMC_CH3_CCNTR      (0xFFFCC26C) // (PWMC_CH3) Channel Counter Register
-#define AT91C_PWMC_CH3_CMR        (0xFFFCC260) // (PWMC_CH3) Channel Mode Register
-// ========== Register definition for PWMC_CH2 peripheral ========== 
-#define AT91C_PWMC_CH2_Reserved   (0xFFFCC254) // (PWMC_CH2) Reserved
-#define AT91C_PWMC_CH2_CMR        (0xFFFCC240) // (PWMC_CH2) Channel Mode Register
-#define AT91C_PWMC_CH2_CCNTR      (0xFFFCC24C) // (PWMC_CH2) Channel Counter Register
-#define AT91C_PWMC_CH2_CPRDR      (0xFFFCC248) // (PWMC_CH2) Channel Period Register
-#define AT91C_PWMC_CH2_CUPDR      (0xFFFCC250) // (PWMC_CH2) Channel Update Register
-#define AT91C_PWMC_CH2_CDTYR      (0xFFFCC244) // (PWMC_CH2) Channel Duty Cycle Register
-// ========== Register definition for PWMC_CH1 peripheral ========== 
-#define AT91C_PWMC_CH1_Reserved   (0xFFFCC234) // (PWMC_CH1) Reserved
-#define AT91C_PWMC_CH1_CUPDR      (0xFFFCC230) // (PWMC_CH1) Channel Update Register
-#define AT91C_PWMC_CH1_CPRDR      (0xFFFCC228) // (PWMC_CH1) Channel Period Register
-#define AT91C_PWMC_CH1_CCNTR      (0xFFFCC22C) // (PWMC_CH1) Channel Counter Register
-#define AT91C_PWMC_CH1_CDTYR      (0xFFFCC224) // (PWMC_CH1) Channel Duty Cycle Register
-#define AT91C_PWMC_CH1_CMR        (0xFFFCC220) // (PWMC_CH1) Channel Mode Register
-// ========== Register definition for PWMC_CH0 peripheral ========== 
-#define AT91C_PWMC_CH0_Reserved   (0xFFFCC214) // (PWMC_CH0) Reserved
-#define AT91C_PWMC_CH0_CPRDR      (0xFFFCC208) // (PWMC_CH0) Channel Period Register
-#define AT91C_PWMC_CH0_CDTYR      (0xFFFCC204) // (PWMC_CH0) Channel Duty Cycle Register
-#define AT91C_PWMC_CH0_CMR        (0xFFFCC200) // (PWMC_CH0) Channel Mode Register
-#define AT91C_PWMC_CH0_CUPDR      (0xFFFCC210) // (PWMC_CH0) Channel Update Register
-#define AT91C_PWMC_CH0_CCNTR      (0xFFFCC20C) // (PWMC_CH0) Channel Counter Register
-// ========== Register definition for PWMC peripheral ========== 
-#define AT91C_PWMC_IDR            (0xFFFCC014) // (PWMC) PWMC Interrupt Disable Register
-#define AT91C_PWMC_DIS            (0xFFFCC008) // (PWMC) PWMC Disable Register
-#define AT91C_PWMC_IER            (0xFFFCC010) // (PWMC) PWMC Interrupt Enable Register
-#define AT91C_PWMC_VR             (0xFFFCC0FC) // (PWMC) PWMC Version Register
-#define AT91C_PWMC_ISR            (0xFFFCC01C) // (PWMC) PWMC Interrupt Status Register
-#define AT91C_PWMC_SR             (0xFFFCC00C) // (PWMC) PWMC Status Register
-#define AT91C_PWMC_IMR            (0xFFFCC018) // (PWMC) PWMC Interrupt Mask Register
-#define AT91C_PWMC_MR             (0xFFFCC000) // (PWMC) PWMC Mode Register
-#define AT91C_PWMC_ENA            (0xFFFCC004) // (PWMC) PWMC Enable Register
-// ========== Register definition for UDP peripheral ========== 
-#define AT91C_UDP_IMR             (0xFFFB0018) // (UDP) Interrupt Mask Register
-#define AT91C_UDP_FADDR           (0xFFFB0008) // (UDP) Function Address Register
-#define AT91C_UDP_NUM             (0xFFFB0000) // (UDP) Frame Number Register
-#define AT91C_UDP_FDR             (0xFFFB0050) // (UDP) Endpoint FIFO Data Register
-#define AT91C_UDP_ISR             (0xFFFB001C) // (UDP) Interrupt Status Register
-#define AT91C_UDP_CSR             (0xFFFB0030) // (UDP) Endpoint Control and Status Register
-#define AT91C_UDP_IDR             (0xFFFB0014) // (UDP) Interrupt Disable Register
-#define AT91C_UDP_ICR             (0xFFFB0020) // (UDP) Interrupt Clear Register
-#define AT91C_UDP_RSTEP           (0xFFFB0028) // (UDP) Reset Endpoint Register
-#define AT91C_UDP_TXVC            (0xFFFB0074) // (UDP) Transceiver Control Register
-#define AT91C_UDP_GLBSTATE        (0xFFFB0004) // (UDP) Global State Register
-#define AT91C_UDP_IER             (0xFFFB0010) // (UDP) Interrupt Enable Register
-// ========== Register definition for TC0 peripheral ========== 
-#define AT91C_TC0_SR              (0xFFFA0020) // (TC0) Status Register
-#define AT91C_TC0_RC              (0xFFFA001C) // (TC0) Register C
-#define AT91C_TC0_RB              (0xFFFA0018) // (TC0) Register B
-#define AT91C_TC0_CCR             (0xFFFA0000) // (TC0) Channel Control Register
-#define AT91C_TC0_CMR             (0xFFFA0004) // (TC0) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC0_IER             (0xFFFA0024) // (TC0) Interrupt Enable Register
-#define AT91C_TC0_RA              (0xFFFA0014) // (TC0) Register A
-#define AT91C_TC0_IDR             (0xFFFA0028) // (TC0) Interrupt Disable Register
-#define AT91C_TC0_CV              (0xFFFA0010) // (TC0) Counter Value
-#define AT91C_TC0_IMR             (0xFFFA002C) // (TC0) Interrupt Mask Register
-// ========== Register definition for TC1 peripheral ========== 
-#define AT91C_TC1_RB              (0xFFFA0058) // (TC1) Register B
-#define AT91C_TC1_CCR             (0xFFFA0040) // (TC1) Channel Control Register
-#define AT91C_TC1_IER             (0xFFFA0064) // (TC1) Interrupt Enable Register
-#define AT91C_TC1_IDR             (0xFFFA0068) // (TC1) Interrupt Disable Register
-#define AT91C_TC1_SR              (0xFFFA0060) // (TC1) Status Register
-#define AT91C_TC1_CMR             (0xFFFA0044) // (TC1) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC1_RA              (0xFFFA0054) // (TC1) Register A
-#define AT91C_TC1_RC              (0xFFFA005C) // (TC1) Register C
-#define AT91C_TC1_IMR             (0xFFFA006C) // (TC1) Interrupt Mask Register
-#define AT91C_TC1_CV              (0xFFFA0050) // (TC1) Counter Value
-// ========== Register definition for TC2 peripheral ========== 
-#define AT91C_TC2_CMR             (0xFFFA0084) // (TC2) Channel Mode Register (Capture Mode / Waveform Mode)
-#define AT91C_TC2_CCR             (0xFFFA0080) // (TC2) Channel Control Register
-#define AT91C_TC2_CV              (0xFFFA0090) // (TC2) Counter Value
-#define AT91C_TC2_RA              (0xFFFA0094) // (TC2) Register A
-#define AT91C_TC2_RB              (0xFFFA0098) // (TC2) Register B
-#define AT91C_TC2_IDR             (0xFFFA00A8) // (TC2) Interrupt Disable Register
-#define AT91C_TC2_IMR             (0xFFFA00AC) // (TC2) Interrupt Mask Register
-#define AT91C_TC2_RC              (0xFFFA009C) // (TC2) Register C
-#define AT91C_TC2_IER             (0xFFFA00A4) // (TC2) Interrupt Enable Register
-#define AT91C_TC2_SR              (0xFFFA00A0) // (TC2) Status Register
-// ========== Register definition for TCB peripheral ========== 
-#define AT91C_TCB_BMR             (0xFFFA00C4) // (TCB) TC Block Mode Register
-#define AT91C_TCB_BCR             (0xFFFA00C0) // (TCB) TC Block Control Register
-// ========== Register definition for CAN_MB0 peripheral ========== 
-#define AT91C_CAN_MB0_MDL         (0xFFFD0214) // (CAN_MB0) MailBox Data Low Register
-#define AT91C_CAN_MB0_MAM         (0xFFFD0204) // (CAN_MB0) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB0_MCR         (0xFFFD021C) // (CAN_MB0) MailBox Control Register
-#define AT91C_CAN_MB0_MID         (0xFFFD0208) // (CAN_MB0) MailBox ID Register
-#define AT91C_CAN_MB0_MSR         (0xFFFD0210) // (CAN_MB0) MailBox Status Register
-#define AT91C_CAN_MB0_MFID        (0xFFFD020C) // (CAN_MB0) MailBox Family ID Register
-#define AT91C_CAN_MB0_MDH         (0xFFFD0218) // (CAN_MB0) MailBox Data High Register
-#define AT91C_CAN_MB0_MMR         (0xFFFD0200) // (CAN_MB0) MailBox Mode Register
-// ========== Register definition for CAN_MB1 peripheral ========== 
-#define AT91C_CAN_MB1_MDL         (0xFFFD0234) // (CAN_MB1) MailBox Data Low Register
-#define AT91C_CAN_MB1_MID         (0xFFFD0228) // (CAN_MB1) MailBox ID Register
-#define AT91C_CAN_MB1_MMR         (0xFFFD0220) // (CAN_MB1) MailBox Mode Register
-#define AT91C_CAN_MB1_MSR         (0xFFFD0230) // (CAN_MB1) MailBox Status Register
-#define AT91C_CAN_MB1_MAM         (0xFFFD0224) // (CAN_MB1) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB1_MDH         (0xFFFD0238) // (CAN_MB1) MailBox Data High Register
-#define AT91C_CAN_MB1_MCR         (0xFFFD023C) // (CAN_MB1) MailBox Control Register
-#define AT91C_CAN_MB1_MFID        (0xFFFD022C) // (CAN_MB1) MailBox Family ID Register
-// ========== Register definition for CAN_MB2 peripheral ========== 
-#define AT91C_CAN_MB2_MCR         (0xFFFD025C) // (CAN_MB2) MailBox Control Register
-#define AT91C_CAN_MB2_MDH         (0xFFFD0258) // (CAN_MB2) MailBox Data High Register
-#define AT91C_CAN_MB2_MID         (0xFFFD0248) // (CAN_MB2) MailBox ID Register
-#define AT91C_CAN_MB2_MDL         (0xFFFD0254) // (CAN_MB2) MailBox Data Low Register
-#define AT91C_CAN_MB2_MMR         (0xFFFD0240) // (CAN_MB2) MailBox Mode Register
-#define AT91C_CAN_MB2_MAM         (0xFFFD0244) // (CAN_MB2) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB2_MFID        (0xFFFD024C) // (CAN_MB2) MailBox Family ID Register
-#define AT91C_CAN_MB2_MSR         (0xFFFD0250) // (CAN_MB2) MailBox Status Register
-// ========== Register definition for CAN_MB3 peripheral ========== 
-#define AT91C_CAN_MB3_MFID        (0xFFFD026C) // (CAN_MB3) MailBox Family ID Register
-#define AT91C_CAN_MB3_MAM         (0xFFFD0264) // (CAN_MB3) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB3_MID         (0xFFFD0268) // (CAN_MB3) MailBox ID Register
-#define AT91C_CAN_MB3_MCR         (0xFFFD027C) // (CAN_MB3) MailBox Control Register
-#define AT91C_CAN_MB3_MMR         (0xFFFD0260) // (CAN_MB3) MailBox Mode Register
-#define AT91C_CAN_MB3_MSR         (0xFFFD0270) // (CAN_MB3) MailBox Status Register
-#define AT91C_CAN_MB3_MDL         (0xFFFD0274) // (CAN_MB3) MailBox Data Low Register
-#define AT91C_CAN_MB3_MDH         (0xFFFD0278) // (CAN_MB3) MailBox Data High Register
-// ========== Register definition for CAN_MB4 peripheral ========== 
-#define AT91C_CAN_MB4_MID         (0xFFFD0288) // (CAN_MB4) MailBox ID Register
-#define AT91C_CAN_MB4_MMR         (0xFFFD0280) // (CAN_MB4) MailBox Mode Register
-#define AT91C_CAN_MB4_MDH         (0xFFFD0298) // (CAN_MB4) MailBox Data High Register
-#define AT91C_CAN_MB4_MFID        (0xFFFD028C) // (CAN_MB4) MailBox Family ID Register
-#define AT91C_CAN_MB4_MSR         (0xFFFD0290) // (CAN_MB4) MailBox Status Register
-#define AT91C_CAN_MB4_MCR         (0xFFFD029C) // (CAN_MB4) MailBox Control Register
-#define AT91C_CAN_MB4_MDL         (0xFFFD0294) // (CAN_MB4) MailBox Data Low Register
-#define AT91C_CAN_MB4_MAM         (0xFFFD0284) // (CAN_MB4) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB5 peripheral ========== 
-#define AT91C_CAN_MB5_MSR         (0xFFFD02B0) // (CAN_MB5) MailBox Status Register
-#define AT91C_CAN_MB5_MCR         (0xFFFD02BC) // (CAN_MB5) MailBox Control Register
-#define AT91C_CAN_MB5_MFID        (0xFFFD02AC) // (CAN_MB5) MailBox Family ID Register
-#define AT91C_CAN_MB5_MDH         (0xFFFD02B8) // (CAN_MB5) MailBox Data High Register
-#define AT91C_CAN_MB5_MID         (0xFFFD02A8) // (CAN_MB5) MailBox ID Register
-#define AT91C_CAN_MB5_MMR         (0xFFFD02A0) // (CAN_MB5) MailBox Mode Register
-#define AT91C_CAN_MB5_MDL         (0xFFFD02B4) // (CAN_MB5) MailBox Data Low Register
-#define AT91C_CAN_MB5_MAM         (0xFFFD02A4) // (CAN_MB5) MailBox Acceptance Mask Register
-// ========== Register definition for CAN_MB6 peripheral ========== 
-#define AT91C_CAN_MB6_MFID        (0xFFFD02CC) // (CAN_MB6) MailBox Family ID Register
-#define AT91C_CAN_MB6_MID         (0xFFFD02C8) // (CAN_MB6) MailBox ID Register
-#define AT91C_CAN_MB6_MAM         (0xFFFD02C4) // (CAN_MB6) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB6_MSR         (0xFFFD02D0) // (CAN_MB6) MailBox Status Register
-#define AT91C_CAN_MB6_MDL         (0xFFFD02D4) // (CAN_MB6) MailBox Data Low Register
-#define AT91C_CAN_MB6_MCR         (0xFFFD02DC) // (CAN_MB6) MailBox Control Register
-#define AT91C_CAN_MB6_MDH         (0xFFFD02D8) // (CAN_MB6) MailBox Data High Register
-#define AT91C_CAN_MB6_MMR         (0xFFFD02C0) // (CAN_MB6) MailBox Mode Register
-// ========== Register definition for CAN_MB7 peripheral ========== 
-#define AT91C_CAN_MB7_MCR         (0xFFFD02FC) // (CAN_MB7) MailBox Control Register
-#define AT91C_CAN_MB7_MDH         (0xFFFD02F8) // (CAN_MB7) MailBox Data High Register
-#define AT91C_CAN_MB7_MFID        (0xFFFD02EC) // (CAN_MB7) MailBox Family ID Register
-#define AT91C_CAN_MB7_MDL         (0xFFFD02F4) // (CAN_MB7) MailBox Data Low Register
-#define AT91C_CAN_MB7_MID         (0xFFFD02E8) // (CAN_MB7) MailBox ID Register
-#define AT91C_CAN_MB7_MMR         (0xFFFD02E0) // (CAN_MB7) MailBox Mode Register
-#define AT91C_CAN_MB7_MAM         (0xFFFD02E4) // (CAN_MB7) MailBox Acceptance Mask Register
-#define AT91C_CAN_MB7_MSR         (0xFFFD02F0) // (CAN_MB7) MailBox Status Register
-// ========== Register definition for CAN peripheral ========== 
-#define AT91C_CAN_TCR             (0xFFFD0024) // (CAN) Transfer Command Register
-#define AT91C_CAN_IMR             (0xFFFD000C) // (CAN) Interrupt Mask Register
-#define AT91C_CAN_IER             (0xFFFD0004) // (CAN) Interrupt Enable Register
-#define AT91C_CAN_ECR             (0xFFFD0020) // (CAN) Error Counter Register
-#define AT91C_CAN_TIMESTP         (0xFFFD001C) // (CAN) Time Stamp Register
-#define AT91C_CAN_MR              (0xFFFD0000) // (CAN) Mode Register
-#define AT91C_CAN_IDR             (0xFFFD0008) // (CAN) Interrupt Disable Register
-#define AT91C_CAN_ACR             (0xFFFD0028) // (CAN) Abort Command Register
-#define AT91C_CAN_TIM             (0xFFFD0018) // (CAN) Timer Register
-#define AT91C_CAN_SR              (0xFFFD0010) // (CAN) Status Register
-#define AT91C_CAN_BR              (0xFFFD0014) // (CAN) Baudrate Register
-#define AT91C_CAN_VR              (0xFFFD00FC) // (CAN) Version Register
-// ========== Register definition for EMAC peripheral ========== 
-#define AT91C_EMAC_ISR            (0xFFFDC024) // (EMAC) Interrupt Status Register
-#define AT91C_EMAC_SA4H           (0xFFFDC0B4) // (EMAC) Specific Address 4 Top, Last 2 bytes
-#define AT91C_EMAC_SA1L           (0xFFFDC098) // (EMAC) Specific Address 1 Bottom, First 4 bytes
-#define AT91C_EMAC_ELE            (0xFFFDC078) // (EMAC) Excessive Length Errors Register
-#define AT91C_EMAC_LCOL           (0xFFFDC05C) // (EMAC) Late Collision Register
-#define AT91C_EMAC_RLE            (0xFFFDC088) // (EMAC) Receive Length Field Mismatch Register
-#define AT91C_EMAC_WOL            (0xFFFDC0C4) // (EMAC) Wake On LAN Register
-#define AT91C_EMAC_DTF            (0xFFFDC058) // (EMAC) Deferred Transmission Frame Register
-#define AT91C_EMAC_TUND           (0xFFFDC064) // (EMAC) Transmit Underrun Error Register
-#define AT91C_EMAC_NCR            (0xFFFDC000) // (EMAC) Network Control Register
-#define AT91C_EMAC_SA4L           (0xFFFDC0B0) // (EMAC) Specific Address 4 Bottom, First 4 bytes
-#define AT91C_EMAC_RSR            (0xFFFDC020) // (EMAC) Receive Status Register
-#define AT91C_EMAC_SA3L           (0xFFFDC0A8) // (EMAC) Specific Address 3 Bottom, First 4 bytes
-#define AT91C_EMAC_TSR            (0xFFFDC014) // (EMAC) Transmit Status Register
-#define AT91C_EMAC_IDR            (0xFFFDC02C) // (EMAC) Interrupt Disable Register
-#define AT91C_EMAC_RSE            (0xFFFDC074) // (EMAC) Receive Symbol Errors Register
-#define AT91C_EMAC_ECOL           (0xFFFDC060) // (EMAC) Excessive Collision Register
-#define AT91C_EMAC_TID            (0xFFFDC0B8) // (EMAC) Type ID Checking Register
-#define AT91C_EMAC_HRB            (0xFFFDC090) // (EMAC) Hash Address Bottom[31:0]
-#define AT91C_EMAC_TBQP           (0xFFFDC01C) // (EMAC) Transmit Buffer Queue Pointer
-#define AT91C_EMAC_USRIO          (0xFFFDC0C0) // (EMAC) USER Input/Output Register
-#define AT91C_EMAC_PTR            (0xFFFDC038) // (EMAC) Pause Time Register
-#define AT91C_EMAC_SA2H           (0xFFFDC0A4) // (EMAC) Specific Address 2 Top, Last 2 bytes
-#define AT91C_EMAC_ROV            (0xFFFDC070) // (EMAC) Receive Overrun Errors Register
-#define AT91C_EMAC_ALE            (0xFFFDC054) // (EMAC) Alignment Error Register
-#define AT91C_EMAC_RJA            (0xFFFDC07C) // (EMAC) Receive Jabbers Register
-#define AT91C_EMAC_RBQP           (0xFFFDC018) // (EMAC) Receive Buffer Queue Pointer
-#define AT91C_EMAC_TPF            (0xFFFDC08C) // (EMAC) Transmitted Pause Frames Register
-#define AT91C_EMAC_NCFGR          (0xFFFDC004) // (EMAC) Network Configuration Register
-#define AT91C_EMAC_HRT            (0xFFFDC094) // (EMAC) Hash Address Top[63:32]
-#define AT91C_EMAC_USF            (0xFFFDC080) // (EMAC) Undersize Frames Register
-#define AT91C_EMAC_FCSE           (0xFFFDC050) // (EMAC) Frame Check Sequence Error Register
-#define AT91C_EMAC_TPQ            (0xFFFDC0BC) // (EMAC) Transmit Pause Quantum Register
-#define AT91C_EMAC_MAN            (0xFFFDC034) // (EMAC) PHY Maintenance Register
-#define AT91C_EMAC_FTO            (0xFFFDC040) // (EMAC) Frames Transmitted OK Register
-#define AT91C_EMAC_REV            (0xFFFDC0FC) // (EMAC) Revision Register
-#define AT91C_EMAC_IMR            (0xFFFDC030) // (EMAC) Interrupt Mask Register
-#define AT91C_EMAC_SCF            (0xFFFDC044) // (EMAC) Single Collision Frame Register
-#define AT91C_EMAC_PFR            (0xFFFDC03C) // (EMAC) Pause Frames received Register
-#define AT91C_EMAC_MCF            (0xFFFDC048) // (EMAC) Multiple Collision Frame Register
-#define AT91C_EMAC_NSR            (0xFFFDC008) // (EMAC) Network Status Register
-#define AT91C_EMAC_SA2L           (0xFFFDC0A0) // (EMAC) Specific Address 2 Bottom, First 4 bytes
-#define AT91C_EMAC_FRO            (0xFFFDC04C) // (EMAC) Frames Received OK Register
-#define AT91C_EMAC_IER            (0xFFFDC028) // (EMAC) Interrupt Enable Register
-#define AT91C_EMAC_SA1H           (0xFFFDC09C) // (EMAC) Specific Address 1 Top, Last 2 bytes
-#define AT91C_EMAC_CSE            (0xFFFDC068) // (EMAC) Carrier Sense Error Register
-#define AT91C_EMAC_SA3H           (0xFFFDC0AC) // (EMAC) Specific Address 3 Top, Last 2 bytes
-#define AT91C_EMAC_RRE            (0xFFFDC06C) // (EMAC) Receive Ressource Error Register
-#define AT91C_EMAC_STE            (0xFFFDC084) // (EMAC) SQE Test Error Register
-// ========== Register definition for PDC_ADC peripheral ========== 
-#define AT91C_ADC_PTSR            (0xFFFD8124) // (PDC_ADC) PDC Transfer Status Register
-#define AT91C_ADC_PTCR            (0xFFFD8120) // (PDC_ADC) PDC Transfer Control Register
-#define AT91C_ADC_TNPR            (0xFFFD8118) // (PDC_ADC) Transmit Next Pointer Register
-#define AT91C_ADC_TNCR            (0xFFFD811C) // (PDC_ADC) Transmit Next Counter Register
-#define AT91C_ADC_RNPR            (0xFFFD8110) // (PDC_ADC) Receive Next Pointer Register
-#define AT91C_ADC_RNCR            (0xFFFD8114) // (PDC_ADC) Receive Next Counter Register
-#define AT91C_ADC_RPR             (0xFFFD8100) // (PDC_ADC) Receive Pointer Register
-#define AT91C_ADC_TCR             (0xFFFD810C) // (PDC_ADC) Transmit Counter Register
-#define AT91C_ADC_TPR             (0xFFFD8108) // (PDC_ADC) Transmit Pointer Register
-#define AT91C_ADC_RCR             (0xFFFD8104) // (PDC_ADC) Receive Counter Register
-// ========== Register definition for ADC peripheral ========== 
-#define AT91C_ADC_CDR2            (0xFFFD8038) // (ADC) ADC Channel Data Register 2
-#define AT91C_ADC_CDR3            (0xFFFD803C) // (ADC) ADC Channel Data Register 3
-#define AT91C_ADC_CDR0            (0xFFFD8030) // (ADC) ADC Channel Data Register 0
-#define AT91C_ADC_CDR5            (0xFFFD8044) // (ADC) ADC Channel Data Register 5
-#define AT91C_ADC_CHDR            (0xFFFD8014) // (ADC) ADC Channel Disable Register
-#define AT91C_ADC_SR              (0xFFFD801C) // (ADC) ADC Status Register
-#define AT91C_ADC_CDR4            (0xFFFD8040) // (ADC) ADC Channel Data Register 4
-#define AT91C_ADC_CDR1            (0xFFFD8034) // (ADC) ADC Channel Data Register 1
-#define AT91C_ADC_LCDR            (0xFFFD8020) // (ADC) ADC Last Converted Data Register
-#define AT91C_ADC_IDR             (0xFFFD8028) // (ADC) ADC Interrupt Disable Register
-#define AT91C_ADC_CR              (0xFFFD8000) // (ADC) ADC Control Register
-#define AT91C_ADC_CDR7            (0xFFFD804C) // (ADC) ADC Channel Data Register 7
-#define AT91C_ADC_CDR6            (0xFFFD8048) // (ADC) ADC Channel Data Register 6
-#define AT91C_ADC_IER             (0xFFFD8024) // (ADC) ADC Interrupt Enable Register
-#define AT91C_ADC_CHER            (0xFFFD8010) // (ADC) ADC Channel Enable Register
-#define AT91C_ADC_CHSR            (0xFFFD8018) // (ADC) ADC Channel Status Register
-#define AT91C_ADC_MR              (0xFFFD8004) // (ADC) ADC Mode Register
-#define AT91C_ADC_IMR             (0xFFFD802C) // (ADC) ADC Interrupt Mask Register
-// ========== Register definition for PDC_AES peripheral ========== 
-#define AT91C_AES_TPR             (0xFFFA4108) // (PDC_AES) Transmit Pointer Register
-#define AT91C_AES_PTCR            (0xFFFA4120) // (PDC_AES) PDC Transfer Control Register
-#define AT91C_AES_RNPR            (0xFFFA4110) // (PDC_AES) Receive Next Pointer Register
-#define AT91C_AES_TNCR            (0xFFFA411C) // (PDC_AES) Transmit Next Counter Register
-#define AT91C_AES_TCR             (0xFFFA410C) // (PDC_AES) Transmit Counter Register
-#define AT91C_AES_RCR             (0xFFFA4104) // (PDC_AES) Receive Counter Register
-#define AT91C_AES_RNCR            (0xFFFA4114) // (PDC_AES) Receive Next Counter Register
-#define AT91C_AES_TNPR            (0xFFFA4118) // (PDC_AES) Transmit Next Pointer Register
-#define AT91C_AES_RPR             (0xFFFA4100) // (PDC_AES) Receive Pointer Register
-#define AT91C_AES_PTSR            (0xFFFA4124) // (PDC_AES) PDC Transfer Status Register
-// ========== Register definition for AES peripheral ========== 
-#define AT91C_AES_IVxR            (0xFFFA4060) // (AES) Initialization Vector x Register
-#define AT91C_AES_MR              (0xFFFA4004) // (AES) Mode Register
-#define AT91C_AES_VR              (0xFFFA40FC) // (AES) AES Version Register
-#define AT91C_AES_ODATAxR         (0xFFFA4050) // (AES) Output Data x Register
-#define AT91C_AES_IDATAxR         (0xFFFA4040) // (AES) Input Data x Register
-#define AT91C_AES_CR              (0xFFFA4000) // (AES) Control Register
-#define AT91C_AES_IDR             (0xFFFA4014) // (AES) Interrupt Disable Register
-#define AT91C_AES_IMR             (0xFFFA4018) // (AES) Interrupt Mask Register
-#define AT91C_AES_IER             (0xFFFA4010) // (AES) Interrupt Enable Register
-#define AT91C_AES_KEYWxR          (0xFFFA4020) // (AES) Key Word x Register
-#define AT91C_AES_ISR             (0xFFFA401C) // (AES) Interrupt Status Register
-// ========== Register definition for PDC_TDES peripheral ========== 
-#define AT91C_TDES_RNCR           (0xFFFA8114) // (PDC_TDES) Receive Next Counter Register
-#define AT91C_TDES_TCR            (0xFFFA810C) // (PDC_TDES) Transmit Counter Register
-#define AT91C_TDES_RCR            (0xFFFA8104) // (PDC_TDES) Receive Counter Register
-#define AT91C_TDES_TNPR           (0xFFFA8118) // (PDC_TDES) Transmit Next Pointer Register
-#define AT91C_TDES_RNPR           (0xFFFA8110) // (PDC_TDES) Receive Next Pointer Register
-#define AT91C_TDES_RPR            (0xFFFA8100) // (PDC_TDES) Receive Pointer Register
-#define AT91C_TDES_TNCR           (0xFFFA811C) // (PDC_TDES) Transmit Next Counter Register
-#define AT91C_TDES_TPR            (0xFFFA8108) // (PDC_TDES) Transmit Pointer Register
-#define AT91C_TDES_PTSR           (0xFFFA8124) // (PDC_TDES) PDC Transfer Status Register
-#define AT91C_TDES_PTCR           (0xFFFA8120) // (PDC_TDES) PDC Transfer Control Register
-// ========== Register definition for TDES peripheral ========== 
-#define AT91C_TDES_KEY2WxR        (0xFFFA8028) // (TDES) Key 2 Word x Register
-#define AT91C_TDES_KEY3WxR        (0xFFFA8030) // (TDES) Key 3 Word x Register
-#define AT91C_TDES_IDR            (0xFFFA8014) // (TDES) Interrupt Disable Register
-#define AT91C_TDES_VR             (0xFFFA80FC) // (TDES) TDES Version Register
-#define AT91C_TDES_IVxR           (0xFFFA8060) // (TDES) Initialization Vector x Register
-#define AT91C_TDES_ODATAxR        (0xFFFA8050) // (TDES) Output Data x Register
-#define AT91C_TDES_IMR            (0xFFFA8018) // (TDES) Interrupt Mask Register
-#define AT91C_TDES_MR             (0xFFFA8004) // (TDES) Mode Register
-#define AT91C_TDES_CR             (0xFFFA8000) // (TDES) Control Register
-#define AT91C_TDES_IER            (0xFFFA8010) // (TDES) Interrupt Enable Register
-#define AT91C_TDES_ISR            (0xFFFA801C) // (TDES) Interrupt Status Register
-#define AT91C_TDES_IDATAxR        (0xFFFA8040) // (TDES) Input Data x Register
-#define AT91C_TDES_KEY1WxR        (0xFFFA8020) // (TDES) Key 1 Word x Register
-
-// *****************************************************************************
-//               PIO DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_PIO_PA0             (1 <<  0) // Pin Controlled by PA0
-#define AT91C_PA0_RXD0            (AT91C_PIO_PA0) //  USART 0 Receive Data
-#define AT91C_PIO_PA1             (1 <<  1) // Pin Controlled by PA1
-#define AT91C_PA1_TXD0            (AT91C_PIO_PA1) //  USART 0 Transmit Data
-#define AT91C_PIO_PA10            (1 << 10) // Pin Controlled by PA10
-#define AT91C_PA10_TWD            (AT91C_PIO_PA10) //  TWI Two-wire Serial Data
-#define AT91C_PIO_PA11            (1 << 11) // Pin Controlled by PA11
-#define AT91C_PA11_TWCK           (AT91C_PIO_PA11) //  TWI Two-wire Serial Clock
-#define AT91C_PIO_PA12            (1 << 12) // Pin Controlled by PA12
-#define AT91C_PA12_NPCS00         (AT91C_PIO_PA12) //  SPI 0 Peripheral Chip Select 0
-#define AT91C_PIO_PA13            (1 << 13) // Pin Controlled by PA13
-#define AT91C_PA13_NPCS01         (AT91C_PIO_PA13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PA13_PCK1           (AT91C_PIO_PA13) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PA14            (1 << 14) // Pin Controlled by PA14
-#define AT91C_PA14_NPCS02         (AT91C_PIO_PA14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PA14_IRQ1           (AT91C_PIO_PA14) //  External Interrupt 1
-#define AT91C_PIO_PA15            (1 << 15) // Pin Controlled by PA15
-#define AT91C_PA15_NPCS03         (AT91C_PIO_PA15) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PA15_TCLK2          (AT91C_PIO_PA15) //  Timer Counter 2 external clock input
-#define AT91C_PIO_PA16            (1 << 16) // Pin Controlled by PA16
-#define AT91C_PA16_MISO0          (AT91C_PIO_PA16) //  SPI 0 Master In Slave
-#define AT91C_PIO_PA17            (1 << 17) // Pin Controlled by PA17
-#define AT91C_PA17_MOSI0          (AT91C_PIO_PA17) //  SPI 0 Master Out Slave
-#define AT91C_PIO_PA18            (1 << 18) // Pin Controlled by PA18
-#define AT91C_PA18_SPCK0          (AT91C_PIO_PA18) //  SPI 0 Serial Clock
-#define AT91C_PIO_PA19            (1 << 19) // Pin Controlled by PA19
-#define AT91C_PA19_CANRX          (AT91C_PIO_PA19) //  CAN Receive
-#define AT91C_PIO_PA2             (1 <<  2) // Pin Controlled by PA2
-#define AT91C_PA2_SCK0            (AT91C_PIO_PA2) //  USART 0 Serial Clock
-#define AT91C_PA2_NPCS11          (AT91C_PIO_PA2) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA20            (1 << 20) // Pin Controlled by PA20
-#define AT91C_PA20_CANTX          (AT91C_PIO_PA20) //  CAN Transmit
-#define AT91C_PIO_PA21            (1 << 21) // Pin Controlled by PA21
-#define AT91C_PA21_TF             (AT91C_PIO_PA21) //  SSC Transmit Frame Sync
-#define AT91C_PA21_NPCS10         (AT91C_PIO_PA21) //  SPI 1 Peripheral Chip Select 0
-#define AT91C_PIO_PA22            (1 << 22) // Pin Controlled by PA22
-#define AT91C_PA22_TK             (AT91C_PIO_PA22) //  SSC Transmit Clock
-#define AT91C_PA22_SPCK1          (AT91C_PIO_PA22) //  SPI 1 Serial Clock
-#define AT91C_PIO_PA23            (1 << 23) // Pin Controlled by PA23
-#define AT91C_PA23_TD             (AT91C_PIO_PA23) //  SSC Transmit data
-#define AT91C_PA23_MOSI1          (AT91C_PIO_PA23) //  SPI 1 Master Out Slave
-#define AT91C_PIO_PA24            (1 << 24) // Pin Controlled by PA24
-#define AT91C_PA24_RD             (AT91C_PIO_PA24) //  SSC Receive Data
-#define AT91C_PA24_MISO1          (AT91C_PIO_PA24) //  SPI 1 Master In Slave
-#define AT91C_PIO_PA25            (1 << 25) // Pin Controlled by PA25
-#define AT91C_PA25_RK             (AT91C_PIO_PA25) //  SSC Receive Clock
-#define AT91C_PA25_NPCS11         (AT91C_PIO_PA25) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PA26            (1 << 26) // Pin Controlled by PA26
-#define AT91C_PA26_RF             (AT91C_PIO_PA26) //  SSC Receive Frame Sync
-#define AT91C_PA26_NPCS12         (AT91C_PIO_PA26) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA27            (1 << 27) // Pin Controlled by PA27
-#define AT91C_PA27_DRXD           (AT91C_PIO_PA27) //  DBGU Debug Receive Data
-#define AT91C_PA27_PCK3           (AT91C_PIO_PA27) //  PMC Programmable Clock Output 3
-#define AT91C_PIO_PA28            (1 << 28) // Pin Controlled by PA28
-#define AT91C_PA28_DTXD           (AT91C_PIO_PA28) //  DBGU Debug Transmit Data
-#define AT91C_PIO_PA29            (1 << 29) // Pin Controlled by PA29
-#define AT91C_PA29_FIQ            (AT91C_PIO_PA29) //  AIC Fast Interrupt Input
-#define AT91C_PA29_NPCS13         (AT91C_PIO_PA29) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA3             (1 <<  3) // Pin Controlled by PA3
-#define AT91C_PA3_RTS0            (AT91C_PIO_PA3) //  USART 0 Ready To Send
-#define AT91C_PA3_NPCS12          (AT91C_PIO_PA3) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PA30            (1 << 30) // Pin Controlled by PA30
-#define AT91C_PA30_IRQ0           (AT91C_PIO_PA30) //  External Interrupt 0
-#define AT91C_PA30_PCK2           (AT91C_PIO_PA30) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PA4             (1 <<  4) // Pin Controlled by PA4
-#define AT91C_PA4_CTS0            (AT91C_PIO_PA4) //  USART 0 Clear To Send
-#define AT91C_PA4_NPCS13          (AT91C_PIO_PA4) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PA5             (1 <<  5) // Pin Controlled by PA5
-#define AT91C_PA5_RXD1            (AT91C_PIO_PA5) //  USART 1 Receive Data
-#define AT91C_PIO_PA6             (1 <<  6) // Pin Controlled by PA6
-#define AT91C_PA6_TXD1            (AT91C_PIO_PA6) //  USART 1 Transmit Data
-#define AT91C_PIO_PA7             (1 <<  7) // Pin Controlled by PA7
-#define AT91C_PA7_SCK1            (AT91C_PIO_PA7) //  USART 1 Serial Clock
-#define AT91C_PA7_NPCS01          (AT91C_PIO_PA7) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PA8             (1 <<  8) // Pin Controlled by PA8
-#define AT91C_PA8_RTS1            (AT91C_PIO_PA8) //  USART 1 Ready To Send
-#define AT91C_PA8_NPCS02          (AT91C_PIO_PA8) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PA9             (1 <<  9) // Pin Controlled by PA9
-#define AT91C_PA9_CTS1            (AT91C_PIO_PA9) //  USART 1 Clear To Send
-#define AT91C_PA9_NPCS03          (AT91C_PIO_PA9) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB0             (1 <<  0) // Pin Controlled by PB0
-#define AT91C_PB0_ETXCK_EREFCK    (AT91C_PIO_PB0) //  Ethernet MAC Transmit Clock/Reference Clock
-#define AT91C_PB0_PCK0            (AT91C_PIO_PB0) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB1             (1 <<  1) // Pin Controlled by PB1
-#define AT91C_PB1_ETXEN           (AT91C_PIO_PB1) //  Ethernet MAC Transmit Enable
-#define AT91C_PIO_PB10            (1 << 10) // Pin Controlled by PB10
-#define AT91C_PB10_ETX2           (AT91C_PIO_PB10) //  Ethernet MAC Transmit Data 2
-#define AT91C_PB10_NPCS11         (AT91C_PIO_PB10) //  SPI 1 Peripheral Chip Select 1
-#define AT91C_PIO_PB11            (1 << 11) // Pin Controlled by PB11
-#define AT91C_PB11_ETX3           (AT91C_PIO_PB11) //  Ethernet MAC Transmit Data 3
-#define AT91C_PB11_NPCS12         (AT91C_PIO_PB11) //  SPI 1 Peripheral Chip Select 2
-#define AT91C_PIO_PB12            (1 << 12) // Pin Controlled by PB12
-#define AT91C_PB12_ETXER          (AT91C_PIO_PB12) //  Ethernet MAC Transmikt Coding Error
-#define AT91C_PB12_TCLK0          (AT91C_PIO_PB12) //  Timer Counter 0 external clock input
-#define AT91C_PIO_PB13            (1 << 13) // Pin Controlled by PB13
-#define AT91C_PB13_ERX2           (AT91C_PIO_PB13) //  Ethernet MAC Receive Data 2
-#define AT91C_PB13_NPCS01         (AT91C_PIO_PB13) //  SPI 0 Peripheral Chip Select 1
-#define AT91C_PIO_PB14            (1 << 14) // Pin Controlled by PB14
-#define AT91C_PB14_ERX3           (AT91C_PIO_PB14) //  Ethernet MAC Receive Data 3
-#define AT91C_PB14_NPCS02         (AT91C_PIO_PB14) //  SPI 0 Peripheral Chip Select 2
-#define AT91C_PIO_PB15            (1 << 15) // Pin Controlled by PB15
-#define AT91C_PB15_ERXDV          (AT91C_PIO_PB15) //  Ethernet MAC Receive Data Valid
-#define AT91C_PIO_PB16            (1 << 16) // Pin Controlled by PB16
-#define AT91C_PB16_ECOL           (AT91C_PIO_PB16) //  Ethernet MAC Collision Detected
-#define AT91C_PB16_NPCS13         (AT91C_PIO_PB16) //  SPI 1 Peripheral Chip Select 3
-#define AT91C_PIO_PB17            (1 << 17) // Pin Controlled by PB17
-#define AT91C_PB17_ERXCK          (AT91C_PIO_PB17) //  Ethernet MAC Receive Clock
-#define AT91C_PB17_NPCS03         (AT91C_PIO_PB17) //  SPI 0 Peripheral Chip Select 3
-#define AT91C_PIO_PB18            (1 << 18) // Pin Controlled by PB18
-#define AT91C_PB18_EF100          (AT91C_PIO_PB18) //  Ethernet MAC Force 100 Mbits/sec
-#define AT91C_PB18_ADTRG          (AT91C_PIO_PB18) //  ADC External Trigger
-#define AT91C_PIO_PB19            (1 << 19) // Pin Controlled by PB19
-#define AT91C_PB19_PWM0           (AT91C_PIO_PB19) //  PWM Channel 0
-#define AT91C_PB19_TCLK1          (AT91C_PIO_PB19) //  Timer Counter 1 external clock input
-#define AT91C_PIO_PB2             (1 <<  2) // Pin Controlled by PB2
-#define AT91C_PB2_ETX0            (AT91C_PIO_PB2) //  Ethernet MAC Transmit Data 0
-#define AT91C_PIO_PB20            (1 << 20) // Pin Controlled by PB20
-#define AT91C_PB20_PWM1           (AT91C_PIO_PB20) //  PWM Channel 1
-#define AT91C_PB20_PCK0           (AT91C_PIO_PB20) //  PMC Programmable Clock Output 0
-#define AT91C_PIO_PB21            (1 << 21) // Pin Controlled by PB21
-#define AT91C_PB21_PWM2           (AT91C_PIO_PB21) //  PWM Channel 2
-#define AT91C_PB21_PCK1           (AT91C_PIO_PB21) //  PMC Programmable Clock Output 1
-#define AT91C_PIO_PB22            (1 << 22) // Pin Controlled by PB22
-#define AT91C_PB22_PWM3           (AT91C_PIO_PB22) //  PWM Channel 3
-#define AT91C_PB22_PCK2           (AT91C_PIO_PB22) //  PMC Programmable Clock Output 2
-#define AT91C_PIO_PB23            (1 << 23) // Pin Controlled by PB23
-#define AT91C_PB23_TIOA0          (AT91C_PIO_PB23) //  Timer Counter 0 Multipurpose Timer I/O Pin A
-#define AT91C_PB23_DCD1           (AT91C_PIO_PB23) //  USART 1 Data Carrier Detect
-#define AT91C_PIO_PB24            (1 << 24) // Pin Controlled by PB24
-#define AT91C_PB24_TIOB0          (AT91C_PIO_PB24) //  Timer Counter 0 Multipurpose Timer I/O Pin B
-#define AT91C_PB24_DSR1           (AT91C_PIO_PB24) //  USART 1 Data Set ready
-#define AT91C_PIO_PB25            (1 << 25) // Pin Controlled by PB25
-#define AT91C_PB25_TIOA1          (AT91C_PIO_PB25) //  Timer Counter 1 Multipurpose Timer I/O Pin A
-#define AT91C_PB25_DTR1           (AT91C_PIO_PB25) //  USART 1 Data Terminal ready
-#define AT91C_PIO_PB26            (1 << 26) // Pin Controlled by PB26
-#define AT91C_PB26_TIOB1          (AT91C_PIO_PB26) //  Timer Counter 1 Multipurpose Timer I/O Pin B
-#define AT91C_PB26_RI1            (AT91C_PIO_PB26) //  USART 1 Ring Indicator
-#define AT91C_PIO_PB27            (1 << 27) // Pin Controlled by PB27
-#define AT91C_PB27_TIOA2          (AT91C_PIO_PB27) //  Timer Counter 2 Multipurpose Timer I/O Pin A
-#define AT91C_PB27_PWM0           (AT91C_PIO_PB27) //  PWM Channel 0
-#define AT91C_PIO_PB28            (1 << 28) // Pin Controlled by PB28
-#define AT91C_PB28_TIOB2          (AT91C_PIO_PB28) //  Timer Counter 2 Multipurpose Timer I/O Pin B
-#define AT91C_PB28_PWM1           (AT91C_PIO_PB28) //  PWM Channel 1
-#define AT91C_PIO_PB29            (1 << 29) // Pin Controlled by PB29
-#define AT91C_PB29_PCK1           (AT91C_PIO_PB29) //  PMC Programmable Clock Output 1
-#define AT91C_PB29_PWM2           (AT91C_PIO_PB29) //  PWM Channel 2
-#define AT91C_PIO_PB3             (1 <<  3) // Pin Controlled by PB3
-#define AT91C_PB3_ETX1            (AT91C_PIO_PB3) //  Ethernet MAC Transmit Data 1
-#define AT91C_PIO_PB30            (1 << 30) // Pin Controlled by PB30
-#define AT91C_PB30_PCK2           (AT91C_PIO_PB30) //  PMC Programmable Clock Output 2
-#define AT91C_PB30_PWM3           (AT91C_PIO_PB30) //  PWM Channel 3
-#define AT91C_PIO_PB4             (1 <<  4) // Pin Controlled by PB4
-#define AT91C_PB4_ECRS_ECRSDV     (AT91C_PIO_PB4) //  Ethernet MAC Carrier Sense/Carrier Sense and Data Valid
-#define AT91C_PIO_PB5             (1 <<  5) // Pin Controlled by PB5
-#define AT91C_PB5_ERX0            (AT91C_PIO_PB5) //  Ethernet MAC Receive Data 0
-#define AT91C_PIO_PB6             (1 <<  6) // Pin Controlled by PB6
-#define AT91C_PB6_ERX1            (AT91C_PIO_PB6) //  Ethernet MAC Receive Data 1
-#define AT91C_PIO_PB7             (1 <<  7) // Pin Controlled by PB7
-#define AT91C_PB7_ERXER           (AT91C_PIO_PB7) //  Ethernet MAC Receive Error
-#define AT91C_PIO_PB8             (1 <<  8) // Pin Controlled by PB8
-#define AT91C_PB8_EMDC            (AT91C_PIO_PB8) //  Ethernet MAC Management Data Clock
-#define AT91C_PIO_PB9             (1 <<  9) // Pin Controlled by PB9
-#define AT91C_PB9_EMDIO           (AT91C_PIO_PB9) //  Ethernet MAC Management Data Input/Output
-
-// *****************************************************************************
-//               PERIPHERAL ID DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ID_FIQ              ( 0) // Advanced Interrupt Controller (FIQ)
-#define AT91C_ID_SYS              ( 1) // System Peripheral
-#define AT91C_ID_PIOA             ( 2) // Parallel IO Controller A
-#define AT91C_ID_PIOB             ( 3) // Parallel IO Controller B
-#define AT91C_ID_SPI0             ( 4) // Serial Peripheral Interface 0
-#define AT91C_ID_SPI1             ( 5) // Serial Peripheral Interface 1
-#define AT91C_ID_US0              ( 6) // USART 0
-#define AT91C_ID_US1              ( 7) // USART 1
-#define AT91C_ID_SSC              ( 8) // Serial Synchronous Controller
-#define AT91C_ID_TWI              ( 9) // Two-Wire Interface
-#define AT91C_ID_PWMC             (10) // PWM Controller
-#define AT91C_ID_UDP              (11) // USB Device Port
-#define AT91C_ID_TC0              (12) // Timer Counter 0
-#define AT91C_ID_TC1              (13) // Timer Counter 1
-#define AT91C_ID_TC2              (14) // Timer Counter 2
-#define AT91C_ID_CAN              (15) // Control Area Network Controller
-#define AT91C_ID_EMAC             (16) // Ethernet MAC
-#define AT91C_ID_ADC              (17) // Analog-to-Digital Converter
-#define AT91C_ID_AES              (18) // Advanced Encryption Standard 128-bit
-#define AT91C_ID_TDES             (19) // Triple Data Encryption Standard
-#define AT91C_ID_20_Reserved      (20) // Reserved
-#define AT91C_ID_21_Reserved      (21) // Reserved
-#define AT91C_ID_22_Reserved      (22) // Reserved
-#define AT91C_ID_23_Reserved      (23) // Reserved
-#define AT91C_ID_24_Reserved      (24) // Reserved
-#define AT91C_ID_25_Reserved      (25) // Reserved
-#define AT91C_ID_26_Reserved      (26) // Reserved
-#define AT91C_ID_27_Reserved      (27) // Reserved
-#define AT91C_ID_28_Reserved      (28) // Reserved
-#define AT91C_ID_29_Reserved      (29) // Reserved
-#define AT91C_ID_IRQ0             (30) // Advanced Interrupt Controller (IRQ0)
-#define AT91C_ID_IRQ1             (31) // Advanced Interrupt Controller (IRQ1)
-
-// *****************************************************************************
-//               BASE ADDRESS DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_BASE_SYS            (0xFFFFF000) // (SYS) Base Address
-#define AT91C_BASE_AIC            (0xFFFFF000) // (AIC) Base Address
-#define AT91C_BASE_PDC_DBGU       (0xFFFFF300) // (PDC_DBGU) Base Address
-#define AT91C_BASE_DBGU           (0xFFFFF200) // (DBGU) Base Address
-#define AT91C_BASE_PIOA           (0xFFFFF400) // (PIOA) Base Address
-#define AT91C_BASE_PIOB           (0xFFFFF600) // (PIOB) Base Address
-#define AT91C_BASE_CKGR           (0xFFFFFC20) // (CKGR) Base Address
-#define AT91C_BASE_PMC            (0xFFFFFC00) // (PMC) Base Address
-#define AT91C_BASE_RSTC           (0xFFFFFD00) // (RSTC) Base Address
-#define AT91C_BASE_RTTC           (0xFFFFFD20) // (RTTC) Base Address
-#define AT91C_BASE_PITC           (0xFFFFFD30) // (PITC) Base Address
-#define AT91C_BASE_WDTC           (0xFFFFFD40) // (WDTC) Base Address
-#define AT91C_BASE_VREG           (0xFFFFFD60) // (VREG) Base Address
-#define AT91C_BASE_MC             (0xFFFFFF00) // (MC) Base Address
-#define AT91C_BASE_PDC_SPI1       (0xFFFE4100) // (PDC_SPI1) Base Address
-#define AT91C_BASE_SPI1           (0xFFFE4000) // (SPI1) Base Address
-#define AT91C_BASE_PDC_SPI0       (0xFFFE0100) // (PDC_SPI0) Base Address
-#define AT91C_BASE_SPI0           (0xFFFE0000) // (SPI0) Base Address
-#define AT91C_BASE_PDC_US1        (0xFFFC4100) // (PDC_US1) Base Address
-#define AT91C_BASE_US1            (0xFFFC4000) // (US1) Base Address
-#define AT91C_BASE_PDC_US0        (0xFFFC0100) // (PDC_US0) Base Address
-#define AT91C_BASE_US0            (0xFFFC0000) // (US0) Base Address
-#define AT91C_BASE_PDC_SSC        (0xFFFD4100) // (PDC_SSC) Base Address
-#define AT91C_BASE_SSC            (0xFFFD4000) // (SSC) Base Address
-#define AT91C_BASE_TWI            (0xFFFB8000) // (TWI) Base Address
-#define AT91C_BASE_PWMC_CH3       (0xFFFCC260) // (PWMC_CH3) Base Address
-#define AT91C_BASE_PWMC_CH2       (0xFFFCC240) // (PWMC_CH2) Base Address
-#define AT91C_BASE_PWMC_CH1       (0xFFFCC220) // (PWMC_CH1) Base Address
-#define AT91C_BASE_PWMC_CH0       (0xFFFCC200) // (PWMC_CH0) Base Address
-#define AT91C_BASE_PWMC           (0xFFFCC000) // (PWMC) Base Address
-#define AT91C_BASE_UDP            (0xFFFB0000) // (UDP) Base Address
-#define AT91C_BASE_TC0            (0xFFFA0000) // (TC0) Base Address
-#define AT91C_BASE_TC1            (0xFFFA0040) // (TC1) Base Address
-#define AT91C_BASE_TC2            (0xFFFA0080) // (TC2) Base Address
-#define AT91C_BASE_TCB            (0xFFFA0000) // (TCB) Base Address
-#define AT91C_BASE_CAN_MB0        (0xFFFD0200) // (CAN_MB0) Base Address
-#define AT91C_BASE_CAN_MB1        (0xFFFD0220) // (CAN_MB1) Base Address
-#define AT91C_BASE_CAN_MB2        (0xFFFD0240) // (CAN_MB2) Base Address
-#define AT91C_BASE_CAN_MB3        (0xFFFD0260) // (CAN_MB3) Base Address
-#define AT91C_BASE_CAN_MB4        (0xFFFD0280) // (CAN_MB4) Base Address
-#define AT91C_BASE_CAN_MB5        (0xFFFD02A0) // (CAN_MB5) Base Address
-#define AT91C_BASE_CAN_MB6        (0xFFFD02C0) // (CAN_MB6) Base Address
-#define AT91C_BASE_CAN_MB7        (0xFFFD02E0) // (CAN_MB7) Base Address
-#define AT91C_BASE_CAN            (0xFFFD0000) // (CAN) Base Address
-#define AT91C_BASE_EMAC           (0xFFFDC000) // (EMAC) Base Address
-#define AT91C_BASE_PDC_ADC        (0xFFFD8100) // (PDC_ADC) Base Address
-#define AT91C_BASE_ADC            (0xFFFD8000) // (ADC) Base Address
-#define AT91C_BASE_PDC_AES        (0xFFFA4100) // (PDC_AES) Base Address
-#define AT91C_BASE_AES            (0xFFFA4000) // (AES) Base Address
-#define AT91C_BASE_PDC_TDES       (0xFFFA8100) // (PDC_TDES) Base Address
-#define AT91C_BASE_TDES           (0xFFFA8000) // (TDES) Base Address
-
-// *****************************************************************************
-//               MEMORY MAPPING DEFINITIONS FOR AT91SAM7X256
-// *****************************************************************************
-#define AT91C_ISRAM	              (0x00200000) // Internal SRAM base address
-#define AT91C_ISRAM_SIZE	         (0x00010000) // Internal SRAM size in byte (64 Kbyte)
-#define AT91C_IFLASH	             (0x00100000) // Internal ROM base address
-#define AT91C_IFLASH_SIZE	        (0x00040000) // Internal ROM size in byte (256 Kbyte)
-
-
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h
deleted file mode 100755
index babc698..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/ISR_Support.h
+++ /dev/null
@@ -1,105 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	EXTERN pxCurrentTCB
-	EXTERN ulCriticalNesting
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-portSAVE_CONTEXT MACRO
-
-	; Push R0 as we are going to use the register.
-	STMDB	SP!, {R0}
-
-	; Set R0 to point to the task stack pointer.
-	STMDB	SP, {SP}^
-	NOP
-	SUB		SP, SP, #4
-	LDMIA	SP!, {R0}
-
-	; Push the return address onto the stack.
-	STMDB	R0!, {LR}
-
-	; Now we have saved LR we can use it instead of R0.
-	MOV		LR, R0
-
-	; Pop R0 so we can save it onto the system mode stack.
-	LDMIA	SP!, {R0}
-
-	; Push all the system mode registers onto the task stack.
-	STMDB	LR, {R0-LR}^
-	NOP
-	SUB		LR, LR, #60
-
-	; Push the SPSR onto the task stack.
-	MRS		R0, SPSR
-	STMDB	LR!, {R0}
-
-	LDR		R0, =ulCriticalNesting
-	LDR		R0, [R0]
-	STMDB	LR!, {R0}
-
-	; Store the new top of stack for the task.
-	LDR		R1, =pxCurrentTCB
-	LDR		R0, [R1]
-	STR		LR, [R0]
-
-	ENDM
-
-
-portRESTORE_CONTEXT MACRO
-
-	; Set the LR to the task stack.
-	LDR		R1, =pxCurrentTCB
-	LDR		R0, [R1]
-	LDR		LR, [R0]
-
-	; The critical nesting depth is the first item on the stack.
-	; Load it into the ulCriticalNesting variable.
-	LDR		R0, =ulCriticalNesting
-	LDMFD	LR!, {R1}
-	STR		R1, [R0]
-
-	; Get the SPSR from the stack.
-	LDMFD	LR!, {R0}
-	MSR		SPSR_cxsf, R0
-
-	; Restore all system mode registers for the task.
-	LDMFD	LR, {R0-R14}^
-	NOP
-
-	; Restore the return address.
-	LDR		LR, [LR, #+60]
-
-	; And return - correcting the offset in the LR to obtain the
-	; correct address.
-	SUBS	PC, LR, #4
-
-	ENDM
-
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
deleted file mode 100755
index 3f1634d..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7S64.h
+++ /dev/null
@@ -1,3265 +0,0 @@
-//*----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//*----------------------------------------------------------------------------
-//* The software is delivered "AS IS" without warranty or condition of any
-//* kind, either express, implied or statutory. This includes without
-//* limitation any warranty or condition with respect to merchantability or
-//* fitness for any particular purpose, or against the infringements of
-//* intellectual property rights of others.
-//*----------------------------------------------------------------------------
-//* File Name           : lib_AT91SAM7S64.h
-//* Object              : AT91SAM7S64 inlined functions
-//* Generated           : AT91 SW Application Group  07/16/2004 (07:43:09)
-//*
-//* CVS Reference       : /lib_MC_SAM.h/1.3/Thu Mar 25 15:19:14 2004//
-//* CVS Reference       : /lib_pdc_1363d.h/1.2/Wed Feb 19 09:25:22 2003//
-//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
-//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 13:23:52 2003//
-//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference       : /lib_pmc_SAM.h/1.6/Tue Apr 27 13:53:52 2004//
-//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 08:12:38 2003//
-//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference       : /lib_twi.h/1.2/Fri Jan 31 12:19:38 2003//
-//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
-//* CVS Reference       : /lib_udp.h/1.3/Fri Jan 31 12:19:48 2003//
-//* CVS Reference       : /lib_aic.h/1.3/Fri Jul 12 07:46:12 2002//
-//*----------------------------------------------------------------------------
-
-#ifndef lib_AT91SAM7S64_H
-#define lib_AT91SAM7S64_H
-
-/* *****************************************************************************
-                SOFTWARE API FOR MC
-   ***************************************************************************** */
-
-#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_Remap
-//* \brief Make Remap
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_Remap (void)     //  
-{
-    AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
-    
-    pMC->MC_RCR = AT91C_MC_RCB;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_CfgModeReg
-//* \brief Configure the EFC Mode Register of the MC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_EFC_CfgModeReg (
-	AT91PS_MC pMC, // pointer to a MC controller
-	unsigned int mode)        // mode register 
-{
-	// Write to the FMR register
-	pMC->MC_FMR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_GetModeReg
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_GetModeReg(
-	AT91PS_MC pMC) // pointer to a MC controller
-{
-	return pMC->MC_FMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_ComputeFMCN
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
-	int master_clock) // master clock in Hz
-{
-	return (master_clock/1000000 +2);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_PerformCmd
-//* \brief Perform EFC Command
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_EFC_PerformCmd (
-	AT91PS_MC pMC, // pointer to a MC controller
-    unsigned int transfer_cmd)
-{
-	pMC->MC_FCR = transfer_cmd;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_GetStatus
-//* \brief Return MC EFC Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_GetStatus(
-	AT91PS_MC pMC) // pointer to a MC controller
-{
-	return pMC->MC_FSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_IsInterruptMasked
-//* \brief Test if EFC MC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
-        AT91PS_MC pMC,   // \arg  pointer to a MC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_IsInterruptSet
-//* \brief Test if EFC MC Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
-        AT91PS_MC pMC,   // \arg  pointer to a MC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_MC_EFC_GetStatus(pMC) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PDC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextRx
-//* \brief Set the next receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextRx (
-	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
-	char *address,       // \arg address to the next bloc to be received
-	unsigned int bytes)  // \arg number of bytes to be received
-{
-	pPDC->PDC_RNPR = (unsigned int) address;
-	pPDC->PDC_RNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextTx
-//* \brief Set the next transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextTx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be transmitted
-	unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-	pPDC->PDC_TNPR = (unsigned int) address;
-	pPDC->PDC_TNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetRx
-//* \brief Set the receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetRx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be received
-	unsigned int bytes)    // \arg number of bytes to be received
-{
-	pPDC->PDC_RPR = (unsigned int) address;
-	pPDC->PDC_RCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetTx
-//* \brief Set the transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetTx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be transmitted
-	unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-	pPDC->PDC_TPR = (unsigned int) address;
-	pPDC->PDC_TCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableTx
-//* \brief Enable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableTx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableRx
-//* \brief Enable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableRx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableTx
-//* \brief Disable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableTx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableRx
-//* \brief Disable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableRx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsTxEmpty
-//* \brief Test if the current transfer descriptor has been sent
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_TCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextTxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_TNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsRxEmpty
-//* \brief Test if the current transfer descriptor has been filled
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_RCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextRxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_RNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Open
-//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Open (
-	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-	AT91F_PDC_DisableRx(pPDC);
-	AT91F_PDC_DisableTx(pPDC);
-
-	//* Reset all Counter register Next buffer first
-	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-    //* Enable the RX and TX PDC transfer requests
-	AT91F_PDC_EnableRx(pPDC);
-	AT91F_PDC_EnableTx(pPDC);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Close
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Close (
-	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-	AT91F_PDC_DisableRx(pPDC);
-	AT91F_PDC_DisableTx(pPDC);
-
-	//* Reset all Counter register Next buffer first
-	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SendFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_SendFrame(
-	AT91PS_PDC pPDC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	if (AT91F_PDC_IsTxEmpty(pPDC)) {
-		//* Buffer and next buffer can be initialized
-		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
-		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
-		return 2;
-	}
-	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
-		//* Only one buffer can be initialized
-		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
-		return 1;
-	}
-	else {
-		//* All buffer are in use...
-		return 0;
-	}
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_ReceiveFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_ReceiveFrame (
-	AT91PS_PDC pPDC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	if (AT91F_PDC_IsRxEmpty(pPDC)) {
-		//* Buffer and next buffer can be initialized
-		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
-		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
-		return 2;
-	}
-	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
-		//* Only one buffer can be initialized
-		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
-		return 1;
-	}
-	else {
-		//* All buffer are in use...
-		return 0;
-	}
-}
-/* *****************************************************************************
-                SOFTWARE API FOR DBGU
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptEnable
-//* \brief Enable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptEnable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be enabled
-{
-        pDbgu->DBGU_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptDisable
-//* \brief Disable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptDisable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be disabled
-{
-        pDbgu->DBGU_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_GetInterruptMaskStatus
-//* \brief Return DBGU Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
-        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
-{
-        return pDbgu->DBGU_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_IsInterruptMasked
-//* \brief Test if DBGU Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_DBGU_IsInterruptMasked(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR SSC
-   ***************************************************************************** */
-//* Define the standard I2S mode configuration
-
-//* Configuration to set in the SSC Transmit Clock Mode Register
-//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
-//* 			  nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
-									   AT91C_SSC_CKS_DIV   +\
-                            		   AT91C_SSC_CKO_CONTINOUS      +\
-                            		   AT91C_SSC_CKG_NONE    +\
-                                       AT91C_SSC_START_FALL_RF +\
-                           			   AT91C_SSC_STTOUT  +\
-                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
-                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
-
-
-//* Configuration to set in the SSC Transmit Frame Mode Register
-//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
-//* 			 nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
-									(nb_bit_by_slot-1)  +\
-                            		AT91C_SSC_MSBF   +\
-                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
-                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
-                            		AT91C_SSC_FSOS_NEGATIVE)
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_SetBaudrate (
-        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
-        unsigned int mainClock, // \arg peripheral clock
-        unsigned int speed)     // \arg SSC baudrate
-{
-        unsigned int baud_value;
-        //* Define the baud rate divisor register
-        if (speed == 0)
-           baud_value = 0;
-        else
-        {
-           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
-           if ((baud_value % 10) >= 5)
-                  baud_value = (baud_value / 10) + 1;
-           else
-                  baud_value /= 10;
-        }
-
-        pSSC->SSC_CMR = baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_Configure
-//* \brief Configure SSC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_Configure (
-             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
-             unsigned int syst_clock,  // \arg System Clock Frequency
-             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
-             unsigned int clock_rx,    // \arg Receiver Clock Parameters
-             unsigned int mode_rx,     // \arg mode Register to be programmed
-             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
-             unsigned int mode_tx)     // \arg mode Register to be programmed
-{
-    //* Disable interrupts
-	pSSC->SSC_IDR = (unsigned int) -1;
-
-    //* Reset receiver and transmitter
-	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
-
-    //* Define the Clock Mode Register
-	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
-
-     //* Write the Receive Clock Mode Register
-	pSSC->SSC_RCMR =  clock_rx;
-
-     //* Write the Transmit Clock Mode Register
-	pSSC->SSC_TCMR =  clock_tx;
-
-     //* Write the Receive Frame Mode Register
-	pSSC->SSC_RFMR =  mode_rx;
-
-     //* Write the Transmit Frame Mode Register
-	pSSC->SSC_TFMR =  mode_tx;
-
-    //* Clear Transmit and Receive Counters
-	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
-
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableRx
-//* \brief Enable receiving datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableRx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Enable receiver
-    pSSC->SSC_CR = AT91C_SSC_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableRx
-//* \brief Disable receiving datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableRx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Disable receiver
-    pSSC->SSC_CR = AT91C_SSC_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableTx
-//* \brief Enable sending datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableTx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Enable  transmitter
-    pSSC->SSC_CR = AT91C_SSC_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableTx
-//* \brief Disable sending datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableTx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Disable  transmitter
-    pSSC->SSC_CR = AT91C_SSC_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableIt
-//* \brief Enable SSC IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableIt (
-	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pSSC->SSC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableIt
-//* \brief Disable SSC IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableIt (
-	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pSSC->SSC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_ReceiveFrame (
-	AT91PS_SSC pSSC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pSSC->SSC_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_SendFrame(
-	AT91PS_SSC pSSC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pSSC->SSC_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_GetInterruptMaskStatus
-//* \brief Return SSC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
-        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
-{
-        return pSsc->SSC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_IsInterruptMasked
-//* \brief Test if SSC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_SSC_IsInterruptMasked(
-        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR SPI
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Open
-//* \brief Open a SPI Port
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_Open (
-        const unsigned int null)  // \arg
-{
-        /* NOT DEFINED AT THIS MOMENT */
-        return ( 0 );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgCs
-//* \brief Configure SPI chip select register
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgCs (
-	AT91PS_SPI pSPI,     // pointer to a SPI controller
-	int cs,     // SPI cs number (0 to 3)
- 	int val)   //  chip select register
-{
-	//* Write to the CSR register
-	*(pSPI->SPI_CSR + cs) = val;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_EnableIt
-//* \brief Enable SPI interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_EnableIt (
-	AT91PS_SPI pSPI,     // pointer to a SPI controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pSPI->SPI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_DisableIt
-//* \brief Disable SPI interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_DisableIt (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pSPI->SPI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Reset
-//* \brief Reset the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Reset (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SWRST;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Enable
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Enable (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Disable
-//* \brief Disable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Disable (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgMode
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgMode (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	int mode)        // mode register 
-{
-	//* Write to the MR register
-	pSPI->SPI_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgPCS
-//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgPCS (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	char PCS_Device) // PCS of the Device
-{	
- 	//* Write to the MR register
-	pSPI->SPI_MR &= 0xFFF0FFFF;
-	pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_ReceiveFrame (
-	AT91PS_SPI pSPI,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pSPI->SPI_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_SendFrame(
-	AT91PS_SPI pSPI,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pSPI->SPI_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Close
-//* \brief Close SPI: disable IT disable transfert, close PDC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Close (
-	AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
-{
-    //* Reset all the Chip Select register
-    pSPI->SPI_CSR[0] = 0 ;
-    pSPI->SPI_CSR[1] = 0 ;
-    pSPI->SPI_CSR[2] = 0 ;
-    pSPI->SPI_CSR[3] = 0 ;
-
-    //* Reset the SPI mode
-    pSPI->SPI_MR = 0  ;
-
-    //* Disable all interrupts
-    pSPI->SPI_IDR = 0xFFFFFFFF ;
-
-    //* Abort the Peripheral Data Transfers
-    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
-
-    //* Disable receiver and transmitter and stop any activity immediately
-    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_PutChar (
-	AT91PS_SPI pSPI,
-	unsigned int character,
-             unsigned int cs_number )
-{
-    unsigned int value_for_cs;
-    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
-    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-__inline int AT91F_SPI_GetChar (
-	const AT91PS_SPI pSPI)
-{
-    return((pSPI->SPI_RDR) & 0xFFFF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_GetInterruptMaskStatus
-//* \brief Return SPI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
-        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
-{
-        return pSpi->SPI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_IsInterruptMasked
-//* \brief Test if SPI Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_SPI_IsInterruptMasked(
-        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PWMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_GetStatus
-//* \brief Return PWM Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
-	AT91PS_PWMC pPWM) // pointer to a PWM controller
-{
-	return pPWM->PWMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_InterruptEnable
-//* \brief Enable PWM Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_InterruptEnable(
-        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  PWM interrupt to be enabled
-{
-        pPwm->PWMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_InterruptDisable
-//* \brief Disable PWM Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_InterruptDisable(
-        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  PWM interrupt to be disabled
-{
-        pPwm->PWMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_GetInterruptMaskStatus
-//* \brief Return PWM Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
-        AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
-{
-        return pPwm->PWMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_IsInterruptMasked
-//* \brief Test if PWM Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_IsInterruptMasked(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_IsStatusSet
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_IsStatusSet(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PWMC_GetStatus(pPWM) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_CfgChannel
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CfgChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int channelId, // \arg PWM channel ID
-        unsigned int mode, // \arg  PWM mode
-        unsigned int period, // \arg PWM period
-        unsigned int duty) // \arg PWM duty cycle
-{
-	pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
-	pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
-	pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_StartChannel
-//* \brief Enable channel
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_StartChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  Channels IDs to be enabled
-{
-	pPWM->PWMC_ENA = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_StopChannel
-//* \brief Disable channel
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_StopChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  Channels IDs to be enabled
-{
-	pPWM->PWMC_DIS = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_UpdateChannel
-//* \brief Update Period or Duty Cycle
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_UpdateChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int channelId, // \arg PWM channel ID
-        unsigned int update) // \arg  Channels IDs to be enabled
-{
-	pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR TC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_InterruptEnable
-//* \brief Enable TC Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC_InterruptEnable(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  TC interrupt to be enabled
-{
-        pTc->TC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_InterruptDisable
-//* \brief Disable TC Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC_InterruptDisable(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  TC interrupt to be disabled
-{
-        pTc->TC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_GetInterruptMaskStatus
-//* \brief Return TC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
-        AT91PS_TC pTc) // \arg  pointer to a TC controller
-{
-        return pTc->TC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_IsInterruptMasked
-//* \brief Test if TC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_TC_IsInterruptMasked(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkEnableReg
-//* \brief Configure the System Clock Enable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkEnableReg (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int mode)
-{
-	//* Write to the SCER register
-	pPMC->PMC_SCER = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkDisableReg
-//* \brief Configure the System Clock Disable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkDisableReg (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int mode)
-{
-	//* Write to the SCDR register
-	pPMC->PMC_SCDR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetSysClkStatusReg
-//* \brief Return the System Clock Status Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
-	AT91PS_PMC pPMC // pointer to a CAN controller
-	)
-{
-	return pPMC->PMC_SCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePeriphClock
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePeriphClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-	pPMC->PMC_PCER = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePeriphClock
-//* \brief Disable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePeriphClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-	pPMC->PMC_PCDR = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetPeriphClock
-//* \brief Get peripheral clock status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetPeriphClock (
-	AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-	return pPMC->PMC_PCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscillatorReg (
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int mode)
-{
-	pCKGR->CKGR_MOR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	return pCKGR->CKGR_MOR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_EnableMainOscillator
-//* \brief Enable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_EnableMainOscillator(
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_DisableMainOscillator
-//* \brief Disable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_DisableMainOscillator (
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
-//* \brief Cfg MOR Register according to the main osc startup time
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscStartUpTime (
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
-	pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClockFreqReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	return pCKGR->CKGR_MCFR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClock
-//* \brief Return Main clock in Hz
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClock (
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgMCKReg
-//* \brief Cfg Master Clock Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgMCKReg (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int mode)
-{
-	pPMC->PMC_MCKR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMCKReg
-//* \brief Return Master Clock Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMCKReg(
-	AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-	return pPMC->PMC_MCKR;
-}
-
-//*------------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMasterClock
-//* \brief Return master clock in Hz which correponds to processor clock for ARM7
-//*------------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMasterClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	unsigned int reg = pPMC->PMC_MCKR;
-	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
-	unsigned int pllDivider, pllMultiplier;
-
-	switch (reg & AT91C_PMC_CSS) {
-		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
-			return slowClock / prescaler;
-		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
-			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
-		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
-			reg = pCKGR->CKGR_PLLR;
-			pllDivider    = (reg  & AT91C_CKGR_DIV);
-			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
-			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
-	}
-	return 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePCK (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
-	unsigned int mode)
-{
-	pPMC->PMC_PCKR[pck] = mode;
-	pPMC->PMC_SCER = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePCK (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
-{
-	pPMC->PMC_SCDR = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnableIt
-//* \brief Enable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnableIt (
-	AT91PS_PMC pPMC,     // pointer to a PMC controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pPMC->PMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisableIt
-//* \brief Disable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisableIt (
-	AT91PS_PMC pPMC, // pointer to a PMC controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pPMC->PMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetStatus
-//* \brief Return PMC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
-	AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-	return pPMC->PMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetInterruptMaskStatus
-//* \brief Return PMC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
-	AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-	return pPMC->PMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsInterruptMasked
-//* \brief Test if PMC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsInterruptMasked(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsStatusSet
-//* \brief Test if PMC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsStatusSet(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PMC_GetStatus(pPMC) & flag);
-}/* *****************************************************************************
-                SOFTWARE API FOR ADC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_EnableIt
-//* \brief Enable ADC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_EnableIt (
-	AT91PS_ADC pADC,     // pointer to a ADC controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pADC->ADC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_DisableIt
-//* \brief Disable ADC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_DisableIt (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pADC->ADC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetStatus
-//* \brief Return ADC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
-	AT91PS_ADC pADC) // pointer to a ADC controller
-{
-	return pADC->ADC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetInterruptMaskStatus
-//* \brief Return ADC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
-	AT91PS_ADC pADC) // pointer to a ADC controller
-{
-	return pADC->ADC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_IsInterruptMasked
-//* \brief Test if ADC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_IsInterruptMasked(
-        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_IsStatusSet
-//* \brief Test if ADC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_IsStatusSet(
-        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_ADC_GetStatus(pADC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgModeReg
-//* \brief Configure the Mode Register of the ADC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgModeReg (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int mode)        // mode register 
-{
-	//* Write to the MR register
-	pADC->ADC_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetModeReg
-//* \brief Return the Mode Register of the ADC controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetModeReg (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_MR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgTimings
-//* \brief Configure the different necessary timings of the ADC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgTimings (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int mck_clock, // in MHz 
-	unsigned int adc_clock, // in MHz 
-	unsigned int startup_time, // in us 
-	unsigned int sample_and_hold_time)	// in ns  
-{
-	unsigned int prescal,startup,shtim;
-	
-	prescal = mck_clock/(2*adc_clock) - 1;
-	startup = adc_clock*startup_time/8 - 1;
-	shtim = adc_clock*sample_and_hold_time/1000 - 1;
-	
-	//* Write to the MR register
-	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_EnableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_EnableChannel (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int channel)        // mode register 
-{
-	//* Write to the CHER register
-	pADC->ADC_CHER = channel;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_DisableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_DisableChannel (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int channel)        // mode register 
-{
-	//* Write to the CHDR register
-	pADC->ADC_CHDR = channel;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetChannelStatus
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetChannelStatus (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CHSR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_StartConversion
-//* \brief Software request for a analog to digital conversion 
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_StartConversion (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	pADC->ADC_CR = AT91C_ADC_START;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_SoftReset
-//* \brief Software reset
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_SoftReset (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	pADC->ADC_CR = AT91C_ADC_SWRST;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetLastConvertedData
-//* \brief Return the Last Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetLastConvertedData (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_LCDR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH0
-//* \brief Return the Channel 0 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR0;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH1
-//* \brief Return the Channel 1 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR1;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH2
-//* \brief Return the Channel 2 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR2;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH3
-//* \brief Return the Channel 3 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR3;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH4
-//* \brief Return the Channel 4 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR4;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH5
-//* \brief Return the Channel 5 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR5;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH6
-//* \brief Return the Channel 6 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR6;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH7
-//* \brief Return the Channel 7 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR7;	
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PIO
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPeriph
-//* \brief Enable pins to be drived by peripheral
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPeriph(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int periphAEnable,  // \arg PERIPH A to enable
-	unsigned int periphBEnable)  // \arg PERIPH B to enable
-
-{
-	pPio->PIO_ASR = periphAEnable;
-	pPio->PIO_BSR = periphBEnable;
-	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOutput
-//* \brief Enable PIO in output mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOutput(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int pioEnable)      // \arg PIO to be enabled
-{
-	pPio->PIO_PER = pioEnable; // Set in PIO mode
-	pPio->PIO_OER = pioEnable; // Configure in Output
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInput
-//* \brief Enable PIO in input mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInput(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int inputEnable)      // \arg PIO to be enabled
-{
-	// Disable output
-	pPio->PIO_ODR  = inputEnable;
-	pPio->PIO_PER  = inputEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOpendrain
-//* \brief Configure PIO in open drain
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOpendrain(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int multiDrvEnable) // \arg pio to be configured in open drain
-{
-	// Configure the multi-drive option
-	pPio->PIO_MDDR = ~multiDrvEnable;
-	pPio->PIO_MDER = multiDrvEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPullup
-//* \brief Enable pullup on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPullup(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int pullupEnable)   // \arg enable pullup on PIO
-{
-		// Connect or not Pullup
-	pPio->PIO_PPUDR = ~pullupEnable;
-	pPio->PIO_PPUER = pullupEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgDirectDrive
-//* \brief Enable direct drive on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgDirectDrive(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int directDrive)    // \arg PIO to be configured with direct drive
-
-{
-	// Configure the Direct Drive
-	pPio->PIO_OWDR  = ~directDrive;
-	pPio->PIO_OWER  = directDrive;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInputFilter
-//* \brief Enable input filter on input PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInputFilter(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int inputFilter)    // \arg PIO to be configured with input filter
-
-{
-	// Configure the Direct Drive
-	pPio->PIO_IFDR  = ~inputFilter;
-	pPio->PIO_IFER  = inputFilter;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInput
-//* \brief Return PIO input value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
-	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-	return pPio->PIO_PDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputSet
-//* \brief Test if PIO is input flag is active
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputSet(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PIO_GetInput(pPio) & flag);
-}
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_SetOutput
-//* \brief Set to 1 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_SetOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be set
-{
-	pPio->PIO_SODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ClearOutput
-//* \brief Set to 0 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ClearOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be cleared
-{
-	pPio->PIO_CODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ForceOutput
-//* \brief Force output when Direct drive option is enabled
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ForceOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be forced
-{
-	pPio->PIO_ODSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Enable
-//* \brief Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Enable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled 
-{
-        pPio->PIO_PER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Disable
-//* \brief Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Disable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled 
-{
-        pPio->PIO_PDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetStatus
-//* \brief Return PIO Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsSet
-//* \brief Test if PIO is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputEnable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be enabled
-{
-        pPio->PIO_OER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputDisable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be disabled
-{
-        pPio->PIO_ODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputStatus
-//* \brief Return PIO Output Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOuputSet
-//* \brief Test if PIO Output is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterEnable
-//* \brief Input Filter Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be enabled
-{
-        pPio->PIO_IFER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterDisable
-//* \brief Input Filter Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be disabled
-{
-        pPio->PIO_IFDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInputFilterStatus
-//* \brief Return PIO Input Filter Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IFSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputFilterSet
-//* \brief Test if PIO Input filter is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputFilterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputDataStatus
-//* \brief Return PIO Output Data Status 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status 
-	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ODSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptEnable
-//* \brief Enable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be enabled
-{
-        pPio->PIO_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptDisable
-//* \brief Disable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be disabled
-{
-        pPio->PIO_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptMaskStatus
-//* \brief Return PIO Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptMasked
-//* \brief Test if PIO Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptMasked(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptSet
-//* \brief Test if PIO Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverEnable
-//* \brief Multi Driver Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
-{
-        pPio->PIO_MDER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverDisable
-//* \brief Multi Driver Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
-{
-        pPio->PIO_MDDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetMultiDriverStatus
-//* \brief Return PIO Multi Driver Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_MDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsMultiDriverSet
-//* \brief Test if PIO MultiDriver is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsMultiDriverSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_A_RegisterSelection
-//* \brief PIO A Register Selection 
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_A_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio A register selection
-{
-        pPio->PIO_ASR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_B_RegisterSelection
-//* \brief PIO B Register Selection 
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_B_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio B register selection 
-{
-        pPio->PIO_BSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Get_AB_RegisterStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ABSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsAB_RegisterSet
-//* \brief Test if PIO AB Register is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsAB_RegisterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteEnable
-//* \brief Output Write Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be enabled
-{
-        pPio->PIO_OWER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteDisable
-//* \brief Output Write Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be disabled
-{
-        pPio->PIO_OWDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputWriteStatus
-//* \brief Return PIO Output Write Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OWSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputWriteSet
-//* \brief Test if PIO OutputWrite is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputWriteSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetCfgPullup
-//* \brief Return PIO Configuration Pullup
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup 
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PPUSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputDataStatusSet
-//* \brief Test if PIO Output Data Status is Set 
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputDataStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsCfgPullupStatusSet
-//* \brief Test if PIO Configuration Pullup Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsCfgPullupStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR TWI
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_EnableIt
-//* \brief Enable TWI IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_EnableIt (
-	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pTWI->TWI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_DisableIt
-//* \brief Disable TWI IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_DisableIt (
-	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pTWI->TWI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_Configure
-//* \brief Configure TWI in master mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
-{
-    //* Disable interrupts
-	pTWI->TWI_IDR = (unsigned int) -1;
-
-    //* Reset peripheral
-	pTWI->TWI_CR = AT91C_TWI_SWRST;
-
-	//* Set Master mode
-	pTWI->TWI_CR = AT91C_TWI_MSEN | AT91C_TWI_SVDIS;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_GetInterruptMaskStatus
-//* \brief Return TWI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
-        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
-{
-        return pTwi->TWI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_IsInterruptMasked
-//* \brief Test if TWI Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_TWI_IsInterruptMasked(
-        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR USART
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Baudrate
-//* \brief Calculate the baudrate
-//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
-                        AT91C_US_NBSTOP_1_BIT + \
-                        AT91C_US_PAR_NONE + \
-                        AT91C_US_CHRL_8_BITS + \
-                        AT91C_US_CLKS_CLOCK )
-
-//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
-                            AT91C_US_NBSTOP_1_BIT + \
-                            AT91C_US_PAR_NONE + \
-                            AT91C_US_CHRL_8_BITS + \
-                            AT91C_US_CLKS_EXT )
-
-//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
-                       AT91C_US_USMODE_NORMAL + \
-                       AT91C_US_NBSTOP_1_BIT + \
-                       AT91C_US_PAR_NONE + \
-                       AT91C_US_CHRL_8_BITS + \
-                       AT91C_US_CLKS_CLOCK )
-
-//* SCK used Label
-#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
-
-//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
-#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
-					   		 AT91C_US_CLKS_CLOCK +\
-                       		 AT91C_US_NBSTOP_1_BIT + \
-                       		 AT91C_US_PAR_EVEN + \
-                       		 AT91C_US_CHRL_8_BITS + \
-                       		 AT91C_US_CKLO +\
-                       		 AT91C_US_OVER)
-
-//* Standard IRDA mode
-#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
-                            AT91C_US_NBSTOP_1_BIT + \
-                            AT91C_US_PAR_NONE + \
-                            AT91C_US_CHRL_8_BITS + \
-                            AT91C_US_CLKS_CLOCK )
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Baudrate
-//* \brief Caluculate baud_value according to the main clock and the baud rate
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_Baudrate (
-	const unsigned int main_clock, // \arg peripheral clock
-	const unsigned int baud_rate)  // \arg UART baudrate
-{
-	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
-	if ((baud_value % 10) >= 5)
-		baud_value = (baud_value / 10) + 1;
-	else
-		baud_value /= 10;
-	return baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetBaudrate (
-	AT91PS_USART pUSART,    // \arg pointer to a USART controller
-	unsigned int mainClock, // \arg peripheral clock
-	unsigned int speed)     // \arg UART baudrate
-{
-	//* Define the baud rate divisor register
-	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetTimeguard
-//* \brief Set USART timeguard
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetTimeguard (
-	AT91PS_USART pUSART,    // \arg pointer to a USART controller
-	unsigned int timeguard) // \arg timeguard value
-{
-	//* Write the Timeguard Register
-	pUSART->US_TTGR = timeguard ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableIt
-//* \brief Enable USART IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableIt (
-	AT91PS_USART pUSART, // \arg pointer to a USART controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pUSART->US_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableIt
-//* \brief Disable USART IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableIt (
-	AT91PS_USART pUSART, // \arg pointer to a USART controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IER register
-	pUSART->US_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Configure
-//* \brief Configure USART
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_Configure (
-	AT91PS_USART pUSART,     // \arg pointer to a USART controller
-	unsigned int mainClock,  // \arg peripheral clock
-	unsigned int mode ,      // \arg mode Register to be programmed
-	unsigned int baudRate ,  // \arg baudrate to be programmed
-	unsigned int timeguard ) // \arg timeguard to be programmed
-{
-    //* Disable interrupts
-    pUSART->US_IDR = (unsigned int) -1;
-
-    //* Reset receiver and transmitter
-    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
-
-	//* Define the baud rate divisor register
-	AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
-
-	//* Write the Timeguard Register
-	AT91F_US_SetTimeguard(pUSART, timeguard);
-
-    //* Clear Transmit and Receive Counters
-    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
-
-    //* Define the USART mode
-    pUSART->US_MR = mode  ;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableRx
-//* \brief Enable receiving characters
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Enable receiver
-    pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableTx
-//* \brief Enable sending characters
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Enable  transmitter
-    pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ResetRx
-//* \brief Reset Receiver and re-enable it
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_ResetRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-	//* Reset receiver
-	pUSART->US_CR = AT91C_US_RSTRX;
-    //* Re-Enable receiver
-    pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ResetTx
-//* \brief Reset Transmitter and re-enable it
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_ResetTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-	//* Reset transmitter
-	pUSART->US_CR = AT91C_US_RSTTX;
-    //* Enable transmitter
-    pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableRx
-//* \brief Disable Receiver
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Disable receiver
-    pUSART->US_CR = AT91C_US_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableTx
-//* \brief Disable Transmitter
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Disable transmitter
-    pUSART->US_CR = AT91C_US_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Close
-//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_Close (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Reset the baud rate divisor register
-    pUSART->US_BRGR = 0 ;
-
-    //* Reset the USART mode
-    pUSART->US_MR = 0  ;
-
-    //* Reset the Timeguard Register
-    pUSART->US_TTGR = 0;
-
-    //* Disable all interrupts
-    pUSART->US_IDR = 0xFFFFFFFF ;
-
-    //* Abort the Peripheral Data Transfers
-    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
-
-    //* Disable receiver and transmitter and stop any activity immediately
-    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_TxReady
-//* \brief Return 1 if a character can be written in US_THR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_TxReady (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR & AT91C_US_TXRDY);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_RxReady
-//* \brief Return 1 if a character can be read in US_RHR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_RxReady (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR & AT91C_US_RXRDY);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Error
-//* \brief Return the error flag
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_Error (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR &
-    	(AT91C_US_OVRE |  // Overrun error
-    	 AT91C_US_FRAME | // Framing error
-    	 AT91C_US_PARE));  // Parity error
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_PutChar (
-	AT91PS_USART pUSART,
-	int character )
-{
-    pUSART->US_THR = (character & 0x1FF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-__inline int AT91F_US_GetChar (
-	const AT91PS_USART pUSART)
-{
-    return((pUSART->US_RHR) & 0x1FF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_SendFrame(
-	AT91PS_USART pUSART,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pUSART->US_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_ReceiveFrame (
-	AT91PS_USART pUSART,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pUSART->US_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetIrdaFilter
-//* \brief Set the value of IrDa filter tregister
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetIrdaFilter (
-	AT91PS_USART pUSART,
-	unsigned char value
-)
-{
-	pUSART->US_IF = value;
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR UDP
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EnableIt
-//* \brief Enable UDP IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EnableIt (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pUDP->UDP_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_DisableIt
-//* \brief Disable UDP IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_DisableIt (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pUDP->UDP_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_SetAddress
-//* \brief Set UDP functional address
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_SetAddress (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char address)   // \arg new UDP address
-{
-	pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EnableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EnableEp (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg endpoints to be enabled
-{
-	pUDP->UDP_GLBSTATE  |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_DisableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_DisableEp (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg endpoints to be enabled
-{
-	pUDP->UDP_GLBSTATE  &= ~(flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_SetState
-//* \brief Set UDP Device state
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_SetState (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg new UDP address
-{
-	pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
-	pUDP->UDP_GLBSTATE  |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_GetState
-//* \brief return UDP Device state
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
-	AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
-{
-	return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_ResetEp
-//* \brief Reset UDP endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg Endpoints to be reset
-{
-	pUDP->UDP_RSTEP = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpStall
-//* \brief Endpoint will STALL requests
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpStall(
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char endpoint)   // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpWrite
-//* \brief Write value in the DPR
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpWrite(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned char value)     // \arg value to be written in the DPR
-{
-	pUDP->UDP_FDR[endpoint] = value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpRead
-//* \brief Return value from the DPR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_EpRead(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	return pUDP->UDP_FDR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpEndOfWr
-//* \brief Notify the UDP that values in DPR are ready to be sent
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpEndOfWr(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpClear
-//* \brief Clear flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpClear(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned int flag)       // \arg flag to be cleared
-{
-	pUDP->UDP_CSR[endpoint] &= ~(flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpSet
-//* \brief Set flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpSet(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned int flag)       // \arg flag to be cleared
-{
-	pUDP->UDP_CSR[endpoint] |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpStatus
-//* \brief Return the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_EpStatus(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	return pUDP->UDP_CSR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_GetInterruptMaskStatus
-//* \brief Return UDP Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
-        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
-{
-        return pUdp->UDP_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_IsInterruptMasked
-//* \brief Test if UDP Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_UDP_IsInterruptMasked(
-        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR AIC
-   ***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AIC_ConfigureIt (
-	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
-	unsigned int irq_id,     // \arg interrupt number to initialize
-	unsigned int priority,   // \arg priority to give to the interrupt
-	unsigned int src_type,   // \arg activation and sense of activation
-	void (*newHandler) (void) ) // \arg address of the interrupt handler
-{
-	unsigned int oldHandler;
-    unsigned int mask ;
-
-    oldHandler = pAic->AIC_SVR[irq_id];
-
-    mask = 0x1 << irq_id ;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Save the interrupt handler routine pointer and the interrupt priority
-    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
-    //* Store the Source Mode Register
-    pAic->AIC_SMR[irq_id] = src_type | priority  ;
-    //* Clear the interrupt on the interrupt controller
-    pAic->AIC_ICCR = mask ;
-
-	return oldHandler;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_EnableIt
-//* \brief Enable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_EnableIt (
-	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-	unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    //* Enable the interrupt on the interrupt controller
-    pAic->AIC_IECR = 0x1 << irq_id ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_DisableIt
-//* \brief Disable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_DisableIt (
-	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-	unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    unsigned int mask = 0x1 << irq_id;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = mask ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ClearIt
-//* \brief Clear corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_ClearIt (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg interrupt number to initialize
-{
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = (0x1 << irq_id);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_AcknowledgeIt
-//* \brief Acknowledge corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_AcknowledgeIt (
-	AT91PS_AIC pAic)     // \arg pointer to the AIC registers
-{
-    pAic->AIC_EOICR = pAic->AIC_EOICR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_SetExceptionVector
-//* \brief Configure vector handler
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_SetExceptionVector (
-	unsigned int *pVector, // \arg pointer to the AIC registers
-	void (*Handler) () )   // \arg Interrupt Handler
-{
-	unsigned int oldVector = *pVector;
-
-	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
-		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
-	else
-		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
-
-	return oldVector;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Trig
-//* \brief Trig an IT
-//*----------------------------------------------------------------------------
-__inline void  AT91F_AIC_Trig (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg interrupt number
-{
-	pAic->AIC_ISCR = (0x1 << irq_id) ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsActive
-//* \brief Test if an IT is active
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsActive (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg Interrupt Number
-{
-	return (pAic->AIC_ISR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsPending
-//* \brief Test if an IT is pending
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsPending (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg Interrupt Number
-{
-	return (pAic->AIC_IPR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Open
-//* \brief Set exception vectors and AIC registers to default values
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_Open(
-	AT91PS_AIC pAic,        // \arg pointer to the AIC registers
-	void (*IrqHandler) (),  // \arg Default IRQ vector exception
-	void (*FiqHandler) (),  // \arg Default FIQ vector exception
-	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
-	void (*SpuriousHandler) (), // \arg Default Spurious Handler
-	unsigned int protectMode)   // \arg Debug Control Register
-{
-	int i;
-
-	// Disable all interrupts and set IVR to the default handler
-	for (i = 0; i < 32; ++i) {
-		AT91F_AIC_DisableIt(pAic, i);
-		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE, DefaultHandler);
-	}
-
-	// Set the IRQ exception vector
-	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
-	// Set the Fast Interrupt exception vector
-	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
-
-	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
-	pAic->AIC_DCR = protectMode;
-}
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  MC
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  DBGU
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_CfgPIO
-//* \brief Configure PIO controllers to drive DBGU signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA10_DTXD    ) |
-		((unsigned int) AT91C_PA9_DRXD    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH3_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH3 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH3_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA14_PWM3    ) |
-		((unsigned int) AT91C_PA7_PWM3    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH2_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH2 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH2_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA2_PWM2    ), // Peripheral A
-		((unsigned int) AT91C_PA25_PWM2    ) |
-		((unsigned int) AT91C_PA13_PWM2    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH1_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA1_PWM1    ), // Peripheral A
-		((unsigned int) AT91C_PA24_PWM1    ) |
-		((unsigned int) AT91C_PA12_PWM1    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH0_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA0_PWM0    ), // Peripheral A
-		((unsigned int) AT91C_PA23_PWM0    ) |
-		((unsigned int) AT91C_PA11_PWM0    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SSC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SSC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_CfgPIO
-//* \brief Configure PIO controllers to drive SSC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA17_TD      ) |
-		((unsigned int) AT91C_PA15_TF      ) |
-		((unsigned int) AT91C_PA19_RK      ) |
-		((unsigned int) AT91C_PA18_RD      ) |
-		((unsigned int) AT91C_PA20_RF      ) |
-		((unsigned int) AT91C_PA16_TK      ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SPI
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SPI));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgPIO
-//* \brief Configure PIO controllers to drive SPI signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA11_NPCS0   ) |
-		((unsigned int) AT91C_PA13_MOSI    ) |
-		((unsigned int) AT91C_PA31_NPCS1   ) |
-		((unsigned int) AT91C_PA12_MISO    ) |
-		((unsigned int) AT91C_PA14_SPCK    ), // Peripheral A
-		((unsigned int) AT91C_PA9_NPCS1   ) |
-		((unsigned int) AT91C_PA30_NPCS2   ) |
-		((unsigned int) AT91C_PA10_NPCS2   ) |
-		((unsigned int) AT91C_PA22_NPCS3   ) |
-		((unsigned int) AT91C_PA3_NPCS3   ) |
-		((unsigned int) AT91C_PA5_NPCS3   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PWMC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PWMC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC2_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC2
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC2_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC2));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC2_CfgPIO
-//* \brief Configure PIO controllers to drive TC2 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC2_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA26_TIOA2   ) |
-		((unsigned int) AT91C_PA27_TIOB2   ) |
-		((unsigned int) AT91C_PA29_TCLK2   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC1
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC1_CfgPIO
-//* \brief Configure PIO controllers to drive TC1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA15_TIOA1   ) |
-		((unsigned int) AT91C_PA16_TIOB1   ) |
-		((unsigned int) AT91C_PA28_TCLK1   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC0
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC0_CfgPIO
-//* \brief Configure PIO controllers to drive TC0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA0_TIOA0   ) |
-		((unsigned int) AT91C_PA1_TIOB0   ) |
-		((unsigned int) AT91C_PA4_TCLK0   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PMC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgPIO
-//* \brief Configure PIO controllers to drive PMC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA17_PCK1    ) |
-		((unsigned int) AT91C_PA21_PCK1    ) |
-		((unsigned int) AT91C_PA31_PCK2    ) |
-		((unsigned int) AT91C_PA18_PCK2    ) |
-		((unsigned int) AT91C_PA6_PCK0    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  ADC
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_ADC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgPIO
-//* \brief Configure PIO controllers to drive ADC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA8_ADTRG   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIOA_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PIOA
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIOA_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PIOA));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TWI
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TWI));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_CfgPIO
-//* \brief Configure PIO controllers to drive TWI signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA3_TWD     ) |
-		((unsigned int) AT91C_PA4_TWCK    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US1
-//*----------------------------------------------------------------------------
-__inline void AT91F_US1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_US1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US1_CfgPIO
-//* \brief Configure PIO controllers to drive US1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_US1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA21_RXD1    ) |
-		((unsigned int) AT91C_PA27_DTR1    ) |
-		((unsigned int) AT91C_PA26_DCD1    ) |
-		((unsigned int) AT91C_PA22_TXD1    ) |
-		((unsigned int) AT91C_PA24_RTS1    ) |
-		((unsigned int) AT91C_PA23_SCK1    ) |
-		((unsigned int) AT91C_PA28_DSR1    ) |
-		((unsigned int) AT91C_PA29_RI1     ) |
-		((unsigned int) AT91C_PA25_CTS1    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US0
-//*----------------------------------------------------------------------------
-__inline void AT91F_US0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_US0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US0_CfgPIO
-//* \brief Configure PIO controllers to drive US0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_US0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA5_RXD0    ) |
-		((unsigned int) AT91C_PA6_TXD0    ) |
-		((unsigned int) AT91C_PA7_RTS0    ) |
-		((unsigned int) AT91C_PA8_CTS0    ), // Peripheral A
-		((unsigned int) AT91C_PA2_SCK0    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  UDP
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_UDP));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  AIC
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_IRQ0) |
-		((unsigned int) 1 << AT91C_ID_FIQ) |
-		((unsigned int) 1 << AT91C_ID_IRQ1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_CfgPIO
-//* \brief Configure PIO controllers to drive AIC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA30_IRQ1    ), // Peripheral A
-		((unsigned int) AT91C_PA20_IRQ0    ) |
-		((unsigned int) AT91C_PA19_FIQ     )); // Peripheral B
-}
-
-#endif // lib_AT91SAM7S64_H
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
deleted file mode 100755
index 93bb5f2..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X128.h
+++ /dev/null
@@ -1,4558 +0,0 @@
-//* ----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//* ----------------------------------------------------------------------------
-//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//* ----------------------------------------------------------------------------
-//* File Name           : lib_AT91SAM7X128.h
-//* Object              : AT91SAM7X128 inlined functions
-//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:23)
-//*
-//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
-//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
-//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
-//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
-//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
-//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
-//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
-//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
-//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
-//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
-//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
-//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
-//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
-//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
-//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
-//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
-//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
-//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
-//* ----------------------------------------------------------------------------
-
-#ifndef lib_AT91SAM7X128_H
-#define lib_AT91SAM7X128_H
-
-/* *****************************************************************************
-                SOFTWARE API FOR AIC
-   ***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AIC_ConfigureIt (
-	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
-	unsigned int irq_id,     // \arg interrupt number to initialize
-	unsigned int priority,   // \arg priority to give to the interrupt
-	unsigned int src_type,   // \arg activation and sense of activation
-	void (*newHandler) (void) ) // \arg address of the interrupt handler
-{
-	unsigned int oldHandler;
-    unsigned int mask ;
-
-    oldHandler = pAic->AIC_SVR[irq_id];
-
-    mask = 0x1 << irq_id ;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Save the interrupt handler routine pointer and the interrupt priority
-    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
-    //* Store the Source Mode Register
-    pAic->AIC_SMR[irq_id] = src_type | priority  ;
-    //* Clear the interrupt on the interrupt controller
-    pAic->AIC_ICCR = mask ;
-
-	return oldHandler;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_EnableIt
-//* \brief Enable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_EnableIt (
-	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-	unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    //* Enable the interrupt on the interrupt controller
-    pAic->AIC_IECR = 0x1 << irq_id ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_DisableIt
-//* \brief Disable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_DisableIt (
-	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-	unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    unsigned int mask = 0x1 << irq_id;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = mask ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ClearIt
-//* \brief Clear corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_ClearIt (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg interrupt number to initialize
-{
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = (0x1 << irq_id);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_AcknowledgeIt
-//* \brief Acknowledge corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_AcknowledgeIt (
-	AT91PS_AIC pAic)     // \arg pointer to the AIC registers
-{
-    pAic->AIC_EOICR = pAic->AIC_EOICR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_SetExceptionVector
-//* \brief Configure vector handler
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_SetExceptionVector (
-	unsigned int *pVector, // \arg pointer to the AIC registers
-	void (*Handler) () )   // \arg Interrupt Handler
-{
-	unsigned int oldVector = *pVector;
-
-	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
-		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
-	else
-		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
-
-	return oldVector;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Trig
-//* \brief Trig an IT
-//*----------------------------------------------------------------------------
-__inline void  AT91F_AIC_Trig (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg interrupt number
-{
-	pAic->AIC_ISCR = (0x1 << irq_id) ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsActive
-//* \brief Test if an IT is active
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsActive (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg Interrupt Number
-{
-	return (pAic->AIC_ISR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsPending
-//* \brief Test if an IT is pending
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsPending (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg Interrupt Number
-{
-	return (pAic->AIC_IPR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Open
-//* \brief Set exception vectors and AIC registers to default values
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_Open(
-	AT91PS_AIC pAic,        // \arg pointer to the AIC registers
-	void (*IrqHandler) (),  // \arg Default IRQ vector exception
-	void (*FiqHandler) (),  // \arg Default FIQ vector exception
-	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
-	void (*SpuriousHandler) (), // \arg Default Spurious Handler
-	unsigned int protectMode)   // \arg Debug Control Register
-{
-	int i;
-
-	// Disable all interrupts and set IVR to the default handler
-	for (i = 0; i < 32; ++i) {
-		AT91F_AIC_DisableIt(pAic, i);
-		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
-	}
-
-	// Set the IRQ exception vector
-	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
-	// Set the Fast Interrupt exception vector
-	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
-
-	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
-	pAic->AIC_DCR = protectMode;
-}
-/* *****************************************************************************
-                SOFTWARE API FOR PDC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextRx
-//* \brief Set the next receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextRx (
-	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
-	char *address,       // \arg address to the next bloc to be received
-	unsigned int bytes)  // \arg number of bytes to be received
-{
-	pPDC->PDC_RNPR = (unsigned int) address;
-	pPDC->PDC_RNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextTx
-//* \brief Set the next transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextTx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be transmitted
-	unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-	pPDC->PDC_TNPR = (unsigned int) address;
-	pPDC->PDC_TNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetRx
-//* \brief Set the receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetRx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be received
-	unsigned int bytes)    // \arg number of bytes to be received
-{
-	pPDC->PDC_RPR = (unsigned int) address;
-	pPDC->PDC_RCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetTx
-//* \brief Set the transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetTx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be transmitted
-	unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-	pPDC->PDC_TPR = (unsigned int) address;
-	pPDC->PDC_TCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableTx
-//* \brief Enable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableTx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableRx
-//* \brief Enable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableRx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableTx
-//* \brief Disable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableTx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableRx
-//* \brief Disable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableRx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsTxEmpty
-//* \brief Test if the current transfer descriptor has been sent
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_TCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextTxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_TNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsRxEmpty
-//* \brief Test if the current transfer descriptor has been filled
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_RCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextRxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_RNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Open
-//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Open (
-	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-	AT91F_PDC_DisableRx(pPDC);
-	AT91F_PDC_DisableTx(pPDC);
-
-	//* Reset all Counter register Next buffer first
-	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-    //* Enable the RX and TX PDC transfer requests
-	AT91F_PDC_EnableRx(pPDC);
-	AT91F_PDC_EnableTx(pPDC);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Close
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Close (
-	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-	AT91F_PDC_DisableRx(pPDC);
-	AT91F_PDC_DisableTx(pPDC);
-
-	//* Reset all Counter register Next buffer first
-	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SendFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_SendFrame(
-	AT91PS_PDC pPDC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	if (AT91F_PDC_IsTxEmpty(pPDC)) {
-		//* Buffer and next buffer can be initialized
-		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
-		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
-		return 2;
-	}
-	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
-		//* Only one buffer can be initialized
-		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
-		return 1;
-	}
-	else {
-		//* All buffer are in use...
-		return 0;
-	}
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_ReceiveFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_ReceiveFrame (
-	AT91PS_PDC pPDC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	if (AT91F_PDC_IsRxEmpty(pPDC)) {
-		//* Buffer and next buffer can be initialized
-		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
-		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
-		return 2;
-	}
-	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
-		//* Only one buffer can be initialized
-		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
-		return 1;
-	}
-	else {
-		//* All buffer are in use...
-		return 0;
-	}
-}
-/* *****************************************************************************
-                SOFTWARE API FOR DBGU
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptEnable
-//* \brief Enable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptEnable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be enabled
-{
-        pDbgu->DBGU_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptDisable
-//* \brief Disable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptDisable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be disabled
-{
-        pDbgu->DBGU_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_GetInterruptMaskStatus
-//* \brief Return DBGU Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
-        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
-{
-        return pDbgu->DBGU_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_IsInterruptMasked
-//* \brief Test if DBGU Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_DBGU_IsInterruptMasked(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PIO
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPeriph
-//* \brief Enable pins to be drived by peripheral
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPeriph(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int periphAEnable,  // \arg PERIPH A to enable
-	unsigned int periphBEnable)  // \arg PERIPH B to enable
-
-{
-	pPio->PIO_ASR = periphAEnable;
-	pPio->PIO_BSR = periphBEnable;
-	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOutput
-//* \brief Enable PIO in output mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOutput(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int pioEnable)      // \arg PIO to be enabled
-{
-	pPio->PIO_PER = pioEnable; // Set in PIO mode
-	pPio->PIO_OER = pioEnable; // Configure in Output
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInput
-//* \brief Enable PIO in input mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInput(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int inputEnable)      // \arg PIO to be enabled
-{
-	// Disable output
-	pPio->PIO_ODR  = inputEnable;
-	pPio->PIO_PER  = inputEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOpendrain
-//* \brief Configure PIO in open drain
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOpendrain(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int multiDrvEnable) // \arg pio to be configured in open drain
-{
-	// Configure the multi-drive option
-	pPio->PIO_MDDR = ~multiDrvEnable;
-	pPio->PIO_MDER = multiDrvEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPullup
-//* \brief Enable pullup on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPullup(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int pullupEnable)   // \arg enable pullup on PIO
-{
-		// Connect or not Pullup
-	pPio->PIO_PPUDR = ~pullupEnable;
-	pPio->PIO_PPUER = pullupEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgDirectDrive
-//* \brief Enable direct drive on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgDirectDrive(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int directDrive)    // \arg PIO to be configured with direct drive
-
-{
-	// Configure the Direct Drive
-	pPio->PIO_OWDR  = ~directDrive;
-	pPio->PIO_OWER  = directDrive;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInputFilter
-//* \brief Enable input filter on input PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInputFilter(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int inputFilter)    // \arg PIO to be configured with input filter
-
-{
-	// Configure the Direct Drive
-	pPio->PIO_IFDR  = ~inputFilter;
-	pPio->PIO_IFER  = inputFilter;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInput
-//* \brief Return PIO input value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
-	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-	return pPio->PIO_PDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputSet
-//* \brief Test if PIO is input flag is active
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputSet(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PIO_GetInput(pPio) & flag);
-}
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_SetOutput
-//* \brief Set to 1 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_SetOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be set
-{
-	pPio->PIO_SODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ClearOutput
-//* \brief Set to 0 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ClearOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be cleared
-{
-	pPio->PIO_CODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ForceOutput
-//* \brief Force output when Direct drive option is enabled
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ForceOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be forced
-{
-	pPio->PIO_ODSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Enable
-//* \brief Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Enable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled 
-{
-        pPio->PIO_PER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Disable
-//* \brief Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Disable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled 
-{
-        pPio->PIO_PDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetStatus
-//* \brief Return PIO Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsSet
-//* \brief Test if PIO is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputEnable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be enabled
-{
-        pPio->PIO_OER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputDisable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be disabled
-{
-        pPio->PIO_ODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputStatus
-//* \brief Return PIO Output Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOuputSet
-//* \brief Test if PIO Output is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterEnable
-//* \brief Input Filter Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be enabled
-{
-        pPio->PIO_IFER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterDisable
-//* \brief Input Filter Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be disabled
-{
-        pPio->PIO_IFDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInputFilterStatus
-//* \brief Return PIO Input Filter Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IFSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputFilterSet
-//* \brief Test if PIO Input filter is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputFilterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputDataStatus
-//* \brief Return PIO Output Data Status 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status 
-	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ODSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptEnable
-//* \brief Enable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be enabled
-{
-        pPio->PIO_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptDisable
-//* \brief Disable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be disabled
-{
-        pPio->PIO_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptMaskStatus
-//* \brief Return PIO Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptMasked
-//* \brief Test if PIO Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptMasked(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptSet
-//* \brief Test if PIO Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverEnable
-//* \brief Multi Driver Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
-{
-        pPio->PIO_MDER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverDisable
-//* \brief Multi Driver Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
-{
-        pPio->PIO_MDDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetMultiDriverStatus
-//* \brief Return PIO Multi Driver Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_MDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsMultiDriverSet
-//* \brief Test if PIO MultiDriver is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsMultiDriverSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_A_RegisterSelection
-//* \brief PIO A Register Selection 
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_A_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio A register selection
-{
-        pPio->PIO_ASR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_B_RegisterSelection
-//* \brief PIO B Register Selection 
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_B_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio B register selection 
-{
-        pPio->PIO_BSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Get_AB_RegisterStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ABSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsAB_RegisterSet
-//* \brief Test if PIO AB Register is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsAB_RegisterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteEnable
-//* \brief Output Write Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be enabled
-{
-        pPio->PIO_OWER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteDisable
-//* \brief Output Write Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be disabled
-{
-        pPio->PIO_OWDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputWriteStatus
-//* \brief Return PIO Output Write Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OWSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputWriteSet
-//* \brief Test if PIO OutputWrite is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputWriteSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetCfgPullup
-//* \brief Return PIO Configuration Pullup
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup 
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PPUSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputDataStatusSet
-//* \brief Test if PIO Output Data Status is Set 
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputDataStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsCfgPullupStatusSet
-//* \brief Test if PIO Configuration Pullup Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsCfgPullupStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkEnableReg
-//* \brief Configure the System Clock Enable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkEnableReg (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int mode)
-{
-	//* Write to the SCER register
-	pPMC->PMC_SCER = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkDisableReg
-//* \brief Configure the System Clock Disable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkDisableReg (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int mode)
-{
-	//* Write to the SCDR register
-	pPMC->PMC_SCDR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetSysClkStatusReg
-//* \brief Return the System Clock Status Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
-	AT91PS_PMC pPMC // pointer to a CAN controller
-	)
-{
-	return pPMC->PMC_SCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePeriphClock
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePeriphClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-	pPMC->PMC_PCER = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePeriphClock
-//* \brief Disable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePeriphClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-	pPMC->PMC_PCDR = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetPeriphClock
-//* \brief Get peripheral clock status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetPeriphClock (
-	AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-	return pPMC->PMC_PCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscillatorReg (
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int mode)
-{
-	pCKGR->CKGR_MOR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	return pCKGR->CKGR_MOR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_EnableMainOscillator
-//* \brief Enable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_EnableMainOscillator(
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_DisableMainOscillator
-//* \brief Disable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_DisableMainOscillator (
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
-//* \brief Cfg MOR Register according to the main osc startup time
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscStartUpTime (
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
-	pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClockFreqReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	return pCKGR->CKGR_MCFR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClock
-//* \brief Return Main clock in Hz
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClock (
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgMCKReg
-//* \brief Cfg Master Clock Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgMCKReg (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int mode)
-{
-	pPMC->PMC_MCKR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMCKReg
-//* \brief Return Master Clock Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMCKReg(
-	AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-	return pPMC->PMC_MCKR;
-}
-
-//*------------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMasterClock
-//* \brief Return master clock in Hz which correponds to processor clock for ARM7
-//*------------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMasterClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	unsigned int reg = pPMC->PMC_MCKR;
-	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
-	unsigned int pllDivider, pllMultiplier;
-
-	switch (reg & AT91C_PMC_CSS) {
-		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
-			return slowClock / prescaler;
-		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
-			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
-		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
-			reg = pCKGR->CKGR_PLLR;
-			pllDivider    = (reg  & AT91C_CKGR_DIV);
-			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
-			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
-	}
-	return 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePCK (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
-	unsigned int mode)
-{
-	pPMC->PMC_PCKR[pck] = mode;
-	pPMC->PMC_SCER = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePCK (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
-{
-	pPMC->PMC_SCDR = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnableIt
-//* \brief Enable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnableIt (
-	AT91PS_PMC pPMC,     // pointer to a PMC controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pPMC->PMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisableIt
-//* \brief Disable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisableIt (
-	AT91PS_PMC pPMC, // pointer to a PMC controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pPMC->PMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetStatus
-//* \brief Return PMC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
-	AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-	return pPMC->PMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetInterruptMaskStatus
-//* \brief Return PMC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
-	AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-	return pPMC->PMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsInterruptMasked
-//* \brief Test if PMC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsInterruptMasked(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsStatusSet
-//* \brief Test if PMC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsStatusSet(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PMC_GetStatus(pPMC) & flag);
-}/* *****************************************************************************
-                SOFTWARE API FOR RSTC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTSoftReset
-//* \brief Start Software Reset
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSoftReset(
-        AT91PS_RSTC pRSTC,
-        unsigned int reset)
-{
-	pRSTC->RSTC_RCR = (0xA5000000 | reset);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTSetMode
-//* \brief Set Reset Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSetMode(
-        AT91PS_RSTC pRSTC,
-        unsigned int mode)
-{
-	pRSTC->RSTC_RMR = (0xA5000000 | mode);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTGetMode
-//* \brief Get Reset Mode
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetMode(
-        AT91PS_RSTC pRSTC)
-{
-	return (pRSTC->RSTC_RMR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTGetStatus
-//* \brief Get Reset Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetStatus(
-        AT91PS_RSTC pRSTC)
-{
-	return (pRSTC->RSTC_RSR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTIsSoftRstActive
-//* \brief Return !=0 if software reset is still not completed
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTIsSoftRstActive(
-        AT91PS_RSTC pRSTC)
-{
-	return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR RTTC
-   ***************************************************************************** */
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_SetRTT_TimeBase()
-//* \brief  Set the RTT prescaler according to the TimeBase in ms
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetTimeBase(
-        AT91PS_RTTC pRTTC, 
-        unsigned int ms)
-{
-	if (ms > 2000)
-		return 1;   // AT91C_TIME_OUT_OF_RANGE
-	pRTTC->RTTC_RTMR &= ~0xFFFF;	
-	pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);	
-	return 0;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTSetPrescaler()
-//* \brief  Set the new prescaler value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetPrescaler(
-        AT91PS_RTTC pRTTC, 
-        unsigned int rtpres)
-{
-	pRTTC->RTTC_RTMR &= ~0xFFFF;	
-	pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);	
-	return (pRTTC->RTTC_RTMR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTRestart()
-//* \brief  Restart the RTT prescaler
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTRestart(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;	
-}
-
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetAlarmINT()
-//* \brief  Enable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmINT(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ClearAlarmINT()
-//* \brief  Disable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearAlarmINT(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetRttIncINT()
-//* \brief  Enable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetRttIncINT(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ClearRttIncINT()
-//* \brief  Disable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearRttIncINT(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetAlarmValue()
-//* \brief  Set RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmValue(
-        AT91PS_RTTC pRTTC, unsigned int alarm)
-{
-	pRTTC->RTTC_RTAR = alarm;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_GetAlarmValue()
-//* \brief  Get RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetAlarmValue(
-        AT91PS_RTTC pRTTC)
-{
-	return(pRTTC->RTTC_RTAR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTGetStatus()
-//* \brief  Read the RTT status
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetStatus(
-        AT91PS_RTTC pRTTC)
-{
-	return(pRTTC->RTTC_RTSR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ReadValue()
-//* \brief  Read the RTT value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTReadValue(
-        AT91PS_RTTC pRTTC)
-{
-        register volatile unsigned int val1,val2;
-	do
-	{
-		val1 = pRTTC->RTTC_RTVR;
-		val2 = pRTTC->RTTC_RTVR;
-	}	
-	while(val1 != val2);
-	return(val1);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR PITC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITInit
-//* \brief System timer init : period in µsecond, system clock freq in MHz
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITInit(
-        AT91PS_PITC pPITC,
-        unsigned int period,
-        unsigned int pit_frequency)
-{
-	pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
-	pPITC->PITC_PIMR |= AT91C_PITC_PITEN;	 
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITSetPIV
-//* \brief Set the PIT Periodic Interval Value 
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITSetPIV(
-        AT91PS_PITC pPITC,
-        unsigned int piv)
-{
-	pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITEnableInt
-//* \brief Enable PIT periodic interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITEnableInt(
-        AT91PS_PITC pPITC)
-{
-	pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;	 
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITDisableInt
-//* \brief Disable PIT periodic interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITDisableInt(
-        AT91PS_PITC pPITC)
-{
-	pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;	 
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITGetMode
-//* \brief Read PIT mode register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetMode(
-        AT91PS_PITC pPITC)
-{
-	return(pPITC->PITC_PIMR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITGetStatus
-//* \brief Read PIT status register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetStatus(
-        AT91PS_PITC pPITC)
-{
-	return(pPITC->PITC_PISR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITGetPIIR
-//* \brief Read PIT CPIV and PICNT without ressetting the counters
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetPIIR(
-        AT91PS_PITC pPITC)
-{
-	return(pPITC->PITC_PIIR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITGetPIVR
-//* \brief Read System timer CPIV and PICNT without ressetting the counters
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetPIVR(
-        AT91PS_PITC pPITC)
-{
-	return(pPITC->PITC_PIVR);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR WDTC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTSetMode
-//* \brief Set Watchdog Mode Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_WDTSetMode(
-        AT91PS_WDTC pWDTC,
-        unsigned int Mode)
-{
-	pWDTC->WDTC_WDMR = Mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTRestart
-//* \brief Restart Watchdog
-//*----------------------------------------------------------------------------
-__inline void AT91F_WDTRestart(
-        AT91PS_WDTC pWDTC)
-{
-	pWDTC->WDTC_WDCR = 0xA5000001;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTSGettatus
-//* \brief Get Watchdog Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_WDTSGettatus(
-        AT91PS_WDTC pWDTC)
-{
-	return(pWDTC->WDTC_WDSR & 0x3);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTGetPeriod
-//* \brief Translate ms into Watchdog Compatible value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
-{
-	if ((ms < 4) || (ms > 16000))
-		return 0;
-	return((ms << 8) / 1000);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR VREG
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_VREG_Enable_LowPowerMode
-//* \brief Enable VREG Low Power Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_VREG_Enable_LowPowerMode(
-        AT91PS_VREG pVREG)
-{
-	pVREG->VREG_MR |= AT91C_VREG_PSTDBY;	 
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_VREG_Disable_LowPowerMode
-//* \brief Disable VREG Low Power Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_VREG_Disable_LowPowerMode(
-        AT91PS_VREG pVREG)
-{
-	pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;	 
-}/* *****************************************************************************
-                SOFTWARE API FOR MC
-   ***************************************************************************** */
-
-#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_Remap
-//* \brief Make Remap
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_Remap (void)     //  
-{
-    AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
-    
-    pMC->MC_RCR = AT91C_MC_RCB;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_CfgModeReg
-//* \brief Configure the EFC Mode Register of the MC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_EFC_CfgModeReg (
-	AT91PS_MC pMC, // pointer to a MC controller
-	unsigned int mode)        // mode register 
-{
-	// Write to the FMR register
-	pMC->MC_FMR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_GetModeReg
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_GetModeReg(
-	AT91PS_MC pMC) // pointer to a MC controller
-{
-	return pMC->MC_FMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_ComputeFMCN
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
-	int master_clock) // master clock in Hz
-{
-	return (master_clock/1000000 +2);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_PerformCmd
-//* \brief Perform EFC Command
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_EFC_PerformCmd (
-	AT91PS_MC pMC, // pointer to a MC controller
-    unsigned int transfer_cmd)
-{
-	pMC->MC_FCR = transfer_cmd;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_GetStatus
-//* \brief Return MC EFC Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_GetStatus(
-	AT91PS_MC pMC) // pointer to a MC controller
-{
-	return pMC->MC_FSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_IsInterruptMasked
-//* \brief Test if EFC MC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
-        AT91PS_MC pMC,   // \arg  pointer to a MC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_IsInterruptSet
-//* \brief Test if EFC MC Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
-        AT91PS_MC pMC,   // \arg  pointer to a MC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_MC_EFC_GetStatus(pMC) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR SPI
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Open
-//* \brief Open a SPI Port
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_Open (
-        const unsigned int null)  // \arg
-{
-        /* NOT DEFINED AT THIS MOMENT */
-        return ( 0 );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgCs
-//* \brief Configure SPI chip select register
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgCs (
-	AT91PS_SPI pSPI,     // pointer to a SPI controller
-	int cs,     // SPI cs number (0 to 3)
- 	int val)   //  chip select register
-{
-	//* Write to the CSR register
-	*(pSPI->SPI_CSR + cs) = val;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_EnableIt
-//* \brief Enable SPI interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_EnableIt (
-	AT91PS_SPI pSPI,     // pointer to a SPI controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pSPI->SPI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_DisableIt
-//* \brief Disable SPI interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_DisableIt (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pSPI->SPI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Reset
-//* \brief Reset the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Reset (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SWRST;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Enable
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Enable (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Disable
-//* \brief Disable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Disable (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgMode
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgMode (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	int mode)        // mode register 
-{
-	//* Write to the MR register
-	pSPI->SPI_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgPCS
-//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgPCS (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	char PCS_Device) // PCS of the Device
-{	
- 	//* Write to the MR register
-	pSPI->SPI_MR &= 0xFFF0FFFF;
-	pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_ReceiveFrame (
-	AT91PS_SPI pSPI,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pSPI->SPI_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_SendFrame(
-	AT91PS_SPI pSPI,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pSPI->SPI_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Close
-//* \brief Close SPI: disable IT disable transfert, close PDC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Close (
-	AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
-{
-    //* Reset all the Chip Select register
-    pSPI->SPI_CSR[0] = 0 ;
-    pSPI->SPI_CSR[1] = 0 ;
-    pSPI->SPI_CSR[2] = 0 ;
-    pSPI->SPI_CSR[3] = 0 ;
-
-    //* Reset the SPI mode
-    pSPI->SPI_MR = 0  ;
-
-    //* Disable all interrupts
-    pSPI->SPI_IDR = 0xFFFFFFFF ;
-
-    //* Abort the Peripheral Data Transfers
-    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
-
-    //* Disable receiver and transmitter and stop any activity immediately
-    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_PutChar (
-	AT91PS_SPI pSPI,
-	unsigned int character,
-             unsigned int cs_number )
-{
-    unsigned int value_for_cs;
-    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
-    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-__inline int AT91F_SPI_GetChar (
-	const AT91PS_SPI pSPI)
-{
-    return((pSPI->SPI_RDR) & 0xFFFF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_GetInterruptMaskStatus
-//* \brief Return SPI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
-        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
-{
-        return pSpi->SPI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_IsInterruptMasked
-//* \brief Test if SPI Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_SPI_IsInterruptMasked(
-        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR USART
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Baudrate
-//* \brief Calculate the baudrate
-//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
-                        AT91C_US_NBSTOP_1_BIT + \
-                        AT91C_US_PAR_NONE + \
-                        AT91C_US_CHRL_8_BITS + \
-                        AT91C_US_CLKS_CLOCK )
-
-//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
-                            AT91C_US_NBSTOP_1_BIT + \
-                            AT91C_US_PAR_NONE + \
-                            AT91C_US_CHRL_8_BITS + \
-                            AT91C_US_CLKS_EXT )
-
-//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
-                       AT91C_US_USMODE_NORMAL + \
-                       AT91C_US_NBSTOP_1_BIT + \
-                       AT91C_US_PAR_NONE + \
-                       AT91C_US_CHRL_8_BITS + \
-                       AT91C_US_CLKS_CLOCK )
-
-//* SCK used Label
-#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
-
-//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
-#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
-					   		 AT91C_US_CLKS_CLOCK +\
-                       		 AT91C_US_NBSTOP_1_BIT + \
-                       		 AT91C_US_PAR_EVEN + \
-                       		 AT91C_US_CHRL_8_BITS + \
-                       		 AT91C_US_CKLO +\
-                       		 AT91C_US_OVER)
-
-//* Standard IRDA mode
-#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
-                            AT91C_US_NBSTOP_1_BIT + \
-                            AT91C_US_PAR_NONE + \
-                            AT91C_US_CHRL_8_BITS + \
-                            AT91C_US_CLKS_CLOCK )
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Baudrate
-//* \brief Caluculate baud_value according to the main clock and the baud rate
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_Baudrate (
-	const unsigned int main_clock, // \arg peripheral clock
-	const unsigned int baud_rate)  // \arg UART baudrate
-{
-	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
-	if ((baud_value % 10) >= 5)
-		baud_value = (baud_value / 10) + 1;
-	else
-		baud_value /= 10;
-	return baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetBaudrate (
-	AT91PS_USART pUSART,    // \arg pointer to a USART controller
-	unsigned int mainClock, // \arg peripheral clock
-	unsigned int speed)     // \arg UART baudrate
-{
-	//* Define the baud rate divisor register
-	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetTimeguard
-//* \brief Set USART timeguard
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetTimeguard (
-	AT91PS_USART pUSART,    // \arg pointer to a USART controller
-	unsigned int timeguard) // \arg timeguard value
-{
-	//* Write the Timeguard Register
-	pUSART->US_TTGR = timeguard ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableIt
-//* \brief Enable USART IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableIt (
-	AT91PS_USART pUSART, // \arg pointer to a USART controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pUSART->US_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableIt
-//* \brief Disable USART IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableIt (
-	AT91PS_USART pUSART, // \arg pointer to a USART controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IER register
-	pUSART->US_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Configure
-//* \brief Configure USART
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_Configure (
-	AT91PS_USART pUSART,     // \arg pointer to a USART controller
-	unsigned int mainClock,  // \arg peripheral clock
-	unsigned int mode ,      // \arg mode Register to be programmed
-	unsigned int baudRate ,  // \arg baudrate to be programmed
-	unsigned int timeguard ) // \arg timeguard to be programmed
-{
-    //* Disable interrupts
-    pUSART->US_IDR = (unsigned int) -1;
-
-    //* Reset receiver and transmitter
-    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
-
-	//* Define the baud rate divisor register
-	AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
-
-	//* Write the Timeguard Register
-	AT91F_US_SetTimeguard(pUSART, timeguard);
-
-    //* Clear Transmit and Receive Counters
-    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
-
-    //* Define the USART mode
-    pUSART->US_MR = mode  ;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableRx
-//* \brief Enable receiving characters
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Enable receiver
-    pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableTx
-//* \brief Enable sending characters
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Enable  transmitter
-    pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ResetRx
-//* \brief Reset Receiver and re-enable it
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_ResetRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-	//* Reset receiver
-	pUSART->US_CR = AT91C_US_RSTRX;
-    //* Re-Enable receiver
-    pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ResetTx
-//* \brief Reset Transmitter and re-enable it
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_ResetTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-	//* Reset transmitter
-	pUSART->US_CR = AT91C_US_RSTTX;
-    //* Enable transmitter
-    pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableRx
-//* \brief Disable Receiver
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Disable receiver
-    pUSART->US_CR = AT91C_US_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableTx
-//* \brief Disable Transmitter
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Disable transmitter
-    pUSART->US_CR = AT91C_US_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Close
-//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_Close (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Reset the baud rate divisor register
-    pUSART->US_BRGR = 0 ;
-
-    //* Reset the USART mode
-    pUSART->US_MR = 0  ;
-
-    //* Reset the Timeguard Register
-    pUSART->US_TTGR = 0;
-
-    //* Disable all interrupts
-    pUSART->US_IDR = 0xFFFFFFFF ;
-
-    //* Abort the Peripheral Data Transfers
-    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
-
-    //* Disable receiver and transmitter and stop any activity immediately
-    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_TxReady
-//* \brief Return 1 if a character can be written in US_THR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_TxReady (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR & AT91C_US_TXRDY);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_RxReady
-//* \brief Return 1 if a character can be read in US_RHR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_RxReady (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR & AT91C_US_RXRDY);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Error
-//* \brief Return the error flag
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_Error (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR &
-    	(AT91C_US_OVRE |  // Overrun error
-    	 AT91C_US_FRAME | // Framing error
-    	 AT91C_US_PARE));  // Parity error
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_PutChar (
-	AT91PS_USART pUSART,
-	int character )
-{
-    pUSART->US_THR = (character & 0x1FF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-__inline int AT91F_US_GetChar (
-	const AT91PS_USART pUSART)
-{
-    return((pUSART->US_RHR) & 0x1FF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_SendFrame(
-	AT91PS_USART pUSART,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pUSART->US_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_ReceiveFrame (
-	AT91PS_USART pUSART,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pUSART->US_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetIrdaFilter
-//* \brief Set the value of IrDa filter tregister
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetIrdaFilter (
-	AT91PS_USART pUSART,
-	unsigned char value
-)
-{
-	pUSART->US_IF = value;
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR SSC
-   ***************************************************************************** */
-//* Define the standard I2S mode configuration
-
-//* Configuration to set in the SSC Transmit Clock Mode Register
-//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
-//* 			  nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
-									   AT91C_SSC_CKS_DIV   +\
-                            		   AT91C_SSC_CKO_CONTINOUS      +\
-                            		   AT91C_SSC_CKG_NONE    +\
-                                       AT91C_SSC_START_FALL_RF +\
-                           			   AT91C_SSC_STTOUT  +\
-                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
-                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
-
-
-//* Configuration to set in the SSC Transmit Frame Mode Register
-//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
-//* 			 nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
-									(nb_bit_by_slot-1)  +\
-                            		AT91C_SSC_MSBF   +\
-                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
-                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
-                            		AT91C_SSC_FSOS_NEGATIVE)
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_SetBaudrate (
-        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
-        unsigned int mainClock, // \arg peripheral clock
-        unsigned int speed)     // \arg SSC baudrate
-{
-        unsigned int baud_value;
-        //* Define the baud rate divisor register
-        if (speed == 0)
-           baud_value = 0;
-        else
-        {
-           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
-           if ((baud_value % 10) >= 5)
-                  baud_value = (baud_value / 10) + 1;
-           else
-                  baud_value /= 10;
-        }
-
-        pSSC->SSC_CMR = baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_Configure
-//* \brief Configure SSC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_Configure (
-             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
-             unsigned int syst_clock,  // \arg System Clock Frequency
-             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
-             unsigned int clock_rx,    // \arg Receiver Clock Parameters
-             unsigned int mode_rx,     // \arg mode Register to be programmed
-             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
-             unsigned int mode_tx)     // \arg mode Register to be programmed
-{
-    //* Disable interrupts
-	pSSC->SSC_IDR = (unsigned int) -1;
-
-    //* Reset receiver and transmitter
-	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
-
-    //* Define the Clock Mode Register
-	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
-
-     //* Write the Receive Clock Mode Register
-	pSSC->SSC_RCMR =  clock_rx;
-
-     //* Write the Transmit Clock Mode Register
-	pSSC->SSC_TCMR =  clock_tx;
-
-     //* Write the Receive Frame Mode Register
-	pSSC->SSC_RFMR =  mode_rx;
-
-     //* Write the Transmit Frame Mode Register
-	pSSC->SSC_TFMR =  mode_tx;
-
-    //* Clear Transmit and Receive Counters
-	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
-
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableRx
-//* \brief Enable receiving datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableRx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Enable receiver
-    pSSC->SSC_CR = AT91C_SSC_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableRx
-//* \brief Disable receiving datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableRx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Disable receiver
-    pSSC->SSC_CR = AT91C_SSC_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableTx
-//* \brief Enable sending datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableTx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Enable  transmitter
-    pSSC->SSC_CR = AT91C_SSC_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableTx
-//* \brief Disable sending datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableTx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Disable  transmitter
-    pSSC->SSC_CR = AT91C_SSC_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableIt
-//* \brief Enable SSC IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableIt (
-	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pSSC->SSC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableIt
-//* \brief Disable SSC IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableIt (
-	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pSSC->SSC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_ReceiveFrame (
-	AT91PS_SSC pSSC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pSSC->SSC_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_SendFrame(
-	AT91PS_SSC pSSC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pSSC->SSC_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_GetInterruptMaskStatus
-//* \brief Return SSC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
-        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
-{
-        return pSsc->SSC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_IsInterruptMasked
-//* \brief Test if SSC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_SSC_IsInterruptMasked(
-        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR TWI
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_EnableIt
-//* \brief Enable TWI IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_EnableIt (
-	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pTWI->TWI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_DisableIt
-//* \brief Disable TWI IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_DisableIt (
-	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pTWI->TWI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_Configure
-//* \brief Configure TWI in master mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
-{
-    //* Disable interrupts
-	pTWI->TWI_IDR = (unsigned int) -1;
-
-    //* Reset peripheral
-	pTWI->TWI_CR = AT91C_TWI_SWRST;
-
-	//* Set Master mode
-	pTWI->TWI_CR = AT91C_TWI_MSEN;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_GetInterruptMaskStatus
-//* \brief Return TWI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
-        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
-{
-        return pTwi->TWI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_IsInterruptMasked
-//* \brief Test if TWI Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_TWI_IsInterruptMasked(
-        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PWMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_GetStatus
-//* \brief Return PWM Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
-	AT91PS_PWMC pPWM) // pointer to a PWM controller
-{
-	return pPWM->PWMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_InterruptEnable
-//* \brief Enable PWM Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_InterruptEnable(
-        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  PWM interrupt to be enabled
-{
-        pPwm->PWMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_InterruptDisable
-//* \brief Disable PWM Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_InterruptDisable(
-        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  PWM interrupt to be disabled
-{
-        pPwm->PWMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_GetInterruptMaskStatus
-//* \brief Return PWM Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
-        AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
-{
-        return pPwm->PWMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_IsInterruptMasked
-//* \brief Test if PWM Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_IsInterruptMasked(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_IsStatusSet
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_IsStatusSet(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PWMC_GetStatus(pPWM) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_CfgChannel
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CfgChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int channelId, // \arg PWM channel ID
-        unsigned int mode, // \arg  PWM mode
-        unsigned int period, // \arg PWM period
-        unsigned int duty) // \arg PWM duty cycle
-{
-	pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
-	pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
-	pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_StartChannel
-//* \brief Enable channel
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_StartChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  Channels IDs to be enabled
-{
-	pPWM->PWMC_ENA = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_StopChannel
-//* \brief Disable channel
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_StopChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  Channels IDs to be enabled
-{
-	pPWM->PWMC_DIS = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_UpdateChannel
-//* \brief Update Period or Duty Cycle
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_UpdateChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int channelId, // \arg PWM channel ID
-        unsigned int update) // \arg  Channels IDs to be enabled
-{
-	pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR UDP
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EnableIt
-//* \brief Enable UDP IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EnableIt (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pUDP->UDP_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_DisableIt
-//* \brief Disable UDP IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_DisableIt (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pUDP->UDP_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_SetAddress
-//* \brief Set UDP functional address
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_SetAddress (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char address)   // \arg new UDP address
-{
-	pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EnableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EnableEp (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char endpoint)   // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_DisableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_DisableEp (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char endpoint)   // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_SetState
-//* \brief Set UDP Device state
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_SetState (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg new UDP address
-{
-	pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
-	pUDP->UDP_GLBSTATE  |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_GetState
-//* \brief return UDP Device state
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
-	AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
-{
-	return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_ResetEp
-//* \brief Reset UDP endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg Endpoints to be reset
-{
-	pUDP->UDP_RSTEP = flag;
-	pUDP->UDP_RSTEP = 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpStall
-//* \brief Endpoint will STALL requests
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpStall(
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char endpoint)   // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpWrite
-//* \brief Write value in the DPR
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpWrite(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned char value)     // \arg value to be written in the DPR
-{
-	pUDP->UDP_FDR[endpoint] = value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpRead
-//* \brief Return value from the DPR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_EpRead(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	return pUDP->UDP_FDR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpEndOfWr
-//* \brief Notify the UDP that values in DPR are ready to be sent
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpEndOfWr(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpClear
-//* \brief Clear flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpClear(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned int flag)       // \arg flag to be cleared
-{
-	pUDP->UDP_CSR[endpoint] &= ~(flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpSet
-//* \brief Set flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpSet(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned int flag)       // \arg flag to be cleared
-{
-	pUDP->UDP_CSR[endpoint] |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpStatus
-//* \brief Return the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_EpStatus(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	return pUDP->UDP_CSR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_GetInterruptMaskStatus
-//* \brief Return UDP Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
-        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
-{
-        return pUdp->UDP_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_IsInterruptMasked
-//* \brief Test if UDP Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_UDP_IsInterruptMasked(
-        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR TC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_InterruptEnable
-//* \brief Enable TC Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC_InterruptEnable(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  TC interrupt to be enabled
-{
-        pTc->TC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_InterruptDisable
-//* \brief Disable TC Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC_InterruptDisable(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  TC interrupt to be disabled
-{
-        pTc->TC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_GetInterruptMaskStatus
-//* \brief Return TC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
-        AT91PS_TC pTc) // \arg  pointer to a TC controller
-{
-        return pTc->TC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_IsInterruptMasked
-//* \brief Test if TC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline int AT91F_TC_IsInterruptMasked(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR CAN
-   ***************************************************************************** */
-#define	STANDARD_FORMAT 0
-#define	EXTENDED_FORMAT 1
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_InitMailboxRegisters()
-//* \brief Configure the corresponding mailbox
-//*----------------------------------------------------------------------------
-__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB	CAN_Mailbox,
-								int  			mode_reg,
-								int 			acceptance_mask_reg,
-								int  			id_reg,
-								int  			data_low_reg,
-								int  			data_high_reg,
-								int  			control_reg)
-{
-	CAN_Mailbox->CAN_MB_MCR 	= 0x0;
-	CAN_Mailbox->CAN_MB_MMR 	= mode_reg;
-	CAN_Mailbox->CAN_MB_MAM 	= acceptance_mask_reg;
-	CAN_Mailbox->CAN_MB_MID 	= id_reg;
-	CAN_Mailbox->CAN_MB_MDL 	= data_low_reg; 		
-	CAN_Mailbox->CAN_MB_MDH 	= data_high_reg;
-	CAN_Mailbox->CAN_MB_MCR 	= control_reg;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_EnableCAN()
-//* \brief 
-//*----------------------------------------------------------------------------
-__inline void AT91F_EnableCAN(
-	AT91PS_CAN pCAN)     // pointer to a CAN controller
-{
-	pCAN->CAN_MR |= AT91C_CAN_CANEN;
-
-	// Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
-	while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DisableCAN()
-//* \brief 
-//*----------------------------------------------------------------------------
-__inline void AT91F_DisableCAN(
-	AT91PS_CAN pCAN)     // pointer to a CAN controller
-{
-	pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_EnableIt
-//* \brief Enable CAN interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_EnableIt (
-	AT91PS_CAN pCAN,     // pointer to a CAN controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pCAN->CAN_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_DisableIt
-//* \brief Disable CAN interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_DisableIt (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pCAN->CAN_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetStatus
-//* \brief Return CAN Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
-	AT91PS_CAN pCAN) // pointer to a CAN controller
-{
-	return pCAN->CAN_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetInterruptMaskStatus
-//* \brief Return CAN Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
-	AT91PS_CAN pCAN) // pointer to a CAN controller
-{
-	return pCAN->CAN_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_IsInterruptMasked
-//* \brief Test if CAN Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_IsInterruptMasked(
-        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_IsStatusSet
-//* \brief Test if CAN Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_IsStatusSet(
-        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_CAN_GetStatus(pCAN) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgModeReg
-//* \brief Configure the Mode Register of the CAN controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgModeReg (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-	unsigned int mode)        // mode register 
-{
-	//* Write to the MR register
-	pCAN->CAN_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetModeReg
-//* \brief Return the Mode Register of the CAN controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetModeReg (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_MR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgBaudrateReg
-//* \brief Configure the Baudrate of the CAN controller for the network
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgBaudrateReg (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-	unsigned int baudrate_cfg)
-{
-	//* Write to the BR register
-	pCAN->CAN_BR = baudrate_cfg;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetBaudrate
-//* \brief Return the Baudrate of the CAN controller for the network value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetBaudrate (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_BR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetInternalCounter
-//* \brief Return CAN Timer Regsiter Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetInternalCounter (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_TIM;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetTimestamp
-//* \brief Return CAN Timestamp Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetTimestamp (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_TIMESTP;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetErrorCounter
-//* \brief Return CAN Error Counter Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetErrorCounter (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_ECR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_InitTransferRequest
-//* \brief Request for a transfer on the corresponding mailboxes
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_InitTransferRequest (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-    unsigned int transfer_cmd)
-{
-	pCAN->CAN_TCR = transfer_cmd;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_InitAbortRequest
-//* \brief Abort the corresponding mailboxes
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_InitAbortRequest (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-    unsigned int abort_cmd)
-{
-	pCAN->CAN_ACR = abort_cmd;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageModeReg
-//* \brief Program the Message Mode Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageModeReg (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int mode)
-{
-	CAN_Mailbox->CAN_MB_MMR = mode;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageModeReg
-//* \brief Return the Message Mode Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageModeReg (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MMR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageIDReg
-//* \brief Program the Message ID Register
-//* \brief Version == 0 for Standard messsage, Version == 1 for Extended  
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageIDReg (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int id,
-    unsigned char version)
-{
-	if(version==0)	// IDvA Standard Format
-		CAN_Mailbox->CAN_MB_MID = id<<18;
-	else	// IDvB Extended Format
-		CAN_Mailbox->CAN_MB_MID = id | (1<<29);	// set MIDE bit
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageIDReg
-//* \brief Return the Message ID Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageIDReg (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MID;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageAcceptanceMaskReg
-//* \brief Program the Message Acceptance Mask Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int mask)
-{
-	CAN_Mailbox->CAN_MB_MAM = mask;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageAcceptanceMaskReg
-//* \brief Return the Message Acceptance Mask Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MAM;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetFamilyID
-//* \brief Return the Message ID Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetFamilyID (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MFID;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageCtrl
-//* \brief Request and config for a transfer on the corresponding mailbox
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageCtrlReg (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int message_ctrl_cmd)
-{
-	CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageStatus
-//* \brief Return CAN Mailbox Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageStatus (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MSR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageDataLow
-//* \brief Program data low value
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageDataLow (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int data)
-{
-	CAN_Mailbox->CAN_MB_MDL = data;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageDataLow
-//* \brief Return data low value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageDataLow (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MDL;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageDataHigh
-//* \brief Program data high value
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageDataHigh (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int data)
-{
-	CAN_Mailbox->CAN_MB_MDH = data;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageDataHigh
-//* \brief Return data high value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageDataHigh (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MDH;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_Open
-//* \brief Open a CAN Port
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_Open (
-        const unsigned int null)  // \arg
-{
-        /* NOT DEFINED AT THIS MOMENT */
-        return ( 0 );
-}
-/* *****************************************************************************
-                SOFTWARE API FOR ADC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_EnableIt
-//* \brief Enable ADC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_EnableIt (
-	AT91PS_ADC pADC,     // pointer to a ADC controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pADC->ADC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_DisableIt
-//* \brief Disable ADC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_DisableIt (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pADC->ADC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetStatus
-//* \brief Return ADC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
-	AT91PS_ADC pADC) // pointer to a ADC controller
-{
-	return pADC->ADC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetInterruptMaskStatus
-//* \brief Return ADC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
-	AT91PS_ADC pADC) // pointer to a ADC controller
-{
-	return pADC->ADC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_IsInterruptMasked
-//* \brief Test if ADC Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_IsInterruptMasked(
-        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_IsStatusSet
-//* \brief Test if ADC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_IsStatusSet(
-        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_ADC_GetStatus(pADC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgModeReg
-//* \brief Configure the Mode Register of the ADC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgModeReg (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int mode)        // mode register 
-{
-	//* Write to the MR register
-	pADC->ADC_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetModeReg
-//* \brief Return the Mode Register of the ADC controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetModeReg (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_MR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgTimings
-//* \brief Configure the different necessary timings of the ADC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgTimings (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int mck_clock, // in MHz 
-	unsigned int adc_clock, // in MHz 
-	unsigned int startup_time, // in us 
-	unsigned int sample_and_hold_time)	// in ns  
-{
-	unsigned int prescal,startup,shtim;
-	
-	prescal = mck_clock/(2*adc_clock) - 1;
-	startup = adc_clock*startup_time/8 - 1;
-	shtim = adc_clock*sample_and_hold_time/1000 - 1;
-	
-	//* Write to the MR register
-	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_EnableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_EnableChannel (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int channel)        // mode register 
-{
-	//* Write to the CHER register
-	pADC->ADC_CHER = channel;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_DisableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_DisableChannel (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int channel)        // mode register 
-{
-	//* Write to the CHDR register
-	pADC->ADC_CHDR = channel;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetChannelStatus
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetChannelStatus (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CHSR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_StartConversion
-//* \brief Software request for a analog to digital conversion 
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_StartConversion (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	pADC->ADC_CR = AT91C_ADC_START;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_SoftReset
-//* \brief Software reset
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_SoftReset (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	pADC->ADC_CR = AT91C_ADC_SWRST;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetLastConvertedData
-//* \brief Return the Last Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetLastConvertedData (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_LCDR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH0
-//* \brief Return the Channel 0 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR0;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH1
-//* \brief Return the Channel 1 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR1;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH2
-//* \brief Return the Channel 2 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR2;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH3
-//* \brief Return the Channel 3 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR3;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH4
-//* \brief Return the Channel 4 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR4;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH5
-//* \brief Return the Channel 5 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR5;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH6
-//* \brief Return the Channel 6 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR6;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH7
-//* \brief Return the Channel 7 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR7;	
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR AES
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_EnableIt
-//* \brief Enable AES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_EnableIt (
-	AT91PS_AES pAES,     // pointer to a AES controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pAES->AES_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_DisableIt
-//* \brief Disable AES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_DisableIt (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pAES->AES_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_GetStatus
-//* \brief Return AES Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
-	AT91PS_AES pAES) // pointer to a AES controller
-{
-	return pAES->AES_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_GetInterruptMaskStatus
-//* \brief Return AES Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
-	AT91PS_AES pAES) // pointer to a AES controller
-{
-	return pAES->AES_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_IsInterruptMasked
-//* \brief Test if AES Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_IsInterruptMasked(
-        AT91PS_AES pAES,   // \arg  pointer to a AES controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_IsStatusSet
-//* \brief Test if AES Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_IsStatusSet(
-        AT91PS_AES pAES,   // \arg  pointer to a AES controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_AES_GetStatus(pAES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_CfgModeReg
-//* \brief Configure the Mode Register of the AES controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_CfgModeReg (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned int mode)        // mode register 
-{
-	//* Write to the MR register
-	pAES->AES_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_GetModeReg
-//* \brief Return the Mode Register of the AES controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetModeReg (
-	AT91PS_AES pAES // pointer to a AES controller
-	)
-{
-	return pAES->AES_MR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_StartProcessing
-//* \brief Start Encryption or Decryption
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_StartProcessing (
-	AT91PS_AES pAES // pointer to a AES controller
-	)
-{
-	pAES->AES_CR = AT91C_AES_START;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_SoftReset
-//* \brief Reset AES
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_SoftReset (
-	AT91PS_AES pAES // pointer to a AES controller
-	)
-{
-	pAES->AES_CR = AT91C_AES_SWRST;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_LoadNewSeed
-//* \brief Load New Seed in the random number generator
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_LoadNewSeed (
-	AT91PS_AES pAES // pointer to a AES controller
-	)
-{
-	pAES->AES_CR = AT91C_AES_LOADSEED;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_SetCryptoKey
-//* \brief Set Cryptographic Key x
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_SetCryptoKey (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned char index,
-	unsigned int keyword
-	)
-{
-	pAES->AES_KEYWxR[index] = keyword;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_InputData
-//* \brief Set Input Data x
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_InputData (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned char index,
-	unsigned int indata
-	)
-{
-	pAES->AES_IDATAxR[index] = indata;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_GetOutputData
-//* \brief Get Output Data x
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetOutputData (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned char index
-	)
-{
-	return pAES->AES_ODATAxR[index];	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_SetInitializationVector
-//* \brief Set Initialization Vector (or Counter) x
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_SetInitializationVector (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned char index,
-	unsigned int initvector
-	)
-{
-	pAES->AES_IVxR[index] = initvector;	
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR TDES
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_EnableIt
-//* \brief Enable TDES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_EnableIt (
-	AT91PS_TDES pTDES,     // pointer to a TDES controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pTDES->TDES_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_DisableIt
-//* \brief Disable TDES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_DisableIt (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pTDES->TDES_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_GetStatus
-//* \brief Return TDES Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
-	AT91PS_TDES pTDES) // pointer to a TDES controller
-{
-	return pTDES->TDES_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_GetInterruptMaskStatus
-//* \brief Return TDES Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
-	AT91PS_TDES pTDES) // pointer to a TDES controller
-{
-	return pTDES->TDES_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_IsInterruptMasked
-//* \brief Test if TDES Interrupt is Masked 
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_IsInterruptMasked(
-        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_IsStatusSet
-//* \brief Test if TDES Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_IsStatusSet(
-        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_TDES_GetStatus(pTDES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_CfgModeReg
-//* \brief Configure the Mode Register of the TDES controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_CfgModeReg (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned int mode)        // mode register 
-{
-	//* Write to the MR register
-	pTDES->TDES_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_GetModeReg
-//* \brief Return the Mode Register of the TDES controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetModeReg (
-	AT91PS_TDES pTDES // pointer to a TDES controller
-	)
-{
-	return pTDES->TDES_MR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_StartProcessing
-//* \brief Start Encryption or Decryption
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_StartProcessing (
-	AT91PS_TDES pTDES // pointer to a TDES controller
-	)
-{
-	pTDES->TDES_CR = AT91C_TDES_START;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SoftReset
-//* \brief Reset TDES
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SoftReset (
-	AT91PS_TDES pTDES // pointer to a TDES controller
-	)
-{
-	pTDES->TDES_CR = AT91C_TDES_SWRST;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SetCryptoKey1
-//* \brief Set Cryptographic Key 1 Word x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetCryptoKey1 (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int keyword
-	)
-{
-	pTDES->TDES_KEY1WxR[index] = keyword;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SetCryptoKey2
-//* \brief Set Cryptographic Key 2 Word x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetCryptoKey2 (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int keyword
-	)
-{
-	pTDES->TDES_KEY2WxR[index] = keyword;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SetCryptoKey3
-//* \brief Set Cryptographic Key 3 Word x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetCryptoKey3 (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int keyword
-	)
-{
-	pTDES->TDES_KEY3WxR[index] = keyword;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_InputData
-//* \brief Set Input Data x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_InputData (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int indata
-	)
-{
-	pTDES->TDES_IDATAxR[index] = indata;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_GetOutputData
-//* \brief Get Output Data x
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetOutputData (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index
-	)
-{
-	return pTDES->TDES_ODATAxR[index];	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SetInitializationVector
-//* \brief Set Initialization Vector x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetInitializationVector (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int initvector
-	)
-{
-	pTDES->TDES_IVxR[index] = initvector;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  DBGU
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_CfgPIO
-//* \brief Configure PIO controllers to drive DBGU signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA27_DRXD    ) |
-		((unsigned int) AT91C_PA28_DTXD    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PMC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgPIO
-//* \brief Configure PIO controllers to drive PMC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB30_PCK2    ) |
-		((unsigned int) AT91C_PB29_PCK1    ), // Peripheral A
-		((unsigned int) AT91C_PB20_PCK0    ) |
-		((unsigned int) AT91C_PB0_PCK0    ) |
-		((unsigned int) AT91C_PB22_PCK2    ) |
-		((unsigned int) AT91C_PB21_PCK1    )); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA30_PCK2    ) |
-		((unsigned int) AT91C_PA13_PCK1    ) |
-		((unsigned int) AT91C_PA27_PCK3    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_VREG_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  VREG
-//*----------------------------------------------------------------------------
-__inline void AT91F_VREG_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  RSTC
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SSC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SSC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_CfgPIO
-//* \brief Configure PIO controllers to drive SSC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA25_RK      ) |
-		((unsigned int) AT91C_PA22_TK      ) |
-		((unsigned int) AT91C_PA21_TF      ) |
-		((unsigned int) AT91C_PA24_RD      ) |
-		((unsigned int) AT91C_PA26_RF      ) |
-		((unsigned int) AT91C_PA23_TD      ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  WDTC
-//*----------------------------------------------------------------------------
-__inline void AT91F_WDTC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US1
-//*----------------------------------------------------------------------------
-__inline void AT91F_US1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_US1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US1_CfgPIO
-//* \brief Configure PIO controllers to drive US1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_US1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PB26_RI1     ) |
-		((unsigned int) AT91C_PB24_DSR1    ) |
-		((unsigned int) AT91C_PB23_DCD1    ) |
-		((unsigned int) AT91C_PB25_DTR1    )); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA7_SCK1    ) |
-		((unsigned int) AT91C_PA8_RTS1    ) |
-		((unsigned int) AT91C_PA6_TXD1    ) |
-		((unsigned int) AT91C_PA5_RXD1    ) |
-		((unsigned int) AT91C_PA9_CTS1    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US0
-//*----------------------------------------------------------------------------
-__inline void AT91F_US0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_US0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US0_CfgPIO
-//* \brief Configure PIO controllers to drive US0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_US0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA0_RXD0    ) |
-		((unsigned int) AT91C_PA4_CTS0    ) |
-		((unsigned int) AT91C_PA3_RTS0    ) |
-		((unsigned int) AT91C_PA2_SCK0    ) |
-		((unsigned int) AT91C_PA1_TXD0    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SPI1
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SPI1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI1_CfgPIO
-//* \brief Configure PIO controllers to drive SPI1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PB16_NPCS13  ) |
-		((unsigned int) AT91C_PB10_NPCS11  ) |
-		((unsigned int) AT91C_PB11_NPCS12  )); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA4_NPCS13  ) |
-		((unsigned int) AT91C_PA29_NPCS13  ) |
-		((unsigned int) AT91C_PA21_NPCS10  ) |
-		((unsigned int) AT91C_PA22_SPCK1   ) |
-		((unsigned int) AT91C_PA25_NPCS11  ) |
-		((unsigned int) AT91C_PA2_NPCS11  ) |
-		((unsigned int) AT91C_PA24_MISO1   ) |
-		((unsigned int) AT91C_PA3_NPCS12  ) |
-		((unsigned int) AT91C_PA26_NPCS12  ) |
-		((unsigned int) AT91C_PA23_MOSI1   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SPI0
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SPI0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI0_CfgPIO
-//* \brief Configure PIO controllers to drive SPI0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PB13_NPCS01  ) |
-		((unsigned int) AT91C_PB17_NPCS03  ) |
-		((unsigned int) AT91C_PB14_NPCS02  )); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA16_MISO0   ) |
-		((unsigned int) AT91C_PA13_NPCS01  ) |
-		((unsigned int) AT91C_PA15_NPCS03  ) |
-		((unsigned int) AT91C_PA17_MOSI0   ) |
-		((unsigned int) AT91C_PA18_SPCK0   ) |
-		((unsigned int) AT91C_PA14_NPCS02  ) |
-		((unsigned int) AT91C_PA12_NPCS00  ), // Peripheral A
-		((unsigned int) AT91C_PA7_NPCS01  ) |
-		((unsigned int) AT91C_PA9_NPCS03  ) |
-		((unsigned int) AT91C_PA8_NPCS02  )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PITC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  AIC
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_FIQ) |
-		((unsigned int) 1 << AT91C_ID_IRQ0) |
-		((unsigned int) 1 << AT91C_ID_IRQ1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_CfgPIO
-//* \brief Configure PIO controllers to drive AIC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA30_IRQ0    ) |
-		((unsigned int) AT91C_PA29_FIQ     ), // Peripheral A
-		((unsigned int) AT91C_PA14_IRQ1    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  AES
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_AES));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TWI
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TWI));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_CfgPIO
-//* \brief Configure PIO controllers to drive TWI signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA11_TWCK    ) |
-		((unsigned int) AT91C_PA10_TWD     ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  ADC
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_ADC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgPIO
-//* \brief Configure PIO controllers to drive ADC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PB18_ADTRG   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH3_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH3 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH3_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB22_PWM3    ), // Peripheral A
-		((unsigned int) AT91C_PB30_PWM3    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH2_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH2 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH2_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB21_PWM2    ), // Peripheral A
-		((unsigned int) AT91C_PB29_PWM2    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH1_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB20_PWM1    ), // Peripheral A
-		((unsigned int) AT91C_PB28_PWM1    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH0_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB19_PWM0    ), // Peripheral A
-		((unsigned int) AT91C_PB27_PWM0    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RTTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  RTTC
-//*----------------------------------------------------------------------------
-__inline void AT91F_RTTC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  UDP
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_UDP));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TDES
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TDES));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_EMAC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  EMAC
-//*----------------------------------------------------------------------------
-__inline void AT91F_EMAC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_EMAC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_EMAC_CfgPIO
-//* \brief Configure PIO controllers to drive EMAC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_EMAC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB2_ETX0    ) |
-		((unsigned int) AT91C_PB12_ETXER   ) |
-		((unsigned int) AT91C_PB16_ECOL    ) |
-		((unsigned int) AT91C_PB11_ETX3    ) |
-		((unsigned int) AT91C_PB6_ERX1    ) |
-		((unsigned int) AT91C_PB15_ERXDV   ) |
-		((unsigned int) AT91C_PB13_ERX2    ) |
-		((unsigned int) AT91C_PB3_ETX1    ) |
-		((unsigned int) AT91C_PB8_EMDC    ) |
-		((unsigned int) AT91C_PB5_ERX0    ) |
-		//((unsigned int) AT91C_PB18_EF100   ) |
-		((unsigned int) AT91C_PB14_ERX3    ) |
-		((unsigned int) AT91C_PB4_ECRS_ECRSDV) |
-		((unsigned int) AT91C_PB1_ETXEN   ) |
-		((unsigned int) AT91C_PB10_ETX2    ) |
-		((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
-		((unsigned int) AT91C_PB9_EMDIO   ) |
-		((unsigned int) AT91C_PB7_ERXER   ) |
-		((unsigned int) AT91C_PB17_ERXCK   ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC0
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC0_CfgPIO
-//* \brief Configure PIO controllers to drive TC0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB23_TIOA0   ) |
-		((unsigned int) AT91C_PB24_TIOB0   ), // Peripheral A
-		((unsigned int) AT91C_PB12_TCLK0   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC1
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC1_CfgPIO
-//* \brief Configure PIO controllers to drive TC1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB25_TIOA1   ) |
-		((unsigned int) AT91C_PB26_TIOB1   ), // Peripheral A
-		((unsigned int) AT91C_PB19_TCLK1   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC2_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC2
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC2_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC2));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC2_CfgPIO
-//* \brief Configure PIO controllers to drive TC2 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC2_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB28_TIOB2   ) |
-		((unsigned int) AT91C_PB27_TIOA2   ), // Peripheral A
-		0); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA15_TCLK2   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  MC
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIOA_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PIOA
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIOA_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PIOA));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIOB_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PIOB
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIOB_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PIOB));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  CAN
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_CAN));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgPIO
-//* \brief Configure PIO controllers to drive CAN signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA20_CANTX   ) |
-		((unsigned int) AT91C_PA19_CANRX   ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PWMC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PWMC));
-}
-
-#endif // lib_AT91SAM7X128_H
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
deleted file mode 100755
index efffc02..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/lib_AT91SAM7X256.h
+++ /dev/null
@@ -1,4558 +0,0 @@
-//* ----------------------------------------------------------------------------
-//*         ATMEL Microcontroller Software Support  -  ROUSSET  -
-//* ----------------------------------------------------------------------------
-//* DISCLAIMER:  THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
-//* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-//* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
-//* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
-//* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
-//* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
-//* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-//* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-//* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-//* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//* ----------------------------------------------------------------------------
-//* File Name           : lib_AT91SAM7X256.h
-//* Object              : AT91SAM7X256 inlined functions
-//* Generated           : AT91 SW Application Group  05/20/2005 (16:22:29)
-//*
-//* CVS Reference       : /lib_dbgu.h/1.1/Fri Jan 31 12:18:40 2003//
-//* CVS Reference       : /lib_pmc_SAM7X.h/1.1/Tue Feb  1 08:32:10 2005//
-//* CVS Reference       : /lib_VREG_6085B.h/1.1/Tue Feb  1 16:20:47 2005//
-//* CVS Reference       : /lib_rstc_6098A.h/1.1/Wed Oct  6 10:39:20 2004//
-//* CVS Reference       : /lib_ssc.h/1.4/Fri Jan 31 12:19:20 2003//
-//* CVS Reference       : /lib_wdtc_6080A.h/1.1/Wed Oct  6 10:38:30 2004//
-//* CVS Reference       : /lib_usart.h/1.5/Thu Nov 21 16:01:54 2002//
-//* CVS Reference       : /lib_spi2.h/1.1/Mon Aug 25 14:23:52 2003//
-//* CVS Reference       : /lib_pitc_6079A.h/1.2/Tue Nov  9 14:43:56 2004//
-//* CVS Reference       : /lib_aic_6075b.h/1.1/Fri May 20 14:01:19 2005//
-//* CVS Reference       : /lib_aes_6149a.h/1.1/Mon Jan 17 07:43:09 2005//
-//* CVS Reference       : /lib_twi.h/1.3/Mon Jul 19 14:27:58 2004//
-//* CVS Reference       : /lib_adc.h/1.6/Fri Oct 17 09:12:38 2003//
-//* CVS Reference       : /lib_rttc_6081A.h/1.1/Wed Oct  6 10:39:38 2004//
-//* CVS Reference       : /lib_udp.h/1.4/Wed Feb 16 08:39:34 2005//
-//* CVS Reference       : /lib_des3_6150a.h/1.1/Mon Jan 17 09:19:19 2005//
-//* CVS Reference       : /lib_tc_1753b.h/1.1/Fri Jan 31 12:20:02 2003//
-//* CVS Reference       : /lib_MC_SAM7X.h/1.1/Thu Mar 25 15:19:14 2004//
-//* CVS Reference       : /lib_pio.h/1.3/Fri Jan 31 12:18:56 2003//
-//* CVS Reference       : /lib_can_AT91.h/1.4/Fri Oct 17 09:12:50 2003//
-//* CVS Reference       : /lib_PWM_SAM.h/1.3/Thu Jan 22 10:10:50 2004//
-//* CVS Reference       : /lib_pdc.h/1.2/Tue Jul  2 13:29:40 2002//
-//* ----------------------------------------------------------------------------
-
-#ifndef lib_AT91SAM7X256_H
-#define lib_AT91SAM7X256_H
-
-/* *****************************************************************************
-                SOFTWARE API FOR AIC
-   ***************************************************************************** */
-#define AT91C_AIC_BRANCH_OPCODE ((void (*) ()) 0xE51FFF20) // ldr, pc, [pc, #-&F20]
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ConfigureIt
-//* \brief Interrupt Handler Initialization
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AIC_ConfigureIt (
-	AT91PS_AIC pAic,  // \arg pointer to the AIC registers
-	unsigned int irq_id,     // \arg interrupt number to initialize
-	unsigned int priority,   // \arg priority to give to the interrupt
-	unsigned int src_type,   // \arg activation and sense of activation
-	void (*newHandler) (void) ) // \arg address of the interrupt handler
-{
-	unsigned int oldHandler;
-    unsigned int mask ;
-
-    oldHandler = pAic->AIC_SVR[irq_id];
-
-    mask = 0x1 << irq_id ;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Save the interrupt handler routine pointer and the interrupt priority
-    pAic->AIC_SVR[irq_id] = (unsigned int) newHandler ;
-    //* Store the Source Mode Register
-    pAic->AIC_SMR[irq_id] = src_type | priority  ;
-    //* Clear the interrupt on the interrupt controller
-    pAic->AIC_ICCR = mask ;
-
-	return oldHandler;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_EnableIt
-//* \brief Enable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_EnableIt (
-	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-	unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    //* Enable the interrupt on the interrupt controller
-    pAic->AIC_IECR = 0x1 << irq_id ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_DisableIt
-//* \brief Disable corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_DisableIt (
-	AT91PS_AIC pAic,      // \arg pointer to the AIC registers
-	unsigned int irq_id ) // \arg interrupt number to initialize
-{
-    unsigned int mask = 0x1 << irq_id;
-    //* Disable the interrupt on the interrupt controller
-    pAic->AIC_IDCR = mask ;
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = mask ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_ClearIt
-//* \brief Clear corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_ClearIt (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg interrupt number to initialize
-{
-    //* Clear the interrupt on the Interrupt Controller ( if one is pending )
-    pAic->AIC_ICCR = (0x1 << irq_id);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_AcknowledgeIt
-//* \brief Acknowledge corresponding IT number
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_AcknowledgeIt (
-	AT91PS_AIC pAic)     // \arg pointer to the AIC registers
-{
-    pAic->AIC_EOICR = pAic->AIC_EOICR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_SetExceptionVector
-//* \brief Configure vector handler
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_SetExceptionVector (
-	unsigned int *pVector, // \arg pointer to the AIC registers
-	void (*Handler) () )   // \arg Interrupt Handler
-{
-	unsigned int oldVector = *pVector;
-
-	if ((unsigned int) Handler == (unsigned int) AT91C_AIC_BRANCH_OPCODE)
-		*pVector = (unsigned int) AT91C_AIC_BRANCH_OPCODE;
-	else
-		*pVector = (((((unsigned int) Handler) - ((unsigned int) pVector) - 0x8) >> 2) & 0x00FFFFFF) | 0xEA000000;
-
-	return oldVector;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Trig
-//* \brief Trig an IT
-//*----------------------------------------------------------------------------
-__inline void  AT91F_AIC_Trig (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg interrupt number
-{
-	pAic->AIC_ISCR = (0x1 << irq_id) ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsActive
-//* \brief Test if an IT is active
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsActive (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg Interrupt Number
-{
-	return (pAic->AIC_ISR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_IsPending
-//* \brief Test if an IT is pending
-//*----------------------------------------------------------------------------
-__inline unsigned int  AT91F_AIC_IsPending (
-	AT91PS_AIC pAic,     // \arg pointer to the AIC registers
-	unsigned int irq_id) // \arg Interrupt Number
-{
-	return (pAic->AIC_IPR & (0x1 << irq_id));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_Open
-//* \brief Set exception vectors and AIC registers to default values
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_Open(
-	AT91PS_AIC pAic,        // \arg pointer to the AIC registers
-	void (*IrqHandler) (),  // \arg Default IRQ vector exception
-	void (*FiqHandler) (),  // \arg Default FIQ vector exception
-	void (*DefaultHandler)  (), // \arg Default Handler set in ISR
-	void (*SpuriousHandler) (), // \arg Default Spurious Handler
-	unsigned int protectMode)   // \arg Debug Control Register
-{
-	int i;
-
-	// Disable all interrupts and set IVR to the default handler
-	for (i = 0; i < 32; ++i) {
-		AT91F_AIC_DisableIt(pAic, i);
-		AT91F_AIC_ConfigureIt(pAic, i, AT91C_AIC_PRIOR_LOWEST, AT91C_AIC_SRCTYPE_HIGH_LEVEL, DefaultHandler);
-	}
-
-	// Set the IRQ exception vector
-	AT91F_AIC_SetExceptionVector((unsigned int *) 0x18, IrqHandler);
-	// Set the Fast Interrupt exception vector
-	AT91F_AIC_SetExceptionVector((unsigned int *) 0x1C, FiqHandler);
-
-	pAic->AIC_SPU = (unsigned int) SpuriousHandler;
-	pAic->AIC_DCR = protectMode;
-}
-/* *****************************************************************************
-                SOFTWARE API FOR PDC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextRx
-//* \brief Set the next receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextRx (
-	AT91PS_PDC pPDC,     // \arg pointer to a PDC controller
-	char *address,       // \arg address to the next bloc to be received
-	unsigned int bytes)  // \arg number of bytes to be received
-{
-	pPDC->PDC_RNPR = (unsigned int) address;
-	pPDC->PDC_RNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetNextTx
-//* \brief Set the next transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetNextTx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be transmitted
-	unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-	pPDC->PDC_TNPR = (unsigned int) address;
-	pPDC->PDC_TNCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetRx
-//* \brief Set the receive transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetRx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be received
-	unsigned int bytes)    // \arg number of bytes to be received
-{
-	pPDC->PDC_RPR = (unsigned int) address;
-	pPDC->PDC_RCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SetTx
-//* \brief Set the transmit transfer descriptor
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_SetTx (
-	AT91PS_PDC pPDC,       // \arg pointer to a PDC controller
-	char *address,         // \arg address to the next bloc to be transmitted
-	unsigned int bytes)    // \arg number of bytes to be transmitted
-{
-	pPDC->PDC_TPR = (unsigned int) address;
-	pPDC->PDC_TCR = bytes;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableTx
-//* \brief Enable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableTx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_EnableRx
-//* \brief Enable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_EnableRx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableTx
-//* \brief Disable transmit
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableTx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_DisableRx
-//* \brief Disable receive
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_DisableRx (
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsTxEmpty
-//* \brief Test if the current transfer descriptor has been sent
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsTxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_TCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextTxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextTxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_TNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsRxEmpty
-//* \brief Test if the current transfer descriptor has been filled
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsRxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_RCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_IsNextRxEmpty
-//* \brief Test if the next transfer descriptor has been moved to the current td
-//*----------------------------------------------------------------------------
-__inline int AT91F_PDC_IsNextRxEmpty ( // \return return 1 if transfer is complete
-	AT91PS_PDC pPDC )       // \arg pointer to a PDC controller
-{
-	return !(pPDC->PDC_RNCR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Open
-//* \brief Open PDC: disable TX and RX reset transfer descriptors, re-enable RX and TX
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Open (
-	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-	AT91F_PDC_DisableRx(pPDC);
-	AT91F_PDC_DisableTx(pPDC);
-
-	//* Reset all Counter register Next buffer first
-	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-    //* Enable the RX and TX PDC transfer requests
-	AT91F_PDC_EnableRx(pPDC);
-	AT91F_PDC_EnableTx(pPDC);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_Close
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline void AT91F_PDC_Close (
-	AT91PS_PDC pPDC)       // \arg pointer to a PDC controller
-{
-    //* Disable the RX and TX PDC transfer requests
-	AT91F_PDC_DisableRx(pPDC);
-	AT91F_PDC_DisableTx(pPDC);
-
-	//* Reset all Counter register Next buffer first
-	AT91F_PDC_SetNextTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetNextRx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetTx(pPDC, (char *) 0, 0);
-	AT91F_PDC_SetRx(pPDC, (char *) 0, 0);
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_SendFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_SendFrame(
-	AT91PS_PDC pPDC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	if (AT91F_PDC_IsTxEmpty(pPDC)) {
-		//* Buffer and next buffer can be initialized
-		AT91F_PDC_SetTx(pPDC, pBuffer, szBuffer);
-		AT91F_PDC_SetNextTx(pPDC, pNextBuffer, szNextBuffer);
-		return 2;
-	}
-	else if (AT91F_PDC_IsNextTxEmpty(pPDC)) {
-		//* Only one buffer can be initialized
-		AT91F_PDC_SetNextTx(pPDC, pBuffer, szBuffer);
-		return 1;
-	}
-	else {
-		//* All buffer are in use...
-		return 0;
-	}
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PDC_ReceiveFrame
-//* \brief Close PDC: disable TX and RX reset transfer descriptors
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PDC_ReceiveFrame (
-	AT91PS_PDC pPDC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	if (AT91F_PDC_IsRxEmpty(pPDC)) {
-		//* Buffer and next buffer can be initialized
-		AT91F_PDC_SetRx(pPDC, pBuffer, szBuffer);
-		AT91F_PDC_SetNextRx(pPDC, pNextBuffer, szNextBuffer);
-		return 2;
-	}
-	else if (AT91F_PDC_IsNextRxEmpty(pPDC)) {
-		//* Only one buffer can be initialized
-		AT91F_PDC_SetNextRx(pPDC, pBuffer, szBuffer);
-		return 1;
-	}
-	else {
-		//* All buffer are in use...
-		return 0;
-	}
-}
-/* *****************************************************************************
-                SOFTWARE API FOR DBGU
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptEnable
-//* \brief Enable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptEnable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be enabled
-{
-        pDbgu->DBGU_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_InterruptDisable
-//* \brief Disable DBGU Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_InterruptDisable(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  dbgu interrupt to be disabled
-{
-        pDbgu->DBGU_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_GetInterruptMaskStatus
-//* \brief Return DBGU Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_DBGU_GetInterruptMaskStatus( // \return DBGU Interrupt Mask Status
-        AT91PS_DBGU pDbgu) // \arg  pointer to a DBGU controller
-{
-        return pDbgu->DBGU_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_IsInterruptMasked
-//* \brief Test if DBGU Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_DBGU_IsInterruptMasked(
-        AT91PS_DBGU pDbgu,   // \arg  pointer to a DBGU controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_DBGU_GetInterruptMaskStatus(pDbgu) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PIO
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPeriph
-//* \brief Enable pins to be drived by peripheral
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPeriph(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int periphAEnable,  // \arg PERIPH A to enable
-	unsigned int periphBEnable)  // \arg PERIPH B to enable
-
-{
-	pPio->PIO_ASR = periphAEnable;
-	pPio->PIO_BSR = periphBEnable;
-	pPio->PIO_PDR = (periphAEnable | periphBEnable); // Set in Periph mode
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOutput
-//* \brief Enable PIO in output mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOutput(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int pioEnable)      // \arg PIO to be enabled
-{
-	pPio->PIO_PER = pioEnable; // Set in PIO mode
-	pPio->PIO_OER = pioEnable; // Configure in Output
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInput
-//* \brief Enable PIO in input mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInput(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int inputEnable)      // \arg PIO to be enabled
-{
-	// Disable output
-	pPio->PIO_ODR  = inputEnable;
-	pPio->PIO_PER  = inputEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgOpendrain
-//* \brief Configure PIO in open drain
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgOpendrain(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int multiDrvEnable) // \arg pio to be configured in open drain
-{
-	// Configure the multi-drive option
-	pPio->PIO_MDDR = ~multiDrvEnable;
-	pPio->PIO_MDER = multiDrvEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgPullup
-//* \brief Enable pullup on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgPullup(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int pullupEnable)   // \arg enable pullup on PIO
-{
-		// Connect or not Pullup
-	pPio->PIO_PPUDR = ~pullupEnable;
-	pPio->PIO_PPUER = pullupEnable;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgDirectDrive
-//* \brief Enable direct drive on PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgDirectDrive(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int directDrive)    // \arg PIO to be configured with direct drive
-
-{
-	// Configure the Direct Drive
-	pPio->PIO_OWDR  = ~directDrive;
-	pPio->PIO_OWER  = directDrive;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_CfgInputFilter
-//* \brief Enable input filter on input PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_CfgInputFilter(
-	AT91PS_PIO pPio,             // \arg pointer to a PIO controller
-	unsigned int inputFilter)    // \arg PIO to be configured with input filter
-
-{
-	// Configure the Direct Drive
-	pPio->PIO_IFDR  = ~inputFilter;
-	pPio->PIO_IFER  = inputFilter;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInput
-//* \brief Return PIO input value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInput( // \return PIO input
-	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-	return pPio->PIO_PDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputSet
-//* \brief Test if PIO is input flag is active
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputSet(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PIO_GetInput(pPio) & flag);
-}
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_SetOutput
-//* \brief Set to 1 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_SetOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be set
-{
-	pPio->PIO_SODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ClearOutput
-//* \brief Set to 0 output PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ClearOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be cleared
-{
-	pPio->PIO_CODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_ForceOutput
-//* \brief Force output when Direct drive option is enabled
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_ForceOutput(
-	AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-	unsigned int flag) // \arg  output to be forced
-{
-	pPio->PIO_ODSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Enable
-//* \brief Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Enable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
-{
-        pPio->PIO_PER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Disable
-//* \brief Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_Disable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
-{
-        pPio->PIO_PDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetStatus
-//* \brief Return PIO Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetStatus( // \return PIO Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsSet
-//* \brief Test if PIO is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputEnable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be enabled
-{
-        pPio->PIO_OER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputDisable
-//* \brief Output Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output to be disabled
-{
-        pPio->PIO_ODR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputStatus
-//* \brief Return PIO Output Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputStatus( // \return PIO Output Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOuputSet
-//* \brief Test if PIO Output is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterEnable
-//* \brief Input Filter Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be enabled
-{
-        pPio->PIO_IFER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InputFilterDisable
-//* \brief Input Filter Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InputFilterDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio input filter to be disabled
-{
-        pPio->PIO_IFDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInputFilterStatus
-//* \brief Return PIO Input Filter Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInputFilterStatus( // \return PIO Input Filter Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IFSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInputFilterSet
-//* \brief Test if PIO Input filter is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInputFilterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInputFilterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputDataStatus
-//* \brief Return PIO Output Data Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputDataStatus( // \return PIO Output Data Status
-	AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ODSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptEnable
-//* \brief Enable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be enabled
-{
-        pPio->PIO_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_InterruptDisable
-//* \brief Disable PIO Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_InterruptDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio interrupt to be disabled
-{
-        pPio->PIO_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptMaskStatus
-//* \brief Return PIO Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptMaskStatus( // \return PIO Interrupt Mask Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetInterruptStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetInterruptStatus( // \return PIO Interrupt Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptMasked
-//* \brief Test if PIO Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptMasked(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptMaskStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsInterruptSet
-//* \brief Test if PIO Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsInterruptSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetInterruptStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverEnable
-//* \brief Multi Driver Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be enabled
-{
-        pPio->PIO_MDER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_MultiDriverDisable
-//* \brief Multi Driver Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_MultiDriverDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio to be disabled
-{
-        pPio->PIO_MDDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetMultiDriverStatus
-//* \brief Return PIO Multi Driver Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetMultiDriverStatus( // \return PIO Multi Driver Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_MDSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsMultiDriverSet
-//* \brief Test if PIO MultiDriver is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsMultiDriverSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetMultiDriverStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_A_RegisterSelection
-//* \brief PIO A Register Selection
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_A_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio A register selection
-{
-        pPio->PIO_ASR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_B_RegisterSelection
-//* \brief PIO B Register Selection
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_B_RegisterSelection(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio B register selection
-{
-        pPio->PIO_BSR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_Get_AB_RegisterStatus
-//* \brief Return PIO Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_Get_AB_RegisterStatus( // \return PIO AB Register Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_ABSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsAB_RegisterSet
-//* \brief Test if PIO AB Register is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsAB_RegisterSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_Get_AB_RegisterStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteEnable
-//* \brief Output Write Enable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteEnable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be enabled
-{
-        pPio->PIO_OWER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_OutputWriteDisable
-//* \brief Output Write Disable PIO
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIO_OutputWriteDisable(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  pio output write to be disabled
-{
-        pPio->PIO_OWDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetOutputWriteStatus
-//* \brief Return PIO Output Write Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetOutputWriteStatus( // \return PIO Output Write Status
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_OWSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputWriteSet
-//* \brief Test if PIO OutputWrite is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputWriteSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputWriteStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_GetCfgPullup
-//* \brief Return PIO Configuration Pullup
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PIO_GetCfgPullup( // \return PIO Configuration Pullup
-        AT91PS_PIO pPio) // \arg  pointer to a PIO controller
-{
-        return pPio->PIO_PPUSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsOutputDataStatusSet
-//* \brief Test if PIO Output Data Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsOutputDataStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_PIO_GetOutputDataStatus(pPio) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIO_IsCfgPullupStatusSet
-//* \brief Test if PIO Configuration Pullup Status is Set
-//*----------------------------------------------------------------------------
-__inline int AT91F_PIO_IsCfgPullupStatusSet(
-        AT91PS_PIO pPio,   // \arg  pointer to a PIO controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (~AT91F_PIO_GetCfgPullup(pPio) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkEnableReg
-//* \brief Configure the System Clock Enable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkEnableReg (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int mode)
-{
-	//* Write to the SCER register
-	pPMC->PMC_SCER = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgSysClkDisableReg
-//* \brief Configure the System Clock Disable Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgSysClkDisableReg (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int mode)
-{
-	//* Write to the SCDR register
-	pPMC->PMC_SCDR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetSysClkStatusReg
-//* \brief Return the System Clock Status Register of the PMC controller
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetSysClkStatusReg (
-	AT91PS_PMC pPMC // pointer to a CAN controller
-	)
-{
-	return pPMC->PMC_SCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePeriphClock
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePeriphClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-	pPMC->PMC_PCER = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePeriphClock
-//* \brief Disable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePeriphClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int periphIds)  // \arg IDs of peripherals to enable
-{
-	pPMC->PMC_PCDR = periphIds;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetPeriphClock
-//* \brief Get peripheral clock status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetPeriphClock (
-	AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-	return pPMC->PMC_PCSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscillatorReg (
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int mode)
-{
-	pCKGR->CKGR_MOR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainOscillatorReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainOscillatorReg (
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	return pCKGR->CKGR_MOR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_EnableMainOscillator
-//* \brief Enable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_EnableMainOscillator(
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	pCKGR->CKGR_MOR |= AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_DisableMainOscillator
-//* \brief Disable the main oscillator
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_DisableMainOscillator (
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	pCKGR->CKGR_MOR &= ~AT91C_CKGR_MOSCEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_CfgMainOscStartUpTime
-//* \brief Cfg MOR Register according to the main osc startup time
-//*----------------------------------------------------------------------------
-__inline void AT91F_CKGR_CfgMainOscStartUpTime (
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int startup_time,  // \arg main osc startup time in microsecond (us)
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	pCKGR->CKGR_MOR &= ~AT91C_CKGR_OSCOUNT;
-	pCKGR->CKGR_MOR |= ((slowClock * startup_time)/(8*1000000)) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClockFreqReg
-//* \brief Cfg the main oscillator
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClockFreqReg (
-	AT91PS_CKGR pCKGR) // \arg pointer to CKGR controller
-{
-	return pCKGR->CKGR_MCFR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CKGR_GetMainClock
-//* \brief Return Main clock in Hz
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CKGR_GetMainClock (
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	return ((pCKGR->CKGR_MCFR  & AT91C_CKGR_MAINF) * slowClock) >> 4;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgMCKReg
-//* \brief Cfg Master Clock Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgMCKReg (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int mode)
-{
-	pPMC->PMC_MCKR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMCKReg
-//* \brief Return Master Clock Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMCKReg(
-	AT91PS_PMC pPMC) // \arg pointer to PMC controller
-{
-	return pPMC->PMC_MCKR;
-}
-
-//*------------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetMasterClock
-//* \brief Return master clock in Hz which correponds to processor clock for ARM7
-//*------------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetMasterClock (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	AT91PS_CKGR pCKGR, // \arg pointer to CKGR controller
-	unsigned int slowClock)  // \arg slowClock in Hz
-{
-	unsigned int reg = pPMC->PMC_MCKR;
-	unsigned int prescaler = (1 << ((reg & AT91C_PMC_PRES) >> 2));
-	unsigned int pllDivider, pllMultiplier;
-
-	switch (reg & AT91C_PMC_CSS) {
-		case AT91C_PMC_CSS_SLOW_CLK: // Slow clock selected
-			return slowClock / prescaler;
-		case AT91C_PMC_CSS_MAIN_CLK: // Main clock is selected
-			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / prescaler;
-		case AT91C_PMC_CSS_PLL_CLK: // PLLB clock is selected
-			reg = pCKGR->CKGR_PLLR;
-			pllDivider    = (reg  & AT91C_CKGR_DIV);
-			pllMultiplier = ((reg  & AT91C_CKGR_MUL) >> 16) + 1;
-			return AT91F_CKGR_GetMainClock(pCKGR, slowClock) / pllDivider * pllMultiplier / prescaler;
-	}
-	return 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnablePCK (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int pck,  // \arg Peripheral clock identifier 0 .. 7
-	unsigned int mode)
-{
-	pPMC->PMC_PCKR[pck] = mode;
-	pPMC->PMC_SCER = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisablePCK
-//* \brief Enable peripheral clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisablePCK (
-	AT91PS_PMC pPMC, // \arg pointer to PMC controller
-	unsigned int pck)  // \arg Peripheral clock identifier 0 .. 7
-{
-	pPMC->PMC_SCDR = (1 << pck) << 8;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_EnableIt
-//* \brief Enable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_EnableIt (
-	AT91PS_PMC pPMC,     // pointer to a PMC controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pPMC->PMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_DisableIt
-//* \brief Disable PMC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_DisableIt (
-	AT91PS_PMC pPMC, // pointer to a PMC controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pPMC->PMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetStatus
-//* \brief Return PMC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetStatus( // \return PMC Interrupt Status
-	AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-	return pPMC->PMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_GetInterruptMaskStatus
-//* \brief Return PMC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_GetInterruptMaskStatus( // \return PMC Interrupt Mask Status
-	AT91PS_PMC pPMC) // pointer to a PMC controller
-{
-	return pPMC->PMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsInterruptMasked
-//* \brief Test if PMC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsInterruptMasked(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PMC_GetInterruptMaskStatus(pPMC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_IsStatusSet
-//* \brief Test if PMC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PMC_IsStatusSet(
-        AT91PS_PMC pPMC,   // \arg  pointer to a PMC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PMC_GetStatus(pPMC) & flag);
-}/* *****************************************************************************
-                SOFTWARE API FOR RSTC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTSoftReset
-//* \brief Start Software Reset
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSoftReset(
-        AT91PS_RSTC pRSTC,
-        unsigned int reset)
-{
-	pRSTC->RSTC_RCR = (0xA5000000 | reset);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTSetMode
-//* \brief Set Reset Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTSetMode(
-        AT91PS_RSTC pRSTC,
-        unsigned int mode)
-{
-	pRSTC->RSTC_RMR = (0xA5000000 | mode);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTGetMode
-//* \brief Get Reset Mode
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetMode(
-        AT91PS_RSTC pRSTC)
-{
-	return (pRSTC->RSTC_RMR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTGetStatus
-//* \brief Get Reset Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTGetStatus(
-        AT91PS_RSTC pRSTC)
-{
-	return (pRSTC->RSTC_RSR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTIsSoftRstActive
-//* \brief Return !=0 if software reset is still not completed
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_RSTIsSoftRstActive(
-        AT91PS_RSTC pRSTC)
-{
-	return ((pRSTC->RSTC_RSR) & AT91C_RSTC_SRCMP);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR RTTC
-   ***************************************************************************** */
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_SetRTT_TimeBase()
-//* \brief  Set the RTT prescaler according to the TimeBase in ms
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetTimeBase(
-        AT91PS_RTTC pRTTC,
-        unsigned int ms)
-{
-	if (ms > 2000)
-		return 1;   // AT91C_TIME_OUT_OF_RANGE
-	pRTTC->RTTC_RTMR &= ~0xFFFF;	
-	pRTTC->RTTC_RTMR |= (((ms << 15) /1000) & 0xFFFF);	
-	return 0;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTSetPrescaler()
-//* \brief  Set the new prescaler value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTSetPrescaler(
-        AT91PS_RTTC pRTTC,
-        unsigned int rtpres)
-{
-	pRTTC->RTTC_RTMR &= ~0xFFFF;	
-	pRTTC->RTTC_RTMR |= (rtpres & 0xFFFF);	
-	return (pRTTC->RTTC_RTMR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTRestart()
-//* \brief  Restart the RTT prescaler
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTRestart(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTRST;	
-}
-
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetAlarmINT()
-//* \brief  Enable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmINT(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR |= AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ClearAlarmINT()
-//* \brief  Disable RTT Alarm Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearAlarmINT(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_ALMIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetRttIncINT()
-//* \brief  Enable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetRttIncINT(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR |= AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ClearRttIncINT()
-//* \brief  Disable RTT INC Interrupt
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTClearRttIncINT(
-        AT91PS_RTTC pRTTC)
-{
-	pRTTC->RTTC_RTMR &= ~AT91C_RTTC_RTTINCIEN;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_SetAlarmValue()
-//* \brief  Set RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline void AT91F_RTTSetAlarmValue(
-        AT91PS_RTTC pRTTC, unsigned int alarm)
-{
-	pRTTC->RTTC_RTAR = alarm;
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_GetAlarmValue()
-//* \brief  Get RTT Alarm Value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetAlarmValue(
-        AT91PS_RTTC pRTTC)
-{
-	return(pRTTC->RTTC_RTAR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTTGetStatus()
-//* \brief  Read the RTT status
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTGetStatus(
-        AT91PS_RTTC pRTTC)
-{
-	return(pRTTC->RTTC_RTSR);
-}
-
-//*--------------------------------------------------------------------------------------
-//* \fn     AT91F_RTT_ReadValue()
-//* \brief  Read the RTT value
-//*--------------------------------------------------------------------------------------
-__inline unsigned int AT91F_RTTReadValue(
-        AT91PS_RTTC pRTTC)
-{
-        register volatile unsigned int val1,val2;
-	do
-	{
-		val1 = pRTTC->RTTC_RTVR;
-		val2 = pRTTC->RTTC_RTVR;
-	}	
-	while(val1 != val2);
-	return(val1);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR PITC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITInit
-//* \brief System timer init : period in µsecond, system clock freq in MHz
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITInit(
-        AT91PS_PITC pPITC,
-        unsigned int period,
-        unsigned int pit_frequency)
-{
-	pPITC->PITC_PIMR = period? (period * pit_frequency + 8) >> 4 : 0; // +8 to avoid %10 and /10
-	pPITC->PITC_PIMR |= AT91C_PITC_PITEN;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITSetPIV
-//* \brief Set the PIT Periodic Interval Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITSetPIV(
-        AT91PS_PITC pPITC,
-        unsigned int piv)
-{
-	pPITC->PITC_PIMR = piv | (pPITC->PITC_PIMR & (AT91C_PITC_PITEN | AT91C_PITC_PITIEN));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITEnableInt
-//* \brief Enable PIT periodic interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITEnableInt(
-        AT91PS_PITC pPITC)
-{
-	pPITC->PITC_PIMR |= AT91C_PITC_PITIEN;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITDisableInt
-//* \brief Disable PIT periodic interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITDisableInt(
-        AT91PS_PITC pPITC)
-{
-	pPITC->PITC_PIMR &= ~AT91C_PITC_PITIEN;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITGetMode
-//* \brief Read PIT mode register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetMode(
-        AT91PS_PITC pPITC)
-{
-	return(pPITC->PITC_PIMR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITGetStatus
-//* \brief Read PIT status register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetStatus(
-        AT91PS_PITC pPITC)
-{
-	return(pPITC->PITC_PISR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITGetPIIR
-//* \brief Read PIT CPIV and PICNT without ressetting the counters
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetPIIR(
-        AT91PS_PITC pPITC)
-{
-	return(pPITC->PITC_PIIR);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITGetPIVR
-//* \brief Read System timer CPIV and PICNT without ressetting the counters
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PITGetPIVR(
-        AT91PS_PITC pPITC)
-{
-	return(pPITC->PITC_PIVR);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR WDTC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTSetMode
-//* \brief Set Watchdog Mode Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_WDTSetMode(
-        AT91PS_WDTC pWDTC,
-        unsigned int Mode)
-{
-	pWDTC->WDTC_WDMR = Mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTRestart
-//* \brief Restart Watchdog
-//*----------------------------------------------------------------------------
-__inline void AT91F_WDTRestart(
-        AT91PS_WDTC pWDTC)
-{
-	pWDTC->WDTC_WDCR = 0xA5000001;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTSGettatus
-//* \brief Get Watchdog Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_WDTSGettatus(
-        AT91PS_WDTC pWDTC)
-{
-	return(pWDTC->WDTC_WDSR & 0x3);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTGetPeriod
-//* \brief Translate ms into Watchdog Compatible value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_WDTGetPeriod(unsigned int ms)
-{
-	if ((ms < 4) || (ms > 16000))
-		return 0;
-	return((ms << 8) / 1000);
-}
-/* *****************************************************************************
-                SOFTWARE API FOR VREG
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_VREG_Enable_LowPowerMode
-//* \brief Enable VREG Low Power Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_VREG_Enable_LowPowerMode(
-        AT91PS_VREG pVREG)
-{
-	pVREG->VREG_MR |= AT91C_VREG_PSTDBY;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_VREG_Disable_LowPowerMode
-//* \brief Disable VREG Low Power Mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_VREG_Disable_LowPowerMode(
-        AT91PS_VREG pVREG)
-{
-	pVREG->VREG_MR &= ~AT91C_VREG_PSTDBY;	
-}/* *****************************************************************************
-                SOFTWARE API FOR MC
-   ***************************************************************************** */
-
-#define AT91C_MC_CORRECT_KEY  ((unsigned int) 0x5A << 24) // (MC) Correct Protect Key
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_Remap
-//* \brief Make Remap
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_Remap (void)     //
-{
-    AT91PS_MC pMC = (AT91PS_MC) AT91C_BASE_MC;
-
-    pMC->MC_RCR = AT91C_MC_RCB;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_CfgModeReg
-//* \brief Configure the EFC Mode Register of the MC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_EFC_CfgModeReg (
-	AT91PS_MC pMC, // pointer to a MC controller
-	unsigned int mode)        // mode register
-{
-	// Write to the FMR register
-	pMC->MC_FMR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_GetModeReg
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_GetModeReg(
-	AT91PS_MC pMC) // pointer to a MC controller
-{
-	return pMC->MC_FMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_ComputeFMCN
-//* \brief Return MC EFC Mode Regsiter
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_ComputeFMCN(
-	int master_clock) // master clock in Hz
-{
-	return (master_clock/1000000 +2);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_PerformCmd
-//* \brief Perform EFC Command
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_EFC_PerformCmd (
-	AT91PS_MC pMC, // pointer to a MC controller
-    unsigned int transfer_cmd)
-{
-	pMC->MC_FCR = transfer_cmd;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_GetStatus
-//* \brief Return MC EFC Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_GetStatus(
-	AT91PS_MC pMC) // pointer to a MC controller
-{
-	return pMC->MC_FSR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_IsInterruptMasked
-//* \brief Test if EFC MC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_IsInterruptMasked(
-        AT91PS_MC pMC,   // \arg  pointer to a MC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_MC_EFC_GetModeReg(pMC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_EFC_IsInterruptSet
-//* \brief Test if EFC MC Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_MC_EFC_IsInterruptSet(
-        AT91PS_MC pMC,   // \arg  pointer to a MC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_MC_EFC_GetStatus(pMC) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR SPI
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Open
-//* \brief Open a SPI Port
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_Open (
-        const unsigned int null)  // \arg
-{
-        /* NOT DEFINED AT THIS MOMENT */
-        return ( 0 );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgCs
-//* \brief Configure SPI chip select register
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgCs (
-	AT91PS_SPI pSPI,     // pointer to a SPI controller
-	int cs,     // SPI cs number (0 to 3)
- 	int val)   //  chip select register
-{
-	//* Write to the CSR register
-	*(pSPI->SPI_CSR + cs) = val;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_EnableIt
-//* \brief Enable SPI interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_EnableIt (
-	AT91PS_SPI pSPI,     // pointer to a SPI controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pSPI->SPI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_DisableIt
-//* \brief Disable SPI interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_DisableIt (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pSPI->SPI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Reset
-//* \brief Reset the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Reset (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SWRST;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Enable
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Enable (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SPIEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Disable
-//* \brief Disable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Disable (
-	AT91PS_SPI pSPI // pointer to a SPI controller
-	)
-{
-	//* Write to the CR register
-	pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgMode
-//* \brief Enable the SPI controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgMode (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	int mode)        // mode register
-{
-	//* Write to the MR register
-	pSPI->SPI_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_CfgPCS
-//* \brief Switch to the correct PCS of SPI Mode Register : Fixed Peripheral Selected
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_CfgPCS (
-	AT91PS_SPI pSPI, // pointer to a SPI controller
-	char PCS_Device) // PCS of the Device
-{	
- 	//* Write to the MR register
-	pSPI->SPI_MR &= 0xFFF0FFFF;
-	pSPI->SPI_MR |= ( (PCS_Device<<16) & AT91C_SPI_PCS );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_ReceiveFrame (
-	AT91PS_SPI pSPI,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pSPI->SPI_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is bSPIy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_SendFrame(
-	AT91PS_SPI pSPI,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pSPI->SPI_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_Close
-//* \brief Close SPI: disable IT disable transfert, close PDC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_Close (
-	AT91PS_SPI pSPI)     // \arg pointer to a SPI controller
-{
-    //* Reset all the Chip Select register
-    pSPI->SPI_CSR[0] = 0 ;
-    pSPI->SPI_CSR[1] = 0 ;
-    pSPI->SPI_CSR[2] = 0 ;
-    pSPI->SPI_CSR[3] = 0 ;
-
-    //* Reset the SPI mode
-    pSPI->SPI_MR = 0  ;
-
-    //* Disable all interrupts
-    pSPI->SPI_IDR = 0xFFFFFFFF ;
-
-    //* Abort the Peripheral Data Transfers
-    AT91F_PDC_Close((AT91PS_PDC) &(pSPI->SPI_RPR));
-
-    //* Disable receiver and transmitter and stop any activity immediately
-    pSPI->SPI_CR = AT91C_SPI_SPIDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI_PutChar (
-	AT91PS_SPI pSPI,
-	unsigned int character,
-             unsigned int cs_number )
-{
-    unsigned int value_for_cs;
-    value_for_cs = (~(1 << cs_number)) & 0xF;  //Place a zero among a 4 ONEs number
-    pSPI->SPI_TDR = (character & 0xFFFF) | (value_for_cs << 16);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-__inline int AT91F_SPI_GetChar (
-	const AT91PS_SPI pSPI)
-{
-    return((pSPI->SPI_RDR) & 0xFFFF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_GetInterruptMaskStatus
-//* \brief Return SPI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SPI_GetInterruptMaskStatus( // \return SPI Interrupt Mask Status
-        AT91PS_SPI pSpi) // \arg  pointer to a SPI controller
-{
-        return pSpi->SPI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI_IsInterruptMasked
-//* \brief Test if SPI Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_SPI_IsInterruptMasked(
-        AT91PS_SPI pSpi,   // \arg  pointer to a SPI controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_SPI_GetInterruptMaskStatus(pSpi) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR USART
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Baudrate
-//* \brief Calculate the baudrate
-//* Standard Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_MODE ( AT91C_US_USMODE_NORMAL + \
-                        AT91C_US_NBSTOP_1_BIT + \
-                        AT91C_US_PAR_NONE + \
-                        AT91C_US_CHRL_8_BITS + \
-                        AT91C_US_CLKS_CLOCK )
-
-//* Standard External Asynchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_ASYNC_SCK_MODE ( AT91C_US_USMODE_NORMAL + \
-                            AT91C_US_NBSTOP_1_BIT + \
-                            AT91C_US_PAR_NONE + \
-                            AT91C_US_CHRL_8_BITS + \
-                            AT91C_US_CLKS_EXT )
-
-//* Standard Synchronous Mode : 8 bits , 1 stop , no parity
-#define AT91C_US_SYNC_MODE ( AT91C_US_SYNC + \
-                       AT91C_US_USMODE_NORMAL + \
-                       AT91C_US_NBSTOP_1_BIT + \
-                       AT91C_US_PAR_NONE + \
-                       AT91C_US_CHRL_8_BITS + \
-                       AT91C_US_CLKS_CLOCK )
-
-//* SCK used Label
-#define AT91C_US_SCK_USED (AT91C_US_CKLO | AT91C_US_CLKS_EXT)
-
-//* Standard ISO T=0 Mode : 8 bits , 1 stop , parity
-#define AT91C_US_ISO_READER_MODE ( AT91C_US_USMODE_ISO7816_0 + \
-					   		 AT91C_US_CLKS_CLOCK +\
-                       		 AT91C_US_NBSTOP_1_BIT + \
-                       		 AT91C_US_PAR_EVEN + \
-                       		 AT91C_US_CHRL_8_BITS + \
-                       		 AT91C_US_CKLO +\
-                       		 AT91C_US_OVER)
-
-//* Standard IRDA mode
-#define AT91C_US_ASYNC_IRDA_MODE (  AT91C_US_USMODE_IRDA + \
-                            AT91C_US_NBSTOP_1_BIT + \
-                            AT91C_US_PAR_NONE + \
-                            AT91C_US_CHRL_8_BITS + \
-                            AT91C_US_CLKS_CLOCK )
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Baudrate
-//* \brief Caluculate baud_value according to the main clock and the baud rate
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_Baudrate (
-	const unsigned int main_clock, // \arg peripheral clock
-	const unsigned int baud_rate)  // \arg UART baudrate
-{
-	unsigned int baud_value = ((main_clock*10)/(baud_rate * 16));
-	if ((baud_value % 10) >= 5)
-		baud_value = (baud_value / 10) + 1;
-	else
-		baud_value /= 10;
-	return baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetBaudrate (
-	AT91PS_USART pUSART,    // \arg pointer to a USART controller
-	unsigned int mainClock, // \arg peripheral clock
-	unsigned int speed)     // \arg UART baudrate
-{
-	//* Define the baud rate divisor register
-	pUSART->US_BRGR = AT91F_US_Baudrate(mainClock, speed);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetTimeguard
-//* \brief Set USART timeguard
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetTimeguard (
-	AT91PS_USART pUSART,    // \arg pointer to a USART controller
-	unsigned int timeguard) // \arg timeguard value
-{
-	//* Write the Timeguard Register
-	pUSART->US_TTGR = timeguard ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableIt
-//* \brief Enable USART IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableIt (
-	AT91PS_USART pUSART, // \arg pointer to a USART controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pUSART->US_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableIt
-//* \brief Disable USART IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableIt (
-	AT91PS_USART pUSART, // \arg pointer to a USART controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IER register
-	pUSART->US_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Configure
-//* \brief Configure USART
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_Configure (
-	AT91PS_USART pUSART,     // \arg pointer to a USART controller
-	unsigned int mainClock,  // \arg peripheral clock
-	unsigned int mode ,      // \arg mode Register to be programmed
-	unsigned int baudRate ,  // \arg baudrate to be programmed
-	unsigned int timeguard ) // \arg timeguard to be programmed
-{
-    //* Disable interrupts
-    pUSART->US_IDR = (unsigned int) -1;
-
-    //* Reset receiver and transmitter
-    pUSART->US_CR = AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS ;
-
-	//* Define the baud rate divisor register
-	AT91F_US_SetBaudrate(pUSART, mainClock, baudRate);
-
-	//* Write the Timeguard Register
-	AT91F_US_SetTimeguard(pUSART, timeguard);
-
-    //* Clear Transmit and Receive Counters
-    AT91F_PDC_Open((AT91PS_PDC) &(pUSART->US_RPR));
-
-    //* Define the USART mode
-    pUSART->US_MR = mode  ;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableRx
-//* \brief Enable receiving characters
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Enable receiver
-    pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_EnableTx
-//* \brief Enable sending characters
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_EnableTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Enable  transmitter
-    pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ResetRx
-//* \brief Reset Receiver and re-enable it
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_ResetRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-	//* Reset receiver
-	pUSART->US_CR = AT91C_US_RSTRX;
-    //* Re-Enable receiver
-    pUSART->US_CR = AT91C_US_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ResetTx
-//* \brief Reset Transmitter and re-enable it
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_ResetTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-	//* Reset transmitter
-	pUSART->US_CR = AT91C_US_RSTTX;
-    //* Enable transmitter
-    pUSART->US_CR = AT91C_US_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableRx
-//* \brief Disable Receiver
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableRx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Disable receiver
-    pUSART->US_CR = AT91C_US_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_DisableTx
-//* \brief Disable Transmitter
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_DisableTx (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Disable transmitter
-    pUSART->US_CR = AT91C_US_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Close
-//* \brief Close USART: disable IT disable receiver and transmitter, close PDC
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_Close (
-	AT91PS_USART pUSART)     // \arg pointer to a USART controller
-{
-    //* Reset the baud rate divisor register
-    pUSART->US_BRGR = 0 ;
-
-    //* Reset the USART mode
-    pUSART->US_MR = 0  ;
-
-    //* Reset the Timeguard Register
-    pUSART->US_TTGR = 0;
-
-    //* Disable all interrupts
-    pUSART->US_IDR = 0xFFFFFFFF ;
-
-    //* Abort the Peripheral Data Transfers
-    AT91F_PDC_Close((AT91PS_PDC) &(pUSART->US_RPR));
-
-    //* Disable receiver and transmitter and stop any activity immediately
-    pUSART->US_CR = AT91C_US_TXDIS | AT91C_US_RXDIS | AT91C_US_RSTTX | AT91C_US_RSTRX ;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_TxReady
-//* \brief Return 1 if a character can be written in US_THR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_TxReady (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR & AT91C_US_TXRDY);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_RxReady
-//* \brief Return 1 if a character can be read in US_RHR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_RxReady (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR & AT91C_US_RXRDY);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_Error
-//* \brief Return the error flag
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_Error (
-	AT91PS_USART pUSART )     // \arg pointer to a USART controller
-{
-    return (pUSART->US_CSR &
-    	(AT91C_US_OVRE |  // Overrun error
-    	 AT91C_US_FRAME | // Framing error
-    	 AT91C_US_PARE));  // Parity error
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_PutChar
-//* \brief Send a character,does not check if ready to send
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_PutChar (
-	AT91PS_USART pUSART,
-	int character )
-{
-    pUSART->US_THR = (character & 0x1FF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_GetChar
-//* \brief Receive a character,does not check if a character is available
-//*----------------------------------------------------------------------------
-__inline int AT91F_US_GetChar (
-	const AT91PS_USART pUSART)
-{
-    return((pUSART->US_RHR) & 0x1FF);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_SendFrame(
-	AT91PS_USART pUSART,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pUSART->US_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initializaed with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_US_ReceiveFrame (
-	AT91PS_USART pUSART,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pUSART->US_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US_SetIrdaFilter
-//* \brief Set the value of IrDa filter tregister
-//*----------------------------------------------------------------------------
-__inline void AT91F_US_SetIrdaFilter (
-	AT91PS_USART pUSART,
-	unsigned char value
-)
-{
-	pUSART->US_IF = value;
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR SSC
-   ***************************************************************************** */
-//* Define the standard I2S mode configuration
-
-//* Configuration to set in the SSC Transmit Clock Mode Register
-//* Parameters :  nb_bit_by_slot : 8, 16 or 32 bits
-//* 			  nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_MASTER_TX_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
-									   AT91C_SSC_CKS_DIV   +\
-                            		   AT91C_SSC_CKO_CONTINOUS      +\
-                            		   AT91C_SSC_CKG_NONE    +\
-                                       AT91C_SSC_START_FALL_RF +\
-                           			   AT91C_SSC_STTOUT  +\
-                            		   ((1<<16) & AT91C_SSC_STTDLY) +\
-                            		   ((((nb_bit_by_slot*nb_slot_by_frame)/2)-1) <<24))
-
-
-//* Configuration to set in the SSC Transmit Frame Mode Register
-//* Parameters : nb_bit_by_slot : 8, 16 or 32 bits
-//* 			 nb_slot_by_frame : number of channels
-#define AT91C_I2S_ASY_TX_FRAME_SETTING(nb_bit_by_slot, nb_slot_by_frame)( +\
-									(nb_bit_by_slot-1)  +\
-                            		AT91C_SSC_MSBF   +\
-                            		(((nb_slot_by_frame-1)<<8) & AT91C_SSC_DATNB)  +\
-                            		(((nb_bit_by_slot-1)<<16) & AT91C_SSC_FSLEN) +\
-                            		AT91C_SSC_FSOS_NEGATIVE)
-
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_SetBaudrate
-//* \brief Set the baudrate according to the CPU clock
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_SetBaudrate (
-        AT91PS_SSC pSSC,        // \arg pointer to a SSC controller
-        unsigned int mainClock, // \arg peripheral clock
-        unsigned int speed)     // \arg SSC baudrate
-{
-        unsigned int baud_value;
-        //* Define the baud rate divisor register
-        if (speed == 0)
-           baud_value = 0;
-        else
-        {
-           baud_value = (unsigned int) (mainClock * 10)/(2*speed);
-           if ((baud_value % 10) >= 5)
-                  baud_value = (baud_value / 10) + 1;
-           else
-                  baud_value /= 10;
-        }
-
-        pSSC->SSC_CMR = baud_value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_Configure
-//* \brief Configure SSC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_Configure (
-             AT91PS_SSC pSSC,          // \arg pointer to a SSC controller
-             unsigned int syst_clock,  // \arg System Clock Frequency
-             unsigned int baud_rate,   // \arg Expected Baud Rate Frequency
-             unsigned int clock_rx,    // \arg Receiver Clock Parameters
-             unsigned int mode_rx,     // \arg mode Register to be programmed
-             unsigned int clock_tx,    // \arg Transmitter Clock Parameters
-             unsigned int mode_tx)     // \arg mode Register to be programmed
-{
-    //* Disable interrupts
-	pSSC->SSC_IDR = (unsigned int) -1;
-
-    //* Reset receiver and transmitter
-	pSSC->SSC_CR = AT91C_SSC_SWRST | AT91C_SSC_RXDIS | AT91C_SSC_TXDIS ;
-
-    //* Define the Clock Mode Register
-	AT91F_SSC_SetBaudrate(pSSC, syst_clock, baud_rate);
-
-     //* Write the Receive Clock Mode Register
-	pSSC->SSC_RCMR =  clock_rx;
-
-     //* Write the Transmit Clock Mode Register
-	pSSC->SSC_TCMR =  clock_tx;
-
-     //* Write the Receive Frame Mode Register
-	pSSC->SSC_RFMR =  mode_rx;
-
-     //* Write the Transmit Frame Mode Register
-	pSSC->SSC_TFMR =  mode_tx;
-
-    //* Clear Transmit and Receive Counters
-	AT91F_PDC_Open((AT91PS_PDC) &(pSSC->SSC_RPR));
-
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableRx
-//* \brief Enable receiving datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableRx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Enable receiver
-    pSSC->SSC_CR = AT91C_SSC_RXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableRx
-//* \brief Disable receiving datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableRx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Disable receiver
-    pSSC->SSC_CR = AT91C_SSC_RXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableTx
-//* \brief Enable sending datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableTx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Enable  transmitter
-    pSSC->SSC_CR = AT91C_SSC_TXEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableTx
-//* \brief Disable sending datas
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableTx (
-	AT91PS_SSC pSSC)     // \arg pointer to a SSC controller
-{
-    //* Disable  transmitter
-    pSSC->SSC_CR = AT91C_SSC_TXDIS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_EnableIt
-//* \brief Enable SSC IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_EnableIt (
-	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pSSC->SSC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_DisableIt
-//* \brief Disable SSC IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_DisableIt (
-	AT91PS_SSC pSSC, // \arg pointer to a SSC controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pSSC->SSC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_ReceiveFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_ReceiveFrame (
-	AT91PS_SSC pSSC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_ReceiveFrame(
-		(AT91PS_PDC) &(pSSC->SSC_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_SendFrame
-//* \brief Return 2 if PDC has been initialized with Buffer and Next Buffer, 1 if PDC has been initialized with Next Buffer, 0 if PDC is busy
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_SendFrame(
-	AT91PS_SSC pSSC,
-	char *pBuffer,
-	unsigned int szBuffer,
-	char *pNextBuffer,
-	unsigned int szNextBuffer )
-{
-	return AT91F_PDC_SendFrame(
-		(AT91PS_PDC) &(pSSC->SSC_RPR),
-		pBuffer,
-		szBuffer,
-		pNextBuffer,
-		szNextBuffer);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_GetInterruptMaskStatus
-//* \brief Return SSC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_SSC_GetInterruptMaskStatus( // \return SSC Interrupt Mask Status
-        AT91PS_SSC pSsc) // \arg  pointer to a SSC controller
-{
-        return pSsc->SSC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_IsInterruptMasked
-//* \brief Test if SSC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_SSC_IsInterruptMasked(
-        AT91PS_SSC pSsc,   // \arg  pointer to a SSC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_SSC_GetInterruptMaskStatus(pSsc) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR TWI
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_EnableIt
-//* \brief Enable TWI IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_EnableIt (
-	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pTWI->TWI_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_DisableIt
-//* \brief Disable TWI IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_DisableIt (
-	AT91PS_TWI pTWI, // \arg pointer to a TWI controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pTWI->TWI_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_Configure
-//* \brief Configure TWI in master mode
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_Configure ( AT91PS_TWI pTWI )          // \arg pointer to a TWI controller
-{
-    //* Disable interrupts
-	pTWI->TWI_IDR = (unsigned int) -1;
-
-    //* Reset peripheral
-	pTWI->TWI_CR = AT91C_TWI_SWRST;
-
-	//* Set Master mode
-	pTWI->TWI_CR = AT91C_TWI_MSEN;
-
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_GetInterruptMaskStatus
-//* \brief Return TWI Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TWI_GetInterruptMaskStatus( // \return TWI Interrupt Mask Status
-        AT91PS_TWI pTwi) // \arg  pointer to a TWI controller
-{
-        return pTwi->TWI_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_IsInterruptMasked
-//* \brief Test if TWI Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_TWI_IsInterruptMasked(
-        AT91PS_TWI pTwi,   // \arg  pointer to a TWI controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_TWI_GetInterruptMaskStatus(pTwi) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR PWMC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_GetStatus
-//* \brief Return PWM Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_GetStatus( // \return PWM Interrupt Status
-	AT91PS_PWMC pPWM) // pointer to a PWM controller
-{
-	return pPWM->PWMC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_InterruptEnable
-//* \brief Enable PWM Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_InterruptEnable(
-        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  PWM interrupt to be enabled
-{
-        pPwm->PWMC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_InterruptDisable
-//* \brief Disable PWM Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_InterruptDisable(
-        AT91PS_PWMC pPwm,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  PWM interrupt to be disabled
-{
-        pPwm->PWMC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_GetInterruptMaskStatus
-//* \brief Return PWM Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_GetInterruptMaskStatus( // \return PWM Interrupt Mask Status
-        AT91PS_PWMC pPwm) // \arg  pointer to a PWM controller
-{
-        return pPwm->PWMC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_IsInterruptMasked
-//* \brief Test if PWM Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_IsInterruptMasked(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PWMC_GetInterruptMaskStatus(pPWM) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_IsStatusSet
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_PWMC_IsStatusSet(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_PWMC_GetStatus(pPWM) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_CfgChannel
-//* \brief Test if PWM Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CfgChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int channelId, // \arg PWM channel ID
-        unsigned int mode, // \arg  PWM mode
-        unsigned int period, // \arg PWM period
-        unsigned int duty) // \arg PWM duty cycle
-{
-	pPWM->PWMC_CH[channelId].PWMC_CMR = mode;
-	pPWM->PWMC_CH[channelId].PWMC_CDTYR = duty;
-	pPWM->PWMC_CH[channelId].PWMC_CPRDR = period;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_StartChannel
-//* \brief Enable channel
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_StartChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  Channels IDs to be enabled
-{
-	pPWM->PWMC_ENA = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_StopChannel
-//* \brief Disable channel
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_StopChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int flag) // \arg  Channels IDs to be enabled
-{
-	pPWM->PWMC_DIS = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWM_UpdateChannel
-//* \brief Update Period or Duty Cycle
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_UpdateChannel(
-        AT91PS_PWMC pPWM,   // \arg  pointer to a PWM controller
-        unsigned int channelId, // \arg PWM channel ID
-        unsigned int update) // \arg  Channels IDs to be enabled
-{
-	pPWM->PWMC_CH[channelId].PWMC_CUPDR = update;
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR UDP
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EnableIt
-//* \brief Enable UDP IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EnableIt (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg IT to be enabled
-{
-	//* Write to the IER register
-	pUDP->UDP_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_DisableIt
-//* \brief Disable UDP IT
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_DisableIt (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg IT to be disabled
-{
-	//* Write to the IDR register
-	pUDP->UDP_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_SetAddress
-//* \brief Set UDP functional address
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_SetAddress (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char address)   // \arg new UDP address
-{
-	pUDP->UDP_FADDR = (AT91C_UDP_FEN | address);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EnableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EnableEp (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char endpoint)   // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_EPEDS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_DisableEp
-//* \brief Enable Endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_DisableEp (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char endpoint)   // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] &= ~AT91C_UDP_EPEDS;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_SetState
-//* \brief Set UDP Device state
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_SetState (
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg new UDP address
-{
-	pUDP->UDP_GLBSTATE  &= ~(AT91C_UDP_FADDEN | AT91C_UDP_CONFG);
-	pUDP->UDP_GLBSTATE  |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_GetState
-//* \brief return UDP Device state
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_GetState ( // \return the UDP device state
-	AT91PS_UDP pUDP)     // \arg pointer to a UDP controller
-{
-	return (pUDP->UDP_GLBSTATE  & (AT91C_UDP_FADDEN | AT91C_UDP_CONFG));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_ResetEp
-//* \brief Reset UDP endpoint
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_ResetEp ( // \return the UDP device state
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned int flag)   // \arg Endpoints to be reset
-{
-	pUDP->UDP_RSTEP = flag;
-	pUDP->UDP_RSTEP = 0;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpStall
-//* \brief Endpoint will STALL requests
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpStall(
-	AT91PS_UDP pUDP,     // \arg pointer to a UDP controller
-	unsigned char endpoint)   // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_FORCESTALL;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpWrite
-//* \brief Write value in the DPR
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpWrite(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned char value)     // \arg value to be written in the DPR
-{
-	pUDP->UDP_FDR[endpoint] = value;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpRead
-//* \brief Return value from the DPR
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_EpRead(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	return pUDP->UDP_FDR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpEndOfWr
-//* \brief Notify the UDP that values in DPR are ready to be sent
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpEndOfWr(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	pUDP->UDP_CSR[endpoint] |= AT91C_UDP_TXPKTRDY;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpClear
-//* \brief Clear flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpClear(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned int flag)       // \arg flag to be cleared
-{
-	pUDP->UDP_CSR[endpoint] &= ~(flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpSet
-//* \brief Set flag in the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_EpSet(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint,  // \arg endpoint number
-	unsigned int flag)       // \arg flag to be cleared
-{
-	pUDP->UDP_CSR[endpoint] |= flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_EpStatus
-//* \brief Return the endpoint CSR register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_EpStatus(
-	AT91PS_UDP pUDP,         // \arg pointer to a UDP controller
-	unsigned char endpoint)  // \arg endpoint number
-{
-	return pUDP->UDP_CSR[endpoint];
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_GetInterruptMaskStatus
-//* \brief Return UDP Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_UDP_GetInterruptMaskStatus( // \return UDP Interrupt Mask Status
-        AT91PS_UDP pUdp) // \arg  pointer to a UDP controller
-{
-        return pUdp->UDP_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_IsInterruptMasked
-//* \brief Test if UDP Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_UDP_IsInterruptMasked(
-        AT91PS_UDP pUdp,   // \arg  pointer to a UDP controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_UDP_GetInterruptMaskStatus(pUdp) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR TC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_InterruptEnable
-//* \brief Enable TC Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC_InterruptEnable(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  TC interrupt to be enabled
-{
-        pTc->TC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_InterruptDisable
-//* \brief Disable TC Interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC_InterruptDisable(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  TC interrupt to be disabled
-{
-        pTc->TC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_GetInterruptMaskStatus
-//* \brief Return TC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TC_GetInterruptMaskStatus( // \return TC Interrupt Mask Status
-        AT91PS_TC pTc) // \arg  pointer to a TC controller
-{
-        return pTc->TC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC_IsInterruptMasked
-//* \brief Test if TC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline int AT91F_TC_IsInterruptMasked(
-        AT91PS_TC pTc,   // \arg  pointer to a TC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-        return (AT91F_TC_GetInterruptMaskStatus(pTc) & flag);
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR CAN
-   ***************************************************************************** */
-#define	STANDARD_FORMAT 0
-#define	EXTENDED_FORMAT 1
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_InitMailboxRegisters()
-//* \brief Configure the corresponding mailbox
-//*----------------------------------------------------------------------------
-__inline void AT91F_InitMailboxRegisters(AT91PS_CAN_MB	CAN_Mailbox,
-								int  			mode_reg,
-								int 			acceptance_mask_reg,
-								int  			id_reg,
-								int  			data_low_reg,
-								int  			data_high_reg,
-								int  			control_reg)
-{
-	CAN_Mailbox->CAN_MB_MCR 	= 0x0;
-	CAN_Mailbox->CAN_MB_MMR 	= mode_reg;
-	CAN_Mailbox->CAN_MB_MAM 	= acceptance_mask_reg;
-	CAN_Mailbox->CAN_MB_MID 	= id_reg;
-	CAN_Mailbox->CAN_MB_MDL 	= data_low_reg; 		
-	CAN_Mailbox->CAN_MB_MDH 	= data_high_reg;
-	CAN_Mailbox->CAN_MB_MCR 	= control_reg;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_EnableCAN()
-//* \brief
-//*----------------------------------------------------------------------------
-__inline void AT91F_EnableCAN(
-	AT91PS_CAN pCAN)     // pointer to a CAN controller
-{
-	pCAN->CAN_MR |= AT91C_CAN_CANEN;
-
-	// Wait for WAKEUP flag raising <=> 11-recessive-bit were scanned by the transceiver
-	while( (pCAN->CAN_SR & AT91C_CAN_WAKEUP) != AT91C_CAN_WAKEUP );
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DisableCAN()
-//* \brief
-//*----------------------------------------------------------------------------
-__inline void AT91F_DisableCAN(
-	AT91PS_CAN pCAN)     // pointer to a CAN controller
-{
-	pCAN->CAN_MR &= ~AT91C_CAN_CANEN;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_EnableIt
-//* \brief Enable CAN interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_EnableIt (
-	AT91PS_CAN pCAN,     // pointer to a CAN controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pCAN->CAN_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_DisableIt
-//* \brief Disable CAN interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_DisableIt (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pCAN->CAN_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetStatus
-//* \brief Return CAN Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetStatus( // \return CAN Interrupt Status
-	AT91PS_CAN pCAN) // pointer to a CAN controller
-{
-	return pCAN->CAN_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetInterruptMaskStatus
-//* \brief Return CAN Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetInterruptMaskStatus( // \return CAN Interrupt Mask Status
-	AT91PS_CAN pCAN) // pointer to a CAN controller
-{
-	return pCAN->CAN_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_IsInterruptMasked
-//* \brief Test if CAN Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_IsInterruptMasked(
-        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_CAN_GetInterruptMaskStatus(pCAN) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_IsStatusSet
-//* \brief Test if CAN Interrupt is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_IsStatusSet(
-        AT91PS_CAN pCAN,   // \arg  pointer to a CAN controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_CAN_GetStatus(pCAN) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgModeReg
-//* \brief Configure the Mode Register of the CAN controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgModeReg (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-	unsigned int mode)        // mode register
-{
-	//* Write to the MR register
-	pCAN->CAN_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetModeReg
-//* \brief Return the Mode Register of the CAN controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetModeReg (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_MR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgBaudrateReg
-//* \brief Configure the Baudrate of the CAN controller for the network
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgBaudrateReg (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-	unsigned int baudrate_cfg)
-{
-	//* Write to the BR register
-	pCAN->CAN_BR = baudrate_cfg;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetBaudrate
-//* \brief Return the Baudrate of the CAN controller for the network value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetBaudrate (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_BR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetInternalCounter
-//* \brief Return CAN Timer Regsiter Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetInternalCounter (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_TIM;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetTimestamp
-//* \brief Return CAN Timestamp Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetTimestamp (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_TIMESTP;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetErrorCounter
-//* \brief Return CAN Error Counter Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetErrorCounter (
-	AT91PS_CAN pCAN // pointer to a CAN controller
-	)
-{
-	return pCAN->CAN_ECR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_InitTransferRequest
-//* \brief Request for a transfer on the corresponding mailboxes
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_InitTransferRequest (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-    unsigned int transfer_cmd)
-{
-	pCAN->CAN_TCR = transfer_cmd;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_InitAbortRequest
-//* \brief Abort the corresponding mailboxes
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_InitAbortRequest (
-	AT91PS_CAN pCAN, // pointer to a CAN controller
-    unsigned int abort_cmd)
-{
-	pCAN->CAN_ACR = abort_cmd;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageModeReg
-//* \brief Program the Message Mode Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageModeReg (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int mode)
-{
-	CAN_Mailbox->CAN_MB_MMR = mode;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageModeReg
-//* \brief Return the Message Mode Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageModeReg (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MMR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageIDReg
-//* \brief Program the Message ID Register
-//* \brief Version == 0 for Standard messsage, Version == 1 for Extended
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageIDReg (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int id,
-    unsigned char version)
-{
-	if(version==0)	// IDvA Standard Format
-		CAN_Mailbox->CAN_MB_MID = id<<18;
-	else	// IDvB Extended Format
-		CAN_Mailbox->CAN_MB_MID = id | (1<<29);	// set MIDE bit
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageIDReg
-//* \brief Return the Message ID Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageIDReg (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MID;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageAcceptanceMaskReg
-//* \brief Program the Message Acceptance Mask Register
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageAcceptanceMaskReg (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int mask)
-{
-	CAN_Mailbox->CAN_MB_MAM = mask;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageAcceptanceMaskReg
-//* \brief Return the Message Acceptance Mask Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageAcceptanceMaskReg (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MAM;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetFamilyID
-//* \brief Return the Message ID Register
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetFamilyID (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MFID;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageCtrl
-//* \brief Request and config for a transfer on the corresponding mailbox
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageCtrlReg (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int message_ctrl_cmd)
-{
-	CAN_Mailbox->CAN_MB_MCR = message_ctrl_cmd;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageStatus
-//* \brief Return CAN Mailbox Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageStatus (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MSR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageDataLow
-//* \brief Program data low value
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageDataLow (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int data)
-{
-	CAN_Mailbox->CAN_MB_MDL = data;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageDataLow
-//* \brief Return data low value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageDataLow (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MDL;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgMessageDataHigh
-//* \brief Program data high value
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgMessageDataHigh (
-	AT91PS_CAN_MB	CAN_Mailbox, // pointer to a CAN Mailbox
-    unsigned int data)
-{
-	CAN_Mailbox->CAN_MB_MDH = data;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_GetMessageDataHigh
-//* \brief Return data high value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_GetMessageDataHigh (
-	AT91PS_CAN_MB	CAN_Mailbox) // pointer to a CAN Mailbox
-{
-	return CAN_Mailbox->CAN_MB_MDH;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_Open
-//* \brief Open a CAN Port
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_CAN_Open (
-        const unsigned int null)  // \arg
-{
-        /* NOT DEFINED AT THIS MOMENT */
-        return ( 0 );
-}
-/* *****************************************************************************
-                SOFTWARE API FOR ADC
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_EnableIt
-//* \brief Enable ADC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_EnableIt (
-	AT91PS_ADC pADC,     // pointer to a ADC controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pADC->ADC_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_DisableIt
-//* \brief Disable ADC interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_DisableIt (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pADC->ADC_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetStatus
-//* \brief Return ADC Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetStatus( // \return ADC Interrupt Status
-	AT91PS_ADC pADC) // pointer to a ADC controller
-{
-	return pADC->ADC_SR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetInterruptMaskStatus
-//* \brief Return ADC Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetInterruptMaskStatus( // \return ADC Interrupt Mask Status
-	AT91PS_ADC pADC) // pointer to a ADC controller
-{
-	return pADC->ADC_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_IsInterruptMasked
-//* \brief Test if ADC Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_IsInterruptMasked(
-        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_ADC_GetInterruptMaskStatus(pADC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_IsStatusSet
-//* \brief Test if ADC Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_IsStatusSet(
-        AT91PS_ADC pADC,   // \arg  pointer to a ADC controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_ADC_GetStatus(pADC) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgModeReg
-//* \brief Configure the Mode Register of the ADC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgModeReg (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int mode)        // mode register
-{
-	//* Write to the MR register
-	pADC->ADC_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetModeReg
-//* \brief Return the Mode Register of the ADC controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetModeReg (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_MR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgTimings
-//* \brief Configure the different necessary timings of the ADC controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgTimings (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int mck_clock, // in MHz
-	unsigned int adc_clock, // in MHz
-	unsigned int startup_time, // in us
-	unsigned int sample_and_hold_time)	// in ns
-{
-	unsigned int prescal,startup,shtim;
-	
-	prescal = mck_clock/(2*adc_clock) - 1;
-	startup = adc_clock*startup_time/8 - 1;
-	shtim = adc_clock*sample_and_hold_time/1000 - 1;
-	
-	//* Write to the MR register
-	pADC->ADC_MR = ( (prescal<<8) & AT91C_ADC_PRESCAL) | ( (startup<<16) & AT91C_ADC_STARTUP) | ( (shtim<<24) & AT91C_ADC_SHTIM);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_EnableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_EnableChannel (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int channel)        // mode register
-{
-	//* Write to the CHER register
-	pADC->ADC_CHER = channel;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_DisableChannel
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_DisableChannel (
-	AT91PS_ADC pADC, // pointer to a ADC controller
-	unsigned int channel)        // mode register
-{
-	//* Write to the CHDR register
-	pADC->ADC_CHDR = channel;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetChannelStatus
-//* \brief Return ADC Timer Register Value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetChannelStatus (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CHSR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_StartConversion
-//* \brief Software request for a analog to digital conversion
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_StartConversion (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	pADC->ADC_CR = AT91C_ADC_START;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_SoftReset
-//* \brief Software reset
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_SoftReset (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	pADC->ADC_CR = AT91C_ADC_SWRST;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetLastConvertedData
-//* \brief Return the Last Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetLastConvertedData (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_LCDR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH0
-//* \brief Return the Channel 0 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH0 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR0;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH1
-//* \brief Return the Channel 1 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH1 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR1;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH2
-//* \brief Return the Channel 2 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH2 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR2;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH3
-//* \brief Return the Channel 3 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH3 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR3;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH4
-//* \brief Return the Channel 4 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH4 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR4;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH5
-//* \brief Return the Channel 5 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH5 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR5;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH6
-//* \brief Return the Channel 6 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH6 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR6;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_GetConvertedDataCH7
-//* \brief Return the Channel 7 Converted Data
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_ADC_GetConvertedDataCH7 (
-	AT91PS_ADC pADC // pointer to a ADC controller
-	)
-{
-	return pADC->ADC_CDR7;	
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR AES
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_EnableIt
-//* \brief Enable AES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_EnableIt (
-	AT91PS_AES pAES,     // pointer to a AES controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pAES->AES_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_DisableIt
-//* \brief Disable AES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_DisableIt (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pAES->AES_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_GetStatus
-//* \brief Return AES Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetStatus( // \return AES Interrupt Status
-	AT91PS_AES pAES) // pointer to a AES controller
-{
-	return pAES->AES_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_GetInterruptMaskStatus
-//* \brief Return AES Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetInterruptMaskStatus( // \return AES Interrupt Mask Status
-	AT91PS_AES pAES) // pointer to a AES controller
-{
-	return pAES->AES_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_IsInterruptMasked
-//* \brief Test if AES Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_IsInterruptMasked(
-        AT91PS_AES pAES,   // \arg  pointer to a AES controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_AES_GetInterruptMaskStatus(pAES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_IsStatusSet
-//* \brief Test if AES Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_IsStatusSet(
-        AT91PS_AES pAES,   // \arg  pointer to a AES controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_AES_GetStatus(pAES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_CfgModeReg
-//* \brief Configure the Mode Register of the AES controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_CfgModeReg (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned int mode)        // mode register
-{
-	//* Write to the MR register
-	pAES->AES_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_GetModeReg
-//* \brief Return the Mode Register of the AES controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetModeReg (
-	AT91PS_AES pAES // pointer to a AES controller
-	)
-{
-	return pAES->AES_MR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_StartProcessing
-//* \brief Start Encryption or Decryption
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_StartProcessing (
-	AT91PS_AES pAES // pointer to a AES controller
-	)
-{
-	pAES->AES_CR = AT91C_AES_START;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_SoftReset
-//* \brief Reset AES
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_SoftReset (
-	AT91PS_AES pAES // pointer to a AES controller
-	)
-{
-	pAES->AES_CR = AT91C_AES_SWRST;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_LoadNewSeed
-//* \brief Load New Seed in the random number generator
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_LoadNewSeed (
-	AT91PS_AES pAES // pointer to a AES controller
-	)
-{
-	pAES->AES_CR = AT91C_AES_LOADSEED;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_SetCryptoKey
-//* \brief Set Cryptographic Key x
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_SetCryptoKey (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned char index,
-	unsigned int keyword
-	)
-{
-	pAES->AES_KEYWxR[index] = keyword;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_InputData
-//* \brief Set Input Data x
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_InputData (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned char index,
-	unsigned int indata
-	)
-{
-	pAES->AES_IDATAxR[index] = indata;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_GetOutputData
-//* \brief Get Output Data x
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_AES_GetOutputData (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned char index
-	)
-{
-	return pAES->AES_ODATAxR[index];	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_SetInitializationVector
-//* \brief Set Initialization Vector (or Counter) x
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_SetInitializationVector (
-	AT91PS_AES pAES, // pointer to a AES controller
-	unsigned char index,
-	unsigned int initvector
-	)
-{
-	pAES->AES_IVxR[index] = initvector;	
-}
-
-/* *****************************************************************************
-                SOFTWARE API FOR TDES
-   ***************************************************************************** */
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_EnableIt
-//* \brief Enable TDES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_EnableIt (
-	AT91PS_TDES pTDES,     // pointer to a TDES controller
-	unsigned int flag)   // IT to be enabled
-{
-	//* Write to the IER register
-	pTDES->TDES_IER = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_DisableIt
-//* \brief Disable TDES interrupt
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_DisableIt (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned int flag) // IT to be disabled
-{
-	//* Write to the IDR register
-	pTDES->TDES_IDR = flag;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_GetStatus
-//* \brief Return TDES Interrupt Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetStatus( // \return TDES Interrupt Status
-	AT91PS_TDES pTDES) // pointer to a TDES controller
-{
-	return pTDES->TDES_ISR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_GetInterruptMaskStatus
-//* \brief Return TDES Interrupt Mask Status
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetInterruptMaskStatus( // \return TDES Interrupt Mask Status
-	AT91PS_TDES pTDES) // pointer to a TDES controller
-{
-	return pTDES->TDES_IMR;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_IsInterruptMasked
-//* \brief Test if TDES Interrupt is Masked
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_IsInterruptMasked(
-        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_TDES_GetInterruptMaskStatus(pTDES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_IsStatusSet
-//* \brief Test if TDES Status is Set
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_IsStatusSet(
-        AT91PS_TDES pTDES,   // \arg  pointer to a TDES controller
-        unsigned int flag) // \arg  flag to be tested
-{
-	return (AT91F_TDES_GetStatus(pTDES) & flag);
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_CfgModeReg
-//* \brief Configure the Mode Register of the TDES controller
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_CfgModeReg (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned int mode)        // mode register
-{
-	//* Write to the MR register
-	pTDES->TDES_MR = mode;
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_GetModeReg
-//* \brief Return the Mode Register of the TDES controller value
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetModeReg (
-	AT91PS_TDES pTDES // pointer to a TDES controller
-	)
-{
-	return pTDES->TDES_MR;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_StartProcessing
-//* \brief Start Encryption or Decryption
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_StartProcessing (
-	AT91PS_TDES pTDES // pointer to a TDES controller
-	)
-{
-	pTDES->TDES_CR = AT91C_TDES_START;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SoftReset
-//* \brief Reset TDES
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SoftReset (
-	AT91PS_TDES pTDES // pointer to a TDES controller
-	)
-{
-	pTDES->TDES_CR = AT91C_TDES_SWRST;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SetCryptoKey1
-//* \brief Set Cryptographic Key 1 Word x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetCryptoKey1 (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int keyword
-	)
-{
-	pTDES->TDES_KEY1WxR[index] = keyword;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SetCryptoKey2
-//* \brief Set Cryptographic Key 2 Word x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetCryptoKey2 (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int keyword
-	)
-{
-	pTDES->TDES_KEY2WxR[index] = keyword;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SetCryptoKey3
-//* \brief Set Cryptographic Key 3 Word x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetCryptoKey3 (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int keyword
-	)
-{
-	pTDES->TDES_KEY3WxR[index] = keyword;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_InputData
-//* \brief Set Input Data x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_InputData (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int indata
-	)
-{
-	pTDES->TDES_IDATAxR[index] = indata;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_GetOutputData
-//* \brief Get Output Data x
-//*----------------------------------------------------------------------------
-__inline unsigned int AT91F_TDES_GetOutputData (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index
-	)
-{
-	return pTDES->TDES_ODATAxR[index];	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_SetInitializationVector
-//* \brief Set Initialization Vector x
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_SetInitializationVector (
-	AT91PS_TDES pTDES, // pointer to a TDES controller
-	unsigned char index,
-	unsigned int initvector
-	)
-{
-	pTDES->TDES_IVxR[index] = initvector;	
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  DBGU
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_DBGU_CfgPIO
-//* \brief Configure PIO controllers to drive DBGU signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_DBGU_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA27_DRXD    ) |
-		((unsigned int) AT91C_PA28_DTXD    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PMC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PMC_CfgPIO
-//* \brief Configure PIO controllers to drive PMC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PMC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB30_PCK2    ) |
-		((unsigned int) AT91C_PB29_PCK1    ), // Peripheral A
-		((unsigned int) AT91C_PB20_PCK0    ) |
-		((unsigned int) AT91C_PB0_PCK0    ) |
-		((unsigned int) AT91C_PB22_PCK2    ) |
-		((unsigned int) AT91C_PB21_PCK1    )); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA30_PCK2    ) |
-		((unsigned int) AT91C_PA13_PCK1    ) |
-		((unsigned int) AT91C_PA27_PCK3    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_VREG_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  VREG
-//*----------------------------------------------------------------------------
-__inline void AT91F_VREG_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RSTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  RSTC
-//*----------------------------------------------------------------------------
-__inline void AT91F_RSTC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SSC
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SSC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SSC_CfgPIO
-//* \brief Configure PIO controllers to drive SSC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SSC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA25_RK      ) |
-		((unsigned int) AT91C_PA22_TK      ) |
-		((unsigned int) AT91C_PA21_TF      ) |
-		((unsigned int) AT91C_PA24_RD      ) |
-		((unsigned int) AT91C_PA26_RF      ) |
-		((unsigned int) AT91C_PA23_TD      ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_WDTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  WDTC
-//*----------------------------------------------------------------------------
-__inline void AT91F_WDTC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US1
-//*----------------------------------------------------------------------------
-__inline void AT91F_US1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_US1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US1_CfgPIO
-//* \brief Configure PIO controllers to drive US1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_US1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PB26_RI1     ) |
-		((unsigned int) AT91C_PB24_DSR1    ) |
-		((unsigned int) AT91C_PB23_DCD1    ) |
-		((unsigned int) AT91C_PB25_DTR1    )); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA7_SCK1    ) |
-		((unsigned int) AT91C_PA8_RTS1    ) |
-		((unsigned int) AT91C_PA6_TXD1    ) |
-		((unsigned int) AT91C_PA5_RXD1    ) |
-		((unsigned int) AT91C_PA9_CTS1    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  US0
-//*----------------------------------------------------------------------------
-__inline void AT91F_US0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_US0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_US0_CfgPIO
-//* \brief Configure PIO controllers to drive US0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_US0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA0_RXD0    ) |
-		((unsigned int) AT91C_PA4_CTS0    ) |
-		((unsigned int) AT91C_PA3_RTS0    ) |
-		((unsigned int) AT91C_PA2_SCK0    ) |
-		((unsigned int) AT91C_PA1_TXD0    ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SPI1
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SPI1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI1_CfgPIO
-//* \brief Configure PIO controllers to drive SPI1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PB16_NPCS13  ) |
-		((unsigned int) AT91C_PB10_NPCS11  ) |
-		((unsigned int) AT91C_PB11_NPCS12  )); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA4_NPCS13  ) |
-		((unsigned int) AT91C_PA29_NPCS13  ) |
-		((unsigned int) AT91C_PA21_NPCS10  ) |
-		((unsigned int) AT91C_PA22_SPCK1   ) |
-		((unsigned int) AT91C_PA25_NPCS11  ) |
-		((unsigned int) AT91C_PA2_NPCS11  ) |
-		((unsigned int) AT91C_PA24_MISO1   ) |
-		((unsigned int) AT91C_PA3_NPCS12  ) |
-		((unsigned int) AT91C_PA26_NPCS12  ) |
-		((unsigned int) AT91C_PA23_MOSI1   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  SPI0
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SPI0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_SPI0_CfgPIO
-//* \brief Configure PIO controllers to drive SPI0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_SPI0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PB13_NPCS01  ) |
-		((unsigned int) AT91C_PB17_NPCS03  ) |
-		((unsigned int) AT91C_PB14_NPCS02  )); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA16_MISO0   ) |
-		((unsigned int) AT91C_PA13_NPCS01  ) |
-		((unsigned int) AT91C_PA15_NPCS03  ) |
-		((unsigned int) AT91C_PA17_MOSI0   ) |
-		((unsigned int) AT91C_PA18_SPCK0   ) |
-		((unsigned int) AT91C_PA14_NPCS02  ) |
-		((unsigned int) AT91C_PA12_NPCS00  ), // Peripheral A
-		((unsigned int) AT91C_PA7_NPCS01  ) |
-		((unsigned int) AT91C_PA9_NPCS03  ) |
-		((unsigned int) AT91C_PA8_NPCS02  )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PITC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PITC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PITC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  AIC
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_FIQ) |
-		((unsigned int) 1 << AT91C_ID_IRQ0) |
-		((unsigned int) 1 << AT91C_ID_IRQ1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AIC_CfgPIO
-//* \brief Configure PIO controllers to drive AIC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_AIC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA30_IRQ0    ) |
-		((unsigned int) AT91C_PA29_FIQ     ), // Peripheral A
-		((unsigned int) AT91C_PA14_IRQ1    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_AES_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  AES
-//*----------------------------------------------------------------------------
-__inline void AT91F_AES_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_AES));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TWI
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TWI));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TWI_CfgPIO
-//* \brief Configure PIO controllers to drive TWI signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TWI_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA11_TWCK    ) |
-		((unsigned int) AT91C_PA10_TWD     ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  ADC
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_ADC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_ADC_CfgPIO
-//* \brief Configure PIO controllers to drive ADC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_ADC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PB18_ADTRG   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH3_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH3 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH3_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB22_PWM3    ), // Peripheral A
-		((unsigned int) AT91C_PB30_PWM3    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH2_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH2 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH2_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB21_PWM2    ), // Peripheral A
-		((unsigned int) AT91C_PB29_PWM2    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH1_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB20_PWM1    ), // Peripheral A
-		((unsigned int) AT91C_PB28_PWM1    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CH0_CfgPIO
-//* \brief Configure PIO controllers to drive PWMC_CH0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CH0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB19_PWM0    ), // Peripheral A
-		((unsigned int) AT91C_PB27_PWM0    )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_RTTC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  RTTC
-//*----------------------------------------------------------------------------
-__inline void AT91F_RTTC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_UDP_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  UDP
-//*----------------------------------------------------------------------------
-__inline void AT91F_UDP_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_UDP));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TDES_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TDES
-//*----------------------------------------------------------------------------
-__inline void AT91F_TDES_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TDES));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_EMAC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  EMAC
-//*----------------------------------------------------------------------------
-__inline void AT91F_EMAC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_EMAC));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_EMAC_CfgPIO
-//* \brief Configure PIO controllers to drive EMAC signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_EMAC_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB2_ETX0    ) |
-		((unsigned int) AT91C_PB12_ETXER   ) |
-		((unsigned int) AT91C_PB16_ECOL    ) |
-		((unsigned int) AT91C_PB11_ETX3    ) |
-		((unsigned int) AT91C_PB6_ERX1    ) |
-		((unsigned int) AT91C_PB15_ERXDV   ) |
-		((unsigned int) AT91C_PB13_ERX2    ) |
-		((unsigned int) AT91C_PB3_ETX1    ) |
-		((unsigned int) AT91C_PB8_EMDC    ) |
-		((unsigned int) AT91C_PB5_ERX0    ) |
-		//((unsigned int) AT91C_PB18_EF100   ) |
-		((unsigned int) AT91C_PB14_ERX3    ) |
-		((unsigned int) AT91C_PB4_ECRS_ECRSDV) |
-		((unsigned int) AT91C_PB1_ETXEN   ) |
-		((unsigned int) AT91C_PB10_ETX2    ) |
-		((unsigned int) AT91C_PB0_ETXCK_EREFCK) |
-		((unsigned int) AT91C_PB9_EMDIO   ) |
-		((unsigned int) AT91C_PB7_ERXER   ) |
-		((unsigned int) AT91C_PB17_ERXCK   ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC0_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC0
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC0_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC0));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC0_CfgPIO
-//* \brief Configure PIO controllers to drive TC0 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC0_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB23_TIOA0   ) |
-		((unsigned int) AT91C_PB24_TIOB0   ), // Peripheral A
-		((unsigned int) AT91C_PB12_TCLK0   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC1_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC1
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC1_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC1));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC1_CfgPIO
-//* \brief Configure PIO controllers to drive TC1 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC1_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB25_TIOA1   ) |
-		((unsigned int) AT91C_PB26_TIOB1   ), // Peripheral A
-		((unsigned int) AT91C_PB19_TCLK1   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC2_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  TC2
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC2_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_TC2));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_TC2_CfgPIO
-//* \brief Configure PIO controllers to drive TC2 signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_TC2_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOB, // PIO controller base address
-		((unsigned int) AT91C_PB28_TIOB2   ) |
-		((unsigned int) AT91C_PB27_TIOA2   ), // Peripheral A
-		0); // Peripheral B
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		0, // Peripheral A
-		((unsigned int) AT91C_PA15_TCLK2   )); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_MC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  MC
-//*----------------------------------------------------------------------------
-__inline void AT91F_MC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_SYS));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIOA_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PIOA
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIOA_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PIOA));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PIOB_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PIOB
-//*----------------------------------------------------------------------------
-__inline void AT91F_PIOB_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PIOB));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  CAN
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_CAN));
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_CAN_CfgPIO
-//* \brief Configure PIO controllers to drive CAN signals
-//*----------------------------------------------------------------------------
-__inline void AT91F_CAN_CfgPIO (void)
-{
-	// Configure PIO controllers to periph mode
-	AT91F_PIO_CfgPeriph(
-		AT91C_BASE_PIOA, // PIO controller base address
-		((unsigned int) AT91C_PA20_CANTX   ) |
-		((unsigned int) AT91C_PA19_CANRX   ), // Peripheral A
-		0); // Peripheral B
-}
-
-//*----------------------------------------------------------------------------
-//* \fn    AT91F_PWMC_CfgPMC
-//* \brief Enable Peripheral clock in PMC for  PWMC
-//*----------------------------------------------------------------------------
-__inline void AT91F_PWMC_CfgPMC (void)
-{
-	AT91F_PMC_EnablePeriphClock(
-		AT91C_BASE_PMC, // PIO controller base address
-		((unsigned int) 1 << AT91C_ID_PWMC));
-}
-
-#endif // lib_AT91SAM7X256_H
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/port.c b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/port.c
deleted file mode 100755
index 8e6152d..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/port.c
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Atmel ARM7 port.
- *----------------------------------------------------------*/
-
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
-
-/* Constants required to setup the PIT. */
-#define portPIT_CLOCK_DIVISOR			( ( uint32_t ) 16 )
-#define portPIT_COUNTER_VALUE			( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
-
-
-#define portINT_LEVEL_SENSITIVE  0
-#define portPIT_ENABLE      	( ( uint16_t ) 0x1 << 24 )
-#define portPIT_INT_ENABLE     	( ( uint16_t ) 0x1 << 25 )
-/*-----------------------------------------------------------*/
-
-/* Setup the PIT to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/* ulCriticalNesting will get set to zero when the first task starts.  It
-cannot be initialised to 0 as this will cause interrupts to be enabled
-during the kernel initialisation process. */
-uint32_t ulCriticalNesting = ( uint32_t ) 9999;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
-	pxOriginalTOS = pxTopOfStack;
-
-	/* To ensure asserts in tasks.c don't fail, although in this case the assert
-	is not really required. */
-	pxTopOfStack--;
-
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* First on the stack is the return address - which in this case is the
-	start of the task.  The offset is added to make the return address appear
-	as it would within an IRQ ISR. */
-	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;	
-
-	/* When the task starts is will expect to find the function parameter in
-	R0. */
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The status register is set for system mode, with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-	
-	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
-	{
-		/* We want the task to start in thumb mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}	
-	
-	pxTopOfStack--;
-
-	/* Interrupt flags cannot always be stored on the stack and will
-	instead be stored in a variable, which is then saved as part of the
-	tasks context. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-
-	return pxTopOfStack;	
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortStartFirstTask( void );
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task. */
-	vPortStartFirstTask();	
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the ARM port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_PREEMPTION == 0
-
-	/* The cooperative scheduler requires a normal IRQ service routine to
-	simply increment the system tick. */
-	static __arm __irq void vPortNonPreemptiveTick( void );
-	static __arm __irq void vPortNonPreemptiveTick( void )
-	{
-		uint32_t ulDummy;
-		
-		/* Increment the tick count - which may wake some tasks but as the
-		preemptive scheduler is not being used any woken task is not given
-		processor time no matter what its priority. */
-		xTaskIncrementTick();
-		
-		/* Clear the PIT interrupt. */
-		ulDummy = AT91C_BASE_PITC->PITC_PIVR;
-		
-		/* End the interrupt in the AIC. */
-		AT91C_BASE_AIC->AIC_EOICR = ulDummy;
-	}
-
-#else
-
-	/* Currently the IAR port requires the preemptive tick function to be
-	defined in an asm file. */
-
-#endif
-
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-AT91PS_PITC pxPIT = AT91C_BASE_PITC;
-
-	/* Setup the AIC for PIT interrupts.  The interrupt routine chosen depends
-	on whether the preemptive or cooperative scheduler is being used. */
-	#if configUSE_PREEMPTION == 0
-
-		AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortNonPreemptiveTick );
-
-	#else
-		
-		extern void ( vPortPreemptiveTick )( void );
-		AT91F_AIC_ConfigureIt( AT91C_BASE_AIC, AT91C_ID_SYS, AT91C_AIC_PRIOR_HIGHEST, portINT_LEVEL_SENSITIVE, ( void (*)(void) ) vPortPreemptiveTick );
-
-	#endif
-
-	/* Configure the PIT period. */
-	pxPIT->PITC_PIMR = portPIT_ENABLE | portPIT_INT_ENABLE | portPIT_COUNTER_VALUE;
-
-	/* Enable the interrupt.  Global interrupts are disables at this point so
-	this is safe. */
-	AT91F_AIC_EnableIt( AT91C_BASE_AIC, AT91C_ID_SYS );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	/* Disable interrupts first! */
-	__disable_interrupt();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as we are leaving a critical section. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then interrupts should be
-		re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			__enable_interrupt();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79 b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79
deleted file mode 100755
index 9a2ca89..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portasm.s79
+++ /dev/null
@@ -1,88 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-		RSEG ICODE:CODE
-		CODE32
-
-	EXTERN vTaskSwitchContext
-	EXTERN xTaskIncrementTick
-
-	PUBLIC vPortYieldProcessor
-	PUBLIC vPortPreemptiveTick
-	PUBLIC vPortStartFirstTask
-
-#include "AT91SAM7S64_inc.h"
-#include "ISR_Support.h"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Starting the first task is just a matter of restoring the context that
-; was created by pxPortInitialiseStack().
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortStartFirstTask:
-	portRESTORE_CONTEXT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Manual context switch function.  This is the SWI hander.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortYieldProcessor:
-	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
-								; as if the context was saved during and IRQ
-								; handler.
-
-	portSAVE_CONTEXT			; Save the context of the current task...
-	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
-	mov     lr, pc
-	BX R0
-	portRESTORE_CONTEXT			; Restore the context of the selected task.
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Preemptive context switch function.  This will only ever get installed if
-; portUSE_PREEMPTION is set to 1 in portmacro.h.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortPreemptiveTick:
-	portSAVE_CONTEXT			; Save the context of the current task.
-
-	LDR R0, =xTaskIncrementTick ; Increment the tick count - this may wake a task.
-	mov lr, pc
-	BX R0
-
-	CMP R0, #0
-	BEQ SkipContextSwitch
-	LDR R0, =vTaskSwitchContext ; Select the next task to execute.
-	mov lr, pc
-	BX R0
-SkipContextSwitch
-	LDR	R14, =AT91C_BASE_PITC	; Clear the PIT interrupt
-	LDR	R0, [R14, #PITC_PIVR ]
-
-	LDR R14, =AT91C_BASE_AIC	; Mark the End of Interrupt on the AIC
-    STR	R14, [R14, #AIC_EOICR]
-
-	portRESTORE_CONTEXT			; Restore the context of the selected task.
-
-
-	END
-
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portmacro.h b/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portmacro.h
deleted file mode 100755
index 605c4d6..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM7S64/portmacro.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-#define portYIELD()					asm ( "SWI 0" )
-#define portNOP()					asm ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-__arm __interwork void vPortDisableInterruptsFromThumb( void );
-__arm __interwork void vPortEnableInterruptsFromThumb( void );
-__arm __interwork void vPortEnterCritical( void );
-__arm __interwork void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()	__disable_interrupt()
-#define portENABLE_INTERRUPTS()		__enable_interrupt()
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
-{													\
-extern void vTaskSwitchContext( void );				\
-													\
-	if( xSwitchRequired ) 							\
-	{												\
-		vTaskSwitchContext();						\
-	}												\
-}
-/*-----------------------------------------------------------*/
-
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
-
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h b/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h
deleted file mode 100755
index 7755c2e..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/ISR_Support.h
+++ /dev/null
@@ -1,78 +0,0 @@
-	EXTERN pxCurrentTCB
-	EXTERN ulCriticalNesting
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-portSAVE_CONTEXT MACRO
-
-	; Push R0 as we are going to use the register. 					
-	STMDB	SP!, {R0}
-
-	; Set R0 to point to the task stack pointer. 					
-	STMDB	SP, {SP}^
-	NOP
-	SUB		SP, SP, #4
-	LDMIA	SP!, {R0}
-
-	; Push the return address onto the stack. 						
-	STMDB	R0!, {LR}
-
-	; Now we have saved LR we can use it instead of R0. 				
-	MOV		LR, R0
-
-	; Pop R0 so we can save it onto the system mode stack. 			
-	LDMIA	SP!, {R0}
-
-	; Push all the system mode registers onto the task stack. 		
-	STMDB	LR, {R0-LR}^
-	NOP
-	SUB		LR, LR, #60
-
-	; Push the SPSR onto the task stack. 							
-	MRS		R0, SPSR
-	STMDB	LR!, {R0}
-
-	LDR		R0, =ulCriticalNesting 
-	LDR		R0, [R0]
-	STMDB	LR!, {R0}
-
-	; Store the new top of stack for the task. 						
-	LDR		R1, =pxCurrentTCB
-	LDR		R0, [R1]
-	STR		LR, [R0]
-
-	ENDM
-
-
-portRESTORE_CONTEXT MACRO
-
-	; Set the LR to the task stack. 									
-	LDR		R1, =pxCurrentTCB
-	LDR		R0, [R1]
-	LDR		LR, [R0]
-
-	; The critical nesting depth is the first item on the stack. 	
-	; Load it into the ulCriticalNesting variable. 					
-	LDR		R0, =ulCriticalNesting
-	LDMFD	LR!, {R1}
-	STR		R1, [R0]
-
-	; Get the SPSR from the stack. 									
-	LDMFD	LR!, {R0}
-	MSR		SPSR_cxsf, R0
-
-	; Restore all system mode registers for the task. 				
-	LDMFD	LR, {R0-R14}^
-	NOP
-
-	; Restore the return address. 									
-	LDR		LR, [LR, #+60]
-
-	; And return - correcting the offset in the LR to obtain the 	
-	; correct address. 												
-	SUBS	PC, LR, #4
-
-	ENDM
-
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/port.c b/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/port.c
deleted file mode 100755
index 68468f9..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/port.c
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Atmel ARM7 port.
- *----------------------------------------------------------*/
-
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Hardware includes. */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-/*-----------------------------------------------------------*/
-
-/* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
-
-/* Constants required to setup the PIT. */
-#define port1MHz_IN_Hz 					( 1000000ul )
-#define port1SECOND_IN_uS				( 1000000.0 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
-
-
-#define portINT_LEVEL_SENSITIVE  0
-#define portPIT_ENABLE      	( ( uint16_t ) 0x1 << 24 )
-#define portPIT_INT_ENABLE     	( ( uint16_t ) 0x1 << 25 )
-/*-----------------------------------------------------------*/
-
-/* Setup the PIT to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/* The PIT interrupt handler - the RTOS tick. */
-static void vPortTickISR( void );
-
-/* ulCriticalNesting will get set to zero when the first task starts.  It
-cannot be initialised to 0 as this will cause interrupts to be enabled
-during the kernel initialisation process. */
-uint32_t ulCriticalNesting = ( uint32_t ) 9999;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
-	pxOriginalTOS = pxTopOfStack;
-
-	/* To ensure asserts in tasks.c don't fail, although in this case the assert
-	is not really required. */
-	pxTopOfStack--;
-
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* First on the stack is the return address - which in this case is the
-	start of the task.  The offset is added to make the return address appear
-	as it would within an IRQ ISR. */
-	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;	
-
-	/* When the task starts is will expect to find the function parameter in
-	R0. */
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The status register is set for system mode, with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-	
-	#ifdef THUMB_INTERWORK
-	{
-		/* We want the task to start in thumb mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-	#endif
-	
-	pxTopOfStack--;
-
-	/* Interrupt flags cannot always be stored on the stack and will
-	instead be stored in a variable, which is then saved as part of the
-	tasks context. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-
-	return pxTopOfStack;	
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortStartFirstTask( void );
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task. */
-	vPortStartFirstTask();	
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the ARM port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-static __arm void vPortTickISR( void )
-{
-volatile uint32_t ulDummy;
-	
-	/* Increment the tick count - which may wake some tasks but as the
-	preemptive scheduler is not being used any woken task is not given
-	processor time no matter what its priority. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		vTaskSwitchContext();
-	}
-		
-	/* Clear the PIT interrupt. */
-	ulDummy = AT91C_BASE_PITC->PITC_PIVR;
-	
-	/* To remove compiler warning. */
-	( void ) ulDummy;
-	
-	/* The AIC is cleared in the asm wrapper, outside of this function. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-const uint32_t ulPeriodIn_uS = ( 1.0 / ( double ) configTICK_RATE_HZ ) * port1SECOND_IN_uS;
-
-	/* Setup the PIT for the required frequency. */
-	PIT_Init( ulPeriodIn_uS, BOARD_MCK / port1MHz_IN_Hz );
-	
-	/* Setup the PIT interrupt. */
-	AIC_DisableIT( AT91C_ID_SYS );
-	AIC_ConfigureIT( AT91C_ID_SYS, AT91C_AIC_PRIOR_LOWEST, vPortTickISR );
-	AIC_EnableIT( AT91C_ID_SYS );
-	PIT_EnableIT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	/* Disable interrupts first! */
-	__disable_irq();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as we are leaving a critical section. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then interrupts should be
-		re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			__enable_irq();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portasm.s79 b/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portasm.s79
deleted file mode 100755
index 9088327..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portasm.s79
+++ /dev/null
@@ -1,34 +0,0 @@
-		RSEG ICODE:CODE
-		CODE32
-
-	EXTERN vTaskSwitchContext
-
-	PUBLIC vPortYieldProcessor
-	PUBLIC vPortStartFirstTask
-
-#include "ISR_Support.h"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Starting the first task is just a matter of restoring the context that
-; was created by pxPortInitialiseStack().
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortStartFirstTask:
-	portRESTORE_CONTEXT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Manual context switch function.  This is the SWI hander.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortYieldProcessor:
-	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
-								; as if the context was saved during and IRQ
-								; handler.
-								
-	portSAVE_CONTEXT			; Save the context of the current task...
-	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
-	mov     lr, pc
-	BX R0
-	portRESTORE_CONTEXT			; Restore the context of the selected task.
-
-
-	END
-
diff --git a/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portmacro.h b/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portmacro.h
deleted file mode 100755
index c20ac28..0000000
--- a/FreeRTOS/Source/portable/IAR/AtmelSAM9XE/portmacro.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-#define portYIELD()					asm ( "SWI 0" )
-#define portNOP()					asm ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-__arm __interwork void vPortDisableInterruptsFromThumb( void );
-__arm __interwork void vPortEnableInterruptsFromThumb( void );
-__arm __interwork void vPortEnterCritical( void );
-__arm __interwork void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()	__disable_irq()
-#define portENABLE_INTERRUPTS()		__enable_irq()
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
-{													\
-extern void vTaskSwitchContext( void );				\
-													\
-	if( xSwitchRequired ) 							\
-	{												\
-		vTaskSwitchContext();						\
-	}												\
-}
-/*-----------------------------------------------------------*/
-
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
-
diff --git a/FreeRTOS/Source/portable/IAR/LPC2000/ISR_Support.h b/FreeRTOS/Source/portable/IAR/LPC2000/ISR_Support.h
deleted file mode 100755
index babc698..0000000
--- a/FreeRTOS/Source/portable/IAR/LPC2000/ISR_Support.h
+++ /dev/null
@@ -1,105 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	EXTERN pxCurrentTCB
-	EXTERN ulCriticalNesting
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-portSAVE_CONTEXT MACRO
-
-	; Push R0 as we are going to use the register.
-	STMDB	SP!, {R0}
-
-	; Set R0 to point to the task stack pointer.
-	STMDB	SP, {SP}^
-	NOP
-	SUB		SP, SP, #4
-	LDMIA	SP!, {R0}
-
-	; Push the return address onto the stack.
-	STMDB	R0!, {LR}
-
-	; Now we have saved LR we can use it instead of R0.
-	MOV		LR, R0
-
-	; Pop R0 so we can save it onto the system mode stack.
-	LDMIA	SP!, {R0}
-
-	; Push all the system mode registers onto the task stack.
-	STMDB	LR, {R0-LR}^
-	NOP
-	SUB		LR, LR, #60
-
-	; Push the SPSR onto the task stack.
-	MRS		R0, SPSR
-	STMDB	LR!, {R0}
-
-	LDR		R0, =ulCriticalNesting
-	LDR		R0, [R0]
-	STMDB	LR!, {R0}
-
-	; Store the new top of stack for the task.
-	LDR		R1, =pxCurrentTCB
-	LDR		R0, [R1]
-	STR		LR, [R0]
-
-	ENDM
-
-
-portRESTORE_CONTEXT MACRO
-
-	; Set the LR to the task stack.
-	LDR		R1, =pxCurrentTCB
-	LDR		R0, [R1]
-	LDR		LR, [R0]
-
-	; The critical nesting depth is the first item on the stack.
-	; Load it into the ulCriticalNesting variable.
-	LDR		R0, =ulCriticalNesting
-	LDMFD	LR!, {R1}
-	STR		R1, [R0]
-
-	; Get the SPSR from the stack.
-	LDMFD	LR!, {R0}
-	MSR		SPSR_cxsf, R0
-
-	; Restore all system mode registers for the task.
-	LDMFD	LR, {R0-R14}^
-	NOP
-
-	; Restore the return address.
-	LDR		LR, [LR, #+60]
-
-	; And return - correcting the offset in the LR to obtain the
-	; correct address.
-	SUBS	PC, LR, #4
-
-	ENDM
-
diff --git a/FreeRTOS/Source/portable/IAR/LPC2000/port.c b/FreeRTOS/Source/portable/IAR/LPC2000/port.c
deleted file mode 100755
index 8829f27..0000000
--- a/FreeRTOS/Source/portable/IAR/LPC2000/port.c
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Philips ARM7 port.
- *----------------------------------------------------------*/
-
-/*
-	Changes from V3.2.2
-
-	+ Bug fix - The prescale value for the timer setup is now written to T0PR
-	  instead of T0PC.  This bug would have had no effect unless a prescale
-	  value was actually used.
-*/
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER			( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE			0x00
-#define portINTERRUPT_ON_MATCH		( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH	( ( uint32_t ) 0x02 )
-
-/* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
-
-/* Constants required to setup the PIT. */
-#define portPIT_CLOCK_DIVISOR			( ( uint32_t ) 16 )
-#define portPIT_COUNTER_VALUE			( ( ( configCPU_CLOCK_HZ / portPIT_CLOCK_DIVISOR ) / 1000UL ) * portTICK_PERIOD_MS )
-
-/* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
-
-
-#define portINT_LEVEL_SENSITIVE  0
-#define portPIT_ENABLE      	( ( uint16_t ) 0x1 << 24 )
-#define portPIT_INT_ENABLE     	( ( uint16_t ) 0x1 << 25 )
-
-/* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL		( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT	( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE		( ( uint32_t ) 0x0020 )
-
-/*-----------------------------------------------------------*/
-
-/* Setup the PIT to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/* ulCriticalNesting will get set to zero when the first task starts.  It
-cannot be initialised to 0 as this will cause interrupts to be enabled
-during the kernel initialisation process. */
-uint32_t ulCriticalNesting = ( uint32_t ) 9999;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
-	pxOriginalTOS = pxTopOfStack;
-
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* First on the stack is the return address - which in this case is the
-	start of the task.  The offset is added to make the return address appear
-	as it would within an IRQ ISR. */
-	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;	
-
-	/* When the task starts is will expect to find the function parameter in
-	R0. */
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The status register is set for system mode, with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-	
-	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
-	{
-		/* We want the task to start in thumb mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-	
-	pxTopOfStack--;
-
-	/* Interrupt flags cannot always be stored on the stack and will
-	instead be stored in a variable, which is then saved as part of the
-	tasks context. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-
-	return pxTopOfStack;	
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortStartFirstTask( void );
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task. */
-	vPortStartFirstTask();	
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the ARM port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_PREEMPTION == 0
-
-	/* The cooperative scheduler requires a normal IRQ service routine to
-	simply increment the system tick. */
-	static __arm __irq void vPortNonPreemptiveTick( void );
-	static __arm __irq void vPortNonPreemptiveTick( void )
-	{
-		/* Increment the tick count - which may wake some tasks but as the
-		preemptive scheduler is not being used any woken task is not given
-		processor time no matter what its priority. */
-		xTaskIncrementTick();
-		
-		/* Ready for the next interrupt. */
-		T0IR = portTIMER_MATCH_ISR_BIT;
-		VICVectAddr = portCLEAR_VIC_INTERRUPT;
-	}
-
-#else
-
-	/* This function is called from an asm wrapper, so does not require the __irq
-	keyword. */
-	void vPortPreemptiveTick( void );
-	void vPortPreemptiveTick( void )
-	{
-		/* Increment the tick counter. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{	
-			/* The new tick value might unblock a task.  Ensure the highest task that
-			is ready to execute is the task that will execute when the tick ISR
-			exits. */
-			vTaskSwitchContext();
-		}
-	
-		/* Ready for the next interrupt. */
-		T0IR = portTIMER_MATCH_ISR_BIT;
-		VICVectAddr = portCLEAR_VIC_INTERRUPT;
-	}
-
-#endif
-
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-uint32_t ulCompareMatch;
-
-	/* A 1ms tick does not require the use of the timer prescale.  This is
-	defaulted to zero but can be used if necessary. */
-	T0PR = portPRESCALE_VALUE;
-
-	/* Calculate the match value required for our wanted tick rate. */
-	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-
-	/* Protect against divide by zero.  Using an if() statement still results
-	in a warning - hence the #if. */
-	#if portPRESCALE_VALUE != 0
-	{
-		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
-	}
-	#endif
-
-	T0MR0 = ulCompareMatch;
-
-	/* Generate tick with timer 0 compare match. */
-	T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
-
-	/* Setup the VIC for the timer. */
-	VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
-	VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
-	
-	/* The ISR installed depends on whether the preemptive or cooperative
-	scheduler is being used. */
-	#if configUSE_PREEMPTION == 1
-	{	
-		extern void ( vPortPreemptiveTickEntry )( void );
-
-		VICVectAddr0 = ( uint32_t ) vPortPreemptiveTickEntry;
-	}
-	#else
-	{
-		extern void ( vNonPreemptiveTick )( void );
-
-		VICVectAddr0 = ( int32_t ) vPortNonPreemptiveTick;
-	}
-	#endif
-
-	VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
-
-	/* Start the timer - interrupts are disabled when this function is called
-	so it is okay to do this here. */
-	T0TCR = portENABLE_TIMER;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	/* Disable interrupts first! */
-	__disable_interrupt();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as we are leaving a critical section. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then interrupts should be
-		re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			__enable_interrupt();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/LPC2000/portasm.s79 b/FreeRTOS/Source/portable/IAR/LPC2000/portasm.s79
deleted file mode 100755
index ff8efb6..0000000
--- a/FreeRTOS/Source/portable/IAR/LPC2000/portasm.s79
+++ /dev/null
@@ -1,76 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-		RSEG ICODE:CODE
-		CODE32
-
-	EXTERN vTaskSwitchContext
-	EXTERN vPortPreemptiveTick
-
-	PUBLIC vPortPreemptiveTickEntry
-	PUBLIC vPortYieldProcessor
-	PUBLIC vPortStartFirstTask
-
-#include "FreeRTOSConfig.h"
-#include "ISR_Support.h"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Starting the first task is just a matter of restoring the context that
-; was created by pxPortInitialiseStack().
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortStartFirstTask:
-	portRESTORE_CONTEXT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Manual context switch function.  This is the SWI hander.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortYieldProcessor:
-	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
-								; as if the context was saved during and IRQ
-								; handler.
-
-	portSAVE_CONTEXT			; Save the context of the current task...
-	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
-	mov     lr, pc
-	BX R0
-	portRESTORE_CONTEXT			; Restore the context of the selected task.
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Preemptive context switch function.  This will only ever get installed if
-; portUSE_PREEMPTION is set to 1 in portmacro.h.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortPreemptiveTickEntry:
-#if configUSE_PREEMPTION == 1
-	portSAVE_CONTEXT			; Save the context of the current task...
-	LDR R0, =vPortPreemptiveTick; before selecting the next task to execute.
-	mov     lr, pc
-	BX R0
-	portRESTORE_CONTEXT			; Restore the context of the selected task.
-#endif
-
-	END
-
diff --git a/FreeRTOS/Source/portable/IAR/LPC2000/portmacro.h b/FreeRTOS/Source/portable/IAR/LPC2000/portmacro.h
deleted file mode 100755
index 4ef35a2..0000000
--- a/FreeRTOS/Source/portable/IAR/LPC2000/portmacro.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-#define portYIELD()					asm ( "SWI 0" )
-#define portNOP()					asm ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-__arm __interwork void vPortDisableInterruptsFromThumb( void );
-__arm __interwork void vPortEnableInterruptsFromThumb( void );
-__arm __interwork void vPortEnterCritical( void );
-__arm __interwork void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()	__disable_interrupt()
-#define portENABLE_INTERRUPTS()		__enable_interrupt()
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
-{													\
-extern void vTaskSwitchContext( void );				\
-													\
-	if( xSwitchRequired ) 							\
-	{												\
-		vTaskSwitchContext();						\
-	}												\
-}
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
-
diff --git a/FreeRTOS/Source/portable/IAR/MSP430/port.c b/FreeRTOS/Source/portable/IAR/MSP430/port.c
deleted file mode 100755
index 6322ba3..0000000
--- a/FreeRTOS/Source/portable/IAR/MSP430/port.c
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MSP430 port.
- *----------------------------------------------------------*/
-
-/* Constants required for hardware setup.  The tick ISR runs off the ACLK,
-not the MCLK. */
-#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
-#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
-#define portFLAGS_INT_ENABLED			( ( StackType_t ) 0x08 )
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/* Each task maintains a count of the critical section nesting depth.  Each
-time a critical section is entered the count is incremented.  Each time a
-critical section is exited the count is decremented - with interrupts only
-being re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as this will cause problems during the startup
-sequence. */
-volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
-/*-----------------------------------------------------------*/
-
-
-/*
- * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
- * could have alternatively used the watchdog timer or timer 1.
- */
-void vPortSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/*
-		Place a few bytes of known values on the bottom of the stack.
-		This is just useful for debugging and can be included if required.
-
-		*pxTopOfStack = ( StackType_t ) 0x1111;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x2222;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x3333;
-		pxTopOfStack--;
-	*/
-
-	/* The msp430 automatically pushes the PC then SR onto the stack before
-	executing an ISR.  We want the stack to look just as if this has happened
-	so place a pointer to the start of the task on the stack first - followed
-	by the flags we want the task to use when it starts up. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-	*pxTopOfStack = portFLAGS_INT_ENABLED;
-	pxTopOfStack--;
-
-	/* Next the general purpose registers. */
-	*pxTopOfStack = ( StackType_t ) 0x4444;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x5555;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x6666;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x7777;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x8888;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x9999;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xaaaa;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xbbbb;
-	pxTopOfStack--;	
-	
-	/* When the task starts is will expect to find the function parameter in
-	R15. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;
-	pxTopOfStack--;
-	
-	*pxTopOfStack = ( StackType_t ) 0xdddd;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xeeee;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xffff;
-	pxTopOfStack--;
-
-	/* A variable is used to keep track of the critical section nesting.
-	This variable has to be stored as part of the task context and is
-	initially set to zero. */
-	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
-
-	/* Return a pointer to the top of the stack we have generated so this can
-	be stored in the task control block for the task. */
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the MSP430 port will get stopped.  If required simply
-	disable the tick interrupt here. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Hardware initialisation to generate the RTOS tick.  This uses timer 0
- * but could alternatively use the watchdog timer or timer 1.
- */
-void vPortSetupTimerInterrupt( void )
-{
-	/* Ensure the timer is stopped. */
-	TACTL = 0;
-
-	/* Run the timer of the ACLK. */
-	TACTL = TASSEL_1;
-
-	/* Clear everything to start with. */
-	TACTL |= TACLR;
-
-	/* Set the compare match value according to the tick rate we want. */
-	TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
-
-	/* Enable the interrupts. */
-	TACCTL0 = CCIE;
-
-	/* Start up clean. */
-	TACTL |= TACLR;
-
-	/* Up mode. */
-	TACTL |= MC_1;
-}
-/*-----------------------------------------------------------*/
-
-
-	
diff --git a/FreeRTOS/Source/portable/IAR/MSP430/portasm.h b/FreeRTOS/Source/portable/IAR/MSP430/portasm.h
deleted file mode 100755
index 0248dd5..0000000
--- a/FreeRTOS/Source/portable/IAR/MSP430/portasm.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTASM_H
-#define PORTASM_H
-
-portSAVE_CONTEXT macro
-
-		IMPORT pxCurrentTCB
-		IMPORT usCriticalNesting
-
-		/* Save the remaining registers. */
-		push	r4
-		push	r5
-		push	r6
-		push	r7
-		push	r8
-		push	r9
-		push	r10
-		push	r11
-		push	r12
-		push	r13
-		push	r14
-		push	r15
-		mov.w	&usCriticalNesting, r14
-		push	r14
-		mov.w	&pxCurrentTCB, r12
-		mov.w	r1, 0(r12)
-		endm
-/*-----------------------------------------------------------*/
-		
-portRESTORE_CONTEXT macro
-		mov.w	&pxCurrentTCB, r12
-		mov.w	@r12, r1
-		pop		r15
-		mov.w	r15, &usCriticalNesting
-		pop		r15
-		pop		r14
-		pop		r13
-		pop		r12
-		pop		r11
-		pop		r10
-		pop		r9
-		pop		r8
-		pop		r7
-		pop		r6
-		pop		r5
-		pop		r4
-
-		/* The last thing on the stack will be the status register.
-        Ensure the power down bits are clear ready for the next
-        time this power down register is popped from the stack. */
-		bic.w   #0xf0,0(SP)
-
-		reti
-		endm
-/*-----------------------------------------------------------*/
-
-#endif
-
diff --git a/FreeRTOS/Source/portable/IAR/MSP430/portext.s43 b/FreeRTOS/Source/portable/IAR/MSP430/portext.s43
deleted file mode 100755
index 6dea51d..0000000
--- a/FreeRTOS/Source/portable/IAR/MSP430/portext.s43
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-#include "FreeRTOSConfig.h"
-#include "portasm.h"
-
-	IMPORT xTaskIncrementTick
-	IMPORT vTaskSwitchContext
-	IMPORT vPortSetupTimerInterrupt
-
-	EXPORT vTickISR
-	EXPORT vPortYield
-	EXPORT xPortStartScheduler
-
-	RSEG CODE
-
-/*
- * The RTOS tick ISR.
- *
- * If the cooperative scheduler is in use this simply increments the tick
- * count.
- *
- * If the preemptive scheduler is in use a context switch can also occur.
- */
-vTickISR:
-	portSAVE_CONTEXT
-
-	call	#xTaskIncrementTick
-	cmp.w	#0x0, R12
-    jeq		SkipContextSwitch
-	call	#vTaskSwitchContext
-SkipContextSwitch:
-
-	portRESTORE_CONTEXT
-/*-----------------------------------------------------------*/
-
-
-/*
- * Manual context switch called by the portYIELD() macro.
- */
-vPortYield:
-
-	/* Mimic an interrupt by pushing the SR. */
-	push	SR
-
-	/* Now the SR is stacked we can disable interrupts. */
-	dint
-
-	/* Save the context of the current task. */
-	portSAVE_CONTEXT
-
-	/* Switch to the highest priority task that is ready to run. */
-	call	#vTaskSwitchContext
-
-	/* Restore the context of the new task. */
-	portRESTORE_CONTEXT
-/*-----------------------------------------------------------*/
-
-
-/*
- * Start off the scheduler by initialising the RTOS tick timer, then restoring
- * the context of the first task.
- */
-xPortStartScheduler:
-
-	/* Setup the hardware to generate the tick.  Interrupts are disabled
-	when this function is called. */
-	call	#vPortSetupTimerInterrupt
-
-	/* Restore the context of the first task that is going to run. */
-	portRESTORE_CONTEXT
-/*-----------------------------------------------------------*/
-
-
-	/* Install vTickISR as the timer A0 interrupt. */
-	ASEG
-	ORG 0xFFE0 + TIMERA0_VECTOR
-
-	_vTickISR_: DC16 vTickISR
-
-
-	END
-
diff --git a/FreeRTOS/Source/portable/IAR/MSP430/portmacro.h b/FreeRTOS/Source/portable/IAR/MSP430/portmacro.h
deleted file mode 100755
index bb39abb..0000000
--- a/FreeRTOS/Source/portable/IAR/MSP430/portmacro.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		int
-#define portSTACK_TYPE	uint16_t
-#define portBASE_TYPE	short
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS()	_DINT(); _NOP()
-#define portENABLE_INTERRUPTS()		_EINT(); _NOP()
-/*-----------------------------------------------------------*/
-
-/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
-
-#define portENTER_CRITICAL()													\
-{																				\
-extern volatile uint16_t usCriticalNesting;							\
-																				\
-	portDISABLE_INTERRUPTS();													\
-																				\
-	/* Now interrupts are disabled usCriticalNesting can be accessed */			\
-	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
-	/* times portENTER_CRITICAL() has been called. */							\
-	usCriticalNesting++;														\
-}
-
-#define portEXIT_CRITICAL()														\
-{																				\
-extern volatile uint16_t usCriticalNesting;							\
-																				\
-	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
-	{																			\
-		/* Decrement the nesting count as we are leaving a critical section. */	\
-		usCriticalNesting--;													\
-																				\
-		/* If the nesting level has reached zero then interrupts should be */	\
-		/* re-enabled. */														\
-		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
-		{																		\
-			portENABLE_INTERRUPTS();											\
-		}																		\
-	}																			\
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/*
- * Manual context switch called by portYIELD or taskYIELD.
- */
-extern void vPortYield( void );
-#define portYIELD() vPortYield()
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			2
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()
-#define portPOINTER_SIZE_TYPE		uint16_t
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#if configINTERRUPT_EXAMPLE_METHOD == 2
-
-extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR( x ) if( x ) vTaskSwitchContext()
-
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/MSP430X/data_model.h b/FreeRTOS/Source/portable/IAR/MSP430X/data_model.h
deleted file mode 100755
index bd4cb6f..0000000
--- a/FreeRTOS/Source/portable/IAR/MSP430X/data_model.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef DATA_MODEL_H
-#define DATA_MODEL_H
-
-#if __DATA_MODEL__ == __DATA_MODEL_SMALL__
-	#define pushm_x pushm.w
-	#define popm_x popm.w
-	#define push_x push.w
-	#define pop_x pop.w
-	#define mov_x mov.w
-	#define cmp_x cmp.w
-#endif
-
-#if __DATA_MODEL__ == __DATA_MODEL_MEDIUM__
-	#define pushm_x pushm.a
-	#define popm_x popm.a
-	#define push_x pushx.a
-	#define pop_x popx.a
-	#define mov_x mov.w
-	#define cmp_x cmp.w
-#endif
-
-#if __DATA_MODEL__ == __DATA_MODEL_LARGE__
-	#define pushm_x pushm.a
-	#define popm_x popm.a
-	#define push_x pushx.a
-	#define pop_x popx.a
-	#define mov_x movx.a
-	#define cmp_x cmpx.a
-#endif
-
-#ifndef pushm_x
-	#error The assembler options must define one of the following symbols: __DATA_MODEL_SMALL__, __DATA_MODEL_MEDIUM__, or __DATA_MODEL_LARGE__
-#endif
-
-#endif /* DATA_MODEL_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/MSP430X/port.c b/FreeRTOS/Source/portable/IAR/MSP430X/port.c
deleted file mode 100755
index 71988bd..0000000
--- a/FreeRTOS/Source/portable/IAR/MSP430X/port.c
+++ /dev/null
@@ -1,182 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MSP430X port.
- *----------------------------------------------------------*/
-
-/* Constants required for hardware setup.  The tick ISR runs off the ACLK,
-not the MCLK. */
-#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
-#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
-#define portFLAGS_INT_ENABLED			( ( StackType_t ) 0x08 )
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/* Each task maintains a count of the critical section nesting depth.  Each
-time a critical section is entered the count is incremented.  Each time a
-critical section is exited the count is decremented - with interrupts only
-being re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as this will cause problems during the startup
-sequence. */
-volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
-/*-----------------------------------------------------------*/
-
-
-/*
- * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
- * could have alternatively used the watchdog timer or timer 1.
- */
-void vPortSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint16_t *pusTopOfStack;
-uint32_t *pulTopOfStack;
-
-	/*
-		Place a few bytes of known values on the bottom of the stack.
-		This is just useful for debugging and can be included if required.
-	
-		*pxTopOfStack = ( StackType_t ) 0x1111;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x2222;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x3333;
-	*/
-
-	/* StackType_t is either 16 bits or 32 bits depending on the data model.
-	Some stacked items do not change size depending on the data model so have
-	to be explicitly cast to the correct size so this function will work
-	whichever data model is being used. */
-	if( sizeof( StackType_t ) == sizeof( uint16_t ) )
-	{
-		/* Make room for a 20 bit value stored as a 32 bit value. */
-		pusTopOfStack = ( uint16_t * ) pxTopOfStack;
-		pusTopOfStack--;
-		pulTopOfStack = ( uint32_t * ) pusTopOfStack;
-	}
-	else
-	{
-		pulTopOfStack = ( uint32_t * ) pxTopOfStack;
-	}
-	*pulTopOfStack = ( uint32_t ) pxCode;
-	
-	pusTopOfStack = ( uint16_t * ) pulTopOfStack;
-	pusTopOfStack--;
-	*pusTopOfStack = portFLAGS_INT_ENABLED;
-	pusTopOfStack -= ( sizeof( StackType_t ) / 2 );
-	
-	/* From here on the size of stacked items depends on the memory model. */
-	pxTopOfStack = ( StackType_t * ) pusTopOfStack;
-
-	/* Next the general purpose registers. */
-	#ifdef PRELOAD_REGISTER_VALUES
-		*pxTopOfStack = ( StackType_t ) 0xffff;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0xeeee;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0xdddd;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) pvParameters;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0xbbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0xaaaa;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x9999;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x8888;
-		pxTopOfStack--;	
-		*pxTopOfStack = ( StackType_t ) 0x5555;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x6666;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x5555;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x4444;
-		pxTopOfStack--;
-	#else
-		pxTopOfStack -= 3;
-		*pxTopOfStack = ( StackType_t ) pvParameters;
-		pxTopOfStack -= 9;
-	#endif
-
-
-	/* A variable is used to keep track of the critical section nesting.
-	This variable has to be stored as part of the task context and is
-	initially set to zero. */
-	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
-
-	/* Return a pointer to the top of the stack we have generated so this can
-	be stored in the task control block for the task. */
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the MSP430 port will get stopped.  If required simply
-	disable the tick interrupt here. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Hardware initialisation to generate the RTOS tick.
- */
-void vPortSetupTimerInterrupt( void )
-{
-	vApplicationSetupTimerInterrupt();
-}
-/*-----------------------------------------------------------*/
-
-#pragma vector=configTICK_VECTOR
-__interrupt __raw void vTickISREntry( void )
-{
-extern void vPortTickISR( void );
-
-	__bic_SR_register_on_exit( SCG1 + SCG0 + OSCOFF + CPUOFF );
-	vPortTickISR();
-}
-
-	
diff --git a/FreeRTOS/Source/portable/IAR/MSP430X/portext.s43 b/FreeRTOS/Source/portable/IAR/MSP430X/portext.s43
deleted file mode 100755
index e669c45..0000000
--- a/FreeRTOS/Source/portable/IAR/MSP430X/portext.s43
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-#include "msp430.h"
-#include "FreeRTOSConfig.h"
-#include "data_model.h"
-
-	IMPORT xTaskIncrementTick
-	IMPORT vTaskSwitchContext
-	IMPORT vPortSetupTimerInterrupt
-	IMPORT pxCurrentTCB
-	IMPORT usCriticalNesting
-
-	EXPORT vPortTickISR
-	EXPORT vPortYield
-	EXPORT xPortStartScheduler
-
-portSAVE_CONTEXT macro
-
-	/* Save the remaining registers. */
-	pushm_x	#12, r15
-	mov.w	&usCriticalNesting, r14
-	push_x r14
-	mov_x	&pxCurrentTCB, r12
-	mov_x	sp, 0( r12 )
-	endm
-/*-----------------------------------------------------------*/
-
-portRESTORE_CONTEXT macro
-
-	mov_x	&pxCurrentTCB, r12
-	mov_x	@r12, sp
-	pop_x	r15
-	mov.w	r15, &usCriticalNesting
-	popm_x	#12, r15
-	nop
-	pop.w	sr
-	nop
-	reta
-	endm
-/*-----------------------------------------------------------*/
-
-
-/*
- * The RTOS tick ISR.
- *
- * If the cooperative scheduler is in use this simply increments the tick
- * count.
- *
- * If the preemptive scheduler is in use a context switch can also occur.
- */
-
-	RSEG CODE
-	EVEN
-
-vPortTickISR:
-
-	/* The sr is not saved in portSAVE_CONTEXT() because vPortYield() needs
-	to save it manually before it gets modified (interrupts get disabled).
-	Entering through this interrupt means the SR is already on the stack, but
-	this keeps the stack frames identical. */
-	push.w sr
-	portSAVE_CONTEXT
-
-	calla	#xTaskIncrementTick
-	cmp.w   #0x0, R12
-    jeq     SkipContextSwitch
-    calla   #vTaskSwitchContext
-SkipContextSwitch:
-	portRESTORE_CONTEXT
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch called by the portYIELD() macro.
- */
- 	EVEN
-
-vPortYield:
-
-	/* The sr needs saving before it is modified. */
-	push.w	sr
-
-	/* Now the SR is stacked interrupts can be disabled. */
-	dint
-	nop
-
-	/* Save the context of the current task. */
-	portSAVE_CONTEXT
-
-	/* Select the next task to run. */
-	calla	#vTaskSwitchContext
-
-	/* Restore the context of the new task. */
-	portRESTORE_CONTEXT
-/*-----------------------------------------------------------*/
-
-
-/*
- * Start off the scheduler by initialising the RTOS tick timer, then restoring
- * the context of the first task.
- */
- 	EVEN
-
-xPortStartScheduler:
-
-	/* Setup the hardware to generate the tick.  Interrupts are disabled
-	when this function is called. */
-	calla	#vPortSetupTimerInterrupt
-
-	/* Restore the context of the first task that is going to run. */
-	portRESTORE_CONTEXT
-/*-----------------------------------------------------------*/
-
-	END
-
diff --git a/FreeRTOS/Source/portable/IAR/MSP430X/portmacro.h b/FreeRTOS/Source/portable/IAR/MSP430X/portmacro.h
deleted file mode 100755
index feb8a14..0000000
--- a/FreeRTOS/Source/portable/IAR/MSP430X/portmacro.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Hardware includes. */
-#include "msp430.h"
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		int
-#define portBASE_TYPE	short
-
-/* The stack type changes depending on the data model. */
-#if( __DATA_MODEL__ == __DATA_MODEL_SMALL__ )
-	#define portSTACK_TYPE uint16_t
-	#define portPOINTER_SIZE_TYPE uint16_t
-#else
-	#define portSTACK_TYPE uint32_t
-#endif
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS()	_DINT(); _NOP()
-#define portENABLE_INTERRUPTS()		_EINT(); _NOP()
-/*-----------------------------------------------------------*/
-
-/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
-
-#define portENTER_CRITICAL()													\
-{																				\
-extern volatile uint16_t usCriticalNesting;										\
-																				\
-	portDISABLE_INTERRUPTS();													\
-																				\
-	/* Now interrupts are disabled usCriticalNesting can be accessed */			\
-	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
-	/* times portENTER_CRITICAL() has been called. */							\
-	usCriticalNesting++;														\
-}
-
-#define portEXIT_CRITICAL()														\
-{																				\
-extern volatile uint16_t usCriticalNesting;										\
-																				\
-	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
-	{																			\
-		/* Decrement the nesting count as we are leaving a critical section. */	\
-		usCriticalNesting--;													\
-																				\
-		/* If the nesting level has reached zero then interrupts should be */	\
-		/* re-enabled. */														\
-		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
-		{																		\
-			portENABLE_INTERRUPTS();											\
-		}																		\
-	}																			\
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/*
- * Manual context switch called by portYIELD or taskYIELD.
- */
-extern void vPortYield( void );
-#define portYIELD() vPortYield()
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			2
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()					__no_operation()
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#define portYIELD_FROM_ISR( x ) if( x ) vPortYield()
-
-void vApplicationSetupTimerInterrupt( void );
-
-/* sizeof( int ) != sizeof( long ) so a full printf() library is required if
-run time stats information is to be displayed. */
-#define portLU_PRINTF_SPECIFIER_REQUIRED
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/RL78/ISR_Support.h b/FreeRTOS/Source/portable/IAR/RL78/ISR_Support.h
deleted file mode 100755
index 143c9c0..0000000
--- a/FreeRTOS/Source/portable/IAR/RL78/ISR_Support.h
+++ /dev/null
@@ -1,83 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-
-#include "FreeRTOSConfig.h"
-
-; Variables used by scheduler
-;------------------------------------------------------------------------------
-	EXTERN    pxCurrentTCB
-	EXTERN    usCriticalNesting
-
-;------------------------------------------------------------------------------
-;   portSAVE_CONTEXT MACRO
-;   Saves the context of the general purpose registers, CS and ES (only in far
-;	memory mode) registers the usCriticalNesting Value and the Stack Pointer
-;   of the active Task onto the task stack
-;------------------------------------------------------------------------------
-portSAVE_CONTEXT MACRO
-
-	PUSH      AX                    ; Save AX Register to stack.
-	PUSH      HL
-	MOV       A, CS                 ; Save CS register.
-	XCH       A, X
-	MOV       A, ES                 ; Save ES register.
-	PUSH      AX
-	PUSH      DE                    ; Save the remaining general purpose registers.
-	PUSH      BC
-	MOVW      AX, usCriticalNesting ; Save the usCriticalNesting value.
-	PUSH      AX
-	MOVW      AX, pxCurrentTCB 	    ; Save the Stack pointer.
-	MOVW      HL, AX
-	MOVW      AX, SP
-	MOVW      [HL], AX
-	ENDM
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   portRESTORE_CONTEXT MACRO
-;   Restores the task Stack Pointer then use this to restore usCriticalNesting,
-;   general purpose registers and the CS and ES (only in far memory mode)
-;   of the selected task from the task stack
-;------------------------------------------------------------------------------
-portRESTORE_CONTEXT MACRO
-	MOVW      AX, pxCurrentTCB	    ; Restore the Stack pointer.
-	MOVW      HL, AX
-	MOVW      AX, [HL]
-	MOVW      SP, AX
-	POP	      AX	                ; Restore usCriticalNesting value.
-	MOVW      usCriticalNesting, AX
-	POP	      BC                    ; Restore the necessary general purpose registers.
-	POP	      DE
-	POP       AX                    ; Restore the ES register.
-	MOV       ES, A
-	XCH       A, X                  ; Restore the CS register.
-	MOV       CS, A
-	POP       HL                    ; Restore general purpose register HL.
-	POP       AX                    ; Restore AX.
-	ENDM
-;------------------------------------------------------------------------------
diff --git a/FreeRTOS/Source/portable/IAR/RL78/port.c b/FreeRTOS/Source/portable/IAR/RL78/port.c
deleted file mode 100755
index 0788d1c..0000000
--- a/FreeRTOS/Source/portable/IAR/RL78/port.c
+++ /dev/null
@@ -1,280 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* The critical nesting value is initialised to a non zero value to ensure
-interrupts don't accidentally become enabled before the scheduler is started. */
-#define portINITIAL_CRITICAL_NESTING  ( ( uint16_t ) 10 )
-
-/* Initial PSW value allocated to a newly created task.
- *   1100011000000000
- *   ||||||||-------------- Fill byte
- *   |||||||--------------- Carry Flag cleared
- *   |||||----------------- In-service priority Flags set to low level
- *   ||||------------------ Register bank Select 0 Flag cleared
- *   |||------------------- Auxiliary Carry Flag cleared
- *   ||-------------------- Register bank Select 1 Flag cleared
- *   |--------------------- Zero Flag set
- *   ---------------------- Global Interrupt Flag set (enabled)
- */
-#define portPSW		  ( 0xc6UL )
-
-/* The address of the pxCurrentTCB variable, but don't know or need to know its
-type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/* Each task maintains a count of the critical section nesting depth.  Each time
-a critical section is entered the count is incremented.  Each time a critical
-section is exited the count is decremented - with interrupts only being
-re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as that could cause problems during the startup
-sequence. */
-volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Sets up the periodic ISR used for the RTOS tick using the interval timer.
- * The application writer can define configSETUP_TICK_INTERRUPT() (in
- * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
- * in place of prvSetupTimerInterrupt().
- */
-static void prvSetupTimerInterrupt( void );
-#ifndef configSETUP_TICK_INTERRUPT
-	/* The user has not provided their own tick interrupt configuration so use
-    the definition in this file (which uses the interval timer). */
-	#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
-#endif /* configSETUP_TICK_INTERRUPT */
-
-/*
- * Defined in portasm.s87, this function starts the scheduler by loading the
- * context of the first task to run.
- */
-extern void vPortStartFirstTask( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint32_t *pulLocal;
-
-	/* With large code and large data sizeof( StackType_t ) == 2, and
-	sizeof( StackType_t * ) == 4.  With small code and small data
-	sizeof( StackType_t ) == 2 and sizeof( StackType_t * ) == 2. */
-
-	#if __DATA_MODEL__ == __DATA_MODEL_FAR__
-	{
-		/* Parameters are passed in on the stack, and written using a 32-bit value
-		hence a space is left for the second two bytes. */
-		pxTopOfStack--;
-
-		/* Write in the parameter value. */
-		pulLocal =  ( uint32_t * ) pxTopOfStack;
-		*pulLocal = ( uint32_t ) pvParameters;
-		pxTopOfStack--;
-
-		/* The return address, leaving space for the first two bytes of	the
-		32-bit value.  See the comments above the prvTaskExitError() prototype
-		at the top of this file. */
-		pxTopOfStack--;
-		pulLocal = ( uint32_t * ) pxTopOfStack;
-		*pulLocal = ( uint32_t ) prvTaskExitError;
-		pxTopOfStack--;
-
-		/* The start address / PSW value is also written in as a 32-bit value,
-		so leave a space for the second two bytes. */
-		pxTopOfStack--;
-
-		/* Task function start address combined with the PSW. */
-		pulLocal = ( uint32_t * ) pxTopOfStack;
-		*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
-		pxTopOfStack--;
-
-		/* An initial value for the AX register. */
-		*pxTopOfStack = ( StackType_t ) 0x1111;
-		pxTopOfStack--;
-	}
-	#else
-	{
-		/* The return address, leaving space for the first two bytes of	the
-		32-bit value.  See the comments above the prvTaskExitError() prototype
-		at the top of this file. */
-		pxTopOfStack--;
-		pulLocal = ( uint32_t * ) pxTopOfStack;
-		*pulLocal = ( uint32_t ) prvTaskExitError;
-		pxTopOfStack--;
-
-		/* Task function.  Again as it is written as a 32-bit value a space is
-		left on the stack for the second two bytes. */
-		pxTopOfStack--;
-
-		/* Task function start address combined with the PSW. */
-		pulLocal = ( uint32_t * ) pxTopOfStack;
-		*pulLocal = ( ( ( uint32_t ) pxCode ) | ( portPSW << 24UL ) );
-		pxTopOfStack--;
-
-		/* The parameter is passed in AX. */
-		*pxTopOfStack = ( StackType_t ) pvParameters;
-		pxTopOfStack--;
-	}
-	#endif
-
-	/* An initial value for the HL register. */
-	*pxTopOfStack = ( StackType_t ) 0x2222;
-	pxTopOfStack--;
-
-	/* CS and ES registers. */
-	*pxTopOfStack = ( StackType_t ) 0x0F00;
-	pxTopOfStack--;
-
-	/* The remaining general purpose registers DE and BC */
-	*pxTopOfStack = ( StackType_t ) 0xDEDE;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xBCBC;
-	pxTopOfStack--;
-
-	/* Finally the critical section nesting count is set to zero when the task
-	first starts. */
-	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
-
-	/* Return a pointer to the top of the stack that has been generated so it
-	can	be stored in the task control block for the task. */
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( usCriticalNesting == ~0U );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Setup the hardware to generate the tick.  Interrupts are disabled when
-	this function is called. */
-	configSETUP_TICK_INTERRUPT();
-
-	/* Restore the context of the first task that is going to run. */
-	vPortStartFirstTask();
-
-	/* Execution should not reach here as the tasks are now running!
-	prvSetupTimerInterrupt() is called here to prevent the compiler outputting
-	a warning about a statically declared function not being referenced in the
-	case that the application writer has provided their own tick interrupt
-	configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
-	their own routine will be called in place of prvSetupTimerInterrupt()). */
-	prvSetupTimerInterrupt();
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the RL78 port will get stopped. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-const uint16_t usClockHz = 15000UL; /* Internal clock. */
-const uint16_t usCompareMatch = ( usClockHz / configTICK_RATE_HZ ) + 1UL;
-
-	/* Use the internal 15K clock. */
-	OSMC = ( uint8_t ) 0x16;
-
-	#ifdef RTCEN
-	{
-		/* Supply the interval timer clock. */
-		RTCEN = ( uint8_t ) 1U;
-
-		/* Disable INTIT interrupt. */
-		ITMK = ( uint8_t ) 1;
-
-		/* Disable ITMC operation. */
-		ITMC = ( uint8_t ) 0x0000;
-
-		/* Clear INIT interrupt. */
-		ITIF = ( uint8_t ) 0;
-
-		/* Set interval and enable interrupt operation. */
-		ITMC = usCompareMatch | 0x8000U;
-
-		/* Enable INTIT interrupt. */
-		ITMK = ( uint8_t ) 0;
-	}
-	#endif
-
-	#ifdef TMKAEN
-	{
-		/* Supply the interval timer clock. */
-		TMKAEN = ( uint8_t ) 1U;
-
-		/* Disable INTIT interrupt. */
-		TMKAMK = ( uint8_t ) 1;
-
-		/* Disable ITMC operation. */
-		ITMC = ( uint8_t ) 0x0000;
-
-		/* Clear INIT interrupt. */
-		TMKAIF = ( uint8_t ) 0;
-
-		/* Set interval and enable interrupt operation. */
-		ITMC = usCompareMatch | 0x8000U;
-
-		/* Enable INTIT interrupt. */
-		TMKAMK = ( uint8_t ) 0;
-	}
-	#endif
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/IAR/RL78/portasm.s87 b/FreeRTOS/Source/portable/IAR/RL78/portasm.s87
deleted file mode 100755
index ee6e7f2..0000000
--- a/FreeRTOS/Source/portable/IAR/RL78/portasm.s87
+++ /dev/null
@@ -1,83 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-#include "ISR_Support.h"
-
-#define CS                    0xFFFFC
-#define ES                    0xFFFFD
-
-	PUBLIC    vPortYield
-	PUBLIC    vPortStartFirstTask
-	PUBLIC    vPortTickISR
-
-	EXTERN    vTaskSwitchContext
-	EXTERN    xTaskIncrementTick
-
-; FreeRTOS yield handler.  This is installed as the BRK software interrupt
-; handler.
-    RSEG CODE:CODE
-vPortYield:
-	portSAVE_CONTEXT		        ; Save the context of the current task.
-	call      vTaskSwitchContext    ; Call the scheduler to select the next task.
-	portRESTORE_CONTEXT		        ; Restore the context of the next task to run.
-	retb
-
-
-; Starts the scheduler by restoring the context of the task that will execute
-; first.
-    RSEG CODE:CODE
-vPortStartFirstTask:
-	portRESTORE_CONTEXT	            ; Restore the context of whichever task the ...
-	reti					        ; An interrupt stack frame is used so the task
-                                    ; is started using a RETI instruction.
-
-; FreeRTOS tick handler.  This is installed as the interval timer interrupt
-; handler.
-	 RSEG CODE:CODE
-vPortTickISR:
-
-	portSAVE_CONTEXT		       ; Save the context of the current task.
-	call	xTaskIncrementTick     ; Call the timer tick function.
-	cmpw	ax, #0x00
-	skz
-	call	vTaskSwitchContext     ; Call the scheduler to select the next task.
-	portRESTORE_CONTEXT		       ; Restore the context of the next task to run.
-	reti
-
-
-; Install the interrupt handlers
-
-	COMMON INTVEC:CODE:ROOT(1)
-	ORG configTICK_VECTOR
-	DW vPortTickISR
-
-	COMMON INTVEC:CODE:ROOT(1)
-	ORG 126
-	DW vPortYield
-
-
-      END
\ No newline at end of file
diff --git a/FreeRTOS/Source/portable/IAR/RL78/portmacro.h b/FreeRTOS/Source/portable/IAR/RL78/portmacro.h
deleted file mode 100755
index 2f66784..0000000
--- a/FreeRTOS/Source/portable/IAR/RL78/portmacro.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-#if __DATA_MODEL__ == __DATA_MODEL_FAR__ && __CODE_MODEL__ == __CODE_MODEL_NEAR__
-	#warning This port has not been tested with your selected memory model combination. If a far data model is required it is recommended to also use a far code model.
-#endif
-
-#if __DATA_MODEL__ == __DATA_MODEL_NEAR__ && __CODE_MODEL__ == __CODE_MODEL_FAR__
-	#warning This port has not been tested with your selected memory model combination. If a far code model is required it is recommended to also use a far data model.
-#endif
-
-/* Type definitions. */
-
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE   short
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-
-#if __DATA_MODEL__ == __DATA_MODEL_FAR__
-	#define portPOINTER_SIZE_TYPE uint32_t
-#else
-	#define portPOINTER_SIZE_TYPE uint16_t
-#endif
-
-
-#if ( configUSE_16_BIT_TICKS == 1 )
-	typedef unsigned int TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() __asm ( "DI" )
-#define portENABLE_INTERRUPTS()	 __asm ( "EI" )
-/*-----------------------------------------------------------*/
-
-/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
-
-#define portENTER_CRITICAL()													\
-{																				\
-extern volatile uint16_t usCriticalNesting;										\
-																				\
-	portDISABLE_INTERRUPTS();													\
-																				\
-	/* Now interrupts are disabled ulCriticalNesting can be accessed */			\
-	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
-	/* times portENTER_CRITICAL() has been called. */							\
-	usCriticalNesting++;														\
-}
-
-#define portEXIT_CRITICAL()														\
-{																				\
-extern volatile uint16_t usCriticalNesting;										\
-																				\
-	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
-	{																			\
-		/* Decrement the nesting count as we are leaving a critical section. */	\
-		usCriticalNesting--;													\
-																				\
-		/* If the nesting level has reached zero then interrupts should be */	\
-		/* re-enabled. */														\
-		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
-		{																		\
-			portENABLE_INTERRUPTS();											\
-		}																		\
-	}																			\
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-#define portYIELD()	__asm( "BRK" )
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
-#define portNOP()	__asm( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Hardwware specifics. */
-#define portBYTE_ALIGNMENT	2
-#define portSTACK_GROWTH	( -1 )
-#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/RX100/port.c b/FreeRTOS/Source/portable/IAR/RX100/port.c
deleted file mode 100755
index df36270..0000000
--- a/FreeRTOS/Source/portable/IAR/RX100/port.c
+++ /dev/null
@@ -1,516 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
-
-/* Standard C includes. */
-#include "limits.h"
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#include "machine.h"
-
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
-
-/* The peripheral clock is divided by this value before being supplying the
-CMT. */
-#if ( configUSE_TICKLESS_IDLE == 0 )
-	/* If tickless idle is not used then the divisor can be fixed. */
-	#define portCLOCK_DIVISOR	8UL
-#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
-	#define portCLOCK_DIVISOR	512UL
-#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
-	#define portCLOCK_DIVISOR	128UL
-#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
-	#define portCLOCK_DIVISOR	32UL
-#else
-	#define portCLOCK_DIVISOR	8UL
-#endif
-
-
-/* Keys required to lock and unlock access to certain system registers
-respectively. */
-#define portUNLOCK_KEY		0xA50B
-#define portLOCK_KEY		0xA500
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-extern void prvStartFirstTask( void );
-
-/*
- * The tick ISR handler.  The peripheral used is configured by the application
- * via a hook/callback function.
- */
-__interrupt static void prvTickISR( void );
-
-/*
- * Sets up the periodic ISR used for the RTOS tick using the CMT.
- * The application writer can define configSETUP_TICK_INTERRUPT() (in
- * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
- * in place of prvSetupTimerInterrupt().
- */
-static void prvSetupTimerInterrupt( void );
-#ifndef configSETUP_TICK_INTERRUPT
-	/* The user has not provided their own tick interrupt configuration so use
-    the definition in this file (which uses the interval timer). */
-	#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
-#endif /* configSETUP_TICK_INTERRUPT */
-
-/*
- * Called after the sleep mode registers have been configured, prvSleep()
- * executes the pre and post sleep macros, and actually calls the wait
- * instruction.
- */
-#if configUSE_TICKLESS_IDLE == 1
-	static void prvSleep( TickType_t xExpectedIdleTime );
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*-----------------------------------------------------------*/
-
-extern void *pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
-
-/* Calculate how many clock increments make up a single tick period. */
-static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
-
-#if configUSE_TICKLESS_IDLE == 1
-
-	/* Holds the maximum number of ticks that can be suppressed - which is
-	basically how far into the future an interrupt can be generated. Set
-	during initialisation.  This is the maximum possible value that the
-	compare match register can hold divided by ulMatchValueForOneTick. */
-	static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
-
-	/* Flag set from the tick interrupt to allow the sleep processing to know if
-	sleep mode was exited because of a tick interrupt, or an interrupt
-	generated by something else. */
-	static volatile uint32_t ulTickFlag = pdFALSE;
-
-	/* The CMT counter is stopped temporarily each time it is re-programmed.
-	The following constant offsets the CMT counter match value by the number of
-	CMT	counts that would typically be missed while the counter was stopped to
-	compensate for the lost time.  The large difference between the divided CMT
-	clock and the CPU clock means it is likely ulStoppedTimerCompensation will
-	equal zero - and be optimised away. */
-	static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
-
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Offset to end up on 8 byte boundary. */
-	pxTopOfStack--;
-
-	/* R0 is not included as it is the stack pointer. */
-	*pxTopOfStack = 0x00;
-	pxTopOfStack--;
-    *pxTopOfStack = 0x00;
-	pxTopOfStack--;
- 	*pxTopOfStack = portINITIAL_PSW;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;
-
-	/* When debugging it can be useful if every register is set to a known
-	value.  Otherwise code space can be saved by just setting the registers
-	that need to be set. */
-	#ifdef USE_FULL_REGISTER_INITIALISATION
-	{
-		pxTopOfStack--;
-		*pxTopOfStack = 0x12345678;	/* r15. */
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaabbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xdddddddd;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xcccccccc;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xbbbbbbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaaaaaa;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x99999999;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x88888888;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x77777777;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x66666666;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x55555555;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x44444444;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x33333333;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x22222222;
-		pxTopOfStack--;
-	}
-	#else
-	{
-		/* Leave space for the registers that will get popped from the stack
-		when the task first starts executing. */
-		pxTopOfStack -= 15;
-	}
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x12345678; /* Accumulator. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x87654321; /* Accumulator. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Use pxCurrentTCB just so it does not get optimised away. */
-	if( pxCurrentTCB != NULL )
-	{
-		/* Call an application function to set up the timer that will generate
-		the tick interrupt.  This way the application can decide which
-		peripheral to use.  If tickless mode is used then the default
-		implementation defined in this file (which uses CMT0) should not be
-		overridden. */
-		configSETUP_TICK_INTERRUPT();
-
-		/* Enable the software interrupt. */
-		_IEN( _ICU_SWINT ) = 1;
-
-		/* Ensure the software interrupt is clear. */
-		_IR( _ICU_SWINT ) = 0;
-
-		/* Ensure the software interrupt is set to the kernel priority. */
-		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
-		/* Start the first task. */
-		prvStartFirstTask();
-	}
-
-	/* Execution should not reach here as the tasks are now running!
-	prvSetupTimerInterrupt() is called here to prevent the compiler outputting
-	a warning about a statically declared function not being referenced in the
-	case that the application writer has provided their own tick interrupt
-	configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
-	their own routine will be called in place of prvSetupTimerInterrupt()). */
-	prvSetupTimerInterrupt();
-
-	/* Should not get here. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-#pragma vector = configTICK_VECTOR
-__interrupt static void prvTickISR( void )
-{
-	/* Re-enable interrupts. */
-	__enable_interrupt();
-
-	/* Increment the tick, and perform any processing the new tick value
-	necessitates. */
-	__set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			taskYIELD();
-		}
-	}
-	__set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
-
-	#if configUSE_TICKLESS_IDLE == 1
-	{
-		/* The CPU woke because of a tick. */
-		ulTickFlag = pdTRUE;
-
-		/* If this is the first tick since exiting tickless mode then the CMT
-		compare match value needs resetting. */
-		CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
-	}
-	#endif
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( pxCurrentTCB == NULL );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-	/* Unlock. */
-	SYSTEM.PRCR.WORD = portUNLOCK_KEY;
-
-	/* Enable CMT0. */
-	MSTP( CMT0 ) = 0;
-
-	/* Lock again. */
-	SYSTEM.PRCR.WORD = portLOCK_KEY;
-
-	/* Interrupt on compare match. */
-	CMT0.CMCR.BIT.CMIE = 1;
-
-	/* Set the compare match value. */
-	CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
-
-	/* Divide the PCLK. */
-	#if portCLOCK_DIVISOR == 512
-	{
-		CMT0.CMCR.BIT.CKS = 3;
-	}
-	#elif portCLOCK_DIVISOR == 128
-	{
-		CMT0.CMCR.BIT.CKS = 2;
-	}
-	#elif portCLOCK_DIVISOR == 32
-	{
-		CMT0.CMCR.BIT.CKS = 1;
-	}
-	#elif portCLOCK_DIVISOR == 8
-	{
-		CMT0.CMCR.BIT.CKS = 0;
-	}
-	#else
-	{
-		#error Invalid portCLOCK_DIVISOR setting
-	}
-	#endif
-
-
-	/* Enable the interrupt... */
-	_IEN( _CMT0_CMI0 ) = 1;
-
-	/* ...and set its priority to the application defined kernel priority. */
-	_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
-
-	/* Start the timer. */
-	CMT.CMSTR0.BIT.STR0 = 1;
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_TICKLESS_IDLE == 1
-
-	static void prvSleep( TickType_t xExpectedIdleTime )
-	{
-		/* Allow the application to define some pre-sleep processing. */
-		configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
-
-		/* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
-		means the application defined code has already executed the WAIT
-		instruction. */
-		if( xExpectedIdleTime > 0 )
-		{
-			__wait_for_interrupt();
-		}
-
-		/* Allow the application to define some post sleep processing. */
-		configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-#if configUSE_TICKLESS_IDLE == 1
-
-	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
-	eSleepModeStatus eSleepAction;
-
-		/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
-
-		/* Make sure the CMT reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Calculate the reload value required to wait xExpectedIdleTime tick
-		periods. */
-		ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
-		if( ulMatchValue > ulStoppedTimerCompensation )
-		{
-			/* Compensate for the fact that the CMT is going to be stopped
-			momentarily. */
-			ulMatchValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Stop the CMT momentarily.  The time the CMT is stopped for is
-		accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		CMT.CMSTR0.BIT.STR0 = 0;
-		while( CMT.CMSTR0.BIT.STR0 == 1 )
-		{
-			/* Nothing to do here. */
-		}
-
-		/* Critical section using the global interrupt bit as the i bit is
-		automatically reset by the WAIT instruction. */
-		__disable_interrupt();
-
-		/* The tick flag is set to false before sleeping.  If it is true when
-		sleep mode is exited then sleep mode was probably exited because the
-		tick was suppressed for the entire xExpectedIdleTime period. */
-		ulTickFlag = pdFALSE;
-
-		/* If a context switch is pending then abandon the low power entry as
-		the context switch might have been pended by an external interrupt that
-		requires processing. */
-		eSleepAction = eTaskConfirmSleepModeStatus();
-		if( eSleepAction == eAbortSleep )
-		{
-			/* Restart tick. */
-			CMT.CMSTR0.BIT.STR0 = 1;
-			__enable_interrupt();
-		}
-		else if( eSleepAction == eNoTasksWaitingTimeout )
-		{
-		    /* Protection off. */
-		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
-
-		    /* Ready for software standby with all clocks stopped. */
-			SYSTEM.SBYCR.BIT.SSBY = 1;
-
-		    /* Protection on. */
-		    SYSTEM.PRCR.WORD = portLOCK_KEY;
-
-			/* Sleep until something happens.  Calling prvSleep() will
-			automatically reset the i bit in the PSW. */
-			prvSleep( xExpectedIdleTime );
-
-			/* Restart the CMT. */
-			CMT.CMSTR0.BIT.STR0 = 1;
-		}
-		else
-		{
-		    /* Protection off. */
-		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
-
-		    /* Ready for deep sleep mode. */
-			SYSTEM.MSTPCRC.BIT.DSLPE = 1;
-			SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
-			SYSTEM.SBYCR.BIT.SSBY = 0;
-
-		    /* Protection on. */
-		    SYSTEM.PRCR.WORD = portLOCK_KEY;
-
-		    /* Adjust the match value to take into account that the current
-			time slice is already partially complete. */
-			ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
-			CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-
-			/* Restart the CMT to count up to the new match value. */
-			CMT0.CMCNT = 0;
-			CMT.CMSTR0.BIT.STR0 = 1;
-
-			/* Sleep until something happens.  Calling prvSleep() will
-			automatically reset the i bit in the PSW. */
-			prvSleep( xExpectedIdleTime );
-
-			/* Stop CMT.  Again, the time the SysTick is stopped for is
-			accounted for as best it can be, but using the tickless mode will
-			inevitably result in some tiny drift of the time maintained by the
-			kernel with	respect to calendar time. */
-			CMT.CMSTR0.BIT.STR0 = 0;
-			while( CMT.CMSTR0.BIT.STR0 == 1 )
-			{
-				/* Nothing to do here. */
-			}
-
-			ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
-
-			if( ulTickFlag != pdFALSE )
-			{
-				/* The tick interrupt has already executed, although because
-				this function is called with the scheduler suspended the actual
-				tick processing will not occur until after this function has
-				exited.  Reset the match value with whatever remains of this
-				tick period. */
-				ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
-				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-
-				/* The tick interrupt handler will already have pended the tick
-				processing in the kernel.  As the pending tick will be
-				processed as soon as this function exits, the tick value
-				maintained by the tick is stepped forward by one less than the
-				time spent sleeping.  The actual stepping of the tick appears
-				later in this function. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				How	many complete tick periods passed while the processor was
-				sleeping? */
-				ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
-
-				/* The match value is set to whatever fraction of a single tick
-				period remains. */
-				ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
-				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-			}
-
-			/* Restart the CMT so it runs up to the match value.  The match value
-			will get set to the value required to generate exactly one tick period
-			the next time the CMT interrupt executes. */
-			CMT0.CMCNT = 0;
-			CMT.CMSTR0.BIT.STR0 = 1;
-
-			/* Wind the tick forward by the number of tick periods that the CPU
-			remained in a low power state. */
-			vTaskStepTick( ulCompleteTickPeriods );
-		}
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-
diff --git a/FreeRTOS/Source/portable/IAR/RX100/port_asm.s b/FreeRTOS/Source/portable/IAR/RX100/port_asm.s
deleted file mode 100755
index ca2e439..0000000
--- a/FreeRTOS/Source/portable/IAR/RX100/port_asm.s
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include "PriorityDefinitions.h"
-
-	PUBLIC _prvStartFirstTask
-	PUBLIC ___interrupt_27
-
-	EXTERN _pxCurrentTCB
-	EXTERN _vTaskSwitchContext
-
-	RSEG CODE:CODE(4)
-
-_prvStartFirstTask:
-
-		/* When starting the scheduler there is nothing that needs moving to the
-		interrupt stack because the function is not called from an interrupt.
-		Just ensure the current stack is the user stack. */
-		SETPSW		U
-
-		/* Obtain the location of the stack associated with which ever task
-		pxCurrentTCB is currently pointing to. */
-		MOV.L		#_pxCurrentTCB, R15
-		MOV.L		[R15], R15
-		MOV.L		[R15], R0
-
-		/* Restore the registers from the stack of the task pointed to by
-		pxCurrentTCB. */
-		POP			R15
-
-		/* Accumulator low 32 bits. */
-		MVTACLO		R15
-		POP			R15
-
-		/* Accumulator high 32 bits. */
-		MVTACHI		R15
-
-		/* R1 to R15 - R0 is not included as it is the SP. */
-		POPM		R1-R15
-
-		/* This pops the remaining registers. */
-		RTE
-		NOP
-		NOP
-
-/*-----------------------------------------------------------*/
-
-/* The software interrupt - overwrite the default 'weak' definition. */
-___interrupt_27:
-
-		/* Re-enable interrupts. */
-		SETPSW		I
-
-		/* Move the data that was automatically pushed onto the interrupt stack when
-		the interrupt occurred from the interrupt stack to the user stack.
-
-		R15 is saved before it is clobbered. */
-		PUSH.L		R15
-
-		/* Read the user stack pointer. */
-		MVFC		USP, R15
-
-		/* Move the address down to the data being moved. */
-		SUB			#12, R15
-		MVTC		R15, USP
-
-		/* Copy the data across, R15, then PC, then PSW. */
-		MOV.L		[ R0 ], [ R15 ]
-		MOV.L 		4[ R0 ], 4[ R15 ]
-		MOV.L		8[ R0 ], 8[ R15 ]
-
-		/* Move the interrupt stack pointer to its new correct position. */
-		ADD		#12, R0
-
-		/* All the rest of the registers are saved directly to the user stack. */
-		SETPSW		U
-
-		/* Save the rest of the general registers (R15 has been saved already). */
-		PUSHM		R1-R14
-
-		/* Save the accumulator. */
-		MVFACHI 	R15
-		PUSH.L		R15
-
-		/* Middle word. */
-		MVFACMI	R15
-
-		/* Shifted left as it is restored to the low order word. */
-		SHLL		#16, R15
-		PUSH.L		R15
-
-		/* Save the stack pointer to the TCB. */
-		MOV.L		#_pxCurrentTCB, R15
-		MOV.L		[ R15 ], R15
-		MOV.L		R0, [ R15 ]
-
-		/* Ensure the interrupt mask is set to the syscall priority while the kernel
-		structures are being accessed. */
-		MVTIPL		#configMAX_SYSCALL_INTERRUPT_PRIORITY
-
-		/* Select the next task to run. */
-		BSR.A		_vTaskSwitchContext
-
-		/* Reset the interrupt mask as no more data structure access is required. */
-		MVTIPL		#configKERNEL_INTERRUPT_PRIORITY
-
-		/* Load the stack pointer of the task that is now selected as the Running
-		state task from its TCB. */
-		MOV.L		#_pxCurrentTCB,R15
-		MOV.L		[ R15 ], R15
-		MOV.L		[ R15 ], R0
-
-		/* Restore the context of the new task.  The PSW (Program Status Word) and
-		PC will be popped by the RTE instruction. */
-		POP			R15
-		MVTACLO 	R15
-		POP			R15
-		MVTACHI 	R15
-		POPM		R1-R15
-		RTE
-		NOP
-		NOP
-
-/*-----------------------------------------------------------*/
-
-		END
-
diff --git a/FreeRTOS/Source/portable/IAR/RX100/portmacro.h b/FreeRTOS/Source/portable/IAR/RX100/portmacro.h
deleted file mode 100755
index 594bc82..0000000
--- a/FreeRTOS/Source/portable/IAR/RX100/portmacro.h
+++ /dev/null
@@ -1,150 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Hardware specifics. */
-#include "machine.h"
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
-#define portSTACK_GROWTH			-1
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()					__no_operation()
-
-#define portYIELD()						\
-	__asm volatile						\
-	(									\
-		"MOV.L #0x872E0, R15		\n"	\
-		"MOV.B #1, [R15]			\n"	\
-		"MOV.L [R15], R15			\n"	\
-		::: "R15"						\
-	)
-
-#define portYIELD_FROM_ISR( x )	if( ( x ) != pdFALSE ) { portYIELD(); }
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) 0 )
-#ifdef configASSERT
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-	#define portDISABLE_INTERRUPTS() 	if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#else
-	#define portDISABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()	vTaskEnterCritical()
-#define portEXIT_CRITICAL()		vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
-
-/* Tickless idle/low power functionality. */
-#if configUSE_TICKLESS_IDLE == 1
-	#ifndef portSUPPRESS_TICKS_AND_SLEEP
-		extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-		#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-	#endif
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-/* Prevent warnings of undefined behaviour: the order of volatile accesses is
-undefined - all warnings have been manually checked and are not an issue, and
-the warnings cannot be prevent by code changes without undesirable effects. */
-#pragma diag_suppress=Pa082
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/RX600/port.c b/FreeRTOS/Source/portable/IAR/RX600/port.c
deleted file mode 100755
index f3922fc..0000000
--- a/FreeRTOS/Source/portable/IAR/RX600/port.c
+++ /dev/null
@@ -1,193 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#include 
-
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW	 ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW	( ( StackType_t ) 0x00000100 )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-extern void prvStartFirstTask( void );
-
-/*
- * The tick ISR handler.  The peripheral used is configured by the application
- * via a hook/callback function.
- */
-__interrupt void vTickISR( void );
-
-/*-----------------------------------------------------------*/
-
-extern void *pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* R0 is not included as it is the stack pointer. */
-
-	*pxTopOfStack = 0x00;
-	pxTopOfStack--;
- 	*pxTopOfStack = portINITIAL_PSW;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;
-
-	/* When debugging it can be useful if every register is set to a known
-	value.  Otherwise code space can be saved by just setting the registers
-	that need to be set. */
-	#ifdef USE_FULL_REGISTER_INITIALISATION
-	{
-		pxTopOfStack--;
-		*pxTopOfStack = 0xffffffff;	/* r15. */
-		pxTopOfStack--;
-		*pxTopOfStack = 0xeeeeeeee;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xdddddddd;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xcccccccc;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xbbbbbbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaaaaaa;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x99999999;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x88888888;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x77777777;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x66666666;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x55555555;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x44444444;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x33333333;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x22222222;
-		pxTopOfStack--;
-	}
-	#else
-	{
-		pxTopOfStack -= 15;
-	}
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_FPSW;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x12345678; /* Accumulator. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x87654321; /* Accumulator. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vApplicationSetupTimerInterrupt( void );
-
-	/* Use pxCurrentTCB just so it does not get optimised away. */
-	if( pxCurrentTCB != NULL )
-	{
-		/* Call an application function to set up the timer that will generate the
-		tick interrupt.  This way the application can decide which peripheral to
-		use.  A demo application is provided to show a suitable example. */
-		vApplicationSetupTimerInterrupt();
-
-		/* Enable the software interrupt. */
-		_IEN( _ICU_SWINT ) = 1;
-
-		/* Ensure the software interrupt is clear. */
-		_IR( _ICU_SWINT ) = 0;
-
-		/* Ensure the software interrupt is set to the kernel priority. */
-		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
-		/* Start the first task. */
-		prvStartFirstTask();
-	}
-
-	/* Should not get here. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-#pragma vector = configTICK_VECTOR
-__interrupt void vTickISR( void )
-{
-	/* Re-enable interrupts. */
-	__enable_interrupt();
-
-	/* Increment the tick, and perform any processing the new tick value
-	necessitates. */
-	__set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			taskYIELD();
-		}
-	}
-	__set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( pxCurrentTCB == NULL );
-}
-/*-----------------------------------------------------------*/
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/RX600/port_asm.s b/FreeRTOS/Source/portable/IAR/RX600/port_asm.s
deleted file mode 100755
index 400e1fd..0000000
--- a/FreeRTOS/Source/portable/IAR/RX600/port_asm.s
+++ /dev/null
@@ -1,159 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include "PriorityDefinitions.h"
-
-	PUBLIC _prvStartFirstTask
-	PUBLIC ___interrupt_27
-
-	EXTERN _pxCurrentTCB
-	EXTERN _vTaskSwitchContext
-
-	RSEG CODE:CODE(4)
-
-_prvStartFirstTask:
-
-		/* When starting the scheduler there is nothing that needs moving to the
-		interrupt stack because the function is not called from an interrupt.
-		Just ensure the current stack is the user stack. */
-		SETPSW		U
-
-		/* Obtain the location of the stack associated with which ever task
-		pxCurrentTCB is currently pointing to. */
-		MOV.L		#_pxCurrentTCB, R15
-		MOV.L		[R15], R15
-		MOV.L		[R15], R0
-
-		/* Restore the registers from the stack of the task pointed to by
-		pxCurrentTCB. */
-		POP			R15
-
-		/* Accumulator low 32 bits. */
-		MVTACLO		R15
-		POP			R15
-
-		/* Accumulator high 32 bits. */
-		MVTACHI		R15
-		POP			R15
-
-		/* Floating point status word. */
-		MVTC		R15, FPSW
-
-		/* R1 to R15 - R0 is not included as it is the SP. */
-		POPM		R1-R15
-
-		/* This pops the remaining registers. */
-		RTE
-		NOP
-		NOP
-
-/*-----------------------------------------------------------*/
-
-/* The software interrupt - overwrite the default 'weak' definition. */
-___interrupt_27:
-
-		/* Re-enable interrupts. */
-		SETPSW		I
-
-		/* Move the data that was automatically pushed onto the interrupt stack when
-		the interrupt occurred from the interrupt stack to the user stack.
-
-		R15 is saved before it is clobbered. */
-		PUSH.L		R15
-
-		/* Read the user stack pointer. */
-		MVFC		USP, R15
-
-		/* Move the address down to the data being moved. */
-		SUB			#12, R15
-		MVTC		R15, USP
-
-		/* Copy the data across, R15, then PC, then PSW. */
-		MOV.L		[ R0 ], [ R15 ]
-		MOV.L 		4[ R0 ], 4[ R15 ]
-		MOV.L		8[ R0 ], 8[ R15 ]
-
-		/* Move the interrupt stack pointer to its new correct position. */
-		ADD		#12, R0
-
-		/* All the rest of the registers are saved directly to the user stack. */
-		SETPSW		U
-
-		/* Save the rest of the general registers (R15 has been saved already). */
-		PUSHM		R1-R14
-
-		/* Save the FPSW and accumulator. */
-		MVFC		FPSW, R15
-		PUSH.L		R15
-		MVFACHI 	R15
-		PUSH.L		R15
-
-		/* Middle word. */
-		MVFACMI	R15
-
-		/* Shifted left as it is restored to the low order word. */
-		SHLL		#16, R15
-		PUSH.L		R15
-
-		/* Save the stack pointer to the TCB. */
-		MOV.L		#_pxCurrentTCB, R15
-		MOV.L		[ R15 ], R15
-		MOV.L		R0, [ R15 ]
-
-		/* Ensure the interrupt mask is set to the syscall priority while the kernel
-		structures are being accessed. */
-		MVTIPL		#configMAX_SYSCALL_INTERRUPT_PRIORITY
-
-		/* Select the next task to run. */
-		BSR.A		_vTaskSwitchContext
-
-		/* Reset the interrupt mask as no more data structure access is required. */
-		MVTIPL		#configKERNEL_INTERRUPT_PRIORITY
-
-		/* Load the stack pointer of the task that is now selected as the Running
-		state task from its TCB. */
-		MOV.L		#_pxCurrentTCB,R15
-		MOV.L		[ R15 ], R15
-		MOV.L		[ R15 ], R0
-
-		/* Restore the context of the new task.  The PSW (Program Status Word) and
-		PC will be popped by the RTE instruction. */
-		POP			R15
-		MVTACLO 	R15
-		POP			R15
-		MVTACHI 	R15
-		POP			R15
-		MVTC		R15, FPSW
-		POPM		R1-R15
-		RTE
-		NOP
-		NOP
-
-/*-----------------------------------------------------------*/
-
-		END
-
diff --git a/FreeRTOS/Source/portable/IAR/RX600/portmacro.h b/FreeRTOS/Source/portable/IAR/RX600/portmacro.h
deleted file mode 100755
index ec974da..0000000
--- a/FreeRTOS/Source/portable/IAR/RX600/portmacro.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
-#define portSTACK_GROWTH			-1
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()					__no_operation()
-
-/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
-where portITU_SWINTR is the location of the software interrupt register
-(0x000872E0).  Don't rely on the assembler to select a register, so instead
-save and restore clobbered registers manually. */
-#define portYIELD()							\
-	__asm volatile 							\
-	(										\
-		"PUSH.L	R10					\n"		\
-		"MOV.L	#0x872E0, R10		\n"		\
-		"MOV.B	#0x1, [R10]			\n"		\
-		"MOV.L	[R10], R10			\n"		\
-		"POP	R10					\n"		\
-	)
-
-#define portYIELD_FROM_ISR( x )	if( ( x ) != pdFALSE ) portYIELD()
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) 0 )
-#ifdef configASSERT
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-	#define portDISABLE_INTERRUPTS() 	if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#else
-	#define portDISABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()	vTaskEnterCritical()
-#define portEXIT_CRITICAL()		vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/RXv2/port.c b/FreeRTOS/Source/portable/IAR/RXv2/port.c
deleted file mode 100755
index 3f4cc78..0000000
--- a/FreeRTOS/Source/portable/IAR/RXv2/port.c
+++ /dev/null
@@ -1,201 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#include 
-
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW	 ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW	( ( StackType_t ) 0x00000100 )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-extern void prvStartFirstTask( void );
-
-/*
- * The tick ISR handler.  The peripheral used is configured by the application
- * via a hook/callback function.
- */
-__interrupt void vTickISR( void );
-
-/*-----------------------------------------------------------*/
-
-extern void *pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* R0 is not included as it is the stack pointer. */
-
-	*pxTopOfStack = 0x00;
-	pxTopOfStack--;
- 	*pxTopOfStack = portINITIAL_PSW;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;
-
-	/* When debugging it can be useful if every register is set to a known
-	value.  Otherwise code space can be saved by just setting the registers
-	that need to be set. */
-	#ifdef USE_FULL_REGISTER_INITIALISATION
-	{
-		pxTopOfStack--;
-		*pxTopOfStack = 0xffffffff;	/* r15. */
-		pxTopOfStack--;
-		*pxTopOfStack = 0xeeeeeeee;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xdddddddd;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xcccccccc;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xbbbbbbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaaaaaa;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x99999999;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x88888888;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x77777777;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x66666666;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x55555555;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x44444444;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x33333333;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x22222222;
-		pxTopOfStack--;
-	}
-	#else
-	{
-		pxTopOfStack -= 15;
-	}
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_FPSW;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x11111111; /* Accumulator 0. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x22222222; /* Accumulator 0. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x33333333; /* Accumulator 0. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x44444444; /* Accumulator 1. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x55555555; /* Accumulator 1. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x66666666; /* Accumulator 1. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vApplicationSetupTimerInterrupt( void );
-
-	/* Use pxCurrentTCB just so it does not get optimised away. */
-	if( pxCurrentTCB != NULL )
-	{
-		/* Call an application function to set up the timer that will generate the
-		tick interrupt.  This way the application can decide which peripheral to
-		use.  A demo application is provided to show a suitable example. */
-		vApplicationSetupTimerInterrupt();
-
-		/* Enable the software interrupt. */
-		_IEN( _ICU_SWINT ) = 1;
-
-		/* Ensure the software interrupt is clear. */
-		_IR( _ICU_SWINT ) = 0;
-
-		/* Ensure the software interrupt is set to the kernel priority. */
-		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
-		/* Start the first task. */
-		prvStartFirstTask();
-	}
-
-	/* Should not get here. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-#pragma vector = configTICK_VECTOR
-__interrupt void vTickISR( void )
-{
-	/* Re-enable interrupts. */
-	__enable_interrupt();
-
-	/* Increment the tick, and perform any processing the new tick value
-	necessitates. */
-	__set_interrupt_level( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			taskYIELD();
-		}
-	}
-	__set_interrupt_level( configKERNEL_INTERRUPT_PRIORITY );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( pxCurrentTCB == NULL );
-}
-/*-----------------------------------------------------------*/
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s b/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s
deleted file mode 100755
index 9e94823..0000000
--- a/FreeRTOS/Source/portable/IAR/RXv2/port_asm.s
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include "PriorityDefinitions.h"
-
-	PUBLIC _prvStartFirstTask
-	PUBLIC ___interrupt_27
-
-	EXTERN _pxCurrentTCB
-	EXTERN _vTaskSwitchContext
-
-	RSEG CODE:CODE(4)
-
-_prvStartFirstTask:
-
-		/* When starting the scheduler there is nothing that needs moving to the
-		interrupt stack because the function is not called from an interrupt.
-		Just ensure the current stack is the user stack. */
-		SETPSW		U
-
-		/* Obtain the location of the stack associated with which ever task
-		pxCurrentTCB is currently pointing to. */
-		MOV.L		#_pxCurrentTCB, R15
-		MOV.L		[R15], R15
-		MOV.L		[R15], R0
-
-		/* Restore the registers from the stack of the task pointed to by
-		pxCurrentTCB. */
-		POP			R15
-
-		/* Accumulator low 32 bits. */
-		MVTACLO		R15, A0
-		POP			R15
-
-		/* Accumulator high 32 bits. */
-		MVTACHI		R15, A0
-		POP			R15
-
-		/* Accumulator guard. */
-		MVTACGU		R15, A0
-		POP			R15
-
-		/* Accumulator low 32 bits. */
-		MVTACLO		R15, A1
-		POP			R15
-
-		/* Accumulator high 32 bits. */
-		MVTACHI		R15, A1
-		POP			R15
-
-		/* Accumulator guard. */
-		MVTACGU		R15, A1
-		POP			R15
-
-		/* Floating point status word. */
-		MVTC		R15, FPSW
-
-		/* R1 to R15 - R0 is not included as it is the SP. */
-		POPM		R1-R15
-
-		/* This pops the remaining registers. */
-		RTE
-		NOP
-		NOP
-
-/*-----------------------------------------------------------*/
-
-/* The software interrupt - overwrite the default 'weak' definition. */
-___interrupt_27:
-
-		/* Re-enable interrupts. */
-		SETPSW		I
-
-		/* Move the data that was automatically pushed onto the interrupt stack when
-		the interrupt occurred from the interrupt stack to the user stack.
-
-		R15 is saved before it is clobbered. */
-		PUSH.L		R15
-
-		/* Read the user stack pointer. */
-		MVFC		USP, R15
-
-		/* Move the address down to the data being moved. */
-		SUB		#12, R15
-		MVTC		R15, USP
-
-		/* Copy the data across, R15, then PC, then PSW. */
-		MOV.L		[ R0 ], [ R15 ]
-		MOV.L 		4[ R0 ], 4[ R15 ]
-		MOV.L		8[ R0 ], 8[ R15 ]
-
-		/* Move the interrupt stack pointer to its new correct position. */
-		ADD		#12, R0
-
-		/* All the rest of the registers are saved directly to the user stack. */
-		SETPSW		U
-
-		/* Save the rest of the general registers (R15 has been saved already). */
-		PUSHM		R1-R14
-
-		/* Save the FPSW and accumulator. */
-		MVFC		FPSW, R15
-		PUSH.L		R15
-		MVFACGU		#0, A1, R15
-		PUSH.L		R15
-		MVFACHI		#0, A1, R15
-		PUSH.L		R15
-		/* Low order word. */
-		MVFACLO		#0, A1, R15
-		PUSH.L		R15
-		MVFACGU		#0, A0, R15
-		PUSH.L		R15
-		MVFACHI		#0, A0, R15
-		PUSH.L		R15
-		/* Low order word. */
-		MVFACLO		#0, A0, R15
-		PUSH.L		R15
-
-		/* Save the stack pointer to the TCB. */
-		MOV.L		#_pxCurrentTCB, R15
-		MOV.L		[ R15 ], R15
-		MOV.L		R0, [ R15 ]
-
-		/* Ensure the interrupt mask is set to the syscall priority while the kernel
-		structures are being accessed. */
-		MVTIPL		#configMAX_SYSCALL_INTERRUPT_PRIORITY
-
-		/* Select the next task to run. */
-		BSR.A		_vTaskSwitchContext
-
-		/* Reset the interrupt mask as no more data structure access is required. */
-		MVTIPL		#configKERNEL_INTERRUPT_PRIORITY
-
-		/* Load the stack pointer of the task that is now selected as the Running
-		state task from its TCB. */
-		MOV.L		#_pxCurrentTCB,R15
-		MOV.L		[ R15 ], R15
-		MOV.L		[ R15 ], R0
-
-		/* Restore the context of the new task.  The PSW (Program Status Word) and
-		PC will be popped by the RTE instruction. */
-		POP		R15
-
-		/* Accumulator low 32 bits. */
-		MVTACLO	R15, A0
-		POP		R15
-
-		/* Accumulator high 32 bits. */
-		MVTACHI	R15, A0
-		POP		R15
-
-		/* Accumulator guard. */
-		MVTACGU	R15, A0
-		POP		R15
-
-		/* Accumulator low 32 bits. */
-		MVTACLO	R15, A1
-		POP		R15
-
-		/* Accumulator high 32 bits. */
-		MVTACHI	R15, A1
-		POP		R15
-
-		/* Accumulator guard. */
-		MVTACGU	R15, A1
-		POP		R15
-		MVTC		R15, FPSW
-		POPM		R1-R15
-		RTE
-		NOP
-		NOP
-
-/*-----------------------------------------------------------*/
-
-		END
-
diff --git a/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h b/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h
deleted file mode 100755
index ee64729..0000000
--- a/FreeRTOS/Source/portable/IAR/RXv2/portmacro.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			8	/* Could make four, according to manual. */
-#define portSTACK_GROWTH			-1
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()					__no_operation()
-
-/* Yield equivalent to "*portITU_SWINTR = 0x01; ( void ) *portITU_SWINTR;"
-where portITU_SWINTR is the location of the software interrupt register
-(0x000872E0).  Don't rely on the assembler to select a register, so instead
-save and restore clobbered registers manually. */
-#define portYIELD()							\
-	__asm volatile 							\
-	(										\
-		"PUSH.L	R10					\n"		\
-		"MOV.L	#0x872E0, R10		\n"		\
-		"MOV.B	#0x1, [R10]			\n"		\
-		"MOV.L	[R10], R10			\n"		\
-		"POP	R10					\n"		\
-	)
-
-#define portYIELD_FROM_ISR( x )	if( ( x ) != pdFALSE ) portYIELD()
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) 0 )
-#ifdef configASSERT
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( __get_interrupt_level() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-	#define portDISABLE_INTERRUPTS() 	if( __get_interrupt_level() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) __set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#else
-	#define portDISABLE_INTERRUPTS() 	__set_interrupt_level( ( uint8_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()	vTaskEnterCritical()
-#define portEXIT_CRITICAL()		vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() __get_interrupt_level(); portDISABLE_INTERRUPTS()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) __set_interrupt_level( ( uint8_t ) ( uxSavedInterruptStatus ) )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-/* Prevent warnings of undefined behaviour: the order of volatile accesses is
-undefined - all warnings have been manually checked and are not an issue, and
-the warnings cannot be prevent by code changes without undesirable effects. */
-#pragma diag_suppress=Pa082
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/IAR/STR71x/ISR_Support.h b/FreeRTOS/Source/portable/IAR/STR71x/ISR_Support.h
deleted file mode 100755
index babc698..0000000
--- a/FreeRTOS/Source/portable/IAR/STR71x/ISR_Support.h
+++ /dev/null
@@ -1,105 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	EXTERN pxCurrentTCB
-	EXTERN ulCriticalNesting
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-portSAVE_CONTEXT MACRO
-
-	; Push R0 as we are going to use the register.
-	STMDB	SP!, {R0}
-
-	; Set R0 to point to the task stack pointer.
-	STMDB	SP, {SP}^
-	NOP
-	SUB		SP, SP, #4
-	LDMIA	SP!, {R0}
-
-	; Push the return address onto the stack.
-	STMDB	R0!, {LR}
-
-	; Now we have saved LR we can use it instead of R0.
-	MOV		LR, R0
-
-	; Pop R0 so we can save it onto the system mode stack.
-	LDMIA	SP!, {R0}
-
-	; Push all the system mode registers onto the task stack.
-	STMDB	LR, {R0-LR}^
-	NOP
-	SUB		LR, LR, #60
-
-	; Push the SPSR onto the task stack.
-	MRS		R0, SPSR
-	STMDB	LR!, {R0}
-
-	LDR		R0, =ulCriticalNesting
-	LDR		R0, [R0]
-	STMDB	LR!, {R0}
-
-	; Store the new top of stack for the task.
-	LDR		R1, =pxCurrentTCB
-	LDR		R0, [R1]
-	STR		LR, [R0]
-
-	ENDM
-
-
-portRESTORE_CONTEXT MACRO
-
-	; Set the LR to the task stack.
-	LDR		R1, =pxCurrentTCB
-	LDR		R0, [R1]
-	LDR		LR, [R0]
-
-	; The critical nesting depth is the first item on the stack.
-	; Load it into the ulCriticalNesting variable.
-	LDR		R0, =ulCriticalNesting
-	LDMFD	LR!, {R1}
-	STR		R1, [R0]
-
-	; Get the SPSR from the stack.
-	LDMFD	LR!, {R0}
-	MSR		SPSR_cxsf, R0
-
-	; Restore all system mode registers for the task.
-	LDMFD	LR, {R0-R14}^
-	NOP
-
-	; Restore the return address.
-	LDR		LR, [LR, #+60]
-
-	; And return - correcting the offset in the LR to obtain the
-	; correct address.
-	SUBS	PC, LR, #4
-
-	ENDM
-
diff --git a/FreeRTOS/Source/portable/IAR/STR71x/port.c b/FreeRTOS/Source/portable/IAR/STR71x/port.c
deleted file mode 100755
index f7b2f9e..0000000
--- a/FreeRTOS/Source/portable/IAR/STR71x/port.c
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ST STR71x ARM7
- * port.
- *----------------------------------------------------------*/
-
-/* Library includes. */
-#include "wdg.h"
-#include "eic.h"
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
-
-#define portMICROS_PER_SECOND 1000000
-
-/*-----------------------------------------------------------*/
-
-/* Setup the watchdog to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/* ulCriticalNesting will get set to zero when the first task starts.  It
-cannot be initialised to 0 as this will cause interrupts to be enabled
-during the kernel initialisation process. */
-uint32_t ulCriticalNesting = ( uint32_t ) 9999;
-
-/* Tick interrupt routines for cooperative and preemptive operation
-respectively.  The preemptive version is not defined as __irq as it is called
-from an asm wrapper function. */
-__arm __irq void vPortNonPreemptiveTick( void );
-void vPortPreemptiveTick( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
-	pxOriginalTOS = pxTopOfStack;
-
-	/* To ensure asserts in tasks.c don't fail, although in this case the assert
-	is not really required. */
-	pxTopOfStack--;
-
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* First on the stack is the return address - which in this case is the
-	start of the task.  The offset is added to make the return address appear
-	as it would within an IRQ ISR. */
-	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;	
-
-	/* When the task starts is will expect to find the function parameter in
-	R0. */
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The status register is set for system mode, with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-	
-	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
-	{
-		/* We want the task to start in thumb mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}		
-	
-	pxTopOfStack--;
-
-	/* Interrupt flags cannot always be stored on the stack and will
-	instead be stored in a variable, which is then saved as part of the
-	tasks context. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-
-	return pxTopOfStack;	
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortStartFirstTask( void );
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task. */
-	vPortStartFirstTask();	
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the ARM port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-/* The cooperative scheduler requires a normal IRQ service routine to
-simply increment the system tick. */
-__arm __irq void vPortNonPreemptiveTick( void )
-{
-	/* Increment the tick count - which may wake some tasks but as the
-	preemptive scheduler is not being used any woken task is not given
-	processor time no matter what its priority. */
-	xTaskIncrementTick();
-
-	/* Clear the interrupt in the watchdog and EIC. */
-	WDG->SR = 0x0000;
-	portCLEAR_EIC();		
-}
-/*-----------------------------------------------------------*/
-
-/* This function is called from an asm wrapper, so does not require the __irq
-keyword. */
-void vPortPreemptiveTick( void )
-{
-	/* Increment the tick counter. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		/* Select a new task to execute. */
-		vTaskSwitchContext();
-	}
-
-	/* Clear the interrupt in the watchdog and EIC. */
-	WDG->SR = 0x0000;
-	portCLEAR_EIC();			
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-	/* Set the watchdog up to generate a periodic tick. */
-	WDG_ECITConfig( DISABLE );
-	WDG_CntOnOffConfig( DISABLE );
-	WDG_PeriodValueConfig( portMICROS_PER_SECOND / configTICK_RATE_HZ );
-
-	/* Setup the tick interrupt in the EIC. */
-	EIC_IRQChannelPriorityConfig( WDG_IRQChannel, 1 );
-	EIC_IRQChannelConfig( WDG_IRQChannel, ENABLE );
-	EIC_IRQConfig( ENABLE );
-	WDG_ECITConfig( ENABLE );
-
-	/* Start the timer - interrupts are actually disabled at this point so
-	it is safe to do this here. */
-	WDG_CntOnOffConfig( ENABLE );
-}
-/*-----------------------------------------------------------*/
-
-__arm __interwork void vPortEnterCritical( void )
-{
-	/* Disable interrupts first! */
-	__disable_interrupt();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-__arm __interwork void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as we are leaving a critical section. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then interrupts should be
-		re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			__enable_interrupt();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/STR71x/portasm.s79 b/FreeRTOS/Source/portable/IAR/STR71x/portasm.s79
deleted file mode 100755
index 9067dcc..0000000
--- a/FreeRTOS/Source/portable/IAR/STR71x/portasm.s79
+++ /dev/null
@@ -1,76 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-		RSEG ICODE:CODE
-		CODE32
-
-	EXTERN vPortPreemptiveTick
-	EXTERN vTaskSwitchContext
-
-	PUBLIC vPortYieldProcessor
-	PUBLIC vPortStartFirstTask
-	PUBLIC vPortPreemptiveTickISR
-
-#include "ISR_Support.h"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Starting the first task is just a matter of restoring the context that
-; was created by pxPortInitialiseStack().
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortStartFirstTask:
-	portRESTORE_CONTEXT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Manual context switch function.  This is the SWI hander.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortYieldProcessor:
-	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
-								; as if the context was saved during and IRQ
-								; handler.
-
-	portSAVE_CONTEXT			; Save the context of the current task...
-	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
-	mov     lr, pc
-	BX R0
-	portRESTORE_CONTEXT			; Restore the context of the selected task.
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Preemptive context switch function.  This will only ever get used if
-; portUSE_PREEMPTION is set to 1 in portmacro.h.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortPreemptiveTickISR:
-	portSAVE_CONTEXT			; Save the context of the current task.
-
-	LDR R0, =vPortPreemptiveTick ; Increment the tick count - this may wake a task.
-	MOV lr, pc
-	BX R0
-
-	portRESTORE_CONTEXT			; Restore the context of the selected task.
-
-
-	END
-
diff --git a/FreeRTOS/Source/portable/IAR/STR71x/portmacro.h b/FreeRTOS/Source/portable/IAR/STR71x/portmacro.h
deleted file mode 100755
index 37d92ee..0000000
--- a/FreeRTOS/Source/portable/IAR/STR71x/portmacro.h
+++ /dev/null
@@ -1,121 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-#define portYIELD()					asm ( "SWI 0" )
-#define portNOP()					asm ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-__arm __interwork void vPortDisableInterruptsFromThumb( void );
-__arm __interwork void vPortEnableInterruptsFromThumb( void );
-__arm __interwork void vPortEnterCritical( void );
-__arm __interwork void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()	__disable_interrupt()
-#define portENABLE_INTERRUPTS()		__enable_interrupt()
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
-{													\
-extern void vTaskSwitchContext( void );				\
-													\
-	if( xSwitchRequired ) 							\
-	{												\
-		vTaskSwitchContext();						\
-	}												\
-}
-/*-----------------------------------------------------------*/
-
-/* EIC utilities. */
-#define portEIC_CICR_ADDR		*( ( uint32_t * ) 0xFFFFF804 )
-#define portEIC_IPR_ADDR		*( ( uint32_t * ) 0xFFFFF840 )
-#define portCLEAR_EIC()			portEIC_IPR_ADDR = 0x01 << portEIC_CICR_ADDR
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
-
diff --git a/FreeRTOS/Source/portable/IAR/STR75x/ISR_Support.h b/FreeRTOS/Source/portable/IAR/STR75x/ISR_Support.h
deleted file mode 100755
index babc698..0000000
--- a/FreeRTOS/Source/portable/IAR/STR75x/ISR_Support.h
+++ /dev/null
@@ -1,105 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	EXTERN pxCurrentTCB
-	EXTERN ulCriticalNesting
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-portSAVE_CONTEXT MACRO
-
-	; Push R0 as we are going to use the register.
-	STMDB	SP!, {R0}
-
-	; Set R0 to point to the task stack pointer.
-	STMDB	SP, {SP}^
-	NOP
-	SUB		SP, SP, #4
-	LDMIA	SP!, {R0}
-
-	; Push the return address onto the stack.
-	STMDB	R0!, {LR}
-
-	; Now we have saved LR we can use it instead of R0.
-	MOV		LR, R0
-
-	; Pop R0 so we can save it onto the system mode stack.
-	LDMIA	SP!, {R0}
-
-	; Push all the system mode registers onto the task stack.
-	STMDB	LR, {R0-LR}^
-	NOP
-	SUB		LR, LR, #60
-
-	; Push the SPSR onto the task stack.
-	MRS		R0, SPSR
-	STMDB	LR!, {R0}
-
-	LDR		R0, =ulCriticalNesting
-	LDR		R0, [R0]
-	STMDB	LR!, {R0}
-
-	; Store the new top of stack for the task.
-	LDR		R1, =pxCurrentTCB
-	LDR		R0, [R1]
-	STR		LR, [R0]
-
-	ENDM
-
-
-portRESTORE_CONTEXT MACRO
-
-	; Set the LR to the task stack.
-	LDR		R1, =pxCurrentTCB
-	LDR		R0, [R1]
-	LDR		LR, [R0]
-
-	; The critical nesting depth is the first item on the stack.
-	; Load it into the ulCriticalNesting variable.
-	LDR		R0, =ulCriticalNesting
-	LDMFD	LR!, {R1}
-	STR		R1, [R0]
-
-	; Get the SPSR from the stack.
-	LDMFD	LR!, {R0}
-	MSR		SPSR_cxsf, R0
-
-	; Restore all system mode registers for the task.
-	LDMFD	LR, {R0-R14}^
-	NOP
-
-	; Restore the return address.
-	LDR		LR, [LR, #+60]
-
-	; And return - correcting the offset in the LR to obtain the
-	; correct address.
-	SUBS	PC, LR, #4
-
-	ENDM
-
diff --git a/FreeRTOS/Source/portable/IAR/STR75x/port.c b/FreeRTOS/Source/portable/IAR/STR75x/port.c
deleted file mode 100755
index 8d919c9..0000000
--- a/FreeRTOS/Source/portable/IAR/STR75x/port.c
+++ /dev/null
@@ -1,237 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ST STR75x ARM7
- * port.
- *----------------------------------------------------------*/
-
-/* Library includes. */
-#include "75x_tb.h"
-#include "75x_eic.h"
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to setup the initial stack. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
-#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
-
-/* Prescale used on the timer clock when calculating the tick period. */
-#define portPRESCALE 20
-
-
-/*-----------------------------------------------------------*/
-
-/* Setup the TB to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/* ulCriticalNesting will get set to zero when the first task starts.  It
-cannot be initialised to 0 as this will cause interrupts to be enabled
-during the kernel initialisation process. */
-uint32_t ulCriticalNesting = ( uint32_t ) 9999;
-
-/* Tick interrupt routines for preemptive operation. */
-__arm void vPortPreemptiveTick( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
-	pxOriginalTOS = pxTopOfStack;
-
-	/* To ensure asserts in tasks.c don't fail, although in this case the assert
-	is not really required. */
-	pxTopOfStack--;
-
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* First on the stack is the return address - which in this case is the
-	start of the task.  The offset is added to make the return address appear
-	as it would within an IRQ ISR. */
-	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;	
-
-	/* When the task starts is will expect to find the function parameter in
-	R0. */
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The status register is set for system mode, with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-	pxTopOfStack--;
-
-	/* Interrupt flags cannot always be stored on the stack and will
-	instead be stored in a variable, which is then saved as part of the
-	tasks context. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-
-	return pxTopOfStack;	
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortStartFirstTask( void );
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task. */
-	vPortStartFirstTask();	
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the ARM port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-__arm void vPortPreemptiveTick( void )
-{
-	/* Increment the tick counter. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		/* Select a new task to execute. */
-		vTaskSwitchContext();
-	}
-		
-	TB_ClearITPendingBit( TB_IT_Update );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-EIC_IRQInitTypeDef  EIC_IRQInitStructure;	
-TB_InitTypeDef      TB_InitStructure;
-
-	/* Setup the EIC for the TB. */
-	EIC_IRQInitStructure.EIC_IRQChannelCmd = ENABLE;
-	EIC_IRQInitStructure.EIC_IRQChannel = TB_IRQChannel;
-	EIC_IRQInitStructure.EIC_IRQChannelPriority = 1;
-	EIC_IRQInit(&EIC_IRQInitStructure);
-	
-	/* Setup the TB for the generation of the tick interrupt. */
-	TB_InitStructure.TB_Mode = TB_Mode_Timing;
-	TB_InitStructure.TB_CounterMode = TB_CounterMode_Down;
-	TB_InitStructure.TB_Prescaler = portPRESCALE - 1;
-	TB_InitStructure.TB_AutoReload = ( ( configCPU_CLOCK_HZ / portPRESCALE ) / configTICK_RATE_HZ );
-	TB_Init(&TB_InitStructure);
-	
-	/* Enable TB Update interrupt */
-	TB_ITConfig(TB_IT_Update, ENABLE);
-
-	/* Clear TB Update interrupt pending bit */
-	TB_ClearITPendingBit(TB_IT_Update);
-
-	/* Enable TB */
-	TB_Cmd(ENABLE);
-}
-/*-----------------------------------------------------------*/
-
-__arm __interwork void vPortEnterCritical( void )
-{
-	/* Disable interrupts first! */
-	__disable_interrupt();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-__arm __interwork void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as we are leaving a critical section. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then interrupts should be
-		re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			__enable_interrupt();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/STR75x/portasm.s79 b/FreeRTOS/Source/portable/IAR/STR75x/portasm.s79
deleted file mode 100755
index 1d5674a..0000000
--- a/FreeRTOS/Source/portable/IAR/STR75x/portasm.s79
+++ /dev/null
@@ -1,63 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	RSEG ICODE:CODE
-	CODE32
-
-	EXTERN vPortPreemptiveTick
-	EXTERN vTaskSwitchContext
-
-	PUBLIC vPortYieldProcessor
-	PUBLIC vPortStartFirstTask
-
-#include "ISR_Support.h"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Starting the first task is just a matter of restoring the context that
-; was created by pxPortInitialiseStack().
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortStartFirstTask:
-	portRESTORE_CONTEXT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Manual context switch function.  This is the SWI hander.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortYieldProcessor:
-	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
-								; as if the context was saved during and IRQ
-								; handler.
-
-	portSAVE_CONTEXT			; Save the context of the current task...
-	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
-	mov     lr, pc
-	BX R0
-	portRESTORE_CONTEXT			; Restore the context of the selected task.
-
-
-
-	END
-
diff --git a/FreeRTOS/Source/portable/IAR/STR75x/portmacro.h b/FreeRTOS/Source/portable/IAR/STR75x/portmacro.h
deleted file mode 100755
index 77ec1b4..0000000
--- a/FreeRTOS/Source/portable/IAR/STR75x/portmacro.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-#define portYIELD()					asm ( "SWI 0" )
-#define portNOP()					asm ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-__arm __interwork void vPortEnterCritical( void );
-__arm __interwork void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()	__disable_interrupt()
-#define portENABLE_INTERRUPTS()		__enable_interrupt()
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
-{													\
-extern void vTaskSwitchContext( void );				\
-													\
-	if( xSwitchRequired ) 							\
-	{												\
-		vTaskSwitchContext();						\
-	}												\
-}
-/*-----------------------------------------------------------*/
-
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
-
diff --git a/FreeRTOS/Source/portable/IAR/STR91x/ISR_Support.h b/FreeRTOS/Source/portable/IAR/STR91x/ISR_Support.h
deleted file mode 100755
index 740f368..0000000
--- a/FreeRTOS/Source/portable/IAR/STR91x/ISR_Support.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	EXTERN pxCurrentTCB
-	EXTERN ulCriticalNesting
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-portSAVE_CONTEXT MACRO
-
-	; Push R0 as we are going to use the register. 					
-	STMDB	SP!, {R0}
-
-	; Set R0 to point to the task stack pointer. 					
-	STMDB	SP, {SP}^
-	NOP
-	SUB		SP, SP, #4
-	LDMIA	SP!, {R0}
-
-	; Push the return address onto the stack. 						
-	STMDB	R0!, {LR}
-
-	; Now we have saved LR we can use it instead of R0. 				
-	MOV		LR, R0
-
-	; Pop R0 so we can save it onto the system mode stack. 			
-	LDMIA	SP!, {R0}
-
-	; Push all the system mode registers onto the task stack. 		
-	STMDB	LR, {R0-LR}^
-	NOP
-	SUB		LR, LR, #60
-
-	; Push the SPSR onto the task stack. 							
-	MRS		R0, SPSR
-	STMDB	LR!, {R0}
-
-	LDR		R0, =ulCriticalNesting 
-	LDR		R0, [R0]
-	STMDB	LR!, {R0}
-
-	; Store the new top of stack for the task. 						
-	LDR		R1, =pxCurrentTCB
-	LDR		R0, [R1]
-	STR		LR, [R0]
-
-	ENDM
-
-
-portRESTORE_CONTEXT MACRO
-
-	; Set the LR to the task stack. 									
-	LDR		R1, =pxCurrentTCB
-	LDR		R0, [R1]
-	LDR		LR, [R0]
-
-	; The critical nesting depth is the first item on the stack. 	
-	; Load it into the ulCriticalNesting variable. 					
-	LDR		R0, =ulCriticalNesting
-	LDMFD	LR!, {R1}
-	STR		R1, [R0]
-
-	; Get the SPSR from the stack. 									
-	LDMFD	LR!, {R0}
-	MSR		SPSR_cxsf, R0
-
-	; Restore all system mode registers for the task. 				
-	LDMFD	LR, {R0-R14}^
-	NOP
-
-	; Restore the return address. 									
-	LDR		LR, [LR, #+60]
-
-	; And return - correcting the offset in the LR to obtain the 	
-	; correct address. 												
-	SUBS	PC, LR, #4
-
-	ENDM
-
diff --git a/FreeRTOS/Source/portable/IAR/STR91x/port.c b/FreeRTOS/Source/portable/IAR/STR91x/port.c
deleted file mode 100755
index af94429..0000000
--- a/FreeRTOS/Source/portable/IAR/STR91x/port.c
+++ /dev/null
@@ -1,421 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ST STR91x ARM9
- * port.
- *----------------------------------------------------------*/
-
-/* Library includes. */
-#include "91x_lib.h"
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef configUSE_WATCHDOG_TICK
-	#error configUSE_WATCHDOG_TICK must be set to either 1 or 0 in FreeRTOSConfig.h to use either the Watchdog or timer 2 to generate the tick interrupt respectively.
-#endif
-
-/* Constants required to setup the initial stack. */
-#ifndef _RUN_TASK_IN_ARM_MODE_
-	#define portINITIAL_SPSR			( ( StackType_t ) 0x3f ) /* System mode, THUMB mode, interrupts enabled. */
-#else
-	#define portINITIAL_SPSR 			( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#endif
-
-#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
-
-/* Constants required to handle critical sections. */
-#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
-
-#ifndef abs
-	#define abs(x) ((x)>0 ? (x) : -(x))
-#endif
-
-/**
- * Toggle a led using the following algorithm:
- * if ( GPIO_ReadBit(GPIO9, GPIO_Pin_2) )
- * {
- *   GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
- * }
- * else
- * {
- *   GPIO_WriteBit( GPIO9, GPIO_Pin_2, Bit_RESET );
- * }
- *
- */
-#define TOGGLE_LED(port,pin) 									\
-	if ( ((((port)->DR[(pin)<<2])) & (pin)) != Bit_RESET ) 		\
-	{															\
-    	(port)->DR[(pin) <<2] = 0x00;							\
-  	}															\
-  	else														\
-	{															\
-    	(port)->DR[(pin) <<2] = (pin);							\
-  	}
-
-
-/*-----------------------------------------------------------*/
-
-/* Setup the watchdog to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/* ulCriticalNesting will get set to zero when the first task starts.  It
-cannot be initialised to 0 as this will cause interrupts to be enabled
-during the kernel initialisation process. */
-uint32_t ulCriticalNesting = ( uint32_t ) 9999;
-
-/* Tick interrupt routines for cooperative and preemptive operation
-respectively.  The preemptive version is not defined as __irq as it is called
-from an asm wrapper function. */
-void WDG_IRQHandler( void );
-
-/* VIC interrupt default handler. */
-static void prvDefaultHandler( void );
-
-#if configUSE_WATCHDOG_TICK == 0
-	/* Used to update the OCR timer register */
-	static u16 s_nPulseLength;
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a task to look exactly as if a call to
- * portSAVE_CONTEXT had been called.
- *
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	StackType_t *pxOriginalTOS;
-
-	pxOriginalTOS = pxTopOfStack;
-
-	/* To ensure asserts in tasks.c don't fail, although in this case the assert
-	is not really required. */
-	pxTopOfStack--;
-
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro. */
-
-	/* First on the stack is the return address - which in this case is the
-	start of the task.  The offset is added to make the return address appear
-	as it would within an IRQ ISR. */
-	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;	
-
-	/* When the task starts is will expect to find the function parameter in
-	R0. */
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The status register is set for system mode, with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-	pxTopOfStack--;
-
-	/* Interrupt flags cannot always be stored on the stack and will
-	instead be stored in a variable, which is then saved as part of the
-	tasks context. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-
-	return pxTopOfStack;	
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortStartFirstTask( void );
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task. */
-	vPortStartFirstTask();	
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the ARM port will require this function as there
-	is nothing to return to.  */
-}
-/*-----------------------------------------------------------*/
-
-/* This function is called from an asm wrapper, so does not require the __irq
-keyword. */
-#if configUSE_WATCHDOG_TICK == 1
-
-	static void prvFindFactors(u32 n, u16 *a, u32 *b)
-	{
-		/* This function is copied from the ST STR7 library and is
-		copyright STMicroelectronics.  Reproduced with permission. */
-	
-		u32 b0;
-		u16 a0;
-		int32_t err, err_min=n;
-	
-		*a = a0 = ((n-1)/65536ul) + 1;
-		*b = b0 = n / *a;
-	
-		for (; *a <= 256; (*a)++)
-		{
-			*b = n / *a;
-			err = (int32_t)*a * (int32_t)*b - (int32_t)n;
-			if (abs(err) > (*a / 2))
-			{
-				(*b)++;
-				err = (int32_t)*a * (int32_t)*b - (int32_t)n;
-			}
-			if (abs(err) < abs(err_min))
-			{
-				err_min = err;
-				a0 = *a;
-				b0 = *b;
-				if (err == 0) break;
-			}
-		}
-	
-		*a = a0;
-		*b = b0;
-	}
-	/*-----------------------------------------------------------*/
-
-	static void prvSetupTimerInterrupt( void )
-	{
-	WDG_InitTypeDef xWdg;
-	uint16_t a;
-	uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ, b;
-	
-		/* Configure the watchdog as a free running timer that generates a
-		periodic interrupt. */
-	
-		SCU_APBPeriphClockConfig( __WDG, ENABLE );
-		WDG_DeInit();
-		WDG_StructInit(&xWdg);
-		prvFindFactors( n, &a, &b );
-		xWdg.WDG_Prescaler = a - 1;
-		xWdg.WDG_Preload = b - 1;
-		WDG_Init( &xWdg );
-		WDG_ITConfig(ENABLE);
-		
-		/* Configure the VIC for the WDG interrupt. */
-		VIC_Config( WDG_ITLine, VIC_IRQ, 10 );
-		VIC_ITCmd( WDG_ITLine, ENABLE );
-		
-		/* Install the default handlers for both VIC's. */
-		VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
-		VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
-		
-		WDG_Cmd(ENABLE);
-	}
-	/*-----------------------------------------------------------*/
-
-	void WDG_IRQHandler( void )
-	{
-		{
-			/* Increment the tick counter. */
-			if( xTaskIncrementTick() != pdFALSE )
-			{		
-				/* Select a new task to execute. */
-				vTaskSwitchContext();
-			}
-		
-			/* Clear the interrupt in the watchdog. */
-			WDG->SR &= ~0x0001;
-		}
-	}
-
-#else
-
-	static void prvFindFactors(u32 n, u8 *a, u16 *b)
-	{
-		/* This function is copied from the ST STR7 library and is
-		copyright STMicroelectronics.  Reproduced with permission. */
-	
-		u16 b0;
-		u8 a0;
-		int32_t err, err_min=n;
-	
-	
-		*a = a0 = ((n-1)/256) + 1;
-		*b = b0 = n / *a;
-	
-		for (; *a <= 256; (*a)++)
-		{
-			*b = n / *a;
-			err = (int32_t)*a * (int32_t)*b - (int32_t)n;
-			if (abs(err) > (*a / 2))
-			{
-				(*b)++;
-				err = (int32_t)*a * (int32_t)*b - (int32_t)n;
-			}
-			if (abs(err) < abs(err_min))
-			{
-				err_min = err;
-				a0 = *a;
-				b0 = *b;
-				if (err == 0) break;
-			}
-		}
-	
-		*a = a0;
-		*b = b0;
-	}
-	/*-----------------------------------------------------------*/
-
-	static void prvSetupTimerInterrupt( void )
-	{
-		uint8_t a;
-		uint16_t b;
-		uint32_t n = configCPU_PERIPH_HZ / configTICK_RATE_HZ;
-		
-		TIM_InitTypeDef timer;
-		
-		SCU_APBPeriphClockConfig( __TIM23, ENABLE );
-		TIM_DeInit(TIM2);
-		TIM_StructInit(&timer);
-		prvFindFactors( n, &a, &b );
-		
-		timer.TIM_Mode           = TIM_OCM_CHANNEL_1;
-		timer.TIM_OC1_Modes      = TIM_TIMING;
-		timer.TIM_Clock_Source   = TIM_CLK_APB;
-		timer.TIM_Clock_Edge     = TIM_CLK_EDGE_RISING;
-		timer.TIM_Prescaler      = a-1;
-		timer.TIM_Pulse_Level_1  = TIM_HIGH;
-		timer.TIM_Pulse_Length_1 = s_nPulseLength  = b-1;
-		
-		TIM_Init (TIM2, &timer);
-		TIM_ITConfig(TIM2, TIM_IT_OC1, ENABLE);
-		/* Configure the VIC for the WDG interrupt. */
-		VIC_Config( TIM2_ITLine, VIC_IRQ, 10 );
-		VIC_ITCmd( TIM2_ITLine, ENABLE );
-		
-		/* Install the default handlers for both VIC's. */
-		VIC0->DVAR = ( uint32_t ) prvDefaultHandler;
-		VIC1->DVAR = ( uint32_t ) prvDefaultHandler;
-		
-		TIM_CounterCmd(TIM2, TIM_CLEAR);
-		TIM_CounterCmd(TIM2, TIM_START);
-	}
-	/*-----------------------------------------------------------*/
-
-	void TIM2_IRQHandler( void )
-	{
-		/* Reset the timer counter to avioid overflow. */
-		TIM2->OC1R += s_nPulseLength;
-		
-		/* Increment the tick counter. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Select a new task to run. */
-			vTaskSwitchContext();
-		}
-		
-		/* Clear the interrupt in the watchdog. */
-		TIM2->SR &= ~TIM_FLAG_OC1;
-	}
-
-#endif /* USE_WATCHDOG_TICK */
-
-/*-----------------------------------------------------------*/
-
-__arm __interwork void vPortEnterCritical( void )
-{
-	/* Disable interrupts first! */
-	portDISABLE_INTERRUPTS();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-__arm __interwork void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as we are leaving a critical section. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then interrupts should be
-		re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			portENABLE_INTERRUPTS();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvDefaultHandler( void )
-{
-}
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/IAR/STR91x/portasm.s79 b/FreeRTOS/Source/portable/IAR/STR91x/portasm.s79
deleted file mode 100755
index d112743..0000000
--- a/FreeRTOS/Source/portable/IAR/STR91x/portasm.s79
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-		RSEG ICODE:CODE
-		CODE32
-
-	EXTERN vTaskSwitchContext
-
-	PUBLIC vPortYieldProcessor
-	PUBLIC vPortStartFirstTask
-
-#include "ISR_Support.h"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Starting the first task is just a matter of restoring the context that
-; was created by pxPortInitialiseStack().
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortStartFirstTask:
-	portRESTORE_CONTEXT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Manual context switch function.  This is the SWI hander.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortYieldProcessor:
-	ADD		LR, LR, #4			; Add 4 to the LR to make the LR appear exactly
-								; as if the context was saved during and IRQ
-								; handler.
-								
-	portSAVE_CONTEXT			; Save the context of the current task...
-	LDR R0, =vTaskSwitchContext	; before selecting the next task to execute.
-	MOV     lr, pc
-	BX R0
-	portRESTORE_CONTEXT			; Restore the context of the selected task.
-
-	END
-
diff --git a/FreeRTOS/Source/portable/IAR/STR91x/portmacro.h b/FreeRTOS/Source/portable/IAR/STR91x/portmacro.h
deleted file mode 100755
index e28d905..0000000
--- a/FreeRTOS/Source/portable/IAR/STR91x/portmacro.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Type definitions. */
-#define portCHAR			char
-#define portFLOAT			float
-#define portDOUBLE			double
-#define portLONG			long
-#define portSHORT			short
-#define portSTACK_TYPE		uint32_t
-#define portBASE_TYPE		long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-#define portYIELD()					asm ( "SWI 0" )
-#define portNOP()					asm ( "NOP" )
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-__arm __interwork void vPortEnterCritical( void );
-__arm __interwork void vPortExitCritical( void );
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-
-#define portDISABLE_INTERRUPTS()	__disable_interrupt()
-#define portENABLE_INTERRUPTS()		__enable_interrupt()
-
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-#define portEND_SWITCHING_ISR( xSwitchRequired ) 	\
-{													\
-extern void vTaskSwitchContext( void );				\
-													\
-	if( xSwitchRequired ) 							\
-	{												\
-		vTaskSwitchContext();						\
-	}												\
-}
-/*-----------------------------------------------------------*/
-
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
-
diff --git a/FreeRTOS/Source/portable/IAR/V850ES/ISR_Support.h b/FreeRTOS/Source/portable/IAR/V850ES/ISR_Support.h
deleted file mode 100755
index dbe871d..0000000
--- a/FreeRTOS/Source/portable/IAR/V850ES/ISR_Support.h
+++ /dev/null
@@ -1,149 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	EXTERN pxCurrentTCB
-	EXTERN usCriticalNesting
-
-#include "FreeRTOSConfig.h"
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Context save and restore macro definitions
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-portSAVE_CONTEXT MACRO
-
-    add     -0x0C,sp			; prepare stack to save necessary values
-    st.w    lp,8[sp]			; store LP to stack
-    stsr    0,r31
-    st.w    lp,4[sp]			; store EIPC to stack
-    stsr    1,lp
-    st.w    lp,0[sp]			; store EIPSW to stack
-#if configDATA_MODE == 1                                        ; Using the Tiny data model
-    prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
-    sst.w   r19,72[ep]
-    sst.w   r18,68[ep]
-    sst.w   r17,64[ep]
-    sst.w   r16,60[ep]
-    sst.w   r15,56[ep]
-    sst.w   r14,52[ep]
-    sst.w   r13,48[ep]
-    sst.w   r12,44[ep]
-    sst.w   r11,40[ep]
-    sst.w   r10,36[ep]
-    sst.w   r9,32[ep]
-    sst.w   r8,28[ep]
-    sst.w   r7,24[ep]
-    sst.w   r6,20[ep]
-    sst.w   r5,16[ep]
-    sst.w   r4,12[ep]
-#else                                                           ; Using the Small/Large data model
-    prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp     ; save general purpose registers
-    sst.w   r19,68[ep]
-    sst.w   r18,64[ep]
-    sst.w   r17,60[ep]
-    sst.w   r16,56[ep]
-    sst.w   r15,52[ep]
-    sst.w   r14,48[ep]
-    sst.w   r13,44[ep]
-    sst.w   r12,40[ep]
-    sst.w   r11,36[ep]
-    sst.w   r10,32[ep]
-    sst.w   r9,28[ep]
-    sst.w   r8,24[ep]
-    sst.w   r7,20[ep]
-    sst.w   r6,16[ep]
-    sst.w   r5,12[ep]
-#endif /* configDATA_MODE */
-    sst.w   r2,8[ep]
-    sst.w   r1,4[ep]
-    MOVHI   hi1(usCriticalNesting),r0,r1	; save usCriticalNesting value to stack
-    ld.w    lw1(usCriticalNesting)[r1],r2
-    sst.w   r2,0[ep]
-    MOVHI   hi1(pxCurrentTCB),r0,r1			; save SP to top of current TCB
-    ld.w    lw1(pxCurrentTCB)[r1],r2
-    st.w    sp,0[r2]
-    ENDM
-
-
-portRESTORE_CONTEXT MACRO
-
-    MOVHI   hi1(pxCurrentTCB),r0,r1			; get Stackpointer address
-    ld.w    lw1(pxCurrentTCB)[r1],sp
-    MOV     sp,r1
-    ld.w    0[r1],sp						; load stackpointer
-    MOV     sp,ep							; set stack pointer to element pointer
-    sld.w   0[ep],r1						; load usCriticalNesting value from stack
-    MOVHI   hi1(usCriticalNesting),r0,r2
-    st.w    r1,lw1(usCriticalNesting)[r2]
-    sld.w   4[ep],r1						; restore general purpose registers
-    sld.w   8[ep],r2
-#if configDATA_MODE == 1					; Using Tiny data model
-    sld.w   12[ep],r4
-    sld.w   16[ep],r5
-    sld.w   20[ep],r6
-    sld.w   24[ep],r7
-    sld.w   28[ep],r8
-    sld.w   32[ep],r9
-    sld.w   36[ep],r10
-    sld.w   40[ep],r11
-    sld.w   44[ep],r12
-    sld.w   48[ep],r13
-    sld.w   52[ep],r14
-    sld.w   56[ep],r15
-    sld.w   60[ep],r16
-    sld.w   64[ep],r17
-    sld.w   68[ep],r18
-    sld.w   72[ep],r19
-    dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
-#else										; Using Small/Large data model
-    sld.w   12[ep],r5
-    sld.w   16[ep],r6
-    sld.w   20[ep],r7
-    sld.w   24[ep],r8
-    sld.w   28[ep],r9
-    sld.w   32[ep],r10
-    sld.w   36[ep],r11
-    sld.w   40[ep],r12
-    sld.w   44[ep],r13
-    sld.w   48[ep],r14
-    sld.w   52[ep],r15
-    sld.w   56[ep],r16
-    sld.w   60[ep],r17
-    sld.w   64[ep],r18
-    sld.w   68[ep],r19
-    dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
-#endif /* configDATA_MODE */
-    ld.w    0[sp],lp						; restore EIPSW from stack
-    ldsr    lp,1
-    ld.w    4[sp],lp						; restore EIPC from stack
-    ldsr    lp,0
-    ld.w    8[sp],lp						; restore LP from stack
-    add     0x0C,sp							; set SP to right position
-
-    RETI
-
-    ENDM
diff --git a/FreeRTOS/Source/portable/IAR/V850ES/port.c b/FreeRTOS/Source/portable/IAR/V850ES/port.c
deleted file mode 100755
index 3dd8f8a..0000000
--- a/FreeRTOS/Source/portable/IAR/V850ES/port.c
+++ /dev/null
@@ -1,183 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Critical nesting should be initialised to a non zero value so interrupts don't
-accidentally get enabled before the scheduler is started. */
-#define portINITIAL_CRITICAL_NESTING  (( StackType_t ) 10)
-
-/* The PSW value assigned to tasks when they start to run for the first time. */
-#define portPSW		  (( StackType_t ) 0x00000000)
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/* Keeps track of the nesting level of critical sections. */
-volatile StackType_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
-/*-----------------------------------------------------------*/
-
-/* Sets up the timer to generate the tick interrupt. */
-static void prvSetupTimerInterrupt( void );
-
-/*-----------------------------------------------------------*/
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	*pxTopOfStack = ( StackType_t ) pxCode;          /* Task function start address */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;          /* Task function start address */
-	pxTopOfStack--;
-	*pxTopOfStack = portPSW;                            /* Initial PSW value */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x20202020;      /* Initial Value of R20 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x21212121;      /* Initial Value of R21 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x22222222;      /* Initial Value of R22 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x23232323;      /* Initial Value of R23 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x24242424;      /* Initial Value of R24 */
-	pxTopOfStack--;
-#if (__DATA_MODEL__ == 0) || (__DATA_MODEL__ == 1)
-	*pxTopOfStack = ( StackType_t ) 0x25252525;      /* Initial Value of R25 */
-	pxTopOfStack--;
-#endif /* configDATA_MODE */
-	*pxTopOfStack = ( StackType_t ) 0x26262626;      /* Initial Value of R26 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x27272727;      /* Initial Value of R27 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x28282828;      /* Initial Value of R28 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x29292929;      /* Initial Value of R29 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x30303030;      /* Initial Value of R30 */
-	pxTopOfStack--; 	
-	*pxTopOfStack = ( StackType_t ) 0x19191919;      /* Initial Value of R19 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x18181818;      /* Initial Value of R18 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x17171717;      /* Initial Value of R17 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x16161616;      /* Initial Value of R16 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x15151515;      /* Initial Value of R15 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x14141414;      /* Initial Value of R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x13131313;      /* Initial Value of R13 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;      /* Initial Value of R12 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x11111111;      /* Initial Value of R11 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x10101010;      /* Initial Value of R10 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x99999999;      /* Initial Value of R09 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x88888888;      /* Initial Value of R08 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x77777777;      /* Initial Value of R07 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x66666666;      /* Initial Value of R06 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x55555555;      /* Initial Value of R05 */
-	pxTopOfStack--;
-#if __DATA_MODEL__ == 0 || __DATA_MODEL__ == 1
-	*pxTopOfStack = ( StackType_t ) 0x44444444;      /* Initial Value of R04 */
-	pxTopOfStack--;
-#endif /* configDATA_MODE */
-	*pxTopOfStack = ( StackType_t ) 0x22222222;      /* Initial Value of R02 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pvParameters;    /* R1 is expected to hold the function parameter*/
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
-
-	/*
-	 * Return a pointer to the top of the stack we have generated so this can
-	 * be stored in the task control block for the task.
-	 */
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Setup the hardware to generate the tick.  Interrupts are disabled when
-	this function is called. */
-	prvSetupTimerInterrupt();
-
-	/* Restore the context of the first task that is going to run. */
-	vPortStart();
-
-	/* Should not get here as the tasks are now running! */
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the V850ES/Fx3 port will get stopped.  If required simply
-	disable the tick interrupt here. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Hardware initialisation to generate the RTOS tick.  This uses
- */
-static void prvSetupTimerInterrupt( void )
-{
-	TM0CE     = 0;	/* TMM0 operation disable */
-	TM0EQMK0  = 1;	/* INTTM0EQ0 interrupt disable */
-	TM0EQIF0  = 0;	/* clear INTTM0EQ0 interrupt flag */
-
-	#ifdef __IAR_V850ES_Fx3__
-	{
-		TM0CMP0   = (((configCPU_CLOCK_HZ / configTICK_RATE_HZ) / 2)-1);    /* divided by 2 because peripherals only run at CPU_CLOCK/2 */
-	}
-	#else
-	{
-		TM0CMP0   = (configCPU_CLOCK_HZ / configTICK_RATE_HZ);	
-	}
-	#endif
-
-	TM0EQIC0 &= 0xF8;
-	TM0CTL0   = 0x00;
-	TM0EQIF0 =  0;	/* clear INTTM0EQ0 interrupt flag */
-	TM0EQMK0 =  0;	/* INTTM0EQ0 interrupt enable */
-	TM0CE =     1;	/* TMM0 operation enable */
-}
-/*-----------------------------------------------------------*/
-
-
diff --git a/FreeRTOS/Source/portable/IAR/V850ES/portasm.s85 b/FreeRTOS/Source/portable/IAR/V850ES/portasm.s85
deleted file mode 100755
index 31d0c8d..0000000
--- a/FreeRTOS/Source/portable/IAR/V850ES/portasm.s85
+++ /dev/null
@@ -1,315 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-; Note: Select the correct include files for the device used by the application.
-#include "FreeRTOSConfig.h"
-;------------------------------------------------------------------------------
-
-; Functions used by scheduler
-;------------------------------------------------------------------------------
-    EXTERN    vTaskSwitchContext
-    EXTERN    xTaskIncrementTick
-
-; Variables used by scheduler
-;------------------------------------------------------------------------------
-    EXTERN    pxCurrentTCB
-    EXTERN    usCriticalNesting
-
-; Functions implemented in this file
-;------------------------------------------------------------------------------
-    PUBLIC    vPortYield
-    PUBLIC    vPortStart
-
-; Security ID definition
-;------------------------------------------------------------------------------
-#define	CG_SECURITY0	0FFH
-#define	CG_SECURITY1	0FFH
-#define	CG_SECURITY2	0FFH
-#define	CG_SECURITY3	0FFH
-#define	CG_SECURITY4	0FFH
-#define	CG_SECURITY5	0FFH
-#define	CG_SECURITY6	0FFH
-#define	CG_SECURITY7	0FFH
-#define	CG_SECURITY8	0FFH
-#define	CG_SECURITY9	0FFH
-
-; Tick ISR Prototype
-;------------------------------------------------------------------------------
-        PUBWEAK `??MD_INTTM0EQ0??INTVEC 640`
-        PUBLIC MD_INTTM0EQ0
-
-MD_INTTM0EQ0        SYMBOL "MD_INTTM0EQ0"
-`??MD_INTTM0EQ0??INTVEC 640` SYMBOL "??INTVEC 640", MD_INTTM0EQ0
-
-;------------------------------------------------------------------------------
-;   portSAVE_CONTEXT MACRO
-;   Saves the context of the remaining general purpose registers
-;   and the usCriticalNesting Value of the active Task onto the task stack
-;   saves stack pointer to the TCB
-;------------------------------------------------------------------------------
-portSAVE_CONTEXT MACRO
-#if configDATA_MODE == 1                                        ; Using the Tiny data model
-    prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
-    sst.w   r19,72[ep]
-    sst.w   r18,68[ep]
-    sst.w   r17,64[ep]
-    sst.w   r16,60[ep]
-    sst.w   r15,56[ep]
-    sst.w   r14,52[ep]
-    sst.w   r13,48[ep]
-    sst.w   r12,44[ep]
-    sst.w   r11,40[ep]
-    sst.w   r10,36[ep]
-    sst.w   r9,32[ep]
-    sst.w   r8,28[ep]
-    sst.w   r7,24[ep]
-    sst.w   r6,20[ep]
-    sst.w   r5,16[ep]
-    sst.w   r4,12[ep]
-#else                                                           ; Using the Small/Large data model
-    prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp     ; save general purpose registers
-    sst.w   r19,68[ep]
-    sst.w   r18,64[ep]
-    sst.w   r17,60[ep]
-    sst.w   r16,56[ep]
-    sst.w   r15,52[ep]
-    sst.w   r14,48[ep]
-    sst.w   r13,44[ep]
-    sst.w   r12,40[ep]
-    sst.w   r11,36[ep]
-    sst.w   r10,32[ep]
-    sst.w   r9,28[ep]
-    sst.w   r8,24[ep]
-    sst.w   r7,20[ep]
-    sst.w   r6,16[ep]
-    sst.w   r5,12[ep]
-#endif /* configDATA_MODE */
-    sst.w   r2,8[ep]
-    sst.w   r1,4[ep]
-    MOVHI   hi1(usCriticalNesting),r0,r1                        ; save usCriticalNesting value to stack
-    ld.w    lw1(usCriticalNesting)[r1],r2
-    sst.w   r2,0[ep]
-    MOVHI   hi1(pxCurrentTCB),r0,r1                             ; save SP to top of current TCB
-    ld.w    lw1(pxCurrentTCB)[r1],r2
-    st.w    sp,0[r2]
-    ENDM
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   portRESTORE_CONTEXT MACRO
-;   Gets stack pointer from the current TCB
-;   Restores the context of the usCriticalNesting value and general purpose
-;   registers of the selected task from the task stack
-;------------------------------------------------------------------------------
-portRESTORE_CONTEXT MACRO
-    MOVHI   hi1(pxCurrentTCB),r0,r1         ; get Stackpointer address
-    ld.w    lw1(pxCurrentTCB)[r1],sp
-    MOV     sp,r1
-    ld.w    0[r1],sp                        ; load stackpointer
-    MOV     sp,ep                           ; set stack pointer to element pointer
-    sld.w   0[ep],r1                        ; load usCriticalNesting value from stack
-    MOVHI   hi1(usCriticalNesting),r0,r2
-    st.w    r1,lw1(usCriticalNesting)[r2]
-    sld.w   4[ep],r1                        ; restore general purpose registers
-    sld.w   8[ep],r2
-#if configDATA_MODE == 1                    ; Using Tiny data model
-    sld.w   12[ep],r4
-    sld.w   16[ep],r5
-    sld.w   20[ep],r6
-    sld.w   24[ep],r7
-    sld.w   28[ep],r8
-    sld.w   32[ep],r9
-    sld.w   36[ep],r10
-    sld.w   40[ep],r11
-    sld.w   44[ep],r12
-    sld.w   48[ep],r13
-    sld.w   52[ep],r14
-    sld.w   56[ep],r15
-    sld.w   60[ep],r16
-    sld.w   64[ep],r17
-    sld.w   68[ep],r18
-    sld.w   72[ep],r19
-    dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
-#else                                       ; Using Small/Large data model
-    sld.w   12[ep],r5
-    sld.w   16[ep],r6
-    sld.w   20[ep],r7
-    sld.w   24[ep],r8
-    sld.w   28[ep],r9
-    sld.w   32[ep],r10
-    sld.w   36[ep],r11
-    sld.w   40[ep],r12
-    sld.w   44[ep],r13
-    sld.w   48[ep],r14
-    sld.w   52[ep],r15
-    sld.w   56[ep],r16
-    sld.w   60[ep],r17
-    sld.w   64[ep],r18
-    sld.w   68[ep],r19
-    dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
-#endif /* configDATA_MODE */
-    ENDM
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   Restore the context of the first task that is going to run.
-;
-;   Input:  NONE
-;
-;   Call:   CALL    vPortStart
-;
-;   Output: NONE
-;------------------------------------------------------------------------------
-    RSEG CODE:CODE
-vPortStart:
-    portRESTORE_CONTEXT	                    ; Restore the context of whichever task the ...
-    ld.w    0[sp],lp
-    ldsr    lp,5                            ; restore PSW
-    DI
-    ld.w    4[sp],lp                        ; restore LP
-    ld.w    8[sp],lp                        ; restore LP
-    ADD     0x0C,sp                         ; set SP to right position
-    EI
-    jmp     [lp]
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   Port Yield function to check for a Task switch in the cooperative and
-;   preemptive mode
-;
-;   Input:  NONE
-;
-;   Call:   CALL    vPortYield
-;
-;   Output: NONE
-;------------------------------------------------------------------------------
-
-	RSEG CODE:CODE
-vPortYield:
-
-    add     -0x0C,sp                          ; prepare stack to save necessary values
-    st.w    lp,8[sp]                        ; store LP to stack
-    stsr    0,r31
-    st.w    lp,4[sp]                        ; store EIPC to stack
-    stsr    1,lp
-    st.w    lp,0[sp]                        ; store EIPSW to stack
-    portSAVE_CONTEXT		            ; Save the context of the current task.
-    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
-    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
-                		            ; ... scheduler decided should run.
-	ld.w    0[sp],lp                        ; restore EIPSW from stack
-    ldsr    lp,1
-    ld.w    4[sp],lp                        ; restore EIPC from stack
-    ldsr    lp,0
-    ld.w    8[sp],lp                        ; restore LP from stack
-    add     0x0C,sp                         ; set SP to right position
-
-    RETI
-
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   Perform the necessary steps of the Tick Count Increment and Task Switch
-;   depending on the chosen kernel configuration
-;
-;   Input:  NONE
-;
-;   Call:   ISR
-;
-;   Output: NONE
-;------------------------------------------------------------------------------
-#if configUSE_PREEMPTION == 1               ; use preemptive kernel mode
-
-MD_INTTM0EQ0:
-
-    add     -0x0C,sp                          ; prepare stack to save necessary values
-    st.w    lp,8[sp]                        ; store LP to stack
-    stsr    0,r31
-    st.w    lp,4[sp]                        ; store EIPC to stack
-    stsr    1,lp
-    st.w    lp,0[sp]                        ; store EIPSW to stack
-    portSAVE_CONTEXT		            ; Save the context of the current task.
-    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
-    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
-    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
-                		            ; ... scheduler decided should run.
-    ld.w    0[sp],lp                        ; restore EIPSW from stack
-    ldsr    lp,1
-    ld.w    4[sp],lp                        ; restore EIPC from stack
-    ldsr    lp,0
-    ld.w    8[sp],lp                        ; restore LP from stack
-    add     0x0C,sp                         ; set SP to right position
-
-    RETI
-;------------------------------------------------------------------------------
-#else                                       ; use cooperative kernel mode
-
-MD_INTTM0EQ0:
-    prepare {lp,ep},8,sp
-    sst.w   r1,4[ep]
-    sst.w   r5,0[ep]
-    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
-    sld.w   0[ep],r5
-    sld.w   4[ep],r1
-    dispose 8,{lp,ep}
-    RETI
-#endif /* configUSE_PREEMPTION */
-
-;------------------------------------------------------------------------------
-        COMMON INTVEC:CODE:ROOT(2)
-        ORG 640
-`??MD_INTTM0EQ0??INTVEC 640`:
-        JR MD_INTTM0EQ0
-
-        RSEG NEAR_ID:CONST:SORT:NOROOT(2)
-`?`:
-        DW 10
-
-      COMMON INTVEC:CODE:ROOT(2)
-      ORG 40H
-`??vPortYield??INTVEC 40`:
-        JR vPortYield
-
-;------------------------------------------------------------------------------
-; set microcontroller security ID
-
-      COMMON INTVEC:CODE:ROOT(2)
-      ORG 70H
-`SECUID`:
-      DB CG_SECURITY0
-      DB CG_SECURITY1
-      DB CG_SECURITY2
-      DB CG_SECURITY3
-      DB CG_SECURITY4
-      DB CG_SECURITY5
-      DB CG_SECURITY6
-      DB CG_SECURITY7
-      DB CG_SECURITY8
-      DB CG_SECURITY9
-
-
-      END
-
diff --git a/FreeRTOS/Source/portable/IAR/V850ES/portasm_Fx3.s85 b/FreeRTOS/Source/portable/IAR/V850ES/portasm_Fx3.s85
deleted file mode 100755
index 89b1f52..0000000
--- a/FreeRTOS/Source/portable/IAR/V850ES/portasm_Fx3.s85
+++ /dev/null
@@ -1,335 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-; Note: Select the correct include files for the device used by the application.
-#include "FreeRTOSConfig.h"
-;------------------------------------------------------------------------------
-
-; Functions used by scheduler
-;------------------------------------------------------------------------------
-    EXTERN    vTaskSwitchContext
-    EXTERN    xTaskIncrementTick
-
-; Variables used by scheduler
-;------------------------------------------------------------------------------
-    EXTERN    pxCurrentTCB
-    EXTERN    usCriticalNesting
-
-; Functions implemented in this file
-;------------------------------------------------------------------------------
-    PUBLIC    vPortYield
-    PUBLIC    vPortStart
-
-; Security ID definition
-;------------------------------------------------------------------------------
-#define	CG_SECURITY0	0FFH
-#define	CG_SECURITY1	0FFH
-#define	CG_SECURITY2	0FFH
-#define	CG_SECURITY3	0FFH
-#define	CG_SECURITY4	0FFH
-#define	CG_SECURITY5	0FFH
-#define	CG_SECURITY6	0FFH
-#define	CG_SECURITY7	0FFH
-#define	CG_SECURITY8	0FFH
-#define	CG_SECURITY9	0FFH
-
-; Option Byte definitions
-;------------------------------------------------------------------------------
-#define	CG_OPTION7A	0x00
-#define	CG_OPTION7B	0x04
-#define	OPT7C		0x00
-#define	OPT7D		0x00
-#define	OPT7E		0x00
-#define	OPT7F		0x00
-
-; Tick ISR Prototype
-;------------------------------------------------------------------------------
-        PUBWEAK `??MD_INTTM0EQ0??INTVEC 608`
-        PUBLIC MD_INTTM0EQ0
-
-MD_INTTM0EQ0        SYMBOL "MD_INTTM0EQ0"
-`??MD_INTTM0EQ0??INTVEC 608` SYMBOL "??INTVEC 608", MD_INTTM0EQ0
-
-;------------------------------------------------------------------------------
-;   portSAVE_CONTEXT MACRO
-;   Saves the context of the remaining general purpose registers
-;   and the usCriticalNesting Value of the active Task onto the task stack
-;   saves stack pointer to the TCB
-;------------------------------------------------------------------------------
-portSAVE_CONTEXT MACRO
-#if configDATA_MODE == 1                                        ; Using the Tiny data model
-    prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
-    sst.w   r19,72[ep]
-    sst.w   r18,68[ep]
-    sst.w   r17,64[ep]
-    sst.w   r16,60[ep]
-    sst.w   r15,56[ep]
-    sst.w   r14,52[ep]
-    sst.w   r13,48[ep]
-    sst.w   r12,44[ep]
-    sst.w   r11,40[ep]
-    sst.w   r10,36[ep]
-    sst.w   r9,32[ep]
-    sst.w   r8,28[ep]
-    sst.w   r7,24[ep]
-    sst.w   r6,20[ep]
-    sst.w   r5,16[ep]
-    sst.w   r4,12[ep]
-#else                                                           ; Using the Small/Large data model
-    prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp     ; save general purpose registers
-    sst.w   r19,68[ep]
-    sst.w   r18,64[ep]
-    sst.w   r17,60[ep]
-    sst.w   r16,56[ep]
-    sst.w   r15,52[ep]
-    sst.w   r14,48[ep]
-    sst.w   r13,44[ep]
-    sst.w   r12,40[ep]
-    sst.w   r11,36[ep]
-    sst.w   r10,32[ep]
-    sst.w   r9,28[ep]
-    sst.w   r8,24[ep]
-    sst.w   r7,20[ep]
-    sst.w   r6,16[ep]
-    sst.w   r5,12[ep]
-#endif /* configDATA_MODE */
-    sst.w   r2,8[ep]
-    sst.w   r1,4[ep]
-    MOVHI   hi1(usCriticalNesting),r0,r1                        ; save usCriticalNesting value to stack
-    ld.w    lw1(usCriticalNesting)[r1],r2
-    sst.w   r2,0[ep]
-    MOVHI   hi1(pxCurrentTCB),r0,r1                             ; save SP to top of current TCB
-    ld.w    lw1(pxCurrentTCB)[r1],r2
-    st.w    sp,0[r2]
-    ENDM
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   portRESTORE_CONTEXT MACRO
-;   Gets stack pointer from the current TCB
-;   Restores the context of the usCriticalNesting value and general purpose
-;   registers of the selected task from the task stack
-;------------------------------------------------------------------------------
-portRESTORE_CONTEXT MACRO
-    MOVHI   hi1(pxCurrentTCB),r0,r1         ; get Stackpointer address
-    ld.w    lw1(pxCurrentTCB)[r1],sp
-    MOV     sp,r1
-    ld.w    0[r1],sp                        ; load stackpointer
-    MOV     sp,ep                           ; set stack pointer to element pointer
-    sld.w   0[ep],r1                        ; load usCriticalNesting value from stack
-    MOVHI   hi1(usCriticalNesting),r0,r2
-    st.w    r1,lw1(usCriticalNesting)[r2]
-    sld.w   4[ep],r1                        ; restore general purpose registers
-    sld.w   8[ep],r2
-#if configDATA_MODE == 1                    ; Using Tiny data model
-    sld.w   12[ep],r4
-    sld.w   16[ep],r5
-    sld.w   20[ep],r6
-    sld.w   24[ep],r7
-    sld.w   28[ep],r8
-    sld.w   32[ep],r9
-    sld.w   36[ep],r10
-    sld.w   40[ep],r11
-    sld.w   44[ep],r12
-    sld.w   48[ep],r13
-    sld.w   52[ep],r14
-    sld.w   56[ep],r15
-    sld.w   60[ep],r16
-    sld.w   64[ep],r17
-    sld.w   68[ep],r18
-    sld.w   72[ep],r19
-    dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
-#else                                       ; Using Small/Large data model
-    sld.w   12[ep],r5
-    sld.w   16[ep],r6
-    sld.w   20[ep],r7
-    sld.w   24[ep],r8
-    sld.w   28[ep],r9
-    sld.w   32[ep],r10
-    sld.w   36[ep],r11
-    sld.w   40[ep],r12
-    sld.w   44[ep],r13
-    sld.w   48[ep],r14
-    sld.w   52[ep],r15
-    sld.w   56[ep],r16
-    sld.w   60[ep],r17
-    sld.w   64[ep],r18
-    sld.w   68[ep],r19
-    dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
-#endif /* configDATA_MODE */
-    ENDM
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   Restore the context of the first task that is going to run.
-;
-;   Input:  NONE
-;
-;   Call:   CALL    vPortStart
-;
-;   Output: NONE
-;------------------------------------------------------------------------------
-    RSEG CODE:CODE
-vPortStart:
-    portRESTORE_CONTEXT	                    ; Restore the context of whichever task the ...
-    ld.w    0[sp],lp
-    ldsr    lp,5                            ; restore PSW
-    DI
-    ld.w    4[sp],lp                        ; restore LP
-    ld.w    8[sp],lp                        ; restore LP
-    ADD     0x0C,sp                         ; set SP to right position
-    EI
-    jmp     [lp]
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   Port Yield function to check for a Task switch in the cooperative and
-;   preemptive mode
-;
-;   Input:  NONE
-;
-;   Call:   CALL    vPortYield
-;
-;   Output: NONE
-;------------------------------------------------------------------------------
-
-	RSEG CODE:CODE
-vPortYield:
-
-    add     -0x0C,sp                          ; prepare stack to save necessary values
-    st.w    lp,8[sp]                        ; store LP to stack
-    stsr    0,r31
-    st.w    lp,4[sp]                        ; store EIPC to stack
-    stsr    1,lp
-    st.w    lp,0[sp]                        ; store EIPSW to stack
-    portSAVE_CONTEXT		            ; Save the context of the current task.
-    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
-    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
-                		            ; ... scheduler decided should run.
-	ld.w    0[sp],lp                        ; restore EIPSW from stack
-    ldsr    lp,1
-    ld.w    4[sp],lp                        ; restore EIPC from stack
-    ldsr    lp,0
-    ld.w    8[sp],lp                        ; restore LP from stack
-    add     0x0C,sp                         ; set SP to right position
-
-    RETI
-
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   Perform the necessary steps of the Tick Count Increment and Task Switch
-;   depending on the chosen kernel configuration
-;
-;   Input:  NONE
-;
-;   Call:   ISR
-;
-;   Output: NONE
-;------------------------------------------------------------------------------
-#if configUSE_PREEMPTION == 1               ; use preemptive kernel mode
-
-MD_INTTM0EQ0:
-
-    add     -0x0C,sp                          ; prepare stack to save necessary values
-    st.w    lp,8[sp]                        ; store LP to stack
-    stsr    0,r31
-    st.w    lp,4[sp]                        ; store EIPC to stack
-    stsr    1,lp
-    st.w    lp,0[sp]                        ; store EIPSW to stack
-    portSAVE_CONTEXT		            ; Save the context of the current task.
-    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
-    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
-    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
-                		            ; ... scheduler decided should run.
-    ld.w    0[sp],lp                        ; restore EIPSW from stack
-    ldsr    lp,1
-    ld.w    4[sp],lp                        ; restore EIPC from stack
-    ldsr    lp,0
-    ld.w    8[sp],lp                        ; restore LP from stack
-    add     0x0C,sp                         ; set SP to right position
-
-    RETI
-;------------------------------------------------------------------------------
-#else                                       ; use cooperative kernel mode
-
-MD_INTTM0EQ0:
-    prepare {lp,ep},8,sp
-    sst.w   r1,4[ep]
-    sst.w   r5,0[ep]
-    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
-    sld.w   0[ep],r5
-    sld.w   4[ep],r1
-    dispose 8,{lp,ep}
-    RETI
-#endif /* configUSE_PREEMPTION */
-
-;------------------------------------------------------------------------------
-        COMMON INTVEC:CODE:ROOT(2)
-        ORG 608
-`??MD_INTTM0EQ0??INTVEC 608`:
-        JR MD_INTTM0EQ0
-
-        RSEG NEAR_ID:CONST:SORT:NOROOT(2)
-`?`:
-        DW 10
-
-      COMMON INTVEC:CODE:ROOT(2)
-      ORG 40H
-`??vPortYield??INTVEC 40`:
-        JR vPortYield
-
-;------------------------------------------------------------------------------
-; set microcontroller security ID
-
-      COMMON INTVEC:CODE:ROOT(2)
-      ORG 70H
-`SECUID`:
-      DB CG_SECURITY0
-      DB CG_SECURITY1
-      DB CG_SECURITY2
-      DB CG_SECURITY3
-      DB CG_SECURITY4
-      DB CG_SECURITY5
-      DB CG_SECURITY6
-      DB CG_SECURITY7
-      DB CG_SECURITY8
-      DB CG_SECURITY9
-
-;------------------------------------------------------------------------------
-; set microcontroller option bytes
-
-      COMMON INTVEC:CODE:ROOT(2)
-      ORG 7AH
-`OPTBYTES`:
-      DB CG_OPTION7A
-      DB CG_OPTION7B
-      DB OPT7C
-      DB OPT7D
-      DB OPT7E
-      DB OPT7F
-
-      END
\ No newline at end of file
diff --git a/FreeRTOS/Source/portable/IAR/V850ES/portasm_Hx2.s85 b/FreeRTOS/Source/portable/IAR/V850ES/portasm_Hx2.s85
deleted file mode 100755
index 35d79f9..0000000
--- a/FreeRTOS/Source/portable/IAR/V850ES/portasm_Hx2.s85
+++ /dev/null
@@ -1,350 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-; Note: Select the correct include files for the device used by the application.
-#include "FreeRTOSConfig.h"
-;------------------------------------------------------------------------------
-
-; Functions used by scheduler
-;------------------------------------------------------------------------------
-    EXTERN    vTaskSwitchContext
-    EXTERN    xTaskIncrementTick
-
-; Variables used by scheduler
-;------------------------------------------------------------------------------
-    EXTERN    pxCurrentTCB
-    EXTERN    usCriticalNesting
-
-; Functions implemented in this file
-;------------------------------------------------------------------------------
-    PUBLIC    vPortYield
-    PUBLIC    vPortStart
-
-; Security ID definition
-;------------------------------------------------------------------------------
-#define	CG_SECURITY0	0FFH
-#define	CG_SECURITY1	0FFH
-#define	CG_SECURITY2	0FFH
-#define	CG_SECURITY3	0FFH
-#define	CG_SECURITY4	0FFH
-#define	CG_SECURITY5	0FFH
-#define	CG_SECURITY6	0FFH
-#define	CG_SECURITY7	0FFH
-#define	CG_SECURITY8	0FFH
-#define	CG_SECURITY9	0FFH
-
-; Tick ISR Prototype
-;------------------------------------------------------------------------------
-        PUBWEAK `??MD_INTTM0EQ0??INTVEC 544`
-        PUBLIC MD_INTTM0EQ0
-
-MD_INTTM0EQ0        SYMBOL "MD_INTTM0EQ0"
-`??MD_INTTM0EQ0??INTVEC 544` SYMBOL "??INTVEC 544", MD_INTTM0EQ0
-
-;------------------------------------------------------------------------------
-;   portSAVE_CONTEXT MACRO
-;   Saves the context of the remaining general purpose registers
-;   and the usCriticalNesting Value of the active Task onto the task stack
-;   saves stack pointer to the TCB
-;------------------------------------------------------------------------------
-portSAVE_CONTEXT MACRO
-#if configDATA_MODE == 1                                        ; Using the Tiny data model
-    prepare {r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30},76,sp ; save general purpose registers
-    sst.w   r19,72[ep]
-    sst.w   r18,68[ep]
-    sst.w   r17,64[ep]
-    sst.w   r16,60[ep]
-    sst.w   r15,56[ep]
-    sst.w   r14,52[ep]
-    sst.w   r13,48[ep]
-    sst.w   r12,44[ep]
-    sst.w   r11,40[ep]
-    sst.w   r10,36[ep]
-    sst.w   r9,32[ep]
-    sst.w   r8,28[ep]
-    sst.w   r7,24[ep]
-    sst.w   r6,20[ep]
-    sst.w   r5,16[ep]
-    sst.w   r4,12[ep]
-#else                                                           ; Using the Small/Large data model
-    prepare {r20,r21,r22,r23,r24,r26,r27,r28,r29,r30},72,sp     ; save general purpose registers
-    sst.w   r19,68[ep]
-    sst.w   r18,64[ep]
-    sst.w   r17,60[ep]
-    sst.w   r16,56[ep]
-    sst.w   r15,52[ep]
-    sst.w   r14,48[ep]
-    sst.w   r13,44[ep]
-    sst.w   r12,40[ep]
-    sst.w   r11,36[ep]
-    sst.w   r10,32[ep]
-    sst.w   r9,28[ep]
-    sst.w   r8,24[ep]
-    sst.w   r7,20[ep]
-    sst.w   r6,16[ep]
-    sst.w   r5,12[ep]
-#endif /* configDATA_MODE */
-    sst.w   r2,8[ep]
-    sst.w   r1,4[ep]
-    MOVHI   hi1(usCriticalNesting),r0,r1                        ; save usCriticalNesting value to stack
-    ld.w    lw1(usCriticalNesting)[r1],r2
-    sst.w   r2,0[ep]
-    MOVHI   hi1(pxCurrentTCB),r0,r1                             ; save SP to top of current TCB
-    ld.w    lw1(pxCurrentTCB)[r1],r2
-    st.w    sp,0[r2]
-    ENDM
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   portRESTORE_CONTEXT MACRO
-;   Gets stack pointer from the current TCB
-;   Restores the context of the usCriticalNesting value and general purpose
-;   registers of the selected task from the task stack
-;------------------------------------------------------------------------------
-portRESTORE_CONTEXT MACRO
-    MOVHI   hi1(pxCurrentTCB),r0,r1         ; get Stackpointer address
-    ld.w    lw1(pxCurrentTCB)[r1],sp
-    MOV     sp,r1
-    ld.w    0[r1],sp                        ; load stackpointer
-    MOV     sp,ep                           ; set stack pointer to element pointer
-    sld.w   0[ep],r1                        ; load usCriticalNesting value from stack
-    MOVHI   hi1(usCriticalNesting),r0,r2
-    st.w    r1,lw1(usCriticalNesting)[r2]
-    sld.w   4[ep],r1                        ; restore general purpose registers
-    sld.w   8[ep],r2
-#if configDATA_MODE == 1                    ; Using Tiny data model
-    sld.w   12[ep],r4
-    sld.w   16[ep],r5
-    sld.w   20[ep],r6
-    sld.w   24[ep],r7
-    sld.w   28[ep],r8
-    sld.w   32[ep],r9
-    sld.w   36[ep],r10
-    sld.w   40[ep],r11
-    sld.w   44[ep],r12
-    sld.w   48[ep],r13
-    sld.w   52[ep],r14
-    sld.w   56[ep],r15
-    sld.w   60[ep],r16
-    sld.w   64[ep],r17
-    sld.w   68[ep],r18
-    sld.w   72[ep],r19
-    dispose 76,{r20,r21,r22,r23,r24,r25,r26,r27,r28,r29,r30}
-#else                                       ; Using Small/Large data model
-    sld.w   12[ep],r5
-    sld.w   16[ep],r6
-    sld.w   20[ep],r7
-    sld.w   24[ep],r8
-    sld.w   28[ep],r9
-    sld.w   32[ep],r10
-    sld.w   36[ep],r11
-    sld.w   40[ep],r12
-    sld.w   44[ep],r13
-    sld.w   48[ep],r14
-    sld.w   52[ep],r15
-    sld.w   56[ep],r16
-    sld.w   60[ep],r17
-    sld.w   64[ep],r18
-    sld.w   68[ep],r19
-    dispose 72,{r20,r21,r22,r23,r24,r26,r27,r28,r29,r30}
-#endif /* configDATA_MODE */
-    ENDM
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   Restore the context of the first task that is going to run.
-;
-;   Input:  NONE
-;
-;   Call:   CALL    vPortStart
-;
-;   Output: NONE
-;------------------------------------------------------------------------------
-    RSEG CODE:CODE
-vPortStart:
-    portRESTORE_CONTEXT	                    ; Restore the context of whichever task the ...
-    ld.w    0[sp],lp
-    ldsr    lp,5                            ; restore PSW
-    DI
-    ld.w    4[sp],lp                        ; restore LP
-    ld.w    8[sp],lp                        ; restore LP
-    ADD     0x0C,sp                         ; set SP to right position
-    EI
-    jmp     [lp]
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   Port Yield function to check for a Task switch in the cooperative and
-;   preemptive mode
-;
-;   Input:  NONE
-;
-;   Call:   CALL    vPortYield
-;
-;   Output: NONE
-;------------------------------------------------------------------------------
-
-	RSEG CODE:CODE
-vPortYield:
-
-    add     -0x0C,sp                          ; prepare stack to save necessary values
-    st.w    lp,8[sp]                        ; store LP to stack
-    stsr    0,r31
-    st.w    lp,4[sp]                        ; store EIPC to stack
-    stsr    1,lp
-    st.w    lp,0[sp]                        ; store EIPSW to stack
-    portSAVE_CONTEXT		            ; Save the context of the current task.
-    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
-    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
-                		            ; ... scheduler decided should run.
-	ld.w    0[sp],lp                        ; restore EIPSW from stack
-    ldsr    lp,1
-    ld.w    4[sp],lp                        ; restore EIPC from stack
-    ldsr    lp,0
-    ld.w    8[sp],lp                        ; restore LP from stack
-    add     0x0C,sp                         ; set SP to right position
-
-    RETI
-
-;------------------------------------------------------------------------------
-
-;------------------------------------------------------------------------------
-;   Perform the necessary steps of the Tick Count Increment and Task Switch
-;   depending on the chosen kernel configuration
-;
-;   Input:  NONE
-;
-;   Call:   ISR
-;
-;   Output: NONE
-;------------------------------------------------------------------------------
-#if configUSE_PREEMPTION == 1               ; use preemptive kernel mode
-
-MD_INTTM0EQ0:
-
-    add     -0x0C,sp                          ; prepare stack to save necessary values
-    st.w    lp,8[sp]                        ; store LP to stack
-    stsr    0,r31
-    st.w    lp,4[sp]                        ; store EIPC to stack
-    stsr    1,lp
-    st.w    lp,0[sp]                        ; store EIPSW to stack
-    portSAVE_CONTEXT		            ; Save the context of the current task.
-    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
-    jarl    vTaskSwitchContext,lp           ; Call the scheduler.
-    portRESTORE_CONTEXT		            ; Restore the context of whichever task the ...
-                		            ; ... scheduler decided should run.
-    ld.w    0[sp],lp                        ; restore EIPSW from stack
-    ldsr    lp,1
-    ld.w    4[sp],lp                        ; restore EIPC from stack
-    ldsr    lp,0
-    ld.w    8[sp],lp                        ; restore LP from stack
-    add     0x0C,sp                         ; set SP to right position
-
-    RETI
-;------------------------------------------------------------------------------
-#else                                       ; use cooperative kernel mode
-
-MD_INTTM0EQ0:
-    prepare {lp,ep},8,sp
-    sst.w   r1,4[ep]
-    sst.w   r5,0[ep]
-    jarl    xTaskIncrementTick,lp           ; Call the timer tick function.
-    sld.w   0[ep],r5
-    sld.w   4[ep],r1
-    dispose 8,{lp,ep}
-    RETI
-#endif /* configUSE_PREEMPTION */
-
-;------------------------------------------------------------------------------
-        COMMON INTVEC:CODE:ROOT(2)
-        ORG 544
-`??MD_INTTM0EQ0??INTVEC 544`:
-        JR MD_INTTM0EQ0
-
-        RSEG NEAR_ID:CONST:SORT:NOROOT(2)
-`?`:
-        DW 10
-
-      COMMON INTVEC:CODE:ROOT(2)
-      ORG 40H
-`??vPortYield??INTVEC 40`:
-        JR vPortYield
-
-;------------------------------------------------------------------------------
-; set microcontroller security ID
-
-      COMMON INTVEC:CODE:ROOT(2)
-      ORG 70H
-`SECUID`:
-      DB CG_SECURITY0
-      DB CG_SECURITY1
-      DB CG_SECURITY2
-      DB CG_SECURITY3
-      DB CG_SECURITY4
-      DB CG_SECURITY5
-      DB CG_SECURITY6
-      DB CG_SECURITY7
-      DB CG_SECURITY8
-      DB CG_SECURITY9
-
-
-; set microcontroller Option bytes
-
-      COMMON INTVEC:CODE:ROOT(2)
-      ORG 122
-`OPTBYTES`:
-      DB 0xFD
-      DB 0xFF
-      DB 0xFF
-      DB 0xFF
-      DB 0xFF
-      DB 0xFF
-
-#if configOCD_USAGE == 1
-
-      COMMON   INTVEC:CODE:ROOT(4)
-      ORG      0x230
-      PUBLIC ROM_INT2
-ROM_INT2:
-      DB 0xff, 0xff, 0xff, 0xff
-      DB 0xff, 0xff, 0xff, 0xff
-      DB 0xff, 0xff, 0xff, 0xff
-      DB 0xff, 0xff, 0xff, 0xff
-
-
-      COMMON   INTVEC:CODE:ROOT(4)
-      ORG      0x60
-      PUBLIC   ROM_INT
-ROM_INT:
-      DB 0xff, 0xff, 0xff, 0xff
-      DB 0xff, 0xff, 0xff, 0xff
-      DB 0xff, 0xff, 0xff, 0xff
-      DB 0xff, 0xff, 0xff, 0xff
-
-#endif /* configOCD_USAGE */
-
-      END
-
diff --git a/FreeRTOS/Source/portable/IAR/V850ES/portmacro.h b/FreeRTOS/Source/portable/IAR/V850ES/portmacro.h
deleted file mode 100755
index 4ca1f7d..0000000
--- a/FreeRTOS/Source/portable/IAR/V850ES/portmacro.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  unsigned int
-#define portBASE_TYPE   int
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if (configUSE_16_BIT_TICKS==1)
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS() __asm ( "DI" )
-#define portENABLE_INTERRUPTS()	 __asm ( "EI" )
-/*-----------------------------------------------------------*/
-
-/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING		( ( UBaseType_t ) 0 )
-
-#define portENTER_CRITICAL()														\
-{																					\
-extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting;						\
-																					\
-	portDISABLE_INTERRUPTS();														\
-																					\
-	/* Now interrupts are disabled ulCriticalNesting can be accessed */				\
-	/* directly.  Increment ulCriticalNesting to keep a count of how many */		\
-	/* times portENTER_CRITICAL() has been called. */								\
-	usCriticalNesting++;															\
-}
-
-#define portEXIT_CRITICAL()															\
-{																					\
-extern volatile /*uint16_t*/ portSTACK_TYPE usCriticalNesting;						\
-																					\
-	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )						\
-	{																				\
-		/* Decrement the nesting count as we are leaving a critical section. */		\
-		usCriticalNesting--;														\
-																					\
-		/* If the nesting level has reached zero then interrupts should be */		\
-		/* re-enabled. */															\
-		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )					\
-		{																			\
-			portENABLE_INTERRUPTS();												\
-		}																			\
-	}																				\
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-extern void vPortYield( void );
-extern void vPortStart( void );
-extern void portSAVE_CONTEXT( void );
-extern void portRESTORE_CONTEXT( void );
-#define portYIELD()	__asm ( "trap 0" )
-#define portNOP()	__asm ( "NOP" )
-extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken ) if( xHigherPriorityTaskWoken ) vTaskSwitchContext()
-
-/*-----------------------------------------------------------*/
-
-/* Hardwware specifics. */
-#define portBYTE_ALIGNMENT	4
-#define portSTACK_GROWTH	( -1 )
-#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/Keil/See-also-the-RVDS-directory.txt b/FreeRTOS/Source/portable/Keil/See-also-the-RVDS-directory.txt
deleted file mode 100755
index bd7fab7..0000000
--- a/FreeRTOS/Source/portable/Keil/See-also-the-RVDS-directory.txt
+++ /dev/null
@@ -1 +0,0 @@
-Nothing to see here.
\ No newline at end of file
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC18F/port.c b/FreeRTOS/Source/portable/MPLAB/PIC18F/port.c
deleted file mode 100755
index b2870bb..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC18F/port.c
+++ /dev/null
@@ -1,615 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* 
-Changes between V1.2.4 and V1.2.5
-
-	+ Introduced portGLOBAL_INTERRUPT_FLAG definition to test the global 
-	  interrupt flag setting.  Using the two bits defined within
-	  portINITAL_INTERRUPT_STATE was causing the w register to get clobbered
-	  before the test was performed.
-
-Changes from V1.2.5
-
-	+ Set the interrupt vector address to 0x08.  Previously it was at the
-	  incorrect address for compatibility mode of 0x18.
-
-Changes from V2.1.1
-
-	+ PCLATU and PCLATH are now saved as part of the context.  This allows
-	  function pointers to be used within tasks.  Thanks to Javier Espeche
-	  for the enhancement. 
-
-Changes from V2.3.1
-
-	+ TABLAT is now saved as part of the task context.
-	
-Changes from V3.2.0
-
-	+ TBLPTRU is now initialised to zero as the MPLAB compiler expects this
-	  value and does not write to the register.
-*/
-
-/* Scheduler include files. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* MPLAB library include file. */
-#include "timers.h"
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PIC port.
- *----------------------------------------------------------*/
-
-/* Hardware setup for tick. */
-#define portTIMER_FOSC_SCALE			( ( uint32_t ) 4 )
-
-/* Initial interrupt enable state for newly created tasks.  This value is
-copied into INTCON when a task switches in for the first time. */
-#define portINITAL_INTERRUPT_STATE			0xc0
-
-/* Just the bit within INTCON for the global interrupt flag. */
-#define portGLOBAL_INTERRUPT_FLAG			0x80
-
-/* Constant used for context switch macro when we require the interrupt 
-enable state to be unchanged when the interrupted task is switched back in. */
-#define portINTERRUPTS_UNCHANGED			0x00
-
-/* Some memory areas get saved as part of the task context.  These memory
-area's get used by the compiler for temporary storage, especially when 
-performing mathematical operations, or when using 32bit data types.  This
-constant defines the size of memory area which must be saved. */
-#define portCOMPILER_MANAGED_MEMORY_SIZE	( ( uint8_t ) 0x13 )
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/* IO port constants. */
-#define portBIT_SET		( ( uint8_t ) 1 )
-#define portBIT_CLEAR	( ( uint8_t ) 0 )
-
-/*
- * The serial port ISR's are defined in serial.c, but are called from portable
- * as they use the same vector as the tick ISR.
- */
-void vSerialTxISR( void );
-void vSerialRxISR( void );
-
-/*
- * Perform hardware setup to enable ticks.
- */
-static void prvSetupTimerInterrupt( void );
-
-/* 
- * ISR to maintain the tick, and perform tick context switches if the
- * preemptive scheduler is being used.
- */
-static void prvTickISR( void );
-
-/*
- * ISR placed on the low priority vector.  This calls the appropriate ISR for
- * the actual interrupt.
- */
-static void prvLowInterrupt( void );
-
-/* 
- * Macro that pushes all the registers that make up the context of a task onto
- * the stack, then saves the new top of stack into the TCB.
- * 
- * If this is called from an ISR then the interrupt enable bits must have been 
- * set for the ISR to ever get called.  Therefore we want to save the INTCON
- * register with the enable bits forced to be set - and ucForcedInterruptFlags 
- * must contain these bit settings.  This means the interrupts will again be
- * enabled when the interrupted task is switched back in.
- *
- * If this is called from a manual context switch (i.e. from a call to yield),
- * then we want to save the INTCON so it is restored with its current state,
- * and ucForcedInterruptFlags must be 0.  This allows a yield from within
- * a critical section.
- *
- * The compiler uses some locations at the bottom of the memory for temporary
- * storage during math and other computations.  This is especially true if
- * 32bit data types are utilised (as they are by the scheduler).  The .tmpdata
- * and MATH_DATA sections have to be stored in there entirety as part of a task
- * context.  This macro stores from data address 0x00 to 
- * portCOMPILER_MANAGED_MEMORY_SIZE.  This is sufficient for the demo 
- * applications but you should check the map file for your project to ensure 
- * this is sufficient for your needs.  It is not clear whether this size is 
- * fixed for all compilations or has the potential to be program specific.
- */
-#define	portSAVE_CONTEXT( ucForcedInterruptFlags )								\
-{																				\
-	_asm																		\
-		/* Save the status and WREG registers first, as these will get modified	\
-		by the operations below. */												\
-		MOVFF	WREG, PREINC1													\
-		MOVFF   STATUS, PREINC1													\
-		/* Save the INTCON register with the appropriate bits forced if			\
-		necessary - as described above. */										\
-		MOVFF	INTCON, WREG													\
-		IORLW	ucForcedInterruptFlags											\
-		MOVFF	WREG, PREINC1													\
-	_endasm																		\
-																				\
-	portDISABLE_INTERRUPTS();													\
-																				\
-	_asm																		\
-		/* Store the necessary registers to the stack. */						\
-		MOVFF	BSR, PREINC1													\
-		MOVFF	FSR2L, PREINC1													\
-		MOVFF	FSR2H, PREINC1													\
-		MOVFF	FSR0L, PREINC1													\
-		MOVFF	FSR0H, PREINC1													\
-		MOVFF	TABLAT, PREINC1													\
-		MOVFF	TBLPTRU, PREINC1												\
-		MOVFF	TBLPTRH, PREINC1												\
-		MOVFF	TBLPTRL, PREINC1												\
-		MOVFF	PRODH, PREINC1													\
-		MOVFF	PRODL, PREINC1													\
-		MOVFF	PCLATU, PREINC1													\
-		MOVFF	PCLATH, PREINC1													\
-		/* Store the .tempdata and MATH_DATA areas as described above. */		\
-		CLRF	FSR0L, 0														\
-		CLRF	FSR0H, 0														\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	POSTINC0, PREINC1												\
-		MOVFF	INDF0, PREINC1													\
-		MOVFF	FSR0L, PREINC1													\
-		MOVFF	FSR0H, PREINC1													\
-		/* Store the hardware stack pointer in a temp register before we		\
-		modify it. */															\
-		MOVFF	STKPTR, FSR0L													\
-	_endasm																		\
-																				\
-		/* Store each address from the hardware stack. */						\
-		while( STKPTR > ( uint8_t ) 0 )								\
-		{																		\
-			_asm																\
-				MOVFF	TOSL, PREINC1											\
-				MOVFF	TOSH, PREINC1											\
-				MOVFF	TOSU, PREINC1											\
-				POP																\
-			_endasm																\
-		}																		\
-																				\
-	_asm																		\
-		/* Store the number of addresses on the hardware stack (from the		\
-		temporary register). */													\
-		MOVFF	FSR0L, PREINC1													\
-		MOVF	PREINC1, 1, 0													\
-	_endasm																		\
-																				\
-	/* Save the new top of the software stack in the TCB. */					\
-	_asm																		\
-		MOVFF	pxCurrentTCB, FSR0L												\
-		MOVFF	pxCurrentTCB + 1, FSR0H											\
-		MOVFF	FSR1L, POSTINC0													\
-		MOVFF	FSR1H, POSTINC0													\
-	_endasm																		\
-}
-/*-----------------------------------------------------------*/
-
-/*
- * This is the reverse of portSAVE_CONTEXT.  See portSAVE_CONTEXT for more
- * details.
- */
-#define portRESTORE_CONTEXT()													\
-{																				\
-	_asm																		\
-		/* Set FSR0 to point to pxCurrentTCB->pxTopOfStack. */					\
-		MOVFF	pxCurrentTCB, FSR0L												\
-		MOVFF	pxCurrentTCB + 1, FSR0H											\
-																				\
-		/* De-reference FSR0 to set the address it holds into FSR1.				\
-		(i.e. *( pxCurrentTCB->pxTopOfStack ) ). */								\
-		MOVFF	POSTINC0, FSR1L													\
-		MOVFF	POSTINC0, FSR1H													\
-																				\
-		/* How many return addresses are there on the hardware stack?  Discard	\
-		the first byte as we are pointing to the next free space. */			\
-		MOVFF	POSTDEC1, FSR0L													\
-		MOVFF	POSTDEC1, FSR0L													\
-	_endasm																		\
-																				\
-	/* Fill the hardware stack from our software stack. */						\
-	STKPTR = 0;																	\
-																				\
-	while( STKPTR < FSR0L )														\
-	{																			\
-		_asm																	\
-			PUSH																\
-			MOVF	POSTDEC1, 0, 0												\
-			MOVWF	TOSU, 0														\
-			MOVF	POSTDEC1, 0, 0												\
-			MOVWF	TOSH, 0														\
-			MOVF	POSTDEC1, 0, 0												\
-			MOVWF	TOSL, 0														\
-		_endasm																	\
-	}																			\
-																				\
-	_asm																		\
-		/* Restore the .tmpdata and MATH_DATA memory. */						\
-		MOVFF	POSTDEC1, FSR0H													\
-		MOVFF	POSTDEC1, FSR0L													\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, POSTDEC0												\
-		MOVFF	POSTDEC1, INDF0													\
-		/* Restore the other registers forming the tasks context. */			\
-		MOVFF	POSTDEC1, PCLATH												\
-		MOVFF	POSTDEC1, PCLATU												\
-		MOVFF	POSTDEC1, PRODL													\
-		MOVFF	POSTDEC1, PRODH													\
-		MOVFF	POSTDEC1, TBLPTRL												\
-		MOVFF	POSTDEC1, TBLPTRH												\
-		MOVFF	POSTDEC1, TBLPTRU												\
-		MOVFF	POSTDEC1, TABLAT												\
-		MOVFF	POSTDEC1, FSR0H													\
-		MOVFF	POSTDEC1, FSR0L													\
-		MOVFF	POSTDEC1, FSR2H													\
-		MOVFF	POSTDEC1, FSR2L													\
-		MOVFF	POSTDEC1, BSR													\
-		/* The next byte is the INTCON register.  Read this into WREG as some	\
-		manipulation is required. */											\
-		MOVFF	POSTDEC1, WREG													\
-	_endasm																		\
-																				\
-	/* From the INTCON register, only the interrupt enable bits form part		\
-	of the tasks context.  It is perfectly legitimate for another task to		\
-	have modified any other bits.  We therefore only restore the top two bits.	\
-	*/																			\
-	if( WREG & portGLOBAL_INTERRUPT_FLAG )										\
-	{																			\
-		_asm 																	\
-			MOVFF	POSTDEC1, STATUS											\
-			MOVFF	POSTDEC1, WREG												\
-			/* Return enabling interrupts. */									\
-			RETFIE	0															\
-		_endasm																	\
-	}																			\
-	else																		\
-	{																			\
-		_asm 																	\
-			MOVFF	POSTDEC1, STATUS											\
-			MOVFF	POSTDEC1, WREG												\
-			/* Return without effecting interrupts.  The context may have		\
-			been saved from a critical region. */								\
-			RETURN	0															\
-		_endasm																	\
-	}																			\
-}
-/*-----------------------------------------------------------*/
-
-/* 
- * See header file for description. 
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint32_t ulAddress;
-uint8_t ucBlock;
-
-	/* Place a few bytes of known values on the bottom of the stack. 
-	This is just useful for debugging. */
-
-	*pxTopOfStack = 0x11;
-	pxTopOfStack++;
-	*pxTopOfStack = 0x22;
-	pxTopOfStack++;
-	*pxTopOfStack = 0x33;
-	pxTopOfStack++;
-
-
-	/* Simulate how the stack would look after a call to vPortYield() generated
-	by the compiler. 
-
-	First store the function parameters.  This is where the task will expect to
-	find them when it starts running. */
-	ulAddress = ( uint32_t ) pvParameters;
-	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
-	pxTopOfStack++;
-
-	ulAddress >>= 8;
-	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
-	pxTopOfStack++;
-
-	/* Next we just leave a space.  When a context is saved the stack pointer
-	is incremented before it is used so as not to corrupt whatever the stack
-	pointer is actually pointing to.  This is especially necessary during 
-	function epilogue code generated by the compiler. */
-	*pxTopOfStack = 0x44;
-	pxTopOfStack++;
-
-	/* Next are all the registers that form part of the task context. */
-	
-	*pxTopOfStack = ( StackType_t ) 0x66; /* WREG. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0xcc; /* Status. */
-	pxTopOfStack++;
-
-	/* INTCON is saved with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) portINITAL_INTERRUPT_STATE; /* INTCON */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0x11; /* BSR. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0x22; /* FSR2L. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0x33; /* FSR2H. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0x44; /* FSR0L. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0x55; /* FSR0H. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0x66; /* TABLAT. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0x00; /* TBLPTRU. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0x88; /* TBLPTRUH. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0x99; /* TBLPTRUL. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0xaa; /* PRODH. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0xbb; /* PRODL. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0x00; /* PCLATU. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0x00; /* PCLATH. */
-	pxTopOfStack++;
-
-	/* Next the .tmpdata and MATH_DATA sections. */
-	for( ucBlock = 0; ucBlock <= portCOMPILER_MANAGED_MEMORY_SIZE; ucBlock++ )
-	{
-		*pxTopOfStack = ( StackType_t ) ucBlock;
-		*pxTopOfStack++;
-	}
-
-	/* Store the top of the global data section. */
-	*pxTopOfStack = ( StackType_t ) portCOMPILER_MANAGED_MEMORY_SIZE; /* Low. */
-	pxTopOfStack++;
-
-	*pxTopOfStack = ( StackType_t ) 0x00; /* High. */
-	pxTopOfStack++;
-
-	/* The only function return address so far is the address of the 
-	task. */
-	ulAddress = ( uint32_t ) pxCode;
-
-	/* TOS low. */
-	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
-	pxTopOfStack++;
-	ulAddress >>= 8;
-
-	/* TOS high. */
-	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
-	pxTopOfStack++;
-	ulAddress >>= 8;
-
-	/* TOS even higher. */
-	*pxTopOfStack = ( StackType_t ) ( ulAddress & ( uint32_t ) 0x00ff );
-	pxTopOfStack++;
-
-	/* Store the number of return addresses on the hardware stack - so far only
-	the address of the task entry point. */
-	*pxTopOfStack = ( StackType_t ) 1;
-	pxTopOfStack++;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Setup a timer for the tick ISR is using the preemptive scheduler. */
-	prvSetupTimerInterrupt(); 
-
-	/* Restore the context of the first task to run. */
-	portRESTORE_CONTEXT();
-
-	/* Should not get here.  Use the function name to stop compiler warnings. */
-	( void ) prvLowInterrupt;
-	( void ) prvTickISR;
-
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the scheduler for the PIC port will get stopped
-	once running.  If required disable the tick interrupt here, then return 
-	to xPortStartScheduler(). */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch.  This is similar to the tick context switch,
- * but does not increment the tick count.  It must be identical to the
- * tick context switch in how it stores the stack of a task.
- */
-void vPortYield( void )
-{
-	/* This can get called with interrupts either enabled or disabled.  We
-	will save the INTCON register with the interrupt enable bits unmodified. */
-	portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
-
-	/* Switch to the highest priority task that is ready to run. */
-	vTaskSwitchContext();
-
-	/* Start executing the task we have just switched to. */
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Vector for ISR.  Nothing here must alter any registers!
- */
-#pragma code high_vector=0x08
-static void prvLowInterrupt( void )
-{
-	/* Was the interrupt the tick? */
-	if( PIR1bits.CCP1IF )
-	{		
-		_asm
-			goto prvTickISR
-		_endasm
-	}
-
-	/* Was the interrupt a byte being received? */
-	if( PIR1bits.RCIF )
-	{
-		_asm
-			goto vSerialRxISR
-		_endasm
-	}
-
-	/* Was the interrupt the Tx register becoming empty? */
-	if( PIR1bits.TXIF )
-	{
-		if( PIE1bits.TXIE )
-		{
-			_asm
-				goto vSerialTxISR
-			_endasm
-		}
-	}
-}
-#pragma code
-
-/*-----------------------------------------------------------*/
-
-/*
- * ISR for the tick.
- * This increments the tick count and, if using the preemptive scheduler, 
- * performs a context switch.  This must be identical to the manual 
- * context switch in how it stores the context of a task. 
- */
-static void prvTickISR( void )
-{
-	/* Interrupts must have been enabled for the ISR to fire, so we have to 
-	save the context with interrupts enabled. */
-	portSAVE_CONTEXT( portGLOBAL_INTERRUPT_FLAG );
-	PIR1bits.CCP1IF = 0;
-
-	/* Maintain the tick count. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		/* Switch to the highest priority task that is ready to run. */
-		vTaskSwitchContext();
-	}
-
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup a timer for a regular tick.
- */
-static void prvSetupTimerInterrupt( void )
-{
-const uint32_t ulConstCompareValue = ( ( configCPU_CLOCK_HZ / portTIMER_FOSC_SCALE ) / configTICK_RATE_HZ );
-uint32_t ulCompareValue;
-uint8_t ucByte;
-
-	/* Interrupts are disabled when this function is called.
-
-	Setup CCP1 to provide the tick interrupt using a compare match on timer
-	1.
-
-	Clear the time count then setup timer. */
-	TMR1H = ( uint8_t ) 0x00;
-	TMR1L = ( uint8_t ) 0x00;
-
-	/* Set the compare match value. */
-	ulCompareValue = ulConstCompareValue;
-	CCPR1L = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );
-	ulCompareValue >>= ( uint32_t ) 8;
-	CCPR1H = ( uint8_t ) ( ulCompareValue & ( uint32_t ) 0xff );	
-
-	CCP1CONbits.CCP1M0 = portBIT_SET;	/*< Compare match mode. */
-	CCP1CONbits.CCP1M1 = portBIT_SET;	/*< Compare match mode. */
-	CCP1CONbits.CCP1M2 = portBIT_CLEAR;	/*< Compare match mode. */
-	CCP1CONbits.CCP1M3 = portBIT_SET;	/*< Compare match mode. */
-	PIE1bits.CCP1IE = portBIT_SET;		/*< Interrupt enable. */
-
-	/* We are only going to use the global interrupt bit, so set the peripheral
-	bit to true. */
-	INTCONbits.GIEL = portBIT_SET;
-
-	/* Provided library function for setting up the timer that will produce the
-	tick. */
-	OpenTimer1( T1_16BIT_RW & T1_SOURCE_INT & T1_PS_1_1 & T1_CCP1_T3_CCP2 );
-}
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC18F/portmacro.h b/FreeRTOS/Source/portable/MPLAB/PIC18F/portmacro.h
deleted file mode 100755
index 4061c94..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC18F/portmacro.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		int
-#define portSTACK_TYPE	uint8_t
-#define portBASE_TYPE	char
-
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			1
-#define portGLOBAL_INT_ENABLE_BIT	0x80
-#define portSTACK_GROWTH			1
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-#define portDISABLE_INTERRUPTS()	INTCONbits.GIEH = 0;
-#define portENABLE_INTERRUPTS()		INTCONbits.GIEH = 1;
-
-/* Push the INTCON register onto the stack, then disable interrupts. */
-#define portENTER_CRITICAL()		POSTINC1 = INTCON;				\
-									INTCONbits.GIEH = 0;
-
-/* Retrieve the INTCON register from the stack, and enable interrupts
-if they were saved as being enabled.  Don't modify any other bits
-within the INTCON register as these may have lagitimately have been
-modified within the critical region. */
-#define portEXIT_CRITICAL()			_asm									\
-										MOVF	POSTDEC1, 1, 0				\
-									_endasm									\
-									if( INDF1 & portGLOBAL_INT_ENABLE_BIT )	\
-									{										\
-										portENABLE_INTERRUPTS();			\
-									}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-extern void vPortYield( void );
-#define portYIELD()				vPortYield()
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Required by the kernel aware debugger. */
-#ifdef __DEBUG
-	#define portREMOVE_STATIC_QUALIFIER
-#endif
-
-
-#define portNOP()				_asm	\
-									NOP \
-								_endasm
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC18F/stdio.h b/FreeRTOS/Source/portable/MPLAB/PIC18F/stdio.h
deleted file mode 100755
index e69de29..0000000
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/port.c b/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/port.c
deleted file mode 100755
index a843ee0..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/port.c
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-	Changes from V4.2.1
-
-	+ Introduced the configKERNEL_INTERRUPT_PRIORITY definition.
-*/
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PIC24 port.
- *----------------------------------------------------------*/
-
-/* Scheduler include files. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Hardware specifics. */
-#define portBIT_SET 1
-#define portTIMER_PRESCALE 8
-#define portINITIAL_SR	0
-
-/* Defined for backward compatability with project created prior to
-FreeRTOS.org V4.3.0. */
-#ifndef configKERNEL_INTERRUPT_PRIORITY
-	#define configKERNEL_INTERRUPT_PRIORITY 1
-#endif
-
-/* Use _T1Interrupt as the interrupt handler name if the application writer has
-not provided their own. */
-#ifndef configTICK_INTERRUPT_HANDLER
-	#define configTICK_INTERRUPT_HANDLER _T1Interrupt
-#endif /* configTICK_INTERRUPT_HANDLER */
-
-/* The program counter is only 23 bits. */
-#define portUNUSED_PR_BITS	0x7f
-
-/* Records the nesting depth of calls to portENTER_CRITICAL(). */
-UBaseType_t uxCriticalNesting = 0xef;
-
-#if configKERNEL_INTERRUPT_PRIORITY != 1
-	#error If configKERNEL_INTERRUPT_PRIORITY is not 1 then the #32 in the following macros needs changing to equal the portINTERRUPT_BITS value, which is ( configKERNEL_INTERRUPT_PRIORITY << 5 )
-#endif
-
-#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
-
-    #ifdef __HAS_EDS__
-		#define portRESTORE_CONTEXT()																						\
-					asm volatile(	"MOV	_pxCurrentTCB, W0		\n"	/* Restore the stack pointer for the task. */		\
-							"MOV	[W0], W15				\n"																\
-							"POP	W0						\n"	/* Restore the critical nesting counter for the task. */	\
-							"MOV	W0, _uxCriticalNesting	\n"																\
-							"POP	DSWPAG					\n"																\
-							"POP    DSRPAG					\n"																\
-							"POP	CORCON					\n"																\
-							"POP	TBLPAG					\n"																\
-							"POP	RCOUNT					\n"	/* Restore the registers from the stack. */					\
-							"POP	W14						\n"																\
-							"POP.D	W12						\n"																\
-							"POP.D	W10						\n"																\
-							"POP.D	W8						\n"																\
-							"POP.D	W6						\n"																\
-							"POP.D	W4						\n"																\
-							"POP.D	W2						\n"																\
-							"POP.D	W0						\n"																\
-							"POP	SR						  " );
-	#else /* __HAS_EDS__ */
-		#define portRESTORE_CONTEXT()																						\
-			asm volatile(	"MOV	_pxCurrentTCB, W0		\n"	/* Restore the stack pointer for the task. */				\
-							"MOV	[W0], W15				\n"																\
-							"POP	W0						\n"	/* Restore the critical nesting counter for the task. */	\
-							"MOV	W0, _uxCriticalNesting	\n"																\
-							"POP	PSVPAG					\n"																\
-							"POP	CORCON					\n"																\
-							"POP	TBLPAG					\n"																\
-							"POP	RCOUNT					\n"	/* Restore the registers from the stack. */					\
-							"POP	W14						\n"																\
-							"POP.D	W12						\n"																\
-							"POP.D	W10						\n"																\
-							"POP.D	W8						\n"																\
-							"POP.D	W6						\n"																\
-							"POP.D	W4						\n"																\
-							"POP.D	W2						\n"																\
-							"POP.D	W0						\n"																\
-							"POP	SR						  " );
-		#endif /* __HAS_EDS__ */
-#endif /* MPLAB_PIC24_PORT */
-
-#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
-
-	#define portRESTORE_CONTEXT()																						\
-		asm volatile(	"MOV	_pxCurrentTCB, W0		\n"	/* Restore the stack pointer for the task. */				\
-						"MOV	[W0], W15				\n"																\
-						"POP	W0						\n"	/* Restore the critical nesting counter for the task. */	\
-						"MOV	W0, _uxCriticalNesting	\n"																\
-						"POP	PSVPAG					\n"																\
-						"POP	CORCON					\n"																\
-						"POP	DOENDH					\n"																\
-						"POP	DOENDL					\n"																\
-						"POP	DOSTARTH				\n"																\
-						"POP	DOSTARTL				\n"																\
-						"POP	DCOUNT					\n"																\
-						"POP	ACCBU					\n"																\
-						"POP	ACCBH					\n"																\
-						"POP	ACCBL					\n"																\
-						"POP	ACCAU					\n"																\
-						"POP	ACCAH					\n"																\
-						"POP	ACCAL					\n"																\
-						"POP	TBLPAG					\n"																\
-						"POP	RCOUNT					\n"	/* Restore the registers from the stack. */					\
-						"POP	W14						\n"																\
-						"POP.D	W12						\n"																\
-						"POP.D	W10						\n"																\
-						"POP.D	W8						\n"																\
-						"POP.D	W6						\n"																\
-						"POP.D	W4						\n"																\
-						"POP.D	W2						\n"																\
-						"POP.D	W0						\n"																\
-						"POP	SR						  " );
-
-#endif /* MPLAB_DSPIC_PORT */
-
-#ifndef portRESTORE_CONTEXT
-	#error Unrecognised device selected
-
-	/* Note:  dsPIC parts with EDS are not supported as there is no easy way to
-	recover the hardware stacked copies for DOCOUNT, DOHIGH, DOLOW. */
-#endif
-
-/*
- * Setup the timer used to generate the tick interrupt.
- */
-void vApplicationSetupTickTimerInterrupt( void );
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint16_t usCode;
-UBaseType_t i;
-
-const StackType_t xInitialStack[] =
-{
-	0x1111,	/* W1 */
-	0x2222, /* W2 */
-	0x3333, /* W3 */
-	0x4444, /* W4 */
-	0x5555, /* W5 */
-	0x6666, /* W6 */
-	0x7777, /* W7 */
-	0x8888, /* W8 */
-	0x9999, /* W9 */
-	0xaaaa, /* W10 */
-	0xbbbb, /* W11 */
-	0xcccc, /* W12 */
-	0xdddd, /* W13 */
-	0xeeee, /* W14 */
-	0xcdce, /* RCOUNT */
-	0xabac, /* TBLPAG */
-
-	/* dsPIC specific registers. */
-	#ifdef MPLAB_DSPIC_PORT
-		0x0202, /* ACCAL */
-		0x0303, /* ACCAH */
-		0x0404, /* ACCAU */
-		0x0505, /* ACCBL */
-		0x0606, /* ACCBH */
-		0x0707, /* ACCBU */
-		0x0808, /* DCOUNT */
-		0x090a, /* DOSTARTL */
-		0x1010, /* DOSTARTH */
-		0x1110, /* DOENDL */
-		0x1212, /* DOENDH */
-	#endif
-};
-
-	/* Setup the stack as if a yield had occurred.
-
-	Save the low bytes of the program counter. */
-	usCode = ( uint16_t ) pxCode;
-	*pxTopOfStack = ( StackType_t ) usCode;
-	pxTopOfStack++;
-
-	/* Save the high byte of the program counter.  This will always be zero
-	here as it is passed in a 16bit pointer.  If the address is greater than
-	16 bits then the pointer will point to a jump table. */
-	*pxTopOfStack = ( StackType_t ) 0;
-	pxTopOfStack++;
-
-	/* Status register with interrupts enabled. */
-	*pxTopOfStack = portINITIAL_SR;
-	pxTopOfStack++;
-
-	/* Parameters are passed in W0. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;
-	pxTopOfStack++;
-
-	for( i = 0; i < ( sizeof( xInitialStack ) / sizeof( StackType_t ) ); i++ )
-	{
-		*pxTopOfStack = xInitialStack[ i ];
-		pxTopOfStack++;
-	}
-
-	*pxTopOfStack = CORCON;
-	pxTopOfStack++;
-
-	#if defined(__HAS_EDS__)
-		*pxTopOfStack = DSRPAG;
-		pxTopOfStack++;
-		*pxTopOfStack = DSWPAG;
-		pxTopOfStack++;
-	#else /* __HAS_EDS__ */
-		*pxTopOfStack = PSVPAG;
-		pxTopOfStack++;
-	#endif /* __HAS_EDS__ */
-
-	/* Finally the critical nesting depth. */
-	*pxTopOfStack = 0x00;
-	pxTopOfStack++;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Setup a timer for the tick ISR. */
-	vApplicationSetupTickTimerInterrupt();
-
-	/* Restore the context of the first task to run. */
-	portRESTORE_CONTEXT();
-
-	/* Simulate the end of the yield function. */
-	asm volatile ( "return" );
-
-	/* Should not reach here. */
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup a timer for a regular tick.
- */
-__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
-{
-const uint32_t ulCompareMatch = ( ( configCPU_CLOCK_HZ / portTIMER_PRESCALE ) / configTICK_RATE_HZ ) - 1;
-
-	/* Prescale of 8. */
-	T1CON = 0;
-	TMR1 = 0;
-
-	PR1 = ( uint16_t ) ulCompareMatch;
-
-	/* Setup timer 1 interrupt priority. */
-	IPC0bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
-
-	/* Clear the interrupt as a starting condition. */
-	IFS0bits.T1IF = 0;
-
-	/* Enable the interrupt. */
-	IEC0bits.T1IE = 1;
-
-	/* Setup the prescale value. */
-	T1CONbits.TCKPS0 = 1;
-	T1CONbits.TCKPS1 = 0;
-
-	/* Start the timer. */
-	T1CONbits.TON = 1;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void __attribute__((__interrupt__, auto_psv)) configTICK_INTERRUPT_HANDLER( void )
-{
-	/* Clear the timer interrupt. */
-	IFS0bits.T1IF = 0;
-
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		portYIELD();
-	}
-}
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S b/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S
deleted file mode 100755
index 7e90e27..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_PIC24.S
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#if defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ )
-
-        .global _vPortYield
-		.extern _vTaskSwitchContext
-		.extern uxCriticalNesting
-
-_vPortYield:
-
-		PUSH	SR						/* Save the SR used by the task.... */
-		PUSH	W0						/* ....then disable interrupts. */
-		MOV		#32, W0
-		MOV		W0, SR
-		PUSH	W1						/* Save registers to the stack. */
-		PUSH.D	W2
-		PUSH.D	W4
-		PUSH.D	W6
-		PUSH.D 	W8
-		PUSH.D 	W10
-		PUSH.D	W12
-		PUSH	W14
-		PUSH	RCOUNT
-		PUSH	TBLPAG
-
-		PUSH	CORCON
-		#ifdef __HAS_EDS__
-			PUSH	DSRPAG
-			PUSH	DSWPAG
-		#else
-			PUSH	PSVPAG
-		#endif /* __HAS_EDS__ */
-		MOV		_uxCriticalNesting, W0		/* Save the critical nesting counter for the task. */
-		PUSH	W0
-		MOV		_pxCurrentTCB, W0			/* Save the new top of stack into the TCB. */
-		MOV		W15, [W0]
-
-		call 	_vTaskSwitchContext
-
-		MOV		_pxCurrentTCB, W0			/* Restore the stack pointer for the task. */
-		MOV		[W0], W15
-		POP		W0							/* Restore the critical nesting counter for the task. */
-		MOV		W0, _uxCriticalNesting
-		#ifdef __HAS_EDS__
-			POP		DSWPAG
-			POP		DSRPAG
-		#else
-			POP		PSVPAG
-		#endif /* __HAS_EDS__ */
-		POP		CORCON
-		POP		TBLPAG
-		POP		RCOUNT						/* Restore the registers from the stack. */
-		POP		W14
-		POP.D	W12
-		POP.D	W10
-		POP.D	W8
-		POP.D	W6
-		POP.D	W4
-		POP.D	W2
-		POP.D	W0
-		POP		SR
-
-        return
-
-        .end
-		
-#endif /* defined( __PIC24E__ ) || defined ( __PIC24F__ ) || defined( __PIC24FK__ ) || defined( __PIC24H__ ) */
\ No newline at end of file
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S b/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S
deleted file mode 100755
index ee24ce3..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portasm_dsPIC.S
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#if defined( __dsPIC30F__ ) || defined( __dsPIC33F__ )
-
-        .global _vPortYield
-		.extern _vTaskSwitchContext
-		.extern uxCriticalNesting
-
-_vPortYield:
-
-		PUSH	SR						/* Save the SR used by the task.... */
-		PUSH	W0						/* ....then disable interrupts. */
-		MOV		#32, W0
-		MOV		W0, SR
-		PUSH	W1						/* Save registers to the stack. */
-		PUSH.D	W2
-		PUSH.D	W4
-		PUSH.D	W6
-		PUSH.D 	W8
-		PUSH.D 	W10
-		PUSH.D	W12
-		PUSH	W14
-		PUSH	RCOUNT
-		PUSH	TBLPAG
-		PUSH	ACCAL
-		PUSH	ACCAH
-		PUSH	ACCAU
-		PUSH	ACCBL
-		PUSH	ACCBH
-		PUSH	ACCBU
-		PUSH	DCOUNT
-		PUSH	DOSTARTL
-		PUSH	DOSTARTH
-		PUSH	DOENDL
-		PUSH	DOENDH
-
-
-		PUSH	CORCON
-		PUSH	PSVPAG
-		MOV		_uxCriticalNesting, W0		/* Save the critical nesting counter for the task. */
-		PUSH	W0
-		MOV		_pxCurrentTCB, W0			/* Save the new top of stack into the TCB. */
-		MOV		W15, [W0]
-
-		call 	_vTaskSwitchContext
-
-		MOV		_pxCurrentTCB, W0			/* Restore the stack pointer for the task. */
-		MOV		[W0], W15
-		POP		W0							/* Restore the critical nesting counter for the task. */
-		MOV		W0, _uxCriticalNesting
-		POP		PSVPAG
-		POP		CORCON
-		POP		DOENDH
-		POP		DOENDL
-		POP		DOSTARTH
-		POP		DOSTARTL
-		POP		DCOUNT
-		POP		ACCBU
-		POP		ACCBH
-		POP		ACCBL
-		POP		ACCAU
-		POP		ACCAH
-		POP		ACCAL
-		POP		TBLPAG
-		POP		RCOUNT						/* Restore the registers from the stack. */
-		POP		W14
-		POP.D	W12
-		POP.D	W10
-		POP.D	W8
-		POP.D	W6
-		POP.D	W4
-		POP.D	W2
-		POP.D	W0
-		POP		SR
-
-        return
-
-        .end
-
-#endif /* defined( __dsPIC30F__ ) || defined( __dsPIC33F__ ) */
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h b/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h
deleted file mode 100755
index 233053d..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC24_dsPIC/portmacro.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint16_t
-#define portBASE_TYPE	short
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			2
-#define portSTACK_GROWTH			1
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-#define portDISABLE_INTERRUPTS()	SET_CPU_IPL( configKERNEL_INTERRUPT_PRIORITY ); __asm volatile ( "NOP" )
-#define portENABLE_INTERRUPTS()		SET_CPU_IPL( 0 )
-
-/* Note that exiting a critical sectino will set the IPL bits to 0, nomatter
-what their value was prior to entering the critical section. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-extern void vPortYield( void );
-#define portYIELD()				asm volatile ( "CALL _vPortYield			\n"		\
-												"NOP					  " );
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Required by the kernel aware debugger. */
-#ifdef __DEBUG
-	#define portREMOVE_STATIC_QUALIFIER
-#endif
-
-#define portNOP()				asm volatile ( "NOP" )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h b/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
deleted file mode 100755
index 58d40b8..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/ISR_Support.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include "FreeRTOSConfig.h"
-
-#define portCONTEXT_SIZE 132
-#define portEPC_STACK_LOCATION 124
-#define portSTATUS_STACK_LOCATION 128
-
-#ifdef __LANGUAGE_ASSEMBLY__
-
-/******************************************************************/
-.macro	portSAVE_CONTEXT
-
-	/* Make room for the context. First save the current status so it can be
-	manipulated, and the cause and EPC registers so their original values are
-	captured. */
-	mfc0	k0, _CP0_CAUSE
-	addiu	sp, sp, -portCONTEXT_SIZE
-	mfc0	k1, _CP0_STATUS
-
-	/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
-	maintain the values of these registers across the ISR. */
-	sw		s6, 44(sp)
-	sw		s5, 40(sp)
-	sw		k1, portSTATUS_STACK_LOCATION(sp)
-
-	/* Prepare to enable interrupts above the current priority.
-	k0 = k0 >> 10. Moves RIPL[17:10] to [7:0] */
-	srl		k0, k0, 0xa
-
-	/* Insert bit field. 7 bits k0[6:0] to k1[16:10] */
-	ins		k1, k0, 10, 7
-
-	/* Sets CP0.Status.IPL = CP0.Cause.RIPL
-	Copy the MSB of the IPL, but it would be an error if it was set anyway. */
-	srl		k0, k0, 0x7
-
-	/* MSB of IPL is bit[18] of CP0.Status */
-	ins		k1, k0, 18, 1
-
-	/* CP0.Status[5:1] = 0 b[5]=Rsvd, b[4]=UM,
-	   b[3]=Rsvd, b[2]=ERL, b[1]=EXL
-	   Setting EXL=0 allows higher priority interrupts
-	   to preempt this handler */
-	ins		k1, zero, 1, 4
-
-
-	/* s5 is used as the frame pointer. */
-	add		s5, zero, sp
-
-	/* Check the nesting count value. */
-	la		k0, uxInterruptNesting
-	lw		s6, (k0)
-
-	/* If the nesting count is 0 then swap to the the system stack, otherwise
-	the system stack is already being used. */
-	bne		s6, zero, 1f
-	nop
-
-	/* Swap to the system stack. */
-	la		sp, xISRStackTop
-	lw		sp, (sp)
-
-	/* Increment and save the nesting count. */
-1:  addiu   s6, s6, 1
-	sw		s6, 0(k0)
-
-	/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
-	mfc0	s6, _CP0_EPC
-
-	/* Re-enable interrupts. */
-	mtc0	k1, _CP0_STATUS
-
-	/* Save the context into the space just created.  s6 is saved again
-	here as it now contains the EPC value.  No other s registers need be
-	saved. */
-	sw		ra, 120(s5) /* Return address (RA=R31) */
-	sw		s8, 116(s5) /* Frame Pointer (FP=R30) */
-	sw		t9, 112(s5)
-	sw		t8, 108(s5)
-	sw		t7, 104(s5)
-	sw		t6, 100(s5)
-	sw		t5, 96(s5)
-	sw		t4, 92(s5)
-	sw		t3, 88(s5)
-	sw		t2, 84(s5)
-	sw		t1, 80(s5)
-	sw		t0, 76(s5)
-	sw		a3, 72(s5)
-	sw		a2, 68(s5)
-	sw		a1, 64(s5)
-	sw		a0, 60(s5)
-	sw		v1, 56(s5)
-	sw		v0, 52(s5)
-	sw		s6, portEPC_STACK_LOCATION(s5)
-	sw		$1, 16(s5)
-
-	/* MEC14xx does not have DSP, removed 7 words */
-	mfhi	s6
-	sw		s6, 12(s5)
-	mflo	s6
-	sw		s6, 8(s5)
-
-	/* Update the task stack pointer value if nesting is zero. */
-	la		s6, uxInterruptNesting
-	lw		s6, (s6)
-	addiu	s6, s6, -1
-	bne		s6, zero, 1f
-	nop
-
-	/* Save the stack pointer. */
-	la		s6, uxSavedTaskStackPointer
-	sw		s5, (s6)
-1:
-	.endm
-
-/******************************************************************/
-.macro	portRESTORE_CONTEXT
-
-	/* Restore the stack pointer from the TCB.  This is only done if the
-	nesting count is 1. */
-	la		s6, uxInterruptNesting
-	lw		s6, (s6)
-	addiu   s6, s6, -1
-	bne		s6, zero, 1f
-	nop
-	la		s6, uxSavedTaskStackPointer
-	lw		s5, (s6)
-
-	/* Restore the context.
-	MCHP MEC14xx does not include DSP */
-1:
-	lw		s6, 8(s5)
-	mtlo	s6
-	lw		s6, 12(s5)
-	mthi	s6
-	lw		$1, 16(s5)
-
-	/* s6 is loaded as it was used as a scratch register and therefore saved
-	as part of the interrupt context. */
-	lw		s6, 44(s5)
-	lw		v0, 52(s5)
-	lw		v1, 56(s5)
-	lw		a0, 60(s5)
-	lw		a1, 64(s5)
-	lw		a2, 68(s5)
-	lw		a3, 72(s5)
-	lw		t0, 76(s5)
-	lw		t1, 80(s5)
-	lw		t2, 84(s5)
-	lw		t3, 88(s5)
-	lw		t4, 92(s5)
-	lw		t5, 96(s5)
-	lw		t6, 100(s5)
-	lw		t7, 104(s5)
-	lw		t8, 108(s5)
-	lw		t9, 112(s5)
-	lw		s8, 116(s5)
-	lw		ra, 120(s5)
-
-	/* Protect access to the k registers, and others. */
-	di
-	ehb
-
-	/* Decrement the nesting count. */
-	la		k0, uxInterruptNesting
-	lw		k1, (k0)
-	addiu	k1, k1, -1
-	sw		k1, 0(k0)
-
-	lw		k0, portSTATUS_STACK_LOCATION(s5)
-	lw		k1, portEPC_STACK_LOCATION(s5)
-
-	/* Leave the stack in its original state.  First load sp from s5, then
-	restore s5 from the stack. */
-	add		sp, zero, s5
-	lw		s5, 40(sp)
-	addiu   sp, sp, portCONTEXT_SIZE
-
-	mtc0	k0, _CP0_STATUS
-	mtc0	k1, _CP0_EPC
-	ehb
-	eret
-	nop
-
-	.endm
-
-#endif /* #ifdef __LANGUAGE_ASSEMBLY__ */
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port.c b/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port.c
deleted file mode 100755
index b5159fa..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port.c
+++ /dev/null
@@ -1,345 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PIC32MEC14xx  port.
- *----------------------------------------------------------*/
-
-/* Scheduler include files. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Microchip includes. */
-#include 
-#include 
-
-#if !defined(__MEC__)
-	#error This port is designed to work with XC32 on MEC14xx.  Please update your C compiler version or settings.
-#endif
-
-#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
-	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
-#endif
-
-/* Bits within various registers. */
-#define portIE_BIT					( 0x00000001 )
-#define portEXL_BIT					( 0x00000002 )
-
-/* The EXL bit is set to ensure interrupts do not occur while the context of
-the first task is being restored.  MEC14xx does not have DSP HW. */
-#define portINITIAL_SR				( portIE_BIT | portEXL_BIT )
-
-/* MEC14xx RTOS Timer MMCR's. */
-#define portMMCR_RTMR_PRELOAD	*((volatile uint32_t *)(0xA0007404ul))
-#define portMMCR_RTMR_CONTROL	*((volatile uint32_t *)(0xA0007408ul))
-
-/* MEC14xx JTVIC external interrupt controller is mapped to M14K closely-coupled
-peripheral space. */
-#define portGIRQ23_RTOS_TIMER_BITPOS	( 4 )
-#define portGIRQ23_RTOS_TIMER_MASK		( 1ul << ( portGIRQ23_RTOS_TIMER_BITPOS ) )
-#define portMMCR_JTVIC_GIRQ23_SRC		*((volatile uint32_t *)(0xBFFFC0F0ul))
-#define portMMCR_JTVIC_GIRQ23_SETEN		*((volatile uint32_t *)(0xBFFFC0F4ul))
-#define portMMCR_JTVIC_GIRQ23_PRIA		*((volatile uint32_t *)(0xBFFFC3F0ul))
-
-/* MIPS Software Interrupts are routed through JTVIC GIRQ24 */
-#define portGIRQ24_M14K_SOFTIRQ0_BITPOS	( 1 )
-#define portGIRQ24_M14K_SOFTIRQ0_MASK	( 1ul << ( portGIRQ24_M14K_SOFTIRQ0_BITPOS ) )
-#define portMMCR_JTVIC_GIRQ24_SRC		*((volatile uint32_t *)(0xBFFFC100ul))
-#define portMMCR_JTVIC_GIRQ24_SETEN		*((volatile uint32_t *)(0xBFFFC104ul))
-#define portMMCR_JTVIC_GIRQ24_PRIA		*((volatile uint32_t *)(0xBFFFC400ul))
-
-/*
-By default port.c generates its tick interrupt from the RTOS timer.  The user
-can override this behaviour by:
-	1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
-	   which is the function that configures the timer.  The function is defined
-	   as a weak symbol in this file so if the same function name is used in the
-	   application code then the version in the application code will be linked
-	   into the application in preference to the version defined in this file.
-	2: Provide a vector implementation in port_asm.S that overrides the default
-	   behaviour for the specified interrupt vector.
-	3: Specify the correct bit to clear the interrupt during the timer interrupt
-	   handler.
-*/
-#ifndef configTICK_INTERRUPT_VECTOR
-	#define configTICK_INTERRUPT_VECTOR girq23_b4
-	#define configCLEAR_TICK_TIMER_INTERRUPT() portMMCR_JTVIC_GIRQ23_SRC = portGIRQ23_RTOS_TIMER_MASK
-#else
-	#ifndef configCLEAR_TICK_TIMER_INTERRUPT
-		#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
-	#endif
-#endif
-
-/* Let the user override the pre-loading of the initial RA with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the debugger -
-in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
-stack checking.  A problem in the ISR stack will trigger an assert, not call the
-stack overflow hook function (because the stack overflow hook is specific to a
-task stack, not the ISR stack). */
-#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
-
-	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernel for
-	the task stacks, and so will legitimately appear in many positions within
-	the ISR stack. */
-    #define portISR_STACK_FILL_BYTE	0xee
-
-	static const uint8_t ucExpectedStackBytes[] = {
-							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-							portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };	\
-
-	#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else
-	/* Define the function away. */
-	#define portCHECK_ISR_STACK()
-#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
-
-
-/*-----------------------------------------------------------*/
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Records the interrupt nesting depth.  This is initialised to one as it is
-decremented to 0 when the first task starts. */
-volatile UBaseType_t uxInterruptNesting = 0x01;
-
-/* Stores the task stack pointer when a switch is made to use the system stack. */
-UBaseType_t uxSavedTaskStackPointer = 0;
-
-/* The stack used by interrupt service routines that cause a context switch. */
-StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
-
-/* The top of stack value ensures there is enough space to store 6 registers on
-the callers stack, as some functions seem to want to do this. */
-const StackType_t * const xISRStackTop = &( xISRStack[ configISR_STACK_SIZE - 7 ] );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Ensure byte alignment is maintained when leaving this function. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) 0x12345678;	/* Word to which the stack pointer will be left pointing after context restore. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) ulPortGetCP0Cause();
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) portINITIAL_SR;	/* CP0_STATUS */
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) pxCode; 		/* CP0_EPC */
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;	/* ra */
-	pxTopOfStack -= 15;
-
-	*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
-	pxTopOfStack -= 15;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static __inline uint32_t prvDisableInterrupt( void )
-{
-uint32_t prev_state;
-
-	__asm volatile( "di %0; ehb" : "=r" ( prev_state ) :: "memory" );
-	return prev_state;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxSavedTaskStackPointer == 0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup a timer for a regular tick.  This function uses the RTOS timer.
- * The function is declared weak so an application writer can use a different
- * timer by redefining this implementation.  If a different timer is used then
- * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
- * ensure the RTOS provided tick interrupt handler is installed on the correct
- * vector number.
- */
-__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
-{
-/* MEC14xx RTOS Timer whose input clock is 32KHz. */
-const uint32_t ulPreload = ( 32768ul / ( configTICK_RATE_HZ ) );
-
-	configASSERT( ulPreload != 0UL );
-
-	/* Configure the RTOS timer. */
-	portMMCR_RTMR_CONTROL = 0ul;
-	portMMCR_RTMR_PRELOAD = ulPreload;
-
-	/* Configure interrupts from the RTOS timer. */
-	portMMCR_JTVIC_GIRQ23_SRC = ( portGIRQ23_RTOS_TIMER_MASK );
-	portMMCR_JTVIC_GIRQ23_PRIA &= ~( 0x0Ful << 16 );
-	portMMCR_JTVIC_GIRQ23_PRIA |= ( ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) ) << 16 );
-	portMMCR_JTVIC_GIRQ23_SETEN = ( portGIRQ23_RTOS_TIMER_MASK );
-
-	/* Enable the RTOS timer. */
-	portMMCR_RTMR_CONTROL = 0x0Fu;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler(void)
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxInterruptNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortStartFirstTask( void );
-extern void *pxCurrentTCB;
-
-	#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
-	{
-		/* Fill the ISR stack to make it easy to asses how much is being used. */
-		memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
-	}
-	#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
-
-	/* Clear the software interrupt flag. */
-	portMMCR_JTVIC_GIRQ24_SRC = (portGIRQ24_M14K_SOFTIRQ0_MASK);
-
-	/* Set software timer priority.  Each GIRQn has one nibble containing its
-	priority */
-	portMMCR_JTVIC_GIRQ24_PRIA &= ~(0xF0ul);
-	portMMCR_JTVIC_GIRQ24_PRIA |= ( portIPL_TO_CODE( configKERNEL_INTERRUPT_PRIORITY ) << 4 );
-
-	/* Enable software interrupt. */
-	portMMCR_JTVIC_GIRQ24_SETEN = ( portGIRQ24_M14K_SOFTIRQ0_MASK );
-
-	/* Setup the timer to generate the tick.  Interrupts will have been disabled
-	by the time we get here. */
-	vApplicationSetupTickTimerInterrupt();
-
-	/* Start the highest priority task that has been created so far.  Its stack
-	location is loaded into uxSavedTaskStackPointer. */
-	uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
-	vPortStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing!  Call the task
-	exit error function to prevent compiler warnings about a static function
-	not being called in the case that the application writer overrides this
-	functionality by defining configTASK_RETURN_ADDRESS. */
-	prvTaskExitError();
-
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortIncrementTick( void )
-{
-UBaseType_t uxSavedStatus;
-uint32_t ulCause;
-
-	uxSavedStatus = uxPortSetInterruptMaskFromISR();
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			ulCause = ulPortGetCP0Cause();
-			ulCause |= ( 1ul << 8UL );
-			vPortSetCP0Cause( ulCause );
-		}
-	}
-	vPortClearInterruptMaskFromISR( uxSavedStatus );
-
-	/* Look for the ISR stack getting near or past its limit. */
-	portCHECK_ISR_STACK();
-
-	/* Clear timer interrupt. */
-	configCLEAR_TICK_TIMER_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxPortSetInterruptMaskFromISR( void )
-{
-UBaseType_t uxSavedStatusRegister;
-
-	prvDisableInterrupt();
-	uxSavedStatusRegister = ulPortGetCP0Status() | 0x01;
-
-	/* This clears the IPL bits, then sets them to
-	configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
-	from an interrupt that has a priority above
-	configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
-	can only result in the IPL being unchanged or raised, and therefore never
-	lowered. */
-	vPortSetCP0Status( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
-
-	return uxSavedStatusRegister;
-}
-/*-----------------------------------------------------------*/
-
-void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
-{
-	vPortSetCP0Status( uxSavedStatusRegister );
-}
-/*-----------------------------------------------------------*/
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S b/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S
deleted file mode 100755
index 60d8072..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/port_asm.S
+++ /dev/null
@@ -1,348 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* FreeRTOS includes. */
-#include "FreeRTOSConfig.h"
-#include "ISR_Support.h"
-
-/* Microchip includes. */
-#include 
-#include 
-
-	.extern pxCurrentTCB
-	.extern vTaskSwitchContext
-	.extern vPortIncrementTick
-	.extern xISRStackTop
-
-	PORT_CPP_JTVIC_BASE = 0xBFFFC000
-	PORT_CCP_JTVIC_GIRQ24_SRC = 0xBFFFC100
-
-	.global vPortStartFirstTask .text
-	.global vPortYieldISR .text
-	.global vPortTickInterruptHandler .text
-
-
-/******************************************************************/
-
-
-/***************************************************************
-*  The following is needed to locate the
-*  vPortTickInterruptHandler function into the correct vector
-*  MEC14xx - This ISR will only be used if HW timers' interrupts
-*  in GIRQ23 are disaggregated.
-*
-***************************************************************/
-
-	.set  noreorder
-	.set  noat
-	.set  micromips
-
-	.section .text, code
-	.ent    vPortTickInterruptHandler
-
-#if configTIMERS_DISAGGREGATED_ISRS == 0
-
-	.globl girq23_isr
-
-girq23_isr:
-vPortTickInterruptHandler:
-
-	portSAVE_CONTEXT
-
-	jal		girq23_handler
-	nop
-
-	portRESTORE_CONTEXT
-
-.end vPortTickInterruptHandler
-
-#else
-
-	.globl girq23_b4
-
-girq23_b4:
-vPortTickInterruptHandler:
-
-	portSAVE_CONTEXT
-
-	jal		vPortIncrementTick
-	nop
-
-	portRESTORE_CONTEXT
-
-.end vPortTickInterruptHandler
-
-#endif /* #if configTIMERS_DISAGGREGATED_ISRS == 0 */
-
-/******************************************************************/
-
-	.set	micromips
-	.set	noreorder
-	.set	noat
-
-	.section .text, code
-	.ent	vPortStartFirstTask
-
-vPortStartFirstTask:
-
-	/* Simply restore the context of the highest priority task that has
-	been created so far. */
-	portRESTORE_CONTEXT
-
-.end vPortStartFirstTask
-
-
-
-/*******************************************************************/
-
-/***************************************************************
-*  The following is needed to locate the vPortYieldISR function into the correct
-* vector.
-***************************************************************/
-
-	.set micromips
-	.set noreorder
-	.set noat
-
-	.section .text, code
-
-	.global vPortYieldISR
-
-
-#if configCPU_DISAGGREGATED_ISRS == 0
-	.global girq24_isr
-	.ent girq24_isr
-girq24_isr:
-	la		k0, PORT_CPP_JTVIC_BASE
-	lw		k0, 0x10C(k0)
-	andi	k1, k0, 0x2
-	bgtz	k1, vPortYieldISR
-	nop
-
-	portSAVE_CONTEXT
-
-	jal		girq24_b_0_2
-
-	portRESTORE_CONTEXT
-
-	.end girq24_isr
-
-#else
-	.global girq24_b1
-girq24_b1:
-#endif
-		.ent  vPortYieldISR
-vPortYieldISR:
-
-	/* Make room for the context. First save the current status so it can be
-	manipulated, and the cause and EPC registers so thier original values
-	are captured. */
-	addiu	sp, sp, -portCONTEXT_SIZE
-	mfc0	k1, _CP0_STATUS
-
-	/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
-	maintain the values of these registers across the ISR. */
-	sw		s6, 44(sp)
-	sw		s5, 40(sp)
-	sw		k1, portSTATUS_STACK_LOCATION(sp)
-
-	/* Prepare to re-enable interrupts above the kernel priority. */
-	ins		k1, zero, 10, 7		 /* Clear IPL bits 0:6. */
-	ins		k1, zero, 18, 1		 /* Clear IPL bit 7  */
-	ori		k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
-	ins		k1, zero, 1, 4		  /* Clear EXL, ERL and UM. */
-
-	/* s5 is used as the frame pointer. */
-	add		s5, zero, sp
-
-	/* Swap to the system stack.  This is not conditional on the nesting
-	count as this interrupt is always the lowest priority and therefore
-	the nesting is always 0. */
-	la		sp, xISRStackTop
-	lw		sp, (sp)
-
-	/* Set the nesting count. */
-	la		k0, uxInterruptNesting
-	addiu   s6, zero, 1
-	sw		s6, 0(k0)
-
-	/* s6 holds the EPC value, this is saved with the rest of the context
-	after interrupts are enabled. */
-	mfc0	s6, _CP0_EPC
-
-	/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	mtc0	k1, _CP0_STATUS
-
-	/* Save the context into the space just created.  s6 is saved again
-	here as it now contains the EPC value. */
-	sw		ra, 120(s5)
-	sw		s8, 116(s5)
-	sw		t9, 112(s5)
-	sw		t8, 108(s5)
-	sw		t7, 104(s5)
-	sw		t6, 100(s5)
-	sw		t5, 96(s5)
-	sw		t4, 92(s5)
-	sw		t3, 88(s5)
-	sw		t2, 84(s5)
-	sw		t1, 80(s5)
-	sw		t0, 76(s5)
-	sw		a3, 72(s5)
-	sw		a2, 68(s5)
-	sw		a1, 64(s5)
-	sw		a0, 60(s5)
-	sw		v1, 56(s5)
-	sw		v0, 52(s5)
-	sw		s7, 48(s5)
-	sw		s6, portEPC_STACK_LOCATION(s5)
-	/* s5 and s6 has already been saved. */
-	sw		s4, 36(s5)
-	sw		s3, 32(s5)
-	sw		s2, 28(s5)
-	sw		s1, 24(s5)
-	sw		s0, 20(s5)
-	sw		$1, 16(s5)
-
-	/* s7 is used as a scratch register as this should always be saved acro ss
-	nesting interrupts. */
-	mfhi	s7
-	sw		s7, 12(s5)
-	mflo	s7
-	sw		s7, 8(s5)
-
-	/* Save the stack pointer to the task. */
-	la		s7, pxCurrentTCB
-	lw		s7, (s7)
-	sw		s5, (s7)
-
-	/* Set the interrupt mask to the max priority that can use the API.
-	The yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY
-	which is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only
-	ever raise the IPL value and never lower it. */
-	di
-	ehb
-	mfc0	s7, _CP0_STATUS
-	ins		s7, zero, 10, 7
-	ins		s7, zero, 18, 1
-	ori		s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
-
-	/* This mtc0 re-enables interrupts, but only above
-	configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	mtc0	s6, _CP0_STATUS
-	ehb
-
-	/* Clear the software interrupt in the core. */
-	mfc0	s6, _CP0_CAUSE
-	ins		s6, zero, 8, 1
-	mtc0	s6, _CP0_CAUSE
-	ehb
-
-	/* Clear the interrupt in the interrupt controller.
-	MEC14xx GIRQ24 Source bit[1] = 1 to clear */
-	la		s6, PORT_CCP_JTVIC_GIRQ24_SRC
-	addiu	s4, zero, 2
-	sw		s4, (s6)
-	jal		vTaskSwitchContext
-	nop
-
-	/* Clear the interrupt mask again. The saved status value is still in s7 */
-	mtc0	s7, _CP0_STATUS
-	ehb
-
-	/* Restore the stack pointer from the TCB. */
-	la		s0, pxCurrentTCB
-	lw		s0, (s0)
-	lw		s5, (s0)
-
-	/* Restore the rest of the context. */
-	lw		s0, 8(s5)
-	mtlo	s0
-	lw		s0, 12(s5)
-	mthi	s0
-
-	lw		$1, 16(s5)
-	lw		s0, 20(s5)
-	lw		s1, 24(s5)
-	lw		s2, 28(s5)
-	lw		s3, 32(s5)
-	lw		s4, 36(s5)
-
-	/* s5 is loaded later. */
-	lw		s6, 44(s5)
-	lw		s7, 48(s5)
-	lw		v0, 52(s5)
-	lw		v1, 56(s5)
-	lw		a0, 60(s5)
-	lw		a1, 64(s5)
-	lw		a2, 68(s5)
-	lw		a3, 72(s5)
-	lw		t0, 76(s5)
-	lw		t1, 80(s5)
-	lw		t2, 84(s5)
-	lw		t3, 88(s5)
-	lw		t4, 92(s5)
-	lw		t5, 96(s5)
-	lw		t6, 100(s5)
-	lw		t7, 104(s5)
-	lw		t8, 108(s5)
-	lw		t9, 112(s5)
-	lw		s8, 116(s5)
-	lw		ra, 120(s5)
-
-	/* Protect access to the k registers, and others. */
-	di
-	ehb
-
-	/* Set nesting back to zero.  As the lowest priority interrupt this
-	interrupt cannot have nested. */
-	la		k0, uxInterruptNesting
-	sw		zero, 0(k0)
-
-	/* Switch back to use the real stack pointer. */
-	add		sp, zero, s5
-
-	/* Restore the real s5 value. */
-	lw		s5, 40(sp)
-
-	/* Pop the status and epc values. */
-	lw		k1, portSTATUS_STACK_LOCATION(sp)
-	lw		k0, portEPC_STACK_LOCATION(sp)
-
-	/* Remove stack frame. */
-	addiu	sp, sp, portCONTEXT_SIZE
-
-	mtc0	k1, _CP0_STATUS
-	mtc0	k0, _CP0_EPC
-	ehb
-	eret
-	nop
-
-.end	vPortYieldISR
-
-
-
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/portmacro.h b/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/portmacro.h
deleted file mode 100755
index 1595288..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MEC14xx/portmacro.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      double
-#define portLONG        long
-#define portSHORT       short
-#define portSTACK_TYPE  uint32_t
-#define portBASE_TYPE   long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT  8
-#define portSTACK_GROWTH    -1
-#define portTICK_PERIOD_MS  ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-#define portIPL_SHIFT       ( 10UL )
-/* Don't straddle the CEE bit.  Interrupts calling FreeRTOS functions should
-never have higher IPL bits set anyway. */
-#define portALL_IPL_BITS    ( 0x7FUL << portIPL_SHIFT )
-#define portSW0_BIT         ( 0x01 << 8 )
-
-/* Interrupt priority conversion */
-#define portIPL_TO_CODE( iplNumber )    ( ( iplNumber >> 1 ) & 0x03ul )
-#define portCODE_TO_IPL( iplCode )      ( ( iplCode << 1 ) | 0x01ul )
-
-/*-----------------------------------------------------------*/
-
-static inline uint32_t ulPortGetCP0Status( void )
-{
-uint32_t rv;
-
-	__asm volatile(
-			"\n\t"
-			"mfc0 %0,$12,0      \n\t"
-			: "=r" ( rv ) :: );
-
-	return rv;
-}
-/*-----------------------------------------------------------*/
-
-static inline void vPortSetCP0Status( uint32_t new_status)
-{
-	( void ) new_status;
-
-	__asm__ __volatile__(
-			"\n\t"
-			"mtc0 %0,$12,0      \n\t"
-			"ehb                \n\t"
-			:
-			:"r" ( new_status ) : );
-}
-/*-----------------------------------------------------------*/
-
-static inline uint32_t ulPortGetCP0Cause( void )
-{
-uint32_t rv;
-
-	__asm volatile(
-			"\n\t"
-			"mfc0 %0,$13,0      \n\t"
-			: "=r" ( rv ) :: );
-
-    return rv;
-}
-/*-----------------------------------------------------------*/
-
-static inline void vPortSetCP0Cause( uint32_t new_cause )
-{
-	( void ) new_cause;
-
-	__asm__ __volatile__(
-			"\n\t"
-			"mtc0 %0,$13,0      \n\t"
-			"ehb                \n\t"
-			:
-			:"r" ( new_cause ) : );
-}
-/*-----------------------------------------------------------*/
-
-/* This clears the IPL bits, then sets them to
-configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
-configASSERT() is defined to ensure an assertion handler does not inadvertently
-attempt to lower the IPL when the call to assert was triggered because the IPL
-value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
-safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
-those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
-ensure API function and interrupt entry is as fast and as simple as possible. */
-#ifdef configASSERT
-    #define portDISABLE_INTERRUPTS() 																			\
-	{ 																											\
-	uint32_t ulStatus; 																							\
-		/* Mask interrupts at and below the kernel interrupt priority. */  										\
-		ulStatus = ulPortGetCP0Status(); 																		\
-		/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */ 									\
-		if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) 		\
-		{ 																										\
-			ulStatus &= ~portALL_IPL_BITS;  																	\
-			vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); 		\
-		} 																										\
-    }
-#else /* configASSERT */
-	#define portDISABLE_INTERRUPTS() 																			\
-	{ 																											\
-	uint32_t ulStatus;  																						\
-		/* Mask interrupts at and below the kernel interrupt priority. */ 										\
-		ulStatus = ulPortGetCP0Status(); 																		\
-		ulStatus &= ~portALL_IPL_BITS; 																			\
-		vPortSetCP0Status( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); 			\
-	}
-#endif /* configASSERT */
-
-#define portENABLE_INTERRUPTS() 			\
-{ 											\
-uint32_t ulStatus; 							\
-	/* Unmask all interrupts. */ 			\
-	ulStatus = ulPortGetCP0Status(); 		\
-	ulStatus &= ~portALL_IPL_BITS; 			\
-	vPortSetCP0Status( ulStatus ); 			\
-}
-
-
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portCRITICAL_NESTING_IN_TCB	1
-#define portENTER_CRITICAL()		vTaskEnterCritical()
-#define portEXIT_CRITICAL()			vTaskExitCritical()
-
-extern UBaseType_t uxPortSetInterruptMaskFromISR();
-extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
-
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - _clz( ( uxReadyPriorities ) ) )
-
-#endif /* taskRECORD_READY_PRIORITY */
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-#define portYIELD() 						\
-{ 											\
-uint32_t ulCause; 							\
-	/* Trigger software interrupt. */ 		\
-	ulCause = ulPortGetCP0Cause(); 			\
-	ulCause |= portSW0_BIT; 				\
-	vPortSetCP0Cause( ulCause ); 			\
-}
-
-extern volatile UBaseType_t uxInterruptNesting;
-#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
-
-#define portNOP() __asm volatile ( "nop" )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#define portEND_SWITCHING_ISR( xSwitchRequired ) 	if( xSwitchRequired )	\
-													{ 						\
-														portYIELD();		\
-													}
-
-/* Required by the kernel aware debugger. */
-#ifdef __DEBUG
-    #define portREMOVE_STATIC_QUALIFIER
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MX/ISR_Support.h b/FreeRTOS/Source/portable/MPLAB/PIC32MX/ISR_Support.h
deleted file mode 100755
index c6bc98c..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MX/ISR_Support.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include "FreeRTOSConfig.h"
-
-#define portCONTEXT_SIZE 132
-#define portEPC_STACK_LOCATION	124
-#define portSTATUS_STACK_LOCATION 128
-
-/******************************************************************/
-.macro	portSAVE_CONTEXT
-
-	/* Make room for the context. First save the current status so it can be
-	manipulated, and the cause and EPC registers so their original values are
-	captured. */
-	mfc0		k0, _CP0_CAUSE
-	addiu		sp,	sp, -portCONTEXT_SIZE
-	mfc0		k1, _CP0_STATUS
-
-	/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
-	maintain the values of these registers across the ISR. */
-	sw			s6, 44(sp)
-	sw			s5, 40(sp)
-	sw			k1, portSTATUS_STACK_LOCATION(sp)
-
-	/* Prepare to enable interrupts above the current priority. */
-	srl			k0, k0, 0xa
-	ins 		k1, k0, 10, 6
-	ins			k1, zero, 1, 4
-
-	/* s5 is used as the frame pointer. */
-	add			s5, zero, sp
-
-	/* Check the nesting count value. */
-	la			k0, uxInterruptNesting
-	lw			s6, (k0)
-
-	/* If the nesting count is 0 then swap to the the system stack, otherwise
-	the system stack is already being used. */
-	bne			s6, zero, 1f
-	nop
-
-	/* Swap to the system stack. */
-	la			sp, xISRStackTop
-	lw			sp, (sp)
-
-	/* Increment and save the nesting count. */
-1:	addiu		s6, s6, 1
-	sw			s6, 0(k0)
-
-	/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
-	mfc0 		s6, _CP0_EPC
-
-	/* Re-enable interrupts. */
-	mtc0		k1, _CP0_STATUS
-
-	/* Save the context into the space just created.  s6 is saved again
-	here as it now contains the EPC value.  No other s registers need be
-	saved. */
-	sw			ra, 120(s5)
-	sw			s8, 116(s5)
-	sw			t9, 112(s5)
-	sw			t8, 108(s5)
-	sw			t7, 104(s5)
-	sw			t6, 100(s5)
-	sw			t5, 96(s5)
-	sw			t4, 92(s5)
-	sw			t3, 88(s5)
-	sw			t2, 84(s5)
-	sw			t1, 80(s5)
-	sw			t0, 76(s5)
-	sw			a3, 72(s5)
-	sw			a2, 68(s5)
-	sw			a1, 64(s5)
-	sw			a0, 60(s5)
-	sw			v1, 56(s5)
-	sw			v0, 52(s5)
-	sw			s6, portEPC_STACK_LOCATION(s5)
-	sw			$1, 16(s5)
-
-	/* s6 is used as a scratch register. */
-	mfhi		s6
-	sw			s6, 12(s5)
-	mflo		s6
-	sw			s6, 8(s5)
-
-	/* Update the task stack pointer value if nesting is zero. */
-	la			s6, uxInterruptNesting
-	lw			s6, (s6)
-	addiu		s6, s6, -1
-	bne			s6, zero, 1f
-	nop
-
-	/* Save the stack pointer. */
-	la			s6, uxSavedTaskStackPointer
-	sw			s5, (s6)
-1:
-	.endm
-
-/******************************************************************/
-.macro	portRESTORE_CONTEXT
-
-	/* Restore the stack pointer from the TCB.  This is only done if the
-	nesting count is 1. */
-	la			s6, uxInterruptNesting
-	lw			s6, (s6)
-	addiu		s6, s6, -1
-	bne			s6, zero, 1f
-	nop
-	la			s6, uxSavedTaskStackPointer
-	lw			s5, (s6)
-
-	/* Restore the context. */
-1:	lw			s6, 8(s5)
-	mtlo		s6
-	lw			s6, 12(s5)
-	mthi		s6
-	lw			$1, 16(s5)
-	/* s6 is loaded as it was used as a scratch register and therefore saved
-	as part of the interrupt context. */
-	lw			s6, 44(s5)
-	lw			v0, 52(s5)
-	lw			v1, 56(s5)
-	lw			a0, 60(s5)
-	lw			a1, 64(s5)
-	lw			a2, 68(s5)
-	lw			a3, 72(s5)
-	lw			t0, 76(s5)
-	lw			t1, 80(s5)
-	lw			t2, 84(s5)
-	lw			t3, 88(s5)
-	lw			t4, 92(s5)
-	lw			t5, 96(s5)
-	lw			t6, 100(s5)
-	lw			t7, 104(s5)
-	lw			t8, 108(s5)
-	lw			t9, 112(s5)
-	lw			s8, 116(s5)
-	lw			ra, 120(s5)
-
-	/* Protect access to the k registers, and others. */
-	di
-	ehb
-
-	/* Decrement the nesting count. */
-	la			k0, uxInterruptNesting
-	lw			k1, (k0)
-	addiu		k1, k1, -1
-	sw			k1, 0(k0)
-
-	lw			k0, portSTATUS_STACK_LOCATION(s5)
-	lw			k1, portEPC_STACK_LOCATION(s5)
-
-	/* Leave the stack in its original state.  First load sp from s5, then
-	restore s5 from the stack. */
-	add			sp, zero, s5
-	lw			s5, 40(sp)
-	addiu		sp, sp,	portCONTEXT_SIZE
-
-	mtc0		k0, _CP0_STATUS
-	mtc0 		k1, _CP0_EPC
-	ehb
-	eret
-	nop
-
-	.endm
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MX/port.c b/FreeRTOS/Source/portable/MPLAB/PIC32MX/port.c
deleted file mode 100755
index e4329a9..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MX/port.c
+++ /dev/null
@@ -1,332 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PIC32MX port.
-  *----------------------------------------------------------*/
-
-#ifndef __XC
-    #error This port is designed to work with XC32.  Please update your C compiler version.
-#endif
-
-/* Scheduler include files. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Hardware specifics. */
-#define portTIMER_PRESCALE	8
-#define portPRESCALE_BITS	1
-
-/* Bits within various registers. */
-#define portIE_BIT						( 0x00000001 )
-#define portEXL_BIT						( 0x00000002 )
-
-/* Bits within the CAUSE register. */
-#define portCORE_SW_0					( 0x00000100 )
-#define portCORE_SW_1					( 0x00000200 )
-
-/* The EXL bit is set to ensure interrupts do not occur while the context of
-the first task is being restored. */
-#define portINITIAL_SR					( portIE_BIT | portEXL_BIT )
-
-/*
-By default port.c generates its tick interrupt from TIMER1.  The user can
-override this behaviour by:
-	1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
-	   which is the function that configures the timer.  The function is defined
-	   as a weak symbol in this file so if the same function name is used in the
-	   application code then the version in the application code will be linked
-	   into the application in preference to the version defined in this file.
-	2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
-	   to generate the tick interrupt.  For example, when timer 1 is used then
-	   configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
-	   configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
-	3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
-	   timer used to generate the tick interrupt.  For example, when timer 1 is
-	   used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
-	   IFS0CLR = _IFS0_T1IF_MASK.
-*/
-#ifndef configTICK_INTERRUPT_VECTOR
-	#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
-	#define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
-#else
-	#ifndef configCLEAR_TICK_TIMER_INTERRUPT
-		#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
-	#endif
-#endif
-
-/* Let the user override the pre-loading of the initial RA with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
-stack checking.  A problem in the ISR stack will trigger an assert, not call the
-stack overflow hook function (because the stack overflow hook is specific to a
-task stack, not the ISR stack). */
-#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
-
-	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
-	the task stacks, and so will legitimately appear in many positions within
-	the ISR stack. */
-	#define portISR_STACK_FILL_BYTE	0xee
-
-	static const uint8_t ucExpectedStackBytes[] = {
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };	\
-
-	#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else
-	/* Define the function away. */
-	#define portCHECK_ISR_STACK()
-#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
-
-/*-----------------------------------------------------------*/
-
-
-/*
- * Place the prototype here to ensure the interrupt vector is correctly installed.
- * Note that because the interrupt is written in assembly, the IPL setting in the
- * following line of code has no effect.  The interrupt priority is set by the
- * call to ConfigIntTimer1() in vApplicationSetupTickTimerInterrupt().
- */
-extern void __attribute__( (interrupt(IPL1AUTO), vector( configTICK_INTERRUPT_VECTOR ))) vPortTickInterruptHandler( void );
-
-/*
- * The software interrupt handler that performs the yield.  Note that, because
- * the interrupt is written in assembly, the IPL setting in the following line of
- * code has no effect.  The interrupt priority is set by the call to
- * mConfigIntCoreSW0() in xPortStartScheduler().
- */
-void __attribute__( (interrupt(IPL1AUTO), vector(_CORE_SOFTWARE_0_VECTOR))) vPortYieldISR( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Records the interrupt nesting depth.  This is initialised to one as it is
-decremented to 0 when the first task starts. */
-volatile UBaseType_t uxInterruptNesting = 0x01;
-
-/* Stores the task stack pointer when a switch is made to use the system stack. */
-UBaseType_t uxSavedTaskStackPointer = 0;
-
-/* The stack used by interrupt service routines that cause a context switch. */
-__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
-
-/* The top of stack value ensures there is enough space to store 6 registers on
-the callers stack, as some functions seem to want to do this. */
-const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Ensure byte alignment is maintained when leaving this function. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) 0x12345678;	/* Word to which the stack pointer will be left pointing after context restore. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) pxCode; 		/* CP0_EPC */
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;	/* ra */
-	pxTopOfStack -= 15;
-
-	*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
-	pxTopOfStack -= 15;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxSavedTaskStackPointer == 0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup a timer for a regular tick.  This function uses peripheral timer 1.
- * The function is declared weak so an application writer can use a different
- * timer by redefining this implementation.  If a different timer is used then
- * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
- * ensure the RTOS provided tick interrupt handler is installed on the correct
- * vector number.  When Timer 1 is used the vector number is defined as
- * _TIMER_1_VECTOR.
- */
-__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
-{
-const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1;
-
-	T1CON = 0x0000;
-	T1CONbits.TCKPS = portPRESCALE_BITS;
-	PR1 = ulCompareMatch;
-	IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
-
-	/* Clear the interrupt as a starting condition. */
-	IFS0bits.T1IF = 0;
-
-	/* Enable the interrupt. */
-	IEC0bits.T1IE = 1;
-
-	/* Start the timer. */
-	T1CONbits.TON = 1;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler(void)
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxInterruptNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortStartFirstTask( void );
-extern void *pxCurrentTCB;
-
-	#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
-	{
-		/* Fill the ISR stack to make it easy to asses how much is being used. */
-		memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
-	}
-	#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
-
-	/* Clear the software interrupt flag. */
-	IFS0CLR = _IFS0_CS0IF_MASK;
-
-	/* Set software timer priority. */
-	IPC0CLR = _IPC0_CS0IP_MASK;
-	IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
-
-	/* Enable software interrupt. */
-	IEC0CLR = _IEC0_CS0IE_MASK;
-	IEC0SET = 1 << _IEC0_CS0IE_POSITION;
-
-	/* Setup the timer to generate the tick.  Interrupts will have been
-	disabled by the time we get here. */
-	vApplicationSetupTickTimerInterrupt();
-
-	/* Kick off the highest priority task that has been created so far.
-	Its stack location is loaded into uxSavedTaskStackPointer. */
-	uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
-	vPortStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing!  Call the task
-	exit error function to prevent compiler warnings about a static function
-	not being called in the case that the application writer overrides this
-	functionality by defining configTASK_RETURN_ADDRESS. */
-	prvTaskExitError();
-
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortIncrementTick( void )
-{
-UBaseType_t uxSavedStatus;
-
-	uxSavedStatus = uxPortSetInterruptMaskFromISR();
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			_CP0_BIS_CAUSE( portCORE_SW_0 );
-		}
-	}
-	vPortClearInterruptMaskFromISR( uxSavedStatus );
-
-	/* Look for the ISR stack getting near or past its limit. */
-	portCHECK_ISR_STACK();
-
-	/* Clear timer interrupt. */
-	configCLEAR_TICK_TIMER_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxPortSetInterruptMaskFromISR( void )
-{
-UBaseType_t uxSavedStatusRegister;
-
-	__builtin_disable_interrupts();
-	uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
-	/* This clears the IPL bits, then sets them to
-	configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
-	from an interrupt that has a priority above
-	configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
-	can only result in the IPL being unchanged or raised, and therefore never
-	lowered. */
-	_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
-
-	return uxSavedStatusRegister;
-}
-/*-----------------------------------------------------------*/
-
-void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
-{
-	_CP0_SET_STATUS( uxSavedStatusRegister );
-}
-/*-----------------------------------------------------------*/
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MX/port_asm.S b/FreeRTOS/Source/portable/MPLAB/PIC32MX/port_asm.S
deleted file mode 100755
index 79a55d7..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MX/port_asm.S
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include 
-#include 
-#include "ISR_Support.h"
-
-
-	.set	nomips16
- 	.set 	noreorder
-
- 	.extern pxCurrentTCB
- 	.extern vTaskSwitchContext
- 	.extern vPortIncrementTick
-	.extern xISRStackTop
-
- 	.global vPortStartFirstTask
-	.global vPortYieldISR
-	.global vPortTickInterruptHandler
-
-
-/******************************************************************/
-
- 	.set		noreorder
-	.set 		noat
- 	.ent		vPortTickInterruptHandler
-
-vPortTickInterruptHandler:
-
-	portSAVE_CONTEXT
-
-	jal 		vPortIncrementTick
-	nop
-
-	portRESTORE_CONTEXT
-
-	.end vPortTickInterruptHandler
-
-/******************************************************************/
-
- 	.set		noreorder
-	.set 		noat
- 	.ent		vPortStartFirstTask
-
-vPortStartFirstTask:
-
-	/* Simply restore the context of the highest priority task that has been
-	created so far. */
-	portRESTORE_CONTEXT
-
-	.end vPortStartFirstTask
-
-
-
-/*******************************************************************/
-
-	.set		noreorder
-	.set 		noat
-	.ent		vPortYieldISR
-
-vPortYieldISR:
-
-	/* Make room for the context. First save the current status so it can be
-	manipulated. */
-	addiu		sp, sp, -portCONTEXT_SIZE
-	mfc0		k1, _CP0_STATUS
-
-	/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
-	maintain the values of these registers across the ISR. */
-	sw			s6, 44(sp)
-	sw			s5, 40(sp)
-	sw			k1, portSTATUS_STACK_LOCATION(sp)
-
-	/* Prepare to re-enabled interrupt above the kernel priority. */
-	ins 		k1, zero, 10, 6
-	ori			k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
-	ins			k1, zero, 1, 4
-
-	/* s5 is used as the frame pointer. */
-	add			s5, zero, sp
-
-	/* Swap to the system stack.  This is not conditional on the nesting
-	count as this interrupt is always the lowest priority and therefore
-	the nesting is always 0. */
-	la			sp, xISRStackTop
-	lw			sp, (sp)
-
-	/* Set the nesting count. */
-	la			k0, uxInterruptNesting
-	addiu		s6, zero, 1
-	sw			s6, 0(k0)
-
-	/* s6 holds the EPC value, this is saved with the rest of the context
-	after interrupts are enabled. */
-	mfc0 		s6, _CP0_EPC
-
-	/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	mtc0		k1, _CP0_STATUS
-
-	/* Save the context into the space just created.  s6 is saved again
-	here as it now contains the EPC value. */
-	sw			ra, 120(s5)
-	sw			s8, 116(s5)
-	sw			t9, 112(s5)
-	sw			t8, 108(s5)
-	sw			t7, 104(s5)
-	sw			t6, 100(s5)
-	sw			t5, 96(s5)
-	sw			t4, 92(s5)
-	sw			t3, 88(s5)
-	sw			t2, 84(s5)
-	sw			t1, 80(s5)
-	sw			t0, 76(s5)
-	sw			a3, 72(s5)
-	sw			a2, 68(s5)
-	sw			a1, 64(s5)
-	sw			a0, 60(s5)
-	sw			v1, 56(s5)
-	sw			v0, 52(s5)
-	sw			s7, 48(s5)
-	sw			s6, portEPC_STACK_LOCATION(s5)
-	/* s5 and s6 has already been saved. */
-	sw			s4, 36(s5)
-	sw			s3, 32(s5)
-	sw			s2, 28(s5)
-	sw			s1, 24(s5)
-	sw			s0, 20(s5)
-	sw			$1, 16(s5)
-
-	/* s7 is used as a scratch register as this should always be saved across
-	nesting interrupts. */
-	mfhi		s7
-	sw			s7, 12(s5)
-	mflo		s7
-	sw			s7, 8(s5)
-
-	/* Save the stack pointer to the task. */
-	la			s7, pxCurrentTCB
-	lw			s7, (s7)
-	sw			s5, (s7)
-
-	/* Set the interrupt mask to the max priority that can use the API.  The
-	yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
-	is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
-	raise the IPL value and never lower it. */
-	di
-	ehb
-	mfc0		s7, _CP0_STATUS
-	ins 		s7, zero, 10, 6
-	ori			s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
-
-	/* This mtc0 re-enables interrupts, but only above
-	configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-	mtc0		s6, _CP0_STATUS
-	ehb
-
-	/* Clear the software interrupt in the core. */
-	mfc0		s6, _CP0_CAUSE
-	ins			s6, zero, 8, 1
-	mtc0		s6, _CP0_CAUSE
-	ehb
-
-	/* Clear the interrupt in the interrupt controller. */
-	la			s6, IFS0CLR
-	addiu		s4, zero, 2
-	sw			s4, (s6)
-
-	jal			vTaskSwitchContext
-	nop
-
-	/* Clear the interrupt mask again.  The saved status value is still in s7. */
-	mtc0		s7, _CP0_STATUS
-	ehb
-
-	/* Restore the stack pointer from the TCB. */
-	la			s0, pxCurrentTCB
-	lw			s0, (s0)
-	lw			s5, (s0)
-
-	/* Restore the rest of the context. */
-	lw			s0, 8(s5)
-	mtlo		s0
-	lw			s0, 12(s5)
-	mthi		s0
-	lw			$1, 16(s5)
-	lw			s0, 20(s5)
-	lw			s1, 24(s5)
-	lw			s2, 28(s5)
-	lw			s3, 32(s5)
-	lw			s4, 36(s5)
-	/* s5 is loaded later. */
-	lw			s6, 44(s5)
-	lw			s7, 48(s5)
-	lw			v0, 52(s5)
-	lw			v1, 56(s5)
-	lw			a0, 60(s5)
-	lw			a1, 64(s5)
-	lw			a2, 68(s5)
-	lw			a3, 72(s5)
-	lw			t0, 76(s5)
-	lw			t1, 80(s5)
-	lw			t2, 84(s5)
-	lw			t3, 88(s5)
-	lw			t4, 92(s5)
-	lw			t5, 96(s5)
-	lw			t6, 100(s5)
-	lw			t7, 104(s5)
-	lw			t8, 108(s5)
-	lw			t9, 112(s5)
-	lw			s8, 116(s5)
-	lw			ra, 120(s5)
-
-	/* Protect access to the k registers, and others. */
-	di
-	ehb
-
-	/* Set nesting back to zero.  As the lowest priority interrupt this
-	interrupt cannot have nested. */
-	la			k0, uxInterruptNesting
-	sw			zero, 0(k0)
-
-	/* Switch back to use the real stack pointer. */
-	add			sp, zero, s5
-
-	/* Restore the real s5 value. */
-	lw			s5, 40(sp)
-
-	/* Pop the status and epc values. */
-	lw			k1, portSTATUS_STACK_LOCATION(sp)
-	lw			k0, portEPC_STACK_LOCATION(sp)
-
-	/* Remove stack frame. */
-	addiu		sp, sp, portCONTEXT_SIZE
-
-	mtc0		k1, _CP0_STATUS
-	mtc0 		k0, _CP0_EPC
-	ehb
-	eret
-	nop
-
-	.end		vPortYieldISR
-
-
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MX/portmacro.h b/FreeRTOS/Source/portable/MPLAB/PIC32MX/portmacro.h
deleted file mode 100755
index 5065732..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MX/portmacro.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/* System include files */
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			8
-#define portSTACK_GROWTH			-1
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-#define portIPL_SHIFT				( 10UL )
-#define portALL_IPL_BITS			( 0x3fUL << portIPL_SHIFT )
-#define portSW0_BIT					( 0x01 << 8 )
-
-/* This clears the IPL bits, then sets them to
-configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
-configASSERT() is defined to ensure an assertion handler does not inadvertently
-attempt to lower the IPL when the call to assert was triggered because the IPL
-value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
-safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
-those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
-ensure API function and interrupt entry is as fast and as simple as possible. */
-#ifdef configASSERT
-	#define portDISABLE_INTERRUPTS()											\
-	{																			\
-	uint32_t ulStatus;														\
-																				\
-		/* Mask interrupts at and below the kernel interrupt priority. */		\
-		ulStatus = _CP0_GET_STATUS();											\
-																				\
-		/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */	\
-		if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
-		{																		\
-			ulStatus &= ~portALL_IPL_BITS;										\
-			_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
-		}																		\
-	}
-#else /* configASSERT */
-	#define portDISABLE_INTERRUPTS()										\
-	{																		\
-	uint32_t ulStatus;													\
-																			\
-		/* Mask interrupts at and below the kernel interrupt priority. */	\
-		ulStatus = _CP0_GET_STATUS();										\
-		ulStatus &= ~portALL_IPL_BITS;										\
-		_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
-	}
-#endif /* configASSERT */
-
-#define portENABLE_INTERRUPTS()											\
-{																		\
-uint32_t ulStatus;													\
-																		\
-	/* Unmask all interrupts. */										\
-	ulStatus = _CP0_GET_STATUS();										\
-	ulStatus &= ~portALL_IPL_BITS;										\
-	_CP0_SET_STATUS( ulStatus );										\
-}
-
-
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portCRITICAL_NESTING_IN_TCB	1
-#define portENTER_CRITICAL()		vTaskEnterCritical()
-#define portEXIT_CRITICAL()			vTaskExitCritical()
-
-extern UBaseType_t uxPortSetInterruptMaskFromISR();
-extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
-
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
-
-#endif /* taskRECORD_READY_PRIORITY */
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-#define portYIELD()								\
-{												\
-uint32_t ulCause;							\
-												\
-	/* Trigger software interrupt. */			\
-	ulCause = _CP0_GET_CAUSE();					\
-	ulCause |= portSW0_BIT;						\
-	_CP0_SET_CAUSE( ulCause );					\
-}
-
-extern volatile UBaseType_t uxInterruptNesting;
-#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
-
-#define portNOP()	__asm volatile ( "nop" )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired )	\
-													{						\
-														portYIELD();		\
-													}
-
-/* Required by the kernel aware debugger. */
-#ifdef __DEBUG
-	#define portREMOVE_STATIC_QUALIFIER
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/ISR_Support.h b/FreeRTOS/Source/portable/MPLAB/PIC32MZ/ISR_Support.h
deleted file mode 100755
index f078406..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/ISR_Support.h
+++ /dev/null
@@ -1,432 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include "FreeRTOSConfig.h"
-
-#define portCONTEXT_SIZE                160
-#define portEPC_STACK_LOCATION          152
-#define portSTATUS_STACK_LOCATION       156
-#define portFPCSR_STACK_LOCATION        0
-#define portTASK_HAS_FPU_STACK_LOCATION     0
-#define portFPU_CONTEXT_SIZE            264
-
-/******************************************************************/
-.macro  portSAVE_FPU_REGS    offset, base
-    /* Macro to assist with saving just the FPU registers to the
-     * specified address and base offset,
-     * offset is a constant, base is the base pointer register  */
-
-	sdc1		$f31, \offset + 248(\base)
-	sdc1		$f30, \offset + 240(\base)
-	sdc1		$f29, \offset + 232(\base)
-	sdc1		$f28, \offset + 224(\base)
-	sdc1		$f27, \offset + 216(\base)
-	sdc1		$f26, \offset + 208(\base)
-	sdc1		$f25, \offset + 200(\base)
-	sdc1		$f24, \offset + 192(\base)
-	sdc1		$f23, \offset + 184(\base)
-	sdc1		$f22, \offset + 176(\base)
-	sdc1		$f21, \offset + 168(\base)
-	sdc1		$f20, \offset + 160(\base)
-	sdc1		$f19, \offset + 152(\base)
-	sdc1		$f18, \offset + 144(\base)
-	sdc1		$f17, \offset + 136(\base)
-	sdc1		$f16, \offset + 128(\base)
-	sdc1		$f15, \offset + 120(\base)
-	sdc1		$f14, \offset + 112(\base)
-	sdc1		$f13, \offset + 104(\base)
-	sdc1		$f12, \offset + 96(\base)
-	sdc1		$f11, \offset + 88(\base)
-	sdc1		$f10, \offset + 80(\base)
-	sdc1		$f9, \offset + 72(\base)
-	sdc1		$f8, \offset + 64(\base)
-	sdc1		$f7, \offset + 56(\base)
-	sdc1		$f6, \offset + 48(\base)
-	sdc1		$f5, \offset + 40(\base)
-	sdc1		$f4, \offset + 32(\base)
-	sdc1		$f3, \offset + 24(\base)
-	sdc1		$f2, \offset + 16(\base)
-	sdc1		$f1, \offset + 8(\base)
-	sdc1		$f0, \offset + 0(\base)
-
-    .endm
-
-/******************************************************************/
-.macro  portLOAD_FPU_REGS    offset, base
-    /* Macro to assist with loading just the FPU registers from the
-     * specified address and base offset, offset is a constant,
-     * base is the base pointer register  */
-
-	ldc1		$f0, \offset + 0(\base)
-	ldc1		$f1, \offset + 8(\base)
-	ldc1		$f2, \offset + 16(\base)
-	ldc1		$f3, \offset + 24(\base)
-	ldc1		$f4, \offset + 32(\base)
-	ldc1		$f5, \offset + 40(\base)
-	ldc1		$f6, \offset + 48(\base)
-	ldc1		$f7, \offset + 56(\base)
-	ldc1		$f8, \offset + 64(\base)
-	ldc1		$f9, \offset + 72(\base)
-	ldc1		$f10, \offset + 80(\base)
-	ldc1		$f11, \offset + 88(\base)
-	ldc1		$f12, \offset + 96(\base)
-	ldc1		$f13, \offset + 104(\base)
-	ldc1		$f14, \offset + 112(\base)
-	ldc1		$f15, \offset + 120(\base)
-	ldc1		$f16, \offset + 128(\base)
-	ldc1		$f17, \offset + 136(\base)
-	ldc1		$f18, \offset + 144(\base)
-	ldc1		$f19, \offset + 152(\base)
-	ldc1		$f20, \offset + 160(\base)
-	ldc1		$f21, \offset + 168(\base)
-	ldc1		$f22, \offset + 176(\base)
-	ldc1		$f23, \offset + 184(\base)
-	ldc1		$f24, \offset + 192(\base)
-	ldc1		$f25, \offset + 200(\base)
-	ldc1		$f26, \offset + 208(\base)
-	ldc1		$f27, \offset + 216(\base)
-	ldc1		$f28, \offset + 224(\base)
-	ldc1		$f29, \offset + 232(\base)
-	ldc1		$f30, \offset + 240(\base)
-	ldc1		$f31, \offset + 248(\base)
-
-    .endm
-
-/******************************************************************/
-.macro	portSAVE_CONTEXT
-
-	/* Make room for the context. First save the current status so it can be
-	manipulated, and the cause and EPC registers so their original values are
-	captured. */
-	mfc0		k0, _CP0_CAUSE
-	addiu		sp, sp, -portCONTEXT_SIZE
-
-	#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-		/* Test if we are already using the system stack. Only tasks may use the
-		FPU so if we are already in a nested interrupt then the FPU context does
-		not require saving. */
-		la			k1, uxInterruptNesting
-		lw			k1, 0(k1)
-		bne			k1, zero, 2f
-		nop
-
-		/* Test if the current task needs the FPU context saving. */
-		la			k1, ulTaskHasFPUContext
-		lw			k1, 0(k1)
-		beq			k1, zero, 1f
-		nop
-
-		/* Adjust the stack to account for the additional FPU context.*/
-		addiu		sp, sp, -portFPU_CONTEXT_SIZE
-
-	1:
-		/* Save the ulTaskHasFPUContext flag. */
-		sw			k1, portTASK_HAS_FPU_STACK_LOCATION(sp)
-
-	2:
-	#endif
-
-	mfc0		k1, _CP0_STATUS
-
-	/* Also save s7, s6 and s5 so they can be used.  Any nesting interrupts
-	should maintain the values of these registers across the ISR. */
-	sw			s7, 48(sp)
-	sw			s6, 44(sp)
-	sw			s5, 40(sp)
-	sw			k1, portSTATUS_STACK_LOCATION(sp)
-
-	/* Prepare to enable interrupts above the current priority. */
-	srl			k0, k0, 0xa
-	ins 		k1, k0, 10, 7
-	srl			k0, k0, 0x7 /* This copies the MSB of the IPL, but it would be an error if it was set anyway. */
-	ins 		k1, k0, 18, 1
-	ins			k1, zero, 1, 4
-
-	/* s5 is used as the frame pointer. */
-	add			s5, zero, sp
-
-	/* Check the nesting count value. */
-	la			k0, uxInterruptNesting
-	lw			s6, (k0)
-
-	/* If the nesting count is 0 then swap to the the system stack, otherwise
-	the system stack is already being used. */
-	bne			s6, zero, 1f
-	nop
-
-	/* Swap to the system stack. */
-	la			sp, xISRStackTop
-	lw			sp, (sp)
-
-	/* Increment and save the nesting count. */
-1:	addiu		s6, s6, 1
-	sw			s6, 0(k0)
-
-	/* s6 holds the EPC value, this is saved after interrupts are re-enabled. */
-	mfc0 		s6, _CP0_EPC
-
-	/* Re-enable interrupts. */
-	mtc0		k1, _CP0_STATUS
-
-	/* Save the context into the space just created.  s6 is saved again
-	here as it now contains the EPC value.  No other s registers need be
-	saved. */
-	sw			ra, 120(s5)
-	sw			s8, 116(s5)
-	sw			t9, 112(s5)
-	sw			t8, 108(s5)
-	sw			t7, 104(s5)
-	sw			t6, 100(s5)
-	sw			t5, 96(s5)
-	sw			t4, 92(s5)
-	sw			t3, 88(s5)
-	sw			t2, 84(s5)
-	sw			t1, 80(s5)
-	sw			t0, 76(s5)
-	sw			a3, 72(s5)
-	sw			a2, 68(s5)
-	sw			a1, 64(s5)
-	sw			a0, 60(s5)
-	sw			v1, 56(s5)
-	sw			v0, 52(s5)
-	sw			s6, portEPC_STACK_LOCATION(s5)
-	sw			$1, 16(s5)
-
-	/* Save the AC0, AC1, AC2, AC3 registers from the DSP.  s6 is used as a
-	scratch register. */
-	mfhi		s6, $ac1
-	sw			s6, 128(s5)
-	mflo		s6, $ac1
-	sw			s6, 124(s5)
-
-	mfhi		s6, $ac2
-	sw			s6, 136(s5)
-	mflo		s6, $ac2
-	sw			s6, 132(s5)
-
-	mfhi		s6, $ac3
-	sw			s6, 144(s5)
-	mflo		s6, $ac3
-	sw			s6, 140(s5)
-
-	/* Save the DSP Control register */
-	rddsp		s6
-	sw			s6, 148(s5)
-
-	/* ac0 is done separately to match the MX port. */
-	mfhi		s6, $ac0
-	sw			s6, 12(s5)
-	mflo		s6, $ac0
-	sw			s6, 8(s5)
-
-	/* Save the FPU context if the nesting count was zero. */
-	#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-		la			s6, uxInterruptNesting
-		lw			s6, 0(s6)
-		addiu		s6, s6, -1
-		bne			s6, zero, 1f
-		nop
-
-		/* Test if the current task needs the FPU context saving. */
-		lw			s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
-		beq			s6, zero, 1f
-		nop
-
-		/* Save the FPU registers. */
-		portSAVE_FPU_REGS ( portCONTEXT_SIZE + 8 ), s5
-
-		/* Save the FPU status register */
-		cfc1		s6, $f31
-		sw			s6, (portCONTEXT_SIZE + portFPCSR_STACK_LOCATION)(s5)
-
-		1:
-	#endif
-
-	/* Update the task stack pointer value if nesting is zero. */
-	la			s6, uxInterruptNesting
-	lw			s6, (s6)
-	addiu		s6, s6, -1
-	bne			s6, zero, 1f
-	nop
-
-	/* Save the stack pointer. */
-	la			s6, uxSavedTaskStackPointer
-	sw			s5, (s6)
-1:
-	.endm
-
-/******************************************************************/
-.macro	portRESTORE_CONTEXT
-
-	/* Restore the stack pointer from the TCB.  This is only done if the
-	nesting count is 1. */
-	la			s6, uxInterruptNesting
-	lw			s6, (s6)
-	addiu		s6, s6, -1
-	bne			s6, zero, 1f
-	nop
-	la			s6, uxSavedTaskStackPointer
-	lw			s5, (s6)
-
-    #if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-		/* Restore the FPU context if required. */
-		lw			s6, portTASK_HAS_FPU_STACK_LOCATION(s5)
-		beq			s6, zero, 1f
-		nop
-
-		/* Restore the FPU registers. */
-		portLOAD_FPU_REGS   ( portCONTEXT_SIZE + 8 ), s5
-
-		/* Restore the FPU status register. */
-		lw			s6, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
-		ctc1		s6, $f31
-   	#endif
-
-1:
-
-	/* Restore the context. */
-	lw			s6, 128(s5)
-	mthi		s6, $ac1
-	lw			s6, 124(s5)
-	mtlo		s6, $ac1
-
-	lw			s6, 136(s5)
-	mthi		s6, $ac2
-	lw			s6, 132(s5)
-	mtlo		s6, $ac2
-
-	lw			s6, 144(s5)
-	mthi		s6, $ac3
-	lw			s6, 140(s5)
-	mtlo		s6, $ac3
-
-	/* Restore DSPControl. */
-	lw			s6, 148(s5)
-	wrdsp		s6
-
-	lw			s6, 8(s5)
-	mtlo		s6, $ac0
-	lw			s6, 12(s5)
-	mthi		s6, $ac0
-	lw			$1, 16(s5)
-
-	/* s6 is loaded as it was used as a scratch register and therefore saved
-	as part of the interrupt context. */
-	lw			s7, 48(s5)
-	lw			s6, 44(s5)
-	lw			v0, 52(s5)
-	lw			v1, 56(s5)
-	lw			a0, 60(s5)
-	lw			a1, 64(s5)
-	lw			a2, 68(s5)
-	lw			a3, 72(s5)
-	lw			t0, 76(s5)
-	lw			t1, 80(s5)
-	lw			t2, 84(s5)
-	lw			t3, 88(s5)
-	lw			t4, 92(s5)
-	lw			t5, 96(s5)
-	lw			t6, 100(s5)
-	lw			t7, 104(s5)
-	lw			t8, 108(s5)
-	lw			t9, 112(s5)
-	lw			s8, 116(s5)
-	lw			ra, 120(s5)
-
-	/* Protect access to the k registers, and others. */
-	di
-	ehb
-
-	/* Decrement the nesting count. */
-	la			k0, uxInterruptNesting
-	lw			k1, (k0)
-	addiu		k1, k1, -1
-	sw			k1, 0(k0)
-
-	#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-		/* If the nesting count is now zero then the FPU context may be restored. */
-		bne			k1, zero, 1f
-		nop
-
-		/* Restore the value of ulTaskHasFPUContext */
-		la			k0, ulTaskHasFPUContext
-		lw			k1, 0(s5)
-		sw			k1, 0(k0)
-
-		/* If the task does not have an FPU context then adjust the stack normally. */
-		beq			k1, zero, 1f
-		nop
-
-		/* Restore the STATUS and EPC registers */
-		lw			k0, portSTATUS_STACK_LOCATION(s5)
-		lw			k1, portEPC_STACK_LOCATION(s5)
-
-		/* Leave the stack in its original state.  First load sp from s5, then
-		restore s5 from the stack. */
-		add			sp, zero, s5
-		lw			s5, 40(sp)
-
-		/* Adjust the stack pointer to remove the FPU context */
-		addiu		sp, sp,	portFPU_CONTEXT_SIZE
-		beq			zero, zero, 2f
-		nop
-
-		1:  /* Restore the STATUS and EPC registers */
-		lw			k0, portSTATUS_STACK_LOCATION(s5)
-		lw			k1, portEPC_STACK_LOCATION(s5)
-
-		/* Leave the stack in its original state.  First load sp from s5, then
-		restore s5 from the stack. */
-		add			sp, zero, s5
-		lw			s5, 40(sp)
-
-		2:  /* Adjust the stack pointer */
-		addiu		sp, sp, portCONTEXT_SIZE
-
-	#else
-
-		/* Restore the frame when there is no hardware FP support. */
-		lw			k0, portSTATUS_STACK_LOCATION(s5)
-		lw			k1, portEPC_STACK_LOCATION(s5)
-
-		/* Leave the stack in its original state.  First load sp from s5, then
-		restore s5 from the stack. */
-		add			sp, zero, s5
-		lw			s5, 40(sp)
-
-		addiu		sp, sp,	portCONTEXT_SIZE
-
-	#endif // ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-
-	mtc0		k0, _CP0_STATUS
-	mtc0 		k1, _CP0_EPC
-	ehb
-	eret
-	nop
-
-	.endm
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port.c b/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port.c
deleted file mode 100755
index b5c0f93..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port.c
+++ /dev/null
@@ -1,372 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the PIC32MZ port.
-  *----------------------------------------------------------*/
-
-/* Microchip specific headers. */
-#include 
-
-/* Standard headers. */
-#include 
-
-/* Scheduler include files. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#if !defined(__PIC32MZ__)
-    #error This port is designed to work with XC32 on PIC32MZ MCUs.  Please update your C compiler version or settings.
-#endif
-
-#if( ( configMAX_SYSCALL_INTERRUPT_PRIORITY >= 0x7 ) || ( configMAX_SYSCALL_INTERRUPT_PRIORITY == 0 ) )
-	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must be less than 7 and greater than 0
-#endif
-
-/* Hardware specifics. */
-#define portTIMER_PRESCALE	8
-#define portPRESCALE_BITS	1
-
-/* Bits within various registers. */
-#define portIE_BIT					( 0x00000001 )
-#define portEXL_BIT					( 0x00000002 )
-#define portMX_BIT					( 0x01000000 ) /* Allow access to DSP instructions. */
-#define portCU1_BIT					( 0x20000000 ) /* enable CP1 for parts with hardware. */
-#define portFR_BIT					( 0x04000000 ) /* Enable 64 bit floating point registers. */
-
-/* Bits within the CAUSE register. */
-#define portCORE_SW_0				( 0x00000100 )
-#define portCORE_SW_1				( 0x00000200 )
-
-/* The EXL bit is set to ensure interrupts do not occur while the context of
-the first task is being restored. */
-#if ( __mips_hard_float == 1 )
-    #define portINITIAL_SR			( portIE_BIT | portEXL_BIT | portMX_BIT | portFR_BIT | portCU1_BIT )
-#else
-    #define portINITIAL_SR			( portIE_BIT | portEXL_BIT | portMX_BIT )
-#endif
-
-/* The initial value to store into the FPU status and control register. This is
- only used on parts that support a hardware FPU. */
-#define portINITIAL_FPSCR			(0x1000000) /* High perf on denormal ops */
-
-
-/*
-By default port.c generates its tick interrupt from TIMER1.  The user can
-override this behaviour by:
-	1: Providing their own implementation of vApplicationSetupTickTimerInterrupt(),
-	   which is the function that configures the timer.  The function is defined
-	   as a weak symbol in this file so if the same function name is used in the
-	   application code then the version in the application code will be linked
-	   into the application in preference to the version defined in this file.
-	2: Define configTICK_INTERRUPT_VECTOR to the vector number of the timer used
-	   to generate the tick interrupt.  For example, when timer 1 is used then
-	   configTICK_INTERRUPT_VECTOR is set to _TIMER_1_VECTOR.
-	   configTICK_INTERRUPT_VECTOR should be defined in FreeRTOSConfig.h.
-	3: Define configCLEAR_TICK_TIMER_INTERRUPT() to clear the interrupt in the
-	   timer used to generate the tick interrupt.  For example, when timer 1 is
-	   used configCLEAR_TICK_TIMER_INTERRUPT() is defined to
-	   IFS0CLR = _IFS0_T1IF_MASK.
-*/
-#ifndef configTICK_INTERRUPT_VECTOR
-	#define configTICK_INTERRUPT_VECTOR _TIMER_1_VECTOR
-	#define configCLEAR_TICK_TIMER_INTERRUPT() IFS0CLR = _IFS0_T1IF_MASK
-#else
-	#ifndef configCLEAR_TICK_TIMER_INTERRUPT
-		#error If configTICK_INTERRUPT_VECTOR is defined in application code then configCLEAR_TICK_TIMER_INTERRUPT must also be defined in application code.
-	#endif
-#endif
-
-/* Let the user override the pre-loading of the initial RA with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger - in which case configTASK_RETURN_ADDRESS can be defined as 0 (NULL). */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/* Set configCHECK_FOR_STACK_OVERFLOW to 3 to add ISR stack checking to task
-stack checking.  A problem in the ISR stack will trigger an assert, not call the
-stack overflow hook function (because the stack overflow hook is specific to a
-task stack, not the ISR stack). */
-#if( configCHECK_FOR_STACK_OVERFLOW > 2 )
-
-	/* Don't use 0xa5 as the stack fill bytes as that is used by the kernerl for
-	the task stacks, and so will legitimately appear in many positions within
-	the ISR stack. */
-	#define portISR_STACK_FILL_BYTE	0xee
-
-	static const uint8_t ucExpectedStackBytes[] = {
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE,		\
-									portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE, portISR_STACK_FILL_BYTE };	\
-
-	#define portCHECK_ISR_STACK() configASSERT( ( memcmp( ( void * ) xISRStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) == 0 ) )
-#else
-	/* Define the function away. */
-	#define portCHECK_ISR_STACK()
-#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
-
-/*-----------------------------------------------------------*/
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Records the interrupt nesting depth.  This is initialised to one as it is
-decremented to 0 when the first task starts. */
-volatile UBaseType_t uxInterruptNesting = 0x01;
-
-/* Stores the task stack pointer when a switch is made to use the system stack. */
-UBaseType_t uxSavedTaskStackPointer = 0;
-
-/* The stack used by interrupt service routines that cause a context switch. */
-__attribute__ ((aligned(8))) StackType_t xISRStack[ configISR_STACK_SIZE ] = { 0 };
-
-/* The top of stack value ensures there is enough space to store 6 registers on
-the callers stack, as some functions seem to want to do this.  8 byte alignment
-is required to allow double word floating point stack pushes generated by the
-compiler. */
-const StackType_t * const xISRStackTop = &( xISRStack[ ( configISR_STACK_SIZE & ~portBYTE_ALIGNMENT_MASK ) - 8 ] );
-
-/* Saved as part of the task context. Set to pdFALSE if the task does not
- require an FPU context. */
-#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-	uint32_t ulTaskHasFPUContext = 0;
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Ensure 8 byte alignment is maintained when leaving this function. */
-	pxTopOfStack--;
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) 0xDEADBEEF;
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) 0x12345678;	/* Word to which the stack pointer will be left pointing after context restore. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) _CP0_GET_CAUSE();
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) portINITIAL_SR;/* CP0_STATUS */
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) pxCode; 		/* CP0_EPC */
-	pxTopOfStack--;
-
-	*pxTopOfStack = (StackType_t) 0x00000000;	/* DSPControl */
-	pxTopOfStack -= 7;  						/* Includes space for AC1 - AC3. */
-
-	*pxTopOfStack = (StackType_t) portTASK_RETURN_ADDRESS;	/* ra */
-	pxTopOfStack -= 15;
-
-	*pxTopOfStack = (StackType_t) pvParameters; /* Parameters to pass in. */
-	pxTopOfStack -= 15;
-
-	*pxTopOfStack = (StackType_t) pdFALSE; /*by default disable FPU context save on parts with FPU */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxSavedTaskStackPointer == 0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup a timer for a regular tick.  This function uses peripheral timer 1.
- * The function is declared weak so an application writer can use a different
- * timer by redefining this implementation.  If a different timer is used then
- * configTICK_INTERRUPT_VECTOR must also be defined in FreeRTOSConfig.h to
- * ensure the RTOS provided tick interrupt handler is installed on the correct
- * vector number.  When Timer 1 is used the vector number is defined as
- * _TIMER_1_VECTOR.
- */
-__attribute__(( weak )) void vApplicationSetupTickTimerInterrupt( void )
-{
-const uint32_t ulCompareMatch = ( (configPERIPHERAL_CLOCK_HZ / portTIMER_PRESCALE) / configTICK_RATE_HZ ) - 1UL;
-
-	T1CON = 0x0000;
-	T1CONbits.TCKPS = portPRESCALE_BITS;
-	PR1 = ulCompareMatch;
-	IPC1bits.T1IP = configKERNEL_INTERRUPT_PRIORITY;
-
-	/* Clear the interrupt as a starting condition. */
-	IFS0bits.T1IF = 0;
-
-	/* Enable the interrupt. */
-	IEC0bits.T1IE = 1;
-
-	/* Start the timer. */
-	T1CONbits.TON = 1;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler(void)
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxInterruptNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vPortStartFirstTask( void );
-extern void *pxCurrentTCB;
-
-	#if ( configCHECK_FOR_STACK_OVERFLOW > 2 )
-	{
-		/* Fill the ISR stack to make it easy to asses how much is being used. */
-		memset( ( void * ) xISRStack, portISR_STACK_FILL_BYTE, sizeof( xISRStack ) );
-	}
-	#endif /* configCHECK_FOR_STACK_OVERFLOW > 2 */
-
-	/* Clear the software interrupt flag. */
-	IFS0CLR = _IFS0_CS0IF_MASK;
-
-	/* Set software timer priority. */
-	IPC0CLR = _IPC0_CS0IP_MASK;
-	IPC0SET = ( configKERNEL_INTERRUPT_PRIORITY << _IPC0_CS0IP_POSITION );
-
-	/* Enable software interrupt. */
-	IEC0CLR = _IEC0_CS0IE_MASK;
-	IEC0SET = 1 << _IEC0_CS0IE_POSITION;
-
-	/* Setup the timer to generate the tick.  Interrupts will have been
-	disabled by the time we get here. */
-	vApplicationSetupTickTimerInterrupt();
-
-	/* Kick off the highest priority task that has been created so far.
-	Its stack location is loaded into uxSavedTaskStackPointer. */
-	uxSavedTaskStackPointer = *( UBaseType_t * ) pxCurrentTCB;
-	vPortStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing!  Call the task
-	exit error function to prevent compiler warnings about a static function
-	not being called in the case that the application writer overrides this
-	functionality by defining configTASK_RETURN_ADDRESS. */
-	prvTaskExitError();
-
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortIncrementTick( void )
-{
-UBaseType_t uxSavedStatus;
-
-	uxSavedStatus = uxPortSetInterruptMaskFromISR();
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			_CP0_BIS_CAUSE( portCORE_SW_0 );
-		}
-	}
-	vPortClearInterruptMaskFromISR( uxSavedStatus );
-
-	/* Look for the ISR stack getting near or past its limit. */
-	portCHECK_ISR_STACK();
-
-	/* Clear timer interrupt. */
-	configCLEAR_TICK_TIMER_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxPortSetInterruptMaskFromISR( void )
-{
-UBaseType_t uxSavedStatusRegister;
-
-	__builtin_disable_interrupts();
-	uxSavedStatusRegister = _CP0_GET_STATUS() | 0x01;
-	/* This clears the IPL bits, then sets them to
-	configMAX_SYSCALL_INTERRUPT_PRIORITY.  This function should not be called
-	from an interrupt that has a priority above
-	configMAX_SYSCALL_INTERRUPT_PRIORITY so, when used correctly, the action
-	can only result in the IPL being unchanged or raised, and therefore never
-	lowered. */
-	_CP0_SET_STATUS( ( ( uxSavedStatusRegister & ( ~portALL_IPL_BITS ) ) ) | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) );
-
-	return uxSavedStatusRegister;
-}
-/*-----------------------------------------------------------*/
-
-void vPortClearInterruptMaskFromISR( UBaseType_t uxSavedStatusRegister )
-{
-	_CP0_SET_STATUS( uxSavedStatusRegister );
-}
-/*-----------------------------------------------------------*/
-
-#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-
-	void vPortTaskUsesFPU(void)
-	{
-	extern void vPortInitialiseFPSCR( uint32_t uxFPSCRInit );
-
-		portENTER_CRITICAL();
-
-		/* Initialise the floating point status register. */
-		vPortInitialiseFPSCR(portINITIAL_FPSCR);
-
-		/* A task is registering the fact that it needs a FPU context. Set the
-		FPU flag (saved as part of the task context). */
-		ulTaskHasFPUContext = pdTRUE;
-
-		portEXIT_CRITICAL();
-	}
-
-#endif /* __mips_hard_float == 1 */
-
-/*-----------------------------------------------------------*/
-
-
-
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S b/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S
deleted file mode 100755
index 43be67d..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/port_asm.S
+++ /dev/null
@@ -1,768 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include 
-#include 
-#include "FreeRTOSConfig.h"
-#include "ISR_Support.h"
-
-	.extern pxCurrentTCB
-	.extern vTaskSwitchContext
-	.extern vPortIncrementTick
-	.extern xISRStackTop
-	.extern ulTaskHasFPUContext
-
-	.global vPortStartFirstTask
-	.global vPortYieldISR
-	.global vPortTickInterruptHandler
-	.global vPortInitialiseFPSCR
-
-
-/******************************************************************/
-
-	.set  nomips16
-	.set  nomicromips
-	.set  noreorder
-	.set  noat
-
-	/***************************************************************
-	*  The following is needed to locate the
-	*  vPortTickInterruptHandler function into the correct vector
-	***************************************************************/
-	#ifdef configTICK_INTERRUPT_VECTOR
-		#if (configTICK_INTERRUPT_VECTOR == _CORE_TIMER_VECTOR)
-			.equ     __vector_dispatch_0, vPortTickInterruptHandler
-			.global  __vector_dispatch_0
-			.section .vector_0, code, keep
-		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_1_VECTOR)
-			.equ     __vector_dispatch_4, vPortTickInterruptHandler
-			.global  __vector_dispatch_4
-			.section .vector_4, code, keep
-		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_2_VECTOR)
-			.equ     __vector_dispatch_9, vPortTickInterruptHandler
-			.global  __vector_dispatch_9
-			.section .vector_9, code, keep
-		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_3_VECTOR)
-			.equ     __vector_dispatch_14, vPortTickInterruptHandler
-			.global  __vector_dispatch_14
-			.section .vector_14, code, keep
-		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_4_VECTOR)
-			.equ     __vector_dispatch_19, vPortTickInterruptHandler
-			.global  __vector_dispatch_19
-			.section .vector_19, code, keep
-		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_5_VECTOR)
-			.equ     __vector_dispatch_24, vPortTickInterruptHandler
-			.global  __vector_dispatch_24
-			.section .vector_24, code, keep
-		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_6_VECTOR)
-			.equ     __vector_dispatch_28, vPortTickInterruptHandler
-			.global  __vector_dispatch_28
-			.section .vector_28, code, keep
-		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_7_VECTOR)
-			.equ     __vector_dispatch_32, vPortTickInterruptHandler
-			.global  __vector_dispatch_32
-			.section .vector_32, code, keep
-		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_8_VECTOR)
-			.equ     __vector_dispatch_36, vPortTickInterruptHandler
-			.global  __vector_dispatch_36
-			.section .vector_36, code, keep
-		#elif (configTICK_INTERRUPT_VECTOR == _TIMER_9_VECTOR)
-			.equ     __vector_dispatch_40, vPortTickInterruptHandler
-			.global  __vector_dispatch_40
-			.section .vector_40, code, keep
-		#endif
-	#else
-		.equ     __vector_dispatch_4, vPortTickInterruptHandler
-		.global  __vector_dispatch_4
-		.section .vector_4, code, keep
-	#endif
-
-	.ent		vPortTickInterruptHandler
-
-vPortTickInterruptHandler:
-
-	portSAVE_CONTEXT
-
-	jal 		vPortIncrementTick
-	nop
-
-	portRESTORE_CONTEXT
-
-	.end vPortTickInterruptHandler
-
-/******************************************************************/
-
-	.set		noreorder
-	.set 		noat
-	.section .text, code
-	.ent		vPortStartFirstTask
-
-vPortStartFirstTask:
-
-	/* Simply restore the context of the highest priority task that has been
-	created so far. */
-	portRESTORE_CONTEXT
-
-	.end vPortStartFirstTask
-
-
-
-/*******************************************************************/
-
-	.set  nomips16
-	.set  nomicromips
-	.set  noreorder
-	.set  noat
-	/***************************************************************
-	*  The following is needed to locate the vPortYieldISR function
-	*  into the correct vector
-	***************************************************************/
-	.equ     __vector_dispatch_1, vPortYieldISR
-	.global  __vector_dispatch_1
-	.section .vector_1, code
-
-	.ent  vPortYieldISR
-vPortYieldISR:
-
-	#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-		/* Code sequence for FPU support, the context save requires advance
-		knowledge of the stack frame size and if the current task actually uses the 
-		FPU. */
-
-		/* Make room for the context. First save the current status so it can be
-		manipulated, and the cause and EPC registers so their original values are
-		captured. */
-		la		k0, ulTaskHasFPUContext
-		lw		k0, 0(k0)
-		beq		k0, zero, 1f
-		addiu	sp, sp, -portCONTEXT_SIZE	/* always reserve space for the context. */
-		addiu	sp, sp, -portFPU_CONTEXT_SIZE	/* reserve additional space for the FPU context. */
-	1:
-		mfc0	k1, _CP0_STATUS
-
-		/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
-		maintain the values of these registers across the ISR. */
-		sw		s6, 44(sp)
-		sw		s5, 40(sp)
-		sw		k1, portSTATUS_STACK_LOCATION(sp)
-		sw		k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
-
-		/* Prepare to re-enabled interrupts above the kernel priority. */
-		ins 	k1, zero, 10, 7         /* Clear IPL bits 0:6. */
-		ins 	k1, zero, 18, 1         /* Clear IPL bit 7.  It would be an error here if this bit were set anyway. */
-		ori		k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
-		ins		k1, zero, 1, 4          /* Clear EXL, ERL and UM. */
-
-		/* s5 is used as the frame pointer. */
-		add		s5, zero, sp
-
-		/* Swap to the system stack.  This is not conditional on the nesting
-		count as this interrupt is always the lowest priority and therefore
-		the nesting is always 0. */
-		la		sp, xISRStackTop
-		lw		sp, (sp)
-
-		/* Set the nesting count. */
-		la		k0, uxInterruptNesting
-		addiu	s6, zero, 1
-		sw		s6, 0(k0)
-
-		/* s6 holds the EPC value, this is saved with the rest of the context
-		after interrupts are enabled. */
-		mfc0 	s6, _CP0_EPC
-
-		/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-		mtc0	k1, _CP0_STATUS
-
-		/* Save the context into the space just created.  s6 is saved again
-		here as it now contains the EPC value. */
-		sw		ra, 120(s5)
-		sw		s8, 116(s5)
-		sw		t9, 112(s5)
-		sw		t8, 108(s5)
-		sw		t7, 104(s5)
-		sw		t6, 100(s5)
-		sw		t5, 96(s5)
-		sw		t4, 92(s5)
-		sw		t3, 88(s5)
-		sw		t2, 84(s5)
-		sw		t1, 80(s5)
-		sw		t0, 76(s5)
-		sw		a3, 72(s5)
-		sw		a2, 68(s5)
-		sw		a1, 64(s5)
-		sw		a0, 60(s5)
-		sw		v1, 56(s5)
-		sw		v0, 52(s5)
-		sw		s7, 48(s5)
-		sw		s6, portEPC_STACK_LOCATION(s5)
-		/* s5 and s6 has already been saved. */
-		sw		s4, 36(s5)
-		sw		s3, 32(s5)
-		sw		s2, 28(s5)
-		sw		s1, 24(s5)
-		sw		s0, 20(s5)
-		sw		$1, 16(s5)
-
-		/* s7 is used as a scratch register as this should always be saved across
-		nesting interrupts. */
-
-		/* Save the AC0, AC1, AC2 and AC3. */
-		mfhi	s7, $ac1
-		sw		s7, 128(s5)
-		mflo	s7, $ac1
-		sw		s7, 124(s5)
-
-		mfhi	s7, $ac2
-		sw		s7, 136(s5)
-		mflo	s7, $ac2
-		sw		s7, 132(s5)
-
-		mfhi	s7, $ac3
-		sw		s7, 144(s5)
-		mflo	s7, $ac3
-		sw		s7, 140(s5)
-
-		rddsp	s7
-		sw		s7, 148(s5)
-
-		mfhi	s7, $ac0
-		sw		s7, 12(s5)
-		mflo	s7, $ac0
-		sw		s7, 8(s5)
-
-		/* Test if FPU context save is required. */
-		lw		s7, portTASK_HAS_FPU_STACK_LOCATION(s5)
-		beq		s7, zero, 1f
-		nop
-
-		/* Save the FPU registers above the normal context. */
-		portSAVE_FPU_REGS   (portCONTEXT_SIZE + 8), s5
-
-		/* Save the FPU status register */
-		cfc1	s7, $f31
-		sw		s7, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
-
-	1:
-		/* Save the stack pointer to the task. */
-		la		s7, pxCurrentTCB
-		lw		s7, (s7)
-		sw		s5, (s7)
-
-		/* Set the interrupt mask to the max priority that can use the API.  The
-		yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
-		is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
-		raise the IPL value and never lower it. */
-		di
-		ehb
-		mfc0	s7, _CP0_STATUS
-		ins 	s7, zero, 10, 7
-		ins 	s7, zero, 18, 1
-		ori		s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
-
-		/* This mtc0 re-enables interrupts, but only above
-		configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-		mtc0	s6, _CP0_STATUS
-		ehb
-
-		/* Clear the software interrupt in the core. */
-		mfc0	s6, _CP0_CAUSE
-		ins		s6, zero, 8, 1
-		mtc0	s6, _CP0_CAUSE
-		ehb
-
-		/* Clear the interrupt in the interrupt controller. */
-		la		s6, IFS0CLR
-		addiu	s4, zero, 2
-		sw		s4, (s6)
-
-		jal		vTaskSwitchContext
-		nop
-
-		/* Clear the interrupt mask again.  The saved status value is still in s7. */
-		mtc0	s7, _CP0_STATUS
-		ehb
-
-		/* Restore the stack pointer from the TCB. */
-		la		s0, pxCurrentTCB
-		lw		s0, (s0)
-		lw		s5, (s0)
-
-		/* Test if the FPU context needs restoring. */
-		lw		s0, portTASK_HAS_FPU_STACK_LOCATION(s5)
-		beq		s0, zero, 1f
-		nop
-
-		/* Restore the FPU status register. */
-		lw		s0, ( portCONTEXT_SIZE + portFPCSR_STACK_LOCATION )(s5)
-		ctc1	s0, $f31
-
-		/* Restore the FPU registers. */
-		portLOAD_FPU_REGS   ( portCONTEXT_SIZE + 8 ), s5
-
-	1:
-		/* Restore the rest of the context. */
-		lw		s0, 128(s5)
-		mthi	s0, $ac1
-		lw		s0, 124(s5)
-		mtlo		s0, $ac1
-
-		lw		s0, 136(s5)
-		mthi	s0, $ac2
-		lw		s0, 132(s5)
-		mtlo	s0, $ac2
-
-		lw		s0, 144(s5)
-		mthi	s0, $ac3
-		lw		s0, 140(s5)
-		mtlo	s0, $ac3
-
-		lw		s0, 148(s5)
-		wrdsp	s0
-
-		lw		s0, 8(s5)
-		mtlo	s0, $ac0
-		lw		s0, 12(s5)
-		mthi	s0, $ac0
-
-		lw		$1, 16(s5)
-		lw		s0, 20(s5)
-		lw		s1, 24(s5)
-		lw		s2, 28(s5)
-		lw		s3, 32(s5)
-		lw		s4, 36(s5)
-
-		/* s5 is loaded later. */
-		lw		s6, 44(s5)
-		lw		s7, 48(s5)
-		lw		v0, 52(s5)
-		lw		v1, 56(s5)
-		lw		a0, 60(s5)
-		lw		a1, 64(s5)
-		lw		a2, 68(s5)
-		lw		a3, 72(s5)
-		lw		t0, 76(s5)
-		lw		t1, 80(s5)
-		lw		t2, 84(s5)
-		lw		t3, 88(s5)
-		lw		t4, 92(s5)
-		lw		t5, 96(s5)
-		lw		t6, 100(s5)
-		lw		t7, 104(s5)
-		lw		t8, 108(s5)
-		lw		t9, 112(s5)
-		lw		s8, 116(s5)
-		lw		ra, 120(s5)
-
-		/* Protect access to the k registers, and others. */
-		di
-		ehb
-
-		/* Set nesting back to zero.  As the lowest priority interrupt this
-		interrupt cannot have nested. */
-		la		k0, uxInterruptNesting
-		sw		zero, 0(k0)
-
-		/* Switch back to use the real stack pointer. */
-		add		sp, zero, s5
-
-		/* Restore the real s5 value. */
-		lw		s5, 40(sp)
-
-		/* Pop the FPU context value from the stack */
-		lw		k0, portTASK_HAS_FPU_STACK_LOCATION(sp)
-		la		k1, ulTaskHasFPUContext
-		sw		k0, 0(k1)
-		beq		k0, zero, 1f
-		nop
-
-		/* task has FPU context so adjust the stack frame after popping the
-		status and epc values. */
-		lw		k1, portSTATUS_STACK_LOCATION(sp)
-		lw		k0, portEPC_STACK_LOCATION(sp)
-		addiu	sp, sp, portFPU_CONTEXT_SIZE
-		beq		zero, zero, 2f
-		nop
-
-	1:
-		/* Pop the status and epc values. */
-		lw		k1, portSTATUS_STACK_LOCATION(sp)
-		lw		k0, portEPC_STACK_LOCATION(sp)
-
-	2:
-		/* Remove stack frame. */
-		addiu	sp, sp, portCONTEXT_SIZE
-
-	#else
-		/* Code sequence for no FPU support, the context save requires advance
-		knowledge of the stack frame size when no FPU is being used */
-
-		/* Make room for the context. First save the current status so it can be
-		manipulated, and the cause and EPC registers so thier original values are
-		captured. */
-		addiu	sp, sp, -portCONTEXT_SIZE
-		mfc0	k1, _CP0_STATUS
-
-		/* Also save s6 and s5 so they can be used.  Any nesting interrupts should
-		maintain the values of these registers across the ISR. */
-		sw		s6, 44(sp)
-		sw		s5, 40(sp)
-		sw		k1, portSTATUS_STACK_LOCATION(sp)
-
-		/* Prepare to re-enabled interrupts above the kernel priority. */
-		ins 	k1, zero, 10, 7         /* Clear IPL bits 0:6. */
-		ins 	k1, zero, 18, 1         /* Clear IPL bit 7.  It would be an error here if this bit were set anyway. */
-		ori		k1, k1, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 )
-		ins		k1, zero, 1, 4          /* Clear EXL, ERL and UM. */
-
-		/* s5 is used as the frame pointer. */
-		add		s5, zero, sp
-
-		/* Swap to the system stack.  This is not conditional on the nesting
-		count as this interrupt is always the lowest priority and therefore
-		the nesting is always 0. */
-		la		sp, xISRStackTop
-		lw		sp, (sp)
-
-		/* Set the nesting count. */
-		la		k0, uxInterruptNesting
-		addiu	s6, zero, 1
-		sw		s6, 0(k0)
-
-		/* s6 holds the EPC value, this is saved with the rest of the context
-		after interrupts are enabled. */
-		mfc0 	s6, _CP0_EPC
-
-		/* Re-enable interrupts above configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-		mtc0	k1, _CP0_STATUS
-
-		/* Save the context into the space just created.  s6 is saved again
-		here as it now contains the EPC value. */
-		sw		ra, 120(s5)
-		sw		s8, 116(s5)
-		sw		t9, 112(s5)
-		sw		t8, 108(s5)
-		sw		t7, 104(s5)
-		sw		t6, 100(s5)
-		sw		t5, 96(s5)
-		sw		t4, 92(s5)
-		sw		t3, 88(s5)
-		sw		t2, 84(s5)
-		sw		t1, 80(s5)
-		sw		t0, 76(s5)
-		sw		a3, 72(s5)
-		sw		a2, 68(s5)
-		sw		a1, 64(s5)
-		sw		a0, 60(s5)
-		sw		v1, 56(s5)
-		sw		v0, 52(s5)
-		sw		s7, 48(s5)
-		sw		s6, portEPC_STACK_LOCATION(s5)
-		/* s5 and s6 has already been saved. */
-		sw		s4, 36(s5)
-		sw		s3, 32(s5)
-		sw		s2, 28(s5)
-		sw		s1, 24(s5)
-		sw		s0, 20(s5)
-		sw		$1, 16(s5)
-
-		/* s7 is used as a scratch register as this should always be saved across
-		nesting interrupts. */
-
-		/* Save the AC0, AC1, AC2 and AC3. */
-		mfhi	s7, $ac1
-		sw		s7, 128(s5)
-		mflo	s7, $ac1
-		sw		s7, 124(s5)
-
-		mfhi	s7, $ac2
-		sw		s7, 136(s5)
-		mflo	s7, $ac2
-		sw		s7, 132(s5)
-
-		mfhi	s7, $ac3
-		sw		s7, 144(s5)
-		mflo	s7, $ac3
-		sw		s7, 140(s5)
-
-		rddsp	s7
-		sw		s7, 148(s5)
-
-		mfhi	s7, $ac0
-		sw		s7, 12(s5)
-		mflo	s7, $ac0
-		sw		s7, 8(s5)
-
-		/* Save the stack pointer to the task. */
-		la		s7, pxCurrentTCB
-		lw		s7, (s7)
-		sw		s5, (s7)
-
-		/* Set the interrupt mask to the max priority that can use the API.  The
-		yield handler will only be called at configKERNEL_INTERRUPT_PRIORITY which
-		is below configMAX_SYSCALL_INTERRUPT_PRIORITY - so this can only ever
-		raise the IPL value and never lower it. */
-		di
-		ehb
-		mfc0	s7, _CP0_STATUS
-		ins 	s7, zero, 10, 7
-		ins 	s7, zero, 18, 1
-		ori		s6, s7, ( configMAX_SYSCALL_INTERRUPT_PRIORITY << 10 ) | 1
-
-		/* This mtc0 re-enables interrupts, but only above
-		configMAX_SYSCALL_INTERRUPT_PRIORITY. */
-		mtc0	s6, _CP0_STATUS
-		ehb
-
-		/* Clear the software interrupt in the core. */
-		mfc0	s6, _CP0_CAUSE
-		ins		s6, zero, 8, 1
-		mtc0	s6, _CP0_CAUSE
-		ehb
-
-		/* Clear the interrupt in the interrupt controller. */
-		la		s6, IFS0CLR
-		addiu	s4, zero, 2
-		sw		s4, (s6)
-
-		jal		vTaskSwitchContext
-		nop
-
-		/* Clear the interrupt mask again.  The saved status value is still in s7. */
-		mtc0	s7, _CP0_STATUS
-		ehb
-
-		/* Restore the stack pointer from the TCB. */
-		la		s0, pxCurrentTCB
-		lw		s0, (s0)
-		lw		s5, (s0)
-
-		/* Restore the rest of the context. */
-		lw		s0, 128(s5)
-		mthi	s0, $ac1
-		lw		s0, 124(s5)
-		mtlo	s0, $ac1
-
-		lw		s0, 136(s5)
-		mthi	s0, $ac2
-		lw		s0, 132(s5)
-		mtlo	s0, $ac2
-
-		lw		s0, 144(s5)
-		mthi	s0, $ac3
-		lw		s0, 140(s5)
-		mtlo	s0, $ac3
-
-		lw		s0, 148(s5)
-		wrdsp	s0
-
-		lw		s0, 8(s5)
-		mtlo	s0, $ac0
-		lw		s0, 12(s5)
-		mthi	s0, $ac0
-
-		lw		$1, 16(s5)
-		lw		s0, 20(s5)
-		lw		s1, 24(s5)
-		lw		s2, 28(s5)
-		lw		s3, 32(s5)
-		lw		s4, 36(s5)
-
-		/* s5 is loaded later. */
-		lw		s6, 44(s5)
-		lw		s7, 48(s5)
-		lw		v0, 52(s5)
-		lw		v1, 56(s5)
-		lw		a0, 60(s5)
-		lw		a1, 64(s5)
-		lw		a2, 68(s5)
-		lw		a3, 72(s5)
-		lw		t0, 76(s5)
-		lw		t1, 80(s5)
-		lw		t2, 84(s5)
-		lw		t3, 88(s5)
-		lw		t4, 92(s5)
-		lw		t5, 96(s5)
-		lw		t6, 100(s5)
-		lw		t7, 104(s5)
-		lw		t8, 108(s5)
-		lw		t9, 112(s5)
-		lw		s8, 116(s5)
-		lw		ra, 120(s5)
-
-		/* Protect access to the k registers, and others. */
-		di
-		ehb
-
-		/* Set nesting back to zero.  As the lowest priority interrupt this
-		interrupt cannot have nested. */
-		la		k0, uxInterruptNesting
-		sw		zero, 0(k0)
-
-		/* Switch back to use the real stack pointer. */
-		add		sp, zero, s5
-
-		/* Restore the real s5 value. */
-		lw		s5, 40(sp)
-
-		/* Pop the status and epc values. */
-		lw		k1, portSTATUS_STACK_LOCATION(sp)
-		lw		k0, portEPC_STACK_LOCATION(sp)
-
-		/* Remove stack frame. */
-		addiu	sp, sp, portCONTEXT_SIZE
-
-	#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
-
-	/* Restore the status and EPC registers and return */
-	mtc0	k1, _CP0_STATUS
-	mtc0 	k0, _CP0_EPC
-	ehb
-	eret
-	nop
-
-	.end	vPortYieldISR
-
-/******************************************************************/
-
-#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-
-	.macro portFPUSetAndInc reg, dest
-	mtc1	\reg, \dest
-	cvt.d.w	\dest, \dest
-	addiu	\reg, \reg, 1
-	.endm
-
-	.set	noreorder
-	.set 	noat
-	.section .text, code
-	.ent	vPortInitialiseFPSCR
-
-vPortInitialiseFPSCR:
-
-	/* Initialize the floating point status register in CP1. The initial
-	value is passed in a0. */
-	ctc1		a0, $f31
-
-	/* Clear the FPU registers */
-	addiu			a0, zero, 0x0000
-	portFPUSetAndInc	a0, $f0
-	portFPUSetAndInc	a0, $f1
-	portFPUSetAndInc	a0, $f2
-	portFPUSetAndInc	a0, $f3
-	portFPUSetAndInc	a0, $f4
-	portFPUSetAndInc	a0, $f5
-	portFPUSetAndInc	a0, $f6
-	portFPUSetAndInc	a0, $f7
-	portFPUSetAndInc	a0, $f8
-	portFPUSetAndInc	a0, $f9
-	portFPUSetAndInc	a0, $f10
-	portFPUSetAndInc	a0, $f11
-	portFPUSetAndInc	a0, $f12
-	portFPUSetAndInc	a0, $f13
-	portFPUSetAndInc	a0, $f14
-	portFPUSetAndInc	a0, $f15
-	portFPUSetAndInc	a0, $f16
-	portFPUSetAndInc	a0, $f17
-	portFPUSetAndInc	a0, $f18
-	portFPUSetAndInc	a0, $f19
-	portFPUSetAndInc	a0, $f20
-	portFPUSetAndInc	a0, $f21
-	portFPUSetAndInc	a0, $f22
-	portFPUSetAndInc	a0, $f23
-	portFPUSetAndInc	a0, $f24
-	portFPUSetAndInc	a0, $f25
-	portFPUSetAndInc	a0, $f26
-	portFPUSetAndInc	a0, $f27
-	portFPUSetAndInc	a0, $f28
-	portFPUSetAndInc	a0, $f29
-	portFPUSetAndInc	a0, $f30
-	portFPUSetAndInc	a0, $f31
-
-	jr		ra
-	nop
-
-	.end vPortInitialiseFPSCR
-
-#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
-	
-#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-
-	/**********************************************************************/
-	/* Test read back								*/
-	/* a0 = address to store registers				*/
-
-	.set		noreorder
-	.set 		noat
-	.section	.text, code
-	.ent		vPortFPUReadback
-	.global		vPortFPUReadback
-
-vPortFPUReadback:
-	sdc1		$f0, 0(a0)
-	sdc1		$f1, 8(a0)
-	sdc1		$f2, 16(a0)
-	sdc1		$f3, 24(a0)
-	sdc1		$f4, 32(a0)
-	sdc1		$f5, 40(a0)
-	sdc1		$f6, 48(a0)
-	sdc1		$f7, 56(a0)
-	sdc1		$f8, 64(a0)
-	sdc1		$f9, 72(a0)
-	sdc1		$f10, 80(a0)
-	sdc1		$f11, 88(a0)
-	sdc1		$f12, 96(a0)
-	sdc1		$f13, 104(a0)
-	sdc1		$f14, 112(a0)
-	sdc1		$f15, 120(a0)
-	sdc1		$f16, 128(a0)
-	sdc1		$f17, 136(a0)
-	sdc1		$f18, 144(a0)
-	sdc1		$f19, 152(a0)
-	sdc1		$f20, 160(a0)
-	sdc1		$f21, 168(a0)
-	sdc1		$f22, 176(a0)
-	sdc1		$f23, 184(a0)
-	sdc1		$f24, 192(a0)
-	sdc1		$f25, 200(a0)
-	sdc1		$f26, 208(a0)
-	sdc1		$f27, 216(a0)
-	sdc1		$f28, 224(a0)
-	sdc1		$f29, 232(a0)
-	sdc1		$f30, 240(a0)
-	sdc1		$f31, 248(a0)
-
-	jr		ra
-	nop
-
-	.end vPortFPUReadback
-
-#endif /* ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 ) */
-
-
-
-
diff --git a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/portmacro.h b/FreeRTOS/Source/portable/MPLAB/PIC32MZ/portmacro.h
deleted file mode 100755
index 7830488..0000000
--- a/FreeRTOS/Source/portable/MPLAB/PIC32MZ/portmacro.h
+++ /dev/null
@@ -1,215 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/* System include files */
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			8
-#define portSTACK_GROWTH			-1
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-#define portIPL_SHIFT				( 10UL )
-/* Don't straddle the CEE bit.  Interrupts calling FreeRTOS functions should
-never have higher IPL bits set anyway. */
-#define portALL_IPL_BITS			( 0x7FUL << portIPL_SHIFT )
-#define portSW0_BIT					( 0x01 << 8 )
-
-/* This clears the IPL bits, then sets them to
-configMAX_SYSCALL_INTERRUPT_PRIORITY.  An extra check is performed if
-configASSERT() is defined to ensure an assertion handler does not inadvertently
-attempt to lower the IPL when the call to assert was triggered because the IPL
-value was found to be above configMAX_SYSCALL_INTERRUPT_PRIORITY when an ISR
-safe FreeRTOS API function was executed.  ISR safe FreeRTOS API functions are
-those that end in FromISR.  FreeRTOS maintains a separate interrupt API to
-ensure API function and interrupt entry is as fast and as simple as possible. */
-#ifdef configASSERT
-	#define portDISABLE_INTERRUPTS()											\
-	{																			\
-	uint32_t ulStatus;															\
-																				\
-		/* Mask interrupts at and below the kernel interrupt priority. */		\
-		ulStatus = _CP0_GET_STATUS();											\
-																				\
-		/* Is the current IPL below configMAX_SYSCALL_INTERRUPT_PRIORITY? */	\
-		if( ( ( ulStatus & portALL_IPL_BITS ) >> portIPL_SHIFT ) < configMAX_SYSCALL_INTERRUPT_PRIORITY ) \
-		{																		\
-			ulStatus &= ~portALL_IPL_BITS;										\
-			_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
-		}																		\
-	}
-#else /* configASSERT */
-	#define portDISABLE_INTERRUPTS()										\
-	{																		\
-	uint32_t ulStatus;														\
-																			\
-		/* Mask interrupts at and below the kernel interrupt priority. */	\
-		ulStatus = _CP0_GET_STATUS();										\
-		ulStatus &= ~portALL_IPL_BITS;										\
-		_CP0_SET_STATUS( ( ulStatus | ( configMAX_SYSCALL_INTERRUPT_PRIORITY << portIPL_SHIFT ) ) ); \
-	}
-#endif /* configASSERT */
-
-#define portENABLE_INTERRUPTS()											\
-{																		\
-uint32_t ulStatus;														\
-																		\
-	/* Unmask all interrupts. */										\
-	ulStatus = _CP0_GET_STATUS();										\
-	ulStatus &= ~portALL_IPL_BITS;										\
-	_CP0_SET_STATUS( ulStatus );										\
-}
-
-
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portCRITICAL_NESTING_IN_TCB	1
-#define portENTER_CRITICAL()		vTaskEnterCritical()
-#define portEXIT_CRITICAL()			vTaskExitCritical()
-
-extern UBaseType_t uxPortSetInterruptMaskFromISR();
-extern void vPortClearInterruptMaskFromISR( UBaseType_t );
-#define portSET_INTERRUPT_MASK_FROM_ISR() uxPortSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusRegister ) vPortClearInterruptMaskFromISR( uxSavedStatusRegister )
-
-#if ( __mips_hard_float == 0 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-    #error configUSE_TASK_FPU_SUPPORT can only be set to 1 when the part supports a hardware FPU module.
-#endif
-
-#if ( __mips_hard_float == 1 ) && ( configUSE_TASK_FPU_SUPPORT == 1 )
-    void vPortTaskUsesFPU( void );
-	#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-#endif
-
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - _clz( ( uxReadyPriorities ) ) )
-
-#endif /* taskRECORD_READY_PRIORITY */
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-#define portYIELD()								\
-{												\
-uint32_t ulCause;								\
-												\
-	/* Trigger software interrupt. */			\
-	ulCause = _CP0_GET_CAUSE();					\
-	ulCause |= portSW0_BIT;						\
-	_CP0_SET_CAUSE( ulCause );					\
-}
-
-extern volatile UBaseType_t uxInterruptNesting;
-#define portASSERT_IF_IN_ISR() configASSERT( uxInterruptNesting == 0 )
-
-#define portNOP()	__asm volatile ( "nop" )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters ) __attribute__((noreturn))
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#define portEND_SWITCHING_ISR( xSwitchRequired )	if( xSwitchRequired )	\
-													{						\
-														portYIELD();		\
-													}
-
-/* Required by the kernel aware debugger. */
-#ifdef __DEBUG
-	#define portREMOVE_STATIC_QUALIFIER
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/MSVC-MingW/port.c b/FreeRTOS/Source/portable/MSVC-MingW/port.c
deleted file mode 100755
index 02d432c..0000000
--- a/FreeRTOS/Source/portable/MSVC-MingW/port.c
+++ /dev/null
@@ -1,620 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifdef __GNUC__
-	#include "mmsystem.h"
-#else
-	#pragma comment(lib, "winmm.lib")
-#endif
-
-#define portMAX_INTERRUPTS				( ( uint32_t ) sizeof( uint32_t ) * 8UL ) /* The number of bits in an uint32_t. */
-#define portNO_CRITICAL_NESTING 		( ( uint32_t ) 0 )
-
-/* The priorities at which the various components of the simulation execute. */
-#define portDELETE_SELF_THREAD_PRIORITY			 THREAD_PRIORITY_TIME_CRITICAL /* Must be highest. */
-#define portSIMULATED_INTERRUPTS_THREAD_PRIORITY THREAD_PRIORITY_TIME_CRITICAL
-#define portSIMULATED_TIMER_THREAD_PRIORITY		 THREAD_PRIORITY_HIGHEST
-#define portTASK_THREAD_PRIORITY				 THREAD_PRIORITY_ABOVE_NORMAL
-
-/*
- * Created as a high priority thread, this function uses a timer to simulate
- * a tick interrupt being generated on an embedded target.  In this Windows
- * environment the timer does not achieve anything approaching real time
- * performance though.
- */
-static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter );
-
-/*
- * Process all the simulated interrupts - each represented by a bit in
- * ulPendingInterrupts variable.
- */
-static void prvProcessSimulatedInterrupts( void );
-
-/*
- * Interrupt handlers used by the kernel itself.  These are executed from the
- * simulated interrupt handler thread.
- */
-static uint32_t prvProcessYieldInterrupt( void );
-static uint32_t prvProcessTickInterrupt( void );
-
-/*
- * Called when the process exits to let Windows know the high timer resolution
- * is no longer required.
- */
-static BOOL WINAPI prvEndProcess( DWORD dwCtrlType );
-
-/*-----------------------------------------------------------*/
-
-/* The WIN32 simulator runs each task in a thread.  The context switching is
-managed by the threads, so the task stack does not have to be managed directly,
-although the task stack is still used to hold an xThreadState structure this is
-the only thing it will ever hold.  The structure indirectly maps the task handle
-to a thread handle. */
-typedef struct
-{
-	/* Handle of the thread that executes the task. */
-	void *pvThread;
-
-} xThreadState;
-
-/* Simulated interrupts waiting to be processed.  This is a bit mask where each
-bit represents one interrupt, so a maximum of 32 interrupts can be simulated. */
-static volatile uint32_t ulPendingInterrupts = 0UL;
-
-/* An event used to inform the simulated interrupt processing thread (a high
-priority thread that simulated interrupt processing) that an interrupt is
-pending. */
-static void *pvInterruptEvent = NULL;
-
-/* Mutex used to protect all the simulated interrupt variables that are accessed
-by multiple threads. */
-static void *pvInterruptEventMutex = NULL;
-
-/* The critical nesting count for the currently executing task.  This is
-initialised to a non-zero value so interrupts do not become enabled during
-the initialisation phase.  As each task has its own critical nesting value
-ulCriticalNesting will get set to zero when the first task runs.  This
-initialisation is probably not critical in this simulated environment as the
-simulated interrupt handlers do not get created until the FreeRTOS scheduler is
-started anyway. */
-static uint32_t ulCriticalNesting = 9999UL;
-
-/* Handlers for all the simulated software interrupts.  The first two positions
-are used for the Yield and Tick interrupts so are handled slightly differently,
-all the other interrupts can be user defined. */
-static uint32_t (*ulIsrHandler[ portMAX_INTERRUPTS ])( void ) = { 0 };
-
-/* Pointer to the TCB of the currently executing task. */
-extern void *pxCurrentTCB;
-
-/* Used to ensure nothing is processed during the startup sequence. */
-static BaseType_t xPortRunning = pdFALSE;
-
-/*-----------------------------------------------------------*/
-
-static DWORD WINAPI prvSimulatedPeripheralTimer( LPVOID lpParameter )
-{
-TickType_t xMinimumWindowsBlockTime;
-TIMECAPS xTimeCaps;
-
-	/* Set the timer resolution to the maximum possible. */
-	if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
-	{
-		xMinimumWindowsBlockTime = ( TickType_t ) xTimeCaps.wPeriodMin;
-		timeBeginPeriod( xTimeCaps.wPeriodMin );
-
-		/* Register an exit handler so the timeBeginPeriod() function can be
-		matched with a timeEndPeriod() when the application exits. */
-		SetConsoleCtrlHandler( prvEndProcess, TRUE );
-	}
-	else
-	{
-		xMinimumWindowsBlockTime = ( TickType_t ) 20;
-	}
-
-	/* Just to prevent compiler warnings. */
-	( void ) lpParameter;
-
-	for( ;; )
-	{
-		/* Wait until the timer expires and we can access the simulated interrupt
-		variables.  *NOTE* this is not a 'real time' way of generating tick
-		events as the next wake time should be relative to the previous wake
-		time, not the time that Sleep() is called.  It is done this way to
-		prevent overruns in this very non real time simulated/emulated
-		environment. */
-		if( portTICK_PERIOD_MS < xMinimumWindowsBlockTime )
-		{
-			Sleep( xMinimumWindowsBlockTime );
-		}
-		else
-		{
-			Sleep( portTICK_PERIOD_MS );
-		}
-
-		configASSERT( xPortRunning );
-
-		WaitForSingleObject( pvInterruptEventMutex, INFINITE );
-
-		/* The timer has expired, generate the simulated tick event. */
-		ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
-
-		/* The interrupt is now pending - notify the simulated interrupt
-		handler thread. */
-		if( ulCriticalNesting == 0 )
-		{
-			SetEvent( pvInterruptEvent );
-		}
-
-		/* Give back the mutex so the simulated interrupt handler unblocks
-		and can	access the interrupt handler variables. */
-		ReleaseMutex( pvInterruptEventMutex );
-	}
-
-	#ifdef __GNUC__
-		/* Should never reach here - MingW complains if you leave this line out,
-		MSVC complains if you put it in. */
-		return 0;
-	#endif
-}
-/*-----------------------------------------------------------*/
-
-static BOOL WINAPI prvEndProcess( DWORD dwCtrlType )
-{
-TIMECAPS xTimeCaps;
-
-	( void ) dwCtrlType;
-
-	if( timeGetDevCaps( &xTimeCaps, sizeof( xTimeCaps ) ) == MMSYSERR_NOERROR )
-	{
-		/* Match the call to timeBeginPeriod( xTimeCaps.wPeriodMin ) made when
-		the process started with a timeEndPeriod() as the process exits. */
-		timeEndPeriod( xTimeCaps.wPeriodMin );
-	}
-
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-xThreadState *pxThreadState = NULL;
-int8_t *pcTopOfStack = ( int8_t * ) pxTopOfStack;
-const SIZE_T xStackSize = 1024; /* Set the size to a small number which will get rounded up to the minimum possible. */
-
-	/* In this simulated case a stack is not initialised, but instead a thread
-	is created that will execute the task being created.  The thread handles
-	the context switching itself.  The xThreadState object is placed onto
-	the stack that was created for the task - so the stack buffer is still
-	used, just not in the conventional way.  It will not be used for anything
-	other than holding this structure. */
-	pxThreadState = ( xThreadState * ) ( pcTopOfStack - sizeof( xThreadState ) );
-
-	/* Create the thread itself. */
-	pxThreadState->pvThread = CreateThread( NULL, xStackSize, ( LPTHREAD_START_ROUTINE ) pxCode, pvParameters, CREATE_SUSPENDED | STACK_SIZE_PARAM_IS_A_RESERVATION, NULL );
-	configASSERT( pxThreadState->pvThread ); /* See comment where TerminateThread() is called. */
-	SetThreadAffinityMask( pxThreadState->pvThread, 0x01 );
-	SetThreadPriorityBoost( pxThreadState->pvThread, TRUE );
-	SetThreadPriority( pxThreadState->pvThread, portTASK_THREAD_PRIORITY );
-
-	return ( StackType_t * ) pxThreadState;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-void *pvHandle = NULL;
-int32_t lSuccess;
-xThreadState *pxThreadState = NULL;
-SYSTEM_INFO xSystemInfo;
-
-	/* This port runs windows threads with extremely high priority.  All the
-	threads execute on the same core - to prevent locking up the host only start
-	if the host has multiple cores. */
-	GetSystemInfo( &xSystemInfo );
-	if( xSystemInfo.dwNumberOfProcessors <= 1 )
-	{
-		printf( "This version of the FreeRTOS Windows port can only be used on multi-core hosts.\r\n" );
-		lSuccess = pdFAIL;
-	}
-	else
-	{
-		lSuccess = pdPASS;
-
-		/* The highest priority class is used to [try to] prevent other Windows
-		activity interfering with FreeRTOS timing too much. */
-		if( SetPriorityClass( GetCurrentProcess(), REALTIME_PRIORITY_CLASS ) == 0 )
-		{
-			printf( "SetPriorityClass() failed\r\n" );
-		}
-
-		/* Install the interrupt handlers used by the scheduler itself. */
-		vPortSetInterruptHandler( portINTERRUPT_YIELD, prvProcessYieldInterrupt );
-		vPortSetInterruptHandler( portINTERRUPT_TICK, prvProcessTickInterrupt );
-
-		/* Create the events and mutexes that are used to synchronise all the
-		threads. */
-		pvInterruptEventMutex = CreateMutex( NULL, FALSE, NULL );
-		pvInterruptEvent = CreateEvent( NULL, FALSE, FALSE, NULL );
-
-		if( ( pvInterruptEventMutex == NULL ) || ( pvInterruptEvent == NULL ) )
-		{
-			lSuccess = pdFAIL;
-		}
-
-		/* Set the priority of this thread such that it is above the priority of
-		the threads that run tasks.  This higher priority is required to ensure
-		simulated interrupts take priority over tasks. */
-		pvHandle = GetCurrentThread();
-		if( pvHandle == NULL )
-		{
-			lSuccess = pdFAIL;
-		}
-	}
-
-	if( lSuccess == pdPASS )
-	{
-		if( SetThreadPriority( pvHandle, portSIMULATED_INTERRUPTS_THREAD_PRIORITY ) == 0 )
-		{
-			lSuccess = pdFAIL;
-		}
-		SetThreadPriorityBoost( pvHandle, TRUE );
-		SetThreadAffinityMask( pvHandle, 0x01 );
-	}
-
-	if( lSuccess == pdPASS )
-	{
-		/* Start the thread that simulates the timer peripheral to generate
-		tick interrupts.  The priority is set below that of the simulated
-		interrupt handler so the interrupt event mutex is used for the
-		handshake / overrun protection. */
-		pvHandle = CreateThread( NULL, 0, prvSimulatedPeripheralTimer, NULL, CREATE_SUSPENDED, NULL );
-		if( pvHandle != NULL )
-		{
-			SetThreadPriority( pvHandle, portSIMULATED_TIMER_THREAD_PRIORITY );
-			SetThreadPriorityBoost( pvHandle, TRUE );
-			SetThreadAffinityMask( pvHandle, 0x01 );
-			ResumeThread( pvHandle );
-		}
-
-		/* Start the highest priority task by obtaining its associated thread
-		state structure, in which is stored the thread handle. */
-		pxThreadState = ( xThreadState * ) *( ( size_t * ) pxCurrentTCB );
-		ulCriticalNesting = portNO_CRITICAL_NESTING;
-
-		/* Bump up the priority of the thread that is going to run, in the
-		hope that this will assist in getting the Windows thread scheduler to
-		behave as an embedded engineer might expect. */
-		ResumeThread( pxThreadState->pvThread );
-
-		/* Handle all simulated interrupts - including yield requests and
-		simulated ticks. */
-		prvProcessSimulatedInterrupts();
-	}
-
-	/* Would not expect to return from prvProcessSimulatedInterrupts(), so should
-	not get here. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-static uint32_t prvProcessYieldInterrupt( void )
-{
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-static uint32_t prvProcessTickInterrupt( void )
-{
-uint32_t ulSwitchRequired;
-
-	/* Process the tick itself. */
-	configASSERT( xPortRunning );
-	ulSwitchRequired = ( uint32_t ) xTaskIncrementTick();
-
-	return ulSwitchRequired;
-}
-/*-----------------------------------------------------------*/
-
-static void prvProcessSimulatedInterrupts( void )
-{
-uint32_t ulSwitchRequired, i;
-xThreadState *pxThreadState;
-void *pvObjectList[ 2 ];
-CONTEXT xContext;
-
-	/* Going to block on the mutex that ensured exclusive access to the simulated
-	interrupt objects, and the event that signals that a simulated interrupt
-	should be processed. */
-	pvObjectList[ 0 ] = pvInterruptEventMutex;
-	pvObjectList[ 1 ] = pvInterruptEvent;
-
-	/* Create a pending tick to ensure the first task is started as soon as
-	this thread pends. */
-	ulPendingInterrupts |= ( 1 << portINTERRUPT_TICK );
-	SetEvent( pvInterruptEvent );
-
-	xPortRunning = pdTRUE;
-
-	for(;;)
-	{
-		WaitForMultipleObjects( sizeof( pvObjectList ) / sizeof( void * ), pvObjectList, TRUE, INFINITE );
-
-		/* Used to indicate whether the simulated interrupt processing has
-		necessitated a context switch to another task/thread. */
-		ulSwitchRequired = pdFALSE;
-
-		/* For each interrupt we are interested in processing, each of which is
-		represented by a bit in the 32bit ulPendingInterrupts variable. */
-		for( i = 0; i < portMAX_INTERRUPTS; i++ )
-		{
-			/* Is the simulated interrupt pending? */
-			if( ulPendingInterrupts & ( 1UL << i ) )
-			{
-				/* Is a handler installed? */
-				if( ulIsrHandler[ i ] != NULL )
-				{
-					/* Run the actual handler. */
-					if( ulIsrHandler[ i ]() != pdFALSE )
-					{
-						ulSwitchRequired |= ( 1 << i );
-					}
-				}
-
-				/* Clear the interrupt pending bit. */
-				ulPendingInterrupts &= ~( 1UL << i );
-			}
-		}
-
-		if( ulSwitchRequired != pdFALSE )
-		{
-			void *pvOldCurrentTCB;
-
-			pvOldCurrentTCB = pxCurrentTCB;
-
-			/* Select the next task to run. */
-			vTaskSwitchContext();
-
-			/* If the task selected to enter the running state is not the task
-			that is already in the running state. */
-			if( pvOldCurrentTCB != pxCurrentTCB )
-			{
-				/* Suspend the old thread. */
-				pxThreadState = ( xThreadState *) *( ( size_t * ) pvOldCurrentTCB );
-				SuspendThread( pxThreadState->pvThread );
-
-				/* Ensure the thread is actually suspended by performing a
-				synchronous operation that can only complete when the thread is
-				actually suspended.  The below code asks for dummy register
-				data. */
-				xContext.ContextFlags = CONTEXT_INTEGER;
-				( void ) GetThreadContext( pxThreadState->pvThread, &xContext );
-
-				/* Obtain the state of the task now selected to enter the
-				Running state. */
-				pxThreadState = ( xThreadState * ) ( *( size_t *) pxCurrentTCB );
-				ResumeThread( pxThreadState->pvThread );
-			}
-		}
-
-		ReleaseMutex( pvInterruptEventMutex );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortDeleteThread( void *pvTaskToDelete )
-{
-xThreadState *pxThreadState;
-uint32_t ulErrorCode;
-
-	/* Remove compiler warnings if configASSERT() is not defined. */
-	( void ) ulErrorCode;
-
-	/* Find the handle of the thread being deleted. */
-	pxThreadState = ( xThreadState * ) ( *( size_t *) pvTaskToDelete );
-
-	/* Check that the thread is still valid, it might have been closed by
-	vPortCloseRunningThread() - which will be the case if the task associated
-	with the thread originally deleted itself rather than being deleted by a
-	different task. */
-	if( pxThreadState->pvThread != NULL )
-	{
-		WaitForSingleObject( pvInterruptEventMutex, INFINITE );
-
-		/* !!! This is not a nice way to terminate a thread, and will eventually
-		result in resources being depleted if tasks frequently delete other
-		tasks (rather than deleting themselves) as the task stacks will not be
-		freed. */
-		ulErrorCode = TerminateThread( pxThreadState->pvThread, 0 );
-		configASSERT( ulErrorCode );
-
-		ulErrorCode = CloseHandle( pxThreadState->pvThread );
-		configASSERT( ulErrorCode );
-
-		ReleaseMutex( pvInterruptEventMutex );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield )
-{
-xThreadState *pxThreadState;
-void *pvThread;
-uint32_t ulErrorCode;
-
-	/* Remove compiler warnings if configASSERT() is not defined. */
-	( void ) ulErrorCode;
-
-	/* Find the handle of the thread being deleted. */
-	pxThreadState = ( xThreadState * ) ( *( size_t *) pvTaskToDelete );
-	pvThread = pxThreadState->pvThread;
-
-	/* Raise the Windows priority of the thread to ensure the FreeRTOS scheduler
-	does not run and swap it out before it is closed.  If that were to happen
-	the thread would never run again and effectively be a thread handle and
-	memory leak. */
-	SetThreadPriority( pvThread, portDELETE_SELF_THREAD_PRIORITY );
-
-	/* This function will not return, therefore a yield is set as pending to
-	ensure a context switch occurs away from this thread on the next tick. */
-	*pxPendYield = pdTRUE;
-
-	/* Mark the thread associated with this task as invalid so
-	vPortDeleteThread() does not try to terminate it. */
-	pxThreadState->pvThread = NULL;
-
-	/* Close the thread. */
-	ulErrorCode = CloseHandle( pvThread );
-	configASSERT( ulErrorCode );
-
-	/* This is called from a critical section, which must be exited before the
-	thread stops. */
-	taskEXIT_CRITICAL();
-
-	ExitThread( 0 );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	exit( 0 );
-}
-/*-----------------------------------------------------------*/
-
-void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber )
-{
-	configASSERT( xPortRunning );
-
-	if( ( ulInterruptNumber < portMAX_INTERRUPTS ) && ( pvInterruptEventMutex != NULL ) )
-	{
-		/* Yield interrupts are processed even when critical nesting is
-		non-zero. */
-		WaitForSingleObject( pvInterruptEventMutex, INFINITE );
-		ulPendingInterrupts |= ( 1 << ulInterruptNumber );
-
-		/* The simulated interrupt is now held pending, but don't actually
-		process it yet if this call is within a critical section.  It is
-		possible for this to be in a critical section as calls to wait for
-		mutexes are accumulative. */
-		if( ulCriticalNesting == 0 )
-		{
-			SetEvent( pvInterruptEvent );
-		}
-
-		ReleaseMutex( pvInterruptEventMutex );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) )
-{
-	if( ulInterruptNumber < portMAX_INTERRUPTS )
-	{
-		if( pvInterruptEventMutex != NULL )
-		{
-			WaitForSingleObject( pvInterruptEventMutex, INFINITE );
-			ulIsrHandler[ ulInterruptNumber ] = pvHandler;
-			ReleaseMutex( pvInterruptEventMutex );
-		}
-		else
-		{
-			ulIsrHandler[ ulInterruptNumber ] = pvHandler;
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	if( xPortRunning == pdTRUE )
-	{
-		/* The interrupt event mutex is held for the entire critical section,
-		effectively disabling (simulated) interrupts. */
-		WaitForSingleObject( pvInterruptEventMutex, INFINITE );
-		ulCriticalNesting++;
-	}
-	else
-	{
-		ulCriticalNesting++;
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-int32_t lMutexNeedsReleasing;
-
-	/* The interrupt event mutex should already be held by this thread as it was
-	obtained on entry to the critical section. */
-
-	lMutexNeedsReleasing = pdTRUE;
-
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		if( ulCriticalNesting == ( portNO_CRITICAL_NESTING + 1 ) )
-		{
-			ulCriticalNesting--;
-
-			/* Were any interrupts set to pending while interrupts were
-			(simulated) disabled? */
-			if( ulPendingInterrupts != 0UL )
-			{
-				configASSERT( xPortRunning );
-				SetEvent( pvInterruptEvent );
-
-				/* Mutex will be released now, so does not require releasing
-				on function exit. */
-				lMutexNeedsReleasing = pdFALSE;
-				ReleaseMutex( pvInterruptEventMutex );
-			}
-		}
-		else
-		{
-			/* Tick interrupts will still not be processed as the critical
-			nesting depth will not be zero. */
-			ulCriticalNesting--;
-		}
-	}
-
-	if( pvInterruptEventMutex != NULL )
-	{
-		if( lMutexNeedsReleasing == pdTRUE )
-		{
-			configASSERT( xPortRunning );
-			ReleaseMutex( pvInterruptEventMutex );
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/MSVC-MingW/portmacro.h b/FreeRTOS/Source/portable/MSVC-MingW/portmacro.h
deleted file mode 100755
index 24822a6..0000000
--- a/FreeRTOS/Source/portable/MSVC-MingW/portmacro.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#include 
-#include 
-
-/******************************************************************************
-	Defines
-******************************************************************************/
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	size_t
-#define portBASE_TYPE	long
-#define portPOINTER_SIZE_TYPE size_t
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32/64-bit tick type on a 32/64-bit architecture, so reads of the tick
-	count do not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portINLINE __inline
-
-#if defined( __x86_64__) || defined( _M_X64 )
-	#define portBYTE_ALIGNMENT		8
-#else
-	#define portBYTE_ALIGNMENT		4
-#endif
-
-#define portYIELD()					vPortGenerateSimulatedInterrupt( portINTERRUPT_YIELD )
-
-/* Simulated interrupts return pdFALSE if no context switch should be performed,
-or a non-zero number if a context switch should be performed. */
-#define portYIELD_FROM_ISR( x ) ( void ) x
-#define portEND_SWITCHING_ISR( x ) portYIELD_FROM_ISR( ( x ) )
-
-void vPortCloseRunningThread( void *pvTaskToDelete, volatile BaseType_t *pxPendYield );
-void vPortDeleteThread( void *pvThreadToDelete );
-#define portCLEAN_UP_TCB( pxTCB )	vPortDeleteThread( pxTCB )
-#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxPendYield ) vPortCloseRunningThread( ( pvTaskToDelete ), ( pxPendYield ) )
-#define portDISABLE_INTERRUPTS() vPortEnterCritical()
-#define portENABLE_INTERRUPTS() vPortExitCritical()
-
-/* Critical section handling. */
-void vPortEnterCritical( void );
-void vPortExitCritical( void );
-
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-
-	/*-----------------------------------------------------------*/
-
-	#ifdef __GNUC__
-		#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities )	\
-			__asm volatile(	"bsr %1, %0\n\t" 									\
-							:"=r"(uxTopPriority) : "rm"(uxReadyPriorities) : "cc" )
-	#else
-		/* BitScanReverse returns the bit position of the most significant '1'
-		in the word. */
-		#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) _BitScanReverse( ( DWORD * ) &( uxTopPriority ), ( uxReadyPriorities ) )
-	#endif /* __GNUC__ */
-
-#endif /* taskRECORD_READY_PRIORITY */
-
-#ifndef __GNUC__
-	__pragma( warning( disable:4211 ) ) /* Nonstandard extension used, as extern is only nonstandard to MSVC. */
-#endif
-
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void * pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void * pvParameters )
-
-#define portINTERRUPT_YIELD				( 0UL )
-#define portINTERRUPT_TICK				( 1UL )
-
-/*
- * Raise a simulated interrupt represented by the bit mask in ulInterruptMask.
- * Each bit can be used to represent an individual interrupt - with the first
- * two bits being used for the Yield and Tick interrupts respectively.
-*/
-void vPortGenerateSimulatedInterrupt( uint32_t ulInterruptNumber );
-
-/*
- * Install an interrupt handler to be called by the simulated interrupt handler
- * thread.  The interrupt number must be above any used by the kernel itself
- * (at the time of writing the kernel was using interrupt numbers 0, 1, and 2
- * as defined above).  The number must also be lower than 32.
- *
- * Interrupt handler functions must return a non-zero value if executing the
- * handler resulted in a task switch being required.
- */
-void vPortSetInterruptHandler( uint32_t ulInterruptNumber, uint32_t (*pvHandler)( void ) );
-
-#endif
-
diff --git a/FreeRTOS/Source/portable/MemMang/ReadMe.url b/FreeRTOS/Source/portable/MemMang/ReadMe.url
deleted file mode 100755
index 6c23737..0000000
--- a/FreeRTOS/Source/portable/MemMang/ReadMe.url
+++ /dev/null
@@ -1,5 +0,0 @@
-[{000214A0-0000-0000-C000-000000000046}]
-Prop3=19,2
-[InternetShortcut]
-URL=http://www.freertos.org/a00111.html
-IDList=
diff --git a/FreeRTOS/Source/portable/MemMang/heap_1.c b/FreeRTOS/Source/portable/MemMang/heap_1.c
deleted file mode 100755
index 542317d..0000000
--- a/FreeRTOS/Source/portable/MemMang/heap_1.c
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*
- * The simplest possible implementation of pvPortMalloc().  Note that this
- * implementation does NOT allow allocated memory to be freed again.
- *
- * See heap_2.c, heap_3.c and heap_4.c for alternative implementations, and the
- * memory management pages of http://www.FreeRTOS.org for more information.
- */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/* A few bytes might be lost to byte aligning the heap start address. */
-#define configADJUSTED_HEAP_SIZE	( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#else
-	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/* Index into the ucHeap array. */
-static size_t xNextFreeByte = ( size_t ) 0;
-
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-void *pvReturn = NULL;
-static uint8_t *pucAlignedHeap = NULL;
-
-	/* Ensure that blocks are always aligned to the required number of bytes. */
-	#if( portBYTE_ALIGNMENT != 1 )
-	{
-		if( xWantedSize & portBYTE_ALIGNMENT_MASK )
-		{
-			/* Byte alignment required. */
-			xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
-		}
-	}
-	#endif
-
-	vTaskSuspendAll();
-	{
-		if( pucAlignedHeap == NULL )
-		{
-			/* Ensure the heap starts on a correctly aligned boundary. */
-			pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
-		}
-
-		/* Check there is enough room left for the allocation. */
-		if( ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) &&
-			( ( xNextFreeByte + xWantedSize ) > xNextFreeByte )	)/* Check for overflow. */
-		{
-			/* Return the next free byte then increment the index past this
-			block. */
-			pvReturn = pucAlignedHeap + xNextFreeByte;
-			xNextFreeByte += xWantedSize;
-		}
-
-		traceMALLOC( pvReturn, xWantedSize );
-	}
-	( void ) xTaskResumeAll();
-
-	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-	}
-	#endif
-
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-	/* Memory cannot be freed using this scheme.  See heap_2.c, heap_3.c and
-	heap_4.c for alternative implementations, and the memory management pages of
-	http://www.FreeRTOS.org for more information. */
-	( void ) pv;
-
-	/* Force an assert as it is invalid to call this function. */
-	configASSERT( pv == NULL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* Only required when static memory is not cleared. */
-	xNextFreeByte = ( size_t ) 0;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return ( configADJUSTED_HEAP_SIZE - xNextFreeByte );
-}
-
-
-
diff --git a/FreeRTOS/Source/portable/MemMang/heap_2.c b/FreeRTOS/Source/portable/MemMang/heap_2.c
deleted file mode 100755
index 7d06921..0000000
--- a/FreeRTOS/Source/portable/MemMang/heap_2.c
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * A sample implementation of pvPortMalloc() and vPortFree() that permits
- * allocated blocks to be freed, but does not combine adjacent free blocks
- * into a single larger block (and so will fragment memory).  See heap_4.c for
- * an equivalent that does combine adjacent blocks into single larger blocks.
- *
- * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the
- * memory management pages of http://www.FreeRTOS.org for more information.
- */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/* A few bytes might be lost to byte aligning the heap start address. */
-#define configADJUSTED_HEAP_SIZE	( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
-
-/*
- * Initialises the heap structures before their first use.
- */
-static void prvHeapInit( void );
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#else
-	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-
-/* Define the linked list structure.  This is used to link free blocks in order
-of their size. */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
-	size_t xBlockSize;						/*<< The size of the free block. */
-} BlockLink_t;
-
-
-static const uint16_t heapSTRUCT_SIZE	= ( ( sizeof ( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );
-#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )
-
-/* Create a couple of list links to mark the start and end of the list. */
-static BlockLink_t xStart, xEnd;
-
-/* Keeps track of the number of free bytes remaining, but says nothing about
-fragmentation. */
-static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
-
-/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */
-
-/*
- * Insert a block into the list of free blocks - which is ordered by size of
- * the block.  Small blocks at the start of the list and large blocks at the end
- * of the list.
- */
-#define prvInsertBlockIntoFreeList( pxBlockToInsert )								\
-{																					\
-BlockLink_t *pxIterator;															\
-size_t xBlockSize;																	\
-																					\
-	xBlockSize = pxBlockToInsert->xBlockSize;										\
-																					\
-	/* Iterate through the list until a block is found that has a larger size */	\
-	/* than the block we are inserting. */											\
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock )	\
-	{																				\
-		/* There is nothing to do here - just iterate to the correct position. */	\
-	}																				\
-																					\
-	/* Update the list to include the block being inserted in the correct */		\
-	/* position. */																	\
-	pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;					\
-	pxIterator->pxNextFreeBlock = pxBlockToInsert;									\
-}
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-static BaseType_t xHeapHasBeenInitialised = pdFALSE;
-void *pvReturn = NULL;
-
-	vTaskSuspendAll();
-	{
-		/* If this is the first call to malloc then the heap will require
-		initialisation to setup the list of free blocks. */
-		if( xHeapHasBeenInitialised == pdFALSE )
-		{
-			prvHeapInit();
-			xHeapHasBeenInitialised = pdTRUE;
-		}
-
-		/* The wanted size is increased so it can contain a BlockLink_t
-		structure in addition to the requested amount of bytes. */
-		if( xWantedSize > 0 )
-		{
-			xWantedSize += heapSTRUCT_SIZE;
-
-			/* Ensure that blocks are always aligned to the required number of bytes. */
-			if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0 )
-			{
-				/* Byte alignment required. */
-				xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
-			}
-		}
-
-		if( ( xWantedSize > 0 ) && ( xWantedSize < configADJUSTED_HEAP_SIZE ) )
-		{
-			/* Blocks are stored in byte order - traverse the list from the start
-			(smallest) block until one of adequate size is found. */
-			pxPreviousBlock = &xStart;
-			pxBlock = xStart.pxNextFreeBlock;
-			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-			{
-				pxPreviousBlock = pxBlock;
-				pxBlock = pxBlock->pxNextFreeBlock;
-			}
-
-			/* If we found the end marker then a block of adequate size was not found. */
-			if( pxBlock != &xEnd )
-			{
-				/* Return the memory space - jumping over the BlockLink_t structure
-				at its start. */
-				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );
-
-				/* This block is being returned for use so must be taken out of the
-				list of free blocks. */
-				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-				/* If the block is larger than required it can be split into two. */
-				if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
-				{
-					/* This block is to be split into two.  Create a new block
-					following the number of bytes requested. The void cast is
-					used to prevent byte alignment warnings from the compiler. */
-					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-
-					/* Calculate the sizes of two blocks split from the single
-					block. */
-					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-					pxBlock->xBlockSize = xWantedSize;
-
-					/* Insert the new block into the list of free blocks. */
-					prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
-				}
-
-				xFreeBytesRemaining -= pxBlock->xBlockSize;
-			}
-		}
-
-		traceMALLOC( pvReturn, xWantedSize );
-	}
-	( void ) xTaskResumeAll();
-
-	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-	}
-	#endif
-
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		before it. */
-		puc -= heapSTRUCT_SIZE;
-
-		/* This unexpected casting is to keep some compilers from issuing
-		byte alignment warnings. */
-		pxLink = ( void * ) puc;
-
-		vTaskSuspendAll();
-		{
-			/* Add this block to the list of free blocks. */
-			prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-			xFreeBytesRemaining += pxLink->xBlockSize;
-			traceFREE( pv, pxLink->xBlockSize );
-		}
-		( void ) xTaskResumeAll();
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
-
-	/* xStart is used to hold a pointer to the first item in the list of free
-	blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
-
-	/* xEnd is used to mark the end of the list of free blocks. */
-	xEnd.xBlockSize = configADJUSTED_HEAP_SIZE;
-	xEnd.pxNextFreeBlock = NULL;
-
-	/* To start with there is a single free block that is sized to take up the
-	entire heap space. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;
-	pxFirstFreeBlock->pxNextFreeBlock = &xEnd;
-}
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/portable/MemMang/heap_3.c b/FreeRTOS/Source/portable/MemMang/heap_3.c
deleted file mode 100755
index e6a2990..0000000
--- a/FreeRTOS/Source/portable/MemMang/heap_3.c
+++ /dev/null
@@ -1,97 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*
- * Implementation of pvPortMalloc() and vPortFree() that relies on the
- * compilers own malloc() and free() implementations.
- *
- * This file can only be used if the linker is configured to to generate
- * a heap memory area.
- *
- * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the
- * memory management pages of http://www.FreeRTOS.org for more information.
- */
-
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-void *pvReturn;
-
-	vTaskSuspendAll();
-	{
-		pvReturn = malloc( xWantedSize );
-		traceMALLOC( pvReturn, xWantedSize );
-	}
-	( void ) xTaskResumeAll();
-
-	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-	}
-	#endif
-
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-	if( pv )
-	{
-		vTaskSuspendAll();
-		{
-			free( pv );
-			traceFREE( pv, 0 );
-		}
-		( void ) xTaskResumeAll();
-	}
-}
-
-
-
diff --git a/FreeRTOS/Source/portable/MemMang/heap_4.c b/FreeRTOS/Source/portable/MemMang/heap_4.c
deleted file mode 100755
index d7cd8a5..0000000
--- a/FreeRTOS/Source/portable/MemMang/heap_4.c
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * A sample implementation of pvPortMalloc() and vPortFree() that combines
- * (coalescences) adjacent memory blocks as they are freed, and in so doing
- * limits memory fragmentation.
- *
- * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
- * memory management pages of http://www.FreeRTOS.org for more information.
- */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/* Block sizes must not get too small. */
-#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define heapBITS_PER_BYTE		( ( size_t ) 8 )
-
-/* Allocate the memory for the heap. */
-#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
-	/* The application writer has already defined the array used for the RTOS
-	heap - probably so it can be placed in a special segment or address. */
-	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#else
-	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
-#endif /* configAPPLICATION_ALLOCATED_HEAP */
-
-/* Define the linked list structure.  This is used to link free blocks in order
-of their memory address. */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
-	size_t xBlockSize;						/*<< The size of the free block. */
-} BlockLink_t;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Inserts a block of memory that is being freed into the correct position in
- * the list of free memory blocks.  The block being freed will be merged with
- * the block in front it and/or the block behind it if the memory blocks are
- * adjacent to each other.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
-
-/*
- * Called automatically to setup the required heap structures the first time
- * pvPortMalloc() is called.
- */
-static void prvHeapInit( void );
-
-/*-----------------------------------------------------------*/
-
-/* The size of the structure placed at the beginning of each allocated memory
-block must by correctly byte aligned. */
-static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
-
-/* Create a couple of list links to mark the start and end of the list. */
-static BlockLink_t xStart, *pxEnd = NULL;
-
-/* Keeps track of the number of free bytes remaining, but says nothing about
-fragmentation. */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
-member of an BlockLink_t structure is set then the block belongs to the
-application.  When the bit is free the block is still part of the free heap
-space. */
-static size_t xBlockAllocatedBit = 0;
-
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
-
-	vTaskSuspendAll();
-	{
-		/* If this is the first call to malloc then the heap will require
-		initialisation to setup the list of free blocks. */
-		if( pxEnd == NULL )
-		{
-			prvHeapInit();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		/* Check the requested block size is not so large that the top bit is
-		set.  The top bit of the block size member of the BlockLink_t structure
-		is used to determine who owns the block - the application or the
-		kernel, so it must be free. */
-		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-		{
-			/* The wanted size is increased so it can contain a BlockLink_t
-			structure in addition to the requested amount of bytes. */
-			if( xWantedSize > 0 )
-			{
-				xWantedSize += xHeapStructSize;
-
-				/* Ensure that blocks are always aligned to the required number
-				of bytes. */
-				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
-				{
-					/* Byte alignment required. */
-					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
-					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-			{
-				/* Traverse the list from the start	(lowest address) block until
-				one	of adequate size is found. */
-				pxPreviousBlock = &xStart;
-				pxBlock = xStart.pxNextFreeBlock;
-				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-				{
-					pxPreviousBlock = pxBlock;
-					pxBlock = pxBlock->pxNextFreeBlock;
-				}
-
-				/* If the end marker was reached then a block of adequate size
-				was	not found. */
-				if( pxBlock != pxEnd )
-				{
-					/* Return the memory space pointed to - jumping over the
-					BlockLink_t structure at its start. */
-					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-					/* This block is being returned for use so must be taken out
-					of the list of free blocks. */
-					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-					/* If the block is larger than required it can be split into
-					two. */
-					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
-					{
-						/* This block is to be split into two.  Create a new
-						block following the number of bytes requested. The void
-						cast is used to prevent byte alignment warnings from the
-						compiler. */
-						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-						configASSERT( ( ( ( size_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
-
-						/* Calculate the sizes of two blocks split from the
-						single block. */
-						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-						pxBlock->xBlockSize = xWantedSize;
-
-						/* Insert the new block into the list of free blocks. */
-						prvInsertBlockIntoFreeList( pxNewBlockLink );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-					{
-						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* The block is being returned - it is allocated and owned
-					by the application and has no "next" block. */
-					pxBlock->xBlockSize |= xBlockAllocatedBit;
-					pxBlock->pxNextFreeBlock = NULL;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		traceMALLOC( pvReturn, xWantedSize );
-	}
-	( void ) xTaskResumeAll();
-
-	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
-
-	configASSERT( ( ( ( size_t ) pvReturn ) & ( size_t ) portBYTE_ALIGNMENT_MASK ) == 0 );
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		before it. */
-		puc -= xHeapStructSize;
-
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
-
-		/* Check the block is actually allocated. */
-		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		configASSERT( pxLink->pxNextFreeBlock == NULL );
-
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-				vTaskSuspendAll();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				( void ) xTaskResumeAll();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-void vPortInitialiseBlocks( void )
-{
-	/* This just exists to keep the linker quiet. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvHeapInit( void )
-{
-BlockLink_t *pxFirstFreeBlock;
-uint8_t *pucAlignedHeap;
-size_t uxAddress;
-size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
-
-	/* Ensure the heap starts on a correctly aligned boundary. */
-	uxAddress = ( size_t ) ucHeap;
-
-	if( ( uxAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
-	{
-		uxAddress += ( portBYTE_ALIGNMENT - 1 );
-		uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
-		xTotalHeapSize -= uxAddress - ( size_t ) ucHeap;
-	}
-
-	pucAlignedHeap = ( uint8_t * ) uxAddress;
-
-	/* xStart is used to hold a pointer to the first item in the list of free
-	blocks.  The void cast is used to prevent compiler warnings. */
-	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
-	xStart.xBlockSize = ( size_t ) 0;
-
-	/* pxEnd is used to mark the end of the list of free blocks and is inserted
-	at the end of the heap space. */
-	uxAddress = ( ( size_t ) pucAlignedHeap ) + xTotalHeapSize;
-	uxAddress -= xHeapStructSize;
-	uxAddress &= ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
-	pxEnd = ( void * ) uxAddress;
-	pxEnd->xBlockSize = 0;
-	pxEnd->pxNextFreeBlock = NULL;
-
-	/* To start with there is a single free block that is sized to take up the
-	entire heap space, minus the space taken by pxEnd. */
-	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
-	pxFirstFreeBlock->xBlockSize = uxAddress - ( size_t ) pxFirstFreeBlock;
-	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
-
-	/* Only one block exists - and it covers the entire usable heap space. */
-	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
-
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
-{
-BlockLink_t *pxIterator;
-uint8_t *puc;
-
-	/* Iterate through the list until a block is found that has a higher address
-	than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
-
-	/* Do the block being inserted, and the block it is being inserted after
-	make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Do the block being inserted, and the block it is being inserted before
-	make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
-
-	/* If the block being inserted plugged a gab, so was merged with the block
-	before and the block after, then it's pxNextFreeBlock pointer will have
-	already been set, and should not be set here as that would make it point
-	to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-
diff --git a/FreeRTOS/Source/portable/MemMang/heap_5.c b/FreeRTOS/Source/portable/MemMang/heap_5.c
deleted file mode 100755
index b52d61c..0000000
--- a/FreeRTOS/Source/portable/MemMang/heap_5.c
+++ /dev/null
@@ -1,485 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * A sample implementation of pvPortMalloc() that allows the heap to be defined
- * across multiple non-contigous blocks and combines (coalescences) adjacent
- * memory blocks as they are freed.
- *
- * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative
- * implementations, and the memory management pages of http://www.FreeRTOS.org
- * for more information.
- *
- * Usage notes:
- *
- * vPortDefineHeapRegions() ***must*** be called before pvPortMalloc().
- * pvPortMalloc() will be called if any task objects (tasks, queues, event
- * groups, etc.) are created, therefore vPortDefineHeapRegions() ***must*** be
- * called before any other objects are defined.
- *
- * vPortDefineHeapRegions() takes a single parameter.  The parameter is an array
- * of HeapRegion_t structures.  HeapRegion_t is defined in portable.h as
- *
- * typedef struct HeapRegion
- * {
- *	uint8_t *pucStartAddress; << Start address of a block of memory that will be part of the heap.
- *	size_t xSizeInBytes;	  << Size of the block of memory.
- * } HeapRegion_t;
- *
- * The array is terminated using a NULL zero sized region definition, and the
- * memory regions defined in the array ***must*** appear in address order from
- * low address to high address.  So the following is a valid example of how
- * to use the function.
- *
- * HeapRegion_t xHeapRegions[] =
- * {
- * 	{ ( uint8_t * ) 0x80000000UL, 0x10000 }, << Defines a block of 0x10000 bytes starting at address 0x80000000
- * 	{ ( uint8_t * ) 0x90000000UL, 0xa0000 }, << Defines a block of 0xa0000 bytes starting at address of 0x90000000
- * 	{ NULL, 0 }                << Terminates the array.
- * };
- *
- * vPortDefineHeapRegions( xHeapRegions ); << Pass the array into vPortDefineHeapRegions().
- *
- * Note 0x80000000 is the lower address so appears in the array first.
- *
- */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-	#error This file must not be used if configSUPPORT_DYNAMIC_ALLOCATION is 0
-#endif
-
-/* Block sizes must not get too small. */
-#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize << 1 ) )
-
-/* Assumes 8bit bytes! */
-#define heapBITS_PER_BYTE		( ( size_t ) 8 )
-
-/* Define the linked list structure.  This is used to link free blocks in order
-of their memory address. */
-typedef struct A_BLOCK_LINK
-{
-	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
-	size_t xBlockSize;						/*<< The size of the free block. */
-} BlockLink_t;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Inserts a block of memory that is being freed into the correct position in
- * the list of free memory blocks.  The block being freed will be merged with
- * the block in front it and/or the block behind it if the memory blocks are
- * adjacent to each other.
- */
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
-
-/*-----------------------------------------------------------*/
-
-/* The size of the structure placed at the beginning of each allocated memory
-block must by correctly byte aligned. */
-static const size_t xHeapStructSize	= ( sizeof( BlockLink_t ) + ( ( size_t ) ( portBYTE_ALIGNMENT - 1 ) ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK );
-
-/* Create a couple of list links to mark the start and end of the list. */
-static BlockLink_t xStart, *pxEnd = NULL;
-
-/* Keeps track of the number of free bytes remaining, but says nothing about
-fragmentation. */
-static size_t xFreeBytesRemaining = 0U;
-static size_t xMinimumEverFreeBytesRemaining = 0U;
-
-/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
-member of an BlockLink_t structure is set then the block belongs to the
-application.  When the bit is free the block is still part of the free heap
-space. */
-static size_t xBlockAllocatedBit = 0;
-
-/*-----------------------------------------------------------*/
-
-void *pvPortMalloc( size_t xWantedSize )
-{
-BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
-void *pvReturn = NULL;
-
-	/* The heap must be initialised before the first call to
-	prvPortMalloc(). */
-	configASSERT( pxEnd );
-
-	vTaskSuspendAll();
-	{
-		/* Check the requested block size is not so large that the top bit is
-		set.  The top bit of the block size member of the BlockLink_t structure
-		is used to determine who owns the block - the application or the
-		kernel, so it must be free. */
-		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
-		{
-			/* The wanted size is increased so it can contain a BlockLink_t
-			structure in addition to the requested amount of bytes. */
-			if( xWantedSize > 0 )
-			{
-				xWantedSize += xHeapStructSize;
-
-				/* Ensure that blocks are always aligned to the required number
-				of bytes. */
-				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
-				{
-					/* Byte alignment required. */
-					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
-			{
-				/* Traverse the list from the start	(lowest address) block until
-				one	of adequate size is found. */
-				pxPreviousBlock = &xStart;
-				pxBlock = xStart.pxNextFreeBlock;
-				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
-				{
-					pxPreviousBlock = pxBlock;
-					pxBlock = pxBlock->pxNextFreeBlock;
-				}
-
-				/* If the end marker was reached then a block of adequate size
-				was	not found. */
-				if( pxBlock != pxEnd )
-				{
-					/* Return the memory space pointed to - jumping over the
-					BlockLink_t structure at its start. */
-					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
-
-					/* This block is being returned for use so must be taken out
-					of the list of free blocks. */
-					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
-
-					/* If the block is larger than required it can be split into
-					two. */
-					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
-					{
-						/* This block is to be split into two.  Create a new
-						block following the number of bytes requested. The void
-						cast is used to prevent byte alignment warnings from the
-						compiler. */
-						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
-
-						/* Calculate the sizes of two blocks split from the
-						single block. */
-						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
-						pxBlock->xBlockSize = xWantedSize;
-
-						/* Insert the new block into the list of free blocks. */
-						prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					xFreeBytesRemaining -= pxBlock->xBlockSize;
-
-					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
-					{
-						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* The block is being returned - it is allocated and owned
-					by the application and has no "next" block. */
-					pxBlock->xBlockSize |= xBlockAllocatedBit;
-					pxBlock->pxNextFreeBlock = NULL;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		traceMALLOC( pvReturn, xWantedSize );
-	}
-	( void ) xTaskResumeAll();
-
-	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
-	{
-		if( pvReturn == NULL )
-		{
-			extern void vApplicationMallocFailedHook( void );
-			vApplicationMallocFailedHook();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif
-
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vPortFree( void *pv )
-{
-uint8_t *puc = ( uint8_t * ) pv;
-BlockLink_t *pxLink;
-
-	if( pv != NULL )
-	{
-		/* The memory being freed will have an BlockLink_t structure immediately
-		before it. */
-		puc -= xHeapStructSize;
-
-		/* This casting is to keep the compiler from issuing warnings. */
-		pxLink = ( void * ) puc;
-
-		/* Check the block is actually allocated. */
-		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
-		configASSERT( pxLink->pxNextFreeBlock == NULL );
-
-		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
-		{
-			if( pxLink->pxNextFreeBlock == NULL )
-			{
-				/* The block is being returned to the heap - it is no longer
-				allocated. */
-				pxLink->xBlockSize &= ~xBlockAllocatedBit;
-
-				vTaskSuspendAll();
-				{
-					/* Add this block to the list of free blocks. */
-					xFreeBytesRemaining += pxLink->xBlockSize;
-					traceFREE( pv, pxLink->xBlockSize );
-					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
-				}
-				( void ) xTaskResumeAll();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetFreeHeapSize( void )
-{
-	return xFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-size_t xPortGetMinimumEverFreeHeapSize( void )
-{
-	return xMinimumEverFreeBytesRemaining;
-}
-/*-----------------------------------------------------------*/
-
-static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
-{
-BlockLink_t *pxIterator;
-uint8_t *puc;
-
-	/* Iterate through the list until a block is found that has a higher address
-	than the block being inserted. */
-	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
-	{
-		/* Nothing to do here, just iterate to the right position. */
-	}
-
-	/* Do the block being inserted, and the block it is being inserted after
-	make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxIterator;
-	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
-	{
-		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
-		pxBlockToInsert = pxIterator;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Do the block being inserted, and the block it is being inserted before
-	make a contiguous block of memory? */
-	puc = ( uint8_t * ) pxBlockToInsert;
-	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
-	{
-		if( pxIterator->pxNextFreeBlock != pxEnd )
-		{
-			/* Form one big block from the two blocks. */
-			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
-			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
-		}
-		else
-		{
-			pxBlockToInsert->pxNextFreeBlock = pxEnd;
-		}
-	}
-	else
-	{
-		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
-	}
-
-	/* If the block being inserted plugged a gab, so was merged with the block
-	before and the block after, then it's pxNextFreeBlock pointer will have
-	already been set, and should not be set here as that would make it point
-	to itself. */
-	if( pxIterator != pxBlockToInsert )
-	{
-		pxIterator->pxNextFreeBlock = pxBlockToInsert;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
-{
-BlockLink_t *pxFirstFreeBlockInRegion = NULL, *pxPreviousFreeBlock;
-size_t xAlignedHeap;
-size_t xTotalRegionSize, xTotalHeapSize = 0;
-BaseType_t xDefinedRegions = 0;
-size_t xAddress;
-const HeapRegion_t *pxHeapRegion;
-
-	/* Can only call once! */
-	configASSERT( pxEnd == NULL );
-
-	pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
-
-	while( pxHeapRegion->xSizeInBytes > 0 )
-	{
-		xTotalRegionSize = pxHeapRegion->xSizeInBytes;
-
-		/* Ensure the heap region starts on a correctly aligned boundary. */
-		xAddress = ( size_t ) pxHeapRegion->pucStartAddress;
-		if( ( xAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
-		{
-			xAddress += ( portBYTE_ALIGNMENT - 1 );
-			xAddress &= ~portBYTE_ALIGNMENT_MASK;
-
-			/* Adjust the size for the bytes lost to alignment. */
-			xTotalRegionSize -= xAddress - ( size_t ) pxHeapRegion->pucStartAddress;
-		}
-
-		xAlignedHeap = xAddress;
-
-		/* Set xStart if it has not already been set. */
-		if( xDefinedRegions == 0 )
-		{
-			/* xStart is used to hold a pointer to the first item in the list of
-			free blocks.  The void cast is used to prevent compiler warnings. */
-			xStart.pxNextFreeBlock = ( BlockLink_t * ) xAlignedHeap;
-			xStart.xBlockSize = ( size_t ) 0;
-		}
-		else
-		{
-			/* Should only get here if one region has already been added to the
-			heap. */
-			configASSERT( pxEnd != NULL );
-
-			/* Check blocks are passed in with increasing start addresses. */
-			configASSERT( xAddress > ( size_t ) pxEnd );
-		}
-
-		/* Remember the location of the end marker in the previous region, if
-		any. */
-		pxPreviousFreeBlock = pxEnd;
-
-		/* pxEnd is used to mark the end of the list of free blocks and is
-		inserted at the end of the region space. */
-		xAddress = xAlignedHeap + xTotalRegionSize;
-		xAddress -= xHeapStructSize;
-		xAddress &= ~portBYTE_ALIGNMENT_MASK;
-		pxEnd = ( BlockLink_t * ) xAddress;
-		pxEnd->xBlockSize = 0;
-		pxEnd->pxNextFreeBlock = NULL;
-
-		/* To start with there is a single free block in this region that is
-		sized to take up the entire heap region minus the space taken by the
-		free block structure. */
-		pxFirstFreeBlockInRegion = ( BlockLink_t * ) xAlignedHeap;
-		pxFirstFreeBlockInRegion->xBlockSize = xAddress - ( size_t ) pxFirstFreeBlockInRegion;
-		pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;
-
-		/* If this is not the first region that makes up the entire heap space
-		then link the previous region to this region. */
-		if( pxPreviousFreeBlock != NULL )
-		{
-			pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion;
-		}
-
-		xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize;
-
-		/* Move onto the next HeapRegion_t structure. */
-		xDefinedRegions++;
-		pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
-	}
-
-	xMinimumEverFreeBytesRemaining = xTotalHeapSize;
-	xFreeBytesRemaining = xTotalHeapSize;
-
-	/* Check something was actually defined before it is accessed. */
-	configASSERT( xTotalHeapSize );
-
-	/* Work out the position of the top bit in a size_t variable. */
-	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
-}
-
diff --git a/FreeRTOS/Source/portable/MikroC/ARM_CM4F/port.c b/FreeRTOS/Source/portable/MikroC/ARM_CM4F/port.c
deleted file mode 100755
index 58933d0..0000000
--- a/FreeRTOS/Source/portable/MikroC/ARM_CM4F/port.c
+++ /dev/null
@@ -1,788 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT			 ( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
-
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16	 ( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR							( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS			( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR					( 0x01000000 )
-#define portINITIAL_EXC_RETURN				( 0xfffffffd )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR			( 45UL )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/* Cannot find a weak linkage attribute, so the
-configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if the
-application writer wants to provide their own implementation of
-vPortSetupTimerInterrupt().  Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
-is defined. */
-#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
-		#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
-#endif
-
-/* Manual definition of missing asm names. */
-#define psp 	9
-#define basepri	17
-#define msp		8
-#define ipsr	5
-#define control	20
-
-/* From port.c. */
-extern void *pxCurrentTCB;
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void );
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvPortStartFirstTask( void );
-
-/*
- * Function to enable the VFP.
- */
- static void vPortEnableVFP( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-
-	/* Offset added to account for the way the MCU uses the stack on entry/exit
-	of interrupts, and to ensure alignment. */
-	pxTopOfStack--;
-
-	/* Sometimes the parameters are loaded from the stack. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;
-	pxTopOfStack--;
-
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-
-	/* Save code space by skipping register initialisation. */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-
-	/* A save method is being used that requires each task to maintain its
-	own exec return value. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void ) iv IVT_INT_SVCall ics ICS_OFF
-{
-	__asm {
-			ldr r3, =_pxCurrentTCB  /* Restore the context. */
-			ldr r1, [r3]			/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
-			ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
-			ldm r0!, (r4-r11, r14)/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
-			msr psp, r0				/* Restore the task stack pointer. */
-			isb
-			mov r0, #0
-			msr basepri, r0
-			bx r14
-	};
-}
-/*-----------------------------------------------------------*/
-
-static void prvPortStartFirstTask( void )
-{
-	__asm {
-				ldr r0, =0xE000ED08	 /* Use the NVIC offset register to locate the stack. */
-				ldr r0, [r0]
-				ldr r0, [r0]
-				msr msp, r0			 /* Set the msp back to the start of the stack. */
-				/* Clear the bit that indicates the FPU is in use in case the FPU was used
-				before the scheduler was started - which would otherwise result in the
-				unnecessary leaving of space in the SVC stack for lazy saving of FPU
-				registers. */
-				mov r0, #0
-				msr control, r0
-				cpsie i				 /* Globally enable interrupts. */
-				cpsie f
-				dsb
-				isb
-				svc #0					/* System call to start first task. */
-				nop
-			};
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* The kernel interrupt priority should be set to the lowest
-		priority. */
-		configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Ensure the VFP is enabled - it should be anyway. */
-	vPortEnableVFP();
-
-	/* Lazy save always. */
-	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
-	/* Start the first task. */
-	prvPortStartFirstTask();
-
-	/* Should never get here as the tasks will now be executing!  Call the task
-	exit error function to prevent compiler warnings about a static function
-	not being called in the case that the application writer overrides this
-	functionality by defining configTASK_RETURN_ADDRESS. */
-	prvTaskExitError();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-const uint8_t ucMaxSyscallInterruptPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-void xPortPendSVHandler( void ) iv IVT_INT_PendSV ics ICS_OFF
-{
-	__asm {
-#ifdef HW_DEBUG
-				/* The function is not truly naked, so add back the 4 bytes subtracted
-				from the stack pointer by the function prologue. */
-		add sp, sp, #4
-#endif
-	mrs r0, psp
-	isb
-
-	ldr	r3, =_pxCurrentTCB		 /* Get the location of the current TCB. */
-	ldr	r2, [r3]
-
-	tst r14, #0x10			 /* Is the task using the FPU context?  If so, push high vfp registers. */
-	it eq
-	vstmdbeq r0!, (s16-s31)
-
-	stmdb r0!, (r4-r11, r14)		 /* Save the core registers. */
-
-	str r0, [r2]			 /* Save the new top of stack into the first member of the TCB. */
-
-	stmdb sp!, (r0, r3)
-	ldr r0, =_ucMaxSyscallInterruptPriority
-	ldr r1, [r0]
-	msr basepri, r1
-	dsb
-	isb
-	bl _vTaskSwitchContext
-	mov r0, #0
-	msr basepri, r0
-	ldm sp!, (r0, r3)
-
-	ldr r1, [r3]			 /* The first item in pxCurrentTCB is the task top of stack. */
-	ldr r0, [r1]
-
-	ldm r0!, (r4-r11, r14)		 /* Pop the core registers. */
-
-	tst r14, #0x10			 /* Is the task using the FPU context?  If so, pop the high vfp registers too. */
-	it eq
-	vldmiaeq r0!, (s16-s31)
-
-	msr psp, r0
-	isb
-	bx r14
-	}
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void ) iv IVT_INT_SysTick ics ICS_AUTO
-{
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known - therefore the slightly faster portDISABLE_INTERRUPTS() function is
-	used in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
-	portDISABLE_INTERRUPTS();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_TICKLESS_IDLE == 1 ) && ( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 ) )
-
-	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-	TickType_t xModifiableIdleTime;
-
-		/* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
-		is accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-		/* Calculate the reload value required to wait xExpectedIdleTime
-		tick periods.  -1 is used because this code will execute part way
-		through one of the tick periods. */
-		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-		if( ulReloadValue > ulStoppedTimerCompensation )
-		{
-			ulReloadValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Enter a critical section but don't use the taskENTER_CRITICAL()
-		method as that will mask interrupts that should exit sleep mode. */
-		__asm { "cpsid i" };
-		__asm { "dsb" };
-		__asm { "isb" };
-
-		/* If a context switch is pending or a task is waiting for the scheduler
-		to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-		{
-			/* Restart from whatever is left in the count register to complete
-			this tick period. */
-			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Reset the reload register to the value required for normal tick
-			periods. */
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Re-enable interrupts - see comments above the cpsid instruction()
-			above. */
-			__asm { "cpsie i" };
-		}
-		else
-		{
-			/* Set the new reload value. */
-			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-			/* Clear the SysTick count flag and set the count value back to
-			zero. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-			set its parameter to 0 to indicate that its implementation contains
-			its own wait for interrupt or wait for event instruction, and so wfi
-			should not be executed again.  However, the original expected idle
-			time variable must remain unmodified, so a copy is taken. */
-			xModifiableIdleTime = xExpectedIdleTime;
-			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-			if( xModifiableIdleTime > 0 )
-			{
-				__asm { "dsb" };
-				__asm { "wfi" };
-				__asm { "isb" };
-			}
-			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-			/* Re-enable interrupts to allow the interrupt that brought the MCU
-			out of sleep mode to execute immediately.  see comments above
-			__disable_interrupt() call above. */
-			__asm { "cpsie i" };
-			__asm { "dsb" };
-			__asm { "isb" };
-
-			/* Disable interrupts again because the clock is about to be stopped
-			and interrupts that execute while the clock is stopped will increase
-			any slippage between the time maintained by the RTOS and calendar
-			time. */
-			__asm { "cpsid i" };
-			__asm { "dsb" };
-			__asm { "isb" };
-
-			/* Disable the SysTick clock without reading the
-			portNVIC_SYSTICK_CTRL_REG register to ensure the
-			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
-			the time the SysTick is stopped for is accounted for as best it can
-			be, but using the tickless mode will inevitably result in some tiny
-			drift of the time maintained by the kernel with respect to calendar
-			time*/
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-			/* Determine if the SysTick clock has already counted to zero and
-			been set back to the current reload value (the reload back being
-			correct for the entire expected idle time) or if the SysTick is yet
-			to count to zero (in which case an interrupt other than the SysTick
-			must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-			{
-				uint32_t ulCalculatedLoadValue;
-
-				/* The tick interrupt is already pending, and the SysTick count
-				reloaded with ulReloadValue.  Reset the
-				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-				period. */
-				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-				/* Don't allow a tiny value, or values that have somehow
-				underflowed because the post sleep hook did something
-				that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-				{
-					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-				}
-
-				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-				/* As the pending tick will be processed as soon as this
-				function exits, the tick value maintained by the tick is stepped
-				forward by one less than the time spent waiting. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				Work out how long the sleep lasted rounded to complete tick
-				periods (not the ulReload value which accounted for part
-				ticks). */
-				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-				/* How many complete tick periods passed while the processor
-				was waiting? */
-				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-				/* The reload value is set to whatever fraction of a single tick
-				period remains. */
-				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-			}
-
-			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-			vTaskStepTick( ulCompleteTickPeriods );
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Exit with interrpts enabled. */
-			__asm { "cpsie i" };
-		}
-	}
-
-#endif /* #if configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-#if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
-
-	void vPortSetupTimerInterrupt( void )
-	{
-			/* Calculate the constants required to configure the tick interrupt. */
-			#if( configUSE_TICKLESS_IDLE == 1 )
-			{
-					ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-					xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-					ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-			}
-			#endif /* configUSE_TICKLESS_IDLE */
-
-			/* Reset SysTick. */
-			portNVIC_SYSTICK_CTRL_REG = 0UL;
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-			/* Configure SysTick to interrupt at the requested rate. */
-			portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-	}
-
-#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
-/*-----------------------------------------------------------*/
-
-/* This is a naked function. */
-static void vPortEnableVFP( void )
-{
-	__asm {
-			ldr r0, =0xE000ED88			 /* The FPU enable bits are in the CPACR. */
-			ldr r1, [r0]
-
-			orr r1, r1, #0xF00000		 /* Enable CP10 and CP11 coprocessors, then save back. */
-			str r1, [r0]
-			bx r14
-	};
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortIsInsideInterrupt( void )
-{
-BaseType_t xReturn;
-
-	/* Obtain the number of the currently executing interrupt. */
-	if( CPU_REG_GET( CPU_IPSR ) == 0 )
-	{
-		xReturn = pdFALSE;
-	}
-	else
-	{
-		xReturn = pdTRUE;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	/* Limitations in the MikroC inline asm means ulCurrentInterrupt has to be
-	global - which makes vPortValidateInterruptPriority() non re-entrant.
-	However that should not matter as an interrupt can only itself be
-	interrupted by a higher priority interrupt.  That means if
-	ulCurrentInterrupt, so ulCurrentInterrupt getting corrupted cannot lead to
-	an invalid interrupt priority being missed. */
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-	void vPortValidateInterruptPriority( void )
-	{
-		/* Obtain the number of the currently executing interrupt. */
-		__asm { push (r0, r1)
-				mrs r0, ipsr
-				ldr r1, =_ulCurrentInterrupt
-				str r0, [r1]
-				pop (r0, r1)
-		};
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = *( ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + ulCurrentInterrupt ) );
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
\ No newline at end of file
diff --git a/FreeRTOS/Source/portable/MikroC/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/MikroC/ARM_CM4F/portmacro.h
deleted file mode 100755
index 2118257..0000000
--- a/FreeRTOS/Source/portable/MikroC/ARM_CM4F/portmacro.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* The compiler needs to be told functions that are only referenced by pointer
-are to be included in the build.  NOTE:  Omitting these lines will result in a
-run-time crash, not a linker error! */
-#pragma funcall vTaskStartScheduler prvIdleTask
-#pragma funcall xTimerCreateTimerTask prvTimerTask
-
-/* Type definitions. */
-#define portCHAR        char
-#define portFLOAT        float
-#define portDOUBLE        double
-#define portLONG        long
-#define portSHORT        short
-#define portSTACK_TYPE    uint32_t
-#define portBASE_TYPE    long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-    typedef uint16_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-    typedef uint32_t TickType_t;
-    #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-    /* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-    not need to be guarded with a critical section. */
-    #define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH            ( -1 )
-#define portTICK_PERIOD_MS            ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT            8
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD()                                                             \
-{                                                                                \
-    /* Set a PendSV to request a context switch. */                                \
-    portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;                                \
-                                                                                \
-    /* Barriers are normally not required but do ensure the code is completely    \
-    within the specified behaviour for the architecture. */                        \
-  __asm{ dsb  };                       \
-  __asm{ isb };                      \
-}
-
-#define portNVIC_INT_CTRL_REG        ( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT        ( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-#define portDISABLE_INTERRUPTS()                CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY ); __asm{ dsb }; __asm{ isb }
-#define portENABLE_INTERRUPTS()                    CPU_REG_SET( CPU_BASEPRI, 0 );
-#define portENTER_CRITICAL()                    vPortEnterCritical()
-#define portEXIT_CRITICAL()                        vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()        ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)    CPU_REG_SET( CPU_BASEPRI, x ); /* Barrier instructions not used as this is only used to lower the basepri. */
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-    extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-    #define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-    #define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-    /* Generic helper function. */
-    __attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
-    {
-    uint8_t ucReturn;
-
-        __asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
-        return ucReturn;
-    }
-
-    /* Check the configuration. */
-    #if( configMAX_PRIORITIES > 32 )
-        #error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-    #endif
-
-    /* Store/clear the ready priorities in a bit map. */
-    #define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-    #define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-    /*-----------------------------------------------------------*/
-
-    #define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-    void vPortValidateInterruptPriority( void );
-    #define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()     vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-BaseType_t xPortIsInsideInterrupt( void );
-
-/*-----------------------------------------------------------*/
-
-static inline uint32_t ulPortRaiseBASEPRI( void )
-{
-uint32_t ulOriginalBASEPRI;
-
-	ulOriginalBASEPRI = CPU_REG_GET( CPU_BASEPRI );
-	CPU_REG_SET( CPU_BASEPRI, configMAX_SYSCALL_INTERRUPT_PRIORITY );
-	__asm{ dsb };
-	__asm{ isb };
-	return ulOriginalBASEPRI;
-}
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
\ No newline at end of file
diff --git a/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/port.c b/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/port.c
deleted file mode 100755
index 51f44f8..0000000
--- a/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/port.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Tern EE 186
- * port.
- *----------------------------------------------------------*/
-
-/* Library includes. */
-#include 
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "portasm.h"
-
-/* The timer increments every four clocks, hence the divide by 4. */
-#define portTIMER_COMPARE ( uint16_t ) ( ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) / ( uint32_t ) 4 )
-
-/* From the RDC data sheet. */
-#define portENABLE_TIMER_AND_INTERRUPT ( uint16_t ) 0xe001
-
-/* Interrupt control. */
-#define portEIO_REGISTER 0xff22
-#define portCLEAR_INTERRUPT 0x0008
-
-/* Setup the hardware to generate the required tick frequency. */
-static void prvSetupTimerInterrupt( void );
-
-/* The ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if( configUSE_PREEMPTION == 1 )
-	/* Tick service routine used by the scheduler when preemptive scheduling is
-	being used. */
-	static void __interrupt __far prvPreemptiveTick( void );
-#else
-	/* Tick service routine used by the scheduler when cooperative scheduling is
-	being used. */
-	static void __interrupt __far prvNonPreemptiveTick( void );
-#endif
-
-/* Trap routine used by taskYIELD() to manually cause a context switch. */
-static void __interrupt __far prvYieldProcessor( void );
-
-/* The timer initialisation functions leave interrupts enabled,
-which is not what we want.  This ISR is installed temporarily in case
-the timer fires before we get a change to disable interrupts again. */
-static void __interrupt __far prvDummyISR( void );
-
-/*-----------------------------------------------------------*/
-/* See header file for description. */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t DS_Reg = 0;
-
-	/* Place a few bytes of known values on the bottom of the stack.
-	This is just useful for debugging. */
-
-	*pxTopOfStack = 0x1111;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2222;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x3333;
-	pxTopOfStack--;
-
-	/* We are going to start the scheduler using a return from interrupt
-	instruction to load the program counter, so first there would be the
-	function call with parameters preamble. */
-	
-	*pxTopOfStack = FP_SEG( pvParameters );
-	pxTopOfStack--;
-	*pxTopOfStack = FP_OFF( pvParameters );
-	pxTopOfStack--;
-	*pxTopOfStack = FP_SEG( pxCode );
-	pxTopOfStack--;
-	*pxTopOfStack = FP_OFF( pxCode );
-	pxTopOfStack--;
-
-	/* Next the status register and interrupt return address. */
-	*pxTopOfStack = portINITIAL_SW;
-	pxTopOfStack--;
-	*pxTopOfStack = FP_SEG( pxCode );
-	pxTopOfStack--;
-	*pxTopOfStack = FP_OFF( pxCode );
-	pxTopOfStack--;
-
-	/* The remaining registers would be pushed on the stack by our context
-	switch function.  These are loaded with values simply to make debugging
-	easier. */
-	*pxTopOfStack = ( StackType_t ) 0xAAAA;	/* AX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xCCCC;	/* CX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xEEEE;	/* ES */
-	pxTopOfStack--;
-
-	/* We need the true data segment. */
-	__asm{	MOV DS_Reg, DS };
-
-	*pxTopOfStack = DS_Reg;						/* DS */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x0123;	/* SI */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DI */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BP */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* This is called with interrupts already disabled. */
-
-	/* Put our manual switch (yield) function on a known
-	vector. */
-	setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
-
-	/* Setup the tick interrupt. */
-	prvSetupTimerInterrupt();
-
-	/* Kick off the scheduler by setting up the context of the first task. */
-	portFIRST_CONTEXT();
-
-	/* Should not get here! */
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-static void __interrupt __far prvDummyISR( void )
-{
-	/* The timer initialisation functions leave interrupts enabled,
-	which is not what we want.  This ISR is installed temporarily in case
-	the timer fires before we get a change to disable interrupts again. */
-	outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
-}
-/*-----------------------------------------------------------*/
-
-/* The ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if( configUSE_PREEMPTION == 1 )
-	static void __interrupt __far prvPreemptiveTick( void )
-	{
-		/* Get the scheduler to update the task states following the tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Switch in the context of the next task to be run. */
-			portSWITCH_CONTEXT();
-		}
-
-		/* Reset interrupt. */
-		outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
-	}
-#else
-	static void __interrupt __far prvNonPreemptiveTick( void )
-	{
-		/* Same as preemptive tick, but the cooperative scheduler is being used
-		so we don't have to switch in the context of the next task. */
-		xTaskIncrementTick();
-		
-		/* Reset interrupt. */
-		outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-static void __interrupt __far prvYieldProcessor( void )
-{
-	/* Switch in the context of the next task to be run. */
-	portSWITCH_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-const uint16_t usTimerACompare = portTIMER_COMPARE, usTimerAMode = portENABLE_TIMER_AND_INTERRUPT;
-const uint16_t usT2_IRQ = 0x13;
-
-	/* Configure the timer, the dummy handler is used here as the init
-	function leaves interrupts enabled. */
-	t2_init( usTimerAMode, usTimerACompare, prvDummyISR );
-
-	/* Disable interrupts again before installing the real handlers. */
-	portDISABLE_INTERRUPTS();
-
-	#if( configUSE_PREEMPTION == 1 )
-		/* Tick service routine used by the scheduler when preemptive scheduling is
-		being used. */
-		setvect( usT2_IRQ, prvPreemptiveTick );
-	#else
-		/* Tick service routine used by the scheduler when cooperative scheduling is
-		being used. */
-		setvect( usT2_IRQ, prvNonPreemptiveTick );
-	#endif
-}
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h b/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h
deleted file mode 100755
index 6539159..0000000
--- a/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portasm.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-extern void vTaskSwitchContext( void );
-
-/*
- * Saves the stack pointer for one task into its TCB, calls
- * vTaskSwitchContext() to update the TCB being used, then restores the stack
- * from the new TCB read to run the task.
- */
-void portSWITCH_CONTEXT( void );
-
-/*
- * Load the stack pointer from the TCB of the task which is going to be first
- * to execute.  Then force an IRET so the registers and IP are popped off the
- * stack.
- */
-void portFIRST_CONTEXT( void );
-
-#define portSWITCH_CONTEXT()										 \
-						asm { mov	ax, seg pxCurrentTCB		} \
-							asm { mov	ds, ax						}  \
-							asm { les	bx, pxCurrentTCB			}	/* Save the stack pointer into the TCB. */    \
-							asm { mov	es:0x2[ bx ], ss			}   \
-							asm { mov	es:[ bx ], sp				}   \
-							asm { call  far ptr vTaskSwitchContext	}	/* Perform the switch. */   \
-							asm { mov	ax, seg pxCurrentTCB		}	/* Restore the stack pointer from the TCB. */  \
-							asm { mov	ds, ax						}   \
-							asm { les	bx, dword ptr pxCurrentTCB	}   \
-							asm { mov	ss, es:[ bx + 2 ]			}      \
-							asm { mov	sp, es:[ bx ]				}
-
-#define portFIRST_CONTEXT()												\
-							asm { mov	ax, seg pxCurrentTCB		}	\
-							asm { mov	ds, ax						}	\
-							asm { les	bx, dword ptr pxCurrentTCB	}	\
-							asm { mov	ss, es:[ bx + 2 ]			}	\
-							asm { mov	sp, es:[ bx ]				}	\
-							asm { pop	bp							}	\
-							asm { pop	di							}	\
-							asm { pop	si							}	\
-							asm { pop	ds							}	\
-							asm { pop	es							}	\
-							asm { pop	dx							}	\
-							asm { pop	cx							}	\
-							asm { pop	bx							}	\
-							asm { pop	ax							}	\
-							asm { iret								}
-
-
diff --git a/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h b/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h
deleted file mode 100755
index 3b0d305..0000000
--- a/FreeRTOS/Source/portable/Paradigm/Tern_EE/large_untested/portmacro.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		long
-#define portLONG		long
-#define portSHORT		int
-#define portSTACK_TYPE	uint16_t
-#define portBASE_TYPE	short
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-#define portENTER_CRITICAL()			__asm{ pushf }  \
-										__asm{ cli 	 }	\
-
-#define portEXIT_CRITICAL()				__asm{ popf }
-
-#define portDISABLE_INTERRUPTS()		__asm{ cli }
-
-#define portENABLE_INTERRUPTS()			__asm{ sti }
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portNOP()						__asm{ nop }
-#define portSTACK_GROWTH				( -1 )
-#define portSWITCH_INT_NUMBER 			0x80
-#define portYIELD()						__asm{ int portSWITCH_INT_NUMBER }
-#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT				2
-#define portINITIAL_SW					( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
-/*-----------------------------------------------------------*/
-
-/* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )				inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
-#define portINPUT_WORD( xAddr )				inpw( xAddr )
-#define portOUTPUT_WORD( xAddr, usValue )	outpw( xAddr, usValue )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/port.c b/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/port.c
deleted file mode 100755
index bfb22f7..0000000
--- a/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/port.c
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Tern EE 186
- * port.
- *----------------------------------------------------------*/
-
-/* Library includes. */
-#include 
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "portasm.h"
-
-/* The timer increments every four clocks, hence the divide by 4. */
-#define portPRESCALE_VALUE ( 16 )
-#define portTIMER_COMPARE ( configCPU_CLOCK_HZ  / ( configTICK_RATE_HZ * 4UL ) )
-
-/* From the RDC data sheet. */
-#define portENABLE_TIMER_AND_INTERRUPT 	( uint16_t ) 0xe00b
-#define portENABLE_TIMER				( uint16_t ) 0xC001
-
-/* Interrupt control. */
-#define portEIO_REGISTER 0xff22
-#define portCLEAR_INTERRUPT 0x0008
-
-/* Setup the hardware to generate the required tick frequency. */
-static void prvSetupTimerInterrupt( void );
-
-/* The ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if( configUSE_PREEMPTION == 1 )
-	/* Tick service routine used by the scheduler when preemptive scheduling is
-	being used. */
-	static void __interrupt __far prvPreemptiveTick( void );
-#else
-	/* Tick service routine used by the scheduler when cooperative scheduling is
-	being used. */
-	static void __interrupt __far prvNonPreemptiveTick( void );
-#endif
-
-/* Trap routine used by taskYIELD() to manually cause a context switch. */
-static void __interrupt __far prvYieldProcessor( void );
-
-/*-----------------------------------------------------------*/
-/* See header file for description. */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t DS_Reg = 0;
-
-	/* We need the true data segment. */
-	__asm{	MOV DS_Reg, DS };
-
-	/* Place a few bytes of known values on the bottom of the stack.
-	This is just useful for debugging. */
-
-	*pxTopOfStack = 0x1111;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2222;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x3333;
-	pxTopOfStack--;
-
-	/* We are going to start the scheduler using a return from interrupt
-	instruction to load the program counter, so first there would be the
-	function call with parameters preamble. */
-	
-	*pxTopOfStack = FP_OFF( pvParameters );
-	pxTopOfStack--;
-	*pxTopOfStack = FP_OFF( pxCode );
-	pxTopOfStack--;
-
-	/* Next the status register and interrupt return address. */
-	*pxTopOfStack = portINITIAL_SW;
-	pxTopOfStack--;
-	*pxTopOfStack = FP_SEG( pxCode );
-	pxTopOfStack--;
-	*pxTopOfStack = FP_OFF( pxCode );
-	pxTopOfStack--;
-
-	/* The remaining registers would be pushed on the stack by our context
-	switch function.  These are loaded with values simply to make debugging
-	easier. */
-	*pxTopOfStack = ( StackType_t ) 0xAAAA;	/* AX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xCCCC;	/* CX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xEEEE;	/* ES */
-	pxTopOfStack--;
-
-	*pxTopOfStack = DS_Reg;						/* DS */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x0123;	/* SI */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DI */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BP */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* This is called with interrupts already disabled. */
-
-	/* Put our manual switch (yield) function on a known
-	vector. */
-	setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
-
-	/* Setup the tick interrupt. */
-	prvSetupTimerInterrupt();
-
-	/* Kick off the scheduler by setting up the context of the first task. */
-	portFIRST_CONTEXT();
-
-	/* Should not get here! */
-	return pdFALSE;
-}
-/*-----------------------------------------------------------*/
-
-/* The ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if( configUSE_PREEMPTION == 1 )
-	static void __interrupt __far prvPreemptiveTick( void )
-	{
-		/* Get the scheduler to update the task states following the tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Switch in the context of the next task to be run. */
-			portEND_SWITCHING_ISR();
-		}
-
-		/* Reset interrupt. */
-		outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
-	}
-#else
-	static void __interrupt __far prvNonPreemptiveTick( void )
-	{
-		/* Same as preemptive tick, but the cooperative scheduler is being used
-		so we don't have to switch in the context of the next task. */
-		xTaskIncrementTick();
-		
-		/* Reset interrupt. */
-		outport( portEIO_REGISTER, portCLEAR_INTERRUPT );
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-static void __interrupt __far prvYieldProcessor( void )
-{
-	/* Switch in the context of the next task to be run. */
-	portEND_SWITCHING_ISR();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-const uint32_t ulCompareValue = portTIMER_COMPARE;
-uint16_t usTimerCompare;
-
-	usTimerCompare = ( uint16_t ) ( ulCompareValue >> 4 );
-    t2_init( portENABLE_TIMER, portPRESCALE_VALUE, NULL );
-
-	#if( configUSE_PREEMPTION == 1 )
-		/* Tick service routine used by the scheduler when preemptive scheduling is
-		being used. */
-		t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvPreemptiveTick );
-	#else
-		/* Tick service routine used by the scheduler when cooperative scheduling is
-		being used. */
-		t1_init( portENABLE_TIMER_AND_INTERRUPT, usTimerCompare, usTimerCompare, prvNonPreemptiveTick );
-	#endif
-}
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portasm.h b/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portasm.h
deleted file mode 100755
index 0b6d3b5..0000000
--- a/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portasm.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORT_ASM_H
-#define PORT_ASM_H
-
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-extern void vTaskSwitchContext( void );
-
-/*
- * Saves the stack pointer for one task into its TCB, calls
- * vTaskSwitchContext() to update the TCB being used, then restores the stack
- * from the new TCB read to run the task.
- */
-void portEND_SWITCHING_ISR( void );
-
-/*
- * Load the stack pointer from the TCB of the task which is going to be first
- * to execute.  Then force an IRET so the registers and IP are popped off the
- * stack.
- */
-void portFIRST_CONTEXT( void );
-
-#define portEND_SWITCHING_ISR()											\
-							asm { mov	bx, [pxCurrentTCB]			}   \
-                            asm { mov	word ptr [bx], sp			}	\
-							asm { call  far ptr vTaskSwitchContext	}	\
-							asm { mov	bx, [pxCurrentTCB]			}	\
-							asm { mov	sp, [bx]					}
-
-#define portFIRST_CONTEXT()											\
-							asm { mov	bx, [pxCurrentTCB]			}	\
-							asm { mov	sp, [bx]					}	\
-							asm { pop	bp							}	\
-							asm { pop	di							}	\
-							asm { pop	si							}	\
-   							asm { pop	ds							}	\
-   							asm { pop	es							}	\
-							asm { pop	dx							}	\
-							asm { pop	cx							}	\
-							asm { pop	bx							}	\
-							asm { pop	ax							}	\
-							asm { iret								}
-
-
-#endif
-
diff --git a/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portmacro.h b/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portmacro.h
deleted file mode 100755
index 7dfb258..0000000
--- a/FreeRTOS/Source/portable/Paradigm/Tern_EE/small/portmacro.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		long
-#define portLONG		long
-#define portSHORT		int
-#define portSTACK_TYPE	uint16_t
-#define portBASE_TYPE	short
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-
-typedef void ( __interrupt __far *pxISR )();
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-#define portENTER_CRITICAL()			__asm{ pushf }  \
-										__asm{ cli 	 }	\
-
-#define portEXIT_CRITICAL()				__asm{ popf }
-
-#define portDISABLE_INTERRUPTS()		__asm{ cli }
-
-#define portENABLE_INTERRUPTS()			__asm{ sti }
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portNOP()						__asm{ nop }
-#define portSTACK_GROWTH				( -1 )
-#define portSWITCH_INT_NUMBER 			0x80
-#define portYIELD()						__asm{ int portSWITCH_INT_NUMBER }
-#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT				2
-#define portINITIAL_SW					( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
-/*-----------------------------------------------------------*/
-
-/* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )				inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
-#define portINPUT_WORD( xAddr )				inpw( xAddr )
-#define portOUTPUT_WORD( xAddr, usValue )	outpw( xAddr, usValue )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, vParameters ) void vTaskFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/port.c b/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/port.c
deleted file mode 100755
index 32803cb..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/port.c
+++ /dev/null
@@ -1,291 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portINSTRUCTION_SIZE			( ( StackType_t ) 4 )
-#define portNO_CRITICAL_SECTION_NESTING	( ( StackType_t ) 0 )
-
-/* Constants required to setup the tick ISR. */
-#define portENABLE_TIMER			( ( uint8_t ) 0x01 )
-#define portPRESCALE_VALUE			0x00
-#define portINTERRUPT_ON_MATCH		( ( uint32_t ) 0x01 )
-#define portRESET_COUNT_ON_MATCH	( ( uint32_t ) 0x02 )
-
-/* Constants required to setup the VIC for the tick ISR. */
-#define portTIMER_VIC_CHANNEL		( ( uint32_t ) 0x0004 )
-#define portTIMER_VIC_CHANNEL_BIT	( ( uint32_t ) 0x0010 )
-#define portTIMER_VIC_ENABLE		( ( uint32_t ) 0x0020 )
-
-/* Constants required to handle interrupts. */
-#define portTIMER_MATCH_ISR_BIT		( ( uint8_t ) 0x01 )
-#define portCLEAR_VIC_INTERRUPT		( ( uint32_t ) 0 )
-
-/*-----------------------------------------------------------*/
-
-/* The code generated by the Keil compiler does not maintain separate
-stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
-use the stack as per other ports.  Instead a variable is used to keep
-track of the critical section nesting.  This variable has to be stored
-as part of the task context and must be initialised to a non zero value. */
-
-#define portNO_CRITICAL_NESTING		( ( uint32_t ) 0 )
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/*-----------------------------------------------------------*/
-
-/* Setup the timer to generate the tick interrupts. */
-static void prvSetupTimerInterrupt( void );
-
-/* 
- * The scheduler can only be started from ARM mode, so 
- * vPortStartFirstSTask() is defined in portISR.c. 
- */
-extern __asm void vPortStartFirstTask( void );
-
-/*-----------------------------------------------------------*/
-
-/* 
- * See header file for description. 
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t *pxOriginalTOS;
-
-	/* Setup the initial stack of the task.  The stack is set exactly as 
-	expected by the portRESTORE_CONTEXT() macro.
-
-	Remember where the top of the (simulated) stack is before we place 
-	anything on it. */
-	pxOriginalTOS = pxTopOfStack;
-	
-	/* To ensure asserts in tasks.c don't fail, although in this case the assert
-	is not really required. */
-	pxTopOfStack--;
-
-	/* First on the stack is the return address - which in this case is the
-	start of the task.  The offset is added to make the return address appear
-	as it would within an IRQ ISR. */
-	*pxTopOfStack = ( StackType_t ) pxCode + portINSTRUCTION_SIZE;		
-	pxTopOfStack--;
-
-	*pxTopOfStack = ( StackType_t ) 0xaaaaaaaa;	/* R14 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) pxOriginalTOS; /* Stack used when task starts goes in R13. */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The last thing onto the stack is the status register, which is set for
-	system mode, with interrupts enabled. */
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	if( ( ( uint32_t ) pxCode & 0x01UL ) != 0x00UL )
-	{
-		/* We want the task to start in thumb mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-
-	pxTopOfStack--;
-
-	/* The code generated by the Keil compiler does not maintain separate
-	stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
-	use the stack as per other ports.  Instead a variable is used to keep
-	track of the critical section nesting.  This variable has to be stored
-	as part of the task context and is initially set to zero. */
-	*pxTopOfStack = portNO_CRITICAL_SECTION_NESTING;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Start the timer that generates the tick ISR. */
-	prvSetupTimerInterrupt();
-
-	/* Start the first task.  This is done from portISR.c as ARM mode must be
-	used. */
-	vPortStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the ARM port will require this function as there
-	is nothing to return to.  If this is required - stop the tick ISR then
-	return back to main. */
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_PREEMPTION == 0
-
-	/* 
-	 * The cooperative scheduler requires a normal IRQ service routine to 
-	 * simply increment the system tick. 
-	 */
-	void vNonPreemptiveTick( void ) __irq;
-	void vNonPreemptiveTick( void ) __irq
-	{
-		/* Increment the tick count - this may make a delaying task ready
-		to run - but a context switch is not performed. */		
-		xTaskIncrementTick();
-
-		T0IR = portTIMER_MATCH_ISR_BIT;				/* Clear the timer event */
-		VICVectAddr = portCLEAR_VIC_INTERRUPT;		/* Acknowledge the Interrupt */
-	}
-
- #else
-
-	/*
-	 **************************************************************************
-	 * The preemptive scheduler ISR is written in assembler and can be found   
-	 * in the portASM.s file. This will only get used if portUSE_PREEMPTION
-	 * is set to 1 in portmacro.h
-	 ************************************************************************** 
-	 */
-
-	  void vPreemptiveTick( void );
-
-#endif
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-uint32_t ulCompareMatch;
-
-	/* A 1ms tick does not require the use of the timer prescale.  This is
-	defaulted to zero but can be used if necessary. */
-	T0PR = portPRESCALE_VALUE;
-
-	/* Calculate the match value required for our wanted tick rate. */
-	ulCompareMatch = configCPU_CLOCK_HZ / configTICK_RATE_HZ;
-
-	/* Protect against divide by zero.  Using an if() statement still results
-	in a warning - hence the #if. */
-	#if portPRESCALE_VALUE != 0
-	{
-		ulCompareMatch /= ( portPRESCALE_VALUE + 1 );
-	}
-	#endif
-
-	T0MR0 = ulCompareMatch;
-
-	/* Generate tick with timer 0 compare match. */
-	T0MCR = portRESET_COUNT_ON_MATCH | portINTERRUPT_ON_MATCH;
-
-	/* Setup the VIC for the timer. */
-	VICIntSelect &= ~( portTIMER_VIC_CHANNEL_BIT );
-	VICIntEnable |= portTIMER_VIC_CHANNEL_BIT;
-	
-	/* The ISR installed depends on whether the preemptive or cooperative
-	scheduler is being used. */
-	#if configUSE_PREEMPTION == 1
-	{	
-		VICVectAddr0 = ( uint32_t ) vPreemptiveTick;
-	}
-	#else
-	{
-		VICVectAddr0 = ( uint32_t ) vNonPreemptiveTick;
-	}
-	#endif
-
-	VICVectCntl0 = portTIMER_VIC_CHANNEL | portTIMER_VIC_ENABLE;
-
-	/* Start the timer - interrupts are disabled when this function is called
-	so it is okay to do this here. */
-	T0TCR = portENABLE_TIMER;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 							*/
-	__disable_irq();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed 
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as we are leaving a critical section. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then interrupts should be
-		re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Enable interrupts as per portEXIT_CRITICAL(). */
-			__enable_irq();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portASM.s b/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portASM.s
deleted file mode 100755
index 972ffda..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portASM.s
+++ /dev/null
@@ -1,124 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	INCLUDE portmacro.inc
-
-	IMPORT	vTaskSwitchContext
-	IMPORT	xTaskIncrementTick
-
-	EXPORT	vPortYieldProcessor
-	EXPORT	vPortStartFirstTask
-	EXPORT	vPreemptiveTick
-	EXPORT	vPortYield
-
-
-VICVECTADDR	EQU	0xFFFFF030
-T0IR		EQU	0xE0004000
-T0MATCHBIT	EQU	0x00000001
-
-	ARM
-	AREA	PORT_ASM, CODE, READONLY
-
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Starting the first task is done by just restoring the context
-; setup by pxPortInitialiseStack
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortStartFirstTask
-
-	PRESERVE8
-
-	portRESTORE_CONTEXT
-
-vPortYield
-
-	PRESERVE8
-
-	SVC 0
-	bx lr
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Interrupt service routine for the SWI interrupt.  The vector table is
-; configured in the startup.s file.
-;
-; vPortYieldProcessor() is used to manually force a context switch.  The
-; SWI interrupt is generated by a call to taskYIELD() or portYIELD().
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-vPortYieldProcessor
-
-	PRESERVE8
-
-	; Within an IRQ ISR the link register has an offset from the true return
-	; address, but an SWI ISR does not.  Add the offset manually so the same
-	; ISR return code can be used in both cases.
-	ADD	LR, LR, #4
-
-	; Perform the context switch.
-	portSAVE_CONTEXT					; Save current task context
-	LDR R0, =vTaskSwitchContext			; Get the address of the context switch function
-	MOV LR, PC							; Store the return address
-	BX	R0								; Call the contedxt switch function
-	portRESTORE_CONTEXT					; restore the context of the selected task
-
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Interrupt service routine for preemptive scheduler tick timer
-; Only used if portUSE_PREEMPTION is set to 1 in portmacro.h
-;
-; Uses timer 0 of LPC21XX Family
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-vPreemptiveTick
-
-	PRESERVE8
-
-	portSAVE_CONTEXT					; Save the context of the current task.
-
-	LDR R0, =xTaskIncrementTick			; Increment the tick count.
-	MOV LR, PC							; This may make a delayed task ready
-	BX R0								; to run.
-
-	CMP R0, #0
-	BEQ SkipContextSwitch
-	LDR R0, =vTaskSwitchContext			; Find the highest priority task that
-	MOV LR, PC							; is ready to run.
-	BX R0
-SkipContextSwitch
-	MOV R0, #T0MATCHBIT					; Clear the timer event
-	LDR R1, =T0IR
-	STR R0, [R1]
-
-	LDR	R0, =VICVECTADDR				; Acknowledge the interrupt
-	STR	R0,[R0]
-
-	portRESTORE_CONTEXT					; Restore the context of the highest
-										; priority task that is ready to run.
-	END
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.h b/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.h
deleted file mode 100755
index e8e7b5b..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/*-----------------------------------------------------------
- * ISR entry and exit macros.  These are only required if a task switch
- * is required from an ISR.
- *----------------------------------------------------------*/
-
-/* If a switch is required then we just need to call */
-/* vTaskSwitchContext() as the context has already been */
-/* saved. */
-
-#define portEXIT_SWITCHING_ISR(SwitchRequired)				 \
-{															 \
-extern void vTaskSwitchContext(void);						 \
-															 \
-		if(SwitchRequired)									 \
-		{													 \
-			vTaskSwitchContext();							 \
-		}													 \
-}															 \
-
-extern void vPortYield( void );
-#define portYIELD() vPortYield()
-
-
-/* Critical section management. */
-
-/*
- ******************************************************************
- * We don't need to worry about whether we're in ARM or
- * THUMB mode with the Keil Real View compiler when enabling
- * or disabling interrupts as the compiler's intrinsic functions
- * take care of that for us.
- *******************************************************************
- */
-#define portDISABLE_INTERRUPTS()	__disable_irq()
-#define portENABLE_INTERRUPTS()		__enable_irq()
-
-
-/*-----------------------------------------------------------
- * Critical section control
- *
- * The code generated by the Keil compiler does not maintain separate
- * stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
- * use the stack as per other ports.  Instead a variable is used to keep
- * track of the critical section nesting.  This necessitates the use of a
- * function in place of the macro.
- *----------------------------------------------------------*/
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portENTER_CRITICAL()		vPortEnterCritical();
-#define portEXIT_CRITICAL()			vPortExitCritical();
-/*-----------------------------------------------------------*/
-
-/* Compiler specifics. */
-#define inline
-#define register
-#define portNOP()	__asm{ NOP }
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.inc b/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.inc
deleted file mode 100755
index 1d0ee67..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM7_LPC21xx/portmacro.inc
+++ /dev/null
@@ -1,91 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	IMPORT  ulCriticalNesting		;
-	IMPORT	pxCurrentTCB			;
-
-
-	MACRO
-	portRESTORE_CONTEXT
-
-
-	LDR		R0, =pxCurrentTCB		; Set the LR to the task stack.  The location was...
-	LDR		R0, [R0]				; ... stored in pxCurrentTCB
-	LDR		LR, [R0]
-
-	LDR		R0, =ulCriticalNesting	; The critical nesting depth is the first item on...
-	LDMFD	LR!, {R1}				; ...the stack.  Load it into the ulCriticalNesting var.
-	STR		R1, [R0]				;
-
-	LDMFD	LR!, {R0}				; Get the SPSR from the stack.
-	MSR		SPSR_cxsf, R0			;
-
-	LDMFD	LR, {R0-R14}^			; Restore all system mode registers for the task.
-	NOP								;
-
-	LDR		LR, [LR, #+60]			; Restore the return address
-
-									; And return - correcting the offset in the LR to obtain ...
-	SUBS	PC, LR, #4				; ...the correct address.
-
-	MEND
-
-; /**********************************************************************/
-
-	MACRO
-	portSAVE_CONTEXT
-
-
-	STMDB 	SP!, {R0}				; Store R0 first as we need to use it.
-
-	STMDB	SP,{SP}^				; Set R0 to point to the task stack pointer.
-	NOP								;
-	SUB		SP, SP, #4				;
-	LDMIA	SP!,{R0}				;
-
-	STMDB	R0!, {LR}				; Push the return address onto the stack.
-	MOV		LR, R0					; Now we have saved LR we can use it instead of R0.
-	LDMIA	SP!, {R0}				; Pop R0 so we can save it onto the system mode stack.
-
-	STMDB	LR,{R0-LR}^				; Push all the system mode registers onto the task stack.
-	NOP								;
-	SUB		LR, LR, #60				;
-
-	MRS		R0, SPSR				; Push the SPSR onto the task stack.
-	STMDB	LR!, {R0}				;
-
-	LDR		R0, =ulCriticalNesting	;
-	LDR		R0, [R0]				;
-	STMDB	LR!, {R0}				;
-
-	LDR		R0, =pxCurrentTCB		; Store the new top of stack for the task.
-	LDR		R1, [R0]				;
-	STR		LR, [R1]				;
-
-	MEND
-
-	END
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CA9/port.c b/FreeRTOS/Source/portable/RVDS/ARM_CA9/port.c
deleted file mode 100755
index 48205d1..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CA9/port.c
+++ /dev/null
@@ -1,480 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef configINTERRUPT_CONTROLLER_BASE_ADDRESS
-	#error configINTERRUPT_CONTROLLER_BASE_ADDRESS must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET
-	#error configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configUNIQUE_INTERRUPT_PRIORITIES
-	#error configUNIQUE_INTERRUPT_PRIORITIES must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#ifndef configSETUP_TICK_INTERRUPT
-	#error configSETUP_TICK_INTERRUPT() must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif /* configSETUP_TICK_INTERRUPT */
-
-#ifndef configMAX_API_CALL_INTERRUPT_PRIORITY
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be defined.  See http://www.freertos.org/Using-FreeRTOS-on-Cortex-A-Embedded-Processors.html
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY == 0
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must not be set to 0
-#endif
-
-#if configMAX_API_CALL_INTERRUPT_PRIORITY > configUNIQUE_INTERRUPT_PRIORITIES
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be less than or equal to configUNIQUE_INTERRUPT_PRIORITIES as the lower the numeric priority value the higher the logical interrupt priority
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/* In case security extensions are implemented. */
-#if configMAX_API_CALL_INTERRUPT_PRIORITY <= ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-	#error configMAX_API_CALL_INTERRUPT_PRIORITY must be greater than ( configUNIQUE_INTERRUPT_PRIORITIES / 2 )
-#endif
-
-#ifndef configCLEAR_TICK_INTERRUPT
-	#define configCLEAR_TICK_INTERRUPT()
-#endif
-
-/* The number of bits to shift for an interrupt priority is dependent on the
-number of bits implemented by the interrupt controller. */
-#if configUNIQUE_INTERRUPT_PRIORITIES == 16
-	#define portPRIORITY_SHIFT 4
-	#define portMAX_BINARY_POINT_VALUE	3
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 32
-	#define portPRIORITY_SHIFT 3
-	#define portMAX_BINARY_POINT_VALUE	2
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 64
-	#define portPRIORITY_SHIFT 2
-	#define portMAX_BINARY_POINT_VALUE	1
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 128
-	#define portPRIORITY_SHIFT 1
-	#define portMAX_BINARY_POINT_VALUE	0
-#elif configUNIQUE_INTERRUPT_PRIORITIES == 256
-	#define portPRIORITY_SHIFT 0
-	#define portMAX_BINARY_POINT_VALUE	0
-#else
-	#error Invalid configUNIQUE_INTERRUPT_PRIORITIES setting.  configUNIQUE_INTERRUPT_PRIORITIES must be set to the number of unique priorities implemented by the target hardware
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
-
-/* In all GICs 255 can be written to the priority mask register to unmask all
-(but the lowest) interrupt priority. */
-#define portUNMASK_VALUE				( 0xFFUL )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
-
-/* Interrupt controller access addresses. */
-#define portICCPMR_PRIORITY_MASK_OFFSET  		( 0x04 )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET ( 0x0C )
-#define portICCEOIR_END_OF_INTERRUPT_OFFSET 	( 0x10 )
-#define portICCBPR_BINARY_POINT_OFFSET			( 0x08 )
-#define portICCRPR_RUNNING_PRIORITY_OFFSET		( 0x14 )
-#define portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS 		( configINTERRUPT_CONTROLLER_BASE_ADDRESS + configINTERRUPT_CONTROLLER_CPU_INTERFACE_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER 					( *( ( volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET ) ) )
-#define portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS 	( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCIAR_INTERRUPT_ACKNOWLEDGE_OFFSET )
-#define portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS 		( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCEOIR_END_OF_INTERRUPT_OFFSET )
-#define portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS 			( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCPMR_PRIORITY_MASK_OFFSET )
-#define portICCBPR_BINARY_POINT_REGISTER 					( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCBPR_BINARY_POINT_OFFSET ) ) )
-#define portICCRPR_RUNNING_PRIORITY_REGISTER 				( *( ( const volatile uint32_t * ) ( portINTERRUPT_CONTROLLER_CPU_INTERFACE_ADDRESS + portICCRPR_RUNNING_PRIORITY_OFFSET ) ) )
-
-/* Used by portASSERT_IF_INTERRUPT_PRIORITY_INVALID() when ensuring the binary
-point is zero. */
-#define portBINARY_POINT_BITS			( ( uint8_t ) 0x03 )
-
-/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, interrupts enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS			( 0x01UL )
-
-/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK			( 0x1F )
-
-/* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE				( 0x10 )
-
-/* Macro to unmask all interrupt priorities. */
-#define portCLEAR_INTERRUPT_MASK()											\
-{																			\
-	__disable_irq();														\
-	portICCPMR_PRIORITY_MASK_REGISTER = portUNMASK_VALUE;					\
-	__asm(	"DSB		\n"													\
-			"ISB		\n" );												\
-	__enable_irq();															\
-}
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing.  This function is necessarily written in
- * assembly code so is implemented in portASM.s.
- */
-extern void vPortRestoreTaskContext( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/* Used to pass constants into the ASM code.  The address at which variables are
-placed is the constant value so indirect loads in the asm code are not
-required. */
-uint32_t ulICCIAR __attribute__( ( at( portICCIAR_INTERRUPT_ACKNOWLEDGE_REGISTER_ADDRESS ) ) );
-uint32_t ulICCEOIR __attribute__( ( at( portICCEOIR_END_OF_INTERRUPT_REGISTER_ADDRESS ) ) );
-uint32_t ulICCPMR __attribute__( ( at( portICCPMR_PRIORITY_MASK_REGISTER_ADDRESS ) ) );
-uint32_t ulAsmAPIPriorityMask __attribute__( ( at( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) ) );
-
-/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
-uint32_t ulPortTaskHasFPUContext = pdFALSE;
-
-/* Set to 1 to pend a context switch from an ISR. */
-uint32_t ulPortYieldRequired = pdFALSE;
-
-/* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
-uint32_t ulPortInterruptNesting = 0UL;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro.
-
-	The fist real value on the stack is the status register, which is set for
-	system mode, with interrupts enabled.  A few NULLs are added first to ensure
-	GDB does not try decoding a non-existent return address. */
-	*pxTopOfStack = NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
-	{
-		/* The task will start in THUMB mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-
-	pxTopOfStack--;
-
-	/* Next the return address, which in this case is the start of the task. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-
-	/* Next all the registers other than the stack pointer. */
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The task will start with a critical nesting count of 0 as interrupts are
-	enabled. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-	pxTopOfStack--;
-
-	/* The task will start without a floating point context.  A task that uses
-	the floating point hardware must call vPortTaskUsesFPU() before executing
-	any floating point instructions. */
-	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( ulPortInterruptNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-uint32_t ulAPSR;
-
-	/* Only continue if the CPU is not in User mode.  The CPU must be in a
-	Privileged mode for the scheduler to start. */
-	__asm( "MRS ulAPSR, APSR" );
-	ulAPSR &= portAPSR_MODE_BITS_MASK;
-	configASSERT( ulAPSR != portAPSR_USER_MODE );
-
-	if( ulAPSR != portAPSR_USER_MODE )
-	{
-		/* Only continue if the binary point value is set to its lowest possible
-		setting.  See the comments in vPortValidateInterruptPriority() below for
-		more information. */
-		configASSERT( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE );
-
-		if( ( portICCBPR_BINARY_POINT_REGISTER & portBINARY_POINT_BITS ) <= portMAX_BINARY_POINT_VALUE )
-		{
-			/* Start the timer that generates the tick ISR. */
-			configSETUP_TICK_INTERRUPT();
-
-			__enable_irq();
-			vPortRestoreTaskContext();
-		}
-	}
-
-	/* Will only get here if vTaskStartScheduler() was called with the CPU in
-	a non-privileged mode or the binary point register was not set to its lowest
-	possible value. */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	/* Disable interrupts as per portDISABLE_INTERRUPTS(); 	*/
-	ulPortSetInterruptMask();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( ulCriticalNesting == 1 )
-	{
-		configASSERT( ulPortInterruptNesting == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as the critical section is being
-		exited. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then all interrupt
-		priorities must be re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Critical nesting has reached zero so all interrupt priorities
-			should be unmasked. */
-			portCLEAR_INTERRUPT_MASK();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void FreeRTOS_Tick_Handler( void )
-{
-	/* Set interrupt mask before altering scheduler structures.   The tick
-	handler runs at the lowest priority, so interrupts cannot already be masked,
-	so there is no need to save and restore the current mask value. */
-	__disable_irq();
-	portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-	__asm(	"DSB		\n"
-			"ISB		\n" );
-	__enable_irq();
-
-	/* Increment the RTOS tick. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		ulPortYieldRequired = pdTRUE;
-	}
-
-	/* Ensure all interrupt priorities are active again. */
-	portCLEAR_INTERRUPT_MASK();
-	configCLEAR_TICK_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortTaskUsesFPU( void )
-{
-uint32_t ulInitialFPSCR = 0;
-
-	/* A task is registering the fact that it needs an FPU context.  Set the
-	FPU flag (which is saved as part of the task context). */
-	ulPortTaskHasFPUContext = pdTRUE;
-
-	/* Initialise the floating point status register. */
-	__asm( "FMXR 	FPSCR, ulInitialFPSCR" );
-}
-/*-----------------------------------------------------------*/
-
-void vPortClearInterruptMask( uint32_t ulNewMaskValue )
-{
-	if( ulNewMaskValue == pdFALSE )
-	{
-		portCLEAR_INTERRUPT_MASK();
-	}
-}
-/*-----------------------------------------------------------*/
-
-uint32_t ulPortSetInterruptMask( void )
-{
-uint32_t ulReturn;
-
-	__disable_irq();
-	if( portICCPMR_PRIORITY_MASK_REGISTER == ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) )
-	{
-		/* Interrupts were already masked. */
-		ulReturn = pdTRUE;
-	}
-	else
-	{
-		ulReturn = pdFALSE;
-		portICCPMR_PRIORITY_MASK_REGISTER = ( uint32_t ) ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT );
-		__asm(	"DSB		\n"
-				"ISB		\n" );
-	}
-	__enable_irq();
-
-	return ulReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-		/* The following assertion will fail if a service routine (ISR) for
-		an interrupt that has been assigned a priority above
-		configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-		function.  ISR safe FreeRTOS API functions must *only* be called
-		from interrupts that have been assigned a priority at or below
-		configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-		Numerically low interrupt priority numbers represent logically high
-		interrupt priorities, therefore the priority of the interrupt must
-		be set to a value equal to or numerically *higher* than
-		configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-		FreeRTOS maintains separate thread and ISR API functions to ensure
-		interrupt entry is as fast and simple as possible.
-
-		The following links provide detailed information:
-		http://www.freertos.org/RTOS-Cortex-M3-M4.html
-		http://www.freertos.org/FAQHelp.html */
-		configASSERT( portICCRPR_RUNNING_PRIORITY_REGISTER >= ( configMAX_API_CALL_INTERRUPT_PRIORITY << portPRIORITY_SHIFT ) );
-
-		/* Priority grouping:  The interrupt controller (GIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		The priority grouping is configured by the GIC's binary point register
-		(ICCBPR).  Writting 0 to ICCBPR will ensure it is set to its lowest
-		possible value (which may be above 0). */
-		configASSERT( portICCBPR_BINARY_POINT_REGISTER <= portMAX_BINARY_POINT_VALUE );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
-
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CA9/portASM.s b/FreeRTOS/Source/portable/RVDS/ARM_CA9/portASM.s
deleted file mode 100755
index cc5772e..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CA9/portASM.s
+++ /dev/null
@@ -1,174 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	INCLUDE portmacro.inc
-
-	IMPORT	vApplicationIRQHandler
-	IMPORT	vTaskSwitchContext
-	IMPORT	ulPortYieldRequired
-	IMPORT	ulPortInterruptNesting
-	IMPORT	vTaskSwitchContext
-	IMPORT	ulICCIAR
-	IMPORT	ulICCEOIR
-
-	EXPORT	FreeRTOS_SWI_Handler
-	EXPORT  FreeRTOS_IRQ_Handler
-	EXPORT 	vPortRestoreTaskContext
-
-	ARM
-	AREA	PORT_ASM, CODE, READONLY
-
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; SVC handler is used to yield a task.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-FreeRTOS_SWI_Handler
-
-	PRESERVE8
-
-	; Save the context of the current task and select a new task to run.
-	portSAVE_CONTEXT
-	LDR R0, =vTaskSwitchContext
-	BLX	R0
-	portRESTORE_CONTEXT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; vPortRestoreTaskContext is used to start the scheduler.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-vPortRestoreTaskContext
-	; Switch to system mode
-	CPS		#SYS_MODE
-	portRESTORE_CONTEXT
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; PL390 GIC interrupt handler
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-FreeRTOS_IRQ_Handler
-
-	; Return to the interrupted instruction.
-	SUB		lr, lr, #4
-
-	; Push the return address and SPSR
-	PUSH	{lr}
-	MRS		lr, SPSR
-	PUSH	{lr}
-
-	; Change to supervisor mode to allow reentry.
-	CPS		#SVC_MODE
-
-	; Push used registers.
-	PUSH	{r0-r4, r12}
-
-	; Increment nesting count.  r3 holds the address of ulPortInterruptNesting
-	; for future use.  r1 holds the original ulPortInterruptNesting value for
-	; future use.
-	LDR		r3, =ulPortInterruptNesting
-	LDR		r1, [r3]
-	ADD		r4, r1, #1
-	STR		r4, [r3]
-
-	; Read value from the interrupt acknowledge register, which is stored in r0
-	; for future parameter and interrupt clearing use.
-	LDR 	r2, =ulICCIAR
-	LDR		r0, [r2]
-
-	; Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
-	; future use.  _RB_ Does this ever actually need to be done provided the
-	; start of the stack is 8-byte aligned?
-	MOV		r2, sp
-	AND		r2, r2, #4
-	SUB		sp, sp, r2
-
-	; Call the interrupt handler.  r4 is pushed to maintain alignment.
-	PUSH	{r0-r4, lr}
-	LDR		r1, =vApplicationIRQHandler
-	BLX		r1
-	POP		{r0-r4, lr}
-	ADD		sp, sp, r2
-
-	CPSID 	i
-
-	; Write the value read from ICCIAR to ICCEOIR
-	LDR 	r4, =ulICCEOIR
-	STR		r0, [r4]
-
-	; Restore the old nesting count
-	STR		r1, [r3]
-
-	; A context switch is never performed if the nesting count is not 0
-	CMP		r1, #0
-	BNE		exit_without_switch
-
-	; Did the interrupt request a context switch?  r1 holds the address of
-	; ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
-	; use.
-	LDR		r1, =ulPortYieldRequired
-	LDR		r0, [r1]
-	CMP		r0, #0
-	BNE		switch_before_exit
-
-exit_without_switch
-	; No context switch.  Restore used registers, LR_irq and SPSR before
-	; returning.
-	POP		{r0-r4, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	MOVS	PC, LR
-
-switch_before_exit
-	; A context swtich is to be performed.  Clear the context switch pending
-	; flag.
-	MOV		r0, #0
-	STR		r0, [r1]
-
-	; Restore used registers, LR-irq and SPSR before saving the context
-	; to the task stack.
-	POP		{r0-r4, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	portSAVE_CONTEXT
-
-	; Call the function that selects the new task to execute.
-	; vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
-	; instructions, or 8 byte aligned stack allocated data.  LR does not need
-	; saving as a new LR will be loaded by portRESTORE_CONTEXT anyway.
-	LDR		r0, =vTaskSwitchContext
-	BLX		r0
-
-	; Restore the context of, and branch to, the task selected to execute next.
-	portRESTORE_CONTEXT
-
-
-	END
-
-
-
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.h b/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.h
deleted file mode 100755
index b7483a1..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{												\
-extern uint32_t ulPortYieldRequired;			\
-												\
-	if( xSwitchRequired != pdFALSE )			\
-	{											\
-		ulPortYieldRequired = pdTRUE;			\
-	}											\
-}
-
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm( "SWI 0" );
-
-
-/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-
-/* These macros do not globally disable/enable interrupts.  They do mask off
-interrupts that have a priority below configMAX_API_CALL_INTERRUPT_PRIORITY. */
-#define portENTER_CRITICAL()		vPortEnterCritical();
-#define portEXIT_CRITICAL()			vPortExitCritical();
-#define portDISABLE_INTERRUPTS()	ulPortSetInterruptMask()
-#define portENABLE_INTERRUPTS()		vPortClearInterruptMask( 0 )
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask(x)
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
-
-/* Prototype of the FreeRTOS tick handler.  This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
-void FreeRTOS_Tick_Handler( void );
-
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
-void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31 - __clz( uxReadyPriorities ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-#define portNOP() __nop()
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.inc b/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.inc
deleted file mode 100755
index c07151d..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CA9/portmacro.inc
+++ /dev/null
@@ -1,120 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-SYS_MODE			EQU		0x1f
-SVC_MODE			EQU		0x13
-IRQ_MODE			EQU		0x12
-
-	IMPORT  ulCriticalNesting
-	IMPORT	pxCurrentTCB
-	IMPORT	ulPortTaskHasFPUContext
-	IMPORT  ulAsmAPIPriorityMask
-	IMPORT	ulICCPMR
-
-
-	MACRO
-	portSAVE_CONTEXT
-
-	; Save the LR and SPSR onto the system mode stack before switching to
-	; system mode to save the remaining system mode registers
-	SRSDB	sp!, #SYS_MODE
-	CPS		#SYS_MODE
-	PUSH	{R0-R12, R14}
-
-	; Push the critical nesting count
-	LDR		R2, =ulCriticalNesting
-	LDR		R1, [R2]
-	PUSH	{R1}
-
-	; Does the task have a floating point context that needs saving?  If
-	; ulPortTaskHasFPUContext is 0 then no.
-	LDR		R2, =ulPortTaskHasFPUContext
-	LDR		R3, [R2]
-	CMP		R3, #0
-
-	; Save the floating point context, if any
-	FMRXNE  R1,  FPSCR
-	VPUSHNE {D0-D15}
-	VPUSHNE	{D16-D31}
-	PUSHNE	{R1}
-
-	; Save ulPortTaskHasFPUContext itself
-	PUSH	{R3}
-
-	; Save the stack pointer in the TCB
-	LDR		R0, =pxCurrentTCB
-	LDR		R1, [R0]
-	STR		SP, [R1]
-
-	MEND
-
-; /**********************************************************************/
-
-	MACRO
-	portRESTORE_CONTEXT
-
-	; Set the SP to point to the stack of the task being restored.
-	LDR		R0, =pxCurrentTCB
-	LDR		R1, [R0]
-	LDR		SP, [R1]
-
-	; Is there a floating point context to restore?  If the restored
-	; ulPortTaskHasFPUContext is zero then no.
-	LDR		R0, =ulPortTaskHasFPUContext
-	POP		{R1}
-	STR		R1, [R0]
-	CMP		R1, #0
-
-	; Restore the floating point context, if any
-	POPNE	{R0}
-	VPOPNE	{D16-D31}
-	VPOPNE	{D0-D15}
-	VMSRNE  FPSCR, R0
-
-	; Restore the critical section nesting depth
-	LDR		R0, =ulCriticalNesting
-	POP		{R1}
-	STR		R1, [R0]
-
-	; Ensure the priority mask is correct for the critical nesting depth
-	LDR		R2, =ulICCPMR
-	CMP		R1, #0
-	MOVEQ	R4, #255
-	LDRNE	R4, =ulAsmAPIPriorityMask
-	STR		R4, [r2]
-
-	; Restore all system mode registers other than the SP (which is already
-	; being used)
-	POP		{R0-R12, R14}
-
-	; Return to the task code, loading CPSR on the way.
-	RFEIA	sp!
-
-	MEND
-
-	END
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c b/FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c
deleted file mode 100755
index eb1613e..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM0/port.c
+++ /dev/null
@@ -1,312 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM0 port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL			( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD			( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSTICK_CURRENT_VALUE	( ( volatile uint32_t * ) 0xe000e018 )
-#define portNVIC_INT_CTRL			( ( volatile uint32_t *) 0xe000ed04 )
-#define portNVIC_SYSPRI2			( ( volatile uint32_t *) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK		0x00000004
-#define portNVIC_SYSTICK_INT		0x00000002
-#define portNVIC_SYSTICK_ENABLE		0x00000001
-#define portNVIC_PENDSVSET			0x10000000
-#define portMIN_INTERRUPT_PRIORITY	( 255UL )
-#define portNVIC_PENDSV_PRI			( portMIN_INTERRUPT_PRIORITY << 16UL )
-#define portNVIC_SYSTICK_PRI		( portMIN_INTERRUPT_PRIORITY << 24UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR			( 0x01000000 )
-
-/* Constants used with memory barrier intrinsics. */
-#define portSY_FULL_READ_WRITE		( 15 )
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void );
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvPortStartFirstTask( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-	pxTopOfStack -= 8; /* R11..R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-void vPortSVCHandler( void )
-{
-	/* This function is no longer used, but retained for backward
-	compatibility. */
-}
-/*-----------------------------------------------------------*/
-
-__asm void prvPortStartFirstTask( void )
-{
-	extern pxCurrentTCB;
-
-	PRESERVE8
-
-	/* The MSP stack is not reset as, unlike on M3/4 parts, there is no vector
-	table offset register that can be used to locate the initial stack value.
-	Not all M0 parts have the application vector table at address 0. */
-
-	ldr	r3, =pxCurrentTCB	/* Obtain location of pxCurrentTCB. */
-	ldr r1, [r3]
-	ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
-	adds r0, #32			/* Discard everything up to r0. */
-	msr psp, r0				/* This is now the new top of stack to use in the task. */
-	movs r0, #2				/* Switch to the psp stack. */
-	msr CONTROL, r0
-	isb
-	pop {r0-r5}				/* Pop the registers that are saved automatically. */
-	mov lr, r5				/* lr is now in r5. */
-	pop {r3}				/* The return address is now in r3. */
-	pop {r2}				/* Pop and discard the XPSR. */
-	cpsie i					/* The first task has its context and interrupts can be enabled. */
-	bx r3					/* Finally, jump to the user defined task code. */
-
-	ALIGN
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* Make PendSV, CallSV and SysTick the same priority as the kernel. */
-	*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
-	*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Start the first task. */
-	prvPortStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortYield( void )
-{
-	/* Set a PendSV to request a context switch. */
-	*( portNVIC_INT_CTRL ) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is completely
-	within the specified behaviour for the architecture. */
-	__dsb( portSY_FULL_READ_WRITE );
-	__isb( portSY_FULL_READ_WRITE );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-    portDISABLE_INTERRUPTS();
-    uxCriticalNesting++;
-	__dsb( portSY_FULL_READ_WRITE );
-	__isb( portSY_FULL_READ_WRITE );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-    uxCriticalNesting--;
-    if( uxCriticalNesting == 0 )
-    {
-        portENABLE_INTERRUPTS();
-    }
-}
-/*-----------------------------------------------------------*/
-
-__asm uint32_t ulSetInterruptMaskFromISR( void )
-{
-	mrs r0, PRIMASK
-	cpsid i
-	bx lr
-}
-/*-----------------------------------------------------------*/
-
-__asm void vClearInterruptMaskFromISR( uint32_t ulMask )
-{
-	msr PRIMASK, r0
-	bx lr
-}
-/*-----------------------------------------------------------*/
-
-__asm void xPortPendSVHandler( void )
-{
-	extern vTaskSwitchContext
-	extern pxCurrentTCB
-
-	PRESERVE8
-
-	mrs r0, psp
-
-	ldr	r3, =pxCurrentTCB 	/* Get the location of the current TCB. */
-	ldr	r2, [r3]
-
-	subs r0, #32			/* Make space for the remaining low registers. */
-	str r0, [r2]			/* Save the new top of stack. */
-	stmia r0!, {r4-r7}		/* Store the low registers that are not saved automatically. */
-	mov r4, r8				/* Store the high registers. */
-	mov r5, r9
-	mov r6, r10
-	mov r7, r11
-	stmia r0!, {r4-r7}
-
-	push {r3, r14}
-	cpsid i
-	bl vTaskSwitchContext
-	cpsie i
-	pop {r2, r3}			/* lr goes in r3. r2 now holds tcb pointer. */
-
-	ldr r1, [r2]
-	ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
-	adds r0, #16			/* Move to the high registers. */
-	ldmia r0!, {r4-r7}		/* Pop the high registers. */
-	mov r8, r4
-	mov r9, r5
-	mov r10, r6
-	mov r11, r7
-
-	msr psp, r0				/* Remember the new top of stack for the task. */
-
-	subs r0, #32			/* Go back for the low registers that are not automatically restored. */
-	ldmia r0!, {r4-r7}      /* Pop low registers.  */
-
-	bx r3
-	ALIGN
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-uint32_t ulPreviousMask;
-
-	ulPreviousMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulPreviousMask );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-void prvSetupTimerInterrupt( void )
-{
-	/* Stop and reset the SysTick. */
-	*(portNVIC_SYSTICK_CTRL) = 0UL;
-	*(portNVIC_SYSTICK_CURRENT_VALUE) = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM0/portmacro.h b/FreeRTOS/Source/portable/RVDS/ARM_CM0/portmacro.h
deleted file mode 100755
index 9843778..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM0/portmacro.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
-extern void vPortYield( void );
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portYIELD()					vPortYield()
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulSetInterruptMaskFromISR( void );
-extern void vClearInterruptMaskFromISR( uint32_t ulMask );
-
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulSetInterruptMaskFromISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vClearInterruptMaskFromISR( x )
-#define portDISABLE_INTERRUPTS()				__disable_irq()
-#define portENABLE_INTERRUPTS()					__enable_irq()
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#define portNOP()
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c b/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
deleted file mode 100755
index bb7f9cc..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM3/port.c
+++ /dev/null
@@ -1,698 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM3 port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef configKERNEL_INTERRUPT_PRIORITY
-	#define configKERNEL_INTERRUPT_PRIORITY 255
-#endif
-
-#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
-	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
-#endif
-
-/* The __weak attribute does not work as you might expect with the Keil tools
-so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
-the application writer wants to provide their own implementation of
-vPortSetupTimerInterrupt().  Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
-is defined. */
-#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
-	#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
-
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR			( 0x01000000 )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR			( 45UL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void );
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvStartFirstTask( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
-
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-__asm void vPortSVCHandler( void )
-{
-	PRESERVE8
-
-	ldr	r3, =pxCurrentTCB	/* Restore the context. */
-	ldr r1, [r3]			/* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
-	ldr r0, [r1]			/* The first item in pxCurrentTCB is the task top of stack. */
-	ldmia r0!, {r4-r11}		/* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
-	msr psp, r0				/* Restore the task stack pointer. */
-	isb
-	mov r0, #0
-	msr	basepri, r0
-	orr r14, #0xd
-	bx r14
-}
-/*-----------------------------------------------------------*/
-
-__asm void prvStartFirstTask( void )
-{
-	PRESERVE8
-
-	/* Use the NVIC offset register to locate the stack. */
-	ldr r0, =0xE000ED08
-	ldr r0, [r0]
-	ldr r0, [r0]
-
-	/* Set the msp back to the start of the stack. */
-	msr msp, r0
-	/* Globally enable interrupts. */
-	cpsie i
-	cpsie f
-	dsb
-	isb
-	/* Call SVC to start the first task. */
-	svc 0
-	nop
-	nop
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* The kernel interrupt priority should be set to the lowest
-		priority. */
-		configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Start the first task. */
-	prvStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-__asm void xPortPendSVHandler( void )
-{
-	extern uxCriticalNesting;
-	extern pxCurrentTCB;
-	extern vTaskSwitchContext;
-
-	PRESERVE8
-
-	mrs r0, psp
-	isb
-
-	ldr	r3, =pxCurrentTCB		/* Get the location of the current TCB. */
-	ldr	r2, [r3]
-
-	stmdb r0!, {r4-r11}			/* Save the remaining registers. */
-	str r0, [r2]				/* Save the new top of stack into the first member of the TCB. */
-
-	stmdb sp!, {r3, r14}
-	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-	msr basepri, r0
-	dsb
-	isb
-	bl vTaskSwitchContext
-	mov r0, #0
-	msr basepri, r0
-	ldmia sp!, {r3, r14}
-
-	ldr r1, [r3]
-	ldr r0, [r1]				/* The first item in pxCurrentTCB is the task top of stack. */
-	ldmia r0!, {r4-r11}			/* Pop the registers and the critical nesting count. */
-	msr psp, r0
-	isb
-	bx r14
-	nop
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known - therefore the slightly faster vPortRaiseBASEPRI() function is used
-	in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
-	vPortRaiseBASEPRI();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	vPortClearBASEPRIFromISR();
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TICKLESS_IDLE == 1 )
-
-	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-	TickType_t xModifiableIdleTime;
-
-		/* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
-		is accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-		/* Calculate the reload value required to wait xExpectedIdleTime
-		tick periods.  -1 is used because this code will execute part way
-		through one of the tick periods. */
-		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-		if( ulReloadValue > ulStoppedTimerCompensation )
-		{
-			ulReloadValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Enter a critical section but don't use the taskENTER_CRITICAL()
-		method as that will mask interrupts that should exit sleep mode. */
-		__disable_irq();
-		__dsb( portSY_FULL_READ_WRITE );
-		__isb( portSY_FULL_READ_WRITE );
-
-		/* If a context switch is pending or a task is waiting for the scheduler
-		to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-		{
-			/* Restart from whatever is left in the count register to complete
-			this tick period. */
-			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Reset the reload register to the value required for normal tick
-			periods. */
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Re-enable interrupts - see comments above __disable_irq() call
-			above. */
-			__enable_irq();
-		}
-		else
-		{
-			/* Set the new reload value. */
-			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-			/* Clear the SysTick count flag and set the count value back to
-			zero. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-			set its parameter to 0 to indicate that its implementation contains
-			its own wait for interrupt or wait for event instruction, and so wfi
-			should not be executed again.  However, the original expected idle
-			time variable must remain unmodified, so a copy is taken. */
-			xModifiableIdleTime = xExpectedIdleTime;
-			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-			if( xModifiableIdleTime > 0 )
-			{
-				__dsb( portSY_FULL_READ_WRITE );
-				__wfi();
-				__isb( portSY_FULL_READ_WRITE );
-			}
-			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-			/* Re-enable interrupts to allow the interrupt that brought the MCU
-			out of sleep mode to execute immediately.  see comments above
-			__disable_interrupt() call above. */
-			__enable_irq();
-			__dsb( portSY_FULL_READ_WRITE );
-			__isb( portSY_FULL_READ_WRITE );
-
-			/* Disable interrupts again because the clock is about to be stopped
-			and interrupts that execute while the clock is stopped will increase
-			any slippage between the time maintained by the RTOS and calendar
-			time. */
-			__disable_irq();
-			__dsb( portSY_FULL_READ_WRITE );
-			__isb( portSY_FULL_READ_WRITE );
-			
-			/* Disable the SysTick clock without reading the 
-			portNVIC_SYSTICK_CTRL_REG register to ensure the
-			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again, 
-			the time the SysTick is stopped for is accounted for as best it can 
-			be, but using the tickless mode will inevitably result in some tiny 
-			drift of the time maintained by the kernel with respect to calendar 
-			time*/
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-			/* Determine if the SysTick clock has already counted to zero and
-			been set back to the current reload value (the reload back being
-			correct for the entire expected idle time) or if the SysTick is yet
-			to count to zero (in which case an interrupt other than the SysTick
-			must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-			{
-				uint32_t ulCalculatedLoadValue;
-
-				/* The tick interrupt is already pending, and the SysTick count
-				reloaded with ulReloadValue.  Reset the
-				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-				period. */
-				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-				/* Don't allow a tiny value, or values that have somehow
-				underflowed because the post sleep hook did something
-				that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-				{
-					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-				}
-
-				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-				/* As the pending tick will be processed as soon as this
-				function exits, the tick value maintained by the tick is stepped
-				forward by one less than the time spent waiting. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				Work out how long the sleep lasted rounded to complete tick
-				periods (not the ulReload value which accounted for part
-				ticks). */
-				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-				/* How many complete tick periods passed while the processor
-				was waiting? */
-				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-				/* The reload value is set to whatever fraction of a single tick
-				period remains. */
-				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-			}
-
-			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-			vTaskStepTick( ulCompleteTickPeriods );
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Exit with interrpts enabled. */
-			__enable_irq();
-		}
-	}
-
-#endif /* #if configUSE_TICKLESS_IDLE */
-
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the SysTick timer to generate the tick interrupts at the required
- * frequency.
- */
-#if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
-
-	void vPortSetupTimerInterrupt( void )
-	{
-		/* Calculate the constants required to configure the tick interrupt. */
-		#if( configUSE_TICKLESS_IDLE == 1 )
-		{
-			ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-			xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-			ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-		}
-		#endif /* configUSE_TICKLESS_IDLE */
-
-		/* Stop and clear the SysTick. */
-		portNVIC_SYSTICK_CTRL_REG = 0UL;
-		portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-		/* Configure SysTick to interrupt at the requested rate. */
-		portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-		portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-	}
-
-#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
-/*-----------------------------------------------------------*/
-
-__asm uint32_t vPortGetIPSR( void )
-{
-	PRESERVE8
-
-	mrs r0, ipsr
-	bx r14
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		/* Obtain the number of the currently executing interrupt. */
-		ulCurrentInterrupt = vPortGetIPSR();
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h b/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
deleted file mode 100755
index 65cd27e..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM3/portmacro.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-
-/* Constants used with memory barrier intrinsics. */
-#define portSY_FULL_READ_WRITE		( 15 )
-
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD()																\
-{																				\
-	/* Set a PendSV to request a context switch. */								\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
-																				\
-	/* Barriers are normally not required but do ensure the code is completely	\
-	within the specified behaviour for the architecture. */						\
-	__dsb( portSY_FULL_READ_WRITE );											\
-	__isb( portSY_FULL_READ_WRITE );											\
-}
-/*-----------------------------------------------------------*/
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
-#define portENABLE_INTERRUPTS()					vPortSetBASEPRI( 0 )
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
-
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-/*-----------------------------------------------------------*/
-
-/* Port specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
-
-#endif /* taskRECORD_READY_PRIORITY */
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-#define portINLINE __inline
-
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE __forceinline
-#endif
-
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
-{
-	__asm
-	{
-		/* Barrier instructions are not used as this function is only used to
-		lower the BASEPRI value. */
-		msr basepri, ulBASEPRI
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortRaiseBASEPRI( void )
-{
-uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
-	__asm
-	{
-		/* Set BASEPRI to the max syscall priority to effect a critical
-		section. */
-		msr basepri, ulNewBASEPRI
-		dsb
-		isb
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
-{
-	__asm
-	{
-		/* Set BASEPRI to 0 so no interrupts are masked.  This function is only
-		used to lower the mask in an interrupt, so memory barriers are not 
-		used. */
-		msr basepri, #0
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
-{
-uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
-	__asm
-	{
-		/* Set BASEPRI to the max syscall priority to effect a critical
-		section. */
-		mrs ulReturn, basepri
-		msr basepri, ulNewBASEPRI
-		dsb
-		isb
-	}
-
-	return ulReturn;
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
-{
-uint32_t ulCurrentInterrupt;
-BaseType_t xReturn;
-
-	/* Obtain the number of the currently executing interrupt. */
-	__asm
-	{
-		mrs ulCurrentInterrupt, ipsr
-	}
-
-	if( ulCurrentInterrupt == 0 )
-	{
-		xReturn = pdFALSE;
-	}
-	else
-	{
-		xReturn = pdTRUE;
-	}
-
-	return xReturn;
-}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c b/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
deleted file mode 100755
index 484e427..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/port.c
+++ /dev/null
@@ -1,788 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __TARGET_FPU_VFP
-	#error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
-	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
-#endif
-
-/* The __weak attribute does not work as you might expect with the Keil tools
-so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
-the application writer wants to provide their own implementation of
-vPortSetupTimerInterrupt().  Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
-is defined. */
-#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
-	#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
-
-/* Constants used to detect a Cortex-M7 r0p1 core, which should use the ARM_CM7
-r0p1 port. */
-#define portCPUID							( * ( ( volatile uint32_t * ) 0xE000ed00 ) )
-#define portCORTEX_M7_r0p1_ID				( 0x410FC271UL )
-#define portCORTEX_M7_r0p0_ID				( 0x410FC270UL )
-
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR					( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS	( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR			( 0x01000000 )
-#define portINITIAL_EXC_RETURN		( 0xfffffffd )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER		( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR	( 45UL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void );
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvStartFirstTask( void );
-
-/*
- * Functions defined in portasm.s to enable the VFP.
- */
-static void prvEnableVFP( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-
-	/* Offset added to account for the way the MCU uses the stack on entry/exit
-	of interrupts, and to ensure alignment. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
-
-	/* Save code space by skipping register initialisation. */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-
-	/* A save method is being used that requires each task to maintain its
-	own exec return value. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-__asm void vPortSVCHandler( void )
-{
-	PRESERVE8
-
-	/* Get the location of the current TCB. */
-	ldr	r3, =pxCurrentTCB
-	ldr r1, [r3]
-	ldr r0, [r1]
-	/* Pop the core registers. */
-	ldmia r0!, {r4-r11, r14}
-	msr psp, r0
-	isb
-	mov r0, #0
-	msr	basepri, r0
-	bx r14
-}
-/*-----------------------------------------------------------*/
-
-__asm void prvStartFirstTask( void )
-{
-	PRESERVE8
-
-	/* Use the NVIC offset register to locate the stack. */
-	ldr r0, =0xE000ED08
-	ldr r0, [r0]
-	ldr r0, [r0]
-	/* Set the msp back to the start of the stack. */
-	msr msp, r0
-	/* Clear the bit that indicates the FPU is in use in case the FPU was used
-	before the scheduler was started - which would otherwise result in the
-	unnecessary leaving of space in the SVC stack for lazy saving of FPU
-	registers. */
-	mov r0, #0
-	msr control, r0
-	/* Globally enable interrupts. */
-	cpsie i
-	cpsie f
-	dsb
-	isb
-	/* Call SVC to start the first task. */
-	svc 0
-	nop
-	nop
-}
-/*-----------------------------------------------------------*/
-
-__asm void prvEnableVFP( void )
-{
-	PRESERVE8
-
-	/* The FPU enable bits are in the CPACR. */
-	ldr.w r0, =0xE000ED88
-	ldr	r1, [r0]
-
-	/* Enable CP10 and CP11 coprocessors, then save back. */
-	orr	r1, r1, #( 0xf << 20 )
-	str r1, [r0]
-	bx	r14
-	nop
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-
-	/* This port can be used on all revisions of the Cortex-M7 core other than
-	the r0p1 parts.  r0p1 parts should use the port from the
-	/source/portable/GCC/ARM_CM7/r0p1 directory. */
-	configASSERT( portCPUID != portCORTEX_M7_r0p1_ID );
-	configASSERT( portCPUID != portCORTEX_M7_r0p0_ID );
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* The kernel interrupt priority should be set to the lowest
-		priority. */
-		configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Ensure the VFP is enabled - it should be anyway. */
-	prvEnableVFP();
-
-	/* Lazy save always. */
-	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
-	/* Start the first task. */
-	prvStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-__asm void xPortPendSVHandler( void )
-{
-	extern uxCriticalNesting;
-	extern pxCurrentTCB;
-	extern vTaskSwitchContext;
-
-	PRESERVE8
-
-	mrs r0, psp
-	isb
-	/* Get the location of the current TCB. */
-	ldr	r3, =pxCurrentTCB
-	ldr	r2, [r3]
-
-	/* Is the task using the FPU context?  If so, push high vfp registers. */
-	tst r14, #0x10
-	it eq
-	vstmdbeq r0!, {s16-s31}
-
-	/* Save the core registers. */
-	stmdb r0!, {r4-r11, r14}
-
-	/* Save the new top of stack into the first member of the TCB. */
-	str r0, [r2]
-
-	stmdb sp!, {r0, r3}
-	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-	msr basepri, r0
-	dsb
-	isb
-	bl vTaskSwitchContext
-	mov r0, #0
-	msr basepri, r0
-	ldmia sp!, {r0, r3}
-
-	/* The first item in pxCurrentTCB is the task top of stack. */
-	ldr r1, [r3]
-	ldr r0, [r1]
-
-	/* Pop the core registers. */
-	ldmia r0!, {r4-r11, r14}
-
-	/* Is the task using the FPU context?  If so, pop the high vfp registers
-	too. */
-	tst r14, #0x10
-	it eq
-	vldmiaeq r0!, {s16-s31}
-
-	msr psp, r0
-	isb
-	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
-		#if WORKAROUND_PMU_CM001 == 1
-			push { r14 }
-			pop { pc }
-			nop
-		#endif
-	#endif
-
-	bx r14
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known - therefore the slightly faster vPortRaiseBASEPRI() function is used
-	in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
-	vPortRaiseBASEPRI();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	vPortClearBASEPRIFromISR();
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TICKLESS_IDLE == 1 )
-
-	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-	TickType_t xModifiableIdleTime;
-
-		/* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
-		is accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-		/* Calculate the reload value required to wait xExpectedIdleTime
-		tick periods.  -1 is used because this code will execute part way
-		through one of the tick periods. */
-		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-		if( ulReloadValue > ulStoppedTimerCompensation )
-		{
-			ulReloadValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Enter a critical section but don't use the taskENTER_CRITICAL()
-		method as that will mask interrupts that should exit sleep mode. */
-		__disable_irq();
-		__dsb( portSY_FULL_READ_WRITE );
-		__isb( portSY_FULL_READ_WRITE );
-
-		/* If a context switch is pending or a task is waiting for the scheduler
-		to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-		{
-			/* Restart from whatever is left in the count register to complete
-			this tick period. */
-			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Reset the reload register to the value required for normal tick
-			periods. */
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Re-enable interrupts - see comments above __disable_irq() call
-			above. */
-			__enable_irq();
-		}
-		else
-		{
-			/* Set the new reload value. */
-			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-			/* Clear the SysTick count flag and set the count value back to
-			zero. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-			set its parameter to 0 to indicate that its implementation contains
-			its own wait for interrupt or wait for event instruction, and so wfi
-			should not be executed again.  However, the original expected idle
-			time variable must remain unmodified, so a copy is taken. */
-			xModifiableIdleTime = xExpectedIdleTime;
-			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-			if( xModifiableIdleTime > 0 )
-			{
-				__dsb( portSY_FULL_READ_WRITE );
-				__wfi();
-				__isb( portSY_FULL_READ_WRITE );
-			}
-			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-			/* Re-enable interrupts to allow the interrupt that brought the MCU
-			out of sleep mode to execute immediately.  see comments above
-			__disable_interrupt() call above. */
-			__enable_irq();
-			__dsb( portSY_FULL_READ_WRITE );
-			__isb( portSY_FULL_READ_WRITE );
-
-			/* Disable interrupts again because the clock is about to be stopped
-			and interrupts that execute while the clock is stopped will increase
-			any slippage between the time maintained by the RTOS and calendar
-			time. */
-			__disable_irq();
-			__dsb( portSY_FULL_READ_WRITE );
-			__isb( portSY_FULL_READ_WRITE );
-
-			/* Disable the SysTick clock without reading the
-			portNVIC_SYSTICK_CTRL_REG register to ensure the
-			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
-			the time the SysTick is stopped for is accounted for as best it can
-			be, but using the tickless mode will inevitably result in some tiny
-			drift of the time maintained by the kernel with respect to calendar
-			time*/
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-			/* Determine if the SysTick clock has already counted to zero and
-			been set back to the current reload value (the reload back being
-			correct for the entire expected idle time) or if the SysTick is yet
-			to count to zero (in which case an interrupt other than the SysTick
-			must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-			{
-				uint32_t ulCalculatedLoadValue;
-
-				/* The tick interrupt is already pending, and the SysTick count
-				reloaded with ulReloadValue.  Reset the
-				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-				period. */
-				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-				/* Don't allow a tiny value, or values that have somehow
-				underflowed because the post sleep hook did something
-				that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-				{
-					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-				}
-
-				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-				/* As the pending tick will be processed as soon as this
-				function exits, the tick value maintained by the tick is stepped
-				forward by one less than the time spent waiting. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				Work out how long the sleep lasted rounded to complete tick
-				periods (not the ulReload value which accounted for part
-				ticks). */
-				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-				/* How many complete tick periods passed while the processor
-				was waiting? */
-				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-				/* The reload value is set to whatever fraction of a single tick
-				period remains. */
-				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-			}
-
-			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-			vTaskStepTick( ulCompleteTickPeriods );
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Exit with interrpts enabled. */
-			__enable_irq();
-		}
-	}
-
-#endif /* #if configUSE_TICKLESS_IDLE */
-
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the SysTick timer to generate the tick interrupts at the required
- * frequency.
- */
-#if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
-
-	void vPortSetupTimerInterrupt( void )
-	{
-		/* Calculate the constants required to configure the tick interrupt. */
-		#if( configUSE_TICKLESS_IDLE == 1 )
-		{
-			ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-			xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-			ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-		}
-		#endif /* configUSE_TICKLESS_IDLE */
-
-		/* Stop and clear the SysTick. */
-		portNVIC_SYSTICK_CTRL_REG = 0UL;
-		portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-		/* Configure SysTick to interrupt at the requested rate. */
-		portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-		portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-	}
-
-#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
-/*-----------------------------------------------------------*/
-
-__asm uint32_t vPortGetIPSR( void )
-{
-	PRESERVE8
-
-	mrs r0, ipsr
-	bx r14
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		/* Obtain the number of the currently executing interrupt. */
-		ulCurrentInterrupt = vPortGetIPSR();
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
deleted file mode 100755
index 65cd27e..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM4F/portmacro.h
+++ /dev/null
@@ -1,252 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-
-/* Constants used with memory barrier intrinsics. */
-#define portSY_FULL_READ_WRITE		( 15 )
-
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD()																\
-{																				\
-	/* Set a PendSV to request a context switch. */								\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
-																				\
-	/* Barriers are normally not required but do ensure the code is completely	\
-	within the specified behaviour for the architecture. */						\
-	__dsb( portSY_FULL_READ_WRITE );											\
-	__isb( portSY_FULL_READ_WRITE );											\
-}
-/*-----------------------------------------------------------*/
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
-#define portENABLE_INTERRUPTS()					vPortSetBASEPRI( 0 )
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
-
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-/*-----------------------------------------------------------*/
-
-/* Port specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
-
-#endif /* taskRECORD_READY_PRIORITY */
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-#define portINLINE __inline
-
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE __forceinline
-#endif
-
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
-{
-	__asm
-	{
-		/* Barrier instructions are not used as this function is only used to
-		lower the BASEPRI value. */
-		msr basepri, ulBASEPRI
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortRaiseBASEPRI( void )
-{
-uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
-	__asm
-	{
-		/* Set BASEPRI to the max syscall priority to effect a critical
-		section. */
-		msr basepri, ulNewBASEPRI
-		dsb
-		isb
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
-{
-	__asm
-	{
-		/* Set BASEPRI to 0 so no interrupts are masked.  This function is only
-		used to lower the mask in an interrupt, so memory barriers are not 
-		used. */
-		msr basepri, #0
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
-{
-uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
-	__asm
-	{
-		/* Set BASEPRI to the max syscall priority to effect a critical
-		section. */
-		mrs ulReturn, basepri
-		msr basepri, ulNewBASEPRI
-		dsb
-		isb
-	}
-
-	return ulReturn;
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
-{
-uint32_t ulCurrentInterrupt;
-BaseType_t xReturn;
-
-	/* Obtain the number of the currently executing interrupt. */
-	__asm
-	{
-		mrs ulCurrentInterrupt, ipsr
-	}
-
-	if( ulCurrentInterrupt == 0 )
-	{
-		xReturn = pdFALSE;
-	}
-	else
-	{
-		xReturn = pdTRUE;
-	}
-
-	return xReturn;
-}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c b/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c
deleted file mode 100755
index 79557fe..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/port.c
+++ /dev/null
@@ -1,867 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM3 port.
- *----------------------------------------------------------*/
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __TARGET_FPU_VFP
-	#error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* Constants required to access and manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL_REG				( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG				( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG		( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG					( *	( ( volatile uint32_t * ) 0xe000ed20 ) )
-#define portNVIC_SYSPRI1_REG					( * ( ( volatile uint32_t * ) 0xe000ed1c ) )
-#define portNVIC_SYS_CTRL_STATE_REG				( * ( ( volatile uint32_t * ) 0xe000ed24 ) )
-#define portNVIC_MEM_FAULT_ENABLE				( 1UL << 16UL )
-
-/* Constants required to access and manipulate the MPU. */
-#define portMPU_TYPE_REG						( * ( ( volatile uint32_t * ) 0xe000ed90 ) )
-#define portMPU_REGION_BASE_ADDRESS_REG			( * ( ( volatile uint32_t * ) 0xe000ed9C ) )
-#define portMPU_REGION_ATTRIBUTE_REG			( * ( ( volatile uint32_t * ) 0xe000edA0 ) )
-#define portMPU_CTRL_REG						( * ( ( volatile uint32_t * ) 0xe000ed94 ) )
-#define portEXPECTED_MPU_TYPE_VALUE				( 8UL << 8UL ) /* 8 regions, unified. */
-#define portMPU_ENABLE							( 0x01UL )
-#define portMPU_BACKGROUND_ENABLE				( 1UL << 2UL )
-#define portPRIVILEGED_EXECUTION_START_ADDRESS	( 0UL )
-#define portMPU_REGION_VALID					( 0x10UL )
-#define portMPU_REGION_ENABLE					( 0x01UL )
-#define portPERIPHERALS_START_ADDRESS			0x40000000UL
-#define portPERIPHERALS_END_ADDRESS				0x5FFFFFFFUL
-
-/* Constants required to access and manipulate the SysTick. */
-#define portNVIC_SYSTICK_CLK					( 0x00000004UL )
-#define portNVIC_SYSTICK_INT					( 0x00000002UL )
-#define portNVIC_SYSTICK_ENABLE					( 0x00000001UL )
-#define portNVIC_PENDSV_PRI						( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-#define portNVIC_SVC_PRI						( ( ( uint32_t ) configMAX_SYSCALL_INTERRUPT_PRIORITY - 1UL ) << 24UL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR								( ( volatile uint32_t * ) 0xe000ef34UL ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS				( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR						( 0x01000000UL )
-#define portINITIAL_EXC_RETURN					( 0xfffffffdUL )
-#define portINITIAL_CONTROL_IF_UNPRIVILEGED		( 0x03 )
-#define portINITIAL_CONTROL_IF_PRIVILEGED		( 0x02 )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Offsets in the stack to the parameters when inside the SVC handler. */
-#define portOFFSET_TO_PC						( 6 )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable.  Note this is not saved as part of the task context as context
-switches can only occur when uxCriticalNesting is zero. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Configure a number of standard MPU regions that are used by all tasks.
- */
-static void prvSetupMPU( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvStartFirstTask( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Return the smallest MPU region size that a given number of bytes will fit
- * into.  The region size is returned as the value that should be programmed
- * into the region attribute register for that region.
- */
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes ) PRIVILEGED_FUNCTION;
-
-/*
- * Standard FreeRTOS exception handlers.
- */
-void xPortPendSVHandler( void ) PRIVILEGED_FUNCTION;
-void xPortSysTickHandler( void ) PRIVILEGED_FUNCTION;
-void vPortSVCHandler( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Starts the scheduler by restoring the context of the first task to run.
- */
-static void prvRestoreContextOfFirstTask( void ) PRIVILEGED_FUNCTION;
-
-/*
- * C portion of the SVC handler.  The SVC handler is split between an asm entry
- * and a C wrapper for simplicity of coding and maintenance.
- */
-void prvSVCHandler( uint32_t *pulRegisters ) __attribute__((used)) PRIVILEGED_FUNCTION;
-
-/*
- * Function to enable the VFP.
- */
-static void vPortEnableVFP( void );
-
-/*
- * Utility function.
- */
-static uint32_t prvPortGetIPSR( void );
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-BaseType_t xIsPrivileged( void );
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- *
- * Bit 0 of the CONTROL register defines the privilege level of Thread Mode.
- *  Bit[0] = 0 --> The processor is running privileged
- *  Bit[0] = 1 --> The processor is running unprivileged.
- */
-void vResetPrivilege( void );
-
-/**
- * @brief Calls the port specific code to raise the privilege.
- *
- * @return pdFALSE if privilege was raised, pdTRUE otherwise.
- */
-extern BaseType_t xPortRaisePrivilege( void );
-
-/**
- * @brief If xRunningPrivileged is not pdTRUE, calls the port specific
- * code to reset the privilege, otherwise does nothing.
- */
-extern void vPortResetPrivilege( BaseType_t xRunningPrivileged );
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = 0;	/* LR */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-
-	/* A save method is being used that requires each task to maintain its
-	own exec return value. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-	pxTopOfStack -= 9;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	if( xRunPrivileged == pdTRUE )
-	{
-		*pxTopOfStack = portINITIAL_CONTROL_IF_PRIVILEGED;
-	}
-	else
-	{
-		*pxTopOfStack = portINITIAL_CONTROL_IF_UNPRIVILEGED;
-	}
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void prvSVCHandler( uint32_t *pulParam )
-{
-uint8_t ucSVCNumber;
-uint32_t ulReg;
-
-	/* The stack contains: r0, r1, r2, r3, r12, r14, the return address and
-	xPSR.  The first argument (r0) is pulParam[ 0 ]. */
-	ucSVCNumber = ( ( uint8_t * ) pulParam[ portOFFSET_TO_PC ] )[ -2 ];
-	switch( ucSVCNumber )
-	{
-		case portSVC_START_SCHEDULER	:	portNVIC_SYSPRI1_REG |= portNVIC_SVC_PRI;
-											prvRestoreContextOfFirstTask();
-											break;
-
-		case portSVC_YIELD				:	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-											/* Barriers are normally not required
-											but do ensure the code is completely
-											within the specified behaviour for the
-											architecture. */
-											__asm volatile( "dsb" );
-											__asm volatile( "isb" );
-
-											break;
-
-		case portSVC_RAISE_PRIVILEGE	:	__asm
-											{
-												mrs ulReg, control	/* Obtain current control value. */
-												bic ulReg, #1		/* Set privilege bit. */
-												msr control, ulReg	/* Write back new control value. */
-											}
-											break;
-
-		default							:	/* Unknown SVC call. */
-											break;
-	}
-}
-/*-----------------------------------------------------------*/
-
-__asm void vPortSVCHandler( void )
-{
-	extern prvSVCHandler
-
-	PRESERVE8
-
-	/* Assumes psp was in use. */
-	#ifndef USE_PROCESS_STACK	/* Code should not be required if a main() is using the process stack. */
-		tst lr, #4
-		ite eq
-		mrseq r0, msp
-		mrsne r0, psp
-	#else
-		mrs r0, psp
-	#endif
-		b prvSVCHandler
-}
-/*-----------------------------------------------------------*/
-
-__asm void prvRestoreContextOfFirstTask( void )
-{
-	PRESERVE8
-
-	ldr r0, =0xE000ED08				/* Use the NVIC offset register to locate the stack. */
-	ldr r0, [r0]
-	ldr r0, [r0]
-	msr msp, r0						/* Set the msp back to the start of the stack. */
-	ldr	r3, =pxCurrentTCB			/* Restore the context. */
-	ldr r1, [r3]
-	ldr r0, [r1]					/* The first item in the TCB is the task top of stack. */
-	add r1, r1, #4					/* Move onto the second item in the TCB... */
-	ldr r2, =0xe000ed9c				/* Region Base Address register. */
-	ldmia r1!, {r4-r11}				/* Read 4 sets of MPU registers. */
-	stmia r2!, {r4-r11}				/* Write 4 sets of MPU registers. */
-	ldmia r0!, {r3-r11, r14}	/* Pop the registers that are not automatically saved on exception entry. */
-	msr control, r3
-	msr psp, r0						/* Restore the task stack pointer. */
-	mov r0, #0
-	msr	basepri, r0
-	bx r14
-	nop
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See
-	http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-	configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
-
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the same priority as the kernel, and the SVC
-	handler higher priority so it can be used to exit a critical section (where
-	lower priorities are masked). */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Configure the regions in the MPU that are common to all tasks. */
-	prvSetupMPU();
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Ensure the VFP is enabled - it should be anyway. */
-	vPortEnableVFP();
-
-	/* Lazy save always. */
-	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
-	/* Start the first task. */
-	prvStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-__asm void prvStartFirstTask( void )
-{
-	PRESERVE8
-
-	/* Use the NVIC offset register to locate the stack. */
-	ldr r0, =0xE000ED08
-	ldr r0, [r0]
-	ldr r0, [r0]
-	/* Set the msp back to the start of the stack. */
-	msr msp, r0
-	/* Clear the bit that indicates the FPU is in use in case the FPU was used
-	before the scheduler was started - which would otherwise result in the
-	unnecessary leaving of space in the SVC stack for lazy saving of FPU
-	registers. */
-	mov r0, #0
-	msr control, r0
-	/* Globally enable interrupts. */
-	cpsie i
-	cpsie f
-	dsb
-	isb
-	svc portSVC_START_SCHEDULER	/* System call to start first task. */
-	nop
-	nop
-}
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-BaseType_t xRunningPrivileged = xPortRaisePrivilege();
-
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-	vPortResetPrivilege( xRunningPrivileged );
-}
-/*-----------------------------------------------------------*/
-
-__asm void xPortPendSVHandler( void )
-{
-	extern uxCriticalNesting;
-	extern pxCurrentTCB;
-	extern vTaskSwitchContext;
-
-	PRESERVE8
-
-	mrs r0, psp
-
-	ldr r3, =pxCurrentTCB			/* Get the location of the current TCB. */
-	ldr r2, [r3]
-
-	tst r14, #0x10					/* Is the task using the FPU context?  If so, push high vfp registers. */
-	it eq
-	vstmdbeq r0!, {s16-s31}
-
-	mrs r1, control
-	stmdb r0!, {r1, r4-r11, r14}	/* Save the remaining registers. */
-	str r0, [r2]					/* Save the new top of stack into the first member of the TCB. */
-
-	stmdb sp!, {r0, r3}
-	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-	msr basepri, r0
-	dsb
-	isb
-	bl vTaskSwitchContext
-	mov r0, #0
-	msr basepri, r0
-	ldmia sp!, {r0, r3}
-									/* Restore the context. */
-	ldr r1, [r3]
-	ldr r0, [r1]					/* The first item in the TCB is the task top of stack. */
-	add r1, r1, #4					/* Move onto the second item in the TCB... */
-	ldr r2, =0xe000ed9c				/* Region Base Address register. */
-	ldmia r1!, {r4-r11}				/* Read 4 sets of MPU registers. */
-	stmia r2!, {r4-r11}				/* Write 4 sets of MPU registers. */
-	ldmia r0!, {r3-r11, r14}		/* Pop the registers that are not automatically saved on exception entry. */
-	msr control, r3
-
-	tst r14, #0x10					/* Is the task using the FPU context?  If so, pop the high vfp registers too. */
-	it eq
-	vldmiaeq r0!, {s16-s31}
-
-	msr psp, r0
-	bx r14
-	nop
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-uint32_t ulDummy;
-
-	ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-static void prvSetupTimerInterrupt( void )
-{
-	/* Reset the SysTick. */
-	portNVIC_SYSTICK_CTRL_REG = 0UL;
-	portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-	/* Configure SysTick to interrupt at the requested rate. */
-	portNVIC_SYSTICK_LOAD_REG = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	portNVIC_SYSTICK_CTRL_REG = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
-__asm void vPortSwitchToUserMode( void )
-{
-	PRESERVE8
-
-	mrs r0, control
-	orr r0, #1
-	msr control, r0
-	bx r14
-}
-/*-----------------------------------------------------------*/
-
-__asm void vPortEnableVFP( void )
-{
-	PRESERVE8
-
-	ldr.w r0, =0xE000ED88		/* The FPU enable bits are in the CPACR. */
-	ldr r1, [r0]
-
-	orr r1, r1, #( 0xf << 20 )	/* Enable CP10 and CP11 coprocessors, then save back. */
-	str r1, [r0]
-	bx r14
-	nop
-	nop
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupMPU( void )
-{
-extern uint32_t __privileged_functions_end__;
-extern uint32_t __FLASH_segment_start__;
-extern uint32_t __FLASH_segment_end__;
-extern uint32_t __privileged_data_start__;
-extern uint32_t __privileged_data_end__;
-
-	/* Check the expected MPU is present. */
-	if( portMPU_TYPE_REG == portEXPECTED_MPU_TYPE_VALUE )
-	{
-		/* First setup the entire flash for unprivileged read only access. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
-											( portMPU_REGION_VALID ) |
-											( portUNPRIVILEGED_FLASH_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_ONLY ) |
-										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-										( prvGetMPURegionSizeSetting( ( uint32_t ) __FLASH_segment_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
-										( portMPU_REGION_ENABLE );
-
-		/* Setup the first 16K for privileged only access (even though less
-		than 10K is actually being used).  This is where the kernel code is
-		placed. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __FLASH_segment_start__ ) | /* Base address. */
-											( portMPU_REGION_VALID ) |
-											( portPRIVILEGED_FLASH_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_ONLY ) |
-										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-										( prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_functions_end__ - ( uint32_t ) __FLASH_segment_start__ ) ) |
-										( portMPU_REGION_ENABLE );
-
-		/* Setup the privileged data RAM region.  This is where the kernel data
-		is placed. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
-											( portMPU_REGION_VALID ) |
-											( portPRIVILEGED_RAM_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-										( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-										prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
-										( portMPU_REGION_ENABLE );
-
-		/* By default allow everything to access the general peripherals.  The
-		system peripherals and registers are protected. */
-		portMPU_REGION_BASE_ADDRESS_REG =	( portPERIPHERALS_START_ADDRESS ) |
-											( portMPU_REGION_VALID ) |
-											( portGENERAL_PERIPHERALS_REGION );
-
-		portMPU_REGION_ATTRIBUTE_REG =	( portMPU_REGION_READ_WRITE | portMPU_REGION_EXECUTE_NEVER ) |
-										( prvGetMPURegionSizeSetting( portPERIPHERALS_END_ADDRESS - portPERIPHERALS_START_ADDRESS ) ) |
-										( portMPU_REGION_ENABLE );
-
-		/* Enable the memory fault exception. */
-		portNVIC_SYS_CTRL_STATE_REG |= portNVIC_MEM_FAULT_ENABLE;
-
-		/* Enable the MPU with the background region configured. */
-		portMPU_CTRL_REG |= ( portMPU_ENABLE | portMPU_BACKGROUND_ENABLE );
-	}
-}
-/*-----------------------------------------------------------*/
-
-static uint32_t prvGetMPURegionSizeSetting( uint32_t ulActualSizeInBytes )
-{
-uint32_t ulRegionSize, ulReturnValue = 4;
-
-	/* 32 is the smallest region size, 31 is the largest valid value for
-	ulReturnValue. */
-	for( ulRegionSize = 32UL; ulReturnValue < 31UL; ( ulRegionSize <<= 1UL ) )
-	{
-		if( ulActualSizeInBytes <= ulRegionSize )
-		{
-			break;
-		}
-		else
-		{
-			ulReturnValue++;
-		}
-	}
-
-	/* Shift the code by one before returning so it can be written directly
-	into the the correct bit position of the attribute register. */
-	return ( ulReturnValue << 1UL );
-}
-/*-----------------------------------------------------------*/
-
-__asm BaseType_t xIsPrivileged( void )
-{
-	PRESERVE8
-
-	mrs r0, control		/* r0 = CONTROL. */
-	tst r0, #1			/* Perform r0 & 1 (bitwise AND) and update the conditions flag. */
-	ite ne
-	movne r0, #0		/* CONTROL[0]!=0. Return false to indicate that the processor is not privileged. */
-	moveq r0, #1		/* CONTROL[0]==0. Return true to indicate that the processor is privileged. */
-	bx lr				/* Return. */
-}
-/*-----------------------------------------------------------*/
-
-__asm void vResetPrivilege( void )
-{
-	PRESERVE8
-
-	mrs r0, control		/* r0 = CONTROL. */
-	orrs r0, #1			/* r0 = r0 | 1. */
-	msr control, r0		/* CONTROL = r0. */
-	bx lr				/* Return. */
-}
-/*-----------------------------------------------------------*/
-
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-{
-extern uint32_t __SRAM_segment_start__;
-extern uint32_t __SRAM_segment_end__;
-extern uint32_t __privileged_data_start__;
-extern uint32_t __privileged_data_end__;
-
-
-int32_t lIndex;
-uint32_t ul;
-
-	if( xRegions == NULL )
-	{
-		/* No MPU regions are specified so allow access to all RAM. */
-		xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
-				( ( uint32_t ) __SRAM_segment_start__ ) | /* Base address. */
-				( portMPU_REGION_VALID ) |
-				( portSTACK_REGION );
-
-		xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
-				( portMPU_REGION_READ_WRITE ) |
-				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-				( prvGetMPURegionSizeSetting( ( uint32_t ) __SRAM_segment_end__ - ( uint32_t ) __SRAM_segment_start__ ) ) |
-				( portMPU_REGION_ENABLE );
-
-		/* Re-instate the privileged only RAM region as xRegion[ 0 ] will have
-		just removed the privileged only parameters. */
-		xMPUSettings->xRegion[ 1 ].ulRegionBaseAddress =
-				( ( uint32_t ) __privileged_data_start__ ) | /* Base address. */
-				( portMPU_REGION_VALID ) |
-				( portSTACK_REGION + 1 );
-
-		xMPUSettings->xRegion[ 1 ].ulRegionAttribute =
-				( portMPU_REGION_PRIVILEGED_READ_WRITE ) |
-				( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-				prvGetMPURegionSizeSetting( ( uint32_t ) __privileged_data_end__ - ( uint32_t ) __privileged_data_start__ ) |
-				( portMPU_REGION_ENABLE );
-
-		/* Invalidate all other regions. */
-		for( ul = 2; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
-		{
-			xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
-			xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
-		}
-	}
-	else
-	{
-		/* This function is called automatically when the task is created - in
-		which case the stack region parameters will be valid.  At all other
-		times the stack parameters will not be valid and it is assumed that the
-		stack region has already been configured. */
-		if( ulStackDepth > 0 )
-		{
-			/* Define the region that allows access to the stack. */
-			xMPUSettings->xRegion[ 0 ].ulRegionBaseAddress =
-					( ( uint32_t ) pxBottomOfStack ) |
-					( portMPU_REGION_VALID ) |
-					( portSTACK_REGION ); /* Region number. */
-
-			xMPUSettings->xRegion[ 0 ].ulRegionAttribute =
-					( portMPU_REGION_READ_WRITE ) | /* Read and write. */
-					( prvGetMPURegionSizeSetting( ulStackDepth * ( uint32_t ) sizeof( StackType_t ) ) ) |
-					( portMPU_REGION_CACHEABLE_BUFFERABLE ) |
-					( portMPU_REGION_ENABLE );
-		}
-
-		lIndex = 0;
-
-		for( ul = 1; ul <= portNUM_CONFIGURABLE_REGIONS; ul++ )
-		{
-			if( ( xRegions[ lIndex ] ).ulLengthInBytes > 0UL )
-			{
-				/* Translate the generic region definition contained in
-				xRegions into the CM3 specific MPU settings that are then
-				stored in xMPUSettings. */
-				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress =
-						( ( uint32_t ) xRegions[ lIndex ].pvBaseAddress ) |
-						( portMPU_REGION_VALID ) |
-						( portSTACK_REGION + ul ); /* Region number. */
-
-				xMPUSettings->xRegion[ ul ].ulRegionAttribute =
-						( prvGetMPURegionSizeSetting( xRegions[ lIndex ].ulLengthInBytes ) ) |
-						( xRegions[ lIndex ].ulParameters ) |
-						( portMPU_REGION_ENABLE );
-			}
-			else
-			{
-				/* Invalidate the region. */
-				xMPUSettings->xRegion[ ul ].ulRegionBaseAddress = ( portSTACK_REGION + ul ) | portMPU_REGION_VALID;
-				xMPUSettings->xRegion[ ul ].ulRegionAttribute = 0UL;
-			}
-
-			lIndex++;
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-__asm uint32_t prvPortGetIPSR( void )
-{
-	PRESERVE8
-
-	mrs r0, ipsr
-	bx r14
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		/* Obtain the number of the currently executing interrupt. */
-		ulCurrentInterrupt = prvPortGetIPSR();
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredicable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h b/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
deleted file mode 100755
index 9a37600..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM4_MPU/portmacro.h
+++ /dev/null
@@ -1,309 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* MPU specific constants. */
-#define portUSING_MPU_WRAPPERS		1
-#define portPRIVILEGE_BIT			( 0x80000000UL )
-
-#define portMPU_REGION_READ_WRITE				( 0x03UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_ONLY		( 0x05UL << 24UL )
-#define portMPU_REGION_READ_ONLY				( 0x06UL << 24UL )
-#define portMPU_REGION_PRIVILEGED_READ_WRITE	( 0x01UL << 24UL )
-#define portMPU_REGION_CACHEABLE_BUFFERABLE		( 0x07UL << 16UL )
-#define portMPU_REGION_EXECUTE_NEVER			( 0x01UL << 28UL )
-
-#define portUNPRIVILEGED_FLASH_REGION		( 0UL )
-#define portPRIVILEGED_FLASH_REGION			( 1UL )
-#define portPRIVILEGED_RAM_REGION			( 2UL )
-#define portGENERAL_PERIPHERALS_REGION		( 3UL )
-#define portSTACK_REGION					( 4UL )
-#define portFIRST_CONFIGURABLE_REGION		( 5UL )
-#define portLAST_CONFIGURABLE_REGION		( 7UL )
-#define portNUM_CONFIGURABLE_REGIONS		( ( portLAST_CONFIGURABLE_REGION - portFIRST_CONFIGURABLE_REGION ) + 1 )
-#define portTOTAL_NUM_REGIONS				( portNUM_CONFIGURABLE_REGIONS + 1 ) /* Plus one to make space for the stack region. */
-
-void vPortSwitchToUserMode( void );
-#define portSWITCH_TO_USER_MODE()	vPortSwitchToUserMode()
-
-typedef struct MPU_REGION_REGISTERS
-{
-	uint32_t ulRegionBaseAddress;
-	uint32_t ulRegionAttribute;
-} xMPU_REGION_REGISTERS;
-
-/* Plus 1 to create space for the stack region. */
-typedef struct MPU_SETTINGS
-{
-	xMPU_REGION_REGISTERS xRegion[ portTOTAL_NUM_REGIONS ];
-} xMPU_SETTINGS;
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-
-/* Constants used with memory barrier intrinsics. */
-#define portSY_FULL_READ_WRITE		( 15 )
-
-/*-----------------------------------------------------------*/
-
-/* SVC numbers for various services. */
-#define portSVC_START_SCHEDULER				0
-#define portSVC_YIELD						1
-#define portSVC_RAISE_PRIVILEGE				2
-
-/* Scheduler utilities. */
-
-#define portYIELD()				__asm{ SVC portSVC_YIELD }
-#define portYIELD_WITHIN_API() 													\
-{																				\
-	/* Set a PendSV to request a context switch. */								\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
-																				\
-	/* Barriers are normally not required but do ensure the code is completely	\
-	within the specified behaviour for the architecture. */						\
-	__dsb( portSY_FULL_READ_WRITE );											\
-	__isb( portSY_FULL_READ_WRITE );											\
-}
-/*-----------------------------------------------------------*/
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
-#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-#define portINLINE __inline
-
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE __forceinline
-#endif
-/*-----------------------------------------------------------*/
-
-extern BaseType_t xIsPrivileged( void );
-extern void vResetPrivilege( void );
-
-/**
- * @brief Checks whether or not the processor is privileged.
- *
- * @return 1 if the processor is already privileged, 0 otherwise.
- */
-#define portIS_PRIVILEGED()			xIsPrivileged()
-
-/**
- * @brief Raise an SVC request to raise privilege.
- */
-#define portRAISE_PRIVILEGE()		__asm { svc portSVC_RAISE_PRIVILEGE }
-
-/**
- * @brief Lowers the privilege level by setting the bit 0 of the CONTROL
- * register.
- */
-#define portRESET_PRIVILEGE()		vResetPrivilege()
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
-{
-	__asm
-	{
-		/* Barrier instructions are not used as this function is only used to
-		lower the BASEPRI value. */
-		msr basepri, ulBASEPRI
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortRaiseBASEPRI( void )
-{
-uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
-	__asm
-	{
-		/* Set BASEPRI to the max syscall priority to effect a critical
-		section. */
-		msr basepri, ulNewBASEPRI
-		dsb
-		isb
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
-{
-	__asm
-	{
-		/* Set BASEPRI to 0 so no interrupts are masked.  This function is only
-		used to lower the mask in an interrupt, so memory barriers are not
-		used. */
-		msr basepri, #0
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
-{
-uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
-	__asm
-	{
-		/* Set BASEPRI to the max syscall priority to effect a critical
-		section. */
-		mrs ulReturn, basepri
-		msr basepri, ulNewBASEPRI
-		dsb
-		isb
-	}
-
-	return ulReturn;
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
-{
-uint32_t ulCurrentInterrupt;
-BaseType_t xReturn;
-
-	/* Obtain the number of the currently executing interrupt. */
-	__asm
-	{
-		mrs ulCurrentInterrupt, ipsr
-	}
-
-	if( ulCurrentInterrupt == 0 )
-	{
-		xReturn = pdFALSE;
-	}
-	else
-	{
-		xReturn = pdTRUE;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM7/ReadMe.txt b/FreeRTOS/Source/portable/RVDS/ARM_CM7/ReadMe.txt
deleted file mode 100755
index 0a2e7fd..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM7/ReadMe.txt
+++ /dev/null
@@ -1,18 +0,0 @@
-There are two options for running FreeRTOS on ARM Cortex-M7 microcontrollers.
-The best option depends on the revision of the ARM Cortex-M7 core in use.  The
-revision is specified by an 'r' number, and a 'p' number, so will look something
-like 'r0p1'.  Check the documentation for the microcontroller in use to find the 
-revision of the Cortex-M7 core used in that microcontroller.  If in doubt, use 
-the FreeRTOS port provided specifically for r0p1 revisions, as that can be used
-with all core revisions.
-
-The first option is to use the ARM Cortex-M4F port, and the second option is to
-use the Cortex-M7 r0p1 port - the latter containing a minor errata workaround.
-
-If the revision of the ARM Cortex-M7 core is not r0p1 then either option can be
-used, but it is recommended to use the FreeRTOS ARM Cortex-M4F port located in 
-the /FreeRTOS/Source/portable/RVDS/ARM_CM4F directory.
-
-If the revision of the ARM Cortex-M7 core is r0p1 then use the FreeRTOS ARM
-Cortex-M7 r0p1 port located in the /FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1
-directory.
\ No newline at end of file
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/port.c b/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/port.c
deleted file mode 100755
index d5a4557..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/port.c
+++ /dev/null
@@ -1,774 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#ifndef __TARGET_FPU_VFP
-	#error This port can only be used when the project options are configured to enable hardware floating point support.
-#endif
-
-#if configMAX_SYSCALL_INTERRUPT_PRIORITY == 0
-	#error configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.  See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html
-#endif
-
-#ifndef configSYSTICK_CLOCK_HZ
-	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
-	/* Ensure the SysTick is clocked at the same frequency as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
-#else
-	/* The way the SysTick is clocked is not modified in case it is not the same
-	as the core. */
-	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
-#endif
-
-/* The __weak attribute does not work as you might expect with the Keil tools
-so the configOVERRIDE_DEFAULT_TICK_CONFIGURATION constant must be set to 1 if
-the application writer wants to provide their own implementation of
-vPortSetupTimerInterrupt().  Ensure configOVERRIDE_DEFAULT_TICK_CONFIGURATION
-is defined. */
-#ifndef configOVERRIDE_DEFAULT_TICK_CONFIGURATION
-	#define configOVERRIDE_DEFAULT_TICK_CONFIGURATION 0
-#endif
-
-/* Constants required to manipulate the core.  Registers first... */
-#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
-#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
-#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
-#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
-/* ...then bits in the registers. */
-#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
-#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
-#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
-#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
-#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
-
-#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
-#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
-
-/* Constants required to check the validity of an interrupt priority. */
-#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
-#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
-#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
-#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
-#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
-#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
-#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
-#define portPRIGROUP_SHIFT					( 8UL )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK					( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR					( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS	( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR			( 0x01000000 )
-#define portINITIAL_EXC_RETURN		( 0xfffffffd )
-
-/* The systick is a 24-bit counter. */
-#define portMAX_24_BIT_NUMBER		( 0xffffffUL )
-
-/* A fiddle factor to estimate the number of SysTick counts that would have
-occurred while the SysTick counter is stopped during tickless idle
-calculations. */
-#define portMISSED_COUNTS_FACTOR	( 45UL )
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK		( ( StackType_t ) 0xfffffffeUL )
-
-/*
- * Setup the timer to generate the tick interrupts.  The implementation in this
- * file is weak to allow application writers to change the timer used to
- * generate the tick interrupt.
- */
-void vPortSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void xPortPendSVHandler( void );
-void xPortSysTickHandler( void );
-void vPortSVCHandler( void );
-
-/*
- * Start first task is a separate function so it can be tested in isolation.
- */
-static void prvStartFirstTask( void );
-
-/*
- * Functions defined in portasm.s to enable the VFP.
- */
-static void prvEnableVFP( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/*
- * The number of SysTick increments that make up one tick period.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulTimerCountsForOneTick = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * The maximum number of tick periods that can be suppressed is limited by the
- * 24 bit resolution of the SysTick timer.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t xMaximumPossibleSuppressedTicks = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Compensate for the CPU cycles that pass while the SysTick is stopped (low
- * power functionality only.
- */
-#if( configUSE_TICKLESS_IDLE == 1 )
-	static uint32_t ulStoppedTimerCompensation = 0;
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*
- * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
- * FreeRTOS API functions are not called from interrupts that have been assigned
- * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
- */
-#if ( configASSERT_DEFINED == 1 )
-	 static uint8_t ucMaxSysCallPriority = 0;
-	 static uint32_t ulMaxPRIGROUPValue = 0;
-	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( uint8_t * ) portNVIC_IP_REGISTERS_OFFSET_16;
-#endif /* configASSERT_DEFINED */
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-
-	/* Offset added to account for the way the MCU uses the stack on entry/exit
-	of interrupts, and to ensure alignment. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) prvTaskExitError;	/* LR */
-
-	/* Save code space by skipping register initialisation. */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-
-	/* A save method is being used that requires each task to maintain its
-	own exec return value. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-__asm void vPortSVCHandler( void )
-{
-	PRESERVE8
-
-	/* Get the location of the current TCB. */
-	ldr	r3, =pxCurrentTCB
-	ldr r1, [r3]
-	ldr r0, [r1]
-	/* Pop the core registers. */
-	ldmia r0!, {r4-r11, r14}
-	msr psp, r0
-	isb
-	mov r0, #0
-	msr	basepri, r0
-	bx r14
-}
-/*-----------------------------------------------------------*/
-
-__asm void prvStartFirstTask( void )
-{
-	PRESERVE8
-
-	/* Use the NVIC offset register to locate the stack. */
-	ldr r0, =0xE000ED08
-	ldr r0, [r0]
-	ldr r0, [r0]
-	/* Set the msp back to the start of the stack. */
-	msr msp, r0
-	/* Clear the bit that indicates the FPU is in use in case the FPU was used
-	before the scheduler was started - which would otherwise result in the
-	unnecessary leaving of space in the SVC stack for lazy saving of FPU
-	registers. */
-	mov r0, #0
-	msr control, r0
-	/* Globally enable interrupts. */
-	cpsie i
-	cpsie f
-	dsb
-	isb
-	/* Call SVC to start the first task. */
-	svc 0
-	nop
-	nop
-}
-/*-----------------------------------------------------------*/
-
-__asm void prvEnableVFP( void )
-{
-	PRESERVE8
-
-	/* The FPU enable bits are in the CPACR. */
-	ldr.w r0, =0xE000ED88
-	ldr	r1, [r0]
-
-	/* Enable CP10 and CP11 coprocessors, then save back. */
-	orr	r1, r1, #( 0xf << 20 )
-	str r1, [r0]
-	bx	r14
-	nop
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	#if( configASSERT_DEFINED == 1 )
-	{
-		volatile uint32_t ulOriginalPriority;
-		volatile uint8_t * const pucFirstUserPriorityRegister = ( uint8_t * ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
-		volatile uint8_t ucMaxPriorityValue;
-
-		/* Determine the maximum priority from which ISR safe FreeRTOS API
-		functions can be called.  ISR safe functions are those that end in
-		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
-		ensure interrupt entry is as fast and simple as possible.
-
-		Save the interrupt priority value that is about to be clobbered. */
-		ulOriginalPriority = *pucFirstUserPriorityRegister;
-
-		/* Determine the number of priority bits available.  First write to all
-		possible bits. */
-		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
-
-		/* Read the value back to see how many bits stuck. */
-		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
-
-		/* The kernel interrupt priority should be set to the lowest
-		priority. */
-		configASSERT( ucMaxPriorityValue == ( configKERNEL_INTERRUPT_PRIORITY & ucMaxPriorityValue ) );
-
-		/* Use the same mask on the maximum system call priority. */
-		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
-
-		/* Calculate the maximum acceptable priority group value for the number
-		of bits read back. */
-		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
-		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
-		{
-			ulMaxPRIGROUPValue--;
-			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
-		}
-
-		#ifdef __NVIC_PRIO_BITS
-		{
-			/* Check the CMSIS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == __NVIC_PRIO_BITS );
-		}
-		#endif
-
-		#ifdef configPRIO_BITS
-		{
-			/* Check the FreeRTOS configuration that defines the number of
-			priority bits matches the number of priority bits actually queried
-			from the hardware. */
-			configASSERT( ( portMAX_PRIGROUP_BITS - ulMaxPRIGROUPValue ) == configPRIO_BITS );
-		}
-		#endif
-
-		/* Shift the priority group value back to its position within the AIRCR
-		register. */
-		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
-		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
-
-		/* Restore the clobbered interrupt priority register to its original
-		value. */
-		*pucFirstUserPriorityRegister = ulOriginalPriority;
-	}
-	#endif /* conifgASSERT_DEFINED */
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
-	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	vPortSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	uxCriticalNesting = 0;
-
-	/* Ensure the VFP is enabled - it should be anyway. */
-	prvEnableVFP();
-
-	/* Lazy save always. */
-	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
-	/* Start the first task. */
-	prvStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( uxCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( uxCriticalNesting == 1 )
-	{
-		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( uxCriticalNesting );
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-__asm void xPortPendSVHandler( void )
-{
-	extern uxCriticalNesting;
-	extern pxCurrentTCB;
-	extern vTaskSwitchContext;
-
-	PRESERVE8
-
-	mrs r0, psp
-	isb
-	/* Get the location of the current TCB. */
-	ldr	r3, =pxCurrentTCB
-	ldr	r2, [r3]
-
-	/* Is the task using the FPU context?  If so, push high vfp registers. */
-	tst r14, #0x10
-	it eq
-	vstmdbeq r0!, {s16-s31}
-
-	/* Save the core registers. */
-	stmdb r0!, {r4-r11, r14}
-
-	/* Save the new top of stack into the first member of the TCB. */
-	str r0, [r2]
-
-	stmdb sp!, {r0, r3}
-	mov r0, #configMAX_SYSCALL_INTERRUPT_PRIORITY
-	cpsid i
-	msr basepri, r0
-	dsb
-	isb
-	cpsie i
-	bl vTaskSwitchContext
-	mov r0, #0
-	msr basepri, r0
-	ldmia sp!, {r0, r3}
-
-	/* The first item in pxCurrentTCB is the task top of stack. */
-	ldr r1, [r3]
-	ldr r0, [r1]
-
-	/* Pop the core registers. */
-	ldmia r0!, {r4-r11, r14}
-
-	/* Is the task using the FPU context?  If so, pop the high vfp registers
-	too. */
-	tst r14, #0x10
-	it eq
-	vldmiaeq r0!, {s16-s31}
-
-	msr psp, r0
-	isb
-	#ifdef WORKAROUND_PMU_CM001 /* XMC4000 specific errata */
-		#if WORKAROUND_PMU_CM001 == 1
-			push { r14 }
-			pop { pc }
-			nop
-		#endif
-	#endif
-
-	bx r14
-}
-/*-----------------------------------------------------------*/
-
-void xPortSysTickHandler( void )
-{
-	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
-	executes all interrupts must be unmasked.  There is therefore no need to
-	save and then restore the interrupt mask value as its value is already
-	known - therefore the slightly faster vPortRaiseBASEPRI() function is used
-	in place of portSET_INTERRUPT_MASK_FROM_ISR(). */
-	vPortRaiseBASEPRI();
-	{
-		/* Increment the RTOS tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* A context switch is required.  Context switching is performed in
-			the PendSV interrupt.  Pend the PendSV interrupt. */
-			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
-		}
-	}
-	vPortClearBASEPRIFromISR();
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TICKLESS_IDLE == 1 )
-
-	__weak void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements;
-	TickType_t xModifiableIdleTime;
-
-		/* Make sure the SysTick reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
-		is accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
-
-		/* Calculate the reload value required to wait xExpectedIdleTime
-		tick periods.  -1 is used because this code will execute part way
-		through one of the tick periods. */
-		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
-		if( ulReloadValue > ulStoppedTimerCompensation )
-		{
-			ulReloadValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Enter a critical section but don't use the taskENTER_CRITICAL()
-		method as that will mask interrupts that should exit sleep mode. */
-		__disable_irq();
-		__dsb( portSY_FULL_READ_WRITE );
-		__isb( portSY_FULL_READ_WRITE );
-
-		/* If a context switch is pending or a task is waiting for the scheduler
-		to be unsuspended then abandon the low power entry. */
-		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
-		{
-			/* Restart from whatever is left in the count register to complete
-			this tick period. */
-			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Reset the reload register to the value required for normal tick
-			periods. */
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Re-enable interrupts - see comments above __disable_irq() call
-			above. */
-			__enable_irq();
-		}
-		else
-		{
-			/* Set the new reload value. */
-			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
-
-			/* Clear the SysTick count flag and set the count value back to
-			zero. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-			/* Restart SysTick. */
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-
-			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
-			set its parameter to 0 to indicate that its implementation contains
-			its own wait for interrupt or wait for event instruction, and so wfi
-			should not be executed again.  However, the original expected idle
-			time variable must remain unmodified, so a copy is taken. */
-			xModifiableIdleTime = xExpectedIdleTime;
-			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
-			if( xModifiableIdleTime > 0 )
-			{
-				__dsb( portSY_FULL_READ_WRITE );
-				__wfi();
-				__isb( portSY_FULL_READ_WRITE );
-			}
-			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-
-			/* Re-enable interrupts to allow the interrupt that brought the MCU
-			out of sleep mode to execute immediately.  see comments above
-			__disable_interrupt() call above. */
-			__enable_irq();
-			__dsb( portSY_FULL_READ_WRITE );
-			__isb( portSY_FULL_READ_WRITE );
-
-			/* Disable interrupts again because the clock is about to be stopped
-			and interrupts that execute while the clock is stopped will increase
-			any slippage between the time maintained by the RTOS and calendar
-			time. */
-			__disable_irq();
-			__dsb( portSY_FULL_READ_WRITE );
-			__isb( portSY_FULL_READ_WRITE );
-
-			/* Disable the SysTick clock without reading the
-			portNVIC_SYSTICK_CTRL_REG register to ensure the
-			portNVIC_SYSTICK_COUNT_FLAG_BIT is not cleared if it is set.  Again,
-			the time the SysTick is stopped for is accounted for as best it can
-			be, but using the tickless mode will inevitably result in some tiny
-			drift of the time maintained by the kernel with respect to calendar
-			time*/
-			portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT );
-
-			/* Determine if the SysTick clock has already counted to zero and
-			been set back to the current reload value (the reload back being
-			correct for the entire expected idle time) or if the SysTick is yet
-			to count to zero (in which case an interrupt other than the SysTick
-			must have brought the system out of sleep mode). */
-			if( ( portNVIC_SYSTICK_CTRL_REG & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
-			{
-				uint32_t ulCalculatedLoadValue;
-
-				/* The tick interrupt is already pending, and the SysTick count
-				reloaded with ulReloadValue.  Reset the
-				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
-				period. */
-				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
-
-				/* Don't allow a tiny value, or values that have somehow
-				underflowed because the post sleep hook did something
-				that took too long. */
-				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
-				{
-					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
-				}
-
-				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
-
-				/* As the pending tick will be processed as soon as this
-				function exits, the tick value maintained by the tick is stepped
-				forward by one less than the time spent waiting. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				Work out how long the sleep lasted rounded to complete tick
-				periods (not the ulReload value which accounted for part
-				ticks). */
-				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
-
-				/* How many complete tick periods passed while the processor
-				was waiting? */
-				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
-
-				/* The reload value is set to whatever fraction of a single tick
-				period remains. */
-				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
-			}
-
-			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
-			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
-			value. */
-			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
-			vTaskStepTick( ulCompleteTickPeriods );
-			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
-
-			/* Exit with interrpts enabled. */
-			__enable_irq();
-		}
-	}
-
-#endif /* #if configUSE_TICKLESS_IDLE */
-
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the SysTick timer to generate the tick interrupts at the required
- * frequency.
- */
-#if( configOVERRIDE_DEFAULT_TICK_CONFIGURATION == 0 )
-
-	void vPortSetupTimerInterrupt( void )
-	{
-		/* Calculate the constants required to configure the tick interrupt. */
-		#if( configUSE_TICKLESS_IDLE == 1 )
-		{
-			ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
-			xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
-			ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
-		}
-		#endif /* configUSE_TICKLESS_IDLE */
-
-		/* Stop and clear the SysTick. */
-		portNVIC_SYSTICK_CTRL_REG = 0UL;
-		portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
-
-		/* Configure SysTick to interrupt at the requested rate. */
-		portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-		portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
-	}
-
-#endif /* configOVERRIDE_DEFAULT_TICK_CONFIGURATION */
-/*-----------------------------------------------------------*/
-
-__asm uint32_t vPortGetIPSR( void )
-{
-	PRESERVE8
-
-	mrs r0, ipsr
-	bx r14
-}
-/*-----------------------------------------------------------*/
-
-#if( configASSERT_DEFINED == 1 )
-
-	void vPortValidateInterruptPriority( void )
-	{
-	uint32_t ulCurrentInterrupt;
-	uint8_t ucCurrentPriority;
-
-		/* Obtain the number of the currently executing interrupt. */
-		ulCurrentInterrupt = vPortGetIPSR();
-
-		/* Is the interrupt number a user defined interrupt? */
-		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
-		{
-			/* Look up the interrupt's priority. */
-			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
-
-			/* The following assertion will fail if a service routine (ISR) for
-			an interrupt that has been assigned a priority above
-			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
-			function.  ISR safe FreeRTOS API functions must *only* be called
-			from interrupts that have been assigned a priority at or below
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Numerically low interrupt priority numbers represent logically high
-			interrupt priorities, therefore the priority of the interrupt must
-			be set to a value equal to or numerically *higher* than
-			configMAX_SYSCALL_INTERRUPT_PRIORITY.
-
-			Interrupts that	use the FreeRTOS API must not be left at their
-			default priority of	zero as that is the highest possible priority,
-			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
-			and	therefore also guaranteed to be invalid.
-
-			FreeRTOS maintains separate thread and ISR API functions to ensure
-			interrupt entry is as fast and simple as possible.
-
-			The following links provide detailed information:
-			http://www.freertos.org/RTOS-Cortex-M3-M4.html
-			http://www.freertos.org/FAQHelp.html */
-			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
-		}
-
-		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
-		that define each interrupt's priority to be split between bits that
-		define the interrupt's pre-emption priority bits and bits that define
-		the interrupt's sub-priority.  For simplicity all bits must be defined
-		to be pre-emption priority bits.  The following assertion will fail if
-		this is not the case (if some bits represent a sub-priority).
-
-		If the application only uses CMSIS libraries for interrupt
-		configuration then the correct setting can be achieved on all Cortex-M
-		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
-		scheduler.  Note however that some vendor specific peripheral libraries
-		assume a non-zero priority group setting, in which cases using a value
-		of zero will result in unpredictable behaviour. */
-		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
-	}
-
-#endif /* configASSERT_DEFINED */
-
-
diff --git a/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h b/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
deleted file mode 100755
index 7004756..0000000
--- a/FreeRTOS/Source/portable/RVDS/ARM_CM7/r0p1/portmacro.h
+++ /dev/null
@@ -1,256 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-
-/* Constants used with memory barrier intrinsics. */
-#define portSY_FULL_READ_WRITE		( 15 )
-
-/*-----------------------------------------------------------*/
-
-/* Scheduler utilities. */
-#define portYIELD()																\
-{																				\
-	/* Set a PendSV to request a context switch. */								\
-	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
-																				\
-	/* Barriers are normally not required but do ensure the code is completely	\
-	within the specified behaviour for the architecture. */						\
-	__dsb( portSY_FULL_READ_WRITE );											\
-	__isb( portSY_FULL_READ_WRITE );											\
-}
-/*-----------------------------------------------------------*/
-
-#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
-#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
-#define portENABLE_INTERRUPTS()					vPortSetBASEPRI( 0 )
-#define portENTER_CRITICAL()					vPortEnterCritical()
-#define portEXIT_CRITICAL()						vPortExitCritical()
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( x )	vPortSetBASEPRI( x )
-
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-/*-----------------------------------------------------------*/
-
-/* Port specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __clz( ( uxReadyPriorities ) ) )
-
-#endif /* taskRECORD_READY_PRIORITY */
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not necessary for to use this port.  They are defined so the common demo files
-(which build with all the ports) will build. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-/*-----------------------------------------------------------*/
-
-#ifdef configASSERT
-	void vPortValidateInterruptPriority( void );
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
-#endif
-
-/* portNOP() is not required by this port. */
-#define portNOP()
-
-#define portINLINE __inline
-
-#ifndef portFORCE_INLINE
-	#define portFORCE_INLINE __forceinline
-#endif
-
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortSetBASEPRI( uint32_t ulBASEPRI )
-{
-	__asm
-	{
-		/* Barrier instructions are not used as this function is only used to
-		lower the BASEPRI value. */
-		msr basepri, ulBASEPRI
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortRaiseBASEPRI( void )
-{
-uint32_t ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
-	__asm
-	{
-		/* Set BASEPRI to the max syscall priority to effect a critical
-		section. */
-		cpsid i
-		msr basepri, ulNewBASEPRI
-		dsb
-		isb
-		cpsie i
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE void vPortClearBASEPRIFromISR( void )
-{
-	__asm
-	{
-		/* Set BASEPRI to 0 so no interrupts are masked.  This function is only
-		used to lower the mask in an interrupt, so memory barriers are not 
-		used. */
-		msr basepri, #0
-	}
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE uint32_t ulPortRaiseBASEPRI( void )
-{
-uint32_t ulReturn, ulNewBASEPRI = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
-	__asm
-	{
-		/* Set BASEPRI to the max syscall priority to effect a critical
-		section. */
-		mrs ulReturn, basepri
-		cpsid i
-		msr basepri, ulNewBASEPRI
-		dsb
-		isb
-		cpsie i
-	}
-
-	return ulReturn;
-}
-/*-----------------------------------------------------------*/
-
-static portFORCE_INLINE BaseType_t xPortIsInsideInterrupt( void )
-{
-uint32_t ulCurrentInterrupt;
-BaseType_t xReturn;
-
-	/* Obtain the number of the currently executing interrupt. */
-	__asm
-	{
-		mrs ulCurrentInterrupt, ipsr
-	}
-
-	if( ulCurrentInterrupt == 0 )
-	{
-		xReturn = pdFALSE;
-	}
-	else
-	{
-		xReturn = pdTRUE;
-	}
-
-	return xReturn;
-}
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/Renesas/RX100/port.c b/FreeRTOS/Source/portable/Renesas/RX100/port.c
deleted file mode 100755
index edc3efe..0000000
--- a/FreeRTOS/Source/portable/Renesas/RX100/port.c
+++ /dev/null
@@ -1,646 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the RX100 port.
- *----------------------------------------------------------*/
-
-/* Standard C includes. */
-#include "limits.h"
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#include "iodefine.h"
-
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
-
-/* The peripheral clock is divided by this value before being supplying the
-CMT. */
-#if ( configUSE_TICKLESS_IDLE == 0 )
-	/* If tickless idle is not used then the divisor can be fixed. */
-	#define portCLOCK_DIVISOR	8UL
-#elif ( configPERIPHERAL_CLOCK_HZ >= 12000000 )
-	#define portCLOCK_DIVISOR	512UL
-#elif ( configPERIPHERAL_CLOCK_HZ >= 6000000 )
-	#define portCLOCK_DIVISOR	128UL
-#elif ( configPERIPHERAL_CLOCK_HZ >= 1000000 )
-	#define portCLOCK_DIVISOR	32UL
-#else
-	#define portCLOCK_DIVISOR	8UL
-#endif
-
-
-/* Keys required to lock and unlock access to certain system registers
-respectively. */
-#define portUNLOCK_KEY		0xA50B
-#define portLOCK_KEY		0xA500
-
-/*-----------------------------------------------------------*/
-
-/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- and therefore installed in the vector table, when the FreeRTOS code is built
-as a library. */
-extern BaseType_t vSoftwareInterruptEntry;
-const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-static void prvStartFirstTask( void );
-
-/*
- * Software interrupt handler.  Performs the actual context switch (saving and
- * restoring of registers).  Written in asm code as direct register access is
- * required.
- */
-static void prvYieldHandler( void );
-
-/*
- * The entry point for the software interrupt handler.  This is the function
- * that calls the inline asm function prvYieldHandler().  It is installed in
- * the vector table, but the code that installs it is in prvYieldHandler rather
- * than using a #pragma.
- */
-void vSoftwareInterruptISR( void );
-
-/*
- * Sets up the periodic ISR used for the RTOS tick using the CMT.
- * The application writer can define configSETUP_TICK_INTERRUPT() (in
- * FreeRTOSConfig.h) such that their own tick interrupt configuration is used
- * in place of prvSetupTimerInterrupt().
- */
-static void prvSetupTimerInterrupt( void );
-#ifndef configSETUP_TICK_INTERRUPT
-	/* The user has not provided their own tick interrupt configuration so use
-    the definition in this file (which uses the interval timer). */
-	#define configSETUP_TICK_INTERRUPT() prvSetupTimerInterrupt()
-#endif /* configSETUP_TICK_INTERRUPT */
-
-/*
- * Called after the sleep mode registers have been configured, prvSleep()
- * executes the pre and post sleep macros, and actually calls the wait
- * instruction.
- */
-#if configUSE_TICKLESS_IDLE == 1
-	static void prvSleep( TickType_t xExpectedIdleTime );
-#endif /* configUSE_TICKLESS_IDLE */
-
-/*-----------------------------------------------------------*/
-
-/* These is accessed by the inline assembler functions. */
-extern void *pxCurrentTCB;
-extern void vTaskSwitchContext( void );
-
-/*-----------------------------------------------------------*/
-
-/* Calculate how many clock increments make up a single tick period. */
-static const uint32_t ulMatchValueForOneTick = ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
-
-#if configUSE_TICKLESS_IDLE == 1
-
-	/* Holds the maximum number of ticks that can be suppressed - which is
-	basically how far into the future an interrupt can be generated. Set
-	during initialisation.  This is the maximum possible value that the
-	compare match register can hold divided by ulMatchValueForOneTick. */
-	static const TickType_t xMaximumPossibleSuppressedTicks = USHRT_MAX / ( ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) / configTICK_RATE_HZ );
-
-	/* Flag set from the tick interrupt to allow the sleep processing to know if
-	sleep mode was exited because of a tick interrupt, or an interrupt
-	generated by something else. */
-	static volatile uint32_t ulTickFlag = pdFALSE;
-
-	/* The CMT counter is stopped temporarily each time it is re-programmed.
-	The following constant offsets the CMT counter match value by the number of
-	CMT	counts that would typically be missed while the counter was stopped to
-	compensate for the lost time.  The large difference between the divided CMT
-	clock and the CPU clock means it is likely ulStoppedTimerCompensation will
-	equal zero - and be optimised away. */
-	static const uint32_t ulStoppedTimerCompensation = 100UL / ( configCPU_CLOCK_HZ / ( configPERIPHERAL_CLOCK_HZ / portCLOCK_DIVISOR ) );
-
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Offset to end up on 8 byte boundary. */
-	pxTopOfStack--;
-
-	/* R0 is not included as it is the stack pointer. */
-	*pxTopOfStack = 0x00;
-	pxTopOfStack--;
-    *pxTopOfStack = 0x00;
-	pxTopOfStack--;
- 	*pxTopOfStack = portINITIAL_PSW;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;
-
-	/* When debugging it can be useful if every register is set to a known
-	value.  Otherwise code space can be saved by just setting the registers
-	that need to be set. */
-	#ifdef USE_FULL_REGISTER_INITIALISATION
-	{
-		pxTopOfStack--;
-		*pxTopOfStack = 0x12345678;	/* r15. */
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaabbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xdddddddd;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xcccccccc;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xbbbbbbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaaaaaa;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x99999999;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x88888888;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x77777777;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x66666666;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x55555555;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x44444444;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x33333333;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x22222222;
-		pxTopOfStack--;
-	}
-	#else
-	{
-		/* Leave space for the registers that will get popped from the stack
-		when the task first starts executing. */
-		pxTopOfStack -= 15;
-	}
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x12345678; /* Accumulator. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x87654321; /* Accumulator. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Use pxCurrentTCB just so it does not get optimised away. */
-	if( pxCurrentTCB != NULL )
-	{
-		/* Call an application function to set up the timer that will generate
-		the tick interrupt.  This way the application can decide which
-		peripheral to use.  If tickless mode is used then the default
-		implementation defined in this file (which uses CMT0) should not be
-		overridden. */
-		configSETUP_TICK_INTERRUPT();
-
-		/* Enable the software interrupt. */
-		_IEN( _ICU_SWINT ) = 1;
-
-		/* Ensure the software interrupt is clear. */
-		_IR( _ICU_SWINT ) = 0;
-
-		/* Ensure the software interrupt is set to the kernel priority. */
-		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
-		/* Start the first task. */
-		prvStartFirstTask();
-	}
-
-	/* Execution should not reach here as the tasks are now running!
-	prvSetupTimerInterrupt() is called here to prevent the compiler outputting
-	a warning about a statically declared function not being referenced in the
-	case that the application writer has provided their own tick interrupt
-	configuration routine (and defined configSETUP_TICK_INTERRUPT() such that
-	their own routine will be called in place of prvSetupTimerInterrupt()). */
-	prvSetupTimerInterrupt();
-
-	/* Just to make sure the function is not optimised away. */
-	( void ) vSoftwareInterruptISR();
-
-	/* Should not get here. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-#pragma inline_asm prvStartFirstTask
-static void prvStartFirstTask( void )
-{
-	/* When starting the scheduler there is nothing that needs moving to the
-	interrupt stack because the function is not called from an interrupt.
-	Just ensure the current stack is the user stack. */
-	SETPSW	U
-
-	/* Obtain the location of the stack associated with which ever task
-	pxCurrentTCB is currently pointing to. */
-	MOV.L	#_pxCurrentTCB, R15
-	MOV.L	[R15], R15
-	MOV.L	[R15], R0
-
-	/* Restore the registers from the stack of the task pointed to by
-	pxCurrentTCB. */
-    POP		R15
-    MVTACLO	R15 		/* Accumulator low 32 bits. */
-    POP		R15
-    MVTACHI	R15 		/* Accumulator high 32 bits. */
-    POPM	R1-R15 		/* R1 to R15 - R0 is not included as it is the SP. */
-    RTE					/* This pops the remaining registers. */
-    NOP
-    NOP
-}
-/*-----------------------------------------------------------*/
-
-#pragma interrupt ( prvTickISR( vect = configTICK_VECTOR, enable ) )
-void prvTickISR( void )
-{
-	/* Increment the tick, and perform any processing the new tick value
-	necessitates. */
-	set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			taskYIELD();
-		}
-	}
-	set_ipl( configKERNEL_INTERRUPT_PRIORITY );
-
-	#if configUSE_TICKLESS_IDLE == 1
-	{
-		/* The CPU woke because of a tick. */
-		ulTickFlag = pdTRUE;
-
-		/* If this is the first tick since exiting tickless mode then the CMT
-		compare match value needs resetting. */
-		CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
-	}
-	#endif
-}
-/*-----------------------------------------------------------*/
-
-void vSoftwareInterruptISR( void )
-{
-	prvYieldHandler();
-}
-/*-----------------------------------------------------------*/
-
-#pragma inline_asm prvYieldHandler
-static void prvYieldHandler( void )
-{
-	/* Re-enable interrupts. */
-	SETPSW	I
-
-	/* Move the data that was automatically pushed onto the interrupt stack
-	when the interrupt occurred from the interrupt stack to the user stack.
-
-	R15 is saved before it is clobbered. */
-	PUSH.L	R15
-
-	/* Read the user stack pointer. */
-	MVFC	USP, R15
-
-	/* Move the address down to the data being moved. */
-	SUB		#12, R15
-	MVTC	R15, USP
-
-	/* Copy the data across. */
-	MOV.L	[ R0 ], [ R15 ] ; R15
-	MOV.L 	4[ R0 ], 4[ R15 ]  ; PC
-	MOV.L	8[ R0 ], 8[ R15 ]  ; PSW
-
-	/* Move the interrupt stack pointer to its new correct position. */
-	ADD	#12, R0
-
-	/* All the rest of the registers are saved directly to the user stack. */
-	SETPSW	U
-
-	/* Save the rest of the general registers (R15 has been saved already). */
-	PUSHM	R1-R14
-
-	/* Save the accumulator. */
-	MVFACHI	R15
-	PUSH.L	R15
-	MVFACMI	R15	; Middle order word.
-	SHLL	#16, R15 ; Shifted left as it is restored to the low order word.
-	PUSH.L	R15
-
-	/* Save the stack pointer to the TCB. */
-	MOV.L	#_pxCurrentTCB, R15
-	MOV.L	[ R15 ], R15
-	MOV.L	R0, [ R15 ]
-
-	/* Ensure the interrupt mask is set to the syscall priority while the
-	kernel structures are being accessed. */
-	MVTIPL	#configMAX_SYSCALL_INTERRUPT_PRIORITY
-
-	/* Select the next task to run. */
-	BSR.A	_vTaskSwitchContext
-
-	/* Reset the interrupt mask as no more data structure access is
-	required. */
-	MVTIPL	#configKERNEL_INTERRUPT_PRIORITY
-
-	/* Load the stack pointer of the task that is now selected as the Running
-	state task from its TCB. */
-	MOV.L	#_pxCurrentTCB,R15
-	MOV.L	[ R15 ], R15
-	MOV.L	[ R15 ], R0
-
-	/* Restore the context of the new task.  The PSW (Program Status Word) and
-	PC will be popped by the RTE instruction. */
-	POP		R15
-	MVTACLO	R15
-	POP		R15
-	MVTACHI	R15
-	POPM	R1-R15
-	RTE
-	NOP
-	NOP
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( pxCurrentTCB == NULL );
-
-	/* The following line is just to prevent the symbol getting optimised away. */
-	( void ) vTaskSwitchContext();
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-	/* Unlock. */
-	SYSTEM.PRCR.WORD = portUNLOCK_KEY;
-
-	/* Enable CMT0. */
-	MSTP( CMT0 ) = 0;
-
-	/* Lock again. */
-	SYSTEM.PRCR.WORD = portLOCK_KEY;
-
-	/* Interrupt on compare match. */
-	CMT0.CMCR.BIT.CMIE = 1;
-
-	/* Set the compare match value. */
-	CMT0.CMCOR = ( uint16_t ) ulMatchValueForOneTick;
-
-	/* Divide the PCLK. */
-	#if portCLOCK_DIVISOR == 512
-	{
-		CMT0.CMCR.BIT.CKS = 3;
-	}
-	#elif portCLOCK_DIVISOR == 128
-	{
-		CMT0.CMCR.BIT.CKS = 2;
-	}
-	#elif portCLOCK_DIVISOR == 32
-	{
-		CMT0.CMCR.BIT.CKS = 1;
-	}
-	#elif portCLOCK_DIVISOR == 8
-	{
-		CMT0.CMCR.BIT.CKS = 0;
-	}
-	#else
-	{
-		#error Invalid portCLOCK_DIVISOR setting
-	}
-	#endif
-
-
-	/* Enable the interrupt... */
-	_IEN( _CMT0_CMI0 ) = 1;
-
-	/* ...and set its priority to the application defined kernel priority. */
-	_IPR( _CMT0_CMI0 ) = configKERNEL_INTERRUPT_PRIORITY;
-
-	/* Start the timer. */
-	CMT.CMSTR0.BIT.STR0 = 1;
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_TICKLESS_IDLE == 1
-
-	static void prvSleep( TickType_t xExpectedIdleTime )
-	{
-		/* Allow the application to define some pre-sleep processing. */
-		configPRE_SLEEP_PROCESSING( xExpectedIdleTime );
-
-		/* xExpectedIdleTime being set to 0 by configPRE_SLEEP_PROCESSING()
-		means the application defined code has already executed the WAIT
-		instruction. */
-		if( xExpectedIdleTime > 0 )
-		{
-			wait();
-		}
-
-		/* Allow the application to define some post sleep processing. */
-		configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-#if configUSE_TICKLESS_IDLE == 1
-
-	void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
-	{
-	uint32_t ulMatchValue, ulCompleteTickPeriods, ulCurrentCount;
-	eSleepModeStatus eSleepAction;
-
-		/* THIS FUNCTION IS CALLED WITH THE SCHEDULER SUSPENDED. */
-
-		/* Make sure the CMT reload value does not overflow the counter. */
-		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
-		{
-			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
-		}
-
-		/* Calculate the reload value required to wait xExpectedIdleTime tick
-		periods. */
-		ulMatchValue = ulMatchValueForOneTick * xExpectedIdleTime;
-		if( ulMatchValue > ulStoppedTimerCompensation )
-		{
-			/* Compensate for the fact that the CMT is going to be stopped
-			momentarily. */
-			ulMatchValue -= ulStoppedTimerCompensation;
-		}
-
-		/* Stop the CMT momentarily.  The time the CMT is stopped for is
-		accounted for as best it can be, but using the tickless mode will
-		inevitably result in some tiny drift of the time maintained by the
-		kernel with respect to calendar time. */
-		CMT.CMSTR0.BIT.STR0 = 0;
-		while( CMT.CMSTR0.BIT.STR0 == 1 )
-		{
-			/* Nothing to do here. */
-		}
-
-		/* Critical section using the global interrupt bit as the i bit is
-		automatically reset by the WAIT instruction. */
-		clrpsw_i();
-
-		/* The tick flag is set to false before sleeping.  If it is true when
-		sleep mode is exited then sleep mode was probably exited because the
-		tick was suppressed for the entire xExpectedIdleTime period. */
-		ulTickFlag = pdFALSE;
-
-		/* If a context switch is pending then abandon the low power entry as
-		the context switch might have been pended by an external interrupt that
-		requires processing. */
-		eSleepAction = eTaskConfirmSleepModeStatus();
-		if( eSleepAction == eAbortSleep )
-		{
-			/* Restart tick. */
-			CMT.CMSTR0.BIT.STR0 = 1;
-			setpsw_i();
-		}
-		else if( eSleepAction == eNoTasksWaitingTimeout )
-		{
-		    /* Protection off. */
-		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
-
-		    /* Ready for software standby with all clocks stopped. */
-			SYSTEM.SBYCR.BIT.SSBY = 1;
-
-		    /* Protection on. */
-		    SYSTEM.PRCR.WORD = portLOCK_KEY;
-
-			/* Sleep until something happens.  Calling prvSleep() will
-			automatically reset the i bit in the PSW. */
-			prvSleep( xExpectedIdleTime );
-
-			/* Restart the CMT. */
-			CMT.CMSTR0.BIT.STR0 = 1;
-		}
-		else
-		{
-		    /* Protection off. */
-		    SYSTEM.PRCR.WORD = portUNLOCK_KEY;
-
-		    /* Ready for deep sleep mode. */
-			SYSTEM.MSTPCRC.BIT.DSLPE = 1;
-			SYSTEM.MSTPCRA.BIT.MSTPA28 = 1;
-			SYSTEM.SBYCR.BIT.SSBY = 0;
-
-		    /* Protection on. */
-		    SYSTEM.PRCR.WORD = portLOCK_KEY;
-
-		    /* Adjust the match value to take into account that the current
-			time slice is already partially complete. */
-			ulMatchValue -= ( uint32_t ) CMT0.CMCNT;
-			CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-
-			/* Restart the CMT to count up to the new match value. */
-			CMT0.CMCNT = 0;
-			CMT.CMSTR0.BIT.STR0 = 1;
-
-			/* Sleep until something happens.  Calling prvSleep() will
-			automatically reset the i bit in the PSW. */
-			prvSleep( xExpectedIdleTime );
-
-			/* Stop CMT.  Again, the time the SysTick is stopped for is
-			accounted for as best it can be, but using the tickless mode will
-			inevitably result in some tiny drift of the time maintained by the
-			kernel with	respect to calendar time. */
-			CMT.CMSTR0.BIT.STR0 = 0;
-			while( CMT.CMSTR0.BIT.STR0 == 1 )
-			{
-				/* Nothing to do here. */
-			}
-
-			ulCurrentCount = ( uint32_t ) CMT0.CMCNT;
-
-			if( ulTickFlag != pdFALSE )
-			{
-				/* The tick interrupt has already executed, although because
-				this function is called with the scheduler suspended the actual
-				tick processing will not occur until after this function has
-				exited.  Reset the match value with whatever remains of this
-				tick period. */
-				ulMatchValue = ulMatchValueForOneTick - ulCurrentCount;
-				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-
-				/* The tick interrupt handler will already have pended the tick
-				processing in the kernel.  As the pending tick will be
-				processed as soon as this function exits, the tick value
-				maintained by the tick is stepped forward by one less than the
-				time spent sleeping.  The actual stepping of the tick appears
-				later in this function. */
-				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
-			}
-			else
-			{
-				/* Something other than the tick interrupt ended the sleep.
-				How	many complete tick periods passed while the processor was
-				sleeping? */
-				ulCompleteTickPeriods = ulCurrentCount / ulMatchValueForOneTick;
-
-				/* The match value is set to whatever fraction of a single tick
-				period remains. */
-				ulMatchValue = ulCurrentCount - ( ulCompleteTickPeriods * ulMatchValueForOneTick );
-				CMT0.CMCOR = ( uint16_t ) ulMatchValue;
-			}
-
-			/* Restart the CMT so it runs up to the match value.  The match value
-			will get set to the value required to generate exactly one tick period
-			the next time the CMT interrupt executes. */
-			CMT0.CMCNT = 0;
-			CMT.CMSTR0.BIT.STR0 = 1;
-
-			/* Wind the tick forward by the number of tick periods that the CPU
-			remained in a low power state. */
-			vTaskStepTick( ulCompleteTickPeriods );
-		}
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-
diff --git a/FreeRTOS/Source/portable/Renesas/RX100/port_asm.src b/FreeRTOS/Source/portable/Renesas/RX100/port_asm.src
deleted file mode 100755
index badce8b..0000000
--- a/FreeRTOS/Source/portable/Renesas/RX100/port_asm.src
+++ /dev/null
@@ -1,41 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-		.GLB	_vSoftwareInterruptISR
-                .GLB    _vSoftwareInterruptEntry
-
-		.SECTION   P,CODE
-
-_vSoftwareInterruptEntry:
-
-	BRA	_vSoftwareInterruptISR
-
-		.RVECTOR	27, _vSoftwareInterruptEntry
-
-		.END
-
-
-
diff --git a/FreeRTOS/Source/portable/Renesas/RX100/portmacro.h b/FreeRTOS/Source/portable/Renesas/RX100/portmacro.h
deleted file mode 100755
index a5aadf8..0000000
--- a/FreeRTOS/Source/portable/Renesas/RX100/portmacro.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Hardware specifics. */
-#include "machine.h"
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions - these are a bit legacy and not really used now, other
-than portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT				8	/* Could make four, according to manual. */
-#define portSTACK_GROWTH				-1
-#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()						nop()
-
-#pragma inline_asm vPortYield
-static void vPortYield( void )
-{
-	/* Save clobbered register - may not actually be necessary if inline asm
-	functions are considered to use the same rules as function calls by the
-	compiler. */
-	PUSH.L R5
-	/* Set ITU SWINTR. */
-	MOV.L #872E0H, R5
-	MOV.B #1, [R5]
-	/* Read back to ensure the value is taken before proceeding. */
-	MOV.L [R5], R5
-	/* Restore clobbered register to its previous value. */
-	POP R5
-}
-#define portYIELD()	vPortYield()
-#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) { portYIELD(); }
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() 	set_ipl( ( long ) 0 )
-#ifdef configASSERT
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-	#define portDISABLE_INTERRUPTS() 	if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#else
-	#define portDISABLE_INTERRUPTS() 	set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()	vTaskEnterCritical()
-#define portEXIT_CRITICAL()		vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( signed long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( signed long ) uxSavedInterruptStatus )
-
-/*-----------------------------------------------------------*/
-
-/* Tickless idle/low power functionality. */
-#if configUSE_TICKLESS_IDLE == 1
-	#ifndef portSUPPRESS_TICKS_AND_SLEEP
-		extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-		#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-	#endif
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/Renesas/RX200/port.c b/FreeRTOS/Source/portable/Renesas/RX200/port.c
deleted file mode 100755
index 0a52a61..0000000
--- a/FreeRTOS/Source/portable/Renesas/RX200/port.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the RX200 port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#include "iodefine.h"
-
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
-
-/*-----------------------------------------------------------*/
-
-/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- and therefore installed in the vector table, when the FreeRTOS code is built
-as a library. */
-extern BaseType_t vSoftwareInterruptEntry;
-const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-static void prvStartFirstTask( void );
-
-/*
- * Software interrupt handler.  Performs the actual context switch (saving and
- * restoring of registers).  Written in asm code as direct register access is
- * required.
- */
-static void prvYieldHandler( void );
-
-/*
- * The entry point for the software interrupt handler.  This is the function
- * that calls the inline asm function prvYieldHandler().  It is installed in
- * the vector table, but the code that installs it is in prvYieldHandler rather
- * than using a #pragma.
- */
-void vSoftwareInterruptISR( void );
-
-/*-----------------------------------------------------------*/
-
-/* This is accessed by the inline assembler functions so is file scope for
-convenience. */
-extern void *pxCurrentTCB;
-extern void vTaskSwitchContext( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Offset to end up on 8 byte boundary. */
-	pxTopOfStack--;
-
-	/* R0 is not included as it is the stack pointer. */
-	*pxTopOfStack = 0x00;
-	pxTopOfStack--;
-    *pxTopOfStack = 0x00;
-	pxTopOfStack--;
- 	*pxTopOfStack = portINITIAL_PSW;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;
-
-	/* When debugging it can be useful if every register is set to a known
-	value.  Otherwise code space can be saved by just setting the registers
-	that need to be set. */
-	#ifdef USE_FULL_REGISTER_INITIALISATION
-	{
-		pxTopOfStack--;
-		*pxTopOfStack = 0x12345678;	/* r15. */
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaabbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xdddddddd;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xcccccccc;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xbbbbbbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaaaaaa;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x99999999;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x88888888;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x77777777;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x66666666;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x55555555;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x44444444;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x33333333;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x22222222;
-		pxTopOfStack--;
-	}
-	#else
-	{
-		pxTopOfStack -= 15;
-	}
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x12345678; /* Accumulator. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x87654321; /* Accumulator. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vApplicationSetupTimerInterrupt( void );
-
-	/* Use pxCurrentTCB just so it does not get optimised away. */
-	if( pxCurrentTCB != NULL )
-	{
-		/* Call an application function to set up the timer that will generate the
-		tick interrupt.  This way the application can decide which peripheral to
-		use.  A demo application is provided to show a suitable example. */
-		vApplicationSetupTimerInterrupt();
-
-		/* Enable the software interrupt. */
-		_IEN( _ICU_SWINT ) = 1;
-
-		/* Ensure the software interrupt is clear. */
-		_IR( _ICU_SWINT ) = 0;
-
-		/* Ensure the software interrupt is set to the kernel priority. */
-		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
-		/* Start the first task. */
-		prvStartFirstTask();
-	}
-
-	/* Just to make sure the function is not optimised away. */
-	( void ) vSoftwareInterruptISR();
-
-	/* Should not get here. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-#pragma inline_asm prvStartFirstTask
-static void prvStartFirstTask( void )
-{
-	/* When starting the scheduler there is nothing that needs moving to the
-	interrupt stack because the function is not called from an interrupt.
-	Just ensure the current stack is the user stack. */
-	SETPSW	U
-
-	/* Obtain the location of the stack associated with which ever task
-	pxCurrentTCB is currently pointing to. */
-	MOV.L	#_pxCurrentTCB, R15
-	MOV.L	[R15], R15
-	MOV.L	[R15], R0
-
-	/* Restore the registers from the stack of the task pointed to by
-	pxCurrentTCB. */
-    POP		R15
-    MVTACLO	R15 		/* Accumulator low 32 bits. */
-    POP		R15
-    MVTACHI	R15 		/* Accumulator high 32 bits. */
-    POPM	R1-R15 		/* R1 to R15 - R0 is not included as it is the SP. */
-    RTE					/* This pops the remaining registers. */
-    NOP
-    NOP
-}
-/*-----------------------------------------------------------*/
-
-#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
-void vTickISR( void )
-{
-	/* Increment the tick, and perform any processing the new tick value
-	necessitates. */
-	set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			taskYIELD();
-		}
-	}
-	set_ipl( configKERNEL_INTERRUPT_PRIORITY );
-}
-/*-----------------------------------------------------------*/
-
-void vSoftwareInterruptISR( void )
-{
-	prvYieldHandler();
-}
-/*-----------------------------------------------------------*/
-
-#pragma inline_asm prvYieldHandler
-static void prvYieldHandler( void )
-{
-	/* Re-enable interrupts. */
-	SETPSW	I
-
-	/* Move the data that was automatically pushed onto the interrupt stack when
-	the interrupt occurred from the interrupt stack to the user stack.
-
-	R15 is saved before it is clobbered. */
-	PUSH.L	R15
-
-	/* Read the user stack pointer. */
-	MVFC	USP, R15
-
-	/* Move the address down to the data being moved. */
-	SUB		#12, R15
-	MVTC	R15, USP
-
-	/* Copy the data across. */
-	MOV.L	[ R0 ], [ R15 ] ; R15
-	MOV.L 	4[ R0 ], 4[ R15 ]  ; PC
-	MOV.L	8[ R0 ], 8[ R15 ]  ; PSW
-
-	/* Move the interrupt stack pointer to its new correct position. */
-	ADD	#12, R0
-
-	/* All the rest of the registers are saved directly to the user stack. */
-	SETPSW	U
-
-	/* Save the rest of the general registers (R15 has been saved already). */
-	PUSHM	R1-R14
-
-	/* Save the accumulator. */
-	MVFACHI	R15
-	PUSH.L	R15
-	MVFACMI	R15	; Middle order word.
-	SHLL	#16, R15 ; Shifted left as it is restored to the low order word.
-	PUSH.L	R15
-
-	/* Save the stack pointer to the TCB. */
-	MOV.L	#_pxCurrentTCB, R15
-	MOV.L	[ R15 ], R15
-	MOV.L	R0, [ R15 ]
-
-	/* Ensure the interrupt mask is set to the syscall priority while the kernel
-	structures are being accessed. */
-	MVTIPL	#configMAX_SYSCALL_INTERRUPT_PRIORITY
-
-	/* Select the next task to run. */
-	BSR.A	_vTaskSwitchContext
-
-	/* Reset the interrupt mask as no more data structure access is required. */
-	MVTIPL	#configKERNEL_INTERRUPT_PRIORITY
-
-	/* Load the stack pointer of the task that is now selected as the Running
-	state task from its TCB. */
-	MOV.L	#_pxCurrentTCB,R15
-	MOV.L	[ R15 ], R15
-	MOV.L	[ R15 ], R0
-
-	/* Restore the context of the new task.  The PSW (Program Status Word) and
-	PC will be popped by the RTE instruction. */
-	POP		R15
-	MVTACLO	R15
-	POP		R15
-	MVTACHI	R15
-	POPM	R1-R15
-	RTE
-	NOP
-	NOP
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( pxCurrentTCB == NULL );
-
-	/* The following line is just to prevent the symbol getting optimised away. */
-	( void ) vTaskSwitchContext();
-}
-/*-----------------------------------------------------------*/
-
-
-
diff --git a/FreeRTOS/Source/portable/Renesas/RX200/port_asm.src b/FreeRTOS/Source/portable/Renesas/RX200/port_asm.src
deleted file mode 100755
index badce8b..0000000
--- a/FreeRTOS/Source/portable/Renesas/RX200/port_asm.src
+++ /dev/null
@@ -1,41 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-		.GLB	_vSoftwareInterruptISR
-                .GLB    _vSoftwareInterruptEntry
-
-		.SECTION   P,CODE
-
-_vSoftwareInterruptEntry:
-
-	BRA	_vSoftwareInterruptISR
-
-		.RVECTOR	27, _vSoftwareInterruptEntry
-
-		.END
-
-
-
diff --git a/FreeRTOS/Source/portable/Renesas/RX200/portmacro.h b/FreeRTOS/Source/portable/Renesas/RX200/portmacro.h
deleted file mode 100755
index 62e9f87..0000000
--- a/FreeRTOS/Source/portable/Renesas/RX200/portmacro.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Hardware specifics. */
-#include "machine.h"
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT				8	/* Could make four, according to manual. */
-#define portSTACK_GROWTH				-1
-#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()						nop()
-
-#pragma inline_asm vPortYield
-static void vPortYield( void )
-{
-	/* Save clobbered register - may not actually be necessary if inline asm
-	functions are considered to use the same rules as function calls by the
-	compiler. */
-	PUSH.L R5
-	/* Set ITU SWINTR. */
-	MOV.L #553696, R5
-	MOV.B #1, [R5]
-	/* Read back to ensure the value is taken before proceeding. */
-	MOV.L [R5], R5
-	/* Restore clobbered register to its previous value. */
-	POP R5
-}
-#define portYIELD()	vPortYield()
-#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() 	set_ipl( ( long ) 0 )
-#ifdef configASSERT
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-	#define portDISABLE_INTERRUPTS() 	if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#else
-	#define portDISABLE_INTERRUPTS() 	set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()	vTaskEnterCritical()
-#define portEXIT_CRITICAL()		vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/Renesas/RX600/port.c b/FreeRTOS/Source/portable/Renesas/RX600/port.c
deleted file mode 100755
index 8e69801..0000000
--- a/FreeRTOS/Source/portable/Renesas/RX600/port.c
+++ /dev/null
@@ -1,329 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the RX600 port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#include "iodefine.h"
-
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
-
-/*-----------------------------------------------------------*/
-
-/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- and therefore installed in the vector table, when the FreeRTOS code is built
-as a library. */
-extern BaseType_t vSoftwareInterruptEntry;
-const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-static void prvStartFirstTask( void );
-
-/*
- * Software interrupt handler.  Performs the actual context switch (saving and
- * restoring of registers).  Written in asm code as direct register access is
- * required.
- */
-static void prvYieldHandler( void );
-
-/*
- * The entry point for the software interrupt handler.  This is the function
- * that calls the inline asm function prvYieldHandler().  It is installed in
- * the vector table, but the code that installs it is in prvYieldHandler rather
- * than using a #pragma.
- */
-void vSoftwareInterruptISR( void );
-
-/*-----------------------------------------------------------*/
-
-/* This is accessed by the inline assembler functions so is file scope for
-convenience. */
-extern void *pxCurrentTCB;
-extern void vTaskSwitchContext( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* R0 is not included as it is the stack pointer. */
-
-	*pxTopOfStack = 0x00;
-	pxTopOfStack--;
- 	*pxTopOfStack = portINITIAL_PSW;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;
-
-	/* When debugging it can be useful if every register is set to a known
-	value.  Otherwise code space can be saved by just setting the registers
-	that need to be set. */
-	#ifdef USE_FULL_REGISTER_INITIALISATION
-	{
-		pxTopOfStack--;
-		*pxTopOfStack = 0xffffffff;	/* r15. */
-		pxTopOfStack--;
-		*pxTopOfStack = 0xeeeeeeee;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xdddddddd;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xcccccccc;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xbbbbbbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaaaaaa;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x99999999;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x88888888;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x77777777;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x66666666;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x55555555;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x44444444;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x33333333;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x22222222;
-		pxTopOfStack--;
-	}
-	#else
-	{
-		pxTopOfStack -= 15;
-	}
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_FPSW;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x12345678; /* Accumulator. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x87654321; /* Accumulator. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vApplicationSetupTimerInterrupt( void );
-
-	/* Use pxCurrentTCB just so it does not get optimised away. */
-	if( pxCurrentTCB != NULL )
-	{
-		/* Call an application function to set up the timer that will generate the
-		tick interrupt.  This way the application can decide which peripheral to
-		use.  A demo application is provided to show a suitable example. */
-		vApplicationSetupTimerInterrupt();
-
-		/* Enable the software interrupt. */
-		_IEN( _ICU_SWINT ) = 1;
-
-		/* Ensure the software interrupt is clear. */
-		_IR( _ICU_SWINT ) = 0;
-
-		/* Ensure the software interrupt is set to the kernel priority. */
-		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
-		/* Start the first task. */
-		prvStartFirstTask();
-	}
-
-	/* Just to make sure the function is not optimised away. */
-	( void ) vSoftwareInterruptISR();
-
-	/* Should not get here. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-#pragma inline_asm prvStartFirstTask
-static void prvStartFirstTask( void )
-{
-	/* When starting the scheduler there is nothing that needs moving to the
-	interrupt stack because the function is not called from an interrupt.
-	Just ensure the current stack is the user stack. */
-	SETPSW	U
-
-	/* Obtain the location of the stack associated with which ever task
-	pxCurrentTCB is currently pointing to. */
-	MOV.L	#_pxCurrentTCB, R15
-	MOV.L	[R15], R15
-	MOV.L	[R15], R0
-
-	/* Restore the registers from the stack of the task pointed to by
-	pxCurrentTCB. */
-    POP		R15
-    MVTACLO	R15 		/* Accumulator low 32 bits. */
-    POP		R15
-    MVTACHI	R15 		/* Accumulator high 32 bits. */
-    POP		R15
-    MVTC	R15,FPSW 	/* Floating point status word. */
-    POPM	R1-R15 		/* R1 to R15 - R0 is not included as it is the SP. */
-    RTE					/* This pops the remaining registers. */
-    NOP
-    NOP
-}
-/*-----------------------------------------------------------*/
-
-#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
-void vTickISR( void )
-{
-	/* Increment the tick, and perform any processing the new tick value
-	necessitates. */
-	set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			taskYIELD();
-		}
-	}
-	set_ipl( configKERNEL_INTERRUPT_PRIORITY );
-}
-/*-----------------------------------------------------------*/
-
-void vSoftwareInterruptISR( void )
-{
-	prvYieldHandler();
-}
-/*-----------------------------------------------------------*/
-
-#pragma inline_asm prvYieldHandler
-static void prvYieldHandler( void )
-{
-	/* Re-enable interrupts. */
-	SETPSW	I
-
-	/* Move the data that was automatically pushed onto the interrupt stack when
-	the interrupt occurred from the interrupt stack to the user stack.
-
-	R15 is saved before it is clobbered. */
-	PUSH.L	R15
-
-	/* Read the user stack pointer. */
-	MVFC	USP, R15
-
-	/* Move the address down to the data being moved. */
-	SUB		#12, R15
-	MVTC	R15, USP
-
-	/* Copy the data across. */
-	MOV.L	[ R0 ], [ R15 ] ; R15
-	MOV.L 	4[ R0 ], 4[ R15 ]  ; PC
-	MOV.L	8[ R0 ], 8[ R15 ]  ; PSW
-
-	/* Move the interrupt stack pointer to its new correct position. */
-	ADD	#12, R0
-
-	/* All the rest of the registers are saved directly to the user stack. */
-	SETPSW	U
-
-	/* Save the rest of the general registers (R15 has been saved already). */
-	PUSHM	R1-R14
-
-	/* Save the FPSW and accumulator. */
-	MVFC	FPSW, R15
-	PUSH.L	R15
-	MVFACHI	R15
-	PUSH.L	R15
-	MVFACMI	R15	; Middle order word.
-	SHLL	#16, R15 ; Shifted left as it is restored to the low order word.
-	PUSH.L	R15
-
-	/* Save the stack pointer to the TCB. */
-	MOV.L	#_pxCurrentTCB, R15
-	MOV.L	[ R15 ], R15
-	MOV.L	R0, [ R15 ]
-
-	/* Ensure the interrupt mask is set to the syscall priority while the kernel
-	structures are being accessed. */
-	MVTIPL	#configMAX_SYSCALL_INTERRUPT_PRIORITY
-
-	/* Select the next task to run. */
-	BSR.A	_vTaskSwitchContext
-
-	/* Reset the interrupt mask as no more data structure access is required. */
-	MVTIPL	#configKERNEL_INTERRUPT_PRIORITY
-
-	/* Load the stack pointer of the task that is now selected as the Running
-	state task from its TCB. */
-	MOV.L	#_pxCurrentTCB,R15
-	MOV.L	[ R15 ], R15
-	MOV.L	[ R15 ], R0
-
-	/* Restore the context of the new task.  The PSW (Program Status Word) and
-	PC will be popped by the RTE instruction. */
-	POP		R15
-	MVTACLO	R15
-	POP		R15
-	MVTACHI	R15
-	POP		R15
-	MVTC	R15,FPSW
-	POPM	R1-R15
-	RTE
-	NOP
-	NOP
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( pxCurrentTCB == NULL );
-
-	/* The following line is just to prevent the symbol getting optimised away. */
-	( void ) vTaskSwitchContext();
-}
-/*-----------------------------------------------------------*/
-
-
-
diff --git a/FreeRTOS/Source/portable/Renesas/RX600/port_asm.src b/FreeRTOS/Source/portable/Renesas/RX600/port_asm.src
deleted file mode 100755
index badce8b..0000000
--- a/FreeRTOS/Source/portable/Renesas/RX600/port_asm.src
+++ /dev/null
@@ -1,41 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-		.GLB	_vSoftwareInterruptISR
-                .GLB    _vSoftwareInterruptEntry
-
-		.SECTION   P,CODE
-
-_vSoftwareInterruptEntry:
-
-	BRA	_vSoftwareInterruptISR
-
-		.RVECTOR	27, _vSoftwareInterruptEntry
-
-		.END
-
-
-
diff --git a/FreeRTOS/Source/portable/Renesas/RX600/portmacro.h b/FreeRTOS/Source/portable/Renesas/RX600/portmacro.h
deleted file mode 100755
index f678450..0000000
--- a/FreeRTOS/Source/portable/Renesas/RX600/portmacro.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Hardware specifics. */
-#include "machine.h"
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT				8	/* Could make four, according to manual. */
-#define portSTACK_GROWTH				-1
-#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()						nop()
-
-
-#pragma inline_asm vPortYield
-static void vPortYield( void )
-{
-	/* Save clobbered register - may not actually be necessary if inline asm
-	functions are considered to use the same rules as function calls by the
-	compiler. */
-	PUSH.L R5
-	/* Set ITU SWINTR. */
-	MOV.L #553696, R5
-	MOV.B #1, [R5]
-	/* Read back to ensure the value is taken before proceeding. */
-	MOV.L [R5], R5
-	/* Restore clobbered register to its previous value. */
-	POP R5
-}
-#define portYIELD()	vPortYield()
-#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() 	set_ipl( ( long ) 0 )
-#ifdef configASSERT
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-	#define portDISABLE_INTERRUPTS() 	if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#else
-	#define portDISABLE_INTERRUPTS() 	set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()	vTaskEnterCritical()
-#define portEXIT_CRITICAL()		vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/Renesas/RX600v2/port.c b/FreeRTOS/Source/portable/Renesas/RX600v2/port.c
deleted file mode 100755
index 3f47412..0000000
--- a/FreeRTOS/Source/portable/Renesas/RX600v2/port.c
+++ /dev/null
@@ -1,364 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the RX600 port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/* Hardware specifics. */
-#if defined( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H ) && ( configINCLUDE_PLATFORM_H_INSTEAD_OF_IODEFINE_H == 1 )
-	#include "platform.h"
-#else
-	#include "iodefine.h"
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Tasks should start with interrupts enabled and in Supervisor mode, therefore
-PSW is set with U and I set, and PM and IPL clear. */
-#define portINITIAL_PSW     ( ( StackType_t ) 0x00030000 )
-#define portINITIAL_FPSW    ( ( StackType_t ) 0x00000100 )
-
-/*-----------------------------------------------------------*/
-
-/* The following lines are to ensure vSoftwareInterruptEntry can be referenced,
- and therefore installed in the vector table, when the FreeRTOS code is built
-as a library. */
-extern BaseType_t vSoftwareInterruptEntry;
-const BaseType_t * p_vSoftwareInterruptEntry = &vSoftwareInterruptEntry;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Function to start the first task executing - written in asm code as direct
- * access to registers is required.
- */
-static void prvStartFirstTask( void );
-
-/*
- * Software interrupt handler.  Performs the actual context switch (saving and
- * restoring of registers).  Written in asm code as direct register access is
- * required.
- */
-static void prvYieldHandler( void );
-
-/*
- * The entry point for the software interrupt handler.  This is the function
- * that calls the inline asm function prvYieldHandler().  It is installed in
- * the vector table, but the code that installs it is in prvYieldHandler rather
- * than using a #pragma.
- */
-void vSoftwareInterruptISR( void );
-
-/*-----------------------------------------------------------*/
-
-/* This is accessed by the inline assembler functions so is file scope for
-convenience. */
-extern void *pxCurrentTCB;
-extern void vTaskSwitchContext( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* R0 is not included as it is the stack pointer. */
-
-	*pxTopOfStack = 0x00;
-	pxTopOfStack--;
- 	*pxTopOfStack = portINITIAL_PSW;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pxCode;
-
-	/* When debugging it can be useful if every register is set to a known
-	value.  Otherwise code space can be saved by just setting the registers
-	that need to be set. */
-	#ifdef USE_FULL_REGISTER_INITIALISATION
-	{
-		pxTopOfStack--;
-		*pxTopOfStack = 0xffffffff;	/* r15. */
-		pxTopOfStack--;
-		*pxTopOfStack = 0xeeeeeeee;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xdddddddd;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xcccccccc;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xbbbbbbbb;
-		pxTopOfStack--;
-		*pxTopOfStack = 0xaaaaaaaa;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x99999999;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x88888888;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x77777777;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x66666666;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x55555555;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x44444444;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x33333333;
-		pxTopOfStack--;
-		*pxTopOfStack = 0x22222222;
-		pxTopOfStack--;
-	}
-	#else
-	{
-		pxTopOfStack -= 15;
-	}
-	#endif
-
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_FPSW;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x11111111; /* Accumulator 0. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x22222222; /* Accumulator 0. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x33333333; /* Accumulator 0. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x44444444; /* Accumulator 1. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x55555555; /* Accumulator 1. */
-	pxTopOfStack--;
-	*pxTopOfStack = 0x66666666; /* Accumulator 1. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vApplicationSetupTimerInterrupt( void );
-
-	/* Use pxCurrentTCB just so it does not get optimised away. */
-	if( pxCurrentTCB != NULL )
-	{
-		/* Call an application function to set up the timer that will generate the
-		tick interrupt.  This way the application can decide which peripheral to
-		use.  A demo application is provided to show a suitable example. */
-		vApplicationSetupTimerInterrupt();
-
-		/* Enable the software interrupt. */
-		_IEN( _ICU_SWINT ) = 1;
-
-		/* Ensure the software interrupt is clear. */
-		_IR( _ICU_SWINT ) = 0;
-
-		/* Ensure the software interrupt is set to the kernel priority. */
-		_IPR( _ICU_SWINT ) = configKERNEL_INTERRUPT_PRIORITY;
-
-		/* Start the first task. */
-		prvStartFirstTask();
-	}
-
-	/* Just to make sure the function is not optimised away. */
-	( void ) vSoftwareInterruptISR();
-
-	/* Should not get here. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-#pragma inline_asm prvStartFirstTask
-static void prvStartFirstTask( void )
-{
-	/* When starting the scheduler there is nothing that needs moving to the
-	interrupt stack because the function is not called from an interrupt.
-	Just ensure the current stack is the user stack. */
-	SETPSW	U
-
-	/* Obtain the location of the stack associated with which ever task
-	pxCurrentTCB is currently pointing to. */
-	MOV.L	#_pxCurrentTCB, R15
-	MOV.L	[R15], R15
-	MOV.L	[R15], R0
-
-	/* Restore the registers from the stack of the task pointed to by
-	pxCurrentTCB. */
-    POP		R15
-    MVTACLO	R15, A0		/* Accumulator low 32 bits. */
-    POP		R15
-    MVTACHI	R15, A0		/* Accumulator high 32 bits. */
-    POP		R15
-    MVTACGU	R15, A0		/* Accumulator guard. */
-    POP		R15
-    MVTACLO	R15, A1		/* Accumulator low 32 bits. */
-    POP		R15
-    MVTACHI	R15, A1		/* Accumulator high 32 bits. */
-    POP		R15
-    MVTACGU	R15, A1		/* Accumulator guard. */
-    POP		R15
-    MVTC	R15,FPSW 	/* Floating point status word. */
-    POPM	R1-R15 		/* R1 to R15 - R0 is not included as it is the SP. */
-    RTE					/* This pops the remaining registers. */
-    NOP
-    NOP
-}
-/*-----------------------------------------------------------*/
-
-#pragma interrupt ( vTickISR( vect = _VECT( configTICK_VECTOR ), enable ) )
-void vTickISR( void )
-{
-	/* Increment the tick, and perform any processing the new tick value
-	necessitates. */
-	set_ipl( configMAX_SYSCALL_INTERRUPT_PRIORITY );
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			taskYIELD();
-		}
-	}
-	set_ipl( configKERNEL_INTERRUPT_PRIORITY );
-}
-/*-----------------------------------------------------------*/
-
-void vSoftwareInterruptISR( void )
-{
-	prvYieldHandler();
-}
-/*-----------------------------------------------------------*/
-
-#pragma inline_asm prvYieldHandler
-static void prvYieldHandler( void )
-{
-	/* Re-enable interrupts. */
-	SETPSW	I
-
-	/* Move the data that was automatically pushed onto the interrupt stack when
-	the interrupt occurred from the interrupt stack to the user stack.
-
-	R15 is saved before it is clobbered. */
-	PUSH.L	R15
-
-	/* Read the user stack pointer. */
-	MVFC	USP, R15
-
-	/* Move the address down to the data being moved. */
-	SUB		#12, R15
-	MVTC	R15, USP
-
-	/* Copy the data across. */
-	MOV.L	[ R0 ], [ R15 ] ; R15
-	MOV.L 	4[ R0 ], 4[ R15 ]  ; PC
-	MOV.L	8[ R0 ], 8[ R15 ]  ; PSW
-
-	/* Move the interrupt stack pointer to its new correct position. */
-	ADD	#12, R0
-
-	/* All the rest of the registers are saved directly to the user stack. */
-	SETPSW	U
-
-	/* Save the rest of the general registers (R15 has been saved already). */
-	PUSHM	R1-R14
-
-	/* Save the FPSW and accumulators. */
-	MVFC	FPSW, R15
-	PUSH.L	R15
-	MVFACGU	#0, A1, R15
-	PUSH.L	R15
-	MVFACHI	#0, A1, R15
-	PUSH.L	R15
-	MVFACLO	#0, A1, R15	; Low order word.
-	PUSH.L	R15
-	MVFACGU	#0, A0, R15
-	PUSH.L	R15
-	MVFACHI	#0, A0, R15
-	PUSH.L	R15
-	MVFACLO	#0, A0, R15	; Low order word.
-	PUSH.L	R15
-
-	/* Save the stack pointer to the TCB. */
-	MOV.L	#_pxCurrentTCB, R15
-	MOV.L	[ R15 ], R15
-	MOV.L	R0, [ R15 ]
-
-	/* Ensure the interrupt mask is set to the syscall priority while the kernel
-	structures are being accessed. */
-	MVTIPL	#configMAX_SYSCALL_INTERRUPT_PRIORITY
-
-	/* Select the next task to run. */
-	BSR.A	_vTaskSwitchContext
-
-	/* Reset the interrupt mask as no more data structure access is required. */
-	MVTIPL	#configKERNEL_INTERRUPT_PRIORITY
-
-	/* Load the stack pointer of the task that is now selected as the Running
-	state task from its TCB. */
-	MOV.L	#_pxCurrentTCB,R15
-	MOV.L	[ R15 ], R15
-	MOV.L	[ R15 ], R0
-
-	/* Restore the context of the new task.  The PSW (Program Status Word) and
-	PC will be popped by the RTE instruction. */
-    POP		R15
-    MVTACLO	R15, A0		/* Accumulator low 32 bits. */
-    POP		R15
-    MVTACHI	R15, A0		/* Accumulator high 32 bits. */
-    POP		R15
-    MVTACGU	R15, A0		/* Accumulator guard. */
-    POP		R15
-    MVTACLO	R15, A1		/* Accumulator low 32 bits. */
-    POP		R15
-    MVTACHI	R15, A1		/* Accumulator high 32 bits. */
-    POP		R15
-    MVTACGU	R15, A1		/* Accumulator guard. */
-	POP		R15
-	MVTC	R15,FPSW
-	POPM	R1-R15
-	RTE
-	NOP
-	NOP
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( pxCurrentTCB == NULL );
-
-	/* The following line is just to prevent the symbol getting optimised away. */
-	( void ) vTaskSwitchContext();
-}
-/*-----------------------------------------------------------*/
-
-
-
diff --git a/FreeRTOS/Source/portable/Renesas/RX600v2/port_asm.src b/FreeRTOS/Source/portable/Renesas/RX600v2/port_asm.src
deleted file mode 100755
index 818b7b8..0000000
--- a/FreeRTOS/Source/portable/Renesas/RX600v2/port_asm.src
+++ /dev/null
@@ -1,41 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-		.GLB	_vSoftwareInterruptISR
-		.GLB    _vSoftwareInterruptEntry
-
-		.SECTION   P,CODE
-
-_vSoftwareInterruptEntry:
-
-	BRA	_vSoftwareInterruptISR
-
-		.RVECTOR	27, _vSoftwareInterruptEntry
-
-		.END
-
-
-
diff --git a/FreeRTOS/Source/portable/Renesas/RX600v2/portmacro.h b/FreeRTOS/Source/portable/Renesas/RX600v2/portmacro.h
deleted file mode 100755
index 76c7921..0000000
--- a/FreeRTOS/Source/portable/Renesas/RX600v2/portmacro.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Hardware specifics. */
-#include "machine.h"
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT				8	/* Could make four, according to manual. */
-#define portSTACK_GROWTH				-1
-#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()						nop()
-
-
-#pragma inline_asm vPortYield
-static void vPortYield( void )
-{
-	/* Save clobbered register - may not actually be necessary if inline asm
-	functions are considered to use the same rules as function calls by the
-	compiler. */
-	PUSH.L R5
-	/* Set ITU SWINTR. */
-	MOV.L #553696, R5
-	MOV.B #1, [R5]
-	/* Read back to ensure the value is taken before proceeding. */
-	MOV.L [R5], R5
-	/* Restore clobbered register to its previous value. */
-	POP R5
-}
-#define portYIELD()	vPortYield()
-#define portYIELD_FROM_ISR( x )	if( x != pdFALSE ) portYIELD()
-
-/* These macros should not be called directly, but through the
-taskENTER_CRITICAL() and taskEXIT_CRITICAL() macros.  An extra check is
-performed if configASSERT() is defined to ensure an assertion handler does not
-inadvertently attempt to lower the IPL when the call to assert was triggered
-because the IPL value was found to be above	configMAX_SYSCALL_INTERRUPT_PRIORITY
-when an ISR safe FreeRTOS API function was executed.  ISR safe FreeRTOS API
-functions are those that end in FromISR.  FreeRTOS maintains a separate
-interrupt API to ensure API function and interrupt entry is as fast and as
-simple as possible. */
-#define portENABLE_INTERRUPTS() 	set_ipl( ( long ) 0 )
-#ifdef configASSERT
-	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() configASSERT( ( get_ipl() <= configMAX_SYSCALL_INTERRUPT_PRIORITY ) )
-	#define portDISABLE_INTERRUPTS() 	if( get_ipl() < configMAX_SYSCALL_INTERRUPT_PRIORITY ) set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#else
-	#define portDISABLE_INTERRUPTS() 	set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#endif
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()	vTaskEnterCritical()
-#define portEXIT_CRITICAL()		vTaskExitCritical()
-
-/* As this port allows interrupt nesting... */
-#define portSET_INTERRUPT_MASK_FROM_ISR() ( UBaseType_t ) get_ipl(); set_ipl( ( long ) configMAX_SYSCALL_INTERRUPT_PRIORITY )
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus ) set_ipl( ( long ) uxSavedInterruptStatus )
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/Renesas/SH2A_FPU/ISR_Support.inc b/FreeRTOS/Source/portable/Renesas/SH2A_FPU/ISR_Support.inc
deleted file mode 100755
index c4fcd3f..0000000
--- a/FreeRTOS/Source/portable/Renesas/SH2A_FPU/ISR_Support.inc
+++ /dev/null
@@ -1,74 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-	.macro portSAVE_CONTEXT
-
-	; Save r0 to r14 and pr.
-	movml.l r15, @-r15
-
-	; Save mac1, mach and gbr
-	sts.l	macl, @-r15
-	sts.l	mach, @-r15
-	stc.l	gbr, @-r15
-
-	; Get the address of pxCurrentTCB
-	mov.l	#_pxCurrentTCB, r0
-
-	; Get the address of pxTopOfStack from the TCB.
-	mov.l	@r0, r0
-
-	; Save the stack pointer in pxTopOfStack.
-	mov.l	r15, @r0
-
-	.endm
-
-;-----------------------------------------------------------
-
-	.macro portRESTORE_CONTEXT
-
-	; Get the address of the pxCurrentTCB variable.
-	mov.l	#_pxCurrentTCB, r0
-
-	; Get the address of the task stack from pxCurrentTCB.
-	mov.l	@r0, r0
-
-	; Get the task stack itself into the stack pointer.
-	mov.l	@r0, r15
-
-	; Restore system registers.
-	ldc.l	@r15+, gbr
-	lds.l	@r15+, mach
-	lds.l	@r15+, macl
-
-	; Restore r0 to r14 and PR
-	movml.l	@r15+, r15
-
-	; Pop the SR and PC to jump to the start of the task.
-	rte
-	nop
-
-	.endm
-;-----------------------------------------------------------
\ No newline at end of file
diff --git a/FreeRTOS/Source/portable/Renesas/SH2A_FPU/port.c b/FreeRTOS/Source/portable/Renesas/SH2A_FPU/port.c
deleted file mode 100755
index e2e78bd..0000000
--- a/FreeRTOS/Source/portable/Renesas/SH2A_FPU/port.c
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the SH2A port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Library includes. */
-#include "string.h"
-
-/*-----------------------------------------------------------*/
-
-/* The SR assigned to a newly created task.  The only important thing in this
-value is for all interrupts to be enabled. */
-#define portINITIAL_SR				( 0UL )
-
-/* Dimensions the array into which the floating point context is saved.
-Allocate enough space for FPR0 to FPR15, FPUL and FPSCR, each of which is 4
-bytes big.  If this number is changed then the 72 in portasm.src also needs
-changing. */
-#define portFLOP_REGISTERS_TO_STORE	( 18 )
-#define portFLOP_STORAGE_SIZE 		( portFLOP_REGISTERS_TO_STORE * 4 )
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 0 )
-	#error configSUPPORT_DYNAMIC_ALLOCATION must be 1 to use this port.
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * The TRAPA handler used to force a context switch.
- */
-void vPortYield( void );
-
-/*
- * Function to start the first task executing - defined in portasm.src.
- */
-extern void vPortStartFirstTask( void );
-
-/*
- * Obtains the current GBR value - defined in portasm.src.
- */
-extern uint32_t ulPortGetGBR( void );
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Mark the end of the stack - used for debugging only and can be removed. */
-	*pxTopOfStack = 0x11111111UL;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x22222222UL;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x33333333UL;
-	pxTopOfStack--;
-
-	/* SR. */
-	*pxTopOfStack = portINITIAL_SR;
-	pxTopOfStack--;
-
-	/* PC. */
-	*pxTopOfStack = ( uint32_t ) pxCode;
-	pxTopOfStack--;
-
-	/* PR. */
-	*pxTopOfStack = 15;
-	pxTopOfStack--;
-
-	/* 14. */
-	*pxTopOfStack = 14;
-	pxTopOfStack--;
-
-	/* R13. */
-	*pxTopOfStack = 13;
-	pxTopOfStack--;
-
-	/* R12. */
-	*pxTopOfStack = 12;
-	pxTopOfStack--;
-
-	/* R11. */
-	*pxTopOfStack = 11;
-	pxTopOfStack--;
-
-	/* R10. */
-	*pxTopOfStack = 10;
-	pxTopOfStack--;
-
-	/* R9. */
-	*pxTopOfStack = 9;
-	pxTopOfStack--;
-
-	/* R8. */
-	*pxTopOfStack = 8;
-	pxTopOfStack--;
-
-	/* R7. */
-	*pxTopOfStack = 7;
-	pxTopOfStack--;
-
-	/* R6. */
-	*pxTopOfStack = 6;
-	pxTopOfStack--;
-
-	/* R5. */
-	*pxTopOfStack = 5;
-	pxTopOfStack--;
-
-	/* R4. */
-	*pxTopOfStack = ( uint32_t ) pvParameters;
-	pxTopOfStack--;
-
-	/* R3. */
-	*pxTopOfStack = 3;
-	pxTopOfStack--;
-
-	/* R2. */
-	*pxTopOfStack = 2;
-	pxTopOfStack--;
-
-	/* R1. */
-	*pxTopOfStack = 1;
-	pxTopOfStack--;
-
-	/* R0 */
-	*pxTopOfStack = 0;
-	pxTopOfStack--;
-
-	/* MACL. */
-	*pxTopOfStack = 16;
-	pxTopOfStack--;
-
-	/* MACH. */
-	*pxTopOfStack = 17;
-	pxTopOfStack--;
-
-	/* GBR. */
-	*pxTopOfStack = ulPortGetGBR();
-
-	/* GBR = global base register.
-	   VBR = vector base register.
-	   TBR = jump table base register.
-	   R15 is the stack pointer. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-extern void vApplicationSetupTimerInterrupt( void );
-
-	/* Call an application function to set up the timer that will generate the
-	tick interrupt.  This way the application can decide which peripheral to
-	use.  A demo application is provided to show a suitable example. */
-	vApplicationSetupTimerInterrupt();
-
-	/* Start the first task.  This will only restore the standard registers and
-	not the flop registers.  This does not really matter though because the only
-	flop register that is initialised to a particular value is fpscr, and it is
-	only initialised to the current value, which will still be the current value
-	when the first task starts executing. */
-	trapa( portSTART_SCHEDULER_TRAP_NO );
-
-	/* Should not get here. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented as there is nothing to return to. */
-}
-/*-----------------------------------------------------------*/
-
-void vPortYield( void )
-{
-int32_t lInterruptMask;
-
-	/* Ensure the yield trap runs at the same priority as the other interrupts
-	that can cause a context switch. */
-	lInterruptMask = get_imask();
-
-	/* taskYIELD() can only be called from a task, not an interrupt, so the
-	current interrupt mask can only be 0 or portKERNEL_INTERRUPT_PRIORITY and
-	the mask can be set without risk of accidentally lowering the mask value. */
-	set_imask( portKERNEL_INTERRUPT_PRIORITY );
-
-	trapa( portYIELD_TRAP_NO );
-
-	/* Restore the interrupt mask to whatever it was previously (when the
-	function was entered). */
-	set_imask( ( int ) lInterruptMask );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortUsesFloatingPoint( TaskHandle_t xTask )
-{
-uint32_t *pulFlopBuffer;
-BaseType_t xReturn;
-extern void * volatile pxCurrentTCB;
-
-	/* This function tells the kernel that the task referenced by xTask is
-	going to use the floating point registers and therefore requires the
-	floating point registers saved as part of its context. */
-
-	/* Passing NULL as xTask is used to indicate that the calling task is the
-	subject task - so pxCurrentTCB is the task handle. */
-	if( xTask == NULL )
-	{
-		xTask = ( TaskHandle_t ) pxCurrentTCB;
-	}
-
-	/* Allocate a buffer large enough to hold all the flop registers. */
-	pulFlopBuffer = ( uint32_t * ) pvPortMalloc( portFLOP_STORAGE_SIZE );
-
-	if( pulFlopBuffer != NULL )
-	{
-		/* Start with the registers in a benign state. */
-		memset( ( void * ) pulFlopBuffer, 0x00, portFLOP_STORAGE_SIZE );
-
-		/* The first thing to get saved in the buffer is the FPSCR value -
-		initialise this to the current FPSCR value. */
-		*pulFlopBuffer = get_fpscr();
-
-		/* Use the task tag to point to the flop buffer.  Pass pointer to just
-		above the buffer because the flop save routine uses a pre-decrement. */
-		vTaskSetApplicationTaskTag( xTask, ( void * ) ( pulFlopBuffer + portFLOP_REGISTERS_TO_STORE ) );
-		xReturn = pdPASS;
-	}
-	else
-	{
-		xReturn = pdFAIL;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-
diff --git a/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portasm.src b/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portasm.src
deleted file mode 100755
index d265852..0000000
--- a/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portasm.src
+++ /dev/null
@@ -1,150 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-	.import _pxCurrentTCB
-	.import _vTaskSwitchContext
-	.import _xTaskIncrementTick
-
-	.export _vPortStartFirstTask
-	.export _ulPortGetGBR
-	.export _vPortYieldHandler
-	.export _vPortPreemptiveTick
-	.export _vPortCooperativeTick
-	.export _vPortSaveFlopRegisters
-	.export _vPortRestoreFlopRegisters
-
-    .section    P
-
-	.INCLUDE "ISR_Support.inc"
-
-_vPortStartFirstTask:
-
-	portRESTORE_CONTEXT
-
-;-----------------------------------------------------------
-
-_vPortYieldHandler:
-
-	portSAVE_CONTEXT
-
-	mov.l	#_vTaskSwitchContext, r0
-	jsr		@r0
-	nop
-
-	portRESTORE_CONTEXT
-
-;-----------------------------------------------------------
-
-_vPortPreemptiveTick
-
-	portSAVE_CONTEXT
-
-	mov.l	#_xTaskIncrementTick, r0
-	jsr		@r0
-	nop
-
-	mov.l	#_vTaskSwitchContext, r0
-	jsr		@r0
-	nop
-
-	portRESTORE_CONTEXT
-
-;-----------------------------------------------------------
-
-_vPortCooperativeTick
-
-	portSAVE_CONTEXT
-
-	mov.l	#_xTaskIncrementTick, r0
-	jsr		@r0
-	nop
-
-	portRESTORE_CONTEXT
-
-;-----------------------------------------------------------
-
-_ulPortGetGBR:
-
-	stc.l	gbr, r0
-	rts
-	nop
-
-;-----------------------------------------------------------
-
-_vPortSaveFlopRegisters:
-
-	fmov.s	fr0, @-r4
-	fmov.s	fr1, @-r4
-	fmov.s	fr2, @-r4
-	fmov.s	fr3, @-r4
-	fmov.s	fr4, @-r4
-	fmov.s	fr5, @-r4
-	fmov.s	fr6, @-r4
-	fmov.s	fr7, @-r4
-	fmov.s	fr8, @-r4
-	fmov.s	fr9, @-r4
-	fmov.s	fr10, @-r4
-	fmov.s	fr11, @-r4
-	fmov.s	fr12, @-r4
-	fmov.s	fr13, @-r4
-	fmov.s	fr14, @-r4
-	fmov.s	fr15, @-r4
-	sts.l   fpul, @-r4
-	sts.l   fpscr, @-r4
-
-	rts
-	nop
-
-;-----------------------------------------------------------
-
-_vPortRestoreFlopRegisters:
-
-	add.l  #-72, r4
-	lds.l  @r4+, fpscr
-	lds.l  @r4+, fpul
-	fmov.s @r4+, fr15
-	fmov.s @r4+, fr14
-	fmov.s @r4+, fr13
-	fmov.s @r4+, fr12
-	fmov.s @r4+, fr11
-	fmov.s @r4+, fr10
-	fmov.s @r4+, fr9
-	fmov.s @r4+, fr8
-	fmov.s @r4+, fr7
-	fmov.s @r4+, fr6
-	fmov.s @r4+, fr5
-	fmov.s @r4+, fr4
-	fmov.s @r4+, fr3
-	fmov.s @r4+, fr2
-	fmov.s @r4+, fr1
-	fmov.s @r4+, fr0
-
-	rts
-	nop
-
-	.end
-
diff --git a/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portmacro.h b/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portmacro.h
deleted file mode 100755
index 328c67a..0000000
--- a/FreeRTOS/Source/portable/Renesas/SH2A_FPU/portmacro.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions - these are a bit legacy and not really used now, other than
-portSTACK_TYPE and portBASE_TYPE. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT				8
-#define portSTACK_GROWTH				-1
-#define portTICK_PERIOD_MS				( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()						nop()
-#define portSTART_SCHEDULER_TRAP_NO		( 32 )
-#define portYIELD_TRAP_NO				( 33 )
-#define portKERNEL_INTERRUPT_PRIORITY	( 1 )
-
-void vPortYield( void );
-#define portYIELD()						vPortYield()
-
-extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR( x )			if( x != pdFALSE ) vTaskSwitchContext()
-
-/*
- * This function tells the kernel that the task referenced by xTask is going to
- * use the floating point registers and therefore requires the floating point
- * registers saved as part of its context.
- */
-BaseType_t xPortUsesFloatingPoint( void* xTask );
-
-/*
- * The flop save and restore functions are defined in portasm.src and called by
- * the trace "task switched in" and "trace task switched out" macros.
- */
-void vPortSaveFlopRegisters( void *pulBuffer );
-void vPortRestoreFlopRegisters( void *pulBuffer );
-
-/*
- * pxTaskTag is used to point to the buffer into which the floating point
- * context should be saved.  If pxTaskTag is NULL then the task does not use
- * a floating point context.
- */
-#define traceTASK_SWITCHED_OUT() if( pxCurrentTCB->pxTaskTag != NULL ) vPortSaveFlopRegisters( pxCurrentTCB->pxTaskTag )
-#define traceTASK_SWITCHED_IN() if( pxCurrentTCB->pxTaskTag != NULL ) vPortRestoreFlopRegisters( pxCurrentTCB->pxTaskTag )
-
-/*
- * These macros should be called directly, but through the taskENTER_CRITICAL()
- * and taskEXIT_CRITICAL() macros.
- */
-#define portENABLE_INTERRUPTS() 	set_imask( 0x00 )
-#define portDISABLE_INTERRUPTS() 	set_imask( portKERNEL_INTERRUPT_PRIORITY )
-
-/* Critical nesting counts are stored in the TCB. */
-#define portCRITICAL_NESTING_IN_TCB ( 1 )
-
-/* The critical nesting functions defined within tasks.c. */
-extern void vTaskEnterCritical( void );
-extern void vTaskExitCritical( void );
-#define portENTER_CRITICAL()	vTaskEnterCritical();
-#define portEXIT_CRITICAL()		vTaskExitCritical();
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/Rowley/ARM7/readme.txt b/FreeRTOS/Source/portable/Rowley/ARM7/readme.txt
deleted file mode 100755
index 8d3e87f..0000000
--- a/FreeRTOS/Source/portable/Rowley/ARM7/readme.txt
+++ /dev/null
@@ -1 +0,0 @@
-The Rowley ARM7 demo uses the GCC ARM7 port files.
\ No newline at end of file
diff --git a/FreeRTOS/Source/portable/Rowley/MSP430F449/port.c b/FreeRTOS/Source/portable/Rowley/MSP430F449/port.c
deleted file mode 100755
index ea01e47..0000000
--- a/FreeRTOS/Source/portable/Rowley/MSP430F449/port.c
+++ /dev/null
@@ -1,172 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the MSP430 port.
- *----------------------------------------------------------*/
-
-/* Constants required for hardware setup.  The tick ISR runs off the ACLK, 
-not the MCLK. */
-#define portACLK_FREQUENCY_HZ			( ( TickType_t ) 32768 )
-#define portINITIAL_CRITICAL_NESTING	( ( uint16_t ) 10 )
-#define portFLAGS_INT_ENABLED			( ( StackType_t ) 0x08 )
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/* Each task maintains a count of the critical section nesting depth.  Each 
-time a critical section is entered the count is incremented.  Each time a 
-critical section is exited the count is decremented - with interrupts only 
-being re-enabled if the count is zero.
-
-usCriticalNesting will get set to zero when the scheduler starts, but must
-not be initialised to zero as this will cause problems during the startup
-sequence. */
-volatile uint16_t usCriticalNesting = portINITIAL_CRITICAL_NESTING;
-/*-----------------------------------------------------------*/
-
-
-/*
- * Sets up the periodic ISR used for the RTOS tick.  This uses timer 0, but
- * could have alternatively used the watchdog timer or timer 1.
- */
-void prvSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-/* 
- * Initialise the stack of a task to look exactly as if a call to 
- * portSAVE_CONTEXT had been called.
- * 
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* 
-		Place a few bytes of known values on the bottom of the stack. 
-		This is just useful for debugging and can be included if required.
-
-		*pxTopOfStack = ( StackType_t ) 0x1111;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x2222;
-		pxTopOfStack--;
-		*pxTopOfStack = ( StackType_t ) 0x3333;
-		pxTopOfStack--; 
-	*/
-
-	/* The msp430 automatically pushes the PC then SR onto the stack before 
-	executing an ISR.  We want the stack to look just as if this has happened
-	so place a pointer to the start of the task on the stack first - followed
-	by the flags we want the task to use when it starts up. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-	*pxTopOfStack = portFLAGS_INT_ENABLED;
-	pxTopOfStack--;
-
-	/* Next the general purpose registers. */
-	*pxTopOfStack = ( StackType_t ) 0x4444;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x5555;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x6666;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x7777;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x8888;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x9999;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xaaaa;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xbbbb;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xcccc;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xdddd;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xeeee;
-	pxTopOfStack--;
-
-	/* When the task starts is will expect to find the function parameter in
-	R15. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;
-	pxTopOfStack--;
-
-	/* A variable is used to keep track of the critical section nesting.  
-	This variable has to be stored as part of the task context and is 
-	initially set to zero. */
-	*pxTopOfStack = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;	
-
-	/* Return a pointer to the top of the stack we have generated so this can
-	be stored in the task control block for the task. */
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the MSP430 port will get stopped.  If required simply
-	disable the tick interrupt here. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Hardware initialisation to generate the RTOS tick.  This uses timer 0
- * but could alternatively use the watchdog timer or timer 1. 
- */
-void prvSetupTimerInterrupt( void )
-{
-	/* Ensure the timer is stopped. */
-	TACTL = 0;
-
-	/* Run the timer of the ACLK. */
-	TACTL = TASSEL_1;
-
-	/* Clear everything to start with. */
-	TACTL |= TACLR;
-
-	/* Set the compare match value according to the tick rate we want. */
-	TACCR0 = portACLK_FREQUENCY_HZ / configTICK_RATE_HZ;
-
-	/* Enable the interrupts. */
-	TACCTL0 = CCIE;
-
-	/* Start up clean. */
-	TACTL |= TACLR;
-
-	/* Up mode. */
-	TACTL |= MC_1;
-}
-/*-----------------------------------------------------------*/
-
-
-	
diff --git a/FreeRTOS/Source/portable/Rowley/MSP430F449/portasm.h b/FreeRTOS/Source/portable/Rowley/MSP430F449/portasm.h
deleted file mode 100755
index fe55c65..0000000
--- a/FreeRTOS/Source/portable/Rowley/MSP430F449/portasm.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORT_ASM_H
-#define PORT_ASM_H
-
-portSAVE_CONTEXT macro
-                /* Save the remaining registers. */
-		push	r4
-		push	r5
-		push	r6
-		push	r7
-		push	r8
-		push	r9
-		push	r10
-		push	r11
-		push	r12
-		push	r13
-		push	r14
-		push	r15
-		mov.w	&_usCriticalNesting, r14
-		push	r14
-		mov.w	&_pxCurrentTCB, r12
-		mov.w	r1, @r12
-		endm
-/*-----------------------------------------------------------*/
-		
-portRESTORE_CONTEXT macro
-		mov.w	&_pxCurrentTCB, r12
-		mov.w	@r12, r1
-		pop		r15
-		mov.w	r15, &_usCriticalNesting
-		pop		r15
-		pop		r14
-		pop		r13
-		pop		r12
-		pop		r11
-		pop		r10
-		pop		r9
-		pop		r8
-		pop		r7
-		pop		r6
-		pop		r5
-		pop		r4
-
-		/* The last thing on the stack will be the status register.
-                Ensure the power down bits are clear ready for the next
-                time this power down register is popped from the stack. */
-		bic.w   #0xf0,0(SP)
-
-		reti
-		endm
-/*-----------------------------------------------------------*/
-
-#endif
-
diff --git a/FreeRTOS/Source/portable/Rowley/MSP430F449/portext.asm b/FreeRTOS/Source/portable/Rowley/MSP430F449/portext.asm
deleted file mode 100755
index 157754c..0000000
--- a/FreeRTOS/Source/portable/Rowley/MSP430F449/portext.asm
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include "FreeRTOSConfig.h"
-#include "portasm.h"
-
-
-.CODE
-
-/*
- * The RTOS tick ISR.
- *
- * If the cooperative scheduler is in use this simply increments the tick 
- * count.
- *
- * If the preemptive scheduler is in use a context switch can also occur.
- */
-_vTickISR:
-		portSAVE_CONTEXT
-				
-		call	#_xTaskIncrementTick
-		cmp.w   #0x00, r15
-                jeq     _SkipContextSwitch
-		call	#_vTaskSwitchContext
-_SkipContextSwitch:		
-		portRESTORE_CONTEXT
-/*-----------------------------------------------------------*/
-
-
-/*
- * Manual context switch called by the portYIELD() macro.
- */                
-_vPortYield::
-
-		/* Mimic an interrupt by pushing the SR. */
-		push	SR			
-
-		/* Now the SR is stacked we can disable interrupts. */
-		dint			
-				
-		/* Save the context of the current task. */
-		portSAVE_CONTEXT			
-
-		/* Switch to the highest priority task that is ready to run. */
-		call	#_vTaskSwitchContext		
-
-		/* Restore the context of the new task. */
-		portRESTORE_CONTEXT
-/*-----------------------------------------------------------*/
-
-
-/*
- * Start off the scheduler by initialising the RTOS tick timer, then restoring
- * the context of the first task.
- */
-_xPortStartScheduler::
-
-		/* Setup the hardware to generate the tick.  Interrupts are disabled 
-		when this function is called. */
-		call	#_prvSetupTimerInterrupt
-
-		/* Restore the context of the first task that is going to run. */
-		portRESTORE_CONTEXT
-/*-----------------------------------------------------------*/          
-      		
-
-		/* Place the tick ISR in the correct vector. */
-		.VECTORS
-		
-		.KEEP
-		
-		ORG		TIMERA0_VECTOR
-		DW		_vTickISR
-		
-
-
-		END
-		
diff --git a/FreeRTOS/Source/portable/Rowley/MSP430F449/portmacro.h b/FreeRTOS/Source/portable/Rowley/MSP430F449/portmacro.h
deleted file mode 100755
index df06497..0000000
--- a/FreeRTOS/Source/portable/Rowley/MSP430F449/portmacro.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		int
-#define portSTACK_TYPE	uint16_t
-#define portBASE_TYPE	short
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-
-/*-----------------------------------------------------------*/
-
-/* Interrupt control macros. */
-#define portDISABLE_INTERRUPTS()	_DINT(); _NOP()
-#define portENABLE_INTERRUPTS()		_EINT();
-/*-----------------------------------------------------------*/
-
-/* Critical section control macros. */
-#define portNO_CRITICAL_SECTION_NESTING		( ( uint16_t ) 0 )
-
-#define portENTER_CRITICAL()													\
-{																				\
-extern volatile uint16_t usCriticalNesting;							\
-																				\
-	portDISABLE_INTERRUPTS();													\
-																				\
-	/* Now interrupts are disabled usCriticalNesting can be accessed */			\
-	/* directly.  Increment ulCriticalNesting to keep a count of how many */	\
-	/* times portENTER_CRITICAL() has been called. */							\
-	usCriticalNesting++;														\
-}
-
-#define portEXIT_CRITICAL()														\
-{																				\
-extern volatile uint16_t usCriticalNesting;							\
-																				\
-	if( usCriticalNesting > portNO_CRITICAL_SECTION_NESTING )					\
-	{																			\
-		/* Decrement the nesting count as we are leaving a critical section. */	\
-		usCriticalNesting--;													\
-																				\
-		/* If the nesting level has reached zero then interrupts should be */	\
-		/* re-enabled. */														\
-		if( usCriticalNesting == portNO_CRITICAL_SECTION_NESTING )				\
-		{																		\
-			portENABLE_INTERRUPTS();											\
-		}																		\
-	}																			\
-}
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/*
- * Manual context switch called by portYIELD or taskYIELD.
- */
-extern void vPortYield( void );
-#define portYIELD() vPortYield()
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			2
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portNOP()
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters ) __toplevel
-
-#if configINTERRUPT_EXAMPLE_METHOD == 2
-
-extern void vTaskSwitchContext( void );
-#define portYIELD_FROM_ISR( x ) if( x ) vTaskSwitchContext()
-
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/SDCC/Cygnal/port.c b/FreeRTOS/Source/portable/SDCC/Cygnal/port.c
deleted file mode 100755
index 21445a0..0000000
--- a/FreeRTOS/Source/portable/SDCC/Cygnal/port.c
+++ /dev/null
@@ -1,424 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Cygnal port.
- *----------------------------------------------------------*/
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to setup timer 2 to produce the RTOS tick. */
-#define portCLOCK_DIVISOR				( ( uint32_t ) 12 )
-#define portMAX_TIMER_VALUE				( ( uint32_t ) 0xffff )
-#define portENABLE_TIMER				( ( uint8_t ) 0x04 )
-#define portTIMER_2_INTERRUPT_ENABLE	( ( uint8_t ) 0x20 )
-
-/* The value used in the IE register when a task first starts. */
-#define portGLOBAL_INTERRUPT_BIT	( ( StackType_t ) 0x80 )
-
-/* The value used in the PSW register when a task first starts. */
-#define portINITIAL_PSW				( ( StackType_t ) 0x00 )
-
-/* Macro to clear the timer 2 interrupt flag. */
-#define portCLEAR_INTERRUPT_FLAG()	TMR2CN &= ~0x80;
-
-/* Used during a context switch to store the size of the stack being copied
-to or from XRAM. */
-data static uint8_t ucStackBytes;
-
-/* Used during a context switch to point to the next byte in XRAM from/to which
-a RAM byte is to be copied. */
-xdata static StackType_t * data pxXRAMStack;
-
-/* Used during a context switch to point to the next byte in RAM from/to which
-an XRAM byte is to be copied. */
-data static StackType_t * data pxRAMStack;
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/*
- * Setup the hardware to generate an interrupt off timer 2 at the required 
- * frequency.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*-----------------------------------------------------------*/
-/*
- * Macro that copies the current stack from internal RAM to XRAM.  This is 
- * required as the 8051 only contains enough internal RAM for a single stack, 
- * but we have a stack for every task.
- */
-#define portCOPY_STACK_TO_XRAM()																\
-{																								\
-	/* pxCurrentTCB points to a TCB which itself points to the location into					\
-	which the first	stack byte should be copied.  Set pxXRAMStack to point						\
-	to the location into which the first stack byte is to be copied. */							\
-	pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB );		\
-																								\
-	/* Set pxRAMStack to point to the first byte to be coped from the stack. */					\
-	pxRAMStack = ( data StackType_t * data ) configSTACK_START;								\
-																								\
-	/* Calculate the size of the stack we are about to copy from the current					\
-	stack pointer value. */																		\
-	ucStackBytes = SP - ( configSTACK_START - 1 );												\
-																								\
-	/* Before starting to copy the stack, store the calculated stack size so					\
-	the stack can be restored when the task is resumed. */										\
-	*pxXRAMStack = ucStackBytes;																\
-																								\
-	/* Copy each stack byte in turn.  pxXRAMStack is incremented first as we					\
-	have already stored the stack size into XRAM. */											\
-	while( ucStackBytes )																		\
-	{																							\
-		pxXRAMStack++;																			\
-		*pxXRAMStack = *pxRAMStack;																\
-		pxRAMStack++;																			\
-		ucStackBytes--;																			\
-	}																							\
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Macro that copies the stack of the task being resumed from XRAM into 
- * internal RAM.
- */
-#define portCOPY_XRAM_TO_STACK()																\
-{																								\
-	/* Setup the pointers as per portCOPY_STACK_TO_XRAM(), but this time to						\
-	copy the data back out of XRAM and into the stack. */										\
-	pxXRAMStack = ( xdata StackType_t * ) *( ( xdata StackType_t ** ) pxCurrentTCB );		\
-	pxRAMStack = ( data StackType_t * data ) ( configSTACK_START - 1 );						\
-																								\
-	/* The first value stored in XRAM was the size of the stack - i.e. the						\
-	number of bytes we need to copy back. */													\
-	ucStackBytes = pxXRAMStack[ 0 ];															\
-																								\
-	/* Copy the required number of bytes back into the stack. */								\
-	do																							\
-	{																							\
-		pxXRAMStack++;																			\
-		pxRAMStack++;																			\
-		*pxRAMStack = *pxXRAMStack;																\
-		ucStackBytes--;																			\
-	} while( ucStackBytes );																	\
-																								\
-	/* Restore the stack pointer ready to use the restored stack. */							\
-	SP = ( uint8_t ) pxRAMStack;														\
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Macro to push the current execution context onto the stack, before the stack 
- * is moved to XRAM. 
- */
-#define portSAVE_CONTEXT()																		\
-{																								\
-	_asm																						\
-		/* Push ACC first, as when restoring the context it must be restored					\
-		last (it is used to set the IE register). */											\
-		push	ACC																				\
-		/* Store the IE register then disable interrupts. */									\
-		push	IE																				\
-		clr		_EA																				\
-		push	DPL																				\
-		push	DPH																				\
-		push	b																				\
-		push	ar2																				\
-		push	ar3																				\
-		push	ar4																				\
-		push	ar5																				\
-		push	ar6																				\
-		push	ar7																				\
-		push	ar0																				\
-		push	ar1																				\
-		push	PSW																				\
-	_endasm;																					\
-		PSW = 0;																				\
-	_asm																						\
-		push	_bp																				\
-	_endasm;																					\
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Macro that restores the execution context from the stack.  The execution 
- * context was saved into the stack before the stack was copied into XRAM.
- */
-#define portRESTORE_CONTEXT()																	\
-{																								\
-	_asm																						\
-		pop		_bp																				\
-		pop		PSW																				\
-		pop		ar1																				\
-		pop		ar0																				\
-		pop		ar7																				\
-		pop		ar6																				\
-		pop		ar5																				\
-		pop		ar4																				\
-		pop		ar3																				\
-		pop		ar2																				\
-		pop		b																				\
-		pop		DPH																				\
-		pop		DPL																				\
-		/* The next byte of the stack is the IE register.  Only the global						\
-		enable bit forms part of the task context.  Pop off the IE then set						\
-		the global enable bit to match that of the stored IE register. */						\
-		pop		ACC																				\
-		JB		ACC.7,0098$																		\
-		CLR		IE.7																			\
-		LJMP	0099$																			\
-	0098$:																						\
-		SETB	IE.7																			\
-	0099$:																						\
-		/* Finally pop off the ACC, which was the first register saved. */						\
-		pop		ACC																				\
-		reti																					\
-	_endasm;																					\
-}
-/*-----------------------------------------------------------*/
-
-/* 
- * See header file for description. 
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint32_t ulAddress;
-StackType_t *pxStartOfStack;
-
-	/* Leave space to write the size of the stack as the first byte. */
-	pxStartOfStack = pxTopOfStack;
-	pxTopOfStack++;
-
-	/* Place a few bytes of known values on the bottom of the stack. 
-	This is just useful for debugging and can be uncommented if required.
-	*pxTopOfStack = 0x11;
-	pxTopOfStack++;
-	*pxTopOfStack = 0x22;
-	pxTopOfStack++;
-	*pxTopOfStack = 0x33;
-	pxTopOfStack++;
-	*/
-
-	/* Simulate how the stack would look after a call to the scheduler tick 
-	ISR. 
-
-	The return address that would have been pushed by the MCU. */
-	ulAddress = ( uint32_t ) pxCode;
-	*pxTopOfStack = ( StackType_t ) ulAddress;
-	ulAddress >>= 8;
-	pxTopOfStack++;
-	*pxTopOfStack = ( StackType_t ) ( ulAddress );
-	pxTopOfStack++;
-
-	/* Next all the registers will have been pushed by portSAVE_CONTEXT(). */
-	*pxTopOfStack = 0xaa;	/* acc */
-	pxTopOfStack++;	
-
-	/* We want tasks to start with interrupts enabled. */
-	*pxTopOfStack = portGLOBAL_INTERRUPT_BIT;
-	pxTopOfStack++;
-
-	/* The function parameters will be passed in the DPTR and B register as
-	a three byte generic pointer is used. */
-	ulAddress = ( uint32_t ) pvParameters;
-	*pxTopOfStack = ( StackType_t ) ulAddress;	/* DPL */
-	ulAddress >>= 8;
-	*pxTopOfStack++;
-	*pxTopOfStack = ( StackType_t ) ulAddress;	/* DPH */
-	ulAddress >>= 8;
-	pxTopOfStack++;
-	*pxTopOfStack = ( StackType_t ) ulAddress;	/* b */
-	pxTopOfStack++;
-
-	/* The remaining registers are straight forward. */
-	*pxTopOfStack = 0x02;	/* R2 */
-	pxTopOfStack++;
-	*pxTopOfStack = 0x03;	/* R3 */
-	pxTopOfStack++;
-	*pxTopOfStack = 0x04;	/* R4 */
-	pxTopOfStack++;
-	*pxTopOfStack = 0x05;	/* R5 */
-	pxTopOfStack++;
-	*pxTopOfStack = 0x06;	/* R6 */
-	pxTopOfStack++;
-	*pxTopOfStack = 0x07;	/* R7 */
-	pxTopOfStack++;
-	*pxTopOfStack = 0x00;	/* R0 */
-	pxTopOfStack++;
-	*pxTopOfStack = 0x01;	/* R1 */
-	pxTopOfStack++;
-	*pxTopOfStack = 0x00;	/* PSW */
-	pxTopOfStack++;
-	*pxTopOfStack = 0xbb;	/* BP */
-
-	/* Dont increment the stack size here as we don't want to include
-	the stack size byte as part of the stack size count.
-
-	Finally we place the stack size at the beginning. */
-	*pxStartOfStack = ( StackType_t ) ( pxTopOfStack - pxStartOfStack );
-
-	/* Unlike most ports, we return the start of the stack as this is where the
-	size of the stack is stored. */
-	return pxStartOfStack;
-}
-/*-----------------------------------------------------------*/
-
-/* 
- * See header file for description. 
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* Setup timer 2 to generate the RTOS tick. */
-	prvSetupTimerInterrupt();	
-
-	/* Make sure we start with the expected SFR page.  This line should not
-	really be required. */
-	SFRPAGE = 0;
-
-	/* Copy the stack for the first task to execute from XRAM into the stack,
-	restore the task context from the new stack, then start running the task. */
-	portCOPY_XRAM_TO_STACK();
-	portRESTORE_CONTEXT();
-
-	/* Should never get here! */
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented for this port. */
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch.  The first thing we do is save the registers so we
- * can use a naked attribute.
- */
-void vPortYield( void ) _naked
-{
-	/* Save the execution context onto the stack, then copy the entire stack
-	to XRAM.  This is necessary as the internal RAM is only large enough to
-	hold one stack, and we want one per task. 
-	
-	PERFORMANCE COULD BE IMPROVED BY ONLY COPYING TO XRAM IF A TASK SWITCH
-	IS REQUIRED. */
-	portSAVE_CONTEXT();
-	portCOPY_STACK_TO_XRAM();
-
-	/* Call the standard scheduler context switch function. */
-	vTaskSwitchContext();
-
-	/* Copy the stack of the task about to execute from XRAM into RAM and
-	restore it's context ready to run on exiting. */
-	portCOPY_XRAM_TO_STACK();
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_PREEMPTION == 1
-	void vTimer2ISR( void ) interrupt 5 _naked
-	{
-		/* Preemptive context switch function triggered by the timer 2 ISR.
-		This does the same as vPortYield() (see above) with the addition
-		of incrementing the RTOS tick count. */
-
-		portSAVE_CONTEXT();
-		portCOPY_STACK_TO_XRAM();
-
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			vTaskSwitchContext();
-		}
-		
-		portCLEAR_INTERRUPT_FLAG();
-		portCOPY_XRAM_TO_STACK();
-		portRESTORE_CONTEXT();
-	}
-#else
-	void vTimer2ISR( void ) interrupt 5
-	{
-		/* When using the cooperative scheduler the timer 2 ISR is only 
-		required to increment the RTOS tick count. */
-
-		xTaskIncrementTick();
-		portCLEAR_INTERRUPT_FLAG();
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-uint8_t ucOriginalSFRPage;
-
-/* Constants calculated to give the required timer capture values. */
-const uint32_t ulTicksPerSecond = configCPU_CLOCK_HZ / portCLOCK_DIVISOR;
-const uint32_t ulCaptureTime = ulTicksPerSecond / configTICK_RATE_HZ;
-const uint32_t ulCaptureValue = portMAX_TIMER_VALUE - ulCaptureTime;
-const uint8_t ucLowCaptureByte = ( uint8_t ) ( ulCaptureValue & ( uint32_t ) 0xff );
-const uint8_t ucHighCaptureByte = ( uint8_t ) ( ulCaptureValue >> ( uint32_t ) 8 );
-
-	/* NOTE:  This uses a timer only present on 8052 architecture. */
-
-	/* Remember the current SFR page so we can restore it at the end of the
-	function. */
-	ucOriginalSFRPage = SFRPAGE;
-	SFRPAGE = 0;
-
-	/* TMR2CF can be left in its default state. */	
-	TMR2CF = ( uint8_t ) 0;
-
-	/* Setup the overflow reload value. */
-	RCAP2L = ucLowCaptureByte;
-	RCAP2H = ucHighCaptureByte;
-
-	/* The initial load is performed manually. */
-	TMR2L = ucLowCaptureByte;
-	TMR2H = ucHighCaptureByte;
-
-	/* Enable the timer 2 interrupts. */
-	IE |= portTIMER_2_INTERRUPT_ENABLE;
-
-	/* Interrupts are disabled when this is called so the timer can be started
-	here. */
-	TMR2CN = portENABLE_TIMER;
-
-	/* Restore the original SFR page. */
-	SFRPAGE = ucOriginalSFRPage;
-}
-
-
-
-
diff --git a/FreeRTOS/Source/portable/SDCC/Cygnal/portmacro.h b/FreeRTOS/Source/portable/SDCC/Cygnal/portmacro.h
deleted file mode 100755
index 1a3eafa..0000000
--- a/FreeRTOS/Source/portable/SDCC/Cygnal/portmacro.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#if configUSE_PREEMPTION == 0
-	void vTimer2ISR( void ) interrupt 5;
-#else
-	void vTimer2ISR( void ) interrupt 5 _naked;
-#endif
-
-void vSerialISR( void ) interrupt 4;
-
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		float
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint8_t
-#define portBASE_TYPE	char
-
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-#define portENTER_CRITICAL()		_asm		\
-									push	ACC	\
-									push	IE	\
-									_endasm;	\
-									EA = 0;
-
-#define portEXIT_CRITICAL()			_asm			\
-									pop		ACC		\
-									_endasm;		\
-									ACC &= 0x80;	\
-									IE |= ACC;		\
-									_asm			\
-									pop		ACC		\
-									_endasm;
-
-#define portDISABLE_INTERRUPTS()	EA = 0;
-#define portENABLE_INTERRUPTS()		EA = 1;
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portBYTE_ALIGNMENT			1
-#define portSTACK_GROWTH			( 1 )
-#define portTICK_PERIOD_MS			( ( uint32_t ) 1000 / configTICK_RATE_HZ )
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-void vPortYield( void ) _naked;
-#define portYIELD()	vPortYield();
-/*-----------------------------------------------------------*/
-
-#define portNOP()				_asm	\
-									nop \
-								_endasm;
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#endif /* PORTMACRO_H */
-
-
diff --git a/FreeRTOS/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c b/FreeRTOS/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c
deleted file mode 100755
index f00cb8f..0000000
--- a/FreeRTOS/Source/portable/Softune/MB91460/__STD_LIB_sbrk.c
+++ /dev/null
@@ -1,23 +0,0 @@
-#include "FreeRTOSConfig.h"
-#include 
-
-	static  long         brk_siz  =  0;
-//	#if  configTOTAL_HEAP_SIZE != 0
-	typedef int          _heep_t;
-	#define ROUNDUP(s)   (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1))
-	static  _heep_t      _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)];
-	#define              _heep_size      ROUNDUP(configTOTAL_HEAP_SIZE)
-/*	#else
-	extern  char        *_heep;
-	extern  long        _heep_size;
-	#endif
-*/	
-	extern  char  *sbrk(int  size)
-	{
-	   if  (brk_siz  +  size  >  _heep_size  ||  brk_siz  +  size  <  0)
-
-          return((char*)-1);
-	   brk_siz  +=  size;
-	   return(  (char*)_heep  +  brk_siz  -  size);
-	}
-
diff --git a/FreeRTOS/Source/portable/Softune/MB91460/port.c b/FreeRTOS/Source/portable/Softune/MB91460/port.c
deleted file mode 100755
index 7c79be1..0000000
--- a/FreeRTOS/Source/portable/Softune/MB91460/port.c
+++ /dev/null
@@ -1,321 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "mb91467d.h"
-
-/*-----------------------------------------------------------*/
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
- 
-#pragma asm
-#macro  SaveContext
-	 ORCCR #0x20								;Switch to user stack
-	 ST RP,@-R15								;Store RP
-	 STM0 (R7,R6,R5,R4,R3,R2,R1,R0)				;Store R7-R0
-	 STM1 (R14,R13,R12,R11,R10,R9,R8)			;Store R14-R8
-	 ST MDH, @-R15								;Store MDH
-	 ST MDL, @-R15								;Store MDL
-	 
-	 ANDCCR #0xDF								;Switch back to system stack
-	 LD @R15+,R0								;Store PC to R0 
-	 ORCCR #0x20								;Switch to user stack
-	 ST R0,@-R15								;Store PC to User stack
-	 
-	 ANDCCR #0xDF								;Switch back to system stack
-	 LD @R15+,R0								;Store PS to R0
-	 ORCCR #0x20								;Switch to user stack
-	 ST R0,@-R15								;Store PS to User stack
-	 
-	 LDI #_pxCurrentTCB, R0						;Get pxCurrentTCB address
-	 LD @R0, R0									;Get the pxCurrentTCB->pxTopOfStack address
-	 ST R15,@R0									;Store USP to pxCurrentTCB->pxTopOfStack
-	 
-	 ANDCCR #0xDF								;Switch back to system stack for the rest of tick ISR
-#endm
-
-#macro RestoreContext
-	 LDI #_pxCurrentTCB, R0						;Get pxCurrentTCB address
-	 LD @R0, R0									;Get the pxCurrentTCB->pxTopOfStack address
-	 ORCCR #0x20								;Switch to user stack
-	 LD @R0, R15								;Restore USP from pxCurrentTCB->pxTopOfStack
-
-	 LD @R15+,R0								;Store PS to R0
-	 ANDCCR #0xDF								;Switch to system stack
-	 ST R0,@-R15								;Store PS to system stack
-
-	 ORCCR #0x20								;Switch to user stack
-	 LD @R15+,R0								;Store PC to R0
-	 ANDCCR #0xDF								;Switch to system stack
-	 ST R0,@-R15								;Store PC to system stack
-
-	 ORCCR #0x20								;Switch back to retrieve the remaining context
-
-	 LD @R15+, MDL								;Restore MDL
-	 LD @R15+, MDH								;Restore MDH
-	 LDM1 (R14,R13,R12,R11,R10,R9,R8)			;Restore R14-R8
-	 LDM0 (R7,R6,R5,R4,R3,R2,R1,R0)				;Restore R7-R0
-	 LD @R15+, RP								;Restore RP
-	 
-	 ANDCCR #0xDF								;Switch back to system stack for the rest of tick ISR
-#endm
-#pragma endasm
-
-/*-----------------------------------------------------------*/
-
-/*
- * Perform hardware setup to enable ticks from timer 1,
- */
-static void prvSetupTimerInterrupt( void );
-/*-----------------------------------------------------------*/
-
-/* 
- * Initialise the stack of a task to look exactly as if a call to 
- * portSAVE_CONTEXT had been called.
- * 
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Place a few bytes of known values on the bottom of the stack. 
-	This is just useful for debugging. */
-
-	*pxTopOfStack = 0x11111111;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x22222222;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x33333333;
-	pxTopOfStack--;
-
-	/* This is a redundant push to the stack, it may be required if 
-	in some implementations of the compiler the parameter to the task 
-	is passed on to the stack rather than in R4 register. */
-	*pxTopOfStack = (StackType_t)(pvParameters);
-	pxTopOfStack--;                  
-    
-	*pxTopOfStack = ( StackType_t ) 0x00000000;	/* RP */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00007777;	/* R7 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00006666;	/* R6 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00005555;	/* R5 */
-	pxTopOfStack--;
-	
-	/* In the current implementation of the compiler the first 
-	parameter to the task (or function) is passed via R4 parameter 
-	to the task, hence the pvParameters pointer is copied into the R4 
-	register. See compiler manual section 4.6.2 for more information. */
-	*pxTopOfStack = ( StackType_t ) (pvParameters);	/* R4 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00003333;	/* R3 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00002222;	/* R2 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00001111;	/* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00000001;	/* R0 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x0000EEEE;	/* R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x0000DDDD;	/* R13 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x0000CCCC;	/* R12 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x0000BBBB;	/* R11 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x0000AAAA;	/* R10 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00009999;	/* R9 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x00008888;	/* R8 */
-	pxTopOfStack--;	
-	*pxTopOfStack = ( StackType_t ) 0x11110000;	/* MDH */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x22220000;	/* MDL */
-	pxTopOfStack--;
-
-	/* The start of the task code. */
-	*pxTopOfStack = ( StackType_t ) pxCode;	/* PC */
-	pxTopOfStack--;
-	 
-    /* PS - User Mode, USP, ILM=31, Interrupts enabled */
-	*pxTopOfStack = ( StackType_t ) 0x001F0030;	/* PS */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Setup the hardware to generate the tick. */
-	prvSetupTimerInterrupt();
-
-	/* Restore the context of the first task that is going to run. */
-	#pragma asm
-		RestoreContext
-	#pragma endasm
-
-	/* Simulate a function call end as generated by the compiler.  We will now
-	jump to the start of the task the context of which we have just restored. */	
-	__asm(" reti ");
-
-	/* Should not get here. */
-	return pdFAIL;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented - unlikely to ever be required as there is nothing to
-	return to. */
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupTimerInterrupt( void )
-{
-/* The peripheral clock divided by 32 is used by the timer. */
-const uint16_t usReloadValue = ( uint16_t ) ( ( ( configPER_CLOCK_HZ / configTICK_RATE_HZ ) / 32UL ) - 1UL );
-
-	/* Setup RLT0 to generate a tick interrupt. */
-
-	TMCSR0_CNTE = 0;		/* Count Disable */
-    TMCSR0_CSL = 0x2;		/* CLKP/32 */
-    TMCSR0_MOD = 0;			/* Software trigger */
-    TMCSR0_RELD = 1;		/* Reload */
-    
-    TMCSR0_UF = 0;			/* Clear underflow flag */
-	TMRLR0 = usReloadValue;
-	TMCSR0_INTE = 1;		/* Interrupt Enable */
-	TMCSR0_CNTE = 1;		/* Count Enable */
-	TMCSR0_TRG = 1;			/* Trigger */
-	
-    PORTEN = 0x3;			/* Port Enable */
-}
-/*-----------------------------------------------------------*/
-
-#if configUSE_PREEMPTION == 1
-
-	/* 
-	 * Tick ISR for preemptive scheduler. The tick count is incremented 
-	 * after the context is saved. Then the context is switched if required,
-	 * and last the context of the task which is to be resumed is restored.
-	 */
-
-	#pragma asm
-
-	.global _ReloadTimer0_IRQHandler
-	_ReloadTimer0_IRQHandler:
-
-	ANDCCR #0xEF							;Disable Interrupts
-	SaveContext								;Save context
-	ORCCR #0x10								;Re-enable Interrupts
-
-	LDI #0xFFFB,R1
-	LDI #_tmcsr0, R0
-	AND R1,@R0								;Clear RLT0 interrupt flag
-
-	CALL32	 _xTaskIncrementTick,R12		;Increment Tick
-	CALL32	 _vTaskSwitchContext,R12		;Switch context if required
-
-	ANDCCR #0xEF							;Disable Interrupts
-	RestoreContext							;Restore context
-	ORCCR #0x10								;Re-enable Interrupts
-
-	RETI
-
-	#pragma endasm
-	
-#else
-	
-	/* 
-	 * Tick ISR for the cooperative scheduler.  All this does is increment the
-	 * tick count.  We don't need to switch context, this can only be done by
-	 * manual calls to taskYIELD();
-	 */
-	__interrupt void ReloadTimer0_IRQHandler( void )
-	{
-		/* Clear RLT0 interrupt flag */
-		TMCSR0_UF = 0; 
-		xTaskIncrementTick();
-	}
-
-#endif
-
-/*
- * Manual context switch. We can use a __nosavereg attribute  as the context 
- * would be saved by PortSAVE_CONTEXT().  The context is switched and then 
- * the context of the new task is restored saved. 
- */
-#pragma asm
-
-	.global _vPortYieldDelayed
-	_vPortYieldDelayed:
-
-	ANDCCR #0xEF							;Disable Interrupts
-	SaveContext								;Save context
-	ORCCR #0x10								;Re-enable Interrupts
-
-	LDI #_dicr, R0
-	BANDL #0x0E, @R0						;Clear Delayed interrupt flag
-
-	CALL32	 _vTaskSwitchContext,R12		;Switch context if required
-
-	ANDCCR #0xEF							;Disable Interrupts
-	RestoreContext							;Restore context
-	ORCCR #0x10								;Re-enable Interrupts
-
-	RETI
-
-#pragma endasm
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch. We can use a __nosavereg attribute  as the context 
- * would be saved by PortSAVE_CONTEXT().  The context is switched and then 
- * the context of the new task is restored saved. 
- */ 	 
-#pragma asm
-
-	.global _vPortYield
-	_vPortYield:
-
-	SaveContext								;Save context
-	CALL32	 _vTaskSwitchContext,R12		;Switch context if required
-	RestoreContext							;Restore context
-	
-	RETI
-
-#pragma endasm
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/Softune/MB91460/portmacro.h b/FreeRTOS/Source/portable/Softune/MB91460/portmacro.h
deleted file mode 100755
index 30501c6..0000000
--- a/FreeRTOS/Source/portable/Softune/MB91460/portmacro.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/* Hardware specific includes. */
-#include "mb91467d.h"
-
-/* Standard includes. */
-#include 
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-#if configKERNEL_INTERRUPT_PRIORITY != 30
-	#error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - 30 (1Eh) being the default.
-#endif
-#define portDISABLE_INTERRUPTS() __asm(" STILM #1Eh ")
-#define portENABLE_INTERRUPTS() __asm(" STILM #1Fh ")
-
-#define portENTER_CRITICAL()	\
-	__asm(" ST PS,@-R15 ");		\
-	__asm(" ANDCCR #0xef ");	\
-
-
-#define portEXIT_CRITICAL()		\
-	__asm(" LD @R15+,PS ");		\
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			4
-#define portNOP()					__asm( " nop " );
-/*-----------------------------------------------------------*/
-
-/* portYIELD() uses a SW interrupt */
-#define portYIELD()					__asm( " INT #40H " );
-
-/* portYIELD_FROM_ISR() uses delayed interrupt */
-#define portYIELD_FROM_ISR()			DICR_DLYI = 1
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
-
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c b/FreeRTOS/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c
deleted file mode 100755
index 467ce87..0000000
--- a/FreeRTOS/Source/portable/Softune/MB96340/__STD_LIB_sbrk.c
+++ /dev/null
@@ -1,28 +0,0 @@
-/* THIS SAMPLE CODE IS PROVIDED AS IS AND IS SUBJECT TO ALTERATIONS. FUJITSU */
-/* MICROELECTRONICS ACCEPTS NO RESPONSIBILITY OR LIABILITY FOR ANY ERRORS OR */
-/* ELIGIBILITY FOR ANY PURPOSES.                                             */
-/*                 (C) Fujitsu Microelectronics Europe GmbH                  */
-/*---------------------------------------------------------------------------
-  __STD_LIB_sbrk.C
-  - Used by heap_3.c for memory accocation and deletion.
-
-/*---------------------------------------------------------------------------*/
-
-#include "FreeRTOSConfig.h"
-#include 
-
-	static  long         brk_siz  =  0;
-	typedef int          _heep_t;
-	#define ROUNDUP(s)   (((s)+sizeof(_heep_t)-1)&~(sizeof(_heep_t)-1))
-	static  _heep_t      _heep[ROUNDUP(configTOTAL_HEAP_SIZE)/sizeof(_heep_t)];
-	#define              _heep_size      ROUNDUP(configTOTAL_HEAP_SIZE)
-
-	extern  char  *sbrk(int  size)
-	{
-	   if  (brk_siz  +  size  >  _heep_size  ||  brk_siz  +  size  <  0)
-
-          return((char*)-1);
-	   brk_siz  +=  size;
-	   return(  (char*)_heep  +  brk_siz  -  size);
-	}
-
diff --git a/FreeRTOS/Source/portable/Softune/MB96340/port.c b/FreeRTOS/Source/portable/Softune/MB96340/port.c
deleted file mode 100755
index 18a0388..0000000
--- a/FreeRTOS/Source/portable/Softune/MB96340/port.c
+++ /dev/null
@@ -1,509 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the 16FX port.
- *----------------------------------------------------------*/
-
-/* 
- * Get current value of DPR and ADB registers 
- */
-StackType_t xGet_DPR_ADB_bank( void ); 
-
-/* 
- * Get current value of DTB and PCB registers 
- */
-StackType_t xGet_DTB_PCB_bank( void );
-
-/*
- * Sets up the periodic ISR used for the RTOS tick.  This uses RLT0, but
- * can be done using any given RLT.
- */
-static void prvSetupRLT0Interrupt( void );
-
-/*-----------------------------------------------------------*/
-
-/* 
- * We require the address of the pxCurrentTCB variable, but don't want to know
- * any details of its type. 
- */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/*-----------------------------------------------------------*/
-
-/* 
- * Macro to save a task context to the task stack. This macro  copies the 
- * saved context (AH:AL, DPR:ADB, DTB:PCB , PC and PS) from  the   system 
- * stack to task stack pointed by user stack pointer ( USP  for SMALL and 
- * MEDIUM memory model amd USB:USP for COMPACT  and LARGE memory model ),
- * then  it pushes the general purpose registers RW0-RW7  on  to the task 
- * stack. Finally the  resultant  stack  pointer  value is saved into the 
- * task  control  block  so  it  can  be retrieved the next time the task 
- * executes.
- */ 
-#if( ( configMEMMODEL == portSMALL ) || ( configMEMMODEL == portMEDIUM ) )
-
-	#define portSAVE_CONTEXT()											\
-			{	__asm(" POPW  A ");										\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" PUSHW  A ");									\
-				__asm(" OR   CCR,#H'20 ");								\
-	    		__asm(" POPW  A ");										\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" PUSHW  A ");									\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" POPW  A ");										\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" PUSHW  A ");									\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" POPW  A ");										\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" PUSHW  A ");									\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" POPW  A ");										\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" PUSHW  A ");									\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" POPW  A ");										\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" PUSHW  A ");									\
-				__asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");		\
-				__asm(" MOVW A, _pxCurrentTCB ");						\
-				__asm(" MOVW A, SP ");									\
-  				__asm(" SWAPW ");										\
-				__asm(" MOVW @AL, AH ");								\
-				__asm(" OR   CCR,#H'20 ");								\
-			}
-
-/* 
- * Macro to restore a task context from the task stack.  This is effecti-
- * vely the reverse of SAVE_CONTEXT(). First the stack pointer  value
- * (USP for SMALL and MEDIUM memory model amd  USB:USP  for  COMPACT  and 
- * LARGE memory model ) is loaded from the task  control block.  Next the 
- * value of all the general purpose registers RW0-RW7 is retrieved. Fina-
- * lly it copies of the context ( AH:AL,  DPR:ADB, DTB:PCB, PC and PS) of 
- * the task to be executed upon RETI from user stack to system stack.  
- */
- 
-	#define portRESTORE_CONTEXT()										\
-			{	__asm(" MOVW A, _pxCurrentTCB ");						\
-				__asm(" MOVW A, @A ");									\
-  				__asm(" AND  CCR,#H'DF ");  							\
-  				__asm(" MOVW SP, A ");									\
-				__asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");		\
-				__asm(" POPW  A ");										\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" PUSHW  A ");									\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" POPW  A ");										\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" PUSHW  A ");									\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" POPW  A ");										\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" PUSHW  A ");									\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" POPW  A ");										\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" PUSHW  A ");									\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" POPW  A ");										\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" PUSHW  A ");									\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" POPW  A ");										\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" PUSHW  A ");									\
-			}
-		
-#elif( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
-
-	#define portSAVE_CONTEXT()											\
-			{	__asm(" POPW  A ");										\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" PUSHW  A ");									\
-				__asm(" OR   CCR,#H'20 ");								\
-	    		__asm(" POPW  A ");										\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" PUSHW  A ");									\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" POPW  A ");										\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" PUSHW  A ");									\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" POPW  A ");										\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" PUSHW  A ");									\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" POPW  A ");										\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" PUSHW  A ");									\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" POPW  A ");										\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" PUSHW  A ");									\
-				__asm(" PUSHW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");		\
-				__asm(" MOVL A, _pxCurrentTCB ");						\
-				__asm(" MOVL RL2, A ");									\
-				__asm(" MOVW A, SP ");									\
-				__asm(" MOVW @RL2+0, A ");								\
-				__asm(" MOV A, USB ");									\
-				__asm(" MOV @RL2+2, A ");								\
-			}	
-            
-	#define portRESTORE_CONTEXT()										\
-			{	__asm(" MOVL A, _pxCurrentTCB ");						\
-				__asm(" MOVL RL2, A ");									\
-				__asm(" MOVW A, @RL2+0 ");								\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" MOVW SP, A ");									\
-				__asm(" MOV A, @RL2+2 ");								\
-				__asm(" MOV USB, A ");									\
-				__asm(" POPW (RW0,RW1,RW2,RW3,RW4,RW5,RW6,RW7) ");		\
-				__asm(" POPW  A ");										\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" PUSHW  A ");									\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" POPW  A ");										\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" PUSHW  A ");									\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" POPW  A ");										\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" PUSHW  A ");									\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" POPW  A ");										\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" PUSHW  A ");									\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" POPW  A ");										\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" PUSHW  A ");									\
-				__asm(" AND  CCR,#H'DF ");  							\
-				__asm(" POPW  A ");										\
-				__asm(" OR   CCR,#H'20 ");								\
-				__asm(" PUSHW  A ");									\
-			}
-#endif
-
-/*-----------------------------------------------------------*/	
-
-/* 
- * Functions for obtaining the current value  of  DPR:ADB, DTB:PCB bank registers
- */
- 
-#pragma asm
-
-        .GLOBAL    _xGet_DPR_ADB_bank
-        .GLOBAL    _xGet_DTB_PCB_bank
-        .SECTION   CODE, CODE, ALIGN=1
-
-_xGet_DPR_ADB_bank:
-
-    MOV A, DPR
-    SWAP
-    MOV A, ADB
-    ORW A
-	#if configMEMMODEL == portMEDIUM || configMEMMODEL == portLARGE
-		RETP
-	#elif configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT   
-		RET
-	#endif 
-
-
-_xGet_DTB_PCB_bank:
-
-    MOV A, DTB
-    SWAP
-    MOV A, PCB
-    ORW A
-	#if configMEMMODEL == portMEDIUM || configMEMMODEL == portLARGE
-		RETP
-	#elif configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT   
-		RET
-	#endif 
-
-#pragma endasm
-/*-----------------------------------------------------------*/
-
-/* 
- * Initialise the stack of a task to look exactly as if a call to 
- * portSAVE_CONTEXT had been called.
- * 
- * See the header file portable.h.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Place a few bytes of known values on the bottom of the stack. 
-	This is just useful for debugging. */
-	*pxTopOfStack = 0x1111;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2222;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x3333;
-	pxTopOfStack--;
-
-	/* Once the task is called the task  would  push  the  pointer to the
-	parameter onto the stack. Hence here the pointer would be copied to the stack
-	first.  When using the COMPACT or LARGE memory model the pointer would be 24 
-	bits, and when using the SMALL or MEDIUM memory model the pointer would be 16 
-	bits. */ 
-	#if( ( configMEMMODEL == portCOMPACT ) || ( configMEMMODEL == portLARGE ) )
-	{
-		*pxTopOfStack = ( StackType_t ) ( ( uint32_t ) ( pvParameters ) >> 16 );
-		pxTopOfStack--;         
-	}
-	#endif
-
-    *pxTopOfStack = ( StackType_t ) ( pvParameters );
-    pxTopOfStack--;                  
-    
-    /* This is redundant push to the stack. This is required in order to introduce 
-    an offset so that the task accesses a parameter correctly that is passed on to 
-    the task stack. */
-	#if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
-	{
-		*pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );      
-		pxTopOfStack--;       
-	}
-	#endif
-
-    /* This is redundant push to the stack. This is required in order to introduce 
-    an offset so the task correctly accesses the parameter passed on the task stack. */
-    *pxTopOfStack = ( StackType_t ) ( pxCode );
-    pxTopOfStack--;       
-
-    /* PS - User Mode, ILM=7, RB=0, Interrupts enabled,USP */
-    *pxTopOfStack = 0xE0C0;							
-	pxTopOfStack--; 
-
-	/* PC */
-	*pxTopOfStack = ( StackType_t ) ( pxCode );     
-    pxTopOfStack--;      
-    
-    /* DTB | PCB */
-	#if configMEMMODEL == portSMALL || configMEMMODEL == portCOMPACT
-	{
-		*pxTopOfStack = xGet_DTB_PCB_bank();         	
-		pxTopOfStack--;
-	}
-	#endif
-
-	/* DTB | PCB, in case of MEDIUM and LARGE memory models, PCB would be used
-	along with PC to indicate the start address of the function. */
-	#if( ( configMEMMODEL == portMEDIUM ) || ( configMEMMODEL == portLARGE ) )
-	{
-		*pxTopOfStack = ( xGet_DTB_PCB_bank() & 0xff00 ) | ( ( ( int32_t ) ( pxCode ) >> 16 ) & 0xff );
-		pxTopOfStack--;       
-	}
-	#endif
-
-	/* DPR | ADB  */
-	*pxTopOfStack = xGet_DPR_ADB_bank();				
-	pxTopOfStack--;
-    
-	/* AL */
-	*pxTopOfStack = ( StackType_t ) 0x9999;		
-	pxTopOfStack--;
-
-	/* AH */
-	*pxTopOfStack = ( StackType_t ) 0xAAAA;		
-	pxTopOfStack--;
-	
-	/* Next the general purpose registers. */
-	*pxTopOfStack = ( StackType_t ) 0x7777;	/* RW7 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x6666;	/* RW6 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x5555;	/* RW5 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x4444;	/* RW4 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x3333;	/* RW3 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x2222;	/* RW2 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x1111;	/* RW1 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x8888;	/* RW0 */
-		
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetupRLT0Interrupt( void )
-{
-/* The peripheral clock divided by 16 is used by the timer. */
-const uint16_t usReloadValue = ( uint16_t ) ( ( ( configCLKP1_CLOCK_HZ / configTICK_RATE_HZ ) / 16UL ) - 1UL );
-
-	/* set reload value = 34999+1, TICK Interrupt after 10 ms @ 56MHz of CLKP1 */
-	TMRLR0 = usReloadValue;    
-    
-    /* prescaler 1:16, reload, interrupt enable, count enable, trigger */
-    TMCSR0 = 0x041B;    
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	/* Setup the hardware to generate the tick. */
-	prvSetupRLT0Interrupt();
-	
-	/* Restore the context of the first task that is going to run. */
-	portRESTORE_CONTEXT();
-
-	/* Simulate a function call end as generated by the compiler.  We will now
-	jump to the start of the task the context of which we have just restored. */	
-	__asm(" reti ");
-
-
-	/* Should not get here. */
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented - unlikely to ever be required as there is nothing to
-	return to. */
-}
-
-/*-----------------------------------------------------------*/
-
-/* 
- * The interrupt service routine used depends on whether the pre-emptive
- * scheduler is being used or not.
- */
-
-#if configUSE_PREEMPTION == 1
-
-	/* 
-	 * Tick ISR for preemptive scheduler.  We can use a __nosavereg attribute
-	 * as the context is to be saved by the portSAVE_CONTEXT() macro, not the
-	 * compiler generated code.  The tick count is incremented after the context 
-	 * is saved. 
-	 */
-	__nosavereg __interrupt void prvRLT0_TICKISR( void )
-	{
-		/* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */
-		__DI();
-		
-		/* Save the context of the interrupted task. */
-		portSAVE_CONTEXT();
-		
-		/* Enable interrupts */
-		__EI();
-		
-		/* Clear RLT0 interrupt flag */
-		TMCSR0_UF = 0;      
-		
-		/* Increment the tick count then switch to the highest priority task
-		that is ready to run. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			vTaskSwitchContext();
-		}
-
-		/* Disable interrupts so that portRESTORE_CONTEXT() is not interrupted */
-		__DI();
-		
-		/* Restore the context of the new task. */
-		portRESTORE_CONTEXT();
-		
-		/* Enable interrupts */
-		__EI();
-	}
-
-#else
-
-	/*
-	 * Tick ISR for the cooperative scheduler.  All this does is increment the
-	 * tick count.  We don't need to switch context, this can only be done by
-	 * manual calls to taskYIELD();
-	 */
-	__interrupt void prvRLT0_TICKISR( void )
-	{
-		/* Clear RLT0 interrupt flag */
-		TMCSR0_UF = 0;  
-		
-		xTaskIncrementTick();
-	}
-
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch. We can use a __nosavereg attribute  as the context 
- * is to be saved by the portSAVE_CONTEXT() macro, not the compiler generated 
- * code.
- */
-__nosavereg __interrupt void vPortYield( void )
-{
-	/* Save the context of the interrupted task. */
-	portSAVE_CONTEXT();
-	
-	/* Switch to the highest priority task that is ready to run. */
-	vTaskSwitchContext();
-	
-	/* Restore the context of the new task. */
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-__nosavereg __interrupt void vPortYieldDelayed( void )
-{    
-    /* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */      
-	__DI();
-	
-	/* Save the context of the interrupted task. */
-	portSAVE_CONTEXT();
-	
-	/* Enable interrupts */
-	__EI();
-				
-	/* Clear delayed interrupt flag */
-    __asm (" CLRB  03A4H:0 ");
-	
-	/* Switch to the highest priority task that is ready to run. */
-	vTaskSwitchContext();
-	
-	/* Disable interrupts so that portSAVE_CONTEXT() is not interrupted */   
-	__DI();
-	
-	/* Restore the context of the new task. */
-	portRESTORE_CONTEXT();
-
-	/* Enable interrupts */
-	__EI();
-}	
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/Softune/MB96340/portmacro.h b/FreeRTOS/Source/portable/Softune/MB96340/portmacro.h
deleted file mode 100755
index 4994b5e..0000000
--- a/FreeRTOS/Source/portable/Softune/MB96340/portmacro.h
+++ /dev/null
@@ -1,116 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-/* Standard includes. */
-#include 
-
-/* Constants denoting the available memory models.  These are used within
-FreeRTOSConfig.h to set the configMEMMODEL value. */
-#define portSMALL     0
-#define portMEDIUM    1
-#define portCOMPACT   2
-#define portLARGE     3
-
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint16_t
-#define portBASE_TYPE	short
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Critical section handling. */
-#if configKERNEL_INTERRUPT_PRIORITY != 6
-	#error configKERNEL_INTERRUPT_PRIORITY (set in FreeRTOSConfig.h) must match the ILM value set in the following line - #06H being the default.
-#endif
-#define portDISABLE_INTERRUPTS()	__asm(" MOV ILM, #06h ")
-#define portENABLE_INTERRUPTS()		__asm(" MOV ILM, #07h ")
-
-#define portENTER_CRITICAL()								\
-		{	__asm(" PUSHW PS ");							\
-			portDISABLE_INTERRUPTS();						\
-		}
-
-#define portEXIT_CRITICAL()									\
-		{	__asm(" POPW PS ");								\
-		}
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			2
-#define portNOP()					__asm( " NOP " );
-/*-----------------------------------------------------------*/
-
-/* portYIELD() uses SW interrupt */
-#define portYIELD()					__asm( " INT #122 " );
-
-/* portYIELD_FROM_ISR() uses delayed interrupt */
-#define portYIELD_FROM_ISR()		 __asm( " SETB  03A4H:0 " );
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#define portMINIMAL_STACK_SIZE configMINIMAL_STACK_SIZE
-
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c b/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c
deleted file mode 100755
index 497a3fd..0000000
--- a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port.c
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the ARM CM4F port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-/* Constants required to manipulate the NVIC. */
-#define portNVIC_SYSTICK_CTRL		( ( volatile uint32_t * ) 0xe000e010 )
-#define portNVIC_SYSTICK_LOAD		( ( volatile uint32_t * ) 0xe000e014 )
-#define portNVIC_SYSPRI2			( ( volatile uint32_t * ) 0xe000ed20 )
-#define portNVIC_SYSTICK_CLK		0x00000004
-#define portNVIC_SYSTICK_INT		0x00000002
-#define portNVIC_SYSTICK_ENABLE		0x00000001
-#define portNVIC_PENDSV_PRI			( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16 )
-#define portNVIC_SYSTICK_PRI		( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24 )
-
-/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
-#define portVECTACTIVE_MASK			( 0xFFUL )
-
-/* Constants required to manipulate the VFP. */
-#define portFPCCR					( ( volatile uint32_t * ) 0xe000ef34 ) /* Floating point context control register. */
-#define portASPEN_AND_LSPEN_BITS	( 0x3UL << 30UL )
-
-/* Constants required to set up the initial stack. */
-#define portINITIAL_XPSR			( 0x01000000 )
-#define portINITIAL_EXC_RETURN		( 0xfffffffd )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/* For strict compliance with the Cortex-M spec the task start address should
-have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
-#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
-
-/* The priority used by the kernel is assigned to a variable to make access
-from inline assembler easier. */
-const uint32_t ulKernelPriority = configKERNEL_INTERRUPT_PRIORITY;
-
-/* Each task maintains its own interrupt status in the critical nesting
-variable. */
-static uint32_t ulCriticalNesting = 0xaaaaaaaaUL;
-
-/*
- * Setup the timer to generate the tick interrupts.
- */
-static void prvSetupTimerInterrupt( void );
-
-/*
- * Exception handlers.
- */
-void SysTick_Handler( void );
-
-/*
- * Functions defined in port_asm.asm.
- */
-extern void vPortEnableVFP( void );
-extern void vPortStartFirstTask( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/* This exists purely to allow the const to be used from within the
-port_asm.asm assembly file. */
-const uint32_t ulMaxSyscallInterruptPriorityConst = configMAX_SYSCALL_INTERRUPT_PRIORITY;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-
-	/* Offset added to account for the way the MCU uses the stack on entry/exit
-	of interrupts, and to ensure alignment. */
-	pxTopOfStack--;
-
-	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
-	pxTopOfStack--;
-	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
-
-	/* Save code space by skipping register initialisation. */
-	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
-	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
-
-	/* A save method is being used that requires each task to maintain its
-	own exec return value. */
-	pxTopOfStack--;
-	*pxTopOfStack = portINITIAL_EXC_RETURN;
-
-	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( ulCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-BaseType_t xPortStartScheduler( void )
-{
-	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
-	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
-	configASSERT( ( configMAX_SYSCALL_INTERRUPT_PRIORITY ) );
-
-	/* Make PendSV and SysTick the lowest priority interrupts. */
-	*(portNVIC_SYSPRI2) |= portNVIC_PENDSV_PRI;
-	*(portNVIC_SYSPRI2) |= portNVIC_SYSTICK_PRI;
-
-	/* Start the timer that generates the tick ISR.  Interrupts are disabled
-	here already. */
-	prvSetupTimerInterrupt();
-
-	/* Initialise the critical nesting count ready for the first task. */
-	ulCriticalNesting = 0;
-
-	/* Ensure the VFP is enabled - it should be anyway. */
-	vPortEnableVFP();
-
-	/* Lazy save always. */
-	*( portFPCCR ) |= portASPEN_AND_LSPEN_BITS;
-
-	/* Start the first task. */
-	vPortStartFirstTask();
-
-	/* Should not get here! */
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortYield( void )
-{
-	/* Set a PendSV to request a context switch. */
-	*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
-
-	/* Barriers are normally not required but do ensure the code is completely
-	within the specified behaviour for the architecture. */
-	__DSB();
-	__ISB();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	ulCriticalNesting++;
-	__DSB();
-	__ISB();
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( ulCriticalNesting == 1 )
-	{
-		configASSERT( ( ( *(portNVIC_INT_CTRL) ) & portVECTACTIVE_MASK ) == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	configASSERT( ulCriticalNesting );
-	ulCriticalNesting--;
-	if( ulCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-void SysTick_Handler( void )
-{
-uint32_t ulDummy;
-
-	ulDummy = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Pend a context switch. */
-			*(portNVIC_INT_CTRL) = portNVIC_PENDSVSET;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulDummy );
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Setup the systick timer to generate the tick interrupts at the required
- * frequency.
- */
-void prvSetupTimerInterrupt( void )
-{
-	/* Configure SysTick to interrupt at the requested rate. */
-	*(portNVIC_SYSTICK_LOAD) = ( configCPU_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
-	*(portNVIC_SYSTICK_CTRL) = portNVIC_SYSTICK_CLK | portNVIC_SYSTICK_INT | portNVIC_SYSTICK_ENABLE;
-}
-/*-----------------------------------------------------------*/
-
diff --git a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port_asm.asm b/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port_asm.asm
deleted file mode 100755
index 46173b6..0000000
--- a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/port_asm.asm
+++ /dev/null
@@ -1,236 +0,0 @@
-;/*
-; * FreeRTOS Kernel V10.2.1
-; * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
-; *
-; * Permission is hereby granted, free of charge, to any person obtaining a copy of
-; * this software and associated documentation files (the "Software"), to deal in
-; * the Software without restriction, including without limitation the rights to
-; * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
-; * the Software, and to permit persons to whom the Software is furnished to do so,
-; * subject to the following conditions:
-; *
-; * The above copyright notice and this permission notice shall be included in all
-; * copies or substantial portions of the Software.
-; *
-; * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-; * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
-; * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
-; * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
-; * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
-; * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-; *
-; * http://www.FreeRTOS.org
-; * http://aws.amazon.com/freertos
-; *
-; * 1 tab == 4 spaces!
-; */
-
-
-	.extern pxCurrentTCB
-	.extern vTaskSwitchContext
-	.extern ulMaxSyscallInterruptPriorityConst
-
-	.global _vector_14
-	.global _lc_ref__vector_pp_14
-	.global SVC_Handler
-	.global vPortStartFirstTask
-	.global vPortEnableVFP
-	.global ulPortSetInterruptMask
-	.global vPortClearInterruptMask
-
-;-----------------------------------------------------------
-
-	.section .text
-	.thumb
-	.align 4
-_vector_14: .type func
-
-	mrs r0, psp
-	isb
-
-	;Get the location of the current TCB.
-	ldr.w	r3, =pxCurrentTCB
-	ldr	r2, [r3]
-
-	;Is the task using the FPU context?  If so, push high vfp registers.
-	tst r14, #0x10
-	it eq
-	vstmdbeq r0!, {s16-s31}
-
-	;Save the core registers.
-	stmdb r0!, {r4-r11, r14}
-
-	;Save the new top of stack into the first member of the TCB.
-	str r0, [r2]
-
-	stmdb sp!, {r0, r3}
-	ldr.w r0, =ulMaxSyscallInterruptPriorityConst
-	ldr r0, [r0]
-	msr basepri, r0
-	bl vTaskSwitchContext
-	mov r0, #0
-	msr basepri, r0
-	ldmia sp!, {r0, r3}
-
-	;The first item in pxCurrentTCB is the task top of stack.
-	ldr r1, [r3]
-	ldr r0, [r1]
-
-	;Pop the core registers.
-	ldmia r0!, {r4-r11, r14}
-
-	;Is the task using the FPU context?  If so, pop the high vfp registers too.
-	tst r14, #0x10
-	it eq
-	vldmiaeq r0!, {s16-s31}
-
-	msr psp, r0
-	isb
-	bx r14
-
-	.size	_vector_14, $-_vector_14
-	.endsec
-
-;-----------------------------------------------------------
-
-; This function is an XMC4000 silicon errata workaround.  It will get used when
-; the SILICON_BUG_PMC_CM_001 linker macro is defined.
-	.section .text
-	.thumb
-	.align 4
-_lc_ref__vector_pp_14: .type func
-
-	mrs r0, psp
-	isb
-
-	;Get the location of the current TCB.
-	ldr.w	r3, =pxCurrentTCB
-	ldr	r2, [r3]
-
-	;Is the task using the FPU context?  If so, push high vfp registers.
-	tst r14, #0x10
-	it eq
-	vstmdbeq r0!, {s16-s31}
-
-	;Save the core registers.
-	stmdb r0!, {r4-r11, r14}
-
-	;Save the new top of stack into the first member of the TCB.
-	str r0, [r2]
-
-	stmdb sp!, {r3}
-	ldr.w r0, =ulMaxSyscallInterruptPriorityConst
-	ldr r0, [r0]
-	msr basepri, r0
-	bl vTaskSwitchContext
-	mov r0, #0
-	msr basepri, r0
-	ldmia sp!, {r3}
-
-	;The first item in pxCurrentTCB is the task top of stack.
-	ldr r1, [r3]
-	ldr r0, [r1]
-
-	;Pop the core registers.
-	ldmia r0!, {r4-r11, r14}
-
-	;Is the task using the FPU context?  If so, pop the high vfp registers too.
-	tst r14, #0x10
-	it eq
-	vldmiaeq r0!, {s16-s31}
-
-	msr psp, r0
-	isb
-	push { lr }
-	pop { pc } ; XMC4000 specific errata workaround.  Do not used "bx lr" here.
-
-	.size	_lc_ref__vector_pp_14, $-_lc_ref__vector_pp_14
-	.endsec
-
-;-----------------------------------------------------------
-
-	.section .text
-	.thumb
-	.align 4
-SVC_Handler: .type func
-	;Get the location of the current TCB.
-	ldr.w	r3, =pxCurrentTCB
-	ldr r1, [r3]
-	ldr r0, [r1]
-	;Pop the core registers.
-	ldmia r0!, {r4-r11, r14}
-	msr psp, r0
-	isb
-	mov r0, #0
-	msr	basepri, r0
-	bx r14
-	.size	SVC_Handler, $-SVC_Handler
-	.endsec
-
-;-----------------------------------------------------------
-
-	.section .text
-	.thumb
-	.align 4
-vPortStartFirstTask .type func
-	;Use the NVIC offset register to locate the stack.
-	ldr.w r0, =0xE000ED08
-	ldr r0, [r0]
-	ldr r0, [r0]
-	;Set the msp back to the start of the stack.
-	msr msp, r0
-	;Call SVC to start the first task.
-	cpsie i
-	cpsie f
-	dsb
-	isb
-	svc 0
-	.size	vPortStartFirstTask, $-vPortStartFirstTask
-	.endsec
-
-;-----------------------------------------------------------
-
-	.section .text
-	.thumb
-	.align 4
-vPortEnableVFP .type func
-	;The FPU enable bits are in the CPACR.
-	ldr.w r0, =0xE000ED88
-	ldr	r1, [r0]
-
-	;Enable CP10 and CP11 coprocessors, then save back.
-	orr	r1, r1, #( 0xf << 20 )
-	str r1, [r0]
-	bx	r14
-	.size	vPortEnableVFP, $-vPortEnableVFP
-	.endsec
-
-;-----------------------------------------------------------
-
-	.section .text
-	.thumb
-	.align 4
-ulPortSetInterruptMask:
-	mrs r0, basepri
-	ldr.w r1, =ulMaxSyscallInterruptPriorityConst
-	ldr r1, [r1]
-	msr basepri, r1
-	bx r14
-	.size	ulPortSetInterruptMask, $-ulPortSetInterruptMask
-	.endsec
-
-;-----------------------------------------------------------
-
-	.section .text
-	.thumb
-	.align 4
-vPortClearInterruptMask:
-	msr basepri, r0
-	bx r14
-	.size	vPortClearInterruptMask, $-vPortClearInterruptMask
-	.endsec
-
-;-----------------------------------------------------------
-
-	.end
-
diff --git a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h b/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
deleted file mode 100755
index fe56903..0000000
--- a/FreeRTOS/Source/portable/Tasking/ARM_CM4F/portmacro.h
+++ /dev/null
@@ -1,133 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-	not need to be guarded with a critical section. */
-	#define portTICK_TYPE_IS_ATOMIC 1
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
-extern void vPortYield( void );
-#define portNVIC_INT_CTRL			( ( volatile uint32_t * ) 0xe000ed04 )
-#define portNVIC_PENDSVSET			0x10000000
-#define portYIELD()					vPortYield()
-
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) *(portNVIC_INT_CTRL) = portNVIC_PENDSVSET
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-/*-----------------------------------------------------------*/
-
-
-/* Critical section management. */
-
-/*
- * Set basepri to portMAX_SYSCALL_INTERRUPT_PRIORITY without effecting other
- * registers.  r0 is clobbered.
- */
-#define portSET_INTERRUPT_MASK() __set_BASEPRI( configMAX_SYSCALL_INTERRUPT_PRIORITY )
-
-/*
- * Set basepri back to 0 without effective other registers.
- * r0 is clobbered.  FAQ:  Setting BASEPRI to 0 is not a bug.  Please see
- * http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html before disagreeing.
- */
-#define portCLEAR_INTERRUPT_MASK() __set_BASEPRI( 0 )
-
-extern uint32_t ulPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( uint32_t ulNewMask );
-#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortSetInterruptMask()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortClearInterruptMask( x )
-
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()	portSET_INTERRUPT_MASK()
-#define portENABLE_INTERRUPTS()		portCLEAR_INTERRUPT_MASK()
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#define portNOP()
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/port.c b/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/port.c
deleted file mode 100755
index 3cbb220..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/port.c
+++ /dev/null
@@ -1,385 +0,0 @@
-/*
-    FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution and was contributed
-    to the project by Technolution B.V. (www.technolution.nl,
-    freertos-riscv@technolution.eu) under the terms of the FreeRTOS
-    contributors license.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the RISC-V port.
- *----------------------------------------------------------*/
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "portmacro.h"
-
-#include "riscv_hal.h"
-
-#ifdef __riscv64
-# define STORE    sd
-# define LOAD     ld
-# define REGBYTES 8
-#else
-# define STORE    sw
-# define LOAD     lw
-# define REGBYTES 4
-#endif
-/* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialized to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
-static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
-
-/* Contains context when starting scheduler, save all 31 registers */
-#ifdef __gracefulExit
-BaseType_t xStartContext[31] = {0};
-#endif
-
-
-typedef struct
-{
-	uint32_t val_low;
-	uint32_t val_high;
-}riscv_machine_timer_t;
-
-static volatile riscv_machine_timer_t *mtime = (riscv_machine_timer_t *)0x4400BFF8;
-
-static volatile riscv_machine_timer_t *mtimecmp = (riscv_machine_timer_t *)0x44004000;
-
-/*
- * Setup the timer to generate the tick interrupts.
- */
-void vPortSetupTimer( void );
-
-/*
- * Set the next interval for the timer
- */
-static void prvSetNextTimerInterrupt( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-	uxCriticalNesting++;
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	uxCriticalNesting--;
-	if( uxCriticalNesting == 0 )
-	{
-		portENABLE_INTERRUPTS();
-	}
-}
-/*-----------------------------------------------------------*/
-
-/* Sets the next timer interrupt
- * Reads previous timer compare register, and adds tickrate */
-static void prvSetNextTimerInterrupt(void)
-{
-	uint64_t time;
-
-	time = mtime->val_low;
-	time |= ((uint64_t)mtime->val_high << 32);
-
-	time += (configCPU_CLOCK_HZ / configTICK_RATE_HZ);
-
-	mtimecmp->val_low = (uint32_t)(time & 0xFFFFFFFF);
-	mtimecmp->val_high = (uint32_t)((time >> 32) & 0xFFFFFFFF);
-
-	/* Enable timer interrupt */
-	__asm volatile("csrs mie,%0"::"r"(0x80));
-}
-/*-----------------------------------------------------------*/
-
-/* Sets and enable the timer interrupt */
-void vPortSetupTimer(void)
-{
-	uint64_t time;
-
-	time = mtime->val_low;
-	time |= ((uint64_t)mtime->val_high << 32);
-
-	time += (configCPU_CLOCK_HZ / configTICK_RATE_HZ);
-
-	mtimecmp->val_low = (uint32_t)(time & 0xFFFFFFFF);
-	mtimecmp->val_high = (uint32_t)((time >> 32) & 0xFFFFFFFF);
-
-
-	/* Enable timer interrupt */
-	__asm volatile("csrs mie,%0"::"r"(0x80));
-}
-/*-----------------------------------------------------------*/
-
-void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( uxCriticalNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-/* Clear current interrupt mask and set given mask */
-void vPortClearInterruptMask(int mask)
-{
-	__asm volatile("csrw mie, %0"::"r"(mask));
-}
-/*-----------------------------------------------------------*/
-
-/* Set interrupt mask and return current interrupt enable register */
-int vPortSetInterruptMask(void)
-{
-	int ret;
-	__asm volatile("csrr %0,mie":"=r"(ret));
-	__asm volatile("csrc mie,%0"::"i"(7));
-	return ret;
-}
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Simulate the stack frame as it would be created by a context switch
-	interrupt. */
-	register int *tp asm("x3");
-	pxTopOfStack--;
-	*pxTopOfStack = (portSTACK_TYPE)pxCode;			/* Start address */
-	pxTopOfStack -= 22;
-	*pxTopOfStack = (portSTACK_TYPE)pvParameters;	/* Register a0 */
-	pxTopOfStack -= 6;
-	*pxTopOfStack = (portSTACK_TYPE)tp; /* Register thread pointer */
-	pxTopOfStack -= 3;
-	*pxTopOfStack = (portSTACK_TYPE)prvTaskExitError; /* Register ra */
-	
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-void vPortSysTickHandler( void )
-{
-	/*Save Context*/
-	{
-		__asm volatile("lw	t0, pxCurrentTCB");
-		__asm volatile("sw	a2, 0x0(t0)");
-	}
-
-	/* Increment the RTOS tick. */
-	prvSetNextTimerInterrupt();
-
-	/*Switch task */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		vTaskSwitchContext();
-	}
-
-	/*Restore Context*/
-	{
-		__asm volatile("lw	sp, pxCurrentTCB");
-		__asm volatile("lw	sp, 0x0(sp)");
-
-		__asm volatile("lw	t0, 31 * 4(sp)");
-		__asm volatile("csrw	mepc, t0");
-
-		__asm volatile("lw	x1, 0x0(sp)");
-		__asm volatile("lw   x4, 3 * 4(sp)");
-		__asm volatile("lw   x5, 4 * 4(sp)");
-		__asm volatile("lw   x6, 5 * 4(sp)");
-		__asm volatile("lw   x7, 6 * 4(sp)");
-		__asm volatile("lw   x8, 7 * 4(sp)");
-		__asm volatile("lw   x9, 8 * 4(sp)");
-		__asm volatile("lw   x10, 9 * 4(sp)");
-		__asm volatile("lw   x11, 10 * 4(sp)");
-		__asm volatile("lw   x12, 11 * 4(sp)");
-		__asm volatile("lw   x13, 12 * 4(sp)");
-		__asm volatile("lw   x14, 13 * 4(sp)");
-		__asm volatile("lw   x15, 14 * 4(sp)");
-		__asm volatile("lw   x16, 15 * 4(sp)");
-		__asm volatile("lw   x17, 16 * 4(sp)");
-		__asm volatile("lw   x18, 17 * 4(sp)");
-		__asm volatile("lw   x19, 18 * 4(sp)");
-		__asm volatile("lw   x20, 19 * 4(sp)");
-		__asm volatile("lw   x21, 20 * 4(sp)");
-		__asm volatile("lw   x22, 21 * 4(sp)");
-		__asm volatile("lw   x23, 22 * 4(sp)");
-		__asm volatile("lw   x24, 23 * 4(sp)");
-		__asm volatile("lw   x25, 24 * 4(sp)");
-		__asm volatile("lw   x26, 25 * 4(sp)");
-		__asm volatile("lw   x27, 26 * 4(sp)");
-		__asm volatile("lw   x28, 27 * 4(sp)");
-		__asm volatile("lw   x29, 28 * 4(sp)");
-		__asm volatile("lw   x30, 29 * 4(sp)");
-		__asm volatile("lw   x31, 30 * 4(sp)");
-
-		__asm volatile("addi	sp, sp, 4 * 32");
-
-		__asm volatile("mret");
-	}
-}
-uint32_t g_startscheduler = 0;
-BaseType_t xPortStartScheduler( void )
-{
-	vPortSetupTimer();
-	uxCriticalNesting = 0;
-	g_startscheduler = 1;
-	__enable_irq();
-
-	raise_soft_interrupt();
-
-	/*Should not get here*/
-	return pdFALSE;
-}
-
-void Software_IRQHandler(void)
-{
-	if(1 == g_startscheduler)
-	{
-		g_startscheduler = 2; //skip the save n switch context first time when scheduler is starting.
-	}
-	else
-	{
-		/*Save Context*/
-		{
-			__asm volatile("lw	t0, pxCurrentTCB");
-			__asm volatile("sw	a2, 0x0(t0)");
-		}
-
-		vTaskSwitchContext();
-	}
-
-	/*Restore Context*/
-	{
-		__asm volatile("lw	sp, pxCurrentTCB");
-		__asm volatile("lw	sp, 0x0(sp)");
-
-		__asm volatile("lw	t0, 31 * 4(sp)");
-		__asm volatile("csrw	mepc, t0");
-
-		__asm volatile("lw	x1, 0x0(sp)");
-		__asm volatile("lw   x4, 3 * 4(sp)");
-		__asm volatile("lw   x5, 4 * 4(sp)");
-		__asm volatile("lw   x6, 5 * 4(sp)");
-		__asm volatile("lw   x7, 6 * 4(sp)");
-		__asm volatile("lw   x8, 7 * 4(sp)");
-		__asm volatile("lw   x9, 8 * 4(sp)");
-		__asm volatile("lw   x10, 9 * 4(sp)");
-		__asm volatile("lw   x11, 10 * 4(sp)");
-		__asm volatile("lw   x12, 11 * 4(sp)");
-		__asm volatile("lw   x13, 12 * 4(sp)");
-		__asm volatile("lw   x14, 13 * 4(sp)");
-		__asm volatile("lw   x15, 14 * 4(sp)");
-		__asm volatile("lw   x16, 15 * 4(sp)");
-		__asm volatile("lw   x17, 16 * 4(sp)");
-		__asm volatile("lw   x18, 17 * 4(sp)");
-		__asm volatile("lw   x19, 18 * 4(sp)");
-		__asm volatile("lw   x20, 19 * 4(sp)");
-		__asm volatile("lw   x21, 20 * 4(sp)");
-		__asm volatile("lw   x22, 21 * 4(sp)");
-		__asm volatile("lw   x23, 22 * 4(sp)");
-		__asm volatile("lw   x24, 23 * 4(sp)");
-		__asm volatile("lw   x25, 24 * 4(sp)");
-		__asm volatile("lw   x26, 25 * 4(sp)");
-		__asm volatile("lw   x27, 26 * 4(sp)");
-		__asm volatile("lw   x28, 27 * 4(sp)");
-		__asm volatile("lw   x29, 28 * 4(sp)");
-		__asm volatile("lw   x30, 29 * 4(sp)");
-		__asm volatile("lw   x31, 30 * 4(sp)");
-
-		__asm volatile("addi	sp, sp, 4 * 32");
-
-		//PRCI->MSIP[0] = 0x00;
-
-		__asm volatile("addi sp, sp, -1*4");
-		__asm volatile("sw t0, 0(sp)");
-		__asm volatile("li t0, 0x44000000");	// address of PRCI->MSIP[0]
-		__asm volatile("sw zero,0(t0)");
-		__asm volatile("lw t0, 0(sp)");
-		__asm volatile("addi sp, sp, 1*4");
-
-		__asm volatile("mret");
-	}
-}
-
-void vPortYield( void )
-{
-	raise_soft_interrupt();
-}
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/portasm.S b/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/portasm.S
deleted file mode 100755
index 9d8ad26..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/portasm.S
+++ /dev/null
@@ -1,282 +0,0 @@
-/*
-    FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution and was contributed
-    to the project by Technolution B.V. (www.technolution.nl,
-    freertos-riscv@technolution.eu) under the terms of the FreeRTOS
-    contributors license.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry''s de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-
-#ifdef __riscv64
-# define STORE    sd
-# define LOAD     ld
-# define REGBYTES 8
-#else
-# define STORE    sw
-# define LOAD     lw
-# define REGBYTES 4
-#endif
-
-#define MSTATUS_PRV1 0x1800
-
-.global portSAVE_CONTEXT
-.global portRESTORE_CONTEXT
-
-//.global xPortStartScheduler
-.global vPortYield
-.global vTaskIncrementTick
-.global vPortEndScheduler
-.global xExitStack
-
-
-/* Macro for saving task context */
-.macro portSAVE_CONTEXT
-	.global	pxCurrentTCB
-	/* make room in stack */
-	addi	sp, sp, -REGBYTES * 32
-
-	/* Save Context */
-	STORE	x1, 0x0(sp)
-	STORE	x2, 1 * REGBYTES(sp)
-	STORE	x3, 2 * REGBYTES(sp)
-	STORE	x4, 3 * REGBYTES(sp)
-	STORE	x5, 4 * REGBYTES(sp)
-	STORE	x6, 5 * REGBYTES(sp)
-	STORE	x7, 6 * REGBYTES(sp)
-	STORE	x8, 7 * REGBYTES(sp)
-	STORE	x9, 8 * REGBYTES(sp)
-	STORE	x10, 9 * REGBYTES(sp)
-	STORE	x11, 10 * REGBYTES(sp)
-	STORE	x12, 11 * REGBYTES(sp)
-	STORE	x13, 12 * REGBYTES(sp)
-	STORE	x14, 13 * REGBYTES(sp)
-	STORE	x15, 14 * REGBYTES(sp)
-	STORE	x16, 15 * REGBYTES(sp)
-	STORE	x17, 16 * REGBYTES(sp)
-	STORE	x18, 17 * REGBYTES(sp)
-	STORE	x19, 18 * REGBYTES(sp)
-	STORE	x20, 19 * REGBYTES(sp)
-	STORE	x21, 20 * REGBYTES(sp)
-	STORE	x22, 21 * REGBYTES(sp)
-	STORE	x23, 22 * REGBYTES(sp)
-	STORE	x24, 23 * REGBYTES(sp)
-	STORE	x25, 24 * REGBYTES(sp)
-	STORE	x26, 25 * REGBYTES(sp)
-	STORE	x27, 26 * REGBYTES(sp)
-	STORE	x28, 27 * REGBYTES(sp)
-	STORE	x29, 28 * REGBYTES(sp)
-	STORE	x30, 29 * REGBYTES(sp)
-	STORE	x31, 30 * REGBYTES(sp)
-
-	/* Store current stackpointer in task control block (TCB) */
-	LOAD	t0, pxCurrentTCB	//pointer
-	STORE	sp, 0x0(t0)
-	.endm
-
-/* Saves current error program counter (EPC) as task program counter */
-.macro portSAVE_EPC
-  	csrr	t0, mepc
-	STORE	t0, 31 * REGBYTES(sp)
-	.endm
-
-/* Saves current return adress (RA) as task program counter */
-.macro portSAVE_RA
-	STORE	ra, 31 * REGBYTES(sp)
-	.endm
-
-/* Macro for restoring task context */
-.macro portRESTORE_CONTEXT
-
-	.global	pxCurrentTCB
-	/* Load stack pointer from the current TCB */
-	LOAD	sp, pxCurrentTCB
-	LOAD	sp, 0x0(sp)
-
-	/* Load task program counter */
-	LOAD	t0, 31 * REGBYTES(sp)
-  	csrw	mepc, t0
-
-	/* Restore registers,
-	   Skip global pointer because that does not change */
-	LOAD	x1, 0x0(sp)
-	LOAD	x4, 3 * REGBYTES(sp)
-	LOAD	x5, 4 * REGBYTES(sp)
-	LOAD	x6, 5 * REGBYTES(sp)
-	LOAD	x7, 6 * REGBYTES(sp)
-	LOAD	x8, 7 * REGBYTES(sp)
-	LOAD	x9, 8 * REGBYTES(sp)
-	LOAD	x10, 9 * REGBYTES(sp)
-	LOAD	x11, 10 * REGBYTES(sp)
-	LOAD	x12, 11 * REGBYTES(sp)
-	LOAD	x13, 12 * REGBYTES(sp)
-	LOAD	x14, 13 * REGBYTES(sp)
-	LOAD	x15, 14 * REGBYTES(sp)
-	LOAD	x16, 15 * REGBYTES(sp)
-	LOAD	x17, 16 * REGBYTES(sp)
-	LOAD	x18, 17 * REGBYTES(sp)
-	LOAD	x19, 18 * REGBYTES(sp)
-	LOAD	x20, 19 * REGBYTES(sp)
-	LOAD	x21, 20 * REGBYTES(sp)
-	LOAD	x22, 21 * REGBYTES(sp)
-	LOAD	x23, 22 * REGBYTES(sp)
-	LOAD	x24, 23 * REGBYTES(sp)
-	LOAD	x25, 24 * REGBYTES(sp)
-	LOAD	x26, 25 * REGBYTES(sp)
-	LOAD	x27, 26 * REGBYTES(sp)
-	LOAD	x28, 27 * REGBYTES(sp)
-	LOAD	x29, 28 * REGBYTES(sp)
-	LOAD	x30, 29 * REGBYTES(sp)
-	LOAD	x31, 30 * REGBYTES(sp)
-
-	addi	sp, sp, REGBYTES * 32
-
-	/* Enable global interupt */
-    csrs mstatus,8
-
-	ret
-	.endm
-
-
-/*
-xPortStartScheduler:
-#ifdef __gracefulExit
-
-	la		t0, xStartContext
-	STORE	x1, 0x0(t0)
-	STORE	x2, 1 * REGBYTES(t0)
-	STORE	x3, 2 * REGBYTES(t0)
-	STORE	x4, 3 * REGBYTES(t0)
-	STORE	x5, 4 * REGBYTES(t0)
-	STORE	x6, 5 * REGBYTES(t0)
-	STORE	x7, 6 * REGBYTES(t0)
-	STORE	x8, 7 * REGBYTES(t0)
-	STORE	x9, 8 * REGBYTES(t0)
-	STORE	x10, 9 * REGBYTES(t0)
-	STORE	x11, 10 * REGBYTES(t0)
-	STORE	x12, 11 * REGBYTES(t0)
-	STORE	x13, 12 * REGBYTES(t0)
-	STORE	x14, 13 * REGBYTES(t0)
-	STORE	x15, 14 * REGBYTES(t0)
-	STORE	x16, 15 * REGBYTES(t0)
-	STORE	x17, 16 * REGBYTES(t0)
-	STORE	x18, 17 * REGBYTES(t0)
-	STORE	x19, 18 * REGBYTES(t0)
-	STORE	x20, 19 * REGBYTES(t0)
-	STORE	x21, 20 * REGBYTES(t0)
-	STORE	x22, 21 * REGBYTES(t0)
-	STORE	x23, 22 * REGBYTES(t0)
-	STORE	x24, 23 * REGBYTES(t0)
-	STORE	x25, 24 * REGBYTES(t0)
-	STORE	x26, 25 * REGBYTES(t0)
-	STORE	x27, 26 * REGBYTES(t0)
-	STORE	x28, 27 * REGBYTES(t0)
-	STORE	x29, 28 * REGBYTES(t0)
-	STORE	x30, 29 * REGBYTES(t0)
-	STORE	x31, 30 * REGBYTES(t0)
-#endif
-	jal		vPortSetupTimer
-	portRESTORE_CONTEXT
-*/
-
-vPortEndScheduler:
-#ifdef __gracefulExit
-	/* Load current context from xStartContext */
-	la		t0, xStartContext
-	LOAD	x1, 0x0(t0)
-	LOAD	x2, 1 * REGBYTES(t0)
-	LOAD	x3, 2 * REGBYTES(t0)
-	LOAD	x4, 3 * REGBYTES(t0)
-	LOAD	x5, 4 * REGBYTES(t0)
-	LOAD	x6, 5 * REGBYTES(t0)
-	LOAD	x7, 6 * REGBYTES(t0)
-	LOAD	x8, 7 * REGBYTES(t0)
-	LOAD	x9, 8 * REGBYTES(t0)
-	LOAD	x10, 9 * REGBYTES(t0)
-	LOAD	x11, 10 * REGBYTES(t0)
-	LOAD	x12, 11 * REGBYTES(t0)
-	LOAD	x13, 12 * REGBYTES(t0)
-	LOAD	x14, 13 * REGBYTES(t0)
-	LOAD	x15, 14 * REGBYTES(t0)
-	LOAD	x16, 15 * REGBYTES(t0)
-	LOAD	x17, 16 * REGBYTES(t0)
-	LOAD	x18, 17 * REGBYTES(t0)
-	LOAD	x19, 18 * REGBYTES(t0)
-	LOAD	x20, 19 * REGBYTES(t0)
-	LOAD	x21, 20 * REGBYTES(t0)
-	LOAD	x22, 21 * REGBYTES(t0)
-	LOAD	x23, 22 * REGBYTES(t0)
-	LOAD	x24, 23 * REGBYTES(t0)
-	LOAD	x25, 24 * REGBYTES(t0)
-	LOAD	x26, 25 * REGBYTES(t0)
-	LOAD	x27, 26 * REGBYTES(t0)
-	LOAD	x28, 27 * REGBYTES(t0)
-	LOAD	x29, 28 * REGBYTES(t0)
-	LOAD	x30, 39 * REGBYTES(t0)
-	LOAD	x31, 30 * REGBYTES(t0)
-#endif
-	ret
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/portmacro.h b/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/portmacro.h
deleted file mode 100755
index 99c4695..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/RISC-V/portmacro.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-    FreeRTOS V8.2.3 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution and was contributed
-    to the project by Technolution B.V. (www.technolution.nl,
-    freertos-riscv@technolution.eu) under the terms of the FreeRTOS
-    contributors license.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
-
-    ***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-    ***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-    the FAQ page "My application does not run, what could be wrong?".  Have you
-    defined configASSERT()?
-
-    http://www.FreeRTOS.org/support - In return for receiving this top quality
-    embedded software for free we request you assist our global community by
-    participating in the support forum.
-
-    http://www.FreeRTOS.org/training - Investing in training allows your team to
-    be as productive as possible as early as possible.  Now you can receive
-    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-    Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portBASE_TYPE	long
-
-#ifdef __riscv64
-	#define portSTACK_TYPE	uint64_t
-	#define portPOINTER_SIZE_TYPE	uint64_t
-#else
-	#define portSTACK_TYPE	uint32_t
-	#define portPOINTER_SIZE_TYPE	uint32_t
-#endif
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) (1000 / configTICK_RATE_HZ) )
-#ifdef __riscv64
-	#define portBYTE_ALIGNMENT	8
-#else
-	#define portBYTE_ALIGNMENT	4
-#endif
-#define portCRITICAL_NESTING_IN_TCB					1
-/*-----------------------------------------------------------*/
-
-
-/* Scheduler utilities. */
-extern void vPortYield( void );
-#define portYIELD()					vPortYield()
-/*-----------------------------------------------------------*/
-
-
-/* Critical section management. */
-extern int vPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( int );
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-
-#define portDISABLE_INTERRUPTS()				__asm volatile 	( "csrc mstatus,8" )
-#define portENABLE_INTERRUPTS()					__asm volatile 	( "csrs mstatus,8" )
-
-#define portENTER_CRITICAL()		vPortEnterCritical()
-#define portEXIT_CRITICAL()			vPortExitCritical()
-
-#define portSET_INTERRUPT_MASK_FROM_ISR()       vPortSetInterruptMask()
-
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue )       vPortClearInterruptMask( uxSavedStatusValue )
-
-#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired ) vPortYield()
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#define portNOP() __asm volatile 	( " nop " )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Wiced_CY/port.c b/FreeRTOS/Source/portable/ThirdParty/GCC/Wiced_CY/port.c
deleted file mode 100755
index b604164..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Wiced_CY/port.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Scheduler includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-	/* Check the configuration. */
-	#if( configMAX_PRIORITIES > 32 )
-		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
-	#endif
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#ifndef configSETUP_TICK_INTERRUPT
-	#error configSETUP_TICK_INTERRUPT() must be defined in FreeRTOSConfig.h to call the function that sets up the tick interrupt.
-#endif
-
-#ifndef configCLEAR_TICK_INTERRUPT
-	#error configCLEAR_TICK_INTERRUPT must be defined in FreeRTOSConfig.h to clear which ever interrupt was used to generate the tick interrupt.
-#endif
-
-/* A critical section is exited when the critical section nesting count reaches
-this value. */
-#define portNO_CRITICAL_NESTING			( ( uint32_t ) 0 )
-
-/* Tasks are not created with a floating point context, but can be given a
-floating point context after they have been created.  A variable is stored as
-part of the tasks context that holds portNO_FLOATING_POINT_CONTEXT if the task
-does not have an FPU context, or any other value if the task does have an FPU
-context. */
-#define portNO_FLOATING_POINT_CONTEXT	( ( StackType_t ) 0 )
-
-/* Constants required to setup the initial task context. */
-#define portINITIAL_SPSR				( ( StackType_t ) 0x1f ) /* System mode, ARM mode, IRQ enabled FIQ enabled. */
-#define portTHUMB_MODE_BIT				( ( StackType_t ) 0x20 )
-#define portTHUMB_MODE_ADDRESS			( 0x01UL )
-
-/* Masks all bits in the APSR other than the mode bits. */
-#define portAPSR_MODE_BITS_MASK			( 0x1F )
-
-/* The value of the mode bits in the APSR when the CPU is executing in user
-mode. */
-#define portAPSR_USER_MODE				( 0x10 )
-
-/* Let the user override the pre-loading of the initial LR with the address of
-prvTaskExitError() in case it messes up unwinding of the stack in the
-debugger. */
-#ifdef configTASK_RETURN_ADDRESS
-	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
-#else
-	#define portTASK_RETURN_ADDRESS	prvTaskExitError
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * Starts the first task executing.  This function is necessarily written in
- * assembly code so is implemented in portASM.s.
- */
-extern void vPortRestoreTaskContext( void );
-
-/*
- * Used to catch tasks that attempt to return from their implementing function.
- */
-static void prvTaskExitError( void );
-
-/*-----------------------------------------------------------*/
-
-/* A variable is used to keep track of the critical section nesting.  This
-variable has to be stored as part of the task context and must be initialised to
-a non zero value to ensure interrupts don't inadvertently become unmasked before
-the scheduler starts.  As it is stored as part of the task context it will
-automatically be set to 0 when the first task is started. */
-volatile uint32_t ulCriticalNesting = 9999UL;
-
-/* Saved as part of the task context.  If ulPortTaskHasFPUContext is non-zero then
-a floating point context must be saved and restored for the task. */
-volatile uint32_t ulPortTaskHasFPUContext = pdFALSE;
-
-/* Set to 1 to pend a context switch from an ISR. */
-volatile uint32_t ulPortYieldRequired = pdFALSE;
-
-/* Counts the interrupt nesting depth.  A context switch is only performed if
-if the nesting depth is 0. */
-volatile uint32_t ulPortInterruptNesting = 0UL;
-
-/* Used in the asm file to clear an interrupt. */
-__attribute__(( used )) const uint32_t ulICCEOIR = configEOI_ADDRESS;
-
-/*-----------------------------------------------------------*/
-
-/*
- * See header file for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-	/* Setup the initial stack of the task.  The stack is set exactly as
-	expected by the portRESTORE_CONTEXT() macro.
-
-	The fist real value on the stack is the status register, which is set for
-	system mode, with interrupts enabled.  A few NULLs are added first to ensure
-	GDB does not try decoding a non-existent return address. */
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) NULL;
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) portINITIAL_SPSR;
-
-	if( ( ( uint32_t ) pxCode & portTHUMB_MODE_ADDRESS ) != 0x00UL )
-	{
-		/* The task will start in THUMB mode. */
-		*pxTopOfStack |= portTHUMB_MODE_BIT;
-	}
-
-	pxTopOfStack--;
-
-	/* Next the return address, which in this case is the start of the task. */
-	*pxTopOfStack = ( StackType_t ) pxCode;
-	pxTopOfStack--;
-
-	/* Next all the registers other than the stack pointer. */
-	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* R14 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x12121212;	/* R12 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x11111111;	/* R11 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x10101010;	/* R10 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x09090909;	/* R9 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x08080808;	/* R8 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x07070707;	/* R7 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x06060606;	/* R6 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x05050505;	/* R5 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x04040404;	/* R4 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x03030303;	/* R3 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x02020202;	/* R2 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x01010101;	/* R1 */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) pvParameters; /* R0 */
-	pxTopOfStack--;
-
-	/* The task will start with a critical nesting count of 0 as interrupts are
-	enabled. */
-	*pxTopOfStack = portNO_CRITICAL_NESTING;
-	pxTopOfStack--;
-
-	/* The task will start without a floating point context.  A task that uses
-	the floating point hardware must call vPortTaskUsesFPU() before executing
-	any floating point instructions. */
-	*pxTopOfStack = portNO_FLOATING_POINT_CONTEXT;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-static void prvTaskExitError( void )
-{
-	/* A function that implements a task must not exit or attempt to return to
-	its caller as there is nothing to return to.  If a task wants to exit it
-	should instead call vTaskDelete( NULL ).
-
-	Artificially force an assert() to be triggered if configASSERT() is
-	defined, then stop here so application writers can catch the error. */
-	configASSERT( ulPortInterruptNesting == ~0UL );
-	portDISABLE_INTERRUPTS();
-	for( ;; );
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-uint32_t ulAPSR;
-
-	/* Only continue if the CPU is not in User mode.  The CPU must be in a
-	Privileged mode for the scheduler to start. */
-	__asm volatile ( "MRS %0, APSR" : "=r" ( ulAPSR ) );
-	ulAPSR &= portAPSR_MODE_BITS_MASK;
-	configASSERT( ulAPSR != portAPSR_USER_MODE );
-
-	if( ulAPSR != portAPSR_USER_MODE )
-	{
-		/* Start the timer that generates the tick ISR. */
-		portDISABLE_INTERRUPTS();
-		configSETUP_TICK_INTERRUPT();
-
-		/* Start the first task executing. */
-		vPortRestoreTaskContext();
-	}
-
-	/* Will only get here if vTaskStartScheduler() was called with the CPU in
-	a non-privileged mode or the binary point register was not set to its lowest
-	possible value.  prvTaskExitError() is referenced to prevent a compiler
-	warning about it being defined but not referenced in the case that the user
-	defines their own exit address. */
-	( void ) prvTaskExitError;
-	return 0;
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Not implemented in ports where there is nothing to return to.
-	Artificially force an assert. */
-	configASSERT( ulCriticalNesting == 1000UL );
-}
-/*-----------------------------------------------------------*/
-
-void vPortEnterCritical( void )
-{
-	portDISABLE_INTERRUPTS();
-
-	/* Now interrupts are disabled ulCriticalNesting can be accessed
-	directly.  Increment ulCriticalNesting to keep a count of how many times
-	portENTER_CRITICAL() has been called. */
-	ulCriticalNesting++;
-
-	/* This is not the interrupt safe version of the enter critical function so
-	assert() if it is being called from an interrupt context.  Only API
-	functions that end in "FromISR" can be used in an interrupt.  Only assert if
-	the critical nesting count is 1 to protect against recursive calls if the
-	assert function also uses a critical section. */
-	if( ulCriticalNesting == 1 )
-	{
-		configASSERT( ulPortInterruptNesting == 0 );
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortExitCritical( void )
-{
-	if( ulCriticalNesting > portNO_CRITICAL_NESTING )
-	{
-		/* Decrement the nesting count as the critical section is being
-		exited. */
-		ulCriticalNesting--;
-
-		/* If the nesting level has reached zero then all interrupt
-		priorities must be re-enabled. */
-		if( ulCriticalNesting == portNO_CRITICAL_NESTING )
-		{
-			/* Critical nesting has reached zero so all interrupt priorities
-			should be unmasked. */
-			portENABLE_INTERRUPTS();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-void FreeRTOS_Tick_Handler( void )
-{
-uint32_t ulInterruptStatus;
-
-	ulInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-
-	/* Increment the RTOS tick. */
-	if( xTaskIncrementTick() != pdFALSE )
-	{
-		ulPortYieldRequired = pdTRUE;
-	}
-
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( ulInterruptStatus );
-
-	configCLEAR_TICK_INTERRUPT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortTaskUsesFPU( void )
-{
-#if configFPU == 1
-uint32_t ulInitialFPSCR = 0;
-
-	/* A task is registering the fact that it needs an FPU context.  Set the
-	FPU flag (which is saved as part of the task context). */
-	ulPortTaskHasFPUContext = pdTRUE;
-
-	/* Initialise the floating point status register. */
-	__asm volatile ( "FMXR 	FPSCR, %0" :: "r" (ulInitialFPSCR) );
-#else
-	/* If FreeRTOS was built without FPU support but a task is using the FPU, we have a problem */
-	configASSERT( 0 );
-#endif
-}
-/*-----------------------------------------------------------*/
-
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Wiced_CY/portASM.S b/FreeRTOS/Source/portable/ThirdParty/GCC/Wiced_CY/portASM.S
deleted file mode 100755
index 0aa650c..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Wiced_CY/portASM.S
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-	.text
-	.arm
-
-	.set SYS_MODE,	0x1f
-	.set SVC_MODE,	0x13
-	.set IRQ_MODE,	0x12
-
-	/* Variables and functions. */
-	.extern ulMaxAPIPriorityMask
-	.extern _freertos_vector_table
-	.extern pxCurrentTCB
-	.extern vTaskSwitchContext
-	.extern vApplicationIRQHandler
-	.extern ulPortInterruptNesting
-	.extern ulPortTaskHasFPUContext
-	.extern ulICCEOIR
-	.extern ulPortYieldRequired
-
-	.global FreeRTOS_IRQ_Handler
-	.global FreeRTOS_SVC_Handler
-	.global vPortRestoreTaskContext
-
-
-.macro portSAVE_CONTEXT
-
-	/* Save the LR and SPSR onto the system mode stack before switching to
-	system mode to save the remaining system mode registers. */
-	SRSDB	sp!, #SYS_MODE
-	CPS		#SYS_MODE
-	PUSH	{R0-R12, R14}
-
-	/* Push the critical nesting count. */
-	LDR		R2, ulCriticalNestingConst
-	LDR		R1, [R2]
-	PUSH	{R1}
-
-	/* Does the task have a floating point context that needs saving?  If
-	ulPortTaskHasFPUContext is 0 then no. */
-	LDR		R2, ulPortTaskHasFPUContextConst
-	LDR		R3, [R2]
-	CMP		R3, #0
-
-#if configFPU == 1
-	/* Save the floating point context, if any. */
-	FMRXNE  R1,  FPSCR
-	VPUSHNE {D0-D15}
-#if configFPU_D32 == 1
-	VPUSHNE	{D16-D31}
-#endif /* configFPU_D32 */
-	PUSHNE	{R1}
-#endif
-
-	/* Save ulPortTaskHasFPUContext itself. */
-	PUSH	{R3}
-
-	/* Save the stack pointer in the TCB. */
-	LDR		R0, pxCurrentTCBConst
-	LDR		R1, [R0]
-	STR		SP, [R1]
-
-	.endm
-
-; /**********************************************************************/
-
-.macro portRESTORE_CONTEXT
-
-	/* Set the SP to point to the stack of the task being restored. */
-	LDR		R0, pxCurrentTCBConst
-	LDR		R1, [R0]
-	LDR		SP, [R1]
-
-	/* Is there a floating point context to restore?  If the restored
-	ulPortTaskHasFPUContext is zero then no. */
-	LDR		R0, ulPortTaskHasFPUContextConst
-	POP		{R1}
-	STR		R1, [R0]
-	CMP		R1, #0
-
-#if configFPU == 1
-	/* Restore the floating point context, if any. */
-	POPNE 	{R0}
-#if configFPU_D32 == 1
-	VPOPNE	{D16-D31}
-#endif /* configFPU_D32 */
-	VPOPNE	{D0-D15}
-	VMSRNE  FPSCR, R0
-#endif
-
-	/* Restore the critical section nesting depth. */
-	LDR		R0, ulCriticalNestingConst
-	POP		{R1}
-	STR		R1, [R0]
-
-	/* Restore all system mode registers other than the SP (which is already
-	being used). */
-	POP		{R0-R12, R14}
-
-	/* Return to the task code, loading CPSR on the way. */
-	RFEIA	sp!
-
-	.endm
-
-
-
-
-/******************************************************************************
- * SVC handler is used to yield.
- *****************************************************************************/
-.align 4
-.type FreeRTOS_SVC_Handler, %function
-FreeRTOS_SVC_Handler:
-	/* Save the context of the current task and select a new task to run. */
-	portSAVE_CONTEXT
-	LDR R0, vTaskSwitchContextConst
-	BLX	R0
-	portRESTORE_CONTEXT
-
-
-/******************************************************************************
- * vPortRestoreTaskContext is used to start the scheduler.
- *****************************************************************************/
-.align 4
-.type vPortRestoreTaskContext, %function
-vPortRestoreTaskContext:
-	/* Switch to system mode. */
-	CPS		#SYS_MODE
-	portRESTORE_CONTEXT
-
-.align 4
-.type FreeRTOS_IRQ_Handler, %function
-FreeRTOS_IRQ_Handler:
-	/* Return to the interrupted instruction. */
-	SUB		lr, lr, #4
-
-	/* Push the return address and SPSR. */
-	PUSH	{lr}
-	MRS		lr, SPSR
-	PUSH	{lr}
-
-	/* Change to supervisor mode to allow reentry. */
-	CPS		#0x13
-
-	/* Push used registers. */
-	PUSH	{r0-r3, r12}
-
-	/* Increment nesting count.  r3 holds the address of ulPortInterruptNesting
-	for future use.  r1 holds the original ulPortInterruptNesting value for
-	future use. */
-	LDR		r3, ulPortInterruptNestingConst
-	LDR		r1, [r3]
-	ADD		r0, r1, #1
-	STR		r0, [r3]
-
-	/* Ensure bit 2 of the stack pointer is clear.  r2 holds the bit 2 value for
-	future use. */
-	MOV		r0, sp
-	AND		r2, r0, #4
-	SUB		sp, sp, r2
-
-	/* Call the interrupt handler. */
-	PUSH	{r0-r3, lr}
-	LDR		r1, vApplicationIRQHandlerConst
-	BLX		r1
-	POP		{r0-r3, lr}
-	ADD		sp, sp, r2
-
-	CPSID	i
-	DSB
-	ISB
-
-	/* Write to the EOI register. */
-	LDR 	r0, ulICCEOIRConst
-	LDR		r2, [r0]
-	STR		r0, [r2]
-
-	/* Restore the old nesting count. */
-	STR		r1, [r3]
-
-	/* A context switch is never performed if the nesting count is not 0. */
-	CMP		r1, #0
-	BNE		exit_without_switch
-
-	/* Did the interrupt request a context switch?  r1 holds the address of
-	ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
-	use. */
-	LDR		r1, ulPortYieldRequiredConst
-	LDR		r0, [r1]
-	CMP		r0, #0
-	BNE		switch_before_exit
-
-exit_without_switch:
-	/* No context switch.  Restore used registers, LR_irq and SPSR before
-	returning. */
-	POP		{r0-r3, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	MOVS	PC, LR
-
-switch_before_exit:
-	/* A context swtich is to be performed.  Clear the context switch pending
-	flag. */
-	MOV		r0, #0
-	STR		r0, [r1]
-
-	/* Restore used registers, LR-irq and SPSR before saving the context
-	to the task stack. */
-	POP		{r0-r3, r12}
-	CPS		#IRQ_MODE
-	POP		{LR}
-	MSR		SPSR_cxsf, LR
-	POP		{LR}
-	portSAVE_CONTEXT
-
-	/* Call the function that selects the new task to execute.
-	vTaskSwitchContext() if vTaskSwitchContext() uses LDRD or STRD
-	instructions, or 8 byte aligned stack allocated data.  LR does not need
-	saving as a new LR will be loaded by portRESTORE_CONTEXT anyway. */
-	LDR		R0, vTaskSwitchContextConst
-	BLX		R0
-
-	/* Restore the context of, and branch to, the task selected to execute
-	next. */
-	portRESTORE_CONTEXT
-
-ulICCEOIRConst:	.word ulICCEOIR
-pxCurrentTCBConst: .word pxCurrentTCB
-ulCriticalNestingConst: .word ulCriticalNesting
-ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
-vTaskSwitchContextConst: .word vTaskSwitchContext
-vApplicationIRQHandlerConst: .word vApplicationIRQHandler
-ulPortInterruptNestingConst: .word ulPortInterruptNesting
-ulPortYieldRequiredConst: .word ulPortYieldRequired
-
-.end
-
-
-
-
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Wiced_CY/portmacro.h b/FreeRTOS/Source/portable/ThirdParty/GCC/Wiced_CY/portmacro.h
deleted file mode 100755
index 8c4aee3..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Wiced_CY/portmacro.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-	extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the given hardware
- * and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	long
-
-typedef portSTACK_TYPE StackType_t;
-typedef long BaseType_t;
-typedef unsigned long UBaseType_t;
-
-typedef uint32_t TickType_t;
-#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-
-/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
-not need to be guarded with a critical section. */
-#define portTICK_TYPE_IS_ATOMIC 1
-
-/*-----------------------------------------------------------*/
-
-/* Hardware specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			8
-
-/*-----------------------------------------------------------*/
-
-/* Task utilities. */
-
-/* Called at the end of an ISR that can cause a context switch. */
-#define portEND_SWITCHING_ISR( xSwitchRequired )\
-{												\
-extern volatile uint32_t ulPortYieldRequired;	\
-												\
-	if( xSwitchRequired != pdFALSE )			\
-	{											\
-		ulPortYieldRequired = pdTRUE;			\
-	}											\
-}
-
-#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
-#define portYIELD() __asm volatile ( "SWI 0		\n"				\
-									 "ISB		  " );
-
-
-/*-----------------------------------------------------------
- * Critical section control
- *----------------------------------------------------------*/
-
-extern void vPortEnterCritical( void );
-extern void vPortExitCritical( void );
-extern uint32_t ulPortSetInterruptMask( void );
-extern void vPortClearInterruptMask( uint32_t ulNewMaskValue );
-extern void vPortInstallFreeRTOSVectorTable( void );
-
-/* The I bit within the CPSR. */
-#define portINTERRUPT_ENABLE_BIT	( 1 << 7 )
-
-/* In the absence of a priority mask register, these functions and macros
-globally enable and disable interrupts. */
-#define portENTER_CRITICAL()		vPortEnterCritical();
-#define portEXIT_CRITICAL()			vPortExitCritical();
-#define portENABLE_INTERRUPTS()		__asm volatile ( "CPSIE i 	\n"	);
-#define portDISABLE_INTERRUPTS()	__asm volatile ( "CPSID i 	\n"		\
-													 "DSB		\n"		\
-													 "ISB		  " );
-
-__attribute__( ( always_inline ) ) static __inline uint32_t portINLINE_SET_INTERRUPT_MASK_FROM_ISR( void )
-{
-volatile uint32_t ulCPSR;
-
-	__asm volatile ( "MRS %0, CPSR" : "=r" (ulCPSR) );
-	ulCPSR &= portINTERRUPT_ENABLE_BIT;
-	portDISABLE_INTERRUPTS();
-	return ulCPSR;
-}
-
-#define portSET_INTERRUPT_MASK_FROM_ISR() portINLINE_SET_INTERRUPT_MASK_FROM_ISR()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	if( x == 0 ) portENABLE_INTERRUPTS()
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site.  These are
-not required for this port but included in case common demo code that uses these
-macros is used. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters )	void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters )	void vFunction( void *pvParameters )
-
-/* Tickless idle/low power functionality. */
-#ifndef portSUPPRESS_TICKS_AND_SLEEP
-	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
-	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
-#endif
-
-/* Prototype of the FreeRTOS tick handler.  This must be installed as the
-handler for whichever peripheral is used to generate the RTOS tick. */
-void FreeRTOS_Tick_Handler( void );
-
-/* Any task that uses the floating point unit MUST call vPortTaskUsesFPU()
-before any floating point instructions are executed. */
-void vPortTaskUsesFPU( void );
-#define portTASK_USES_FLOATING_POINT() vPortTaskUsesFPU()
-
-#define portLOWEST_INTERRUPT_PRIORITY ( ( ( uint32_t ) configUNIQUE_INTERRUPT_PRIORITIES ) - 1UL )
-#define portLOWEST_USABLE_INTERRUPT_PRIORITY ( portLOWEST_INTERRUPT_PRIORITY - 1UL )
-
-/* Architecture specific optimisations. */
-#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
-	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
-#endif
-
-#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
-
-	/* Store/clear the ready priorities in a bit map. */
-	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
-	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
-
-	/*-----------------------------------------------------------*/
-
-	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) __builtin_clz( uxReadyPriorities ) )
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-#define portNOP() __asm volatile( "NOP" )
-#define portINLINE __inline
-
-#ifdef __cplusplus
-	} /* extern C */
-#endif
-
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c
deleted file mode 100755
index 2367d82..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/FreeRTOS-openocd.c
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * Since at least FreeRTOS V7.5.3 uxTopUsedPriority is no longer
- * present in the kernel, so it has to be supplied by other means for
- * OpenOCD's threads awareness.
- *
- * Add this file to your project, and, if you're using --gc-sections,
- * ``--undefined=uxTopUsedPriority'' (or
- * ``-Wl,--undefined=uxTopUsedPriority'' when using gcc for final
- * linking) to your LDFLAGS; same with all the other symbols you need.
- */
-
-#include "FreeRTOS.h"
-#include "esp_attr.h"
-#include "sdkconfig.h"
-
-#ifdef __GNUC__
-#define USED __attribute__((used))
-#else
-#define USED
-#endif
-
-#ifdef CONFIG_ESP32_DEBUG_OCDAWARE
-const int USED DRAM_ATTR uxTopUsedPriority = configMAX_PRIORITIES - 1;
-#endif
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h
deleted file mode 100755
index 4ce41d3..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portbenchmark.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*******************************************************************************
-// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-*/
-
-/*
- * This utility helps benchmarking interrupt latency and context switches.
- * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h.
- * You will also need to download the FreeRTOS_trace patch that contains
- * portbenchmark.c and the complete version of portbenchmark.h
- */
-
-#ifndef PORTBENCHMARK_H
-#define PORTBENCHMARK_H
-
-#if configBENCHMARK
-    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
-#endif
-
-#define portbenchmarkINTERRUPT_DISABLE()
-#define portbenchmarkINTERRUPT_RESTORE(newstate)
-#define portbenchmarkIntLatency()
-#define portbenchmarkIntWait()
-#define portbenchmarkReset()
-#define portbenchmarkPrint()
-
-#endif /* PORTBENCHMARK */
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
deleted file mode 100755
index d22318c..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/portmacro.h
+++ /dev/null
@@ -1,462 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that has become a de facto standard.             *
-     *                                                                       *
-     *    Help yourself get started quickly and support the FreeRTOS         *
-     *    project by purchasing a FreeRTOS tutorial book, reference          *
-     *    manual, or both from: http://www.FreeRTOS.org/Documentation        *
-     *                                                                       *
-     *    Thank you!                                                         *
-     *                                                                       *
-    ***************************************************************************
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available from the following
-    link: http://www.freertos.org/a00114.html
-
-    1 tab == 4 spaces!
-
-    ***************************************************************************
-     *                                                                       *
-     *    Having a problem?  Start by reading the FAQ "My application does   *
-     *    not run, what could be wrong?"                                     *
-     *                                                                       *
-     *    http://www.FreeRTOS.org/FAQHelp.html                               *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org - Documentation, books, training, latest versions,
-    license and Real Time Engineers Ltd. contact details.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
-    Integrity Systems to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include 
-
-#include 
-#include 
-#include 	/* required for XSHAL_CLIB */
-#include 
-#include "esp_timer.h"              /* required for FreeRTOS run time stats */
-#include "esp_system.h"
-
-
-#include 
-#include "soc/soc_memory_layout.h"
-
-//#include "xtensa_context.h"
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-
-#define portCHAR		int8_t
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		int32_t
-#define portSHORT		int16_t
-#define portSTACK_TYPE	uint8_t
-#define portBASE_TYPE	int
-
-typedef portSTACK_TYPE			StackType_t;
-typedef portBASE_TYPE			BaseType_t;
-typedef unsigned portBASE_TYPE	UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-// portbenchmark
-#include "portbenchmark.h"
-
-#include "sdkconfig.h"
-#include "esp_attr.h"
-
-/* "mux" data structure (spinlock) */
-typedef struct {
-	/* owner field values:
-	 * 0                - Uninitialized (invalid)
-	 * portMUX_FREE_VAL - Mux is free, can be locked by either CPU
-	 * CORE_ID_PRO / CORE_ID_APP - Mux is locked to the particular core
-	 *
-	 * Any value other than portMUX_FREE_VAL, CORE_ID_PRO, CORE_ID_APP indicates corruption
-	 */
-	uint32_t owner;
-	/* count field:
-	 * If mux is unlocked, count should be zero.
-	 * If mux is locked, count is non-zero & represents the number of recursive locks on the mux.
-	 */
-	uint32_t count;
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-	const char *lastLockedFn;
-	int lastLockedLine;
-#endif
-} portMUX_TYPE;
-
-#define portMUX_FREE_VAL		0xB33FFFFF
-
-/* Special constants for vPortCPUAcquireMutexTimeout() */
-#define portMUX_NO_TIMEOUT      (-1)  /* When passed for 'timeout_cycles', spin forever if necessary */
-#define portMUX_TRY_LOCK        0     /* Try to acquire the spinlock a single time only */
-
-// Keep this in sync with the portMUX_TYPE struct definition please.
-#ifndef CONFIG_FREERTOS_PORTMUX_DEBUG
-#define portMUX_INITIALIZER_UNLOCKED {					\
-		.owner = portMUX_FREE_VAL,						\
-		.count = 0,										\
-	}
-#else
-#define portMUX_INITIALIZER_UNLOCKED {					\
-		.owner = portMUX_FREE_VAL,						\
-		.count = 0,										\
-		.lastLockedFn = "(never locked)",				\
-		.lastLockedLine = -1							\
-	}
-#endif
-
-
-#define portASSERT_IF_IN_ISR()        vPortAssertIfInISR()
-void vPortAssertIfInISR();
-
-#define portCRITICAL_NESTING_IN_TCB 1
-
-/*
-Modifications to portENTER_CRITICAL.
-
-For an introduction, see "Critical Sections & Disabling Interrupts" in docs/api-guides/freertos-smp.rst
-
-The original portENTER_CRITICAL only disabled the ISRs. This is enough for single-CPU operation: by
-disabling the interrupts, there is no task switch so no other tasks can meddle in the data, and because
-interrupts are disabled, ISRs can't corrupt data structures either.
-
-For multiprocessing, things get a bit more hairy. First of all, disabling the interrupts doesn't stop
-the tasks or ISRs on the other processors meddling with our CPU. For tasks, this is solved by adding
-a spinlock to the portENTER_CRITICAL macro. A task running on the other CPU accessing the same data will
-spinlock in the portENTER_CRITICAL code until the first CPU is done.
-
-For ISRs, we now also need muxes: while portENTER_CRITICAL disabling interrupts will stop ISRs on the same
-CPU from meddling with the data, it does not stop interrupts on the other cores from interfering with the
-data. For this, we also use a spinlock in the routines called by the ISR, but these spinlocks
-do not disable the interrupts (because they already are).
-
-This all assumes that interrupts are either entirely disabled or enabled. Interrupt priority levels
-will break this scheme.
-
-Remark: For the ESP32, portENTER_CRITICAL and portENTER_CRITICAL_ISR both alias vTaskEnterCritical, meaning
-that either function can be called both from ISR as well as task context. This is not standard FreeRTOS 
-behaviour; please keep this in mind if you need any compatibility with other FreeRTOS implementations.
-*/
-void vPortCPUInitializeMutex(portMUX_TYPE *mux);
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-#error CONFIG_FREERTOS_PORTMUX_DEBUG not supported in Amazon FreeRTOS
-#endif
-
-void vTaskExitCritical();
-void vTaskEnterCritical();
-static inline void vPortConsumeSpinlockArg(int unused, ...)
-{
-}
-
-/** @brief Acquire a portmux spinlock with a timeout
- *
- * @param mux Pointer to portmux to acquire.
- * @param timeout_cycles Timeout to spin, in CPU cycles. Pass portMUX_NO_TIMEOUT to wait forever,
- * portMUX_TRY_LOCK to try a single time to acquire the lock.
- *
- * @return true if mutex is successfully acquired, false on timeout.
- */
-bool vPortCPUAcquireMutexTimeout(portMUX_TYPE *mux, int timeout_cycles);
-void vPortCPUReleaseMutex(portMUX_TYPE *mux);
-
-#define portENTER_CRITICAL(...)        do { vTaskEnterCritical(); vPortConsumeSpinlockArg(0, ##__VA_ARGS__); } while(0)
-#define portEXIT_CRITICAL(...)         do { vTaskExitCritical(); vPortConsumeSpinlockArg(0, ##__VA_ARGS__); } while(0)
-
-
-#define portENTER_CRITICAL_ISR(mux)    vPortCPUAcquireMutexTimeout(mux, portMUX_NO_TIMEOUT)
-#define portEXIT_CRITICAL_ISR(mux)     vPortCPUReleaseMutex(mux)
-
-#define portENTER_CRITICAL_SAFE(mux)  do {                                             \
-                                         if (xPortInIsrContext()) {                    \
-                                             portENTER_CRITICAL_ISR(mux);              \
-                                         } else {                                      \
-                                             portENTER_CRITICAL(mux);                  \
-                                         }                                             \
-                                      } while(0)
-
-#define portEXIT_CRITICAL_SAFE(mux)  do {                                              \
-                                         if (xPortInIsrContext()) {                    \
-                                             portEXIT_CRITICAL_ISR(mux);               \
-                                         } else {                                      \
-                                             portEXIT_CRITICAL(mux);                   \
-                                         }                                             \
-                                      } while(0)
-
-
-// Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any?
-// These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level.
-//
-// Only applies to one CPU. See notes above & below for reasons not to use these.
-#define portDISABLE_INTERRUPTS()      do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0)
-#define portENABLE_INTERRUPTS()       do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0)
-
-// Cleaner solution allows nested interrupts disabling and restoring via local registers or stack.
-// They can be called from interrupts too.
-// WARNING: Only applies to current CPU. See notes above.
-static inline unsigned portENTER_CRITICAL_NESTED() {
-	unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL);
-	portbenchmarkINTERRUPT_DISABLE();
-	return state;
-}
-#define portEXIT_CRITICAL_NESTED(state)   do { portbenchmarkINTERRUPT_RESTORE(state); XTOS_RESTORE_JUST_INTLEVEL(state); } while (0)
-
-// These FreeRTOS versions are similar to the nested versions above
-#define portSET_INTERRUPT_MASK_FROM_ISR()            portENTER_CRITICAL_NESTED()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(state)     portEXIT_CRITICAL_NESTED(state)
-
-//Because the ROM routines don't necessarily handle a stack in external RAM correctly, we force
-//the stack memory to always be internal.
-#define pvPortMallocTcbMem(size) heap_caps_malloc(size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
-#define pvPortMallocStackMem(size)  heap_caps_malloc(size, MALLOC_CAP_INTERNAL|MALLOC_CAP_8BIT)
-
-//xTaskCreateStatic uses these functions to check incoming memory.
-#define portVALID_TCB_MEM(ptr) (esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr))
-#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
-#define portVALID_STACK_MEM(ptr) esp_ptr_byte_accessible(ptr)
-#else
-#define portVALID_STACK_MEM(ptr) (esp_ptr_internal(ptr) && esp_ptr_byte_accessible(ptr))
-#endif
-
-/*
- * Wrapper for the Xtensa compare-and-set instruction. This subroutine will atomically compare
- * *addr to 'compare'. If *addr == compare, *addr is set to *set. *set is updated with the previous
- * value of *addr (either 'compare' or some other value.)
- *
- * Warning: From the ISA docs: in some (unspecified) cases, the s32c1i instruction may return the
- * *bitwise inverse* of the old mem if the mem wasn't written. This doesn't seem to happen on the
- * ESP32 (portMUX assertions would fail).
- */
-static inline void uxPortCompareSet(volatile uint32_t *addr, uint32_t compare, uint32_t *set) {
-    __asm__ __volatile__ (
-        "WSR 	    %2,SCOMPARE1 \n"
-        "S32C1I     %0, %1, 0	 \n"
-        :"=r"(*set)
-        :"r"(addr), "r"(compare), "0"(*set)
-        );
-}
-
-void uxPortCompareSetExtram(volatile uint32_t *addr, uint32_t compare, uint32_t *set);
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			4
-#define portNOP()					XT_NOP()
-/*-----------------------------------------------------------*/
-
-/* Fine resolution time */
-#define portGET_RUN_TIME_COUNTER_VALUE()  xthal_get_ccount()
-//ccount or esp_timer are initialized elsewhere
-#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
-
-#ifdef CONFIG_FREERTOS_RUN_TIME_STATS_USING_ESP_TIMER
-/* Coarse resolution time (us) */
-#define portALT_GET_RUN_TIME_COUNTER_VALUE(x)    x = (uint32_t)esp_timer_get_time()
-#endif
-
-
-
-/* Kernel utilities. */
-void vPortYield( void );
-void _frxt_setup_switch( void );
-#define portYIELD()					vPortYield()
-#define portYIELD_FROM_ISR()        {traceISR_EXIT_TO_SCHEDULER(); _frxt_setup_switch();}
-
-static inline uint32_t xPortGetCoreID();
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-// When coprocessors are defined, we to maintain a pointer to coprocessors area.
-// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold:
-// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed.
-// The field is normally used for memory protection. FreeRTOS should create another general purpose field.
-typedef struct {
-	#if XCHAL_CP_NUM > 0
-	volatile StackType_t* coproc_area; // Pointer to coprocessor save area; MUST BE FIRST
-	#endif
-
-	#if portUSING_MPU_WRAPPERS
-	// Define here mpu_settings, which is port dependent
-	int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet
-	#endif
-
-	#if configUSE_TRACE_FACILITY_2
-	struct {
-		// Cf. porttraceStamp()
-		int taskstamp;        /* Stamp from inside task to see where we are */
-		int taskstampcount;   /* A counter usually incremented when we restart the task's loop */
-	} porttrace;
-	#endif
-} xMPU_SETTINGS;
-
-// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS)
-#if (XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2) && !portUSING_MPU_WRAPPERS   // If MPU wrappers not used, we still need to allocate coproc area
-	#undef portUSING_MPU_WRAPPERS
-	#define portUSING_MPU_WRAPPERS 1   // Enable it to allocate coproc area
-	#define MPU_WRAPPERS_H             // Override mpu_wrapper.h to disable unwanted code
-	#define PRIVILEGED_FUNCTION
-	#define PRIVILEGED_DATA
-#endif
-
-bool vApplicationSleep( TickType_t xExpectedIdleTime );
-
-#define portSUPPRESS_TICKS_AND_SLEEP( idleTime ) vApplicationSleep( idleTime )
-
-
-
-void _xt_coproc_release(volatile void * coproc_sa_base);
-
-
-/*
- * Map to the memory management routines required for the port.
- *
- * Note that libc standard malloc/free are also available for
- * non-FreeRTOS-specific code, and behave the same as
- * pvPortMalloc()/vPortFree().
- */
-#define pvPortMalloc heap_caps_malloc_default
-#define vPortFree heap_caps_free
-#define xPortGetFreeHeapSize esp_get_free_heap_size
-#define xPortGetMinimumEverFreeHeapSize esp_get_minimum_free_heap_size
-
-/*
- * Send an interrupt to another core in order to make the task running
- * on it yield for a higher-priority task.
- */
-
-void vPortYieldOtherCore( BaseType_t coreid) PRIVILEGED_FUNCTION;
-
-
-/*
- Callback to set a watchpoint on the end of the stack. Called every context switch to change the stack
- watchpoint around.
- */
-void vPortSetStackWatchpoint( void* pxStackStart );
-
-/*
- * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs
- * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway.
- */
-BaseType_t xPortInIsrContext();
-
-/*
- * This function will be called in High prio ISRs. Returns true if the current core was in ISR context
- * before calling into high prio ISR context.
- */
-BaseType_t xPortInterruptedFromISRContext();
-
-/*
- * The structures and methods of manipulating the MPU are contained within the
- * port layer.
- *
- * Fills the xMPUSettings structure with the memory region information
- * contained in xRegions.
- */
-#if( portUSING_MPU_WRAPPERS == 1 )
-    struct xMEMORY_REGION;
-    void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t usStackDepth ) PRIVILEGED_FUNCTION;
-    void vPortReleaseTaskMPUSettings( xMPU_SETTINGS *xMPUSettings );
-#endif
-
-/* Multi-core: get current core ID */
-static inline uint32_t IRAM_ATTR xPortGetCoreID() {
-    int id;
-    asm (
-        "rsr.prid %0\n"
-        " extui %0,%0,13,1"
-        :"=r"(id));
-    return id;
-}
-
-/* Get tick rate per second */
-uint32_t xPortGetTickRateHz(void);
-
-// porttrace
-#if configUSE_TRACE_FACILITY_2
-#include "porttrace.h"
-#endif
-
-// configASSERT_2 if requested
-#if configASSERT_2
-#include 
-void exit(int);
-#define configASSERT( x )   if (!(x)) { porttracePrint(-1); printf("\nAssertion failed in %s:%d\n", __FILE__, __LINE__); exit(-1); }
-#endif
-
-#endif // __ASSEMBLER__
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h
deleted file mode 100755
index 19630ce..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_api.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*******************************************************************************
-Copyright (c) 2006-2015 Cadence Design Systems Inc.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice shall be included
-in all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-******************************************************************************/
-
-/******************************************************************************
-  Xtensa-specific API for RTOS ports.
-******************************************************************************/
-
-#ifndef __XTENSA_API_H__
-#define __XTENSA_API_H__
-
-#include 
-
-#include "xtensa_context.h"
-
-
-/* Typedef for C-callable interrupt handler function */
-typedef void (*xt_handler)(void *);
-
-/* Typedef for C-callable exception handler function */
-typedef void (*xt_exc_handler)(XtExcFrame *);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to set a handler for the specified exception. The handler
-  will be installed on the core that calls this function.
-
-    n        - Exception number (type)
-    f        - Handler function address, NULL to uninstall handler.
-
-  The handler will be passed a pointer to the exception frame, which is created
-  on the stack of the thread that caused the exception.
-
-  If the handler returns, the thread context will be restored and the faulting
-  instruction will be retried. Any values in the exception frame that are
-  modified by the handler will be restored as part of the context. For details
-  of the exception frame structure see xtensa_context.h.
--------------------------------------------------------------------------------
-*/
-extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to set a handler for the specified interrupt. The handler
-  will be installed on the core that calls this function.
- 
-    n        - Interrupt number.
-    f        - Handler function address, NULL to uninstall handler.
-    arg      - Argument to be passed to handler.
--------------------------------------------------------------------------------
-*/
-extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to enable the specified interrupts on the core that runs
-  this code.
-
-    mask     - Bit mask of interrupts to be enabled.
--------------------------------------------------------------------------------
-*/
-extern void xt_ints_on(unsigned int mask);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to disable the specified interrupts on the core that runs
-  this code.
-
-    mask     - Bit mask of interrupts to be disabled.
--------------------------------------------------------------------------------
-*/
-extern void xt_ints_off(unsigned int mask);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to set the specified (s/w) interrupt.
--------------------------------------------------------------------------------
-*/
-static inline void xt_set_intset(unsigned int arg)
-{
-    xthal_set_intset(arg);
-}
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to clear the specified (s/w or edge-triggered)
-  interrupt.
--------------------------------------------------------------------------------
-*/
-static inline void xt_set_intclear(unsigned int arg)
-{
-    xthal_set_intclear(arg);
-}
-
-/*
--------------------------------------------------------------------------------
-  Call this function to get handler's argument for the specified interrupt.
- 
-    n        - Interrupt number.
--------------------------------------------------------------------------------
-*/
-extern void * xt_get_interrupt_handler_arg(int n);
-
-#endif /* __XTENSA_API_H__ */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h
deleted file mode 100755
index 58baee2..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_config.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*******************************************************************************
-// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-
-  Configuration-specific information for Xtensa build. This file must be
-  included in FreeRTOSConfig.h to properly set up the config-dependent
-  parameters correctly.
-
-  NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must
-  be defined to be > 0 somewhere above or on the command line.
-
-*******************************************************************************/
-
-#ifndef XTENSA_CONFIG_H
-#define XTENSA_CONFIG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include 
-#include 
-#include 	/* required for XSHAL_CLIB */
-
-#include "xtensa_context.h"
-
-
-/*-----------------------------------------------------------------------------
-*                                 STACK REQUIREMENTS
-*
-* This section defines the minimum stack size, and the extra space required to
-* be allocated for saving coprocessor state and/or C library state information
-* (if thread safety is enabled for the C library). The sizes are in bytes.
-*
-* Stack sizes for individual tasks should be derived from these minima based on
-* the maximum call depth of the task and the maximum level of interrupt nesting.
-* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
-* on the requirement for a task that calls nothing else but can be interrupted.
-* This assumes that interrupt handlers do not call more than a few levels deep.
-* If this is not true, i.e. one or more interrupt handlers make deep calls then
-* the minimum must be increased.
-*
-* If the Xtensa processor configuration includes coprocessors, then space is 
-* allocated to save the coprocessor state on the stack.
-*
-* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
-* is defined) then space is allocated to save the C library context in the TCB.
-* 
-* Allocating insufficient stack space is a common source of hard-to-find errors.
-* During development, it is best to enable the FreeRTOS stack checking features.
-*
-* Usage:
-* 
-* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
-*                            use of the C library. This will require extra stack
-*                            space to be allocated for tasks that use the C library
-*                            reentrant functions. See below for more information.
-* 
-* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
-* support thread safety. Check your core configuration to see which C library
-* was chosen for your system.
-* 
-* XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
-*                            that you do not use a stack smaller than this for any
-*                            task. In case you want to use stacks smaller than this
-*                            size, you must verify that the smaller size(s) will work
-*                            under all operating conditions.
-*
-* XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
-*                            that does not make C library reentrant calls. Add this
-*                            to the amount of stack space required by the task itself.
-*
-* XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
-*
------------------------------------------------------------------------------*/
-
-/* Extra space required for interrupt/exception hooks. */
-#ifdef XT_INTEXC_HOOKS
-  #ifdef __XTENSA_CALL0_ABI__
-    #define STK_INTEXC_EXTRA        0x200
-  #else
-    #define STK_INTEXC_EXTRA        0x180
-  #endif
-#else
-  #define STK_INTEXC_EXTRA          0
-#endif
-
-#define XT_CLIB_CONTEXT_AREA_SIZE         0
-
-/*------------------------------------------------------------------------------
-  Extra size -- interrupt frame plus coprocessor save area plus hook space.
-  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
-------------------------------------------------------------------------------*/
-#ifdef __XTENSA_CALL0_ABI__
-  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE)
-#else
-  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE)
-#endif
-
-/*------------------------------------------------------------------------------
-  Space allocated for user code -- function calls and local variables.
-  NOTE: This number can be adjusted to suit your needs. You must verify that the
-  amount of space you reserve is adequate for the worst-case conditions in your
-  application.
-  NOTE: The windowed ABI requires more stack, since space has to be reserved
-  for spilling register windows.
-------------------------------------------------------------------------------*/
-#ifdef __XTENSA_CALL0_ABI__
-  #define XT_USER_SIZE            0x200
-#else
-  #define XT_USER_SIZE            0x400
-#endif
-
-/* Minimum recommended stack size. */
-#define XT_STACK_MIN_SIZE         ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char))
-
-/* OS overhead with and without C library thread context. */
-#define XT_STACK_EXTRA            (XT_XTRA_SIZE)
-#define XT_STACK_EXTRA_CLIB       (XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE)
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XTENSA_CONFIG_H */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h
deleted file mode 100755
index 9e6fe55..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_context.h
+++ /dev/null
@@ -1,378 +0,0 @@
-/*******************************************************************************
-Copyright (c) 2006-2015 Cadence Design Systems Inc.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice shall be included
-in all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-
-        XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
-
-This header contains definitions and macros for use primarily by Xtensa
-RTOS assembly coded source files. It includes and uses the Xtensa hardware
-abstraction layer (HAL) to deal with config specifics. It may also be
-included in C source files.
-
-!! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
-
-NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
-
-*******************************************************************************/
-
-#ifndef XTENSA_CONTEXT_H
-#define XTENSA_CONTEXT_H
-
-#ifdef __ASSEMBLER__
-#include    
-#endif
-
-#include    
-#include    
-#include    
-#include 
-
-
-/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
-#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
-
-
-/*
--------------------------------------------------------------------------------
-  Macros that help define structures for both C and assembler.
--------------------------------------------------------------------------------
-*/
-
-#ifdef STRUCT_BEGIN
-#undef STRUCT_BEGIN
-#undef STRUCT_FIELD
-#undef STRUCT_AFIELD
-#undef STRUCT_END
-#endif
-
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-
-#define STRUCT_BEGIN            .pushsection .text; .struct 0
-#define STRUCT_FIELD(ctype,size,asname,name)    asname: .space  size
-#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space  (size)*(n)
-#define STRUCT_END(sname)       sname##Size:; .popsection
-
-#else
-
-#define STRUCT_BEGIN            typedef struct {
-#define STRUCT_FIELD(ctype,size,asname,name)    ctype   name;
-#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype   name[n];
-#define STRUCT_END(sname)       } sname;
-
-#endif //_ASMLANGUAGE || __ASSEMBLER__
-
-
-/*
--------------------------------------------------------------------------------
-  INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
-
-  A stack frame of this structure is allocated for any interrupt or exception.
-  It goes on the current stack. If the RTOS has a system stack for handling 
-  interrupts, every thread stack must allow space for just one interrupt stack 
-  frame, then nested interrupt stack frames go on the system stack.
-
-  The frame includes basic registers (explicit) and "extra" registers introduced 
-  by user TIE or the use of the MAC16 option in the user's Xtensa config.
-  The frame size is minimized by omitting regs not applicable to user's config.
-
-  For Windowed ABI, this stack frame includes the interruptee's base save area,
-  another base save area to manage gcc nested functions, and a little temporary 
-  space to help manage the spilling of the register windows.
--------------------------------------------------------------------------------
-*/
-
-STRUCT_BEGIN
-STRUCT_FIELD (long, 4, XT_STK_EXIT,     exit) /* exit point for dispatch */
-STRUCT_FIELD (long, 4, XT_STK_PC,       pc)   /* return PC */
-STRUCT_FIELD (long, 4, XT_STK_PS,       ps)   /* return PS */
-STRUCT_FIELD (long, 4, XT_STK_A0,       a0)
-STRUCT_FIELD (long, 4, XT_STK_A1,       a1)   /* stack pointer before interrupt */
-STRUCT_FIELD (long, 4, XT_STK_A2,       a2)
-STRUCT_FIELD (long, 4, XT_STK_A3,       a3)
-STRUCT_FIELD (long, 4, XT_STK_A4,       a4)
-STRUCT_FIELD (long, 4, XT_STK_A5,       a5)
-STRUCT_FIELD (long, 4, XT_STK_A6,       a6)
-STRUCT_FIELD (long, 4, XT_STK_A7,       a7)
-STRUCT_FIELD (long, 4, XT_STK_A8,       a8)
-STRUCT_FIELD (long, 4, XT_STK_A9,       a9)
-STRUCT_FIELD (long, 4, XT_STK_A10,      a10)
-STRUCT_FIELD (long, 4, XT_STK_A11,      a11)
-STRUCT_FIELD (long, 4, XT_STK_A12,      a12)
-STRUCT_FIELD (long, 4, XT_STK_A13,      a13)
-STRUCT_FIELD (long, 4, XT_STK_A14,      a14)
-STRUCT_FIELD (long, 4, XT_STK_A15,      a15)
-STRUCT_FIELD (long, 4, XT_STK_SAR,      sar)
-STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
-STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
-#if XCHAL_HAVE_LOOPS
-STRUCT_FIELD (long, 4, XT_STK_LBEG,   lbeg)
-STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
-STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
-#endif
-#ifndef __XTENSA_CALL0_ABI__
-/* Temporary space for saving stuff during window spill */
-STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
-STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
-STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
-#endif
-#ifdef XT_USE_SWPRI
-/* Storage for virtual priority mask */
-STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)
-#endif
-#ifdef XT_USE_OVLY
-/* Storage for overlay state */
-STRUCT_FIELD (long, 4, XT_STK_OVLY,   ovly)
-#endif
-STRUCT_END(XtExcFrame)
-
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-#define XT_STK_NEXT1      XtExcFrameSize
-#else
-#define XT_STK_NEXT1      sizeof(XtExcFrame)
-#endif
-
-/* Allocate extra storage if needed */
-#if XCHAL_EXTRA_SA_SIZE != 0
-
-#if XCHAL_EXTRA_SA_ALIGN <= 16
-#define XT_STK_EXTRA            ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
-#else
-/* If need more alignment than stack, add space for dynamic alignment */
-#define XT_STK_EXTRA            (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
-#endif
-#define XT_STK_NEXT2            (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
-
-#else
-
-#define XT_STK_NEXT2            XT_STK_NEXT1   
-
-#endif
-
-/*
--------------------------------------------------------------------------------
-  This is the frame size. Add space for 4 registers (interruptee's base save
-  area) and some space for gcc nested functions if any.
--------------------------------------------------------------------------------
-*/
-#define XT_STK_FRMSZ            (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
-
-
-/*
--------------------------------------------------------------------------------
-  SOLICITED STACK FRAME FOR A THREAD
-
-  A stack frame of this structure is allocated whenever a thread enters the 
-  RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
-  It goes on the current thread's stack.
-
-  The solicited frame only includes registers that are required to be preserved
-  by the callee according to the compiler's ABI conventions, some space to save 
-  the return address for returning to the caller, and the caller's PS register.
-
-  For Windowed ABI, this stack frame includes the caller's base save area.
-
-  Note on XT_SOL_EXIT field:
-      It is necessary to distinguish a solicited from an interrupt stack frame.
-      This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
-      always at the same offset (0). It can be written with a code (usually 0) 
-      to distinguish a solicted frame from an interrupt frame. An RTOS port may
-      opt to ignore this field if it has another way of distinguishing frames.
--------------------------------------------------------------------------------
-*/
-
-STRUCT_BEGIN
-#ifdef __XTENSA_CALL0_ABI__
-STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
-STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
-STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
-STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
-STRUCT_FIELD (long, 4, XT_SOL_A12,  a12)    /* should be on 16-byte alignment */
-STRUCT_FIELD (long, 4, XT_SOL_A13,  a13)
-STRUCT_FIELD (long, 4, XT_SOL_A14,  a14)
-STRUCT_FIELD (long, 4, XT_SOL_A15,  a15)
-#else
-STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
-STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
-STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
-STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
-STRUCT_FIELD (long, 4, XT_SOL_A0,   a0)    /* should be on 16-byte alignment */
-STRUCT_FIELD (long, 4, XT_SOL_A1,   a1)
-STRUCT_FIELD (long, 4, XT_SOL_A2,   a2)
-STRUCT_FIELD (long, 4, XT_SOL_A3,   a3)
-#endif
-STRUCT_END(XtSolFrame)
-
-/* Size of solicited stack frame */
-#define XT_SOL_FRMSZ            ALIGNUP(0x10, XtSolFrameSize)
-
-
-/*
--------------------------------------------------------------------------------
-  CO-PROCESSOR STATE SAVE AREA FOR A THREAD
-
-  The RTOS must provide an area per thread to save the state of co-processors
-  when that thread does not have control. Co-processors are context-switched
-  lazily (on demand) only when a new thread uses a co-processor instruction,
-  otherwise a thread retains ownership of the co-processor even when it loses
-  control of the processor. An Xtensa co-processor exception is triggered when
-  any co-processor instruction is executed by a thread that is not the owner,
-  and the context switch of that co-processor is then peformed by the handler.
-  Ownership represents which thread's state is currently in the co-processor.
-
-  Co-processors may not be used by interrupt or exception handlers. If an 
-  co-processor instruction is executed by an interrupt or exception handler,
-  the co-processor exception handler will trigger a kernel panic and freeze.
-  This restriction is introduced to reduce the overhead of saving and restoring
-  co-processor state (which can be quite large) and in particular remove that
-  overhead from interrupt handlers.
-
-  The co-processor state save area may be in any convenient per-thread location
-  such as in the thread control block or above the thread stack area. It need
-  not be in the interrupt stack frame since interrupts don't use co-processors.
-
-  Along with the save area for each co-processor, two bitmasks with flags per 
-  co-processor (laid out as in the CPENABLE reg) help manage context-switching
-  co-processors as efficiently as possible:
-
-  XT_CPENABLE
-    The contents of a non-running thread's CPENABLE register.
-    It represents the co-processors owned (and whose state is still needed)
-    by the thread. When a thread is preempted, its CPENABLE is saved here.
-    When a thread solicits a context-swtich, its CPENABLE is cleared - the
-    compiler has saved the (caller-saved) co-proc state if it needs to.
-    When a non-running thread loses ownership of a CP, its bit is cleared.
-    When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
-    Avoids co-processor exceptions when no change of ownership is needed.
-
-  XT_CPSTORED
-    A bitmask with the same layout as CPENABLE, a bit per co-processor.
-    Indicates whether the state of each co-processor is saved in the state 
-    save area. When a thread enters the kernel, only the state of co-procs
-    still enabled in CPENABLE is saved. When the co-processor exception 
-    handler assigns ownership of a co-processor to a thread, it restores 
-    the saved state only if this bit is set, and clears this bit.
-
-  XT_CP_CS_ST
-    A bitmask with the same layout as CPENABLE, a bit per co-processor.
-    Indicates whether callee-saved state is saved in the state save area.
-    Callee-saved state is saved by itself on a solicited context switch,
-    and restored when needed by the coprocessor exception handler.
-    Unsolicited switches will cause the entire coprocessor to be saved
-    when necessary.
-
-  XT_CP_ASA
-    Pointer to the aligned save area.  Allows it to be aligned more than
-    the overall save area (which might only be stack-aligned or TCB-aligned).
-    Especially relevant for Xtensa cores configured with a very large data
-    path that requires alignment greater than 16 bytes (ABI stack alignment).
--------------------------------------------------------------------------------
-*/
-
-#if XCHAL_CP_NUM > 0
-
-/*  Offsets of each coprocessor save area within the 'aligned save area':  */
-#define XT_CP0_SA   0
-#define XT_CP1_SA   ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
-#define XT_CP2_SA   ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
-#define XT_CP3_SA   ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
-#define XT_CP4_SA   ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
-#define XT_CP5_SA   ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
-#define XT_CP6_SA   ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
-#define XT_CP7_SA   ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
-#define XT_CP_SA_SIZE   ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
-
-/*  Offsets within the overall save area:  */
-#define XT_CPENABLE 0   /* (2 bytes) coprocessors active for this thread */
-#define XT_CPSTORED 2   /* (2 bytes) coprocessors saved for this thread */
-#define XT_CP_CS_ST 4   /* (2 bytes) coprocessor callee-saved regs stored for this thread */
-#define XT_CP_ASA   8   /* (4 bytes) ptr to aligned save area */
-/*  Overall size allows for dynamic alignment:  */
-#define XT_CP_SIZE  (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
-#else
-#define XT_CP_SIZE  0
-#endif
-
-
-/*
- Macro to get the current core ID. Only uses the reg given as an argument.
- Reading PRID on the ESP32 gives us 0xCDCD on the PRO processor (0)
- and 0xABAB on the APP CPU (1). We can distinguish between the two by checking
- bit 13: it's 1 on the APP and 0 on the PRO processor.
-*/
-#ifdef __ASSEMBLER__
-	.macro getcoreid reg
-	rsr.prid \reg
-	extui \reg,\reg,13,1
-	.endm
-#endif
-
-#define CORE_ID_PRO 0xCDCD
-#define CORE_ID_APP 0xABAB
-
-/*
--------------------------------------------------------------------------------
-  MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
-
-  Convenient where the frame size requirements are the same for both ABIs.
-    ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
-    ENTRY0,    RET0    are for frameless functions (no locals, no calls).
-
-  where size = size of stack frame in bytes (must be >0 and aligned to 16).
-  For framed functions the frame is created and the return address saved at
-  base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
-  For frameless functions, there is no frame and return address remains in a0.
-  Note: Because CPP macros expand to a single line, macros requiring multi-line 
-  expansions are implemented as assembler macros.
--------------------------------------------------------------------------------
-*/
-
-#ifdef __ASSEMBLER__
-#ifdef __XTENSA_CALL0_ABI__
-  /* Call0 */
-  #define ENTRY(sz)     entry1  sz
-    .macro  entry1 size=0x10
-    addi    sp, sp, -\size
-    s32i    a0, sp, 0
-    .endm
-  #define ENTRY0      
-  #define RET(sz)       ret1    sz
-    .macro  ret1 size=0x10
-    l32i    a0, sp, 0
-    addi    sp, sp, \size
-    ret
-    .endm
-  #define RET0          ret
-#else
-  /* Windowed */
-  #define ENTRY(sz)     entry   sp, sz
-  #define ENTRY0        entry   sp, 0x10
-  #define RET(sz)       retw
-  #define RET0          retw
-#endif
-#endif
-
-
-
-
-
-#endif /* XTENSA_CONTEXT_H */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h
deleted file mode 100755
index 25d42da..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_rtos.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/*******************************************************************************
-// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-
-        RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
-                            (FreeRTOS Port)
-
-This header is the primary glue between generic Xtensa RTOS support
-sources and a specific RTOS port for Xtensa.  It contains definitions
-and macros for use primarily by Xtensa assembly coded source files.
-
-Macros in this header map callouts from generic Xtensa files to specific
-RTOS functions. It may also be included in C source files.
-
-Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa 
-architecture, using the Xtensa hardware abstraction layer (HAL) to deal 
-with configuration specifics.
-
-Should be included by all Xtensa generic and RTOS port-specific sources.
-
-*******************************************************************************/
-
-#ifndef XTENSA_RTOS_H
-#define XTENSA_RTOS_H
-
-#ifdef __ASSEMBLER__
-#include    
-#else
-#include    
-#endif
-
-#include    
-#include    
-
-/*
-Include any RTOS specific definitions that are needed by this header.
-*/
-#include    "FreeRTOSConfig.h"
-
-/*
-Convert FreeRTOSConfig definitions to XTENSA definitions.
-However these can still be overridden from the command line.
-*/
-
-#ifndef XT_SIMULATOR
-  #if configXT_SIMULATOR
-    #define XT_SIMULATOR             1  /* Simulator mode */
-  #endif
-#endif
-
-#ifndef XT_BOARD
-  #if configXT_BOARD
-    #define XT_BOARD                 1  /* Board mode */
-  #endif
-#endif
-
-#ifndef XT_TIMER_INDEX
-  #if defined configXT_TIMER_INDEX
-    #define XT_TIMER_INDEX           configXT_TIMER_INDEX  /* Index of hardware timer to be used */
-  #endif
-#endif
-
-#ifndef XT_INTEXC_HOOKS
-  #if configXT_INTEXC_HOOKS
-    #define XT_INTEXC_HOOKS          1  /* Enables exception hooks */
-  #endif
-#endif
-
-#if !defined(XT_SIMULATOR) && !defined(XT_BOARD)
-  #error Either XT_SIMULATOR or XT_BOARD must be defined.
-#endif
-
-
-/*
-Name of RTOS (for messages).
-*/
-#define XT_RTOS_NAME    FreeRTOS
-
-/*
-Check some Xtensa configuration requirements and report error if not met.
-Error messages can be customize to the RTOS port.
-*/
-
-#if !XCHAL_HAVE_XEA2
-#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
-#endif
-
-
-/*******************************************************************************
-
-RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
-
-Define callout macros used in generic Xtensa code to interact with the RTOS.
-The macros are simply the function names for use in calls from assembler code.
-Some of these functions may call back to generic functions in xtensa_context.h .
-
-*******************************************************************************/
-
-/*
-Inform RTOS of entry into an interrupt handler that will affect it. 
-Allows RTOS to manage switch to any system stack and count nesting level.
-Called after minimal context has been saved, with interrupts disabled.
-RTOS port can call0 _xt_context_save to save the rest of the context.
-May only be called from assembly code by the 'call0' instruction.
-*/
-// void XT_RTOS_INT_ENTER(void)
-#define XT_RTOS_INT_ENTER   _frxt_int_enter
-
-/*
-Inform RTOS of completion of an interrupt handler, and give control to
-RTOS to perform thread/task scheduling, switch back from any system stack
-and restore the context, and return to the exit dispatcher saved in the
-stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
-to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
-leaving only a minimal part of the context to be restored by the exit
-dispatcher. This function does not return to the place it was called from.
-May only be called from assembly code by the 'call0' instruction.
-*/
-// void XT_RTOS_INT_EXIT(void)
-#define XT_RTOS_INT_EXIT    _frxt_int_exit
-
-/*
-Inform RTOS of the occurrence of a tick timer interrupt.
-If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
-May be coded in or called from C or assembly, per ABI conventions.
-RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
-*/
-// void XT_RTOS_TIMER_INT(void)
-#define XT_RTOS_TIMER_INT   _frxt_timer_int
-#define XT_TICK_PER_SEC     configTICK_RATE_HZ
-
-/*
-Return in a15 the base address of the co-processor state save area for the 
-thread that triggered a co-processor exception, or 0 if no thread was running.
-The state save area is structured as defined in xtensa_context.h and has size 
-XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
-in interrupt handlers or the RTOS kernel. May only be called from assembly code
-and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. 
-The implementation may use only a2-4, a15 (all other regs must be preserved).
-*/
-// void* XT_RTOS_CP_STATE(void)
-#define XT_RTOS_CP_STATE    _frxt_task_coproc_state
-
-
-/*******************************************************************************
-
-HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
-
-This Xtensa RTOS port provides hooks for dynamically installing exception
-and interrupt handlers to facilitate automated testing where each test
-case can install its own handler for user exceptions and each interrupt
-priority (level). This consists of an array of function pointers indexed
-by interrupt priority, with index 0 being the user exception handler hook.
-Each entry in the array is initially 0, and may be replaced by a function 
-pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
-
-The handler for low and medium priority obeys ABI conventions so may be coded
-in C. For the exception handler, the cause is the contents of the EXCCAUSE
-reg, and the result is -1 if handled, else the cause (still needs handling).
-For interrupt handlers, the cause is a mask of pending enabled interrupts at
-that level, and the result is the same mask with the bits for the handled
-interrupts cleared (those not cleared still need handling). This allows a test
-case to either pre-handle or override the default handling for the exception
-or interrupt level (see xtensa_vectors.S).
-
-High priority handlers (including NMI) must be coded in assembly, are always
-called by 'call0' regardless of ABI, must preserve all registers except a0,
-and must not use or modify the interrupted stack. The hook argument 'cause'
-is not passed and the result is ignored, so as not to burden the caller with
-saving and restoring a2 (it assumes only one interrupt per level - see the
-discussion in high priority interrupts in xtensa_vectors.S). The handler
-therefore should be coded to prototype 'void h(void)' even though it plugs
-into an array of handlers of prototype 'unsigned h(unsigned)'.
-
-To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
-
-*******************************************************************************/
-
-#define XT_INTEXC_HOOK_NUM  (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
-
-#ifndef __ASSEMBLER__
-typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause);
-extern  volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
-#endif
-
-
-/*******************************************************************************
-
-CONVENIENCE INCLUSIONS.
-
-Ensures RTOS specific files need only include this one Xtensa-generic header.
-These headers are included last so they can use the RTOS definitions above.
-
-*******************************************************************************/
-
-#include    "xtensa_context.h"
-
-#ifdef XT_RTOS_TIMER_INT
-#include    "xtensa_timer.h"
-#endif
-
-
-/*******************************************************************************
-
-Xtensa Port Version.
-
-*******************************************************************************/
-
-#define XTENSA_PORT_VERSION             1.4.2
-#define XTENSA_PORT_VERSION_STRING      "1.4.2"
-
-#endif /* XTENSA_RTOS_H */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h
deleted file mode 100755
index fa4f960..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/include/xtensa_timer.h
+++ /dev/null
@@ -1,159 +0,0 @@
-/*******************************************************************************
-// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-
-        XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
-
-This header contains definitions and macros for use primarily by Xtensa
-RTOS assembly coded source files. It includes and uses the Xtensa hardware
-abstraction layer (HAL) to deal with config specifics. It may also be
-included in C source files.
-
-User may edit to modify timer selection and to specify clock frequency and
-tick duration to match timer interrupt to the real-time tick duration.
-
-If the RTOS has no timer interrupt, then there is no tick timer and the
-clock frequency is irrelevant, so all of these macros are left undefined
-and the Xtensa core configuration need not have a timer.
-
-*******************************************************************************/
-
-#ifndef XTENSA_TIMER_H
-#define XTENSA_TIMER_H
-
-#ifdef __ASSEMBLER__
-#include    
-#endif
-
-#include    
-#include    
-
-#include    "xtensa_rtos.h"     /* in case this wasn't included directly */
-
-#include    "FreeRTOSConfig.h"
-
-/*
-Select timer to use for periodic tick, and determine its interrupt number 
-and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
-in which case its validity is checked (it must exist in this core and must 
-not be on a high priority interrupt - an error will be reported in invalid).
-Otherwise select the first low or medium priority interrupt timer available.
-*/
-#if XCHAL_NUM_TIMERS == 0
-
-  #error "This Xtensa configuration is unsupported, it has no timers."
-
-#else
-
-#ifndef XT_TIMER_INDEX
-  #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    3
-    #endif
-  #endif
-  #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    2
-    #endif
-  #endif
-  #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    1
-    #endif
-  #endif
-  #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    0
-    #endif
-  #endif
-#endif
-#ifndef XT_TIMER_INDEX
-  #error "There is no suitable timer in this Xtensa configuration."
-#endif
-
-#define XT_CCOMPARE             (CCOMPARE + XT_TIMER_INDEX)
-#define XT_TIMER_INTNUM         XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
-#define XT_TIMER_INTPRI         XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
-#define XT_TIMER_INTEN          (1 << XT_TIMER_INTNUM)
-
-#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
-  #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
-#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
-  #error "The timer interrupt cannot be high priority (use medium or low)."
-#endif
-
-#endif /* XCHAL_NUM_TIMERS */
-
-/*
-Set processor clock frequency, used to determine clock divisor for timer tick.
-User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
-If using a supported board via the board-independent API defined in xtbsp.h,
-this may be left undefined and frequency and tick divisor will be computed 
-and cached during run-time initialization.
-
-NOTE ON SIMULATOR:
-Under the Xtensa instruction set simulator, the frequency can only be estimated 
-because it depends on the speed of the host and the version of the simulator.
-Also because it runs much slower than hardware, it is not possible to achieve
-real-time performance for most applications under the simulator. A frequency
-too low does not allow enough time between timer interrupts, starving threads.
-To obtain a more convenient but non-real-time tick duration on the simulator, 
-compile with xt-xcc option "-DXT_SIMULATOR".
-Adjust this frequency to taste (it's not real-time anyway!).
-*/
-#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
-#define XT_CLOCK_FREQ       configCPU_CLOCK_HZ
-#endif
-
-#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
-  #error "XT_CLOCK_FREQ must be defined for the target platform."
-#endif
-
-/*
-Default number of timer "ticks" per second (default 100 for 10ms tick).
-RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
-User may redefine this to an optimal value for the application, either by
-editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
-"-DXT_TICK_PER_SEC=" where  is a suitable number.
-*/
-#ifndef XT_TICK_PER_SEC
-#define XT_TICK_PER_SEC    configTICK_RATE_HZ        /* 10 ms tick = 100 ticks per second */
-#endif
-
-/*
-Derivation of clock divisor for timer tick and interrupt (one per tick).
-*/
-#ifdef XT_CLOCK_FREQ
-#define XT_TICK_DIVISOR     (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
-#endif
-
-#ifndef __ASSEMBLER__
-extern unsigned _xt_tick_divisor;
-extern void     _xt_tick_divisor_init(void);
-#endif
-
-#endif  /* XTENSA_TIMER_H */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port.c b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
deleted file mode 100755
index bdf74d3..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/port.c
+++ /dev/null
@@ -1,428 +0,0 @@
-/*
-    FreeRTOS V8.2.0 - Copyright (C) 2015 Real Time Engineers Ltd.
-    All rights reserved
-
-    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
-
-    This file is part of the FreeRTOS distribution.
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-
-    ***************************************************************************
-     *                                                                       *
-     *    FreeRTOS provides completely free yet professionally developed,    *
-     *    robust, strictly quality controlled, supported, and cross          *
-     *    platform software that is more than just the market leader, it     *
-     *    is the industry's de facto standard.                               *
-     *                                                                       *
-     *    Help yourself get started quickly while simultaneously helping     *
-     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
-     *    tutorial book, reference manual, or both:                          *
-     *    http://www.FreeRTOS.org/Documentation                              *
-     *                                                                       *
-    ***************************************************************************
-
-    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
-	the FAQ page "My application does not run, what could be wrong?".  Have you
-	defined configASSERT()?
-
-	http://www.FreeRTOS.org/support - In return for receiving this top quality
-	embedded software for free we request you assist our global community by
-	participating in the support forum.
-
-	http://www.FreeRTOS.org/training - Investing in training allows your team to
-	be as productive as possible as early as possible.  Now you can receive
-	FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
-	Ltd, and the world's leading authority on the world's leading RTOS.
-
-    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
-    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
-    compatible FAT file system, and our tiny thread aware UDP/IP stack.
-
-    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
-    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
-
-    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
-    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
-    licenses offer ticketed support, indemnification and commercial middleware.
-
-    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
-    engineered and independently SIL3 certified version for use in safety and
-    mission critical applications that require provable dependability.
-
-    1 tab == 4 spaces!
-*/
-
-/*******************************************************************************
-// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-*/
-
-#include 
-#include 
-
-#include "xtensa_rtos.h"
-
-#include "rom/ets_sys.h"
-#include "soc/cpu.h"
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-#include "esp_panic.h"
-#include "esp_heap_caps.h"
-#include "esp_crosscore_int.h"
-
-#include "esp_intr_alloc.h"
-
-/* Defined in portasm.h */
-extern void _frxt_tick_timer_init(void);
-
-/* Defined in xtensa_context.S */
-extern void _xt_coproc_init(void);
-
-
-#if CONFIG_FREERTOS_CORETIMER_0
-    #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER0_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
-#endif
-#if CONFIG_FREERTOS_CORETIMER_1
-    #define SYSTICK_INTR_ID (ETS_INTERNAL_TIMER1_INTR_SOURCE+ETS_INTERNAL_INTR_SOURCE_OFF)
-#endif
-
-/*-----------------------------------------------------------*/
-
-unsigned port_xSchedulerRunning[portNUM_PROCESSORS] = {0}; // Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting
-unsigned port_interruptNesting[portNUM_PROCESSORS] = {0};  // Interrupt nesting level. Increased/decreased in portasm.c, _frxt_int_enter/_frxt_int_exit
-
-/*-----------------------------------------------------------*/
-
-// User exception dispatcher when exiting
-void _xt_user_exit(void);
-
-/*
- * Stack initialization
- */
-#if portUSING_MPU_WRAPPERS
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
-#else
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-#endif
-{
-	StackType_t *sp, *tp;
-	XtExcFrame  *frame;
-	#if XCHAL_CP_NUM > 0
-	uint32_t *p;
-	#endif
-
-	/* Create interrupt stack frame aligned to 16 byte boundary */
-	sp = (StackType_t *) (((UBaseType_t)(pxTopOfStack + 1) - XT_CP_SIZE - XT_STK_FRMSZ) & ~0xf);
-
-	/* Clear the entire frame (do not use memset() because we don't depend on C library) */
-	for (tp = sp; tp <= pxTopOfStack; ++tp)
-		*tp = 0;
-
-	frame = (XtExcFrame *) sp;
-
-	/* Explicitly initialize certain saved registers */
-	frame->pc   = (UBaseType_t) pxCode;             /* task entrypoint                */
-	frame->a0   = 0;                                /* to terminate GDB backtrace     */
-	frame->a1   = (UBaseType_t) sp + XT_STK_FRMSZ;  /* physical top of stack frame    */
-	frame->exit = (UBaseType_t) _xt_user_exit;      /* user exception exit dispatcher */
-
-	/* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
-	/* Also set entry point argument parameter. */
-	#ifdef __XTENSA_CALL0_ABI__
-	frame->a2 = (UBaseType_t) pvParameters;
-	frame->ps = PS_UM | PS_EXCM;
-	#else
-	/* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
-	frame->a6 = (UBaseType_t) pvParameters;
-	frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1);
-	#endif
-
-	#ifdef XT_USE_SWPRI
-	/* Set the initial virtual priority mask value to all 1's. */
-	frame->vpri = 0xFFFFFFFF;
-	#endif
-
-	#if XCHAL_CP_NUM > 0
-	/* Init the coprocessor save area (see xtensa_context.h) */
-	/* No access to TCB here, so derive indirectly. Stack growth is top to bottom.
-         * //p = (uint32_t *) xMPUSettings->coproc_area;
-	 */
-	p = (uint32_t *)(((uint32_t) pxTopOfStack - XT_CP_SIZE) & ~0xf);
-	p[0] = 0;
-	p[1] = 0;
-	p[2] = (((uint32_t) p) + 12 + XCHAL_TOTAL_SA_ALIGN - 1) & -XCHAL_TOTAL_SA_ALIGN;
-	#endif
-
-	return sp;
-}
-
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the Xtensa port will get stopped.  If required simply
-	disable the tick interrupt here. */
-}
-
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	// Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored
-
-	#if XCHAL_CP_NUM > 0
-	/* Initialize co-processor management for tasks. Leave CPENABLE alone. */
-	_xt_coproc_init();
-	#endif
-
-	/* Init the tick divisor value */
-	_xt_tick_divisor_init();
-
-	/* Setup the hardware to generate the tick. */
-	_frxt_tick_timer_init();
-
-	port_xSchedulerRunning[xPortGetCoreID()] = 1;
-
-	// Cannot be directly called from C; never returns
-	__asm__ volatile ("call0    _frxt_dispatch\n");
-
-	/* Should not get here. */
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortSysTickHandler( void )
-{
-	BaseType_t ret;
-	unsigned interruptMask;
-
-	portbenchmarkIntLatency();
-	traceISR_ENTER(SYSTICK_INTR_ID);
-
-	/* Interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY must be
-	 * disabled before calling xTaskIncrementTick as it access the
-	 * kernel lists. */
-	interruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		ret = xTaskIncrementTick();
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( interruptMask );
-
-	if( ret != pdFALSE )
-	{
-		portYIELD_FROM_ISR();
-	} else {
-		traceISR_EXIT();
-	}
-	return ret;
-}
-
-
-void vPortYieldOtherCore( BaseType_t coreid ) {
-	esp_crosscore_int_send_yield( coreid );
-}
-
-/*-----------------------------------------------------------*/
-
-/*
- * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
- */
-#if portUSING_MPU_WRAPPERS
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t usStackDepth )
-{
-	#if XCHAL_CP_NUM > 0
-	xMPUSettings->coproc_area = (StackType_t*)((((uint32_t)(pxBottomOfStack + usStackDepth - 1)) - XT_CP_SIZE ) & ~0xf);
-
-
-	/* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
-         * clear the stack area after we return. This is done in pxPortInitialiseStack().
-	 */
-	#endif
-}
-
-void vPortReleaseTaskMPUSettings( xMPU_SETTINGS *xMPUSettings )
-{
-	/* If task has live floating point registers somewhere, release them */
-	_xt_coproc_release( xMPUSettings->coproc_area );
-}
-
-#endif
-
-/*
- * Returns true if the current core is in ISR context; low prio ISR, med prio ISR or timer tick ISR. High prio ISRs
- * aren't detected here, but they normally cannot call C code, so that should not be an issue anyway.
- */
-BaseType_t xPortInIsrContext()
-{
-	unsigned int irqStatus;
-	BaseType_t ret;
-	irqStatus=portENTER_CRITICAL_NESTED();
-	ret=(port_interruptNesting[xPortGetCoreID()] != 0);
-	portEXIT_CRITICAL_NESTED(irqStatus);
-	return ret;
-}
-
-/*
- * This function will be called in High prio ISRs. Returns true if the current core was in ISR context
- * before calling into high prio ISR context.
- */
-BaseType_t IRAM_ATTR xPortInterruptedFromISRContext()
-{
-	return (port_interruptNesting[xPortGetCoreID()] != 0);
-}
-
-void vPortAssertIfInISR()
-{
-	if (xPortInIsrContext()) {
-		ets_printf("core=%d port_interruptNesting=%d\n\n", xPortGetCoreID(), port_interruptNesting[xPortGetCoreID()]);
-	}
-	configASSERT(!xPortInIsrContext());
-}
-
-/*
- * For kernel use: Initialize a per-CPU mux. Mux will be initialized unlocked.
- */
-void vPortCPUInitializeMutex(portMUX_TYPE *mux) {
-
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-	ets_printf("Initializing mux %p\n", mux);
-	mux->lastLockedFn="(never locked)";
-	mux->lastLockedLine=-1;
-#endif
-	mux->owner=portMUX_FREE_VAL;
-	mux->count=0;
-}
-
-#include "portmux_impl.h"
-
-/*
- * For kernel use: Acquire a per-CPU mux. Spinlocks, so don't hold on to these muxes for too long.
- */
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-void vPortCPUAcquireMutex(portMUX_TYPE *mux, const char *fnName, int line) {
-	unsigned int irqStatus = portENTER_CRITICAL_NESTED();
-	vPortCPUAcquireMutexIntsDisabled(mux, portMUX_NO_TIMEOUT, fnName, line);
-	portEXIT_CRITICAL_NESTED(irqStatus);
-}
-
-bool vPortCPUAcquireMutexTimeout(portMUX_TYPE *mux, int timeout_cycles, const char *fnName, int line) {
-	unsigned int irqStatus = portENTER_CRITICAL_NESTED();
-	bool result = vPortCPUAcquireMutexIntsDisabled(mux, timeout_cycles, fnName, line);
-	portEXIT_CRITICAL_NESTED(irqStatus);
-	return result;
-}
-
-#else
-void vPortCPUAcquireMutex(portMUX_TYPE *mux) {
-	unsigned int irqStatus = portENTER_CRITICAL_NESTED();
-	vPortCPUAcquireMutexIntsDisabled(mux, portMUX_NO_TIMEOUT);
-	portEXIT_CRITICAL_NESTED(irqStatus);
-}
-
-bool vPortCPUAcquireMutexTimeout(portMUX_TYPE *mux, int timeout_cycles) {
-	unsigned int irqStatus = portENTER_CRITICAL_NESTED();
-	bool result = vPortCPUAcquireMutexIntsDisabled(mux, timeout_cycles);
-	portEXIT_CRITICAL_NESTED(irqStatus);
-	return result;
-}
-#endif
-
-
-/*
- * For kernel use: Release a per-CPU mux
- *
- * Mux must be already locked by this core
- */
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-void vPortCPUReleaseMutex(portMUX_TYPE *mux, const char *fnName, int line) {
-	unsigned int irqStatus = portENTER_CRITICAL_NESTED();
-	vPortCPUReleaseMutexIntsDisabled(mux, fnName, line);
-	portEXIT_CRITICAL_NESTED(irqStatus);
-}
-#else
-void vPortCPUReleaseMutex(portMUX_TYPE *mux) {
-	unsigned int irqStatus = portENTER_CRITICAL_NESTED();
-	vPortCPUReleaseMutexIntsDisabled(mux);
-	portEXIT_CRITICAL_NESTED(irqStatus);
-}
-#endif
-
-void vPortSetStackWatchpoint( void* pxStackStart ) {
-	//Set watchpoint 1 to watch the last 32 bytes of the stack.
-	//Unfortunately, the Xtensa watchpoints can't set a watchpoint on a random [base - base+n] region because
-	//the size works by masking off the lowest address bits. For that reason, we futz a bit and watch the lowest 32
-	//bytes of the stack we can actually watch. In general, this can cause the watchpoint to be triggered at most
-	//28 bytes early. The value 32 is chosen because it's larger than the stack canary, which in FreeRTOS is 20 bytes.
-	//This way, we make sure we trigger before/when the stack canary is corrupted, not after.
-	int addr=(int)pxStackStart;
-	addr=(addr+31)&(~31);
-	esp_set_watchpoint(1, (char*)addr, 32, ESP_WATCHPOINT_STORE);
-}
-
-#if defined(CONFIG_SPIRAM_SUPPORT)
-/*
- * Compare & set (S32C1) does not work in external RAM. Instead, this routine uses a mux (in internal memory) to fake it.
- */
-static portMUX_TYPE extram_mux = portMUX_INITIALIZER_UNLOCKED;
-
-void uxPortCompareSetExtram(volatile uint32_t *addr, uint32_t compare, uint32_t *set) {
-	uint32_t prev;
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-	vPortCPUAcquireMutexIntsDisabled(&extram_mux, portMUX_NO_TIMEOUT, __FUNCTION__, __LINE__);
-#else
-	vPortCPUAcquireMutexIntsDisabled(&extram_mux, portMUX_NO_TIMEOUT); 
-#endif
-	prev=*addr;
-	if (prev==compare) {
-		*addr=*set;
-	}
-	*set=prev;
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-	vPortCPUReleaseMutexIntsDisabled(&extram_mux, __FUNCTION__, __LINE__);
-#else
-	vPortCPUReleaseMutexIntsDisabled(&extram_mux);
-#endif
-}
-#endif //defined(CONFIG_SPIRAM_SUPPORT)
-
-
-
-uint32_t xPortGetTickRateHz(void) {
-	return (uint32_t)configTICK_RATE_HZ;
-}
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S
deleted file mode 100755
index f5b280f..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portasm.S
+++ /dev/null
@@ -1,653 +0,0 @@
-/*
-//-----------------------------------------------------------------------------
-// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-//-----------------------------------------------------------------------------
-*/
-
-#include "xtensa_rtos.h"
-#include "sdkconfig.h"
-
-#define TOPOFSTACK_OFFS                 0x00    /* StackType_t *pxTopOfStack */
-#define CP_TOPOFSTACK_OFFS              0x04    /* xMPU_SETTINGS.coproc_area */
-
-.extern pxCurrentTCB
-
-/*
-*******************************************************************************
-* Interrupt stack. The size of the interrupt stack is determined by the config
-* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h
-*******************************************************************************
-*/
-
-    .data
-    .align      16
-    .global     port_IntStack
-    .global     port_IntStackTop
-    .global     port_switch_flag
-port_IntStack:
-    .space      configISR_STACK_SIZE*portNUM_PROCESSORS		/* This allocates stacks for each individual CPU. */
-port_IntStackTop:
-    .word		0
-port_switch_flag:
-    .space      portNUM_PROCESSORS*4 /* One flag for each individual CPU. */
-
-    .text
-
-/*
-*******************************************************************************
-* _frxt_setup_switch
-* void _frxt_setup_switch(void);
-* 
-* Sets an internal flag indicating that a task switch is required on return
-* from interrupt handling.
-* 
-*******************************************************************************
-*/
-    .global     _frxt_setup_switch
-    .type       _frxt_setup_switch,@function
-    .align      4
-_frxt_setup_switch:
-
-    ENTRY(16)
-
-	getcoreid a3
-    movi    a2, port_switch_flag
-	addx4	a2,  a3, a2
-
-    movi    a3, 1
-    s32i    a3, a2, 0
-
-    RET(16)
-
-
-
-
-
-
-/*
-*******************************************************************************
-* _frxt_int_enter
-* void _frxt_int_enter(void)
-*
-* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
-* freeRTOS. Saves the rest of the interrupt context (not already saved).
-* May only be called from assembly code by the 'call0' instruction, with
-* interrupts disabled.
-* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
-*
-*******************************************************************************
-*/
-    .globl  _frxt_int_enter
-    .type   _frxt_int_enter,@function
-    .align  4
-_frxt_int_enter:
-
-    /* Save a12-13 in the stack frame as required by _xt_context_save. */
-    s32i    a12, a1, XT_STK_A12
-    s32i    a13, a1, XT_STK_A13
-
-    /* Save return address in a safe place (free a0). */
-    mov     a12, a0
-
-    /* Save the rest of the interrupted context (preserves A12-13). */
-    call0   _xt_context_save
-
-    /*
-    Save interrupted task's SP in TCB only if not nesting.
-    Manage nesting directly rather than call the generic IntEnter()
-    (in windowed ABI we can't call a C function here anyway because PS.EXCM is still set).
-    */
-	getcoreid a4
-    movi    a2,  port_xSchedulerRunning
-	addx4	a2,  a4, a2
-    movi    a3,  port_interruptNesting
-	addx4	a3,  a4, a3
-    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
-    beqz    a2,  1f                     /* scheduler not running, no tasks */
-    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
-    addi    a2,  a2, 1                  /* increment nesting count         */
-    s32i    a2,  a3, 0                  /* save nesting count              */
-    bnei    a2,  1, .Lnested            /* !=0 before incr, so nested      */
-
-    movi    a2,  pxCurrentTCB
-	addx4	a2,  a4, a2
-    l32i    a2,  a2, 0                  /* a2 = current TCB                */
-    beqz    a2,  1f
-    s32i    a1,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP */
-    movi    a1,  port_IntStack+configISR_STACK_SIZE   /* a1 = top of intr stack for CPU 0  */
-    movi    a2,  configISR_STACK_SIZE   /* add configISR_STACK_SIZE * cpu_num to arrive at top of stack for cpu_num */
-	mull	a2,  a4, a2
-	add     a1,  a1, a2					/* for current proc */
-
-.Lnested:
-1:
-    mov     a0,  a12                    /* restore return addr and return  */
-    ret
-
-/*
-*******************************************************************************
-* _frxt_int_exit
-* void _frxt_int_exit(void)
-*
-* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
-* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context
-* switching, restore the (possibly) new task's context, and return to the
-* exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
-* May only be called from assembly code by the 'call0' instruction. Does not
-* return to caller.
-* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
-*
-*******************************************************************************
-*/
-    .globl  _frxt_int_exit
-    .type   _frxt_int_exit,@function
-    .align  4
-_frxt_int_exit:
-
-	getcoreid a4
-    movi    a2,  port_xSchedulerRunning
-	addx4	a2,  a4, a2
-    movi    a3,  port_interruptNesting
-	addx4	a3,  a4, a3
-    rsil    a0,  XCHAL_EXCM_LEVEL       /* lock out interrupts             */
-    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
-    beqz    a2,  .Lnoswitch             /* scheduler not running, no tasks */
-    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
-    addi    a2,  a2, -1                 /* decrement nesting count         */
-    s32i    a2,  a3, 0                  /* save nesting count              */
-    bnez    a2,  .Lnesting              /* !=0 after decr so still nested  */
-
-    movi    a2,  pxCurrentTCB
-	addx4	a2,  a4, a2
-    l32i    a2,  a2, 0                  /* a2 = current TCB                */
-    beqz    a2,  1f                     /* no task ? go to dispatcher      */
-    l32i    a1,  a2, TOPOFSTACK_OFFS    /* SP = pxCurrentTCB->pxTopOfStack */
-
-    movi    a2,  port_switch_flag       /* address of switch flag          */
-	addx4	a2,  a4, a2					/* point to flag for this cpu      */
-    l32i    a3,  a2, 0                  /* a3 = port_switch_flag           */
-    beqz    a3,  .Lnoswitch             /* flag = 0 means no switch reqd   */
-    movi    a3,  0
-    s32i    a3,  a2, 0                  /* zero out the flag for next time */
-
-1:
-    /*
-    Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.
-    However a12-13 were already saved by _frxt_int_enter().
-    */
-    #ifdef __XTENSA_CALL0_ABI__
-    s32i    a14, a1, XT_STK_A14
-    s32i    a15, a1, XT_STK_A15
-    #endif
-
-    #ifdef __XTENSA_CALL0_ABI__
-    call0   vPortYieldFromInt       /* call dispatch inside the function; never returns */
-    #else
-    call4   vPortYieldFromInt       /* this one returns */
-    call0   _frxt_dispatch          /* tail-call dispatcher */
-    /* Never returns here. */
-    #endif
-
-.Lnoswitch:
-    /*
-    If we came here then about to resume the interrupted task.
-    */
-
-.Lnesting:
-    /*
-    We come here only if there was no context switch, that is if this
-    is a nested interrupt, or the interrupted task was not preempted.
-    In either case there's no need to load the SP.
-    */
-
-    /* Restore full context from interrupt stack frame */
-    call0   _xt_context_restore
-
-    /*
-    Must return via the exit dispatcher corresponding to the entrypoint from which
-    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
-    stack frame is deallocated in the exit dispatcher.
-    */
-    l32i    a0,  a1, XT_STK_EXIT
-    ret
-
-
-/*
-**********************************************************************************************************
-*                                           _frxt_timer_int
-*                                      void _frxt_timer_int(void)
-*
-* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
-* Called every timer interrupt.
-* Manages the tick timer and calls xPortSysTickHandler() every tick.
-* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
-*
-* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance.
-*
-**********************************************************************************************************
-*/
-    .globl  _frxt_timer_int
-    .type   _frxt_timer_int,@function
-    .align  4
-_frxt_timer_int:
-
-    /*
-    Xtensa timers work by comparing a cycle counter with a preset value.  Once the match occurs
-    an interrupt is generated, and the handler has to set a new cycle count into the comparator.
-    To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,
-    not the time the interrupt was serviced. However if a timer interrupt is ever serviced more
-    than one tick late, it is necessary to process multiple ticks until the new cycle count is
-    in the future, otherwise the next timer interrupt would not occur until after the cycle
-    counter had wrapped (2^32 cycles later).
-
-    do {
-        ticks++;
-        old_ccompare = read_ccompare_i();
-        write_ccompare_i( old_ccompare + divisor );
-        service one tick;
-        diff = read_ccount() - old_ccompare;
-    } while ( diff > divisor );
-    */
-
-    ENTRY(16)
-
-    #ifdef CONFIG_PM_TRACE
-    movi a6, 1 /* = ESP_PM_TRACE_TICK */
-    getcoreid a7
-    call4 esp_pm_trace_enter
-    #endif // CONFIG_PM_TRACE
-
-.L_xt_timer_int_catchup:
-
-    /* Update the timer comparator for the next tick. */
-    #ifdef XT_CLOCK_FREQ
-    movi    a2, XT_TICK_DIVISOR         /* a2 = comparator increment          */
-    #else
-    movi    a3, _xt_tick_divisor
-    l32i    a2, a3, 0                   /* a2 = comparator increment          */
-    #endif
-    rsr     a3, XT_CCOMPARE             /* a3 = old comparator value          */
-    add     a4, a3, a2                  /* a4 = new comparator value          */
-    wsr     a4, XT_CCOMPARE             /* update comp. and clear interrupt   */
-    esync
-
-    #ifdef __XTENSA_CALL0_ABI__
-    /* Preserve a2 and a3 across C calls. */
-    s32i    a2, sp, 4
-    s32i    a3, sp, 8
-    #endif
-
-    /* Call the FreeRTOS tick handler (see port.c). */
-    #ifdef __XTENSA_CALL0_ABI__
-    call0   xPortSysTickHandler
-    #else
-    call4   xPortSysTickHandler
-    #endif
-
-    #ifdef __XTENSA_CALL0_ABI__
-    /* Restore a2 and a3. */
-    l32i    a2, sp, 4
-    l32i    a3, sp, 8
-    #endif
-
-    /* Check if we need to process more ticks to catch up. */
-    esync                               /* ensure comparator update complete  */
-    rsr     a4, CCOUNT                  /* a4 = cycle count                   */
-    sub     a4, a4, a3                  /* diff = ccount - old comparator     */
-    blt     a2, a4, .L_xt_timer_int_catchup  /* repeat while diff > divisor */
-
-#ifdef CONFIG_PM_TRACE
-    movi a6, 1 /* = ESP_PM_TRACE_TICK */
-    getcoreid a7
-    call4 esp_pm_trace_exit
-#endif // CONFIG_PM_TRACE
-
-    RET(16)
-
-    /*
-**********************************************************************************************************
-*                                           _frxt_tick_timer_init
-*                                      void _frxt_tick_timer_init(void)
-*
-* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).
-* Callable from C (obeys ABI conventions on entry).
-*
-**********************************************************************************************************
-*/
-    .globl  _frxt_tick_timer_init
-    .type   _frxt_tick_timer_init,@function
-    .align  4
-_frxt_tick_timer_init:
-
-    ENTRY(16)
-
-
-    /* Set up the periodic tick timer (assume enough time to complete init). */
-    #ifdef XT_CLOCK_FREQ
-    movi    a3, XT_TICK_DIVISOR
-    #else
-    movi    a2, _xt_tick_divisor
-    l32i    a3, a2, 0
-    #endif
-    rsr     a2, CCOUNT              /* current cycle count */
-    add     a2, a2, a3              /* time of first timer interrupt */
-    wsr     a2, XT_CCOMPARE         /* set the comparator */
-
-    /*
-    Enable the timer interrupt at the device level. Don't write directly
-    to the INTENABLE register because it may be virtualized.
-    */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a2, XT_TIMER_INTEN
-    call0   xt_ints_on
-    #else
-    movi    a6, XT_TIMER_INTEN
-    call4   xt_ints_on
-    #endif
-
-    RET(16)
-
-/*
-**********************************************************************************************************
-*                                    DISPATCH THE HIGH READY TASK
-*                                     void _frxt_dispatch(void)
-*
-* Switch context to the highest priority ready task, restore its state and dispatch control to it.
-*
-* This is a common dispatcher that acts as a shared exit path for all the context switch functions
-* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher
-* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ).
-*
-* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see
-* comments on stack frames in xtensa_context.h). This function restores the state accordingly.
-* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear.
-* If restoring a task that was preempted, restores all state including the task's CPENABLE.
-*
-* Entry:
-*   pxCurrentTCB  points to the TCB of the task to suspend,
-*   Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction.
-*
-* Exit:
-*   If incoming task called vPortYield() (solicited), this function returns as if from vPortYield().
-*   If incoming task was preempted by an interrupt, this function jumps to exit dispatcher.
-*
-**********************************************************************************************************
-*/
-    .globl  _frxt_dispatch
-    .type   _frxt_dispatch,@function
-    .align  4
-_frxt_dispatch:
-
-    #ifdef __XTENSA_CALL0_ABI__
-    call0   vTaskSwitchContext  // Get next TCB to resume
-    movi    a2, pxCurrentTCB
-	getcoreid a3
-	addx4	a2,  a3, a2
-    #else
-    call4   vTaskSwitchContext  // Get next TCB to resume
-    movi    a2, pxCurrentTCB
-	getcoreid a3
-	addx4	a2,  a3, a2
-    #endif
-    l32i    a3,  a2, 0
-    l32i    sp,  a3, TOPOFSTACK_OFFS     /* SP = next_TCB->pxTopOfStack;  */
-    s32i    a3,  a2, 0
-
-    /* Determine the type of stack frame. */
-    l32i    a2,  sp, XT_STK_EXIT        /* exit dispatcher or solicited flag */
-    bnez    a2,  .L_frxt_dispatch_stk
-
-.L_frxt_dispatch_sol:
-
-    /* Solicited stack frame. Restore minimal context and return from vPortYield(). */
-    l32i    a3,  sp, XT_SOL_PS
-    #ifdef __XTENSA_CALL0_ABI__
-    l32i    a12, sp, XT_SOL_A12
-    l32i    a13, sp, XT_SOL_A13
-    l32i    a14, sp, XT_SOL_A14
-    l32i    a15, sp, XT_SOL_A15
-    #endif
-    l32i    a0,  sp, XT_SOL_PC
-    #if XCHAL_CP_NUM > 0
-    /* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */
-    rsync
-    #endif
-    /* As soons as PS is restored, interrupts can happen. No need to sync PS. */
-    wsr     a3,  PS
-    #ifdef __XTENSA_CALL0_ABI__
-    addi    sp,  sp, XT_SOL_FRMSZ
-    ret
-    #else
-    retw
-    #endif
-
-.L_frxt_dispatch_stk:
-
-    #if XCHAL_CP_NUM > 0
-    /* Restore CPENABLE from task's co-processor save area. */
-    movi    a3, pxCurrentTCB            /* cp_state =                       */
-	getcoreid a2
-	addx4	a3,  a2, a3
-    l32i    a3, a3, 0
-    l32i    a2, a3, CP_TOPOFSTACK_OFFS     /* StackType_t                       *pxStack; */
-    l16ui   a3, a2, XT_CPENABLE         /* CPENABLE = cp_state->cpenable;   */
-    wsr     a3, CPENABLE
-    #endif
-
-    /* Interrupt stack frame. Restore full context and return to exit dispatcher. */
-    call0   _xt_context_restore
-
-    /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
-    #ifdef __XTENSA_CALL0_ABI__
-    l32i    a14, sp, XT_STK_A14
-    l32i    a15, sp, XT_STK_A15
-    #endif
-
-    #if XCHAL_CP_NUM > 0
-    /* Ensure wsr.CPENABLE has completed. */
-    rsync
-    #endif
-
-    /*
-    Must return via the exit dispatcher corresponding to the entrypoint from which
-    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
-    stack frame is deallocated in the exit dispatcher.
-    */
-    l32i    a0, sp, XT_STK_EXIT
-    ret
-
-
-/*
-**********************************************************************************************************
-*                            PERFORM A SOLICTED CONTEXT SWITCH (from a task)
-*                                        void vPortYield(void)
-*
-* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE,
-* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch
-*
-* At Entry:
-*   pxCurrentTCB  points to the TCB of the task to suspend
-*   Callable from C (obeys ABI conventions on entry).
-*
-* Does not return to caller.
-*
-**********************************************************************************************************
-*/
-    .globl  vPortYield
-    .type   vPortYield,@function
-    .align  4
-vPortYield:
-
-    #ifdef __XTENSA_CALL0_ABI__
-    addi    sp,  sp, -XT_SOL_FRMSZ
-    #else
-    entry   sp,  XT_SOL_FRMSZ
-    #endif
-
-    rsr     a2,  PS
-    s32i    a0,  sp, XT_SOL_PC
-    s32i    a2,  sp, XT_SOL_PS
-    #ifdef __XTENSA_CALL0_ABI__
-    s32i    a12, sp, XT_SOL_A12         /* save callee-saved registers      */
-    s32i    a13, sp, XT_SOL_A13
-    s32i    a14, sp, XT_SOL_A14
-    s32i    a15, sp, XT_SOL_A15
-    #else
-    /* Spill register windows. Calling xthal_window_spill() causes extra    */
-    /* spills and reloads, so we will set things up to call the _nw version */
-    /* instead to save cycles.                                              */
-    movi    a6,  ~(PS_WOE_MASK|PS_INTLEVEL_MASK)  /* spills a4-a7 if needed */
-    and     a2,  a2, a6                           /* clear WOE, INTLEVEL    */
-    addi    a2,  a2, XCHAL_EXCM_LEVEL             /* set INTLEVEL           */
-    wsr     a2,  PS
-    rsync
-    call0   xthal_window_spill_nw
-    l32i    a2,  sp, XT_SOL_PS                    /* restore PS             */
-    wsr     a2,  PS
-    #endif
-
-    rsil    a2,  XCHAL_EXCM_LEVEL       /* disable low/med interrupts       */
-
-    #if XCHAL_CP_NUM > 0
-    /* Save coprocessor callee-saved state (if any). At this point CPENABLE */
-    /* should still reflect which CPs were in use (enabled).                */
-    call0   _xt_coproc_savecs
-    #endif
-
-    movi    a2,  pxCurrentTCB
-	getcoreid a3
-	addx4	a2,  a3, a2
-    l32i    a2,  a2, 0                  /* a2 = pxCurrentTCB                */
-    movi    a3,  0
-    s32i    a3,  sp, XT_SOL_EXIT        /* 0 to flag as solicited frame     */
-    s32i    sp,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP  */
-
-    #if XCHAL_CP_NUM > 0
-    /* Clear CPENABLE, also in task's co-processor state save area. */
-    l32i    a2,  a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state      */
-    movi    a3,  0
-    wsr     a3,  CPENABLE
-    beqz    a2,  1f
-    s16i    a3,  a2, XT_CPENABLE        /* clear saved cpenable             */
-1:
-    #endif
-
-    /* Tail-call dispatcher. */
-    call0   _frxt_dispatch
-    /* Never reaches here. */
-
-
-/*
-**********************************************************************************************************
-*                         PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt)
-*                                        void vPortYieldFromInt(void)
-*
-* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher
-* _frxt_dispatch() to perform the actual context switch.
-*
-* At Entry:
-*   Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack.
-*   pxCurrentTCB  points to the TCB of the task to suspend,
-*   Callable from C (obeys ABI conventions on entry).
-*
-* At Exit:
-*   Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry.
-*   Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller.
-*
-**********************************************************************************************************
-*/
-    .globl  vPortYieldFromInt
-    .type   vPortYieldFromInt,@function
-    .align  4
-vPortYieldFromInt:
-
-    ENTRY(16)
-
-    #if XCHAL_CP_NUM > 0
-    /* Save CPENABLE in task's co-processor save area, and clear CPENABLE.  */
-    movi    a3, pxCurrentTCB            /* cp_state =                       */
-	getcoreid a2
-	addx4	a3,  a2, a3
-    l32i    a3, a3, 0
-
-    l32i    a2, a3, CP_TOPOFSTACK_OFFS
-
-    rsr     a3, CPENABLE
-    s16i    a3, a2, XT_CPENABLE         /* cp_state->cpenable = CPENABLE;   */
-    movi    a3, 0
-    wsr     a3, CPENABLE                /* disable all co-processors        */
-    #endif
-
-    #ifdef __XTENSA_CALL0_ABI__
-    /* Tail-call dispatcher. */
-    call0   _frxt_dispatch
-    /* Never reaches here. */
-    #else
-    RET(16)
-    #endif
-
-/*
-**********************************************************************************************************
-*                                        _frxt_task_coproc_state
-*                                   void _frxt_task_coproc_state(void)
-*
-* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS.
-*
-* May only be called when a task is running, not within an interrupt handler (returns 0 in that case).
-* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.
-* Returns in A15 a pointer to the base of the co-processor state save area for the current task.
-* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
-*
-**********************************************************************************************************
-*/
-#if XCHAL_CP_NUM > 0
-
-    .globl  _frxt_task_coproc_state
-    .type   _frxt_task_coproc_state,@function
-    .align  4
-_frxt_task_coproc_state:
-
-
-	/* We can use a3 as a scratchpad, the instances of code calling XT_RTOS_CP_STATE don't seem to need it saved. */
-	getcoreid a3
-    movi    a15, port_xSchedulerRunning /* if (port_xSchedulerRunning              */
-	addx4	a15, a3,a15
-    l32i    a15, a15, 0
-    beqz    a15, 1f
-    movi    a15, port_interruptNesting  /* && port_interruptNesting == 0           */
-	addx4	a15, a3, a15
-    l32i    a15, a15, 0
-    bnez    a15, 1f
-
-    movi    a15, pxCurrentTCB
-	addx4	a15, a3, a15
-    l32i    a15, a15, 0                 /* && pxCurrentTCB != 0) {                 */
-
-
-    beqz    a15, 2f
-    l32i    a15, a15, CP_TOPOFSTACK_OFFS
-    ret
-
-1:  movi    a15, 0
-2:  ret
-
-#endif /* XCHAL_CP_NUM > 0 */
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h
deleted file mode 100755
index 60bc996..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
-    Copyright (C) 2016-2017 Espressif Shanghai PTE LTD
-    Copyright (C) 2015 Real Time Engineers Ltd.
-
-    All rights reserved
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-*/
-
-/* This header exists for performance reasons, in order to inline the
-   implementation of vPortCPUAcquireMutexIntsDisabled and
-   vPortCPUReleaseMutexIntsDisabled into the
-   vTaskEnterCritical/vTaskExitCritical functions in task.c as well as the
-   vPortCPUAcquireMutex/vPortCPUReleaseMutex implementations.
-
-   Normally this kind of performance hack is over the top, but
-   vTaskEnterCritical/vTaskExitCritical is called a great
-   deal by FreeRTOS internals.
-
-   It should be #included by freertos port.c or tasks.c, in esp-idf.
-
-   The way it works is that it essentially uses portmux_impl.inc.h as a
-   generator template of sorts. When no external memory is used, this 
-   template is only used to generate the vPortCPUAcquireMutexIntsDisabledInternal
-   and vPortCPUReleaseMutexIntsDisabledInternal functions, which use S32C1 to
-   do an atomic compare & swap. When external memory is used the functions
-   vPortCPUAcquireMutexIntsDisabledExtram and vPortCPUReleaseMutexIntsDisabledExtram
-   are also generated, which use uxPortCompareSetExtram to fake the S32C1 instruction.
-   The wrapper functions vPortCPUAcquireMutexIntsDisabled and 
-   vPortCPUReleaseMutexIntsDisabled will then use the appropriate function to do the
-   actual lock/unlock.
-*/
-#include "soc/cpu.h"
-#include "portable.h"
-
-/* XOR one core ID with this value to get the other core ID */
-#define CORE_ID_XOR_SWAP (CORE_ID_PRO ^ CORE_ID_APP)
-
-
-
-
-//Define the mux routines for use with muxes in internal RAM
-#define PORTMUX_AQUIRE_MUX_FN_NAME vPortCPUAcquireMutexIntsDisabledInternal
-#define PORTMUX_RELEASE_MUX_FN_NAME vPortCPUReleaseMutexIntsDisabledInternal
-#define PORTMUX_COMPARE_SET_FN_NAME uxPortCompareSet
-#include "portmux_impl.inc.h"
-#undef PORTMUX_AQUIRE_MUX_FN_NAME
-#undef PORTMUX_RELEASE_MUX_FN_NAME
-#undef PORTMUX_COMPARE_SET_FN_NAME
-
-
-#if defined(CONFIG_SPIRAM_SUPPORT)
-
-#define PORTMUX_AQUIRE_MUX_FN_NAME vPortCPUAcquireMutexIntsDisabledExtram
-#define PORTMUX_RELEASE_MUX_FN_NAME vPortCPUReleaseMutexIntsDisabledExtram
-#define PORTMUX_COMPARE_SET_FN_NAME uxPortCompareSetExtram
-#include "portmux_impl.inc.h"
-#undef PORTMUX_AQUIRE_MUX_FN_NAME
-#undef PORTMUX_RELEASE_MUX_FN_NAME
-#undef PORTMUX_COMPARE_SET_FN_NAME
-
-#endif
-
-
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-#define PORTMUX_AQUIRE_MUX_FN_ARGS portMUX_TYPE *mux, int timeout_cycles, const char *fnName, int line
-#define PORTMUX_RELEASE_MUX_FN_ARGS portMUX_TYPE *mux, const char *fnName, int line
-#define PORTMUX_AQUIRE_MUX_FN_CALL_ARGS(x) x, timeout_cycles, fnName, line
-#define PORTMUX_RELEASE_MUX_FN_CALL_ARGS(x) x, fnName, line
-#else
-#define PORTMUX_AQUIRE_MUX_FN_ARGS portMUX_TYPE *mux, int timeout_cycles
-#define PORTMUX_RELEASE_MUX_FN_ARGS portMUX_TYPE *mux
-#define PORTMUX_AQUIRE_MUX_FN_CALL_ARGS(x) x, timeout_cycles
-#define PORTMUX_RELEASE_MUX_FN_CALL_ARGS(x) x
-#endif
-
-
-static inline bool __attribute__((always_inline)) vPortCPUAcquireMutexIntsDisabled(PORTMUX_AQUIRE_MUX_FN_ARGS) {
-#if defined(CONFIG_SPIRAM_SUPPORT)
-	if (esp_ptr_external_ram(mux)) {
-		return vPortCPUAcquireMutexIntsDisabledExtram(PORTMUX_AQUIRE_MUX_FN_CALL_ARGS(mux));
-	}
-#endif
-	return vPortCPUAcquireMutexIntsDisabledInternal(PORTMUX_AQUIRE_MUX_FN_CALL_ARGS(mux));
-}
-
-
-static inline void vPortCPUReleaseMutexIntsDisabled(PORTMUX_RELEASE_MUX_FN_ARGS) {
-#if defined(CONFIG_SPIRAM_SUPPORT)
-	if (esp_ptr_external_ram(mux)) {
-		vPortCPUReleaseMutexIntsDisabledExtram(PORTMUX_RELEASE_MUX_FN_CALL_ARGS(mux));
-		return;
-	}
-#endif
-	vPortCPUReleaseMutexIntsDisabledInternal(PORTMUX_RELEASE_MUX_FN_CALL_ARGS(mux));
-}
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h
deleted file mode 100755
index 07a7ce9..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/portmux_impl.inc.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
-    Copyright (C) 2016-2017 Espressif Shanghai PTE LTD
-    Copyright (C) 2015 Real Time Engineers Ltd.
-
-    All rights reserved
-
-    FreeRTOS is free software; you can redistribute it and/or modify it under
-    the terms of the GNU General Public License (version 2) as published by the
-    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
-
-	***************************************************************************
-    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
-    >>!   distribute a combined work that includes FreeRTOS without being   !<<
-    >>!   obliged to provide the source code for proprietary components     !<<
-    >>!   outside of the FreeRTOS kernel.                                   !<<
-	***************************************************************************
-
-    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
-    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
-    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
-    link: http://www.freertos.org/a00114.html
-*/
-
-
-/*
-  Warning: funky preprocessor hackery ahead. Including these headers will generate two
-  functions, which names are defined by the preprocessor macros 
-  PORTMUX_AQUIRE_MUX_FN_NAME and PORTMUX_RELEASE_MUX_FN_NAME. In order to do the compare
-  and exchange function, they will use whatever PORTMUX_COMPARE_SET_FN_NAME resolves to.
-
-  In some scenarios, this header is included *twice* in portmux_impl.h: one time 
-  for the 'normal' mux code which uses a compare&exchange routine, another time 
-  to generate code for a second set of these routines that use a second mux 
-  (in internal ram) to fake a compare&exchange on a variable in external memory.
-*/
-
-
-
-static inline bool __attribute__((always_inline))
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-PORTMUX_AQUIRE_MUX_FN_NAME(portMUX_TYPE *mux, int timeout_cycles, const char *fnName, int line) {
-#else
-PORTMUX_AQUIRE_MUX_FN_NAME(portMUX_TYPE *mux, int timeout_cycles) {
-#endif
-
-
-#if !CONFIG_FREERTOS_UNICORE
-	uint32_t res;
-	portBASE_TYPE coreID, otherCoreID;
-	uint32_t ccount_start;
-	bool set_timeout = timeout_cycles > portMUX_NO_TIMEOUT;
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-	if (!set_timeout) {
-		timeout_cycles = 10000; // Always set a timeout in debug mode
-		set_timeout = true;
-	}
-#endif
-	if (set_timeout) { // Timeout
-		RSR(CCOUNT, ccount_start);
-	}
-
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-	uint32_t owner = mux->owner;
-	if (owner != portMUX_FREE_VAL && owner != CORE_ID_PRO && owner != CORE_ID_APP) {
-		ets_printf("ERROR: vPortCPUAcquireMutex: mux %p is uninitialized (0x%X)! Called from %s line %d.\n", mux, owner, fnName, line);
-		mux->owner=portMUX_FREE_VAL;
-	}
-#endif
-
-	/* Spin until we own the core */
-
-	RSR(PRID, coreID);
-	/* Note: coreID is the full 32 bit core ID (CORE_ID_PRO/CORE_ID_APP),
-	   not the 0/1 value returned by xPortGetCoreID()
-	*/
-	otherCoreID = CORE_ID_XOR_SWAP ^ coreID;
-	do {
-		/* mux->owner should be one of portMUX_FREE_VAL, CORE_ID_PRO,
-		   CORE_ID_APP:
-
-		   - If portMUX_FREE_VAL, we want to atomically set to 'coreID'.
-		   - If "our" coreID, we can drop through immediately.
-		   - If "otherCoreID", we spin here.
-		 */
-		res = coreID;
-		PORTMUX_COMPARE_SET_FN_NAME(&mux->owner, portMUX_FREE_VAL, &res);
-
-		if (res != otherCoreID) {
-			break; // mux->owner is "our" coreID
-		}
-
-		if (set_timeout) {
-			uint32_t ccount_now;
-			RSR(CCOUNT, ccount_now);
-			if (ccount_now - ccount_start > (unsigned)timeout_cycles) {
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-				ets_printf("Timeout on mux! last non-recursive lock %s line %d, curr %s line %d\n", mux->lastLockedFn, mux->lastLockedLine, fnName, line);
-				ets_printf("Owner 0x%x count %d\n", mux->owner, mux->count);
-#endif
-				return false;
-			}
-		}
-	} while (1);
-
-	assert(res == coreID || res == portMUX_FREE_VAL); /* any other value implies memory corruption or uninitialized mux */
-	assert((res == portMUX_FREE_VAL) == (mux->count == 0)); /* we're first to lock iff count is zero */
-    assert(mux->count < 0xFF); /* Bad count value implies memory corruption */
-
-	/* now we own it, we can increment the refcount */
-	mux->count++;
-
-
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-	if (res==portMUX_FREE_VAL) { //initial lock
-		mux->lastLockedFn=fnName;
-		mux->lastLockedLine=line;
-	} else {
-		ets_printf("Recursive lock: count=%d last non-recursive lock %s line %d, curr %s line %d\n", mux->count-1,
-				   mux->lastLockedFn, mux->lastLockedLine, fnName, line);
-	}
-#endif /* CONFIG_FREERTOS_PORTMUX_DEBUG */
-#endif /* CONFIG_FREERTOS_UNICORE */
-	return true;
-}
-
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-static inline void PORTMUX_RELEASE_MUX_FN_NAME(portMUX_TYPE *mux, const char *fnName, int line) {
-#else
-static inline void PORTMUX_RELEASE_MUX_FN_NAME(portMUX_TYPE *mux) {
-#endif
-
-
-#if !CONFIG_FREERTOS_UNICORE
-	portBASE_TYPE coreID;
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-	const char *lastLockedFn=mux->lastLockedFn;
-	int lastLockedLine=mux->lastLockedLine;
-	mux->lastLockedFn=fnName;
-	mux->lastLockedLine=line;
-	uint32_t owner = mux->owner;
-	if (owner != portMUX_FREE_VAL && owner != CORE_ID_PRO && owner != CORE_ID_APP) {
-		ets_printf("ERROR: vPortCPUReleaseMutex: mux %p is invalid (0x%x)!\n", mux, mux->owner);
-	}
-#endif
-
-#if CONFIG_FREERTOS_PORTMUX_DEBUG || !defined(NDEBUG)
-	RSR(PRID, coreID);
-#endif
-
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG
-	if (coreID != mux->owner) {
-		ets_printf("ERROR: vPortCPUReleaseMutex: mux %p was already unlocked!\n", mux);
-		ets_printf("Last non-recursive unlock %s line %d, curr unlock %s line %d\n", lastLockedFn, lastLockedLine, fnName, line);
-	}
-#endif
-
-	assert(coreID == mux->owner); // This is a mutex we didn't lock, or it's corrupt
-
-	mux->count--;
-	if(mux->count == 0) {
-		mux->owner = portMUX_FREE_VAL;
-	} else {
-		assert(mux->count < 0x100); // Indicates memory corruption
-#ifdef CONFIG_FREERTOS_PORTMUX_DEBUG_RECURSIVE
-		ets_printf("Recursive unlock: count=%d last locked %s line %d, curr %s line %d\n", mux->count, lastLockedFn, lastLockedLine, fnName, line);
-#endif
-	}
-#endif //!CONFIG_FREERTOS_UNICORE
-}
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S
deleted file mode 100755
index a8a19be..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_context.S
+++ /dev/null
@@ -1,648 +0,0 @@
-/*******************************************************************************
-Copyright (c) 2006-2015 Cadence Design Systems Inc.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice shall be included
-in all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-
-        XTENSA CONTEXT SAVE AND RESTORE ROUTINES
-
-Low-level Call0 functions for handling generic context save and restore of
-registers not specifically addressed by the interrupt vectors and handlers.
-Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
-Except for the calls to RTOS functions, this code is generic to Xtensa.
-
-Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
-save regs (A12-A15), which is always the case if the handlers are coded in C.
-However A12, A13 are made available as scratch registers for interrupt dispatch
-code, so are presumed saved anyway, and are always restored even in Call0 ABI.
-Only A14, A15 are truly handled as callee-save regs.
-
-Because Xtensa is a configurable architecture, this port supports all user
-generated configurations (except restrictions stated in the release notes).
-This is accomplished by conditional compilation using macros and functions
-defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
-Only the processor state included in your configuration is saved and restored,
-including any processor state added by user configuration options or TIE.
-
-*******************************************************************************/
-
-/*  Warn nicely if this file gets named with a lowercase .s instead of .S:  */
-#define NOERROR #
-NOERROR: .error "C preprocessor needed for this file: make sure its filename\
- ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
-
-
-#include "xtensa_rtos.h"
-#include "xtensa_context.h"
-
-#ifdef XT_USE_OVLY
-#include 
-#endif
-
-    .text
-
-
-
-/*******************************************************************************
-
-_xt_context_save
-
-    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
-
-Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
-interrupt stack frame defined in xtensa_rtos.h.
-Its counterpart is _xt_context_restore (which also restores A12, A13).
-
-Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
-This function preserves A12 & A13 in order to provide the caller with 2 scratch 
-regs that need not be saved over the call to this function. The choice of which
-2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
-to avoid moving data more than necessary. Caller can assign regs accordingly.
-
-Entry Conditions:
-    A0  = Return address in caller.
-    A1  = Stack pointer of interrupted thread or handler ("interruptee").
-    Original A12, A13 have already been saved in the interrupt stack frame.
-    Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the 
-    point of interruption.
-    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
-
-Exit conditions:
-    A0  = Return address in caller.
-    A1  = Stack pointer of interrupted thread or handler ("interruptee").
-    A12, A13 as at entry (preserved).
-    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
-
-*******************************************************************************/
-
-    .global _xt_context_save
-    .type   _xt_context_save,@function
-    .align  4
-	.literal_position
-    .align  4
-_xt_context_save:
-
-    s32i    a2,  sp, XT_STK_A2
-    s32i    a3,  sp, XT_STK_A3
-    s32i    a4,  sp, XT_STK_A4
-    s32i    a5,  sp, XT_STK_A5
-    s32i    a6,  sp, XT_STK_A6
-    s32i    a7,  sp, XT_STK_A7
-    s32i    a8,  sp, XT_STK_A8
-    s32i    a9,  sp, XT_STK_A9
-    s32i    a10, sp, XT_STK_A10
-    s32i    a11, sp, XT_STK_A11
-
-    /*
-    Call0 ABI callee-saved regs a12-15 do not need to be saved here.
-    a12-13 are the caller's responsibility so it can use them as scratch.
-    So only need to save a14-a15 here for Windowed ABI (not Call0).
-    */
-    #ifndef __XTENSA_CALL0_ABI__
-    s32i    a14, sp, XT_STK_A14
-    s32i    a15, sp, XT_STK_A15
-    #endif
-
-    rsr     a3,  SAR
-    s32i    a3,  sp, XT_STK_SAR
-
-    #if XCHAL_HAVE_LOOPS
-    rsr     a3,  LBEG
-    s32i    a3,  sp, XT_STK_LBEG
-    rsr     a3,  LEND
-    s32i    a3,  sp, XT_STK_LEND
-    rsr     a3,  LCOUNT
-    s32i    a3,  sp, XT_STK_LCOUNT
-    #endif
-
-    #ifdef XT_USE_SWPRI
-    /* Save virtual priority mask */
-    movi    a3,  _xt_vpri_mask
-    l32i    a3,  a3, 0
-    s32i    a3,  sp, XT_STK_VPRI
-    #endif
-
-    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
-    mov     a9,  a0                     /* preserve ret addr */
-    #endif
-
-    #ifndef __XTENSA_CALL0_ABI__
-    /*
-    To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
-    Need to save a9,12,13 temporarily (in frame temps) and recover originals.
-    Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
-    and underflow exceptions disabled (assured by PS.EXCM == 1).
-    */
-    s32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
-    s32i    a13, sp, XT_STK_TMP1    
-    s32i    a9,  sp, XT_STK_TMP2    
-
-    /*
-    Save the overlay state if we are supporting overlays. Since we just saved
-    three registers, we can conveniently use them here. Note that as of now,
-    overlays only work for windowed calling ABI.
-    */
-    #ifdef XT_USE_OVLY
-    l32i    a9,  sp, XT_STK_PC          /* recover saved PC */
-    _xt_overlay_get_state    a9, a12, a13
-    s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
-    #endif
-
-    l32i    a12, sp, XT_STK_A12         /* recover original a9,12,13 */
-    l32i    a13, sp, XT_STK_A13
-    l32i    a9,  sp, XT_STK_A9
-    addi    sp,  sp, XT_STK_FRMSZ       /* restore the interruptee's SP */
-    call0   xthal_window_spill_nw       /* preserves only a4,5,8,9,12,13 */
-    addi    sp,  sp, -XT_STK_FRMSZ
-    l32i    a12, sp, XT_STK_TMP0        /* recover stuff from stack frame */
-    l32i    a13, sp, XT_STK_TMP1    
-    l32i    a9,  sp, XT_STK_TMP2    
-    #endif
-
-    #if XCHAL_EXTRA_SA_SIZE > 0
-    /*  
-    NOTE: Normally the xthal_save_extra_nw macro only affects address
-    registers a2-a5. It is theoretically possible for Xtensa processor
-    designers to write TIE that causes more address registers to be
-    affected, but it is generally unlikely. If that ever happens,
-    more registers need to be saved/restored around this macro invocation.
-    Here we assume a9,12,13 are preserved.
-    Future Xtensa tools releases might limit the regs that can be affected.
-    */
-    addi    a2,  sp, XT_STK_EXTRA       /* where to save it */
-    # if XCHAL_EXTRA_SA_ALIGN > 16
-    movi    a3, -XCHAL_EXTRA_SA_ALIGN
-    and     a2, a2, a3                  /* align dynamically >16 bytes */
-    # endif
-    call0   xthal_save_extra_nw         /* destroys a0,2,3,4,5 */
-    #endif
-
-    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
-    mov     a0, a9                      /* retrieve ret addr */
-    #endif
-
-    ret
-
-/*******************************************************************************
-
-_xt_context_restore
-
-    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
-
-Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
-ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt 
-stack frame defined in xtensa_rtos.h .
-Its counterpart is _xt_context_save (whose caller saved A12, A13).
-
-Caller is responsible to restore PC, PS, A0, A1 (SP).
-
-Entry Conditions:
-    A0  = Return address in caller.
-    A1  = Stack pointer of interrupted thread or handler ("interruptee").
-
-Exit conditions:
-    A0  = Return address in caller.
-    A1  = Stack pointer of interrupted thread or handler ("interruptee").
-    Other processor state except PC, PS, A0, A1 (SP), is as at the point 
-    of interruption.
-
-*******************************************************************************/
-
-    .global _xt_context_restore
-    .type   _xt_context_restore,@function
-    .align  4
-	.literal_position
-    .align  4
-_xt_context_restore:
-
-    #if XCHAL_EXTRA_SA_SIZE > 0
-    /*  
-    NOTE: Normally the xthal_restore_extra_nw macro only affects address
-    registers a2-a5. It is theoretically possible for Xtensa processor
-    designers to write TIE that causes more address registers to be
-    affected, but it is generally unlikely. If that ever happens,
-    more registers need to be saved/restored around this macro invocation.
-    Here we only assume a13 is preserved.
-    Future Xtensa tools releases might limit the regs that can be affected.
-    */
-    mov     a13, a0                     /* preserve ret addr */
-    addi    a2,  sp, XT_STK_EXTRA       /* where to find it */
-    # if XCHAL_EXTRA_SA_ALIGN > 16
-    movi    a3, -XCHAL_EXTRA_SA_ALIGN
-    and     a2, a2, a3                  /* align dynamically >16 bytes */
-    # endif
-    call0   xthal_restore_extra_nw      /* destroys a0,2,3,4,5 */
-    mov     a0,  a13                    /* retrieve ret addr */
-    #endif
-
-    #if XCHAL_HAVE_LOOPS
-    l32i    a2,  sp, XT_STK_LBEG
-    l32i    a3,  sp, XT_STK_LEND
-    wsr     a2,  LBEG
-    l32i    a2,  sp, XT_STK_LCOUNT
-    wsr     a3,  LEND
-    wsr     a2,  LCOUNT
-    #endif
-
-    #ifdef XT_USE_OVLY
-    /*
-    If we are using overlays, this is a good spot to check if we need
-    to restore an overlay for the incoming task. Here we have a bunch
-    of registers to spare. Note that this step is going to use a few
-    bytes of storage below SP (SP-20 to SP-32) if an overlay is going
-    to be restored.
-    */
-    l32i    a2,  sp, XT_STK_PC          /* retrieve PC */
-    l32i    a3,  sp, XT_STK_PS          /* retrieve PS */
-    l32i    a4,  sp, XT_STK_OVLY        /* retrieve overlay state */
-    l32i    a5,  sp, XT_STK_A1          /* retrieve stack ptr */
-    _xt_overlay_check_map    a2, a3, a4, a5, a6
-    s32i    a2,  sp, XT_STK_PC          /* save updated PC */
-    s32i    a3,  sp, XT_STK_PS          /* save updated PS */
-    #endif
-
-    #ifdef XT_USE_SWPRI
-    /* Restore virtual interrupt priority and interrupt enable */
-    movi    a3,  _xt_intdata
-    l32i    a4,  a3, 0                  /* a4 = _xt_intenable */
-    l32i    a5,  sp, XT_STK_VPRI        /* a5 = saved _xt_vpri_mask */
-    and     a4,  a4, a5
-    wsr     a4,  INTENABLE              /* update INTENABLE */
-    s32i    a5,  a3, 4                  /* restore _xt_vpri_mask */
-    #endif
-
-    l32i    a3,  sp, XT_STK_SAR
-    l32i    a2,  sp, XT_STK_A2
-    wsr     a3,  SAR
-    l32i    a3,  sp, XT_STK_A3
-    l32i    a4,  sp, XT_STK_A4
-    l32i    a5,  sp, XT_STK_A5
-    l32i    a6,  sp, XT_STK_A6
-    l32i    a7,  sp, XT_STK_A7
-    l32i    a8,  sp, XT_STK_A8
-    l32i    a9,  sp, XT_STK_A9
-    l32i    a10, sp, XT_STK_A10
-    l32i    a11, sp, XT_STK_A11
-
-    /*
-    Call0 ABI callee-saved regs a12-15 do not need to be restored here.
-    However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), 
-    so need to be restored anyway, despite being callee-saved in Call0.
-    */
-    l32i    a12, sp, XT_STK_A12
-    l32i    a13, sp, XT_STK_A13
-    #ifndef __XTENSA_CALL0_ABI__
-    l32i    a14, sp, XT_STK_A14
-    l32i    a15, sp, XT_STK_A15
-    #endif
-
-    ret
-
-
-/*******************************************************************************
-
-_xt_coproc_init
-
-Initializes global co-processor management data, setting all co-processors
-to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
-
-Called during initialization of the RTOS, before any threads run.
-
-This may be called from normal Xtensa single-threaded application code which
-might use co-processors. The Xtensa run-time initialization enables all 
-co-processors. They must remain enabled here, else a co-processor exception
-might occur outside of a thread, which the exception handler doesn't expect.
-
-Entry Conditions:
-    Xtensa single-threaded run-time environment is in effect.
-    No thread is yet running.
-
-Exit conditions:
-    None.
-
-Obeys ABI conventions per prototype:
-    void _xt_coproc_init(void)
-
-*******************************************************************************/
-
-#if XCHAL_CP_NUM > 0
-
-    .global _xt_coproc_init
-    .type   _xt_coproc_init,@function
-    .align  4
-	.literal_position
-    .align  4
-_xt_coproc_init:
-    ENTRY0
-
-    /* Initialize thread co-processor ownerships to 0 (unowned). */
-    movi    a2, _xt_coproc_owner_sa         /* a2 = base of owner array */
-    addi    a3, a2, (XCHAL_CP_MAX*portNUM_PROCESSORS) << 2       /* a3 = top+1 of owner array */
-    movi    a4, 0                           /* a4 = 0 (unowned) */
-1:  s32i    a4, a2, 0
-    addi    a2, a2, 4
-    bltu    a2, a3, 1b
-
-    RET0
-
-#endif
-
-
-/*******************************************************************************
-
-_xt_coproc_release
-
-Releases any and all co-processors owned by a given thread. The thread is 
-identified by it's co-processor state save area defined in xtensa_context.h .
-
-Must be called before a thread's co-proc save area is deleted to avoid
-memory corruption when the exception handler tries to save the state.
-May be called when a thread terminates or completes but does not delete
-the co-proc save area, to avoid the exception handler having to save the 
-thread's co-proc state before another thread can use it (optimization).
-
-Needs to be called on the processor the thread was running on. Unpinned threads
-won't have an entry here because they get pinned as soon they use a coprocessor.
-
-Entry Conditions:
-    A2  = Pointer to base of co-processor state save area.
-
-Exit conditions:
-    None.
-
-Obeys ABI conventions per prototype:
-    void _xt_coproc_release(void * coproc_sa_base)
-
-*******************************************************************************/
-
-#if XCHAL_CP_NUM > 0
-
-    .global _xt_coproc_release
-    .type   _xt_coproc_release,@function
-    .align  4
-	.literal_position
-    .align  4
-_xt_coproc_release:
-    ENTRY0                                  /* a2 = base of save area */
-
-	getcoreid a5
-	movi    a3, XCHAL_CP_MAX << 2
-	mull    a5, a5, a3
-    movi    a3, _xt_coproc_owner_sa         /* a3 = base of owner array */
-	add     a3, a3, a5
-
-    addi    a4, a3, XCHAL_CP_MAX << 2       /* a4 = top+1 of owner array */
-    movi    a5, 0                           /* a5 = 0 (unowned) */
-
-    rsil    a6, XCHAL_EXCM_LEVEL            /* lock interrupts */
-
-1:  l32i    a7, a3, 0                       /* a7 = owner at a3 */
-    bne     a2, a7, 2f                      /* if (coproc_sa_base == owner) */
-    s32i    a5, a3, 0                       /*   owner = unowned */
-2:  addi    a3, a3, 1<<2                    /* a3 = next entry in owner array */
-    bltu    a3, a4, 1b                      /* repeat until end of array */
-
-3:  wsr     a6, PS                          /* restore interrupts */
-
-    RET0
-
-#endif
-
-
-/*******************************************************************************
-_xt_coproc_savecs
-
-If there is a current thread and it has a coprocessor state save area, then
-save all callee-saved state into this area. This function is called from the
-solicited context switch handler. It calls a system-specific function to get
-the coprocessor save area base address.
-
-Entry conditions:
-    - The thread being switched out is still the current thread.
-    - CPENABLE state reflects which coprocessors are active.
-    - Registers have been saved/spilled already.
-
-Exit conditions:
-    - All necessary CP callee-saved state has been saved.
-    - Registers a2-a7, a13-a15 have been trashed.
-
-Must be called from assembly code only, using CALL0.
-*******************************************************************************/
-#if XCHAL_CP_NUM > 0
-
-    .extern     _xt_coproc_sa_offset   /* external reference */
-
-    .global     _xt_coproc_savecs
-    .type       _xt_coproc_savecs,@function
-    .align  4
-	.literal_position
-    .align      4
-_xt_coproc_savecs:
-
-    /* At entry, CPENABLE should be showing which CPs are enabled. */
-
-    rsr     a2, CPENABLE                /* a2 = which CPs are enabled      */
-    beqz    a2, .Ldone                  /* quick exit if none              */
-    mov     a14, a0                     /* save return address             */
-    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
-    mov     a0, a14                     /* restore return address          */
-    beqz    a15, .Ldone                 /* if none then nothing to do      */
-    s16i    a2, a15, XT_CP_CS_ST        /* save mask of CPs being stored   */
-    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
-    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
-
-#if XCHAL_CP0_SA_SIZE
-    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
-    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
-    add     a3, a14, a15                /* a3 = save area for CP 0         */
-    xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP1_SA_SIZE
-    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
-    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
-    add     a3, a14, a15                /* a3 = save area for CP 1         */
-    xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP2_SA_SIZE
-    bbci.l  a2, 2, 2f
-    l32i    a14, a13, 8
-    add     a3, a14, a15
-    xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP3_SA_SIZE
-    bbci.l  a2, 3, 2f
-    l32i    a14, a13, 12
-    add     a3, a14, a15
-    xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP4_SA_SIZE
-    bbci.l  a2, 4, 2f
-    l32i    a14, a13, 16
-    add     a3, a14, a15
-    xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP5_SA_SIZE
-    bbci.l  a2, 5, 2f
-    l32i    a14, a13, 20
-    add     a3, a14, a15
-    xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP6_SA_SIZE
-    bbci.l  a2, 6, 2f
-    l32i    a14, a13, 24
-    add     a3, a14, a15
-    xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP7_SA_SIZE
-    bbci.l  a2, 7, 2f
-    l32i    a14, a13, 28
-    add     a3, a14, a15
-    xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-.Ldone:
-    ret
-#endif
-
-
-/*******************************************************************************
-_xt_coproc_restorecs
-
-Restore any callee-saved coprocessor state for the incoming thread.
-This function is called from coprocessor exception handling, when giving
-ownership to a thread that solicited a context switch earlier. It calls a
-system-specific function to get the coprocessor save area base address.
-
-Entry conditions:
-    - The incoming thread is set as the current thread.
-    - CPENABLE is set up correctly for all required coprocessors.
-    - a2 = mask of coprocessors to be restored.
-
-Exit conditions:
-    - All necessary CP callee-saved state has been restored.
-    - CPENABLE - unchanged.
-    - Registers a2-a7, a13-a15 have been trashed.
-
-Must be called from assembly code only, using CALL0.
-*******************************************************************************/
-#if XCHAL_CP_NUM > 0
-
-    .global     _xt_coproc_restorecs
-    .type       _xt_coproc_restorecs,@function
-    .align  4
-	.literal_position
-    .align      4
-_xt_coproc_restorecs:
-
-    mov     a14, a0                     /* save return address             */
-    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
-    mov     a0, a14                     /* restore return address          */
-    beqz    a15, .Ldone2                /* if none then nothing to do      */
-    l16ui   a3, a15, XT_CP_CS_ST        /* a3 = which CPs have been saved  */
-    xor     a3, a3, a2                  /* clear the ones being restored   */
-    s32i    a3, a15, XT_CP_CS_ST        /* update saved CP mask            */
-    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
-    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
-    
-#if XCHAL_CP0_SA_SIZE
-    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
-    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
-    add     a3, a14, a15                /* a3 = save area for CP 0         */
-    xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:  
-#endif
-
-#if XCHAL_CP1_SA_SIZE
-    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
-    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
-    add     a3, a14, a15                /* a3 = save area for CP 1         */
-    xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP2_SA_SIZE
-    bbci.l  a2, 2, 2f
-    l32i    a14, a13, 8
-    add     a3, a14, a15
-    xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP3_SA_SIZE
-    bbci.l  a2, 3, 2f
-    l32i    a14, a13, 12
-    add     a3, a14, a15
-    xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP4_SA_SIZE
-    bbci.l  a2, 4, 2f
-    l32i    a14, a13, 16
-    add     a3, a14, a15
-    xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP5_SA_SIZE
-    bbci.l  a2, 5, 2f
-    l32i    a14, a13, 20
-    add     a3, a14, a15
-    xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP6_SA_SIZE
-    bbci.l  a2, 6, 2f
-    l32i    a14, a13, 24
-    add     a3, a14, a15
-    xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP7_SA_SIZE
-    bbci.l  a2, 7, 2f
-    l32i    a14, a13, 28
-    add     a3, a14, a15
-    xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-.Ldone2:
-    ret
-
-#endif
-
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c
deleted file mode 100755
index 624f242..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_init.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*******************************************************************************
-// Copyright (c) 2003-2015 Cadence Design Systems, Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-
-        XTENSA INITIALIZATION ROUTINES CODED IN C
-
-This file contains miscellaneous Xtensa RTOS-generic initialization functions
-that are implemented in C.
-
-*******************************************************************************/
-
-
-#ifdef XT_BOARD
-#include    
-#endif
-
-#include    "xtensa_rtos.h"
-#include    "esp_clk.h"
-
-#ifdef XT_RTOS_TIMER_INT
-
-unsigned _xt_tick_divisor = 0;  /* cached number of cycles per tick */
-
-void _xt_tick_divisor_init(void)
-{
-    _xt_tick_divisor = esp_clk_cpu_freq() / XT_TICK_PER_SEC;
-}
-
-/* Deprecated, to be removed */
-int xt_clock_freq(void)
-{
-    return esp_clk_cpu_freq();
-}
-
-#endif /* XT_RTOS_TIMER_INT */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c
deleted file mode 100755
index 856096d..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr.c
+++ /dev/null
@@ -1,158 +0,0 @@
-/*******************************************************************************
-Copyright (c) 2006-2015 Cadence Design Systems Inc.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice shall be included
-in all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-******************************************************************************/
-
-/******************************************************************************
-  Xtensa-specific interrupt and exception functions for RTOS ports.
-  Also see xtensa_intr_asm.S.
-******************************************************************************/
-
-#include 
-
-#include 
-
-#include "freertos/FreeRTOS.h"
-#include "freertos/xtensa_api.h"
-#include "freertos/portable.h"
-
-#include "rom/ets_sys.h"
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-/* Handler table is in xtensa_intr_asm.S */
-
-extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM*portNUM_PROCESSORS];
-
-
-/*
-  Default handler for unhandled exceptions.
-  CHANGED: We do this in panic.c now
-*/
-
-//void xt_unhandled_exception(XtExcFrame *frame)
-//{
-    //exit(-1);
-//}
-extern void xt_unhandled_exception(XtExcFrame *frame);
-
-
-/*
-  This function registers a handler for the specified exception.
-  The function returns the address of the previous handler.
-  On error, it returns 0.
-*/
-xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f)
-{
-    xt_exc_handler old;
-
-    if( n < 0 || n >= XCHAL_EXCCAUSE_NUM )
-        return 0;       /* invalid exception number */
-
-    /* Convert exception number to _xt_exception_table name */
-    n = n * portNUM_PROCESSORS + xPortGetCoreID();
-    old = _xt_exception_table[n];
-
-    if (f) {
-        _xt_exception_table[n] = f;
-    }
-    else {
-        _xt_exception_table[n] = &xt_unhandled_exception;
-    }
-
-    return ((old == &xt_unhandled_exception) ? 0 : old);
-}
-
-#endif
-
-#if XCHAL_HAVE_INTERRUPTS
-
-/* Handler table is in xtensa_intr_asm.S */
-
-typedef struct xt_handler_table_entry {
-    void * handler;
-    void * arg;
-} xt_handler_table_entry;
-
-extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS];
-
-
-/*
-  Default handler for unhandled interrupts.
-*/
-void xt_unhandled_interrupt(void * arg)
-{
-	ets_printf("Unhandled interrupt %d on cpu %d!\n", (int)arg, xPortGetCoreID());
-}
-
-
-/*
-  This function registers a handler for the specified interrupt. The "arg"
-  parameter specifies the argument to be passed to the handler when it is
-  invoked. The function returns the address of the previous handler.
-  On error, it returns 0.
-*/
-xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg)
-{
-    xt_handler_table_entry * entry;
-    xt_handler               old;
-
-    if( n < 0 || n >= XCHAL_NUM_INTERRUPTS )
-        return 0;       /* invalid interrupt number */
-    if( Xthal_intlevel[n] > XCHAL_EXCM_LEVEL )
-        return 0;       /* priority level too high to safely handle in C */
-
-    /* Convert exception number to _xt_exception_table name */
-    n = n * portNUM_PROCESSORS + xPortGetCoreID();
-
-    entry = _xt_interrupt_table + n;
-    old   = entry->handler;
-
-    if (f) {
-        entry->handler = f;
-        entry->arg     = arg;
-    }
-    else {
-        entry->handler = &xt_unhandled_interrupt;
-        entry->arg     = (void*)n;
-    }
-
-    return ((old == &xt_unhandled_interrupt) ? 0 : old);
-}
-
-#if CONFIG_SYSVIEW_ENABLE
-void * xt_get_interrupt_handler_arg(int n)
-{
-    xt_handler_table_entry * entry;
-
-    if( n < 0 || n >= XCHAL_NUM_INTERRUPTS )
-        return 0;       /* invalid interrupt number */
-
-    /* Convert exception number to _xt_exception_table name */
-    n = n * portNUM_PROCESSORS + xPortGetCoreID();
-
-    entry = _xt_interrupt_table + n;
-    return entry->arg;
-}
-#endif
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr_asm.S b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr_asm.S
deleted file mode 100755
index f2d2361..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_intr_asm.S
+++ /dev/null
@@ -1,225 +0,0 @@
-/*******************************************************************************
-Copyright (c) 2006-2015 Cadence Design Systems Inc.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice shall be included
-in all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-******************************************************************************/
-
-/******************************************************************************
-  Xtensa interrupt handling data and assembly routines.
-  Also see xtensa_intr.c and xtensa_vectors.S.
-******************************************************************************/
-
-#include 
-#include 
-
-#include "xtensa_context.h"
-#include "FreeRTOSConfig.h"
-
-#if XCHAL_HAVE_INTERRUPTS
-
-/*
--------------------------------------------------------------------------------
-  INTENABLE virtualization information.
--------------------------------------------------------------------------------
-*/
-
-
-#if XT_USE_SWPRI
-/* Warning - this is not multicore-compatible. */
-    .data
-    .global _xt_intdata
-    .align  8
-_xt_intdata:
-    .global _xt_intenable
-    .type   _xt_intenable,@object
-    .size   _xt_intenable,4
-    .global _xt_vpri_mask
-    .type   _xt_vpri_mask,@object
-    .size   _xt_vpri_mask,4
-
-_xt_intenable:     .word   0             /* Virtual INTENABLE     */
-_xt_vpri_mask:     .word   0xFFFFFFFF    /* Virtual priority mask */
-#endif
-
-/*
--------------------------------------------------------------------------------
-  Table of C-callable interrupt handlers for each interrupt. Note that not all
-  slots can be filled, because interrupts at level > EXCM_LEVEL will not be
-  dispatched to a C handler by default.
-
-  Stored as:
-  int 0 cpu 0
-  int 0 cpu 1
-  ...
-  int 0 cpu n
-  int 1 cpu 0
-  int 1 cpu 1
-  etc
--------------------------------------------------------------------------------
-*/
-
-    .data
-    .global _xt_interrupt_table
-    .align  8
-
-_xt_interrupt_table:
-
-    .set    i, 0
-    .rept   XCHAL_NUM_INTERRUPTS*portNUM_PROCESSORS
-    .word   xt_unhandled_interrupt      /* handler address               */
-    .word   i                           /* handler arg (default: intnum) */
-    .set    i, i+1
-    .endr
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-/*
--------------------------------------------------------------------------------
-  Table of C-callable exception handlers for each exception. Note that not all
-  slots will be active, because some exceptions (e.g. coprocessor exceptions)
-  are always handled by the OS and cannot be hooked by user handlers.
-
-  Stored as:
-  exc 0 cpu 0
-  exc 0 cpu 1
-  ...
-  exc 0 cpu n
-  exc 1 cpu 0
-  exc 1 cpu 1
-  etc
--------------------------------------------------------------------------------
-*/
-
-    .data
-    .global _xt_exception_table
-    .align  4
-
-_xt_exception_table:
-    .rept   XCHAL_EXCCAUSE_NUM * portNUM_PROCESSORS
-    .word   xt_unhandled_exception    /* handler address */
-    .endr
-
-#endif
-
-
-/*
--------------------------------------------------------------------------------
-  unsigned int xt_ints_on ( unsigned int mask )
-
-  Enables a set of interrupts. Does not simply set INTENABLE directly, but
-  computes it as a function of the current virtual priority if XT_USE_SWPRI is
-  enabled.
-  Can be called from interrupt handlers.
--------------------------------------------------------------------------------
-*/
-
-    .text
-    .align  4
-    .global xt_ints_on
-    .type   xt_ints_on,@function
-
-xt_ints_on:
-
-    ENTRY0
-
-#if XCHAL_HAVE_INTERRUPTS
-#if XT_USE_SWPRI
-    movi    a3, 0
-    movi    a4, _xt_intdata
-    xsr     a3, INTENABLE        /* Disables all interrupts   */
-    rsync
-    l32i    a3, a4, 0            /* a3 = _xt_intenable        */
-    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask        */
-    or      a5, a3, a2           /* a5 = _xt_intenable | mask */
-    s32i    a5, a4, 0            /* _xt_intenable |= mask     */
-    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
-    wsr     a5, INTENABLE        /* Reenable interrupts       */
-    mov     a2, a3               /* Previous mask             */
-#else
-    movi    a3, 0
-    xsr     a3, INTENABLE        /* Disables all interrupts   */
-    rsync
-    or      a2, a3, a2           /* set bits in mask */
-    wsr     a2, INTENABLE        /* Re-enable ints */
-    rsync
-    mov     a2, a3               /* return prev mask */
-#endif
-#else
-    movi    a2, 0                /* Return zero */
-#endif
-    RET0
-
-    .size   xt_ints_on, . - xt_ints_on
-
-
-/*
--------------------------------------------------------------------------------
-  unsigned int xt_ints_off ( unsigned int mask )
-
-  Disables a set of interrupts. Does not simply set INTENABLE directly,
-  but computes it as a function of the current virtual priority if XT_USE_SWPRI is
-  enabled.
-  Can be called from interrupt handlers.
--------------------------------------------------------------------------------
-*/
-
-    .text
-    .align  4
-    .global xt_ints_off
-    .type   xt_ints_off,@function
-
-xt_ints_off:
-
-    ENTRY0
-#if XCHAL_HAVE_INTERRUPTS
-#if XT_USE_SWPRI
-    movi    a3, 0
-    movi    a4, _xt_intdata
-    xsr     a3, INTENABLE        /* Disables all interrupts    */
-    rsync
-    l32i    a3, a4, 0            /* a3 = _xt_intenable         */
-    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask         */
-    or      a5, a3, a2           /* a5 = _xt_intenable | mask  */
-    xor     a5, a5, a2           /* a5 = _xt_intenable & ~mask */
-    s32i    a5, a4, 0            /* _xt_intenable &= ~mask     */
-    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
-    wsr     a5, INTENABLE        /* Reenable interrupts        */
-    mov     a2, a3               /* Previous mask              */
-#else
-    movi    a4, 0
-    xsr     a4, INTENABLE        /* Disables all interrupts   */
-    rsync
-    or      a3, a4, a2           /* set bits in mask */
-    xor     a3, a3, a2           /* invert bits in mask set in mask, essentially clearing them */
-    wsr     a3, INTENABLE        /* Re-enable ints */
-    rsync
-    mov     a2, a4               /* return prev mask */
-#endif
-#else
-    movi    a2, 0                /* return zero */
-#endif
-    RET0
-
-    .size   xt_ints_off, . - xt_ints_off
-
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c
deleted file mode 100755
index a5ca23c..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_overlay_os_hook.c
+++ /dev/null
@@ -1,67 +0,0 @@
-// xtensa_overlay_os_hook.c -- Overlay manager OS hooks for FreeRTOS.
-
-// Copyright (c) 2015-2015 Cadence Design Systems Inc.
-//
-// Permission is hereby granted, free of charge, to any person obtaining
-// a copy of this software and associated documentation files (the
-// "Software"), to deal in the Software without restriction, including
-// without limitation the rights to use, copy, modify, merge, publish,
-// distribute, sublicense, and/or sell copies of the Software, and to
-// permit persons to whom the Software is furnished to do so, subject to
-// the following conditions:
-//
-// The above copyright notice and this permission notice shall be included
-// in all copies or substantial portions of the Software.
-//
-// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-// EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-// IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-// CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-// SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
-
-
-#include "FreeRTOS.h"
-#include "semphr.h"
-
-#if configUSE_MUTEX
-
-/* Mutex object that controls access to the overlay. Currently only one
- * overlay region is supported so one mutex suffices.
- */
-static SemaphoreHandle_t xt_overlay_mutex;
-
-
-/* This function should be overridden to provide OS specific init such
- * as the creation of a mutex lock that can be used for overlay locking.
- * Typically this mutex would be set up with priority inheritance. See
- * overlay manager documentation for more details.
- */
-void xt_overlay_init_os(void)
-{
-    /* Create the mutex for overlay access. Priority inheritance is
-     * required.
-     */
-    xt_overlay_mutex = xSemaphoreCreateMutex();
-}
-
-
-/* This function locks access to shared overlay resources, typically
- * by acquiring a mutex.
- */
-void xt_overlay_lock(void)
-{
-    xSemaphoreTake(xt_overlay_mutex, 0);
-}
-
-
-/* This function releases access to shared overlay resources, typically
- * by unlocking a mutex.
- */
-void xt_overlay_unlock(void)
-{
-    xSemaphoreGive(xt_overlay_mutex);
-}
-
-#endif
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S
deleted file mode 100755
index 592dc32..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vector_defaults.S
+++ /dev/null
@@ -1,164 +0,0 @@
-// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
-//
-// Licensed under the Apache License, Version 2.0 (the "License");
-// you may not use this file except in compliance with the License.
-// You may obtain a copy of the License at
-
-//     http://www.apache.org/licenses/LICENSE-2.0
-//
-// Unless required by applicable law or agreed to in writing, software
-// distributed under the License is distributed on an "AS IS" BASIS,
-// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-// See the License for the specific language governing permissions and
-// limitations under the License.
-
-#include "xtensa_rtos.h"
-#include "esp_panic.h"
-#include "sdkconfig.h"
-#include "soc/soc.h"
-
-/*
-This file contains the default handlers for the high interrupt levels as well as some specialized exceptions. 
-The default behaviour is to just exit the interrupt or call the panic handler on the exceptions
-*/
-
-
-#if XCHAL_HAVE_DEBUG
-    .global    xt_debugexception
-    .weak xt_debugexception
-    .set xt_debugexception, _xt_debugexception
-    .section .iram1,"ax"
-    .type       _xt_debugexception,@function
-    .align      4
-
-_xt_debugexception:
-    movi    a0,PANIC_RSN_DEBUGEXCEPTION
-    wsr     a0,EXCCAUSE
-    /* _xt_panic assumes a level 1 exception. As we're
-       crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL
-       to level 1. */
-    rsr     a0,(EPC + XCHAL_DEBUGLEVEL)
-    wsr     a0,EPC_1
-    rsr     a0,(EXCSAVE + XCHAL_DEBUGLEVEL)
-    wsr     a0,EXCSAVE_1
-    call0   _xt_panic                       /* does not return */
-    rfi     XCHAL_DEBUGLEVEL
-
-#endif /* Debug exception */
-
-
-#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
-    .global    xt_highint2
-    .weak xt_highint2
-    .set xt_highint2, _xt_highint2
-    .section .iram1,"ax"
-    .type       _xt_highint2,@function
-    .align      4
-_xt_highint2:
-
-    /* Default handler does nothing; just returns */
-    .align  4
-.L_xt_highint2_exit:
-    rsr     a0, EXCSAVE_2                   /* restore a0 */
-    rfi     2
-
-#endif  /* Level 2 */
-
-#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
-
-    .global    xt_highint3
-    .weak xt_highint3
-    .set xt_highint3, _xt_highint3
-    .section .iram1,"ax"
-    .type       _xt_highint3,@function
-    .align      4
-_xt_highint3:
-
-    /* Default handler does nothing; just returns */
-
-    .align  4
-.L_xt_highint3_exit:
-    rsr     a0, EXCSAVE_3                   /* restore a0 */
-    rfi     3
-
-#endif  /* Level 3 */
-
-#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
-
-    .global    xt_highint4
-    .weak xt_highint4
-    .set xt_highint4, _xt_highint4
-    .section .iram1,"ax"
-    .type       _xt_highint4,@function
-    .align      4
-_xt_highint4:
-
-    /* Default handler does nothing; just returns */
-
-    .align  4
-.L_xt_highint4_exit:
-    rsr     a0, EXCSAVE_4                   /* restore a0 */
-    rfi     4
-
-#endif  /* Level 4 */
-
-#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
-
-    .global    xt_highint5
-    .weak xt_highint5
-    .set xt_highint5, _xt_highint5
-    .section .iram1,"ax"
-    .type       _xt_highint5,@function
-    .align      4
-_xt_highint5:
-
-    /* Default handler does nothing; just returns */
-
-    .align  4
-.L_xt_highint5_exit:
-    rsr     a0, EXCSAVE_5                   /* restore a0 */
-    rfi     5
-
-
-#endif  /* Level 5 */
-
-#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
-
-    .global    _xt_highint6
-    .global    xt_highint6
-    .weak xt_highint6
-    .set xt_highint6, _xt_highint6
-    .section .iram1,"ax"
-    .type       _xt_highint6,@function
-    .align      4
-_xt_highint6:
-
-    /* Default handler does nothing; just returns */
-
-    .align  4
-.L_xt_highint6_exit:
-    rsr     a0, EXCSAVE_6                   /* restore a0 */
-    rfi     6
-
-#endif  /* Level 6 */
-
-#if XCHAL_HAVE_NMI
-
-    .global    _xt_nmi
-    .global    xt_nmi
-    .weak xt_nmi
-    .set xt_nmi, _xt_nmi
-    .section .iram1,"ax"
-    .type       _xt_nmi,@function
-    .align      4
-_xt_nmi:
-
-    /* Default handler does nothing; just returns */
-
-    .align  4
-.L_xt_nmi_exit:
-    rsr     a0, EXCSAVE + XCHAL_NMILEVEL    /* restore a0 */
-    rfi     XCHAL_NMILEVEL
-
-#endif  /* NMI */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S b/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S
deleted file mode 100755
index b023837..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/GCC/Xtensa_ESP32/xtensa_vectors.S
+++ /dev/null
@@ -1,1891 +0,0 @@
-/*******************************************************************************
-Copyright (c) 2006-2015 Cadence Design Systems Inc.
-
-Permission is hereby granted, free of charge, to any person obtaining
-a copy of this software and associated documentation files (the
-"Software"), to deal in the Software without restriction, including
-without limitation the rights to use, copy, modify, merge, publish,
-distribute, sublicense, and/or sell copies of the Software, and to
-permit persons to whom the Software is furnished to do so, subject to
-the following conditions:
-
-The above copyright notice and this permission notice shall be included
-in all copies or substantial portions of the Software.
-
-THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
-EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
-MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
-IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
-CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
-TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
-SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
---------------------------------------------------------------------------------
-
-        XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS
-
-  Xtensa low level exception and interrupt vectors and handlers for an RTOS.
-
-  Interrupt handlers and user exception handlers support interaction with
-  the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and
-  after user's specific interrupt handlers. These macros are defined in
-  xtensa_.h to call suitable functions in a specific RTOS.
-
-  Users can install application-specific interrupt handlers for low and
-  medium level interrupts, by calling xt_set_interrupt_handler(). These
-  handlers can be written in C, and must obey C calling convention. The
-  handler table is indexed by the interrupt number. Each handler may be
-  provided with an argument. 
-
-  Note that the system timer interrupt is handled specially, and is
-  dispatched to the RTOS-specific handler. This timer cannot be hooked
-  by application code.
-
-  Optional hooks are also provided to install a handler per level at 
-  run-time, made available by compiling this source file with 
-  '-DXT_INTEXC_HOOKS' (useful for automated testing).
-
-!!  This file is a template that usually needs to be modified to handle       !!
-!!  application specific interrupts. Search USER_EDIT for helpful comments    !!
-!!  on where to insert handlers and how to write them.                        !!
-
-  Users can also install application-specific exception handlers in the
-  same way, by calling xt_set_exception_handler(). One handler slot is
-  provided for each exception type. Note that some exceptions are handled
-  by the porting layer itself, and cannot be taken over by application
-  code in this manner. These are the alloca, syscall, and coprocessor
-  exceptions.
-
-  The exception handlers can be written in C, and must follow C calling
-  convention. Each handler is passed a pointer to an exception frame as
-  its single argument. The exception frame is created on the stack, and
-  holds the saved context of the thread that took the exception. If the
-  handler returns, the context will be restored and the instruction that
-  caused the exception will be retried. If the handler makes any changes
-  to the saved state in the exception frame, the changes will be applied
-  when restoring the context.
-
-  Because Xtensa is a configurable architecture, this port supports all user
-  generated configurations (except restrictions stated in the release notes).
-  This is accomplished by conditional compilation using macros and functions
-  defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
-  Only the relevant parts of this file will be included in your RTOS build.
-  For example, this file provides interrupt vector templates for all types and
-  all priority levels, but only the ones in your configuration are built.
-
-  NOTES on the use of 'call0' for long jumps instead of 'j':
-   1. This file should be assembled with the -mlongcalls option to xt-xcc.
-   2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
-      a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the
-      distance from the call to the destination. The linker then relaxes
-      it back to 'call0 dest' if it determines that dest is within range.
-      This allows more flexibility in locating code without the performance
-      overhead of the 'l32r' literal data load in cases where the destination
-      is in range of 'call0'. There is an additional benefit in that 'call0'
-      has a longer range than 'j' due to the target being word-aligned, so 
-      the 'l32r' sequence is less likely needed.
-   3. The use of 'call0' with -mlongcalls requires that register a0 not be 
-      live at the time of the call, which is always the case for a function 
-      call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.
-   4. This use of 'call0' is independent of the C function call ABI.
-
-*******************************************************************************/
-
-#include "xtensa_rtos.h"
-#include "esp_panic.h"
-#include "sdkconfig.h"
-#include "soc/soc.h"
-#include "soc/dport_reg.h"
-
-/*
-  Define for workaround: pin no-cpu-affinity tasks to a cpu when fpu is used.
-  Please change this when the tcb structure is changed
-*/
-#define TASKTCB_XCOREID_OFFSET (0x38+configMAX_TASK_NAME_LEN+3)&~3
-.extern pxCurrentTCB
-
-/* Enable stack backtrace across exception/interrupt - see below */
-#ifdef CONFIG_FREERTOS_INTERRUPT_BACKTRACE
-#define XT_DEBUG_BACKTRACE    1
-#endif
-
-
-/*
---------------------------------------------------------------------------------
-  Defines used to access _xtos_interrupt_table.
---------------------------------------------------------------------------------
-*/
-#define XIE_HANDLER     0
-#define XIE_ARG         4
-#define XIE_SIZE        8
-
-
-/*
-  Macro get_percpu_entry_for - convert a per-core ID into a multicore entry.
-  Basically does reg=reg*portNUM_PROCESSORS+current_core_id
-  Multiple versions here to optimize for specific portNUM_PROCESSORS values.
-*/
-    .macro get_percpu_entry_for reg scratch
-#if (portNUM_PROCESSORS == 1)
-    /* No need to do anything */
-#elif  (portNUM_PROCESSORS == 2)
-    /* Optimized 2-core code. */
-    getcoreid \scratch
-    addx2 \reg,\reg,\scratch
-#else
-    /* Generalized n-core code. Untested! */
-    movi \scratch,portNUM_PROCESSORS
-    mull \scratch,\reg,\scratch
-    getcoreid \reg
-    add \reg,\scratch,\reg
-#endif
-   .endm
-/*
---------------------------------------------------------------------------------
-  Macro extract_msb - return the input with only the highest bit set.
-
-  Input  : "ain"  - Input value, clobbered.
-  Output : "aout" - Output value, has only one bit set, MSB of "ain".
-  The two arguments must be different AR registers.
---------------------------------------------------------------------------------
-*/
-
-    .macro  extract_msb     aout ain
-1:
-    addi    \aout, \ain, -1         /* aout = ain - 1        */
-    and     \ain, \ain, \aout       /* ain  = ain & aout     */
-    bnez    \ain, 1b                /* repeat until ain == 0 */
-    addi    \aout, \aout, 1         /* return aout + 1       */
-    .endm
-
-/*
---------------------------------------------------------------------------------
-  Macro dispatch_c_isr - dispatch interrupts to user ISRs.
-  This will dispatch to user handlers (if any) that are registered in the
-  XTOS dispatch table (_xtos_interrupt_table). These handlers would have
-  been registered by calling _xtos_set_interrupt_handler(). There is one
-  exception - the timer interrupt used by the OS will not be dispatched
-  to a user handler - this must be handled by the caller of this macro.
-
-  Level triggered and software interrupts are automatically deasserted by
-  this code.
-
-  ASSUMPTIONS:
-    -- PS.INTLEVEL is set to "level" at entry
-    -- PS.EXCM = 0, C calling enabled
-
-  NOTE: For CALL0 ABI, a12-a15 have not yet been saved.
-
-  NOTE: This macro will use registers a0 and a2-a7. The arguments are:
-    level -- interrupt level
-    mask  -- interrupt bitmask for this level
---------------------------------------------------------------------------------
-*/
-
-    .macro  dispatch_c_isr    level  mask
-
-    #ifdef CONFIG_PM_TRACE
-    movi a6, 0 /* = ESP_PM_TRACE_IDLE */
-    getcoreid a7
-    call4 esp_pm_trace_exit
-    #endif // CONFIG_PM_TRACE
-
-    /* Get mask of pending, enabled interrupts at this level into a2. */
-
-.L_xt_user_int_&level&:
-    rsr     a2, INTENABLE
-    rsr     a3, INTERRUPT
-    movi    a4, \mask
-    and     a2, a2, a3
-    and     a2, a2, a4
-    beqz    a2, 9f                          /* nothing to do */
-
-    /* This bit of code provides a nice debug backtrace in the debugger.
-       It does take a few more instructions, so undef XT_DEBUG_BACKTRACE
-       if you want to save the cycles.
-    */
-    #ifdef XT_DEBUG_BACKTRACE
-    #ifndef __XTENSA_CALL0_ABI__
-    rsr     a0, EPC_1 + \level - 1          /* return address */
-    movi    a4, 0xC0000000                  /* constant with top 2 bits set (call size) */
-    or      a0, a0, a4                      /* set top 2 bits */
-    addx2   a0, a4, a0                      /* clear top bit -- simulating call4 size   */
-    #endif
-    #endif
-
-    #ifdef CONFIG_PM_ENABLE
-    call4 esp_pm_impl_isr_hook
-    #endif
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a4, _xt_intexc_hooks
-    l32i    a4, a4, \level << 2
-    beqz    a4, 2f
-    #ifdef __XTENSA_CALL0_ABI__
-    callx0  a4
-    beqz    a2, 9f
-    #else
-    mov     a6, a2
-    callx4  a4
-    beqz    a6, 9f
-    mov     a2, a6
-    #endif
-2:
-    #endif
-
-    /* Now look up in the dispatch table and call user ISR if any. */
-    /* If multiple bits are set then MSB has highest priority.     */
-
-    extract_msb  a4, a2                     /* a4 = MSB of a2, a2 trashed */
-
-    #ifdef XT_USE_SWPRI
-    /* Enable all interrupts at this level that are numerically higher
-       than the one we just selected, since they are treated as higher
-       priority.
-    */
-    movi    a3, \mask                       /* a3 = all interrupts at this level */
-    add     a2, a4, a4                      /* a2 = a4 << 1 */
-    addi    a2, a2, -1                      /* a2 = mask of 1's <= a4 bit */
-    and     a2, a2, a3                      /* a2 = mask of all bits <= a4 at this level */
-    movi    a3, _xt_intdata
-    l32i    a6, a3, 4                       /* a6 = _xt_vpri_mask */
-    neg     a2, a2
-    addi    a2, a2, -1                      /* a2 = mask to apply */
-    and     a5, a6, a2                      /* mask off all bits <= a4 bit */
-    s32i    a5, a3, 4                       /* update _xt_vpri_mask */
-    rsr     a3, INTENABLE
-    and     a3, a3, a2                      /* mask off all bits <= a4 bit */
-    wsr     a3, INTENABLE
-    rsil    a3, \level - 1                  /* lower interrupt level by 1 */
-    #endif
-
-    movi    a3, XT_TIMER_INTEN              /* a3 = timer interrupt bit */
-    wsr     a4, INTCLEAR                    /* clear sw or edge-triggered interrupt */
-    beq     a3, a4, 7f                      /* if timer interrupt then skip table */
-
-    find_ms_setbit a3, a4, a3, 0            /* a3 = interrupt number */
-
-    get_percpu_entry_for a3, a12
-    movi    a4, _xt_interrupt_table
-    addx8   a3, a3, a4                      /* a3 = address of interrupt table entry */
-    l32i    a4, a3, XIE_HANDLER             /* a4 = handler address */
-    #ifdef __XTENSA_CALL0_ABI__
-    mov     a12, a6                         /* save in callee-saved reg */
-    l32i    a2, a3, XIE_ARG                 /* a2 = handler arg */
-    callx0  a4                              /* call handler */
-    mov     a2, a12
-    #else
-    mov     a2, a6                          /* save in windowed reg */
-    l32i    a6, a3, XIE_ARG                 /* a6 = handler arg */
-    callx4  a4                              /* call handler */
-    #endif
-
-    #ifdef XT_USE_SWPRI
-    j       8f
-    #else
-    j       .L_xt_user_int_&level&          /* check for more interrupts */
-    #endif
-
-7:
-
-    .ifeq XT_TIMER_INTPRI - \level
-.L_xt_user_int_timer_&level&:
-    /*
-    Interrupt handler for the RTOS tick timer if at this level.
-    We'll be reading the interrupt state again after this call
-    so no need to preserve any registers except a6 (vpri_mask).
-    */
-
-    #ifdef __XTENSA_CALL0_ABI__
-    mov     a12, a6
-    call0   XT_RTOS_TIMER_INT
-    mov     a2, a12
-    #else
-    mov     a2, a6
-    call4   XT_RTOS_TIMER_INT
-    #endif
-    .endif
-
-    #ifdef XT_USE_SWPRI
-    j       8f
-    #else
-    j       .L_xt_user_int_&level&          /* check for more interrupts */
-    #endif
-
-    #ifdef XT_USE_SWPRI
-8:
-    /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from
-       virtual _xt_intenable which _could_ have changed during interrupt
-       processing. */
-
-    movi    a3, _xt_intdata
-    l32i    a4, a3, 0                       /* a4 = _xt_intenable    */
-    s32i    a2, a3, 4                       /* update _xt_vpri_mask  */
-    and     a4, a4, a2                      /* a4 = masked intenable */
-    wsr     a4, INTENABLE                   /* update INTENABLE      */
-    #endif
-
-9:
-    /* done */
-
-    .endm
-
-
-/*
---------------------------------------------------------------------------------
-  Panic handler.
-  Should be reached by call0 (preferable) or jump only. If call0, a0 says where 
-  from. If on simulator, display panic message and abort, else loop indefinitely.
---------------------------------------------------------------------------------
-*/
-
-    .section .iram1,"ax"
-    .global panicHandler
-
-    .global     _xt_panic
-    .type       _xt_panic,@function
-    .align      4
-    .literal_position
-    .align      4
-
-_xt_panic:
-    /* Allocate exception frame and save minimal context. */
-    mov     a0, sp
-    addi    sp, sp, -XT_STK_FRMSZ
-    s32i    a0, sp, XT_STK_A1
-    #if XCHAL_HAVE_WINDOWED
-    s32e    a0, sp, -12                     /* for debug backtrace */
-    #endif
-    rsr     a0, PS                          /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_1                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    #if XCHAL_HAVE_WINDOWED
-    s32e    a0, sp, -16                     /* for debug backtrace */
-    #endif
-    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
-    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
-    call0   _xt_context_save
-
-    /* Save exc cause and vaddr into exception frame */
-    rsr     a0, EXCCAUSE
-    s32i    a0, sp, XT_STK_EXCCAUSE
-    rsr     a0, EXCVADDR
-    s32i    a0, sp, XT_STK_EXCVADDR
-
-    /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
-    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
-
-    s32i    a0, sp, XT_STK_A0
-
-    /* Set up PS for C, disable all interrupts except NMI and debug, and clear EXCM. */
-    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
-    wsr     a0, PS
-
-    //Call panic handler
-    mov     a6,sp
-    call4 panicHandler
-
-
-    .align 4
-//Call using call0. Prints the hex char in a2. Kills a3, a4, a5
-panic_print_hex:
-    movi a3,0x60000000
-    movi a4,8
-panic_print_hex_loop:
-    l32i a5, a3, 0x1c
-    extui a5, a5, 16, 8
-    bgei a5,64,panic_print_hex_loop
-
-    srli a5,a2,28
-    bgei a5,10,panic_print_hex_a
-    addi a5,a5,'0'
-    j panic_print_hex_ok
-panic_print_hex_a:
-    addi a5,a5,'A'-10
-panic_print_hex_ok:
-    s32i a5,a3,0
-    slli a2,a2,4
-    
-    addi a4,a4,-1
-    bnei a4,0,panic_print_hex_loop
-    movi a5,' '
-    s32i a5,a3,0
-
-    ret
-
-
-
-    .section    .rodata, "a"
-    .align      4
-
-
-
-/*
---------------------------------------------------------------------------------
-    Hooks to dynamically install handlers for exceptions and interrupts.
-    Allows automated regression frameworks to install handlers per test.
-    Consists of an array of function pointers indexed by interrupt level, 
-    with index 0 containing the entry for user exceptions.
-    Initialized with all 0s, meaning no handler is installed at each level.
-    See comment in xtensa_rtos.h for more details.
-
-    *WARNING*  This array is for all CPUs, that is, installing a hook for 
-    one CPU will install it for all others as well!
---------------------------------------------------------------------------------
-*/
-
-    #ifdef XT_INTEXC_HOOKS
-    .data
-    .global     _xt_intexc_hooks
-    .type       _xt_intexc_hooks,@object
-    .align      4
-
-_xt_intexc_hooks:
-    .fill       XT_INTEXC_HOOK_NUM, 4, 0
-    #endif
-
-
-/*
---------------------------------------------------------------------------------
-  EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS
-  (except window exception vectors).
-
-  Each vector goes at a predetermined location according to the Xtensa
-  hardware configuration, which is ensured by its placement in a special
-  section known to the Xtensa linker support package (LSP). It performs
-  the minimum necessary before jumping to the handler in the .text section.
-
-  The corresponding handler goes in the normal .text section. It sets up
-  the appropriate stack frame, saves a few vector-specific registers and
-  calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
-  and enter the RTOS, then sets up a C environment. It then calls the
-  user's interrupt handler code (which may be coded in C) and finally 
-  calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
-
-  While XT_RTOS_INT_EXIT does not return directly to the interruptee,
-  eventually the RTOS scheduler will want to dispatch the interrupted
-  task or handler. The scheduler will return to the exit point that was
-  saved in the interrupt stack frame at XT_STK_EXIT.
---------------------------------------------------------------------------------
-*/
-
-
-/*
---------------------------------------------------------------------------------
-Debug Exception.
---------------------------------------------------------------------------------
-*/
-
-#if XCHAL_HAVE_DEBUG
-
-    .begin      literal_prefix .DebugExceptionVector
-    .section    .DebugExceptionVector.text, "ax"
-    .global     _DebugExceptionVector
-    .align      4
-    .global     xt_debugexception
-_DebugExceptionVector:
-    wsr     a0, EXCSAVE+XCHAL_DEBUGLEVEL    /* preserve a0 */
-    call0   xt_debugexception            /* load exception handler */
-
-    .end        literal_prefix
-
-#endif
-
-/*
---------------------------------------------------------------------------------
-Double Exception.
-Double exceptions are not a normal occurrence. They indicate a bug of some kind.
---------------------------------------------------------------------------------
-*/
-
-#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
-
-    .begin      literal_prefix .DoubleExceptionVector
-    .section    .DoubleExceptionVector.text, "ax"
-    .global     _DoubleExceptionVector
-    .align      4
-
-_DoubleExceptionVector:
-
-    #if XCHAL_HAVE_DEBUG
-    break   1, 4                            /* unhandled double exception */
-    #endif
-    movi    a0,PANIC_RSN_DOUBLEEXCEPTION
-    wsr     a0,EXCCAUSE
-    call0   _xt_panic                       /* does not return */
-    rfde                                    /* make a0 point here not later */
-
-    .end        literal_prefix
-
-#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */
-
-/*
---------------------------------------------------------------------------------
-Kernel Exception (including Level 1 Interrupt from kernel mode).
---------------------------------------------------------------------------------
-*/
-
-    .begin      literal_prefix .KernelExceptionVector
-    .section    .KernelExceptionVector.text, "ax"
-    .global     _KernelExceptionVector
-    .align      4
-
-_KernelExceptionVector:
-
-    wsr     a0, EXCSAVE_1                   /* preserve a0 */
-    call0   _xt_kernel_exc                  /* kernel exception handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .section .iram1,"ax"
-    .align      4
-
-_xt_kernel_exc:
-    #if XCHAL_HAVE_DEBUG
-    break   1, 0                            /* unhandled kernel exception */
-    #endif
-    movi    a0,PANIC_RSN_KERNELEXCEPTION
-    wsr     a0,EXCCAUSE
-    call0   _xt_panic                       /* does not return */
-    rfe                                     /* make a0 point here not there */
-
-
-/*
---------------------------------------------------------------------------------
-User Exception (including Level 1 Interrupt from user mode).
---------------------------------------------------------------------------------
-*/
-
-    .begin      literal_prefix .UserExceptionVector
-    .section    .UserExceptionVector.text, "ax"
-    .global     _UserExceptionVector
-    .type       _UserExceptionVector,@function
-    .align      4
-
-_UserExceptionVector:
-
-    wsr     a0, EXCSAVE_1                   /* preserve a0 */
-    call0   _xt_user_exc                    /* user exception handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-/*
---------------------------------------------------------------------------------
-  Insert some waypoints for jumping beyond the signed 8-bit range of
-  conditional branch instructions, so the conditional branchces to specific
-  exception handlers are not taken in the mainline. Saves some cycles in the
-  mainline.
---------------------------------------------------------------------------------
-*/
-
-    .section .iram1,"ax"
-
-    #if XCHAL_HAVE_WINDOWED
-    .align      4
-_xt_to_alloca_exc:
-    call0   _xt_alloca_exc                  /* in window vectors section */
-    /* never returns here - call0 is used as a jump (see note at top) */
-    #endif
-
-    .align      4
-_xt_to_syscall_exc:
-    call0   _xt_syscall_exc
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    #if XCHAL_CP_NUM > 0
-    .align      4
-_xt_to_coproc_exc:
-    call0   _xt_coproc_exc
-    /* never returns here - call0 is used as a jump (see note at top) */
-    #endif
-
-
-/*
---------------------------------------------------------------------------------
-  User exception handler.
---------------------------------------------------------------------------------
-*/
-
-    .type       _xt_user_exc,@function
-    .align      4
-
-_xt_user_exc:
-
-    /* If level 1 interrupt then jump to the dispatcher */
-    rsr     a0, EXCCAUSE
-    beqi    a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1
-
-    /* Handle any coprocessor exceptions. Rely on the fact that exception
-       numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors.
-    */
-    #if XCHAL_CP_NUM > 0
-    bgeui   a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc
-    #endif
-
-    /* Handle alloca and syscall exceptions */
-    #if XCHAL_HAVE_WINDOWED
-    beqi    a0, EXCCAUSE_ALLOCA,  _xt_to_alloca_exc
-    #endif
-    beqi    a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc
-
-    /* Handle all other exceptions. All can have user-defined handlers. */
-    /* NOTE: we'll stay on the user stack for exception handling.       */
-
-    /* Allocate exception frame and save minimal context. */
-    mov     a0, sp
-    addi    sp, sp, -XT_STK_FRMSZ
-    s32i    a0, sp, XT_STK_A1
-    #if XCHAL_HAVE_WINDOWED
-    s32e    a0, sp, -12                     /* for debug backtrace */
-    #endif
-    rsr     a0, PS                          /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_1                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    #if XCHAL_HAVE_WINDOWED
-    s32e    a0, sp, -16                     /* for debug backtrace */
-    #endif
-    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
-    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
-    call0   _xt_context_save
-
-    /* Save exc cause and vaddr into exception frame */
-    rsr     a0, EXCCAUSE
-    s32i    a0, sp, XT_STK_EXCCAUSE
-    rsr     a0, EXCVADDR
-    s32i    a0, sp, XT_STK_EXCVADDR
-
-    /* _xt_context_save seems to save the current a0, but we need the interuptees a0. Fix this. */
-    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-
-    /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-
-    #ifdef XT_DEBUG_BACKTRACE
-    #ifndef __XTENSA_CALL0_ABI__
-    rsr     a0, EPC_1                       /* return address for debug backtrace */
-    movi    a5, 0xC0000000                  /* constant with top 2 bits set (call size) */
-    rsync                                   /* wait for WSR.PS to complete */
-    or      a0, a0, a5                      /* set top 2 bits */
-    addx2   a0, a5, a0                      /* clear top bit -- thus simulating call4 size */
-    #else
-    rsync                                   /* wait for WSR.PS to complete */
-    #endif
-    #endif
-
-    rsr     a2, EXCCAUSE                    /* recover exc cause */
-
-    #ifdef XT_INTEXC_HOOKS
-    /*
-    Call exception hook to pre-handle exceptions (if installed).
-    Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling).
-    */
-    movi    a4, _xt_intexc_hooks
-    l32i    a4, a4, 0                       /* user exception hook index 0 */
-    beqz    a4, 1f
-.Ln_xt_user_exc_call_hook:
-    #ifdef __XTENSA_CALL0_ABI__
-    callx0  a4
-    beqi    a2, -1, .L_xt_user_done
-    #else
-    mov     a6, a2
-    callx4  a4
-    beqi    a6, -1, .L_xt_user_done
-    mov     a2, a6
-    #endif
-1:
-    #endif
-
-    rsr     a2, EXCCAUSE                    /* recover exc cause */
-    movi    a3, _xt_exception_table
-    get_percpu_entry_for a2, a4
-    addx4   a4, a2, a3                      /* a4 = address of exception table entry */
-    l32i    a4, a4, 0                       /* a4 = handler address */
-    #ifdef __XTENSA_CALL0_ABI__
-    mov     a2, sp                          /* a2 = pointer to exc frame */
-    callx0  a4                              /* call handler */
-    #else
-    mov     a6, sp                          /* a6 = pointer to exc frame */
-    callx4  a4                              /* call handler */
-    #endif
-
-.L_xt_user_done:
-
-    /* Restore context and return */
-    call0   _xt_context_restore
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, PS
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_1
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove exception frame */
-    rsync                                   /* ensure PS and EPC written */
-    rfe                                     /* PS.EXCM is cleared */
-
-
-/*
---------------------------------------------------------------------------------
-  Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-  on entry and used to return to a thread or interrupted interrupt handler.
---------------------------------------------------------------------------------
-*/
-
-    .global     _xt_user_exit
-    .type       _xt_user_exit,@function
-    .align      4
-_xt_user_exit:
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, PS
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_1
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure PS and EPC written */
-    rfe                                     /* PS.EXCM is cleared */
-
-
-/*
-
---------------------------------------------------------------------------------
-Syscall Exception Handler (jumped to from User Exception Handler).
-Syscall 0 is required to spill the register windows (no-op in Call 0 ABI).
-Only syscall 0 is handled here. Other syscalls return -1 to caller in a2.
---------------------------------------------------------------------------------
-*/
-
-    .section .iram1,"ax"
-    .type       _xt_syscall_exc,@function
-    .align      4
-_xt_syscall_exc:
-
-    #ifdef __XTENSA_CALL0_ABI__
-    /*
-    Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI.
-    Use a minimal stack frame (16B) to save A2 & A3 for scratch.
-    PS.EXCM could be cleared here, but unlikely to improve worst-case latency.
-    rsr     a0, PS
-    addi    a0, a0, -PS_EXCM_MASK
-    wsr     a0, PS
-    */
-    addi    sp, sp, -16
-    s32i    a2, sp, 8
-    s32i    a3, sp, 12
-    #else   /* Windowed ABI */
-    /*
-    Save necessary context and spill the register windows.
-    PS.EXCM is still set and must remain set until after the spill.
-    Reuse context save function though it saves more than necessary.
-    For this reason, a full interrupt stack frame is allocated.
-    */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
-    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
-    call0   _xt_context_save
-    #endif
-
-    /*
-    Grab the interruptee's PC and skip over the 'syscall' instruction.
-    If it's at the end of a zero-overhead loop and it's not on the last
-    iteration, decrement loop counter and skip to beginning of loop.
-    */
-    rsr     a2, EPC_1                       /* a2 = PC of 'syscall' */
-    addi    a3, a2, 3                       /* ++PC                 */
-    #if XCHAL_HAVE_LOOPS
-    rsr     a0, LEND                        /* if (PC == LEND       */
-    bne     a3, a0, 1f
-    rsr     a0, LCOUNT                      /*     && LCOUNT != 0)  */
-    beqz    a0, 1f                          /* {                    */
-    addi    a0, a0, -1                      /*   --LCOUNT           */
-    rsr     a3, LBEG                        /*   PC = LBEG          */
-    wsr     a0, LCOUNT                      /* }                    */
-    #endif
-1:  wsr     a3, EPC_1                       /* update PC            */
-
-    /* Restore interruptee's context and return from exception. */
-    #ifdef __XTENSA_CALL0_ABI__
-    l32i    a2, sp, 8
-    l32i    a3, sp, 12
-    addi    sp, sp, 16
-    #else
-    call0   _xt_context_restore
-    addi    sp, sp, XT_STK_FRMSZ
-    #endif
-    movi    a0, -1
-    movnez  a2, a0, a2                      /* return -1 if not syscall 0 */
-    rsr     a0, EXCSAVE_1
-    rfe
-
-/*
---------------------------------------------------------------------------------
-Co-Processor Exception Handler (jumped to from User Exception Handler).
-These exceptions are generated by co-processor instructions, which are only
-allowed in thread code (not in interrupts or kernel code). This restriction is 
-deliberately imposed to reduce the burden of state-save/restore in interrupts.
---------------------------------------------------------------------------------
-*/
-#if XCHAL_CP_NUM > 0
-
-    .section .rodata, "a"
-
-/* Offset to CP n save area in thread's CP save area. */
-    .global _xt_coproc_sa_offset
-    .type   _xt_coproc_sa_offset,@object
-    .align  16                      /* minimize crossing cache boundaries */
-_xt_coproc_sa_offset:
-    .word   XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA
-    .word   XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA
-
-/* Bitmask for CP n's CPENABLE bit. */
-    .type   _xt_coproc_mask,@object
-    .align  16,,8                   /* try to keep it all in one cache line */
-    .set    i, 0
-_xt_coproc_mask:
-    .rept   XCHAL_CP_MAX
-    .long   (i<<16) | (1<= 2
-
-    .begin      literal_prefix .Level2InterruptVector
-    .section    .Level2InterruptVector.text, "ax"
-    .global     _Level2Vector
-    .type       _Level2Vector,@function
-    .align      4
-_Level2Vector:
-    wsr     a0, EXCSAVE_2                   /* preserve a0 */
-    call0   _xt_medint2                     /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .section .iram1,"ax"
-    .type       _xt_medint2,@function
-    .align      4
-_xt_medint2:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_2                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_2                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_2                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint2_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(2) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(2) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint2_exit
-    .type       _xt_medint2_exit,@function
-    .align      4
-_xt_medint2_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_2
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_2
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     2
-
-#endif  /* Level 2 */
-
-#if XCHAL_EXCM_LEVEL >= 3
-
-    .begin      literal_prefix .Level3InterruptVector
-    .section    .Level3InterruptVector.text, "ax"
-    .global     _Level3Vector
-    .type       _Level3Vector,@function
-    .align      4
-_Level3Vector:
-    wsr     a0, EXCSAVE_3                   /* preserve a0 */
-    call0   _xt_medint3                     /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .section .iram1,"ax"
-    .type       _xt_medint3,@function
-    .align      4
-_xt_medint3:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_3                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_3                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_3                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint3_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(3) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(3) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint3_exit
-    .type       _xt_medint3_exit,@function
-    .align      4
-_xt_medint3_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_3
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_3
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     3
-
-#endif  /* Level 3 */
-
-#if XCHAL_EXCM_LEVEL >= 4
-
-    .begin      literal_prefix .Level4InterruptVector
-    .section    .Level4InterruptVector.text, "ax"
-    .global     _Level4Vector
-    .type       _Level4Vector,@function
-    .align      4
-_Level4Vector:
-    wsr     a0, EXCSAVE_4                   /* preserve a0 */
-    call0   _xt_medint4                     /* load interrupt handler */
-
-    .end        literal_prefix
-
-    .section .iram1,"ax"
-    .type       _xt_medint4,@function
-    .align      4
-_xt_medint4:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_4                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_4                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_4                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint4_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(4) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(4) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint4_exit
-    .type       _xt_medint4_exit,@function
-    .align      4
-_xt_medint4_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_4
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_4
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     4
-
-#endif  /* Level 4 */
-
-#if XCHAL_EXCM_LEVEL >= 5
-
-    .begin      literal_prefix .Level5InterruptVector
-    .section    .Level5InterruptVector.text, "ax"
-    .global     _Level5Vector
-    .type       _Level5Vector,@function
-    .align      4
-_Level5Vector:
-    wsr     a0, EXCSAVE_5                   /* preserve a0 */
-    call0   _xt_medint5                     /* load interrupt handler */
-
-    .end        literal_prefix
-
-    .section .iram1,"ax"
-    .type       _xt_medint5,@function
-    .align      4
-_xt_medint5:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_5                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_5                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_5                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint5_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(5) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint5_exit
-    .type       _xt_medint5_exit,@function
-    .align      4
-_xt_medint5_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_5
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_5
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     5
-
-#endif  /* Level 5 */
-
-#if XCHAL_EXCM_LEVEL >= 6
-
-    .begin      literal_prefix .Level6InterruptVector
-    .section    .Level6InterruptVector.text, "ax"
-    .global     _Level6Vector
-    .type       _Level6Vector,@function
-    .align      4
-_Level6Vector:
-    wsr     a0, EXCSAVE_6                   /* preserve a0 */
-    call0   _xt_medint6                     /* load interrupt handler */
-
-    .end        literal_prefix
-
-    .section .iram1,"ax"
-    .type       _xt_medint6,@function
-    .align      4
-_xt_medint6:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_6                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_6                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_6                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint6_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(6) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(6) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint6_exit
-    .type       _xt_medint6_exit,@function
-    .align      4
-_xt_medint6_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_6
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_6
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     6
-
-#endif  /* Level 6 */
-
-
-/*******************************************************************************
-
-HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
-
-High priority interrupts are by definition those with priorities greater
-than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority
-interrupts cannot interact with the RTOS, that is they must save all regs
-they use and not call any RTOS function.
-
-A further restriction imposed by the Xtensa windowed architecture is that
-high priority interrupts must not modify the stack area even logically
-"above" the top of the interrupted stack (they need to provide their
-own stack or static save area).
-
-Cadence Design Systems recommends high priority interrupt handlers be coded in assembly
-and used for purposes requiring very short service times.
-
-Here are templates for high priority (level 2+) interrupt vectors.
-They assume only one interrupt per level to avoid the burden of identifying
-which interrupts at this level are pending and enabled. This allows for 
-minimum latency and avoids having to save/restore a2 in addition to a0.
-If more than one interrupt per high priority level is configured, this burden
-is on the handler which in any case must provide a way to save and restore
-registers it uses without touching the interrupted stack.
-
-Each vector goes at a predetermined location according to the Xtensa
-hardware configuration, which is ensured by its placement in a special
-section known to the Xtensa linker support package (LSP). It performs
-the minimum necessary before jumping to the handler in the .text section.
-
-*******************************************************************************/
-
-/*
-These stubs just call xt_highintX/xt_nmi to handle the real interrupt. Please define
-these in an external assembly source file. If these symbols are not defined anywhere
-else, the defaults in xtensa_vector_defaults.S are used.
-*/
-
-#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
-
-    .begin      literal_prefix .Level2InterruptVector
-    .section    .Level2InterruptVector.text, "ax"
-    .global     _Level2Vector
-    .type       _Level2Vector,@function
-    .global     xt_highint2
-    .align      4
-_Level2Vector:
-    wsr     a0, EXCSAVE_2                   /* preserve a0 */
-    call0   xt_highint2                    /* load interrupt handler */
-
-    .end        literal_prefix
-
-#endif  /* Level 2 */
-
-#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
-
-    .begin      literal_prefix .Level3InterruptVector
-    .section    .Level3InterruptVector.text, "ax"
-    .global     _Level3Vector
-    .type       _Level3Vector,@function
-    .global     xt_highint3
-    .align      4
-_Level3Vector:
-    wsr     a0, EXCSAVE_3                   /* preserve a0 */
-    call0   xt_highint3                    /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-#endif  /* Level 3 */
-
-#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
-
-    .begin      literal_prefix .Level4InterruptVector
-    .section    .Level4InterruptVector.text, "ax"
-    .global     _Level4Vector
-    .type       _Level4Vector,@function
-    .global     xt_highint4
-    .align      4
-_Level4Vector:
-    wsr     a0, EXCSAVE_4                   /* preserve a0 */
-    call0   xt_highint4                    /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-#endif  /* Level 4 */
-
-#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
-
-    .begin      literal_prefix .Level5InterruptVector
-    .section    .Level5InterruptVector.text, "ax"
-    .global     _Level5Vector
-    .type       _Level5Vector,@function
-    .global     xt_highint5
-    .align      4
-_Level5Vector:
-    wsr     a0, EXCSAVE_5                   /* preserve a0 */
-    call0   xt_highint5                    /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-#endif  /* Level 5 */
-
-#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
-
-    .begin      literal_prefix .Level6InterruptVector
-    .section    .Level6InterruptVector.text, "ax"
-    .global     _Level6Vector
-    .type       _Level6Vector,@function
-    .global     xt_highint6
-    .align      4
-_Level6Vector:
-    wsr     a0, EXCSAVE_6                   /* preserve a0 */
-    call0   xt_highint6                    /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-#endif  /* Level 6 */
-
-#if XCHAL_HAVE_NMI
-
-    .begin      literal_prefix .NMIExceptionVector
-    .section    .NMIExceptionVector.text, "ax"
-    .global     _NMIExceptionVector
-    .type       _NMIExceptionVector,@function
-    .global     xt_nmi
-    .align      4
-_NMIExceptionVector:
-    wsr     a0, EXCSAVE + XCHAL_NMILEVEL  _ /* preserve a0 */
-    call0   xt_nmi                         /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-#endif  /* NMI */
-
-
-/*******************************************************************************
-
-WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER
-
-Here is the code for each window overflow/underflow exception vector and 
-(interspersed) efficient code for handling the alloca exception cause.
-Window exceptions are handled entirely in the vector area and are very
-tight for performance. The alloca exception is also handled entirely in 
-the window vector area so comes at essentially no cost in code size.
-Users should never need to modify them and Cadence Design Systems recommends 
-they do not.
-
-Window handlers go at predetermined vector locations according to the
-Xtensa hardware configuration, which is ensured by their placement in a
-special section known to the Xtensa linker support package (LSP). Since
-their offsets in that section are always the same, the LSPs do not define
-a section per vector.
-
-These things are coded for XEA2 only (XEA1 is not supported).
-
-Note on Underflow Handlers:
-The underflow handler for returning from call[i+1] to call[i]
-must preserve all the registers from call[i+1]'s window.
-In particular, a0 and a1 must be preserved because the RETW instruction
-will be reexecuted (and may even underflow if an intervening exception
-has flushed call[i]'s registers).
-Registers a2 and up may contain return values.
-
-*******************************************************************************/
-
-#if XCHAL_HAVE_WINDOWED
-
-    .section .WindowVectors.text, "ax"
-
-/*
---------------------------------------------------------------------------------
-Window Overflow Exception for Call4.
-
-Invoked if a call[i] referenced a register (a4-a15)
-that contains data from ancestor call[j];
-call[j] had done a call4 to call[j+1].
-On entry here:
-    window rotated to call[j] start point;
-        a0-a3 are registers to be saved;
-        a4-a15 must be preserved;
-        a5 is call[j+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0x0
-    .global _WindowOverflow4
-_WindowOverflow4:
-
-    s32e    a0, a5, -16     /* save a0 to call[j+1]'s stack frame */
-    s32e    a1, a5, -12     /* save a1 to call[j+1]'s stack frame */
-    s32e    a2, a5,  -8     /* save a2 to call[j+1]'s stack frame */
-    s32e    a3, a5,  -4     /* save a3 to call[j+1]'s stack frame */
-    rfwo                    /* rotates back to call[i] position */
-
-/*
---------------------------------------------------------------------------------
-Window Underflow Exception for Call4
-
-Invoked by RETW returning from call[i+1] to call[i]
-where call[i]'s registers must be reloaded (not live in ARs);
-where call[i] had done a call4 to call[i+1].
-On entry here:
-        window rotated to call[i] start point;
-        a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
-        a4-a15 must be preserved (they are call[i+1].reg[0..11]);
-        a5 is call[i+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0x40
-    .global _WindowUnderflow4
-_WindowUnderflow4:
-
-    l32e    a0, a5, -16     /* restore a0 from call[i+1]'s stack frame */
-    l32e    a1, a5, -12     /* restore a1 from call[i+1]'s stack frame */
-    l32e    a2, a5,  -8     /* restore a2 from call[i+1]'s stack frame */
-    l32e    a3, a5,  -4     /* restore a3 from call[i+1]'s stack frame */
-    rfwu
-
-/*
---------------------------------------------------------------------------------
-Handle alloca exception generated by interruptee executing 'movsp'.
-This uses space between the window vectors, so is essentially "free".
-All interruptee's regs are intact except a0 which is saved in EXCSAVE_1,
-and PS.EXCM has been set by the exception hardware (can't be interrupted).
-The fact the alloca exception was taken means the registers associated with
-the base-save area have been spilled and will be restored by the underflow
-handler, so those 4 registers are available for scratch.
-The code is optimized to avoid unaligned branches and minimize cache misses.
---------------------------------------------------------------------------------
-*/
-
-    .align  4
-    .global _xt_alloca_exc
-_xt_alloca_exc:
-
-    rsr     a0, WINDOWBASE  /* grab WINDOWBASE before rotw changes it */
-    rotw    -1              /* WINDOWBASE goes to a4, new a0-a3 are scratch */
-    rsr     a2, PS
-    extui   a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
-    xor     a3, a3, a4      /* bits changed from old to current windowbase */
-    rsr     a4, EXCSAVE_1   /* restore original a0 (now in a4) */
-    slli    a3, a3, XCHAL_PS_OWB_SHIFT
-    xor     a2, a2, a3      /* flip changed bits in old window base */
-    wsr     a2, PS          /* update PS.OWB to new window base */
-    rsync
-
-    _bbci.l a4, 31, _WindowUnderflow4
-    rotw    -1              /* original a0 goes to a8 */
-    _bbci.l a8, 30, _WindowUnderflow8
-    rotw    -1
-    j               _WindowUnderflow12
-
-/*
---------------------------------------------------------------------------------
-Window Overflow Exception for Call8
-
-Invoked if a call[i] referenced a register (a4-a15)
-that contains data from ancestor call[j];
-call[j] had done a call8 to call[j+1].
-On entry here:
-    window rotated to call[j] start point;
-        a0-a7 are registers to be saved;
-        a8-a15 must be preserved;
-        a9 is call[j+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0x80
-    .global _WindowOverflow8
-_WindowOverflow8:
-
-    s32e    a0, a9, -16     /* save a0 to call[j+1]'s stack frame */
-    l32e    a0, a1, -12     /* a0 <- call[j-1]'s sp
-                               (used to find end of call[j]'s frame) */
-    s32e    a1, a9, -12     /* save a1 to call[j+1]'s stack frame */
-    s32e    a2, a9,  -8     /* save a2 to call[j+1]'s stack frame */
-    s32e    a3, a9,  -4     /* save a3 to call[j+1]'s stack frame */
-    s32e    a4, a0, -32     /* save a4 to call[j]'s stack frame */
-    s32e    a5, a0, -28     /* save a5 to call[j]'s stack frame */
-    s32e    a6, a0, -24     /* save a6 to call[j]'s stack frame */
-    s32e    a7, a0, -20     /* save a7 to call[j]'s stack frame */
-    rfwo                    /* rotates back to call[i] position */
-
-/*
---------------------------------------------------------------------------------
-Window Underflow Exception for Call8
-
-Invoked by RETW returning from call[i+1] to call[i]
-where call[i]'s registers must be reloaded (not live in ARs);
-where call[i] had done a call8 to call[i+1].
-On entry here:
-        window rotated to call[i] start point;
-        a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
-        a8-a15 must be preserved (they are call[i+1].reg[0..7]);
-        a9 is call[i+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0xC0
-    .global _WindowUnderflow8
-_WindowUnderflow8:
-
-    l32e    a0, a9, -16     /* restore a0 from call[i+1]'s stack frame */
-    l32e    a1, a9, -12     /* restore a1 from call[i+1]'s stack frame */
-    l32e    a2, a9,  -8     /* restore a2 from call[i+1]'s stack frame */
-    l32e    a7, a1, -12     /* a7 <- call[i-1]'s sp
-                               (used to find end of call[i]'s frame) */
-    l32e    a3, a9,  -4     /* restore a3 from call[i+1]'s stack frame */
-    l32e    a4, a7, -32     /* restore a4 from call[i]'s stack frame */
-    l32e    a5, a7, -28     /* restore a5 from call[i]'s stack frame */
-    l32e    a6, a7, -24     /* restore a6 from call[i]'s stack frame */
-    l32e    a7, a7, -20     /* restore a7 from call[i]'s stack frame */
-    rfwu
-
-/*
---------------------------------------------------------------------------------
-Window Overflow Exception for Call12
-
-Invoked if a call[i] referenced a register (a4-a15)
-that contains data from ancestor call[j];
-call[j] had done a call12 to call[j+1].
-On entry here:
-    window rotated to call[j] start point;
-        a0-a11 are registers to be saved;
-        a12-a15 must be preserved;
-        a13 is call[j+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0x100
-    .global _WindowOverflow12
-_WindowOverflow12:
-
-    s32e    a0,  a13, -16   /* save a0 to call[j+1]'s stack frame */
-    l32e    a0,  a1,  -12   /* a0 <- call[j-1]'s sp
-                               (used to find end of call[j]'s frame) */
-    s32e    a1,  a13, -12   /* save a1 to call[j+1]'s stack frame */
-    s32e    a2,  a13,  -8   /* save a2 to call[j+1]'s stack frame */
-    s32e    a3,  a13,  -4   /* save a3 to call[j+1]'s stack frame */
-    s32e    a4,  a0,  -48   /* save a4 to end of call[j]'s stack frame */
-    s32e    a5,  a0,  -44   /* save a5 to end of call[j]'s stack frame */
-    s32e    a6,  a0,  -40   /* save a6 to end of call[j]'s stack frame */
-    s32e    a7,  a0,  -36   /* save a7 to end of call[j]'s stack frame */
-    s32e    a8,  a0,  -32   /* save a8 to end of call[j]'s stack frame */
-    s32e    a9,  a0,  -28   /* save a9 to end of call[j]'s stack frame */
-    s32e    a10, a0,  -24   /* save a10 to end of call[j]'s stack frame */
-    s32e    a11, a0,  -20   /* save a11 to end of call[j]'s stack frame */
-    rfwo                    /* rotates back to call[i] position */
-
-/*
---------------------------------------------------------------------------------
-Window Underflow Exception for Call12
-
-Invoked by RETW returning from call[i+1] to call[i]
-where call[i]'s registers must be reloaded (not live in ARs);
-where call[i] had done a call12 to call[i+1].
-On entry here:
-        window rotated to call[i] start point;
-        a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
-        a12-a15 must be preserved (they are call[i+1].reg[0..3]);
-        a13 is call[i+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org 0x140
-    .global _WindowUnderflow12
-_WindowUnderflow12:
-
-    l32e    a0,  a13, -16   /* restore a0 from call[i+1]'s stack frame */
-    l32e    a1,  a13, -12   /* restore a1 from call[i+1]'s stack frame */
-    l32e    a2,  a13,  -8   /* restore a2 from call[i+1]'s stack frame */
-    l32e    a11, a1,  -12   /* a11 <- call[i-1]'s sp
-                               (used to find end of call[i]'s frame) */
-    l32e    a3,  a13,  -4   /* restore a3 from call[i+1]'s stack frame */
-    l32e    a4,  a11, -48   /* restore a4 from end of call[i]'s stack frame */
-    l32e    a5,  a11, -44   /* restore a5 from end of call[i]'s stack frame */
-    l32e    a6,  a11, -40   /* restore a6 from end of call[i]'s stack frame */
-    l32e    a7,  a11, -36   /* restore a7 from end of call[i]'s stack frame */
-    l32e    a8,  a11, -32   /* restore a8 from end of call[i]'s stack frame */
-    l32e    a9,  a11, -28   /* restore a9 from end of call[i]'s stack frame */
-    l32e    a10, a11, -24   /* restore a10 from end of call[i]'s stack frame */
-    l32e    a11, a11, -20   /* restore a11 from end of call[i]'s stack frame */
-    rfwu
-
-#endif /* XCHAL_HAVE_WINDOWED */
-
-    .section    .UserEnter.text, "ax"
-    .global     call_user_start
-    .type       call_user_start,@function
-    .align      4
-    .literal_position
-
-
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/Makefile b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/Makefile
deleted file mode 100755
index 2b295e0..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/Makefile
+++ /dev/null
@@ -1,98 +0,0 @@
-### Makefile to build the FreeRTOS library ###
-
-# Build target (options: sim, board)
-
-TARGET      = sim
-SMALL       =
-
-# Tools
-
-CC          = xt-xcc
-AS          = xt-xcc
-AR          = xt-ar
-XT_CORE     = $(patsubst %-params,%,$(notdir $(shell xt-xcc --show-config=core)))
-CONFIGDIR   = $(shell xt-xcc --show-config=config)
-
-# For platform-specific commands
-
-include $(CONFIGDIR)/misc/hostenv.mk
-
-# Source code and build locations
-
-SRCROOT     = $(subst /,$(S),$(CURDIR))
-TSTROOT     = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..$(S)..$(S)..$(S)demos$(S)cadence$(S)sim$(SMALL))
-BLDROOT     = $(TSTROOT)$(S)build
-BLDDIR      = $(BLDROOT)$(S)$(XT_CORE)
-
-FR_SRCDIR   = $(abspath $(SRCROOT)$(S)..$(S)..$(S)..)
-FR_SRCDIR2  = $(FR_SRCDIR)$(S)portable$(S)MemMang
-XT_SRCDIR   = $(SRCROOT)
-
-vpath %.c $(FR_SRCDIR) $(FR_SRCDIR2) $(XT_SRCDIR)
-vpath %.S $(XT_SRCDIR)
-
-# File lists
-
-FR_C_FILES  = $(notdir $(wildcard $(FR_SRCDIR)/*.c)) $(notdir $(wildcard $(FR_SRCDIR2)/*.c))
-XT_C_FILES  = $(notdir $(wildcard $(XT_SRCDIR)/*.c))
-XT_S_FILES  = $(notdir $(wildcard $(XT_SRCDIR)/*.S))
-
-# List of all .o files that will go into the library
-
-LIB_C_O     = $(patsubst %.c,%.o,$(XT_C_FILES) $(FR_C_FILES))
-LIB_S_O     = $(patsubst %.S,%.o,$(XT_S_FILES))
-LIB_O_LIST  = $(addprefix $(BLDDIR)/,$(LIB_C_O) $(LIB_S_O))
-
-# Output files
-
-OSLIB       = $(BLDDIR)$(S)libfreertos.a
-
-# Build options
-
-ifeq ($(TARGET),sim)
-DFLAGS      = -DXT_SIMULATOR
-endif
-ifeq ($(TARGET),board)
-DFLAGS      = -DXT_BOARD
-endif
-
-IFLAGS      = \
-  -I$(FR_SRCDIR)$(S)..$(S)include -I$(FR_SRCDIR)$(S)..$(S)include$(S)private \
-  -I$(XT_SRCDIR) -I$(TSTROOT)$(S)common$(S)config_files -I$(BLDDIR)
-
-CFLAGS      = -O2 -g
-CCFLAGS     = $(CFLAGS) -Wall -mno-coproc -mlongcalls -ffunction-sections -mno-l32r-flix $(DFLAGS)
-ASFLAGS     = $(CCFLAGS)
-
-# Include dependency rules (generated using -MD)
-
--include $(wildcard $(BLDDIR)/*.d)
-
-# Targets
-
-all : mkdir $(OSLIB)
-
-mkdir : $(BLDDIR)/.mkdir
-
-$(BLDDIR)/.mkdir :
-	@$(MKPATH) $(BLDDIR)
-	@echo "" > $@
-	-$(CP) $(CONFIGDIR)/xtensa-elf/include/sys/reent.h $(BLDDIR)/reent.h
-
-$(OSLIB) : $(LIB_O_LIST)
-	$(AR) -rs $@ $^
-
-$(BLDDIR)/%.o : %.c
-	$(CC) $(CCFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $<
-
-$(BLDDIR)/%.o : %.S
-	$(CC) $(ASFLAGS) $(IFLAGS) -MD -MF $(subst .o,.d,$@) -c -o $@ $<
-
-clean :
-	$(RM_R) $(BLDDIR)
-
-clean_all :
-	$(RM_R) $(BLDROOT)
-
-.PHONY : all mkdir clean clean_all
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/port.c b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/port.c
deleted file mode 100755
index 371ccfa..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/port.c
+++ /dev/null
@@ -1,222 +0,0 @@
-
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include 
-#include 
-
-#include "xtensa_rtos.h"
-
-#include "FreeRTOS.h"
-#include "task.h"
-
-
-/* Defined in portasm.h */
-extern void _frxt_tick_timer_init(void);
-
-/* Defined in xtensa_context.S */
-extern void _xt_coproc_init(void);
-
-
-/*-----------------------------------------------------------*/
-
-/* We require the address of the pxCurrentTCB variable, but don't want to know
-any details of its type. */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-unsigned port_xSchedulerRunning = 0; // Duplicate of inaccessible xSchedulerRunning; needed at startup to avoid counting nesting
-unsigned port_interruptNesting = 0;  // Interrupt nesting level
-
-/*-----------------------------------------------------------*/
-
-// User exception dispatcher when exiting
-void _xt_user_exit(void);
-
-/* 
- * Stack initialization
- */
-#if portUSING_MPU_WRAPPERS
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged )
-#else
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-#endif
-{
-	StackType_t *sp, *tp;
-	XtExcFrame  *frame;
-	#if XCHAL_CP_NUM > 0
-	uint32_t *p;
-	#endif
-
-	/* Create interrupt stack frame aligned to 16 byte boundary */
-	sp = (StackType_t *) (((UBaseType_t)(pxTopOfStack + 1) - XT_CP_SIZE - XT_STK_FRMSZ) & ~0xf);
-
-	/* Clear the entire frame (do not use memset() because we don't depend on C library) */
-	for (tp = sp; tp <= pxTopOfStack; ++tp)
-		*tp = 0;
-
-	frame = (XtExcFrame *) sp;
-
-	/* Explicitly initialize certain saved registers */
-	frame->pc   = (UBaseType_t) pxCode;             /* task entrypoint                */
-	frame->a0   = 0;                                /* to terminate GDB backtrace     */
-	frame->a1   = (UBaseType_t) sp + XT_STK_FRMSZ;  /* physical top of stack frame    */
-	frame->exit = (UBaseType_t) _xt_user_exit;      /* user exception exit dispatcher */
-
-	/* Set initial PS to int level 0, EXCM disabled ('rfe' will enable), user mode. */
-	/* Also set entry point argument parameter. */
-	#ifdef __XTENSA_CALL0_ABI__
-	frame->a2 = (UBaseType_t) pvParameters;
-	frame->ps = PS_UM | PS_EXCM;
-	#else
-	/* + for windowed ABI also set WOE and CALLINC (pretend task was 'call4'd). */
-	frame->a6 = (UBaseType_t) pvParameters;
-	frame->ps = PS_UM | PS_EXCM | PS_WOE | PS_CALLINC(1);
-	#endif
-
-	#ifdef XT_USE_SWPRI
-	/* Set the initial virtual priority mask value to all 1's. */
-	frame->vpri = 0xFFFFFFFF;
-	#endif
-
-	#if XCHAL_CP_NUM > 0
-	/* Init the coprocessor save area (see xtensa_context.h) */
-	/* No access to TCB here, so derive indirectly. Stack growth is top to bottom.
-         * //p = (uint32_t *) xMPUSettings->coproc_area;
-	 */
-	p = (uint32_t *)(((uint32_t) pxTopOfStack - XT_CP_SIZE) & ~0xf);
-	p[0] = 0;
-	p[1] = 0;
-	p[2] = (((uint32_t) p) + 12 + XCHAL_TOTAL_SA_ALIGN - 1) & -XCHAL_TOTAL_SA_ALIGN;
-	#endif
-
-	return sp;
-}
-
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* It is unlikely that the Xtensa port will get stopped.  If required simply
-	disable the tick interrupt here. */
-}
-
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	// Interrupts are disabled at this point and stack contains PS with enabled interrupts when task context is restored
-
-	#if XCHAL_CP_NUM > 0
-	/* Initialize co-processor management for tasks. Leave CPENABLE alone. */
-	_xt_coproc_init();
-	#endif
-
-	/* Init the tick divisor value */
-	_xt_tick_divisor_init();
-
-	/* Setup the hardware to generate the tick. */
-	_frxt_tick_timer_init();
-
-	#if XT_USE_THREAD_SAFE_CLIB
-	// Init C library
-	vPortClibInit();
-	#endif
-
-	port_xSchedulerRunning = 1;
-
-	// Cannot be directly called from C; never returns
-	__asm__ volatile ("call0    _frxt_dispatch\n");
-
-	/* Should not get here. */
-	return pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortSysTickHandler( void )
-{
-	BaseType_t ret;
-	uint32_t interruptMask;
-
-	portbenchmarkIntLatency();
-
-	/* Interrupts upto configMAX_SYSCALL_INTERRUPT_PRIORITY must be
-	 * disabled before calling xTaskIncrementTick as it access the
-	 * kernel lists. */
-	interruptMask = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		ret = xTaskIncrementTick();
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( interruptMask );
-
-	portYIELD_FROM_ISR( ret );
-
-	return ret;
-}
-/*-----------------------------------------------------------*/
-
-/*
- * Used to set coprocessor area in stack. Current hack is to reuse MPU pointer for coprocessor area.
- */
-#if portUSING_MPU_WRAPPERS
-void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth )
-{
-	#if XCHAL_CP_NUM > 0
-	xMPUSettings->coproc_area = (StackType_t*)((((uint32_t)(pxBottomOfStack + ulStackDepth - 1)) - XT_CP_SIZE ) & ~0xf);
-
-
-	/* NOTE: we cannot initialize the coprocessor save area here because FreeRTOS is going to
-         * clear the stack area after we return. This is done in pxPortInitialiseStack().
-	 */
-	#endif
-}
-#endif
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portasm.S b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portasm.S
deleted file mode 100755
index 03852d8..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portasm.S
+++ /dev/null
@@ -1,596 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "xtensa_rtos.h"
-
-#define TOPOFSTACK_OFFS                 0x00    /* StackType_t *pxTopOfStack */
-#define CP_TOPOFSTACK_OFFS              0x04    /* xMPU_SETTINGS.coproc_area */
-
-.extern pxCurrentTCB
-
-
-/*
-*******************************************************************************
-* Interrupt stack. The size of the interrupt stack is determined by the config
-* parameter "configISR_STACK_SIZE" in FreeRTOSConfig.h
-*******************************************************************************
-*/
-    .data
-    .align      16
-    .global     port_IntStack
-port_IntStack:
-    .space      configISR_STACK_SIZE
-port_IntStackTop:
-    .word       0
-port_switch_flag:
-    .word       0
-
-    .text
-/*
-*******************************************************************************
-* _frxt_setup_switch
-* void _frxt_setup_switch(void);
-* 
-* Sets an internal flag indicating that a task switch is required on return
-* from interrupt handling.
-* 
-*******************************************************************************
-*/
-    .global     _frxt_setup_switch
-    .type       _frxt_setup_switch,@function
-    .align      4
-_frxt_setup_switch:
-
-    ENTRY(16)
-
-    movi    a2, port_switch_flag
-    movi    a3, 1
-    s32i    a3, a2, 0
-
-    RET(16)
-
-/*
-*******************************************************************************
-*                                            _frxt_int_enter
-*                                       void _frxt_int_enter(void)
-*
-* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_ENTER function for
-* freeRTOS. Saves the rest of the interrupt context (not already saved).
-* May only be called from assembly code by the 'call0' instruction, with
-* interrupts disabled.
-* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
-*
-*******************************************************************************
-*/
-    .globl  _frxt_int_enter
-    .type   _frxt_int_enter,@function
-    .align  4
-_frxt_int_enter:
-
-    /* Save a12-13 in the stack frame as required by _xt_context_save. */
-    s32i    a12, a1, XT_STK_A12
-    s32i    a13, a1, XT_STK_A13
-
-    /* Save return address in a safe place (free a0). */
-    mov     a12, a0
-
-    /* Save the rest of the interrupted context (preserves A12-13). */
-    call0   _xt_context_save
-
-    /*
-    Save interrupted task's SP in TCB only if not nesting.
-    Manage nesting directly rather than call the generic IntEnter()
-    (in windowed ABI we can't call a C function here anyway because PS.EXCM is still set).
-    */
-    movi    a2,  port_xSchedulerRunning
-    movi    a3,  port_interruptNesting
-    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
-    beqz    a2,  1f                     /* scheduler not running, no tasks */
-    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
-    addi    a2,  a2, 1                  /* increment nesting count         */
-    s32i    a2,  a3, 0                  /* save nesting count              */
-    bnei    a2,  1, .Lnested            /* !=0 before incr, so nested      */
-
-    movi    a2,  pxCurrentTCB
-    l32i    a2,  a2, 0                  /* a2 = current TCB                */
-    beqz    a2,  1f
-    s32i    a1,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP */
-    movi    a1,  port_IntStackTop       /* a1 = top of intr stack          */
-
-.Lnested:
-1:
-    mov     a0,  a12                    /* restore return addr and return  */
-    ret
-
-/*
-*******************************************************************************
-*                                            _frxt_int_exit
-*                                       void _frxt_int_exit(void)
-*
-* Implements the Xtensa RTOS porting layer's XT_RTOS_INT_EXIT function for
-* FreeRTOS. If required, calls vPortYieldFromInt() to perform task context
-* switching, restore the (possibly) new task's context, and return to the
-* exit dispatcher saved in the task's stack frame at XT_STK_EXIT.
-* May only be called from assembly code by the 'call0' instruction. Does not
-* return to caller.
-* See the description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
-*
-*******************************************************************************
-*/
-    .globl  _frxt_int_exit
-    .type   _frxt_int_exit,@function
-    .align  4
-_frxt_int_exit:
-
-    movi    a2,  port_xSchedulerRunning
-    movi    a3,  port_interruptNesting
-    rsil    a0,  XCHAL_EXCM_LEVEL       /* lock out interrupts             */
-    l32i    a2,  a2, 0                  /* a2 = port_xSchedulerRunning     */
-    beqz    a2,  .Lnoswitch             /* scheduler not running, no tasks */
-    l32i    a2,  a3, 0                  /* a2 = port_interruptNesting      */
-    addi    a2,  a2, -1                 /* decrement nesting count         */
-    s32i    a2,  a3, 0                  /* save nesting count              */
-    bnez    a2,  .Lnesting              /* !=0 after decr so still nested  */
-
-    movi    a2,  pxCurrentTCB
-    l32i    a2,  a2, 0                  /* a2 = current TCB                */
-    beqz    a2,  1f                     /* no task ? go to dispatcher      */
-    l32i    a1,  a2, TOPOFSTACK_OFFS    /* SP = pxCurrentTCB->pxTopOfStack */
-
-    movi    a2,  port_switch_flag       /* address of switch flag          */
-    l32i    a3,  a2, 0                  /* a3 = port_switch_flag           */
-    beqz    a3,  .Lnoswitch             /* flag = 0 means no switch reqd   */
-    movi    a3,  0
-    s32i    a3,  a2, 0                  /* zero out the flag for next time */
-
-1:
-    /*
-    Call0 ABI callee-saved regs a12-15 need to be saved before possible preemption.
-    However a12-13 were already saved by _frxt_int_enter().
-    */
-    #ifdef __XTENSA_CALL0_ABI__
-    s32i    a14, a1, XT_STK_A14
-    s32i    a15, a1, XT_STK_A15
-    #endif
-
-    #ifdef __XTENSA_CALL0_ABI__
-    call0   vPortYieldFromInt       /* call dispatch inside the function; never returns */
-    #else
-    call4   vPortYieldFromInt       /* this one returns */
-    call0   _frxt_dispatch          /* tail-call dispatcher */
-    /* Never returns here. */
-    #endif
-
-.Lnoswitch:
-    /*
-    If we came here then about to resume the interrupted task.
-    */
-
-.Lnesting:
-    /*
-    We come here only if there was no context switch, that is if this
-    is a nested interrupt, or the interrupted task was not preempted.
-    In either case there's no need to load the SP.
-    */
-
-    /* Restore full context from interrupt stack frame */
-    call0   _xt_context_restore
-
-    /*
-    Must return via the exit dispatcher corresponding to the entrypoint from which
-    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
-    stack frame is deallocated in the exit dispatcher.
-    */
-    l32i    a0,  a1, XT_STK_EXIT
-    ret
-
-
-/*
-**********************************************************************************************************
-*                                           _frxt_timer_int
-*                                      void _frxt_timer_int(void)
-*
-* Implements the Xtensa RTOS porting layer's XT_RTOS_TIMER_INT function for FreeRTOS.
-* Called every timer interrupt.
-* Manages the tick timer and calls xPortSysTickHandler() every tick.
-* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
-*
-* Callable from C (obeys ABI conventions). Implemented in assmebly code for performance.
-*
-**********************************************************************************************************
-*/
-    .globl  _frxt_timer_int
-    .type   _frxt_timer_int,@function
-    .align  4
-_frxt_timer_int:
-
-    /*
-    Xtensa timers work by comparing a cycle counter with a preset value.  Once the match occurs
-    an interrupt is generated, and the handler has to set a new cycle count into the comparator.
-    To avoid clock drift due to interrupt latency, the new cycle count is computed from the old,
-    not the time the interrupt was serviced. However if a timer interrupt is ever serviced more
-    than one tick late, it is necessary to process multiple ticks until the new cycle count is
-    in the future, otherwise the next timer interrupt would not occur until after the cycle
-    counter had wrapped (2^32 cycles later).
-
-    do {
-        ticks++;
-        old_ccompare = read_ccompare_i();
-        write_ccompare_i( old_ccompare + divisor );
-        service one tick;
-        diff = read_ccount() - old_ccompare;
-    } while ( diff > divisor );
-    */
-
-    ENTRY(16)
-
-.L_xt_timer_int_catchup:
-
-    /* Update the timer comparator for the next tick. */
-    #ifdef XT_CLOCK_FREQ
-    movi    a2, XT_TICK_DIVISOR         /* a2 = comparator increment          */
-    #else
-    movi    a3, _xt_tick_divisor
-    l32i    a2, a3, 0                   /* a2 = comparator increment          */
-    #endif
-    rsr     a3, XT_CCOMPARE             /* a3 = old comparator value          */
-    add     a4, a3, a2                  /* a4 = new comparator value          */
-    wsr     a4, XT_CCOMPARE             /* update comp. and clear interrupt   */
-    esync
-
-    #ifdef __XTENSA_CALL0_ABI__
-    /* Preserve a2 and a3 across C calls. */
-    s32i    a2, sp, 4
-    s32i    a3, sp, 8
-    #endif
-
-    /* Call the FreeRTOS tick handler (see port.c). */
-    #ifdef __XTENSA_CALL0_ABI__
-    call0   xPortSysTickHandler
-    #else
-    call4   xPortSysTickHandler
-    #endif
-
-    #ifdef __XTENSA_CALL0_ABI__
-    /* Restore a2 and a3. */
-    l32i    a2, sp, 4
-    l32i    a3, sp, 8
-    #endif
-
-    /* Check if we need to process more ticks to catch up. */
-    esync                               /* ensure comparator update complete  */
-    rsr     a4, CCOUNT                  /* a4 = cycle count                   */
-    sub     a4, a4, a3                  /* diff = ccount - old comparator     */
-    blt     a2, a4, .L_xt_timer_int_catchup  /* repeat while diff > divisor */
-
-    RET(16)
-
-    /*
-**********************************************************************************************************
-*                                           _frxt_tick_timer_init
-*                                      void _frxt_tick_timer_init(void)
-*
-* Initialize timer and timer interrrupt handler (_xt_tick_divisor_init() has already been been called).
-* Callable from C (obeys ABI conventions on entry).
-*
-**********************************************************************************************************
-*/
-    .globl  _frxt_tick_timer_init
-    .type   _frxt_tick_timer_init,@function
-    .align  4
-_frxt_tick_timer_init:
-
-    ENTRY(16)
-
-    /* Set up the periodic tick timer (assume enough time to complete init). */
-    #ifdef XT_CLOCK_FREQ
-    movi    a3, XT_TICK_DIVISOR
-    #else
-    movi    a2, _xt_tick_divisor
-    l32i    a3, a2, 0
-    #endif
-    rsr     a2, CCOUNT              /* current cycle count */
-    add     a2, a2, a3              /* time of first timer interrupt */
-    wsr     a2, XT_CCOMPARE         /* set the comparator */
-
-    /*
-    Enable the timer interrupt at the device level. Don't write directly
-    to the INTENABLE register because it may be virtualized.
-    */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a2, XT_TIMER_INTEN
-    call0   xt_ints_on
-    #else
-    movi    a6, XT_TIMER_INTEN
-    call4   xt_ints_on
-    #endif
-
-    RET(16)
-
-/*
-**********************************************************************************************************
-*                                    DISPATCH THE HIGH READY TASK
-*                                     void _frxt_dispatch(void)
-*
-* Switch context to the highest priority ready task, restore its state and dispatch control to it.
-*
-* This is a common dispatcher that acts as a shared exit path for all the context switch functions
-* including vPortYield() and vPortYieldFromInt(), all of which tail-call this dispatcher
-* (for windowed ABI vPortYieldFromInt() calls it indirectly via _frxt_int_exit() ).
-*
-* The Xtensa port uses different stack frames for solicited and unsolicited task suspension (see
-* comments on stack frames in xtensa_context.h). This function restores the state accordingly.
-* If restoring a task that solicited entry, restores the minimal state and leaves CPENABLE clear.
-* If restoring a task that was preempted, restores all state including the task's CPENABLE.
-*
-* Entry:
-*   pxCurrentTCB  points to the TCB of the task to suspend,
-*   Because it is tail-called without a true function entrypoint, it needs no 'entry' instruction.
-*
-* Exit:
-*   If incoming task called vPortYield() (solicited), this function returns as if from vPortYield().
-*   If incoming task was preempted by an interrupt, this function jumps to exit dispatcher.
-*
-**********************************************************************************************************
-*/
-    .globl  _frxt_dispatch
-    .type   _frxt_dispatch,@function
-    .align  4
-_frxt_dispatch:
-
-    #ifdef __XTENSA_CALL0_ABI__
-    call0   vTaskSwitchContext  // Get next TCB to resume
-    movi    a2, pxCurrentTCB
-    #else
-    movi    a2, pxCurrentTCB
-    call4   vTaskSwitchContext  // Get next TCB to resume
-    #endif
-    l32i    a3,  a2, 0
-    l32i    sp,  a3, TOPOFSTACK_OFFS     /* SP = next_TCB->pxTopOfStack;  */
-    s32i    a3,  a2, 0
-
-    /* Determine the type of stack frame. */
-    l32i    a2,  sp, XT_STK_EXIT        /* exit dispatcher or solicited flag */
-    bnez    a2,  .L_frxt_dispatch_stk
-
-.L_frxt_dispatch_sol:
-
-    /* Solicited stack frame. Restore minimal context and return from vPortYield(). */
-    l32i    a3,  sp, XT_SOL_PS
-    #ifdef __XTENSA_CALL0_ABI__
-    l32i    a12, sp, XT_SOL_A12
-    l32i    a13, sp, XT_SOL_A13
-    l32i    a14, sp, XT_SOL_A14
-    l32i    a15, sp, XT_SOL_A15
-    #endif
-    l32i    a0,  sp, XT_SOL_PC
-    #if XCHAL_CP_NUM > 0
-    /* Ensure wsr.CPENABLE is complete (should be, it was cleared on entry). */
-    rsync
-    #endif
-    /* As soons as PS is restored, interrupts can happen. No need to sync PS. */
-    wsr     a3,  PS
-    #ifdef __XTENSA_CALL0_ABI__
-    addi    sp,  sp, XT_SOL_FRMSZ
-    ret
-    #else
-    retw
-    #endif
-
-.L_frxt_dispatch_stk:
-
-    #if XCHAL_CP_NUM > 0
-    /* Restore CPENABLE from task's co-processor save area. */
-    movi    a3, pxCurrentTCB            /* cp_state =                       */
-    l32i    a3, a3, 0
-    l32i    a2, a3, CP_TOPOFSTACK_OFFS     /* StackType_t                       *pxStack; */
-    l16ui    a3, a2, XT_CPENABLE         /* CPENABLE = cp_state->cpenable;   */
-    wsr     a3, CPENABLE
-    #endif
-
-    /* Interrupt stack frame. Restore full context and return to exit dispatcher. */
-    call0   _xt_context_restore
-
-    /* In Call0 ABI, restore callee-saved regs (A12, A13 already restored). */
-    #ifdef __XTENSA_CALL0_ABI__
-    l32i    a14, sp, XT_STK_A14
-    l32i    a15, sp, XT_STK_A15
-    #endif
-
-    #if XCHAL_CP_NUM > 0
-    /* Ensure wsr.CPENABLE has completed. */
-    rsync
-    #endif
-
-    /*
-    Must return via the exit dispatcher corresponding to the entrypoint from which
-    this was called. Interruptee's A0, A1, PS, PC are restored and the interrupt
-    stack frame is deallocated in the exit dispatcher.
-    */
-    l32i    a0, sp, XT_STK_EXIT
-    ret
-
-
-/*
-**********************************************************************************************************
-*                            PERFORM A SOLICTED CONTEXT SWITCH (from a task)
-*                                        void vPortYield(void)
-*
-* This function saves the minimal state needed for a solicited task suspension, clears CPENABLE,
-* then tail-calls the dispatcher _frxt_dispatch() to perform the actual context switch
-*
-* At Entry:
-*   pxCurrentTCB  points to the TCB of the task to suspend
-*   Callable from C (obeys ABI conventions on entry).
-*
-* Does not return to caller.
-*
-**********************************************************************************************************
-*/
-    .globl  vPortYield
-    .type   vPortYield,@function
-    .align  4
-vPortYield:
-
-    #ifdef __XTENSA_CALL0_ABI__
-    addi    sp,  sp, -XT_SOL_FRMSZ
-    #else
-    entry   sp,  XT_SOL_FRMSZ
-    #endif
-
-    rsr     a2,  PS
-    s32i    a0,  sp, XT_SOL_PC
-    s32i    a2,  sp, XT_SOL_PS
-    #ifdef __XTENSA_CALL0_ABI__
-    s32i    a12, sp, XT_SOL_A12         /* save callee-saved registers      */
-    s32i    a13, sp, XT_SOL_A13
-    s32i    a14, sp, XT_SOL_A14
-    s32i    a15, sp, XT_SOL_A15
-    #else
-    /* Spill register windows. Calling xthal_window_spill() causes extra    */
-    /* spills and reloads, so we will set things up to call the _nw version */
-    /* instead to save cycles.                                              */
-    movi    a6,  ~(PS_WOE_MASK|PS_INTLEVEL_MASK)  /* spills a4-a7 if needed */
-    and     a2,  a2, a6                           /* clear WOE, INTLEVEL    */
-    addi    a2,  a2, XCHAL_EXCM_LEVEL             /* set INTLEVEL           */
-    wsr     a2,  PS
-    rsync
-    call0   xthal_window_spill_nw
-    l32i    a2,  sp, XT_SOL_PS                    /* restore PS             */
-    wsr     a2,  PS
-    #endif
-
-    rsil    a2,  XCHAL_EXCM_LEVEL       /* disable low/med interrupts       */
-
-    #if XCHAL_CP_NUM > 0
-    /* Save coprocessor callee-saved state (if any). At this point CPENABLE */
-    /* should still reflect which CPs were in use (enabled).                */
-    call0   _xt_coproc_savecs
-    #endif
-
-    movi    a2,  pxCurrentTCB
-    movi    a3,  0
-    l32i    a2,  a2, 0                  /* a2 = pxCurrentTCB                */
-    s32i    a3,  sp, XT_SOL_EXIT        /* 0 to flag as solicited frame     */
-    s32i    sp,  a2, TOPOFSTACK_OFFS    /* pxCurrentTCB->pxTopOfStack = SP  */
-
-    #if XCHAL_CP_NUM > 0
-    /* Clear CPENABLE, also in task's co-processor state save area. */
-    l32i    a2,  a2, CP_TOPOFSTACK_OFFS /* a2 = pxCurrentTCB->cp_state      */
-    movi    a3,  0
-    wsr     a3,  CPENABLE
-    beqz    a2,  1f
-    s16i     a3,  a2, XT_CPENABLE        /* clear saved cpenable             */
-1:
-    #endif
-
-    /* Tail-call dispatcher. */
-    call0   _frxt_dispatch
-    /* Never reaches here. */
-
-
-/*
-**********************************************************************************************************
-*                         PERFORM AN UNSOLICITED CONTEXT SWITCH (from an interrupt)
-*                                        void vPortYieldFromInt(void)
-*
-* This calls the context switch hook (removed), saves and clears CPENABLE, then tail-calls the dispatcher
-* _frxt_dispatch() to perform the actual context switch.
-*
-* At Entry:
-*   Interrupted task context has been saved in an interrupt stack frame at pxCurrentTCB->pxTopOfStack.
-*   pxCurrentTCB  points to the TCB of the task to suspend,
-*   Callable from C (obeys ABI conventions on entry).
-*
-* At Exit:
-*   Windowed ABI defers the actual context switch until the stack is unwound to interrupt entry.
-*   Call0 ABI tail-calls the dispatcher directly (no need to unwind) so does not return to caller.
-*
-**********************************************************************************************************
-*/
-    .globl  vPortYieldFromInt
-    .type   vPortYieldFromInt,@function
-    .align  4
-vPortYieldFromInt:
-
-    ENTRY(16)
-
-    #if XCHAL_CP_NUM > 0
-    /* Save CPENABLE in task's co-processor save area, and clear CPENABLE.  */
-    movi    a3, pxCurrentTCB            /* cp_state =                       */
-    l32i    a3, a3, 0
-    l32i    a2, a3, CP_TOPOFSTACK_OFFS
-
-    rsr     a3, CPENABLE
-    s16i     a3, a2, XT_CPENABLE         /* cp_state->cpenable = CPENABLE;   */
-    movi    a3, 0
-    wsr     a3, CPENABLE                /* disable all co-processors        */
-    #endif
-
-    #ifdef __XTENSA_CALL0_ABI__
-    /* Tail-call dispatcher. */
-    call0   _frxt_dispatch
-    /* Never reaches here. */
-    #else
-    RET(16)
-    #endif
-
-/*
-**********************************************************************************************************
-*                                        _frxt_task_coproc_state
-*                                   void _frxt_task_coproc_state(void)
-*
-* Implements the Xtensa RTOS porting layer's XT_RTOS_CP_STATE function for FreeRTOS.
-*
-* May only be called when a task is running, not within an interrupt handler (returns 0 in that case).
-* May only be called from assembly code by the 'call0' instruction. Does NOT obey ABI conventions.
-* Returns in A15 a pointer to the base of the co-processor state save area for the current task.
-* See the detailed description of the XT_RTOS_ENTER macro in xtensa_rtos.h.
-*
-**********************************************************************************************************
-*/
-#if XCHAL_CP_NUM > 0
-
-    .globl  _frxt_task_coproc_state
-    .type   _frxt_task_coproc_state,@function
-    .align  4
-_frxt_task_coproc_state:
-
-    movi    a15, port_xSchedulerRunning /* if (port_xSchedulerRunning              */
-    l32i    a15, a15, 0
-    beqz    a15, 1f
-    movi    a15, port_interruptNesting  /* && port_interruptNesting == 0           */
-    l32i    a15, a15, 0
-    bnez    a15, 1f
-    movi    a15, pxCurrentTCB
-    l32i    a15, a15, 0                 /* && pxCurrentTCB != 0) {                 */
-    beqz    a15, 2f
-    l32i    a15, a15, CP_TOPOFSTACK_OFFS
-    ret
-
-1:  movi    a15, 0
-2:  ret
-
-#endif /* XCHAL_CP_NUM > 0 */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
deleted file mode 100755
index f5f1899..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portbenchmark.h
+++ /dev/null
@@ -1,46 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * This utility helps benchmarking interrupt latency and context switches.
- * In order to enable it, set configBENCHMARK to 1 in FreeRTOSConfig.h.
- * You will also need to download the FreeRTOS_trace patch that contains
- * portbenchmark.c and the complete version of portbenchmark.h
- */
-
-#ifndef PORTBENCHMARK_H
-#define PORTBENCHMARK_H
-
-#if configBENCHMARK
-    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
-#endif
-
-#define portbenchmarkINTERRUPT_DISABLE()
-#define portbenchmarkINTERRUPT_RESTORE(newstate)
-#define portbenchmarkIntLatency()
-#define portbenchmarkIntWait()
-#define portbenchmarkReset()
-#define portbenchmarkPrint()
-
-#endif /* PORTBENCHMARK */
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portclib.c b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portclib.c
deleted file mode 100755
index b602134..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portclib.c
+++ /dev/null
@@ -1,225 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#include "FreeRTOS.h"
-
-#if XT_USE_THREAD_SAFE_CLIB
-
-#if XSHAL_CLIB == XTHAL_CLIB_XCLIB
-
-#include 
-#include 
-
-#include "semphr.h"
-
-typedef SemaphoreHandle_t       _Rmtx;
-
-//-----------------------------------------------------------------------------
-//  Override this and set to nonzero to enable locking.
-//-----------------------------------------------------------------------------
-int32_t _xclib_use_mt = 1;
-
-
-//-----------------------------------------------------------------------------
-//  Init lock.
-//-----------------------------------------------------------------------------
-void
-_Mtxinit(_Rmtx * mtx)
-{
-    *mtx = xSemaphoreCreateRecursiveMutex();
-}
-
-//-----------------------------------------------------------------------------
-//  Destroy lock.
-//-----------------------------------------------------------------------------
-void
-_Mtxdst(_Rmtx * mtx)
-{
-    if ((mtx != NULL) && (*mtx != NULL)) {
-        vSemaphoreDelete(*mtx);
-    }
-}
-
-//-----------------------------------------------------------------------------
-//  Lock.
-//-----------------------------------------------------------------------------
-void
-_Mtxlock(_Rmtx * mtx)
-{
-    if ((mtx != NULL) && (*mtx != NULL)) {
-        xSemaphoreTakeRecursive(*mtx, portMAX_DELAY);
-    }
-}
-
-//-----------------------------------------------------------------------------
-//  Unlock.
-//-----------------------------------------------------------------------------
-void
-_Mtxunlock(_Rmtx * mtx)
-{
-    if ((mtx != NULL) && (*mtx != NULL)) {
-        xSemaphoreGiveRecursive(*mtx);
-    }
-}
-
-//-----------------------------------------------------------------------------
-//  Called by malloc() to allocate blocks of memory from the heap.
-//-----------------------------------------------------------------------------
-void *
-_sbrk_r (struct _reent * reent, int32_t incr)
-{
-    extern char _end;
-    extern char _heap_sentry;
-    static char * _heap_sentry_ptr = &_heap_sentry;
-    static char * heap_ptr;
-    char * base;
-
-    if (!heap_ptr)
-        heap_ptr = (char *) &_end;
-
-    base = heap_ptr;
-    if (heap_ptr + incr >= _heap_sentry_ptr) {
-        reent->_errno = ENOMEM;
-        return (char *) -1;
-    }
-
-    heap_ptr += incr;
-    return base;
-}
-
-//-----------------------------------------------------------------------------
-//  Global initialization for C library.
-//-----------------------------------------------------------------------------
-void
-vPortClibInit(void)
-{
-}
-
-//-----------------------------------------------------------------------------
-//  Per-thread cleanup stub provided for linking, does nothing.
-//-----------------------------------------------------------------------------
-void
-_reclaim_reent(void * ptr)
-{
-}
-
-#endif /* XSHAL_CLIB == XTHAL_CLIB_XCLIB */
-
-#if XSHAL_CLIB == XTHAL_CLIB_NEWLIB
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "semphr.h"
-
-static SemaphoreHandle_t xClibMutex;
-static uint32_t  ulClibInitDone = 0;
-
-//-----------------------------------------------------------------------------
-//  Get C library lock.
-//-----------------------------------------------------------------------------
-void
-__malloc_lock(struct _reent * ptr)
-{
-    if (!ulClibInitDone)
-        return;
-
-    xSemaphoreTakeRecursive(xClibMutex, portMAX_DELAY);
-}
-
-//-----------------------------------------------------------------------------
-//  Release C library lock.
-//-----------------------------------------------------------------------------
-void
-__malloc_unlock(struct _reent * ptr)
-{
-    if (!ulClibInitDone)
-        return;
-
-    xSemaphoreGiveRecursive(xClibMutex);
-}
-
-//-----------------------------------------------------------------------------
-//  Lock for environment. Since we have only one global lock we can just call
-//  the malloc() lock function.
-//-----------------------------------------------------------------------------
-void
-__env_lock(struct _reent * ptr)
-{
-    __malloc_lock(ptr);
-}
-
-
-//-----------------------------------------------------------------------------
-//  Unlock environment.
-//-----------------------------------------------------------------------------
-void
-__env_unlock(struct _reent * ptr)
-{
-    __malloc_unlock(ptr);
-}
-
-//-----------------------------------------------------------------------------
-//  Called by malloc() to allocate blocks of memory from the heap.
-//-----------------------------------------------------------------------------
-void *
-_sbrk_r (struct _reent * reent, int32_t incr)
-{
-    extern char _end;
-    extern char _heap_sentry;
-    static char * _heap_sentry_ptr = &_heap_sentry;
-    static char * heap_ptr;
-    char * base;
-
-    if (!heap_ptr)
-        heap_ptr = (char *) &_end;
-
-    base = heap_ptr;
-    if (heap_ptr + incr >= _heap_sentry_ptr) {
-        reent->_errno = ENOMEM;
-        return (char *) -1;
-    }
-
-    heap_ptr += incr;
-    return base;
-}
-
-//-----------------------------------------------------------------------------
-//  Global initialization for C library.
-//-----------------------------------------------------------------------------
-void
-vPortClibInit(void)
-{
-    configASSERT(!ulClibInitDone);
-
-    xClibMutex = xSemaphoreCreateRecursiveMutex();
-    ulClibInitDone  = 1;
-}
-
-#endif /* XSHAL_CLIB == XTHAL_CLIB_NEWLIB */
-
-#endif /* XT_USE_THREAD_SAFE_CLIB */
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h
deleted file mode 100755
index e30db0b..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/portmacro.h
+++ /dev/null
@@ -1,236 +0,0 @@
-
-/*
- * FreeRTOS Kernel V10.0.0
- * Copyright (C) 2017 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software. If you wish to use our Amazon
- * FreeRTOS name, please do so in a fair use way that does not cause confusion.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef __ASSEMBLER__
-
-#include 
-
-#include 
-#include 
-#include 
-#include 	/* required for XSHAL_CLIB */
-#include 
-
-//#include "xtensa_context.h"
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-
-#define portCHAR		int8_t
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		int32_t
-#define portSHORT		int16_t
-#define portSTACK_TYPE	uint32_t
-#define portBASE_TYPE	int
-
-typedef portSTACK_TYPE			StackType_t;
-typedef portBASE_TYPE			BaseType_t;
-typedef unsigned portBASE_TYPE	UBaseType_t;
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-// portbenchmark
-#include "portbenchmark.h"
-
-/* Critical section management. NW-TODO: replace XTOS_SET_INTLEVEL with more efficient version, if any? */
-// These cannot be nested. They should be used with a lot of care and cannot be called from interrupt level.
-#define portDISABLE_INTERRUPTS()      do { XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); } while (0)
-#define portENABLE_INTERRUPTS()       do { portbenchmarkINTERRUPT_RESTORE(0); XTOS_SET_INTLEVEL(0); } while (0)
-
-// These can be nested
-#define portCRITICAL_NESTING_IN_TCB 1  // For now, let FreeRTOS' (tasks.c) manage critical nesting
-void vTaskEnterCritical(void);
-void vTaskExitCritical(void);
-#define portENTER_CRITICAL()        vTaskEnterCritical()
-#define portEXIT_CRITICAL()         vTaskExitCritical()
-
-// Cleaner and preferred solution allows nested interrupts disabling and restoring via local registers or stack.
-// They can be called from interrupts too.
-static inline unsigned portENTER_CRITICAL_NESTED() { unsigned state = XTOS_SET_INTLEVEL(XCHAL_EXCM_LEVEL); portbenchmarkINTERRUPT_DISABLE(); return state; }
-#define portEXIT_CRITICAL_NESTED(state)   do { portbenchmarkINTERRUPT_RESTORE(state); XTOS_RESTORE_JUST_INTLEVEL(state); } while (0)
-
-// These FreeRTOS versions are similar to the nested versions above
-#define portSET_INTERRUPT_MASK_FROM_ISR()            portENTER_CRITICAL_NESTED()
-#define portCLEAR_INTERRUPT_MASK_FROM_ISR(state)     portEXIT_CRITICAL_NESTED(state)
-
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH			( -1 )
-#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT			4
-#define portNOP()					XT_NOP()
-/*-----------------------------------------------------------*/
-
-/* Fine resolution time */
-#define portGET_RUN_TIME_COUNTER_VALUE()  xthal_get_ccount()
-
-/* Kernel utilities. */
-void vPortYield( void );
-void _frxt_setup_switch( void );
-#define portYIELD()       vPortYield()
-#define portYIELD_FROM_ISR( xHigherPriorityTaskWoken )	\
-	if ( ( xHigherPriorityTaskWoken ) != 0 ) {	\
-		_frxt_setup_switch();			\
-	}
-
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-// When coprocessors are defined, we to maintain a pointer to coprocessors area.
-// We currently use a hack: redefine field xMPU_SETTINGS in TCB block as a structure that can hold:
-// MPU wrappers, coprocessor area pointer, trace code structure, and more if needed.
-// The field is normally used for memory protection. FreeRTOS should create another general purpose field.
-typedef struct {
-	#if XCHAL_CP_NUM > 0
-	volatile StackType_t* coproc_area; // Pointer to coprocessor save area; MUST BE FIRST
-	#endif
-
-	#if portUSING_MPU_WRAPPERS
-	// Define here mpu_settings, which is port dependent
-	int mpu_setting; // Just a dummy example here; MPU not ported to Xtensa yet
-	#endif
-
-	#if configUSE_TRACE_FACILITY_2
-	struct {
-		// Cf. porttraceStamp()
-		int taskstamp;        /* Stamp from inside task to see where we are */
-		int taskstampcount;   /* A counter usually incremented when we restart the task's loop */
-	} porttrace;
-	#endif
-} xMPU_SETTINGS;
-
-// Main hack to use MPU_wrappers even when no MPU is defined (warning: mpu_setting should not be accessed; otherwise move this above xMPU_SETTINGS)
-#if (XCHAL_CP_NUM > 0 || configUSE_TRACE_FACILITY_2) && !portUSING_MPU_WRAPPERS   // If MPU wrappers not used, we still need to allocate coproc area
-	#undef portUSING_MPU_WRAPPERS
-	#define portUSING_MPU_WRAPPERS 1   // Enable it to allocate coproc area
-	#define MPU_WRAPPERS_H             // Override mpu_wrapper.h to disable unwanted code
-	#define PRIVILEGED_FUNCTION
-	#define PRIVILEGED_DATA
-#endif
-
-// porttrace
-#if configUSE_TRACE_FACILITY_2
-#include "porttrace.h"
-#endif
-
-// configASSERT_2 if requested
-#if configASSERT_2
-#include 
-void exit(int);
-#define configASSERT( x )   if (!(x)) { porttracePrint(-1); printf("\nAssertion failed in %s:%d\n", __FILE__, __LINE__); exit(-1); }
-#endif
-
-
-/* C library support -- only XCLIB and NEWLIB are supported. */
-
-/* To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must be
-   defined to be > 0 somewhere above or on the command line. */
-
-#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
-extern void vPortClibInit(void);
-
-// No cleanup necessary at this time.
-#define portCLEAN_UP_TCB(pxTCB)
-#endif // XCLIB support
-
-#if (XT_USE_THREAD_SAFE_CLIB > 0u) && (XSHAL_CLIB == XTHAL_CLIB_NEWLIB)
-extern void vPortClibInit(void);
-
-// This C library cleanup is not currently done by FreeRTOS when deleting a task
-#include 
-#define portCLEAN_UP_TCB(pxTCB)   vPortCleanUpTcbClib(&((pxTCB)->xNewLib_reent))
-static inline void vPortCleanUpTcbClib(struct _reent *ptr)
-{
-    FILE * fp = &(ptr->__sf[0]);
-    int i;
-    for (i = 0; i < 3; ++i, ++fp) {
-        fp->_close = NULL;
-    }
-}
-#endif // NEWLIB support
-
-#endif // __ASSEMBLER__
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h
deleted file mode 100755
index 834b160..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/porttrace.h
+++ /dev/null
@@ -1,44 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * This utility helps tracing the entering and exiting from tasks.
- * It maintains a circular buffer of tasks in the order they execute,
- * and their execution time. To enable it, set configUSE_TRACE_FACILITY_2
- * to 1 in FreeRTOSConfig.h. You will also need to download the 
- * FreeRTOS_trace patch that contains porttrace.c and the complete version
- * of porttrace.h.
- */
-
-#ifndef PORTTRACE_H
-#define PORTTRACE_H
-
-#if configUSE_TRACE_FACILITY_2
-    #error "You need to download the FreeRTOS_trace patch that overwrites this file"
-#endif
-
-#define porttracePrint(nelements)
-#define porttraceStamp(stamp, count_incr)
-
-#endif /* PORTTRACE_H */
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt
deleted file mode 100755
index 5622809..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/readme_xtensa.txt
+++ /dev/null
@@ -1,764 +0,0 @@
-    FreeRTOS Port for Xtensa Configurable and Diamond Processors
-    ============================================================
-
-                FreeRTOS Kernel Version 10.0.0
-
-
-Introduction
-------------
-
-This document describes the Xtensa port for FreeRTOS multitasking RTOS.
-For an introduction to FreeRTOS itself, please refer to FreeRTOS
-documentation.
-
-This port currently works with FreeRTOS kernel version 10.0.0.
-
-
-Xtensa Configuration Requirements and Restrictions
---------------------------------------------------
-
-The Xtensa configurable architecture supports a vast space of processor
-features. This port supports all of them, including custom processor
-extensions defined in the TIE language, with certain minimum
-requirements. You must use Xtensa Tools to compile and link FreeRTOS and
-your application for your Xtensa configuration. The port uses the Xtensa
-Hardware Abstraction Layer (HAL) to adapt to your Xtensa configuration.
-NOTE: It may be possible to build and run this with the open-source 
-xtensa-linux tools provided you have the correct overlay for your Xtensa
-configuration. However, this has not been tested and is currently not
-supported by Cadence.
-
-This port includes optional reentrancy support for the 'newlib' and
-'xclib' C runtime libraries distributed with Xtensa Tools, providing
-thread-safety on a per task basis (for use in tasks only, not interrupt
-handlers).
-
-NOTE: At this time only 'newlib' and 'xclib' C libraries are supported
-for thread safety. The 'uclibc' library is not reentrant and does not
-provide thread safety at this time. However, if you are not concerned
-with reentrancy then you can use any of these libraries.
-
-This port also includes a simple example application that may run on
-a supported board or the Xtensa instruction set simulator (ISS). There
-are also a couple of test programs used in maintaining the port, which
-serve as additional examples.
-
-FreeRTOS for Xtensa configurable processors requires the following minimum 
-processor configuration options:
-- Timer interrupt option with at least one interruptible timer.
-- Interrupt option (implied by the timer interrupt option).
-- Exception Architecture 2 (XEA2). Please note that XEA1 is NOT supported.
-  All 'Diamond', 'Xtensa 6', 'Xtensa LX' and 'Xtensa LX2' processors and
-  most 'Xtensa T1050' processors are configured with XEA2.
-All Diamond processor cores meet these requirements and are supported.
-
-Minimal support for certain evaluation boards is provided via a board
-independent XTBSP API implemented by a board specific library distributed
-with the Xtensa Tools. This provides the board clock frequency and basic
-polled drivers for the display and console device. Note that XTBSP
-is not a tradtional RTOS "board support package" with RTOS specific
-interrupt-driven drivers - it is not specific to any RTOS. Note that
-FreeRTOS can run on any Xtensa or Diamond board without this board support
-(a "raw" platform), but you will have to provide the clock frequency
-and drivers for any on-board devices you want to use.
-
-
-Installation
-------------
-
-The Xtensa port of FreeRTOS is available at this location:
-
-    https://github.com/foss-xtensa/amazon-freertos
-
-This download includes the core FreeRTOS source and include files needed
-to build the port. You can also download the official release of FreeRTOS
-version 1.0.0 or later from this location:
-
-    https://github.com/aws/amazon-freertos
-
-The Xtensa port files are currently not included in the official package.
-
-All source is provided along with a Makefile that works for any host
-platform supported by Xtensa Tools (Windows, Linux). These instructions
-are written for Windows users, but can easily be understood and adapted
-to other host platforms.
-
-First install the FreeRTOS common package in a directory of your choosing.
-The structure of that package will look like this:
-
-
-|-- demos
-|   `-- cadence
-|       `-- sim
-|           |-- common
-|           |   |-- application_code
-|           |   |   `-- cadence_code
-|           |   `-- config_files
-|           `-- xplorer
-`-- lib
-    |-- FreeRTOS
-    |   `-- portable
-    |       |-- Common
-    |       |-- MemMang
-    |       `-- XCC
-    |           `-- Xtensa
-    `-- include
-        `-- private
-
-The Xtensa Tools are available from Cadence as part of a processor
-license. Be sure you have installed the Xtensa Tools and your processor
-configuration.
-
-
-Building FreeRTOS for Xtensa
-----------------------------
-
-To build the FreeRTOS library and the example programs, go into the
-directory 'demos/cadence/sim' and use the makefile in that directory.
-"make all" will build all the examples. There is another makefile in
-the 'lib/FreeRTOS/portable/XCC/Xtensa' directory that builds just the
-FreeRTOS library.
-
-By default, you will build for the Xtensa instruction set simulator. If
-you have a supported emulation board, you can build to run on that. You
-can also build to run on a raw Xtensa core with no board support, a
-good starting point for supporting your own target platform. Cadence
-recommends doing functional development on the simulator because it
-is easier to debug with, then move to a board if/when you need to test
-hardware drivers or real-time performance.
-
-The provided makefile simplifies building FreeRTOS and the example
-for your Xtensa configuration and platform (ISS, board, etc.). There
-are detailed instructions in the comments at the top of the makefile.
-
-The makefiles work on Windows and Linux and support incremental builds.
-The build for each Xtensa configuration and target platform is placed in
-a subdirectory so several core and platform builds can co-exist even with
-incremental rebuilds. You may specify the root of the build area (if tou
-want it to be elsewhere than under the source tree) by defining BLDROOT
-either in the make command or your shell environment.
-
-
-Building the FreeRTOS Library
------------------------------
-
-First, be sure you have installed Xtensa Tools and your processor
-configuration, and be sure that Xtensa Tools are in your search path.
-You can use xt-make, which comes with the Xtensa Tools, to run the
-makefiles.
-
-Change directories to the Xtensa port directory:
-
-> cd lib/FreeRTOS/portable/XCC/Xtensa
-
-Now build the FreeRTOS RTOS as a library (libfreertos.a) as follows:
-
-> xt-make
-
-which by default builds for the simulator (TARGET=sim), or:
-
-> xt-make TARGET=board
-
-which builds for a supported board. Note that the board type does not
-need to be specified when building the FreeRTOS library.
-
-If you are building for an Xtensa processor configuration that is not the
-default you selected when you installed Xtensa Tools, you need to define the 
-environment variable XTENSA_CORE. If your configuration is not in the 
-default registry you selected when you installed Xtensa Tools, you also
-need to define the environment variable XTENSA_SYSTEM. See tools manuals.
-You can avoid defining these in your environment if you pass the variables 
-you need to redefine into xt-make as follows:
-
-> xt-make XTENSA_CORE= XTENSA_SYSTEM= ...
-
-There are more details about build options in the comment in the Makefile.
-
-After the library has been built, you must link your application with this
-library in order to use FreeRTOS.
-
-
-Building the FreeRTOS Examples
-------------------------------
-
-The provided examples are designed to run on the Xtensa instruction set
-simulator (ISS) or a supported evaluation board programmed with your
-Xtensa processor configuration.
-
-To build the examples for the default platform (simulator):
-
-> cd demos/cadence/sim
-
-> xt-make all
-
-which is the same as
-
-> xt-make all TARGET=sim
-
-The boards currently supported are the Xilinx ML605 and KC705 FPGA
-development boards. To target these boards, type
-
-> xt-make all TARGET=ml605
-
-or
-
-> xt-make all TARGET=kc705
-
-To build in a location other than the default, specify the new location
-using the BLDROOT variable. Note that this makefile will invoke the 
-FreeRTOS library build makefile automatically, passing on the relevant
-parameters based on what you specified.
-
-You can override the default compilation options by specifying the new
-options via CFLAGS. For example:
-
-> xt-make all TARGET=sim CFLAGS="-O2 -Os -g"
-
-This compiles the examples and links them with the FreeRTOS library
-libfreertos.a and the appropriate linker-support package (LSP) for your
-target platform (you can override the LSP by adding LSP= to the
-xt-make command line). The resulting ELF files can be downloaded and
-executed on the target. The example binaries appear in the platform
-specific subdirectory described earlier.
-
-To build your application with thread-safe C library support, you
-need to make certain modifications to the application to plug in and
-invoke the reentrancy support. This allows each task to use the library
-without interference with other tasks (it is not safe for interrupt
-handlers to call the C library).
-
-First, you must define
-
-    XT_USE_THREAD_SAFE_CLIB
-
-to a nonzero value either in xtensa_config.h or on the compiler's command
-line. Note that the default xtensa_config.h provided with this port does
-define this to 1 if either newlib or xclib is detected.
-
-Then, you must also make sure to allocate extra space on the stack for
-each task that will use the C library reentrant functions. This extra
-space is to be allocated over and above the actual stack space required
-by the task itself. The define
-
-    XT_STACK_EXTRA_CLIB
-
-specifies the amount of extra space to be added on to the stack to allow
-saving the context for the C library as well as the coprocessors if any.
-E.g. if your task requires 2000 bytes of stack space, you must allocate
-(2000 + XT_STACK_EXTRA_CLIB) bytes for the stack.
-
-
-IMPORTANT NOTE
---------------
-
-The header file FreeRTOS.h, which is a part of the core FreeRTOS sources,
-includes  if thread safety for the C libraries is enabled. For
-xclib, this file exists in  and so is reported as missing.
-To work around this, the makefiles supplied with this port will copy the
-reent.h header into the build directory during the build process. If you
-use a different build process, then you must make sure to copy this file
-to a location that is included in the list of include paths. This can be
-the build directory or the directory that contains the Xtensa port source
-files.
-
-
-Running or Debugging an Application
------------------------------------
-
-To execute the example application on the simulator:
-
-> xt-run [--turbo] example.exe
-
-The option --turbo provides much faster, but non-cycle-accurate simulation
-(the --turbo option is only available with Xtensa Tools version 7 or later).
-
-
-To execute on the simulator using the Xplorer GUI based debugger:
-
-> xplorer --debug example.exe
-
-
-To execute on a supported evaluation board, download example.exe per
-instructions in the tools manuals. Be sure the board has been programmed
-with the correct configuration and is set up to boot from RAM and debug
-a downloaded program!  Optionally you may connect a terminal or terminal
-emulator to the serial port on the board with settings as described in
-the board user manual, and see the output of printf on the terminal.
-
-To obtain I/O on a "raw" platform such as an unsupported board, you need
-to provide low level I/O drivers (eg. inbyte() and outbyte() for character
-I/O if you want to use printf etc.).  You can run "raw" executables on
-any Xtensa platform, including simulator and any board, but you will not
-see any behavior specific to the platform (eg. display, printed output,
-stopping simulation at end of program). You can, while debugging, use a
-debugger mechanism called GDBIO to obtain basic I/O. To use GDBIO, link
-with the gdbio LSP. Refer to Xtensa tools documentation for details.
-
-
-Task Stack Sizes
-----------------
-
-The application must ensure that every task has enough space for its
-stack. Each task needs enough space for its own use, its own interrupt
-stack frame (defined in xtensa_context.h) and space to save coprocessor
-state, if any. Several factors influence the size of the stack required,
-including the compiler optimization level and the use of the C library.
-Calls to standard output functions such as printf() can use up a lot of
-stack space. The tool xt-stack-usage is helpful in determining safe stack
-sizes for your application.
-
-Some macros are provided in xtensa_config.h to help determine the stack
-size for tasks that do and do not use the C library. Use these as the
-basis for each task's stack size. They are minimum requirements taking
-into account your configuration and use of the C library. In particular,
-the define
-
-    XT_STACK_MIN_SIZE
-
-defines the minimum stack size for any task. Be very careful if you try
-to use a stack size smaller than this minimum. Stack overruns can cause
-all kinds of hard-to-debug errors. It is recommended that you enable the
-FreeRTOS stack checking features during development.
-
-WARNING: The newlib printf() function uses a lot of stack space. Be very
-careful in using it. Optionally you can use the 'libxtutil' library for
-output - it implements a subset of printf() that has smaller code size
-and uses far less stack space. More information about this library is in
-the Xtensa Tools documentation.
-
-
-Interrupt Stack
----------------
-
-Beginning with port version 1.2, the port uses a separate interrupt stack
-for handling interrupts. Thus, it is no longer necessary for each task to
-reserve space on its stack to handle interrupts. The size of the interrupt
-stack is controlled by the parameter "configISR_STACK_SIZE" defined in
-FreeRTOSConfig.h. Define this carefully to match your system requirements.
-
-
-Assembler / Compiler Switches
------------------------------
-
-The following are compiler switches are used by the provided
-Makefile in building the FreeRTOS library and example application.
-These can be modified by editing the Makefile or by overriding the
-CFLAGS variable in the make command line, for example:
-
-> xt-make CFLAGS="-O2 -DXT_USE_THREAD_SAFE_CLIB"
-
-    -g                      Specifies debug information.
-    -c                      Specifies object code generation.
-    -On                     Sets compiler optimization level n (default -O0).
-    -mlongcalls             Allows assembler and linker to convert call 
-                            instructions to longer indirect call sequences 
-                            when target is out of range.
-    -x assembler-with-cpp   Passes .s and .S files through C preprocessor.
-    -Dmacro                 Define a preprocessor macro with no value.
-    -Dmacro=value           Define a preprocessor macro with a value.
-
-See the compiler / linker documentation for a full list of switches and
-their use.
-
-Many definitions can be provided at compile-time via the -D option 
-without editing the source code. Here are some of the more useful ones:
-
-    XT_USE_THREAD_SAFE_CLIB Enable support for the reentrancy to provide
-                            thread-safety for the newlib and xclib libraries
-                            supplied with Xtensa Tools. Default ON.
-
-    Note, the follwing defines are unique to the Xtensa port so have names
-    beginning with "XT_".
-
-    XT_SIMULATOR            Set this if building to run on the simulator.
-                            Takes advantage of certain simulator control
-                            and reporting facilities, and adjusts timing 
-                            of periodic tick to provide a more acceptable
-                            performance in simulation (see XT_CLOCK_FREQ).
-                            Set by default unless PLATFORM is overridden.
-
-    XT_BOARD                Set this if building for a supported board.
-                            Be sure to specify the correct LSP for the
-                            board. See the example makefile for usage.
-
-    XT_CLOCK_FREQ=freq      Specifies the target processor's clock 
-                            frequency in Hz. Used primarily to set the 
-                            timer that generates the periodic interrupt.
-                            Defaults are provided and may be edited in
-                            xtensa_timer.h (see comments there also).
-                            Default for simulator provides more acceptable
-                            performance, but cannot provide real-time
-                            performance due to variation in simulation
-                            speed per host platform and insufficient 
-                            cycles between interrupts to process them.
-                            Supported board platforms by default leave 
-                            this undefined and compute the clock frequency 
-                            at initialization unless this is explicitly 
-                            defined.
-
-    XT_TICK_PER_SEC=n       Specifies the frequency of the periodic tick.
-
-    XT_TIMER_INDEX=n        Specifies which timer to use for periodic tick.
-                            Set this if your Xtensa processor configuration 
-                            provides more than one suitable timer and you 
-                            want to override the default. See xtensa_timer.h .
-
-    XT_INTEXC_HOOKS         Enables hooks in interrupt vector handlers
-                            to support dynamic installation of exception
-                            and interrupt handlers. Disabled by default.
-
-    XT_USE_OVLY             Enable code overlay support. It uses a mutex,
-                            hence configUSE_MUTEX must be enabled. This
-                            option is currently unsupported.
-
-    XT_USE_SWPRI            Enable software prioritization of interrupts.
-                            Enabling this will prioritize interrupts with
-                            higher bit numbers over those with lower bit
-                            numbers at the same level. This works only for
-                            low and medium priority interrupts that can be
-                            dispatched to C handlers.
-
-
-Register Usage and Stack Frames
--------------------------------
-
-The Xtensa architecture specifies two ABIs that determine how the general
-purpose registers a0-a15 are used: the standard windowed ABI use with
-the Xtensa windowed register file architecture, and the optional and
-more conventional Call0 ABI (required for Xtensa configurations without
-a windowed register file).
-
-Xtensa processors may have other special registers (including co-processor
-registers and other TIE "states") that are independent of this choice
-of ABI. See Xtensa documentation for more details.
-
-In the windowed ABI the registers of the current window are used as follows:
-    a0      = return address
-    a1      = stack pointer (alias sp)
-    a2      = first argument and result of call (in simple cases)
-    a3-7    = second through sixth arguments of call (in simple cases).
-              Note that complex or large arguments are passed on the
-              stack. Details are in the Xtensa Tools manuals.
-    a8-a15  = available for use as temporaries.
-There are no callee-save registers. The windowed hardware automatically
-saves registers a0-a3 on a call4, a0-a8 on a call8, a0-a12 on a call12,
-by rotating the register window. Hardware triggers window overflow and
-underflow exceptions as necessary when registers outside the current 
-window need to be spilled to preallocated space in the stack frame, or
-restored. Complete details are in the Xtensa manuals. The entire windowed
-register file is saved and restored on interrupt or task context switch.
-
-The Call0 ABI does not make use of register windows, relying instead
-on a fixed set of 16 registers without window rotation.
-The Call0 ABI is more conventional and uses registers as follows:
-    a0      = return address
-    a1      = stack pointer (alias sp)
-    a2      = first argument and result of call (in simple cases)
-    a3-7    = second through sixth arguments of call (in simple cases).
-              Note that complex or large arguments are passed on the
-              stack. Details are in the Xtensa Tools manuals.
-    a8-a11  = scratch.
-    a12-a15 = callee-save (a function must preserve these for its caller).
-On a FreeRTOS API call, callee-save registers are saved only when a task
-context switch occurs, and other registers are not saved at all (the caller
-does not expect them to be preserved). On an interrupt, callee-saved
-registers might only be saved and restored when a task context-switch
-occurs, but all other registers are always saved and restored.
-
-An Xtensa processor has other special registers independent of the ABI,
-depending on the configuration (including co-processor registers and other
-TIE state) that are part of the task context. FreeRTOS preserves all such
-registers over an unsolicited context-switch triggered by an interrupt.
-However it does NOT preserve these over a solicited context-switch during
-a FreeRTOS API call. This bears some explanation. These special registers
-are either ignored by the compiler or treated as caller-saved, meaning
-that if kept "live" over a function call (ie. need to be preserved)
-they must be saved and restored by the caller. Since solicited entry to
-FreeRTOS is always made by a function call, FreeRTOS assumes the caller
-has saved any of these registers that are "live". FreeRTOS avoids a lot
-of overhead by not having to save and restore every special register
-(there can be many) on every solicited context switch.
-
-As a consequence, the application developer should NOT assume that special
-registers are preserved over a FreeRTOS API call such as vTaskDelay().
-If multiple tasks use a register, the caller must save and restore it.
-
-The saved context stack frames for context switches that occur as
-a result of interrupt handling (interrupt frame) or from task-level
-API calls (solicited frame) are described in human readable form in
-xtensa_context.h .  All suspended tasks have one of these two types
-of stack frames. The top of the suspended task's stack is pointed to
-by pxCurrentTCB->pxTopOfStack. A special location common to both stack
-frames differentiates solicited and interrupt stack frames.
-
-
-Improving Performance, Footprint, or Ease of Debugging
-------------------------------------------------------
-
-By default FreeRTOS for Xtensa is built with debug (-g) and without
-compiler optimizations (-O0). This makes debugging easier. Of course,
--O0 costs performance and usually also increases stack usage. To make
-FreeRTOS run faster you can change the Makefile to enable the desired
-optimizations or set a predefined optimization level (-O) .
-
-Maximum performance is achieved with -O3 -ipa, but that might increase 
-the footprint substantially. A good compromise is -O2. See the compiler
-manual for details.
-
-Minimal footprint is achieved by optimizing for space with -Os, at the
-cost of some performance. See the compiler manual for details.
-
-The Xtensa architecture port-specific assembly files are coded with no
-file-scope labels inside functions (all labels inside functions begin with
-".L"). This allows a profiler to accurately associate an address with a
-function, and also allows the debugger's stack trace to show the correct
-function wherever the program counter is within that function. However
-there are some tradeoffs in debugging. Local (".L") labels are not
-visible to the debugger, so the following limitations may be observed
-during debugging:
-- You cannot set a breakpoint on a local label inside a function.
-- Disassembly will show the entire function, but will get out of sync and
-  show incorrect opcodes if it crosses any padding before an aligned local
-  branch target (".L" label, not ".Ln"). Restart disassembly specifying an
-  address range explicitly between points where there is padding.
-Since FreeRTOS is provided in source form, it is not difficult to remove
-the ".L" and ".Ln" prefixes from local labels if you want them visible.
-They can also be made visible by passing the '-L' option to the assembler
-and linker (see the assembler and linker manuals for details).
-
-
-Interrupt and Exception Handling
---------------------------------
-
-FreeRTOS provides a complete set of efficient exception and first-level
-interrupt handlers installed at the appropriate exception and interrupt
-vector locations. The Xtensa architecture supports several different
-classes of exceptions and interrupts. Being a configurable architecture,
-many of these are optional, and the vector locations are determined by
-your processor configuration. (Note that Diamond cores are pre-configured
-with specific vector locations.) The handlers provided use conditional
-compilation to adapt to your processor configuration and include only 
-the code that is needed.
-
-Xtensa vector locations may reside almost anywhere, including in ROM.
-The amount of code space available at each of these locations is
-often very small (e.g. due to following vectors). A small stub of
-code installed at the vector jumps to the corresponding handler,
-usually in RAM. The exception and interrupt handlers are defined in
-xtensa_vectors.S. They are not specific to FreeRTOS, but call into
-FreeRTOS where appropriate via macros defined in xtensa_rtos.h .
-
-The handlers provided for low and medium priority interrupts are just
-dispatchers that save relevant state and call user-definable handlers.
-See the files xtensa_vectors.S and xtensa_api.h for more details of how
-to create and install application-specific user interrupt handlers.
-Similarly, user-defined handlers can be installed for exceptions (other
-than a few which are always handled by the OS).
-
-The high priority interrupt handlers provided may be considered templates
-into which the application adds code to service specific interrupts.
-The places where application handlers should be inserted are tagged with
-the comment "USER_EDIT" in xtensa_vectors.S.
-
-This FreeRTOS port supports strict priority-based nesting of interrupts.
-An interrupt may only nest on top of one of strictly lower priority.
-Equal priority interrupts concurrently pending are handled in an
-application-defined sequence before any lower priority interrupts
-are handled. During interrupt and exception handling, the processor's
-interrupt level (PS.INTLEVEL) is used to control the interrupt priority
-level that can be accepted; interrupt sources are not controlled
-individually by FreeRTOS (the application is free to access the INTENABLE
-register directly to enable/disable individual interrupts, eg. using
-Xtensa HAL services). This approach provides the most deterministic
-bounds on interrupt latency (for a given priority) and stack depth.
-
-Software prioritization of interrupts at the same priority is controlled
-by the definition of XT_USE_SWPRI. See above for a description of this
-parameter.
-
-The following subsections describe the handling of each class of exception
-and interrupt in more detail. Many have nothing to do with FreeRTOS but
-are mentioned because there is code to handle them in xtensa_vectors.S.
-
-User Exception and Interrupt Handler (Low/Medium Priority):
-
-    All Xtensa 'general exceptions' come to the user, kernel, or double
-    exception vector.  The exception type is identified by the EXCCAUSE
-    special register (level 1 interrupts are one particular cause of a
-    general exception). This port sets up PS to direct all such exceptions
-    to the user vector. Exceptions taken at the other two vectors usually
-    indicate a kernel or application bug.
-
-    Level 1 interrupts are identified at the beginning of the handler
-    and are dispatched to a dedicated handler. Then, syscall and alloca
-    exceptions are identified and dispatched to special handlers described
-    below. After this, coprocessor exceptions are identified and dispatched
-    to the coprocessor handler.
-
-    Any remaining exceptions are processed as follows:
-
-    Having allocated the exception stack frame, the user exception handler
-    saves the current task state and sets up a C environment and enables
-    the high-priority class of interrupts (which do not interact with
-    FreeRTOS), then reads EXCCAUSE and uses the cause (number) to index
-    into a table of user-specified handlers. The correct handler is then
-    called. If the handler returns, the context is restored and control is
-    returned to the code that caused the exception. The user-defined handler
-    may alter the saved context, or any other system state, that allows the
-    faulting instruction to be retried.
-
-    If the cause is a level 1 (low-priority) or medium-priority interrupt,
-    the handler enables all interrupts above that priority level after
-    saving the task context. It then sets up the environment for C code
-    and then calls the handler (found in the handler table) for the
-    interrupt number. If the user has not specified a handler, then the
-    default handler will be called, which will terminate the program.
-
-    If the interrupt is for the system timer, it calls a special interrupt
-    handler for the system timer tick, which calls _frxt_timer_int then
-    clears its bit from the mask. This interrupt cannot be hooked by the
-    user-defined handler.
-
-    Finally, the handler calls _frxt_int_exit to allow FreeRTOS to perform
-    any scheduling necessary and return either to the interrupted task
-    or another.
-
-    If software prioritization is enabled, the handler will re-enable all
-    interrupts at the same level that are numerically higher than the current
-    one, before calling the user handler. This allows a higher priority
-    interrupt to pre-empt the lower priority handler.
-
-Medium Priority Interrupt Handlers:
-
-    Medium priority interrupts are those at levels 2 up to XCHAL_EXCM_LEVEL,
-    a configuration-specific maximum interrupt level affected by the global
-    'exception mode' bit in the processor status word (PS.EXCM).
-    Interrupt levels above XCHAL_EXCM_LEVEL are of the high-priority class.
-    The Xtensa hardware documentation considers medium priority interrupts
-    to be a special case of high-priority interrupts, but from a software
-    perspective they are very different.
-
-    Dispatch of medium-priority interrupts is discussed in the section
-    above.
-
-High Priority Interrupt Handlers:
-
-    High priority interrupts are those strictly above XCHAL_EXCM_LEVEL, 
-    a configuration-specific maximum interrupt level affected by the 
-    global 'exception mode' bit in the processor status word (PS.EXCM).
-    High priority handlers may not directly interact with FreeRTOS at all,
-    and are described here only for the sake of completeness. They must
-    be coded in assembler (may not be coded in C) and are intended to be 
-    used for handling extremely high frequency hardware events that need
-    to be handled in only a few cycles. A high priority interrupt handler
-    may trigger a software interrupt at a medium or low priority level to
-    occasionally signal FreeRTOS. Please see Xtensa documentation.
-
-    There is a separate vector and a few special registers for each high
-    priority interrupt, providing for fast dispatch and efficient nesting
-    on top of lower priority interrupts. Handlers are templates included
-    only for the vectors that exist in your Xtensa processor configuration.
-    These templates are written for only one interrupt per high priority 
-    level to minimize latency servicing very fast time-critical interrupts.
-    The vector code jumps to the corresponding first-level interrupt handler,
-    which then executes application-provided assembler code before returning
-    quickly to the interrupted task or lower priority handler.
-
-Kernel Exception Handler:
-
-    Kernel mode is not used in this port of FreeRTOS, and therefore kernel
-    exceptions should not happen. A stub is provided for the vector that
-    triggers the debugger (if connected) or calls _xt_panic to freeze the 
-    processor should a kernel exception occur.
-
-Alloca Exception Handler:
-
-    Alloca exceptions are generated by the 'movsp' instruction, which
-    is used only in the windowed ABI. Its purpose is to allocate some
-    space on top of the stack. Because the window hardware may have
-    spilled some registers to the 16 byte "base save" area below the
-    stack pointer, it is necessary to protect those values. The alloca
-    handler accomplishes this quickly without setting up an interrupt
-    frame or entering FreeRTOS, by emulating a register underflow and
-    re-executing 'movsp'.
-
-Syscall Exception Handler:
-
-    Syscall exceptions are generated by a 'syscall' instruction.
-    The windowed ABI specifies that executing this instruction with
-    a value of zero in register a2 must spill any unsaved registers
-    in the windowed register file to their pre-determined locations
-    on the caller's stack. The handler does exactly that, and skips
-    over the 'syscall' instruction before returning to the caller.
-    If a2 is non-zero, the handler returns a2 == -1 to the caller.
-
-Co-Processor Exception Handler:
-
-    A co-processor exception is generated when a task accesses a
-    co-processor that it does not "own". Ownership represents which
-    task's state is currently in the co-processor. Co-processors are
-    context-switched "lazily" (on demand) only when a non-owning task
-    uses a co-processor instruction, otherwise a task retains ownership
-    even when it is preempted from the main processor. The co-processor
-    exception handler performs the context-switch and manages ownership.
-
-    Co-processors may not be used by any code outside the context of a
-    task. A co-processor exception triggered by code that is not part
-    of a running task is a fatal error and FreeRTOS for Xtensa will panic.
-    This restriction is intended to reduce the overhead of saving and 
-    restoring co-processor state (which can be quite large) and in 
-    particular remove that overhead from interrupt handlers.
-
-Debug Exception Handler:
-
-    A debug exception is caused as a result of running code, such as by
-    a 'break' instruction or hardware breakpoints and watchpoints, or
-    as a result of an external debug interrupt, such as from an OCD based
-    debugger or multiprocessor debug events ("breakin/breakout"). If the
-    processor is running in OCD mode under control of an OCD-based debugger,
-    the trigger event immediately halts the processor and gives control to
-    the OCD debugger. Otherwise control is transferred to the debug vector.
-    The debug vector handler calls the simulator if running on the ISS,
-    which then takes control and interacts with any attached debugger.
-    If running on hardware and not in OCD mode, debug exceptions are not
-    expected, so the debug handler calls _xt_panic to freeze the processor.
-
-Double Exception Handler:
-
-    A double exception is a general exception that happens while the
-    processor is in exception mode (PS.EXCM set), and thus indicates a
-    bug in kernel code. The double exception vector handler triggers
-    the debugger (if connected) or calls _xt_panic to freeze the 
-    processor.
-
-Window Overflow and Underflow Exception Handlers:
-
-    Window overflow and underflow handlers are required for use of the
-    windowed ABI. Each has its own dedicated vector and highly optimized
-    code that is independent of OS. See Xtensa documentation for details.
-
-Hooks for Dynamic Installation of Handlers:
-
-    Optional hooks are provided in the user exception and low level
-    interrupt handler and all medium and high priority interrupt handlers,
-    to dynamically install a handler function (which may be coded in C,
-    unless in a high-priority interrupt handler). These hooks are enabled
-    and used by automatic regression tests, they are not part of a normal
-    FreeRTOS build. However an application is free to take advantage of
-    them. The interrupt/exception hooks are described in xtensa_rtos.h .
-
-    It is recommended that the application not make use of these hooks, but
-    rather use xt_set_interrupt_handler() and xt_set_exception_handler()
-    to install application-specific handlers. This method is more convenient
-    and allows arguments to be passed to the handlers. Software prioritization
-    of interrupts works only with this method. See xtensa_api.h for details.
-
-Overlay Support
-
-    Code overlays are currently not supported for FreeRTOS. This will be
-    supported in a future release. Make sure that the option XT_USE_OVLY is
-    never defined when building.
-
-
--End-
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
deleted file mode 100755
index 8e2d8c9..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_api.h
+++ /dev/null
@@ -1,123 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Xtensa-specific API for RTOS ports.
- */
-
-#ifndef __XTENSA_API_H__
-#define __XTENSA_API_H__
-
-#include 
-
-#include "xtensa_context.h"
-
-
-/* Typedef for C-callable interrupt handler function */
-typedef void (*xt_handler)(void *);
-
-/* Typedef for C-callable exception handler function */
-typedef void (*xt_exc_handler)(XtExcFrame *);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to set a handler for the specified exception.
-
-    n        - Exception number (type)
-    f        - Handler function address, NULL to uninstall handler.
-
-  The handler will be passed a pointer to the exception frame, which is created
-  on the stack of the thread that caused the exception.
-
-  If the handler returns, the thread context will be restored and the faulting
-  instruction will be retried. Any values in the exception frame that are
-  modified by the handler will be restored as part of the context. For details
-  of the exception frame structure see xtensa_context.h.
--------------------------------------------------------------------------------
-*/
-extern xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to set a handler for the specified interrupt.
- 
-    n        - Interrupt number.
-    f        - Handler function address, NULL to uninstall handler.
-    arg      - Argument to be passed to handler.
--------------------------------------------------------------------------------
-*/
-extern xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to enable the specified interrupts.
-
-    mask     - Bit mask of interrupts to be enabled.
-
-  Returns the previous state of the interrupt enables.
--------------------------------------------------------------------------------
-*/
-extern unsigned int xt_ints_on(unsigned int mask);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to disable the specified interrupts.
-
-    mask     - Bit mask of interrupts to be disabled.
-
-  Returns the previous state of the interrupt enables.
--------------------------------------------------------------------------------
-*/
-extern unsigned int xt_ints_off(unsigned int mask);
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to set the specified (s/w) interrupt.
--------------------------------------------------------------------------------
-*/
-static inline void xt_set_intset(unsigned int arg)
-{
-    xthal_set_intset(arg);
-}
-
-
-/*
--------------------------------------------------------------------------------
-  Call this function to clear the specified (s/w or edge-triggered)
-  interrupt.
--------------------------------------------------------------------------------
-*/
-static inline void xt_set_intclear(unsigned int arg)
-{
-    xthal_set_intclear(arg);
-}
-
-
-#endif /* __XTENSA_API_H__ */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
deleted file mode 100755
index 43f3daa..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_config.h
+++ /dev/null
@@ -1,183 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Configuration-specific information for Xtensa build. This file must be
- * included in FreeRTOSConfig.h to properly set up the config-dependent
- * parameters correctly.
- *
- * NOTE: To enable thread-safe C library support, XT_USE_THREAD_SAFE_CLIB must
- * be defined to be > 0 somewhere above or on the command line.
- */
-
-#ifndef XTENSA_CONFIG_H
-#define XTENSA_CONFIG_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include 
-#include 
-#include 	/* required for XSHAL_CLIB */
-
-#include "xtensa_context.h"
-
-
-/*-----------------------------------------------------------------------------
-*                                 STACK REQUIREMENTS
-*
-* This section defines the minimum stack size, and the extra space required to
-* be allocated for saving coprocessor state and/or C library state information
-* (if thread safety is enabled for the C library). The sizes are in bytes.
-*
-* Stack sizes for individual tasks should be derived from these minima based on
-* the maximum call depth of the task and the maximum level of interrupt nesting.
-* A minimum stack size is defined by XT_STACK_MIN_SIZE. This minimum is based
-* on the requirement for a task that calls nothing else but can be interrupted.
-* This assumes that interrupt handlers do not call more than a few levels deep.
-* If this is not true, i.e. one or more interrupt handlers make deep calls then
-* the minimum must be increased.
-*
-* If the Xtensa processor configuration includes coprocessors, then space is 
-* allocated to save the coprocessor state on the stack.
-*
-* If thread safety is enabled for the C runtime library, (XT_USE_THREAD_SAFE_CLIB
-* is defined) then space is allocated to save the C library context in the TCB.
-* 
-* Allocating insufficient stack space is a common source of hard-to-find errors.
-* During development, it is best to enable the FreeRTOS stack checking features.
-*
-* Usage:
-* 
-* XT_USE_THREAD_SAFE_CLIB -- Define this to a nonzero value to enable thread-safe
-*                            use of the C library. This will require extra stack
-*                            space to be allocated for tasks that use the C library
-*                            reentrant functions. See below for more information.
-* 
-* NOTE: The Xtensa toolchain supports multiple C libraries and not all of them
-* support thread safety. Check your core configuration to see which C library
-* was chosen for your system.
-* 
-* XT_STACK_MIN_SIZE       -- The minimum stack size for any task. It is recommended
-*                            that you do not use a stack smaller than this for any
-*                            task. In case you want to use stacks smaller than this
-*                            size, you must verify that the smaller size(s) will work
-*                            under all operating conditions.
-*
-* XT_STACK_EXTRA          -- The amount of extra stack space to allocate for a task
-*                            that does not make C library reentrant calls. Add this
-*                            to the amount of stack space required by the task itself.
-*
-* XT_STACK_EXTRA_CLIB     -- The amount of space to allocate for C library state.
-*
------------------------------------------------------------------------------*/
-
-/* Extra space required for interrupt/exception hooks. */
-#ifdef XT_INTEXC_HOOKS
-  #ifdef __XTENSA_CALL0_ABI__
-    #define STK_INTEXC_EXTRA        0x200
-  #else
-    #define STK_INTEXC_EXTRA        0x180
-  #endif
-#else
-  #define STK_INTEXC_EXTRA          0
-#endif
-
-/* Check C library thread safety support and compute size of C library save area.
-   For the supported libraries, we enable thread safety by default, and this can
-   be overridden from the compiler/make command line. */
-#if (XSHAL_CLIB == XTHAL_CLIB_NEWLIB) || (XSHAL_CLIB == XTHAL_CLIB_XCLIB)
-  #ifndef XT_USE_THREAD_SAFE_CLIB
-    #define XT_USE_THREAD_SAFE_CLIB         1
-  #endif
-#else
-  #define XT_USE_THREAD_SAFE_CLIB           0
-#endif
-
-#if XT_USE_THREAD_SAFE_CLIB > 0u
-  #if XSHAL_CLIB == XTHAL_CLIB_XCLIB
-    #define XT_HAVE_THREAD_SAFE_CLIB        1
-    #if !defined __ASSEMBLER__
-      #include 
-      #define XT_CLIB_CONTEXT_AREA_SIZE     ((sizeof(struct _reent) + 15) + (-16))
-      #define XT_CLIB_GLOBAL_PTR            _reent_ptr
-      #define _REENT_INIT_PTR               _init_reent
-      #define _impure_ptr                   _reent_ptr
-
-      void _reclaim_reent(void * ptr);
-    #endif
-  #elif XSHAL_CLIB == XTHAL_CLIB_NEWLIB
-    #define XT_HAVE_THREAD_SAFE_CLIB        1
-    #if !defined __ASSEMBLER__
-      #include 
-      #define XT_CLIB_CONTEXT_AREA_SIZE     ((sizeof(struct _reent) + 15) + (-16))
-      #define XT_CLIB_GLOBAL_PTR            _impure_ptr
-    #endif
-  #else
-    #define XT_HAVE_THREAD_SAFE_CLIB        0
-    #error The selected C runtime library is not thread safe.
-  #endif
-#else
-  #define XT_CLIB_CONTEXT_AREA_SIZE         0
-#endif
-
-/*------------------------------------------------------------------------------
-  Extra size -- interrupt frame plus coprocessor save area plus hook space.
-  NOTE: Make sure XT_INTEXC_HOOKS is undefined unless you really need the hooks.
-------------------------------------------------------------------------------*/
-#ifdef __XTENSA_CALL0_ABI__
-  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x10 + XT_CP_SIZE)
-#else
-  #define XT_XTRA_SIZE            (XT_STK_FRMSZ + STK_INTEXC_EXTRA + 0x20 + XT_CP_SIZE)
-#endif
-
-/*------------------------------------------------------------------------------
-  Space allocated for user code -- function calls and local variables.
-  NOTE: This number can be adjusted to suit your needs. You must verify that the
-  amount of space you reserve is adequate for the worst-case conditions in your
-  application.
-  NOTE: The windowed ABI requires more stack, since space has to be reserved
-  for spilling register windows.
-------------------------------------------------------------------------------*/
-#ifdef __XTENSA_CALL0_ABI__
-  #define XT_USER_SIZE            0x200
-#else
-  #define XT_USER_SIZE            0x400
-#endif
-
-/* Minimum recommended stack size. */
-#define XT_STACK_MIN_SIZE         ((XT_XTRA_SIZE + XT_USER_SIZE) / sizeof(unsigned char))
-
-/* OS overhead with and without C library thread context. */
-#define XT_STACK_EXTRA              (XT_XTRA_SIZE)
-#define XT_STACK_EXTRA_CLIB         (XT_XTRA_SIZE + XT_CLIB_CONTEXT_AREA_SIZE)
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* XTENSA_CONFIG_H */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S
deleted file mode 100755
index d3748c7..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.S
+++ /dev/null
@@ -1,625 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * XTENSA CONTEXT SAVE AND RESTORE ROUTINES
- *
- * Low-level Call0 functions for handling generic context save and restore of
- * registers not specifically addressed by the interrupt vectors and handlers.
- * Those registers (not handled by these functions) are PC, PS, A0, A1 (SP).
- * Except for the calls to RTOS functions, this code is generic to Xtensa.
- *
- * Note that in Call0 ABI, interrupt handlers are expected to preserve the callee-
- * save regs (A12-A15), which is always the case if the handlers are coded in C.
- * However A12, A13 are made available as scratch registers for interrupt dispatch
- * code, so are presumed saved anyway, and are always restored even in Call0 ABI.
- * Only A14, A15 are truly handled as callee-save regs.
- *
- * Because Xtensa is a configurable architecture, this port supports all user
- * generated configurations (except restrictions stated in the release notes).
- * This is accomplished by conditional compilation using macros and functions
- * defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
- * Only the processor state included in your configuration is saved and restored,
- * including any processor state added by user configuration options or TIE.
- */
-
-/*  Warn nicely if this file gets named with a lowercase .s instead of .S:  */
-#define NOERROR #
-NOERROR: .error "C preprocessor needed for this file: make sure its filename\
- ends in uppercase .S, or use xt-xcc's -x assembler-with-cpp option."
-
-
-#include "xtensa_rtos.h"
-
-#ifdef XT_USE_OVLY
-#include 
-#endif
-
-    .text
-
-/*******************************************************************************
-
-_xt_context_save
-
-    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
-
-Saves all Xtensa processor state except PC, PS, A0, A1 (SP), A12, A13, in the
-interrupt stack frame defined in xtensa_rtos.h.
-Its counterpart is _xt_context_restore (which also restores A12, A13).
-
-Caller is expected to have saved PC, PS, A0, A1 (SP), A12, A13 in the frame.
-This function preserves A12 & A13 in order to provide the caller with 2 scratch 
-regs that need not be saved over the call to this function. The choice of which
-2 regs to provide is governed by xthal_window_spill_nw and xthal_save_extra_nw,
-to avoid moving data more than necessary. Caller can assign regs accordingly.
-
-Entry Conditions:
-    A0  = Return address in caller.
-    A1  = Stack pointer of interrupted thread or handler ("interruptee").
-    Original A12, A13 have already been saved in the interrupt stack frame.
-    Other processor state except PC, PS, A0, A1 (SP), A12, A13, is as at the 
-    point of interruption.
-    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
-
-Exit conditions:
-    A0  = Return address in caller.
-    A1  = Stack pointer of interrupted thread or handler ("interruptee").
-    A12, A13 as at entry (preserved).
-    If windowed ABI, PS.EXCM = 1 (exceptions disabled).
-
-*******************************************************************************/
-
-    .global _xt_context_save
-    .type   _xt_context_save,@function
-    .align  4
-_xt_context_save:
-
-    s32i    a2,  sp, XT_STK_A2
-    s32i    a3,  sp, XT_STK_A3
-    s32i    a4,  sp, XT_STK_A4
-    s32i    a5,  sp, XT_STK_A5
-    s32i    a6,  sp, XT_STK_A6
-    s32i    a7,  sp, XT_STK_A7
-    s32i    a8,  sp, XT_STK_A8
-    s32i    a9,  sp, XT_STK_A9
-    s32i    a10, sp, XT_STK_A10
-    s32i    a11, sp, XT_STK_A11
-
-    /*
-    Call0 ABI callee-saved regs a12-15 do not need to be saved here.
-    a12-13 are the caller's responsibility so it can use them as scratch.
-    So only need to save a14-a15 here for Windowed ABI (not Call0).
-    */
-    #ifndef __XTENSA_CALL0_ABI__
-    s32i    a14, sp, XT_STK_A14
-    s32i    a15, sp, XT_STK_A15
-    #endif
-
-    rsr     a3,  SAR
-    s32i    a3,  sp, XT_STK_SAR
-
-    #if XCHAL_HAVE_LOOPS
-    rsr     a3,  LBEG
-    s32i    a3,  sp, XT_STK_LBEG
-    rsr     a3,  LEND
-    s32i    a3,  sp, XT_STK_LEND
-    rsr     a3,  LCOUNT
-    s32i    a3,  sp, XT_STK_LCOUNT
-    #endif
-
-    #if XT_USE_SWPRI
-    /* Save virtual priority mask */
-    movi    a3,  _xt_vpri_mask
-    l32i    a3,  a3, 0
-    s32i    a3,  sp, XT_STK_VPRI
-    #endif
-
-    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
-    mov     a9,  a0                     /* preserve ret addr */
-    #endif
-
-    #ifndef __XTENSA_CALL0_ABI__
-    /*
-    To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
-    Need to save a9,12,13 temporarily (in frame temps) and recover originals.
-    Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
-    and underflow exceptions disabled (assured by PS.EXCM == 1).
-    */
-    s32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
-    s32i    a13, sp, XT_STK_TMP1    
-    s32i    a9,  sp, XT_STK_TMP2    
-
-    /*
-    Save the overlay state if we are supporting overlays. Since we just saved
-    three registers, we can conveniently use them here. Note that as of now,
-    overlays only work for windowed calling ABI.
-    */
-    #ifdef XT_USE_OVLY
-    l32i    a9,  sp, XT_STK_PC          /* recover saved PC */
-    _xt_overlay_get_state    a9, a12, a13
-    s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
-    #endif
-
-    l32i    a12, sp, XT_STK_A12         /* recover original a9,12,13 */
-    l32i    a13, sp, XT_STK_A13
-    l32i    a9,  sp, XT_STK_A9
-    addi    sp,  sp, XT_STK_FRMSZ       /* restore the interruptee's SP */
-    call0   xthal_window_spill_nw       /* preserves only a4,5,8,9,12,13 */
-    addi    sp,  sp, -XT_STK_FRMSZ
-    l32i    a12, sp, XT_STK_TMP0        /* recover stuff from stack frame */
-    l32i    a13, sp, XT_STK_TMP1    
-    l32i    a9,  sp, XT_STK_TMP2    
-    #endif
-
-    #if XCHAL_EXTRA_SA_SIZE > 0
-    /*  
-    NOTE: Normally the xthal_save_extra_nw macro only affects address
-    registers a2-a5. It is theoretically possible for Xtensa processor
-    designers to write TIE that causes more address registers to be
-    affected, but it is generally unlikely. If that ever happens,
-    more registers need to be saved/restored around this macro invocation.
-    Here we assume a9,12,13 are preserved.
-    Future Xtensa tools releases might limit the regs that can be affected.
-    */
-    addi    a2,  sp, XT_STK_EXTRA       /* where to save it */
-    # if XCHAL_EXTRA_SA_ALIGN > 16
-    movi    a3, -XCHAL_EXTRA_SA_ALIGN
-    and     a2, a2, a3                  /* align dynamically >16 bytes */
-    # endif
-    call0   xthal_save_extra_nw         /* destroys a0,2,3,4,5 */
-    #endif
-
-    #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
-    mov     a0, a9                      /* retrieve ret addr */
-    #endif
-
-    ret
-
-/*******************************************************************************
-
-_xt_context_restore
-
-    !! MUST BE CALLED ONLY BY 'CALL0' INSTRUCTION !!
-
-Restores all Xtensa processor state except PC, PS, A0, A1 (SP) (and in Call0
-ABI, A14, A15 which are preserved by all interrupt handlers) from an interrupt 
-stack frame defined in xtensa_rtos.h .
-Its counterpart is _xt_context_save (whose caller saved A12, A13).
-
-Caller is responsible to restore PC, PS, A0, A1 (SP).
-
-Entry Conditions:
-    A0  = Return address in caller.
-    A1  = Stack pointer of interrupted thread or handler ("interruptee").
-
-Exit conditions:
-    A0  = Return address in caller.
-    A1  = Stack pointer of interrupted thread or handler ("interruptee").
-    Other processor state except PC, PS, A0, A1 (SP), is as at the point 
-    of interruption.
-
-*******************************************************************************/
-
-    .global _xt_context_restore
-    .type   _xt_context_restore,@function
-    .align  4
-_xt_context_restore:
-
-    #if XCHAL_EXTRA_SA_SIZE > 0
-    /*  
-    NOTE: Normally the xthal_restore_extra_nw macro only affects address
-    registers a2-a5. It is theoretically possible for Xtensa processor
-    designers to write TIE that causes more address registers to be
-    affected, but it is generally unlikely. If that ever happens,
-    more registers need to be saved/restored around this macro invocation.
-    Here we only assume a13 is preserved.
-    Future Xtensa tools releases might limit the regs that can be affected.
-    */
-    mov     a13, a0                     /* preserve ret addr */
-    addi    a2,  sp, XT_STK_EXTRA       /* where to find it */
-    # if XCHAL_EXTRA_SA_ALIGN > 16
-    movi    a3, -XCHAL_EXTRA_SA_ALIGN
-    and     a2, a2, a3                  /* align dynamically >16 bytes */
-    # endif
-    call0   xthal_restore_extra_nw      /* destroys a0,2,3,4,5 */
-    mov     a0,  a13                    /* retrieve ret addr */
-    #endif
-
-    #if XCHAL_HAVE_LOOPS
-    l32i    a2,  sp, XT_STK_LBEG
-    l32i    a3,  sp, XT_STK_LEND
-    wsr     a2,  LBEG
-    l32i    a2,  sp, XT_STK_LCOUNT
-    wsr     a3,  LEND
-    wsr     a2,  LCOUNT
-    #endif
-
-    #ifdef XT_USE_OVLY
-    /*
-    If we are using overlays, this is a good spot to check if we need
-    to restore an overlay for the incoming task. Here we have a bunch
-    of registers to spare. Note that this step is going to use a few
-    bytes of storage below SP (SP-20 to SP-32) if an overlay is going
-    to be restored.
-    */
-    l32i    a2,  sp, XT_STK_PC          /* retrieve PC */
-    l32i    a3,  sp, XT_STK_PS          /* retrieve PS */
-    l32i    a4,  sp, XT_STK_OVLY        /* retrieve overlay state */
-    l32i    a5,  sp, XT_STK_A1          /* retrieve stack ptr */
-    _xt_overlay_check_map    a2, a3, a4, a5, a6
-    s32i    a2,  sp, XT_STK_PC          /* save updated PC */
-    s32i    a3,  sp, XT_STK_PS          /* save updated PS */
-    #endif
-
-    #ifdef XT_USE_SWPRI
-    /* Restore virtual interrupt priority and interrupt enable */
-    movi    a3,  _xt_intdata
-    l32i    a4,  a3, 0                  /* a4 = _xt_intenable */
-    l32i    a5,  sp, XT_STK_VPRI        /* a5 = saved _xt_vpri_mask */
-    and     a4,  a4, a5
-    wsr     a4,  INTENABLE              /* update INTENABLE */
-    s32i    a5,  a3, 4                  /* restore _xt_vpri_mask */
-    #endif
-
-    l32i    a3,  sp, XT_STK_SAR
-    l32i    a2,  sp, XT_STK_A2
-    wsr     a3,  SAR
-    l32i    a3,  sp, XT_STK_A3
-    l32i    a4,  sp, XT_STK_A4
-    l32i    a5,  sp, XT_STK_A5
-    l32i    a6,  sp, XT_STK_A6
-    l32i    a7,  sp, XT_STK_A7
-    l32i    a8,  sp, XT_STK_A8
-    l32i    a9,  sp, XT_STK_A9
-    l32i    a10, sp, XT_STK_A10
-    l32i    a11, sp, XT_STK_A11
-
-    /*
-    Call0 ABI callee-saved regs a12-15 do not need to be restored here.
-    However a12-13 were saved for scratch before XT_RTOS_INT_ENTER(), 
-    so need to be restored anyway, despite being callee-saved in Call0.
-    */
-    l32i    a12, sp, XT_STK_A12
-    l32i    a13, sp, XT_STK_A13
-    #ifndef __XTENSA_CALL0_ABI__
-    l32i    a14, sp, XT_STK_A14
-    l32i    a15, sp, XT_STK_A15
-    #endif
-
-    ret
-
-
-/*******************************************************************************
-
-_xt_coproc_init
-
-Initializes global co-processor management data, setting all co-processors
-to "unowned". Leaves CPENABLE as it found it (does NOT clear it).
-
-Called during initialization of the RTOS, before any threads run.
-
-This may be called from normal Xtensa single-threaded application code which
-might use co-processors. The Xtensa run-time initialization enables all 
-co-processors. They must remain enabled here, else a co-processor exception
-might occur outside of a thread, which the exception handler doesn't expect.
-
-Entry Conditions:
-    Xtensa single-threaded run-time environment is in effect.
-    No thread is yet running.
-
-Exit conditions:
-    None.
-
-Obeys ABI conventions per prototype:
-    void _xt_coproc_init(void)
-
-*******************************************************************************/
-
-#if XCHAL_CP_NUM > 0
-
-    .global _xt_coproc_init
-    .type   _xt_coproc_init,@function
-    .align  4
-_xt_coproc_init:
-    ENTRY0
-
-    /* Initialize thread co-processor ownerships to 0 (unowned). */
-    movi    a2, _xt_coproc_owner_sa         /* a2 = base of owner array */
-    addi    a3, a2, XCHAL_CP_MAX << 2       /* a3 = top+1 of owner array */
-    movi    a4, 0                           /* a4 = 0 (unowned) */
-1:  s32i    a4, a2, 0
-    addi    a2, a2, 4
-    bltu    a2, a3, 1b
-
-    RET0
-
-#endif
-
-
-/*******************************************************************************
-
-_xt_coproc_release
-
-Releases any and all co-processors owned by a given thread. The thread is 
-identified by it's co-processor state save area defined in xtensa_context.h .
-
-Must be called before a thread's co-proc save area is deleted to avoid
-memory corruption when the exception handler tries to save the state.
-May be called when a thread terminates or completes but does not delete
-the co-proc save area, to avoid the exception handler having to save the 
-thread's co-proc state before another thread can use it (optimization).
-
-Entry Conditions:
-    A2  = Pointer to base of co-processor state save area.
-
-Exit conditions:
-    None.
-
-Obeys ABI conventions per prototype:
-    void _xt_coproc_release(void * coproc_sa_base)
-
-*******************************************************************************/
-
-#if XCHAL_CP_NUM > 0
-
-    .global _xt_coproc_release
-    .type   _xt_coproc_release,@function
-    .align  4
-_xt_coproc_release:
-    ENTRY0                                  /* a2 = base of save area */
-
-    movi    a3, _xt_coproc_owner_sa         /* a3 = base of owner array */
-    addi    a4, a3, XCHAL_CP_MAX << 2       /* a4 = top+1 of owner array */
-    movi    a5, 0                           /* a5 = 0 (unowned) */
-
-    rsil    a6, XCHAL_EXCM_LEVEL            /* lock interrupts */
-
-1:  l32i    a7, a3, 0                       /* a7 = owner at a3 */
-    bne     a2, a7, 2f                      /* if (coproc_sa_base == owner) */
-    s32i    a5, a3, 0                       /*   owner = unowned */
-2:  addi    a3, a3, 1<<2                    /* a3 = next entry in owner array */
-    bltu    a3, a4, 1b                      /* repeat until end of array */
-
-3:  wsr     a6, PS                          /* restore interrupts */
-
-    RET0
-
-#endif
-
-
-/*******************************************************************************
-_xt_coproc_savecs
-
-If there is a current thread and it has a coprocessor state save area, then
-save all callee-saved state into this area. This function is called from the
-solicited context switch handler. It calls a system-specific function to get
-the coprocessor save area base address.
-
-Entry conditions:
-    - The thread being switched out is still the current thread.
-    - CPENABLE state reflects which coprocessors are active.
-    - Registers have been saved/spilled already.
-
-Exit conditions:
-    - All necessary CP callee-saved state has been saved.
-    - Registers a2-a7, a13-a15 have been trashed.
-
-Must be called from assembly code only, using CALL0.
-*******************************************************************************/
-#if XCHAL_CP_NUM > 0
-
-    .extern     _xt_coproc_sa_offset   /* external reference */
-
-    .global     _xt_coproc_savecs
-    .type       _xt_coproc_savecs,@function
-    .align      4
-_xt_coproc_savecs:
-
-    /* At entry, CPENABLE should be showing which CPs are enabled. */
-
-    rsr     a2, CPENABLE                /* a2 = which CPs are enabled      */
-    beqz    a2, .Ldone                  /* quick exit if none              */
-    mov     a14, a0                     /* save return address             */
-    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
-    mov     a0, a14                     /* restore return address          */
-    beqz    a15, .Ldone                 /* if none then nothing to do      */
-    s16i    a2, a15, XT_CP_CS_ST        /* save mask of CPs being stored   */
-    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
-    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
-
-#if XCHAL_CP0_SA_SIZE
-    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
-    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
-    add     a3, a14, a15                /* a3 = save area for CP 0         */
-    xchal_cp0_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP1_SA_SIZE
-    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
-    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
-    add     a3, a14, a15                /* a3 = save area for CP 1         */
-    xchal_cp1_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP2_SA_SIZE
-    bbci.l  a2, 2, 2f
-    l32i    a14, a13, 8
-    add     a3, a14, a15
-    xchal_cp2_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP3_SA_SIZE
-    bbci.l  a2, 3, 2f
-    l32i    a14, a13, 12
-    add     a3, a14, a15
-    xchal_cp3_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP4_SA_SIZE
-    bbci.l  a2, 4, 2f
-    l32i    a14, a13, 16
-    add     a3, a14, a15
-    xchal_cp4_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP5_SA_SIZE
-    bbci.l  a2, 5, 2f
-    l32i    a14, a13, 20
-    add     a3, a14, a15
-    xchal_cp5_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP6_SA_SIZE
-    bbci.l  a2, 6, 2f
-    l32i    a14, a13, 24
-    add     a3, a14, a15
-    xchal_cp6_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP7_SA_SIZE
-    bbci.l  a2, 7, 2f
-    l32i    a14, a13, 28
-    add     a3, a14, a15
-    xchal_cp7_store a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-.Ldone:
-    ret
-#endif
-
-
-/*******************************************************************************
-_xt_coproc_restorecs
-
-Restore any callee-saved coprocessor state for the incoming thread.
-This function is called from coprocessor exception handling, when giving
-ownership to a thread that solicited a context switch earlier. It calls a
-system-specific function to get the coprocessor save area base address.
-
-Entry conditions:
-    - The incoming thread is set as the current thread.
-    - CPENABLE is set up correctly for all required coprocessors.
-    - a2 = mask of coprocessors to be restored.
-
-Exit conditions:
-    - All necessary CP callee-saved state has been restored.
-    - CPENABLE - unchanged.
-    - Registers a2-a7, a13-a15 have been trashed.
-
-Must be called from assembly code only, using CALL0.
-*******************************************************************************/
-#if XCHAL_CP_NUM > 0
-
-    .global     _xt_coproc_restorecs
-    .type       _xt_coproc_restorecs,@function
-    .align      4
-_xt_coproc_restorecs:
-
-    mov     a14, a0                     /* save return address             */
-    call0   XT_RTOS_CP_STATE            /* get address of CP save area     */
-    mov     a0, a14                     /* restore return address          */
-    beqz    a15, .Ldone2                /* if none then nothing to do      */
-    l16ui   a3, a15, XT_CP_CS_ST        /* a3 = which CPs have been saved  */
-    xor     a3, a3, a2                  /* clear the ones being restored   */
-    s32i    a3, a15, XT_CP_CS_ST        /* update saved CP mask            */
-    movi    a13, _xt_coproc_sa_offset   /* array of CP save offsets        */
-    l32i    a15, a15, XT_CP_ASA         /* a15 = base of aligned save area */
-    
-#if XCHAL_CP0_SA_SIZE
-    bbci.l  a2, 0, 2f                   /* CP 0 not enabled                */
-    l32i    a14, a13, 0                 /* a14 = _xt_coproc_sa_offset[0]   */
-    add     a3, a14, a15                /* a3 = save area for CP 0         */
-    xchal_cp0_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:  
-#endif
-
-#if XCHAL_CP1_SA_SIZE
-    bbci.l  a2, 1, 2f                   /* CP 1 not enabled                */
-    l32i    a14, a13, 4                 /* a14 = _xt_coproc_sa_offset[1]   */
-    add     a3, a14, a15                /* a3 = save area for CP 1         */
-    xchal_cp1_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP2_SA_SIZE
-    bbci.l  a2, 2, 2f
-    l32i    a14, a13, 8
-    add     a3, a14, a15
-    xchal_cp2_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP3_SA_SIZE
-    bbci.l  a2, 3, 2f
-    l32i    a14, a13, 12
-    add     a3, a14, a15
-    xchal_cp3_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP4_SA_SIZE
-    bbci.l  a2, 4, 2f
-    l32i    a14, a13, 16
-    add     a3, a14, a15
-    xchal_cp4_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP5_SA_SIZE
-    bbci.l  a2, 5, 2f
-    l32i    a14, a13, 20
-    add     a3, a14, a15
-    xchal_cp5_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP6_SA_SIZE
-    bbci.l  a2, 6, 2f
-    l32i    a14, a13, 24
-    add     a3, a14, a15
-    xchal_cp6_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-#if XCHAL_CP7_SA_SIZE
-    bbci.l  a2, 7, 2f
-    l32i    a14, a13, 28
-    add     a3, a14, a15
-    xchal_cp7_load a3, a4, a5, a6, a7 continue=0 ofs=-1 select=XTHAL_SAS_TIE|XTHAL_SAS_NOCC|XTHAL_SAS_CALE alloc=XTHAL_SAS_ALL
-2:
-#endif
-
-.Ldone2:
-    ret
-
-#endif
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
deleted file mode 100755
index 8898e11..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_context.h
+++ /dev/null
@@ -1,351 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * XTENSA CONTEXT FRAMES AND MACROS FOR RTOS ASSEMBLER SOURCES
- *
- * This header contains definitions and macros for use primarily by Xtensa
- * RTOS assembly coded source files. It includes and uses the Xtensa hardware
- * abstraction layer (HAL) to deal with config specifics. It may also be
- * included in C source files.
- *
- * !! Supports only Xtensa Exception Architecture 2 (XEA2). XEA1 not supported. !!
- *
- * NOTE: The Xtensa architecture requires stack pointer alignment to 16 bytes.
- */
-
-#ifndef XTENSA_CONTEXT_H
-#define XTENSA_CONTEXT_H
-
-#ifdef __ASSEMBLER__
-#include    
-#endif
-
-#include    
-#include    
-#include    
-
-
-/* Align a value up to nearest n-byte boundary, where n is a power of 2. */
-#define ALIGNUP(n, val) (((val) + (n)-1) & -(n))
-
-
-/*
--------------------------------------------------------------------------------
-  Macros that help define structures for both C and assembler.
--------------------------------------------------------------------------------
-*/
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-
-#define STRUCT_BEGIN            .pushsection .text; .struct 0
-#define STRUCT_FIELD(ctype,size,asname,name)    asname: .space  size
-#define STRUCT_AFIELD(ctype,size,asname,name,n) asname: .space  (size)*(n)
-#define STRUCT_END(sname)       sname##Size:; .popsection
-
-#else
-
-#define STRUCT_BEGIN            typedef struct {
-#define STRUCT_FIELD(ctype,size,asname,name)    ctype   name;
-#define STRUCT_AFIELD(ctype,size,asname,name,n) ctype   name[n];
-#define STRUCT_END(sname)       } sname;
-
-#endif //_ASMLANGUAGE || __ASSEMBLER__
-
-
-/*
--------------------------------------------------------------------------------
-  INTERRUPT/EXCEPTION STACK FRAME FOR A THREAD OR NESTED INTERRUPT
-
-  A stack frame of this structure is allocated for any interrupt or exception.
-  It goes on the current stack. If the RTOS has a system stack for handling 
-  interrupts, every thread stack must allow space for just one interrupt stack 
-  frame, then nested interrupt stack frames go on the system stack.
-
-  The frame includes basic registers (explicit) and "extra" registers introduced 
-  by user TIE or the use of the MAC16 option in the user's Xtensa config.
-  The frame size is minimized by omitting regs not applicable to user's config.
-
-  For Windowed ABI, this stack frame includes the interruptee's base save area,
-  another base save area to manage gcc nested functions, and a little temporary 
-  space to help manage the spilling of the register windows.
--------------------------------------------------------------------------------
-*/
-
-STRUCT_BEGIN
-STRUCT_FIELD (long, 4, XT_STK_EXIT,     exit) /* exit point for dispatch */
-STRUCT_FIELD (long, 4, XT_STK_PC,       pc)   /* return PC */
-STRUCT_FIELD (long, 4, XT_STK_PS,       ps)   /* return PS */
-STRUCT_FIELD (long, 4, XT_STK_A0,       a0)
-STRUCT_FIELD (long, 4, XT_STK_A1,       a1)   /* stack pointer before interrupt */
-STRUCT_FIELD (long, 4, XT_STK_A2,       a2)
-STRUCT_FIELD (long, 4, XT_STK_A3,       a3)
-STRUCT_FIELD (long, 4, XT_STK_A4,       a4)
-STRUCT_FIELD (long, 4, XT_STK_A5,       a5)
-STRUCT_FIELD (long, 4, XT_STK_A6,       a6)
-STRUCT_FIELD (long, 4, XT_STK_A7,       a7)
-STRUCT_FIELD (long, 4, XT_STK_A8,       a8)
-STRUCT_FIELD (long, 4, XT_STK_A9,       a9)
-STRUCT_FIELD (long, 4, XT_STK_A10,      a10)
-STRUCT_FIELD (long, 4, XT_STK_A11,      a11)
-STRUCT_FIELD (long, 4, XT_STK_A12,      a12)
-STRUCT_FIELD (long, 4, XT_STK_A13,      a13)
-STRUCT_FIELD (long, 4, XT_STK_A14,      a14)
-STRUCT_FIELD (long, 4, XT_STK_A15,      a15)
-STRUCT_FIELD (long, 4, XT_STK_SAR,      sar)
-STRUCT_FIELD (long, 4, XT_STK_EXCCAUSE, exccause)
-STRUCT_FIELD (long, 4, XT_STK_EXCVADDR, excvaddr)
-#if XCHAL_HAVE_LOOPS
-STRUCT_FIELD (long, 4, XT_STK_LBEG,   lbeg)
-STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
-STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
-#endif
-#ifndef __XTENSA_CALL0_ABI__
-/* Temporary space for saving stuff during window spill */
-STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
-STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
-STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
-#endif
-#ifdef XT_USE_SWPRI
-/* Storage for virtual priority mask */
-STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)
-#endif
-#ifdef XT_USE_OVLY
-/* Storage for overlay state */
-STRUCT_FIELD (long, 4, XT_STK_OVLY,   ovly)
-#endif
-STRUCT_END(XtExcFrame)
-
-#if defined(_ASMLANGUAGE) || defined(__ASSEMBLER__)
-#define XT_STK_NEXT1      XtExcFrameSize
-#else
-#define XT_STK_NEXT1      sizeof(XtExcFrame)
-#endif
-
-/* Allocate extra storage if needed */
-#if XCHAL_EXTRA_SA_SIZE != 0
-
-#if XCHAL_EXTRA_SA_ALIGN <= 16
-#define XT_STK_EXTRA            ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1)
-#else
-/* If need more alignment than stack, add space for dynamic alignment */
-#define XT_STK_EXTRA            (ALIGNUP(XCHAL_EXTRA_SA_ALIGN, XT_STK_NEXT1) + XCHAL_EXTRA_SA_ALIGN)
-#endif
-#define XT_STK_NEXT2            (XT_STK_EXTRA + XCHAL_EXTRA_SA_SIZE)
-
-#else
-
-#define XT_STK_NEXT2            XT_STK_NEXT1   
-
-#endif
-
-/*
--------------------------------------------------------------------------------
-  This is the frame size. Add space for 4 registers (interruptee's base save
-  area) and some space for gcc nested functions if any.
--------------------------------------------------------------------------------
-*/
-#define XT_STK_FRMSZ            (ALIGNUP(0x10, XT_STK_NEXT2) + 0x20)
-
-
-/*
--------------------------------------------------------------------------------
-  SOLICITED STACK FRAME FOR A THREAD
-
-  A stack frame of this structure is allocated whenever a thread enters the 
-  RTOS kernel intentionally (and synchronously) to submit to thread scheduling.
-  It goes on the current thread's stack.
-
-  The solicited frame only includes registers that are required to be preserved
-  by the callee according to the compiler's ABI conventions, some space to save 
-  the return address for returning to the caller, and the caller's PS register.
-
-  For Windowed ABI, this stack frame includes the caller's base save area.
-
-  Note on XT_SOL_EXIT field:
-      It is necessary to distinguish a solicited from an interrupt stack frame.
-      This field corresponds to XT_STK_EXIT in the interrupt stack frame and is
-      always at the same offset (0). It can be written with a code (usually 0) 
-      to distinguish a solicted frame from an interrupt frame. An RTOS port may
-      opt to ignore this field if it has another way of distinguishing frames.
--------------------------------------------------------------------------------
-*/
-
-STRUCT_BEGIN
-#ifdef __XTENSA_CALL0_ABI__
-STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
-STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
-STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
-STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
-STRUCT_FIELD (long, 4, XT_SOL_A12,  a12)    /* should be on 16-byte alignment */
-STRUCT_FIELD (long, 4, XT_SOL_A13,  a13)
-STRUCT_FIELD (long, 4, XT_SOL_A14,  a14)
-STRUCT_FIELD (long, 4, XT_SOL_A15,  a15)
-#else
-STRUCT_FIELD (long, 4, XT_SOL_EXIT, exit)
-STRUCT_FIELD (long, 4, XT_SOL_PC,   pc)
-STRUCT_FIELD (long, 4, XT_SOL_PS,   ps)
-STRUCT_FIELD (long, 4, XT_SOL_NEXT, next)
-STRUCT_FIELD (long, 4, XT_SOL_A0,   a0)    /* should be on 16-byte alignment */
-STRUCT_FIELD (long, 4, XT_SOL_A1,   a1)
-STRUCT_FIELD (long, 4, XT_SOL_A2,   a2)
-STRUCT_FIELD (long, 4, XT_SOL_A3,   a3)
-#endif
-STRUCT_END(XtSolFrame)
-
-/* Size of solicited stack frame */
-#define XT_SOL_FRMSZ            ALIGNUP(0x10, XtSolFrameSize)
-
-
-/*
--------------------------------------------------------------------------------
-  CO-PROCESSOR STATE SAVE AREA FOR A THREAD
-
-  The RTOS must provide an area per thread to save the state of co-processors
-  when that thread does not have control. Co-processors are context-switched
-  lazily (on demand) only when a new thread uses a co-processor instruction,
-  otherwise a thread retains ownership of the co-processor even when it loses
-  control of the processor. An Xtensa co-processor exception is triggered when
-  any co-processor instruction is executed by a thread that is not the owner,
-  and the context switch of that co-processor is then peformed by the handler.
-  Ownership represents which thread's state is currently in the co-processor.
-
-  Co-processors may not be used by interrupt or exception handlers. If an 
-  co-processor instruction is executed by an interrupt or exception handler,
-  the co-processor exception handler will trigger a kernel panic and freeze.
-  This restriction is introduced to reduce the overhead of saving and restoring
-  co-processor state (which can be quite large) and in particular remove that
-  overhead from interrupt handlers.
-
-  The co-processor state save area may be in any convenient per-thread location
-  such as in the thread control block or above the thread stack area. It need
-  not be in the interrupt stack frame since interrupts don't use co-processors.
-
-  Along with the save area for each co-processor, two bitmasks with flags per 
-  co-processor (laid out as in the CPENABLE reg) help manage context-switching
-  co-processors as efficiently as possible:
-
-  XT_CPENABLE
-    The contents of a non-running thread's CPENABLE register.
-    It represents the co-processors owned (and whose state is still needed)
-    by the thread. When a thread is preempted, its CPENABLE is saved here.
-    When a thread solicits a context-swtich, its CPENABLE is cleared - the
-    compiler has saved the (caller-saved) co-proc state if it needs to.
-    When a non-running thread loses ownership of a CP, its bit is cleared.
-    When a thread runs, it's XT_CPENABLE is loaded into the CPENABLE reg.
-    Avoids co-processor exceptions when no change of ownership is needed.
-
-  XT_CPSTORED
-    A bitmask with the same layout as CPENABLE, a bit per co-processor.
-    Indicates whether the state of each co-processor is saved in the state 
-    save area. When a thread enters the kernel, only the state of co-procs
-    still enabled in CPENABLE is saved. When the co-processor exception 
-    handler assigns ownership of a co-processor to a thread, it restores 
-    the saved state only if this bit is set, and clears this bit.
-
-  XT_CP_CS_ST
-    A bitmask with the same layout as CPENABLE, a bit per co-processor.
-    Indicates whether callee-saved state is saved in the state save area.
-    Callee-saved state is saved by itself on a solicited context switch,
-    and restored when needed by the coprocessor exception handler.
-    Unsolicited switches will cause the entire coprocessor to be saved
-    when necessary.
-
-  XT_CP_ASA
-    Pointer to the aligned save area.  Allows it to be aligned more than
-    the overall save area (which might only be stack-aligned or TCB-aligned).
-    Especially relevant for Xtensa cores configured with a very large data
-    path that requires alignment greater than 16 bytes (ABI stack alignment).
--------------------------------------------------------------------------------
-*/
-
-#if XCHAL_CP_NUM > 0
-
-/*  Offsets of each coprocessor save area within the 'aligned save area':  */
-#define XT_CP0_SA   0
-#define XT_CP1_SA   ALIGNUP(XCHAL_CP1_SA_ALIGN, XT_CP0_SA + XCHAL_CP0_SA_SIZE)
-#define XT_CP2_SA   ALIGNUP(XCHAL_CP2_SA_ALIGN, XT_CP1_SA + XCHAL_CP1_SA_SIZE)
-#define XT_CP3_SA   ALIGNUP(XCHAL_CP3_SA_ALIGN, XT_CP2_SA + XCHAL_CP2_SA_SIZE)
-#define XT_CP4_SA   ALIGNUP(XCHAL_CP4_SA_ALIGN, XT_CP3_SA + XCHAL_CP3_SA_SIZE)
-#define XT_CP5_SA   ALIGNUP(XCHAL_CP5_SA_ALIGN, XT_CP4_SA + XCHAL_CP4_SA_SIZE)
-#define XT_CP6_SA   ALIGNUP(XCHAL_CP6_SA_ALIGN, XT_CP5_SA + XCHAL_CP5_SA_SIZE)
-#define XT_CP7_SA   ALIGNUP(XCHAL_CP7_SA_ALIGN, XT_CP6_SA + XCHAL_CP6_SA_SIZE)
-#define XT_CP_SA_SIZE   ALIGNUP(16, XT_CP7_SA + XCHAL_CP7_SA_SIZE)
-
-/*  Offsets within the overall save area:  */
-#define XT_CPENABLE 0   /* (2 bytes) coprocessors active for this thread */
-#define XT_CPSTORED 2   /* (2 bytes) coprocessors saved for this thread */
-#define XT_CP_CS_ST 4   /* (2 bytes) coprocessor callee-saved regs stored for this thread */
-#define XT_CP_ASA   8   /* (4 bytes) ptr to aligned save area */
-/*  Overall size allows for dynamic alignment:  */
-#define XT_CP_SIZE  (12 + XT_CP_SA_SIZE + XCHAL_TOTAL_SA_ALIGN)
-#else
-#define XT_CP_SIZE  0
-#endif
-
-
-/*
--------------------------------------------------------------------------------
-  MACROS TO HANDLE ABI SPECIFICS OF FUNCTION ENTRY AND RETURN
-
-  Convenient where the frame size requirements are the same for both ABIs.
-    ENTRY(sz), RET(sz) are for framed functions (have locals or make calls).
-    ENTRY0,    RET0    are for frameless functions (no locals, no calls).
-
-  where size = size of stack frame in bytes (must be >0 and aligned to 16).
-  For framed functions the frame is created and the return address saved at
-  base of frame (Call0 ABI) or as determined by hardware (Windowed ABI).
-  For frameless functions, there is no frame and return address remains in a0.
-  Note: Because CPP macros expand to a single line, macros requiring multi-line 
-  expansions are implemented as assembler macros.
--------------------------------------------------------------------------------
-*/
-
-#ifdef __ASSEMBLER__
-#ifdef __XTENSA_CALL0_ABI__
-  /* Call0 */
-  #define ENTRY(sz)     entry1  sz
-    .macro  entry1 size=0x10
-    addi    sp, sp, -\size
-    s32i    a0, sp, 0
-    .endm
-  #define ENTRY0      
-  #define RET(sz)       ret1    sz
-    .macro  ret1 size=0x10
-    l32i    a0, sp, 0
-    addi    sp, sp, \size
-    ret
-    .endm
-  #define RET0          ret
-#else
-  /* Windowed */
-  #define ENTRY(sz)     entry   sp, sz
-  #define ENTRY0        entry   sp, 0x10
-  #define RET(sz)       retw
-  #define RET0          retw
-#endif
-#endif
-
-
-#endif /* XTENSA_CONTEXT_H */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
deleted file mode 100755
index 2de1116..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_init.c
+++ /dev/null
@@ -1,66 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * XTENSA INITIALIZATION ROUTINES CODED IN C
- *
- * This file contains miscellaneous Xtensa RTOS-generic initialization functions
- * that are implemented in C.
- */
-
-
-#ifdef XT_BOARD
-#include    
-#endif
-
-#include    "xtensa_rtos.h"
-
-#ifdef XT_RTOS_TIMER_INT
-
-unsigned _xt_tick_divisor = 0;  /* cached number of cycles per tick */
-
-/*
-Compute and initialize at run-time the tick divisor (the number of 
-processor clock cycles in an RTOS tick, used to set the tick timer).
-Called when the processor clock frequency is not known at compile-time.
-*/
-void _xt_tick_divisor_init(void)
-{
-#ifdef XT_CLOCK_FREQ
-
-    _xt_tick_divisor = (XT_CLOCK_FREQ / XT_TICK_PER_SEC);
-
-#else
-
-    #ifdef XT_BOARD
-    _xt_tick_divisor = xtbsp_clock_freq_hz() / XT_TICK_PER_SEC;
-    #else
-    #error "No way to obtain processor clock frequency"
-    #endif  /* XT_BOARD */
-
-#endif /* XT_CLOCK_FREQ */
-}
-
-#endif /* XT_RTOS_TIMER_INT */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
deleted file mode 100755
index 524ebf6..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr.c
+++ /dev/null
@@ -1,133 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Xtensa-specific interrupt and exception functions for RTOS ports.
- * Also see xtensa_intr_asm.S.
- */
-
-#include 
-
-#include 
-
-#include "xtensa_api.h"
-
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-/* Handler table is in xtensa_intr_asm.S */
-
-extern xt_exc_handler _xt_exception_table[XCHAL_EXCCAUSE_NUM];
-
-
-/*
-  Default handler for unhandled exceptions.
-*/
-void xt_unhandled_exception(XtExcFrame *frame)
-{
-    exit(-1);
-}
-
-
-/*
-  This function registers a handler for the specified exception.
-  The function returns the address of the previous handler.
-  On error, it returns 0.
-*/
-xt_exc_handler xt_set_exception_handler(int n, xt_exc_handler f)
-{
-    xt_exc_handler old;
-
-    if( n < 0 || n >= XCHAL_EXCCAUSE_NUM )
-        return 0;       /* invalid exception number */
-
-    old = _xt_exception_table[n];
-
-    if (f) {
-        _xt_exception_table[n] = f;
-    }
-    else {
-        _xt_exception_table[n] = &xt_unhandled_exception;
-    }
-
-    return ((old == &xt_unhandled_exception) ? 0 : old);
-}
-
-#endif
-
-#if XCHAL_HAVE_INTERRUPTS
-
-/* Handler table is in xtensa_intr_asm.S */
-
-typedef struct xt_handler_table_entry {
-    void * handler;
-    void * arg;
-} xt_handler_table_entry;
-
-extern xt_handler_table_entry _xt_interrupt_table[XCHAL_NUM_INTERRUPTS];
-
-
-/*
-  Default handler for unhandled interrupts.
-*/
-void xt_unhandled_interrupt(void * arg)
-{
-    exit(-1);
-}
-
-
-/*
-  This function registers a handler for the specified interrupt. The "arg"
-  parameter specifies the argument to be passed to the handler when it is
-  invoked. The function returns the address of the previous handler.
-  On error, it returns 0.
-*/
-xt_handler xt_set_interrupt_handler(int n, xt_handler f, void * arg)
-{
-    xt_handler_table_entry * entry;
-    xt_handler               old;
-
-    if( n < 0 || n >= XCHAL_NUM_INTERRUPTS )
-        return 0;       /* invalid interrupt number */
-    if( Xthal_intlevel[n] > XCHAL_EXCM_LEVEL )
-        return 0;       /* priority level too high to safely handle in C */
-
-    entry = _xt_interrupt_table + n;
-    old   = entry->handler;
-
-    if (f) {
-        entry->handler = f;
-        entry->arg     = arg;
-    }
-    else {
-        entry->handler = &xt_unhandled_interrupt;
-        entry->arg     = (void*)n;
-    }
-
-    return ((old == &xt_unhandled_interrupt) ? 0 : old);
-}
-
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
deleted file mode 100755
index bf3017d..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_intr_asm.S
+++ /dev/null
@@ -1,180 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * Xtensa interrupt handling data and assembly routines.
- * Also see xtensa_intr.c and xtensa_vectors.S.
- */
-
-#include 
-#include 
-
-#include "xtensa_context.h"
-
-#if XCHAL_HAVE_INTERRUPTS
-
-/*
--------------------------------------------------------------------------------
-  INTENABLE virtualization information.
--------------------------------------------------------------------------------
-*/
-
-    .data
-    .global _xt_intdata
-    .align  8
-_xt_intdata:
-    .global _xt_intenable
-    .type   _xt_intenable,@object
-    .size   _xt_intenable,4
-    .global _xt_vpri_mask
-    .type   _xt_vpri_mask,@object
-    .size   _xt_vpri_mask,4
-
-_xt_intenable:     .word   0             /* Virtual INTENABLE     */
-_xt_vpri_mask:     .word   0xFFFFFFFF    /* Virtual priority mask */
-
-
-/*
--------------------------------------------------------------------------------
-  Table of C-callable interrupt handlers for each interrupt. Note that not all
-  slots can be filled, because interrupts at level > EXCM_LEVEL will not be
-  dispatched to a C handler by default.
--------------------------------------------------------------------------------
-*/
-
-    .data
-    .global _xt_interrupt_table
-    .align  8
-
-_xt_interrupt_table:
-
-    .set    i, 0
-    .rept   XCHAL_NUM_INTERRUPTS
-    .word   xt_unhandled_interrupt      /* handler address               */
-    .word   i                           /* handler arg (default: intnum) */
-    .set    i, i+1
-    .endr
-
-#endif /* XCHAL_HAVE_INTERRUPTS */
-
-
-#if XCHAL_HAVE_EXCEPTIONS
-
-/*
--------------------------------------------------------------------------------
-  Table of C-callable exception handlers for each exception. Note that not all
-  slots will be active, because some exceptions (e.g. coprocessor exceptions)
-  are always handled by the OS and cannot be hooked by user handlers.
--------------------------------------------------------------------------------
-*/
-
-    .data
-    .global _xt_exception_table
-    .align  4
-
-_xt_exception_table:
-    .rept   XCHAL_EXCCAUSE_NUM
-    .word   xt_unhandled_exception    /* handler address */
-    .endr
-
-#endif
-
-
-/*
--------------------------------------------------------------------------------
-  unsigned int xt_ints_on ( unsigned int mask )
-
-  Enables a set of interrupts. Does not simply set INTENABLE directly, but
-  computes it as a function of the current virtual priority.
-  Can be called from interrupt handlers.
--------------------------------------------------------------------------------
-*/
-
-    .text
-    .align  4
-    .global xt_ints_on
-    .type   xt_ints_on,@function
-
-xt_ints_on:
-
-    ENTRY0
-#if XCHAL_HAVE_INTERRUPTS
-    movi    a3, 0
-    movi    a4, _xt_intdata
-    xsr     a3, INTENABLE        /* Disables all interrupts   */
-    rsync
-    l32i    a3, a4, 0            /* a3 = _xt_intenable        */
-    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask        */
-    or      a5, a3, a2           /* a5 = _xt_intenable | mask */
-    s32i    a5, a4, 0            /* _xt_intenable |= mask     */
-    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
-    wsr     a5, INTENABLE        /* Reenable interrupts       */
-    mov     a2, a3               /* Previous mask             */
-#else
-    movi    a2, 0                /* Return zero */
-#endif
-    RET0
-
-    .size   xt_ints_on, . - xt_ints_on
-
-
-/*
--------------------------------------------------------------------------------
-  unsigned int xt_ints_off ( unsigned int mask )
-
-  Disables a set of interrupts. Does not simply set INTENABLE directly,
-  but computes it as a function of the current virtual priority.
-  Can be called from interrupt handlers.
--------------------------------------------------------------------------------
-*/
-
-    .text
-    .align  4
-    .global xt_ints_off
-    .type   xt_ints_off,@function
-
-xt_ints_off:
-
-    ENTRY0
-#if XCHAL_HAVE_INTERRUPTS
-    movi    a3, 0
-    movi    a4, _xt_intdata
-    xsr     a3, INTENABLE        /* Disables all interrupts    */
-    rsync
-    l32i    a3, a4, 0            /* a3 = _xt_intenable         */
-    l32i    a6, a4, 4            /* a6 = _xt_vpri_mask         */
-    or      a5, a3, a2           /* a5 = _xt_intenable | mask  */
-    xor     a5, a5, a2           /* a5 = _xt_intenable & ~mask */
-    s32i    a5, a4, 0            /* _xt_intenable &= ~mask     */
-    and     a5, a5, a6           /* a5 = _xt_intenable & _xt_vpri_mask */
-    wsr     a5, INTENABLE        /* Reenable interrupts        */
-    mov     a2, a3               /* Previous mask              */
-#else
-    movi    a2, 0                /* return zero */
-#endif
-    RET0
-
-    .size   xt_ints_off, . - xt_ints_off
-
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
deleted file mode 100755
index 004bfb5..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_overlay_os_hook.c
+++ /dev/null
@@ -1,71 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * xtensa_overlay_os_hook.c -- Overlay manager OS hooks for FreeRTOS.
- */
-
-#include "FreeRTOS.h"
-#include "semphr.h"
-
-#if configUSE_MUTEX
-
-/* Mutex object that controls access to the overlay. Currently only one
- * overlay region is supported so one mutex suffices.
- */
-static SemaphoreHandle_t xt_overlay_mutex;
-
-
-/* This function should be overridden to provide OS specific init such
- * as the creation of a mutex lock that can be used for overlay locking.
- * Typically this mutex would be set up with priority inheritance. See
- * overlay manager documentation for more details.
- */
-void xt_overlay_init_os(void)
-{
-    /* Create the mutex for overlay access. Priority inheritance is
-     * required.
-     */
-    xt_overlay_mutex = xSemaphoreCreateMutex();
-}
-
-
-/* This function locks access to shared overlay resources, typically
- * by acquiring a mutex.
- */
-void xt_overlay_lock(void)
-{
-    xSemaphoreTake(xt_overlay_mutex, 0);
-}
-
-
-/* This function releases access to shared overlay resources, typically
- * by unlocking a mutex.
- */
-void xt_overlay_unlock(void)
-{
-    xSemaphoreGive(xt_overlay_mutex);
-}
-
-#endif
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
deleted file mode 100755
index ecf6b61..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_rtos.h
+++ /dev/null
@@ -1,234 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * RTOS-SPECIFIC INFORMATION FOR XTENSA RTOS ASSEMBLER SOURCES
- *                       (FreeRTOS Port)
- *
- * This header is the primary glue between generic Xtensa RTOS support
- * sources and a specific RTOS port for Xtensa.  It contains definitions
- * and macros for use primarily by Xtensa assembly coded source files.
- *
- * Macros in this header map callouts from generic Xtensa files to specific
- * RTOS functions. It may also be included in C source files.
- *
- * Xtensa RTOS ports support all RTOS-compatible configurations of the Xtensa 
- * architecture, using the Xtensa hardware abstraction layer (HAL) to deal 
- * with configuration specifics.
- * 
- * Should be included by all Xtensa generic and RTOS port-specific sources.
- */
-
-#ifndef XTENSA_RTOS_H
-#define XTENSA_RTOS_H
-
-#ifdef __ASSEMBLER__
-#include    
-#else
-#include    
-#endif
-
-#include    
-#include    
-#include    
-
-/*
-Include any RTOS specific definitions that are needed by this header.
-*/
-#include    
-
-/*
-Convert FreeRTOSConfig definitions to XTENSA definitions.
-However these can still be overridden from the command line.
-*/
-
-#ifndef XT_SIMULATOR
-  #if configXT_SIMULATOR
-    #define XT_SIMULATOR             1  /* Simulator mode */
-  #endif
-#endif
-
-#ifndef XT_BOARD
-  #if configXT_BOARD
-    #define XT_BOARD                 1  /* Board mode */
-  #endif
-#endif
-
-#ifndef XT_TIMER_INDEX
-  #if defined configXT_TIMER_INDEX
-    #define XT_TIMER_INDEX           configXT_TIMER_INDEX  /* Index of hardware timer to be used */
-  #endif
-#endif
-
-#ifndef XT_INTEXC_HOOKS
-  #if configXT_INTEXC_HOOKS
-    #define XT_INTEXC_HOOKS          1  /* Enables exception hooks */
-  #endif
-#endif
-
-#if (!XT_SIMULATOR) && (!XT_BOARD)
-  #error Either XT_SIMULATOR or XT_BOARD must be defined.
-#endif
-
-
-/*
-Name of RTOS (for messages).
-*/
-#define XT_RTOS_NAME    FreeRTOS
-
-/*
-Check some Xtensa configuration requirements and report error if not met.
-Error messages can be customize to the RTOS port.
-*/
-
-#if !XCHAL_HAVE_XEA2
-#error "FreeRTOS/Xtensa requires XEA2 (exception architecture 2)."
-#endif
-
-
-/*******************************************************************************
-
-RTOS CALLOUT MACROS MAPPED TO RTOS PORT-SPECIFIC FUNCTIONS.
-
-Define callout macros used in generic Xtensa code to interact with the RTOS.
-The macros are simply the function names for use in calls from assembler code.
-Some of these functions may call back to generic functions in xtensa_context.h .
-
-*******************************************************************************/
-
-/*
-Inform RTOS of entry into an interrupt handler that will affect it. 
-Allows RTOS to manage switch to any system stack and count nesting level.
-Called after minimal context has been saved, with interrupts disabled.
-RTOS port can call0 _xt_context_save to save the rest of the context.
-May only be called from assembly code by the 'call0' instruction.
-*/
-// void XT_RTOS_INT_ENTER(void)
-#define XT_RTOS_INT_ENTER   _frxt_int_enter
-
-/*
-Inform RTOS of completion of an interrupt handler, and give control to
-RTOS to perform thread/task scheduling, switch back from any system stack
-and restore the context, and return to the exit dispatcher saved in the
-stack frame at XT_STK_EXIT. RTOS port can call0 _xt_context_restore
-to save the context saved in XT_RTOS_INT_ENTER via _xt_context_save,
-leaving only a minimal part of the context to be restored by the exit
-dispatcher. This function does not return to the place it was called from.
-May only be called from assembly code by the 'call0' instruction.
-*/
-// void XT_RTOS_INT_EXIT(void)
-#define XT_RTOS_INT_EXIT    _frxt_int_exit
-
-/*
-Inform RTOS of the occurrence of a tick timer interrupt.
-If RTOS has no tick timer, leave XT_RTOS_TIMER_INT undefined.
-May be coded in or called from C or assembly, per ABI conventions.
-RTOS may optionally define XT_TICK_PER_SEC in its own way (eg. macro).
-*/
-// void XT_RTOS_TIMER_INT(void)
-#define XT_RTOS_TIMER_INT   _frxt_timer_int
-#define XT_TICK_PER_SEC     configTICK_RATE_HZ
-
-/*
-Return in a15 the base address of the co-processor state save area for the 
-thread that triggered a co-processor exception, or 0 if no thread was running.
-The state save area is structured as defined in xtensa_context.h and has size 
-XT_CP_SIZE. Co-processor instructions should only be used in thread code, never
-in interrupt handlers or the RTOS kernel. May only be called from assembly code
-and by the 'call0' instruction. A result of 0 indicates an unrecoverable error. 
-The implementation may use only a2-4, a15 (all other regs must be preserved).
-*/
-// void* XT_RTOS_CP_STATE(void)
-#define XT_RTOS_CP_STATE    _frxt_task_coproc_state
-
-
-/*******************************************************************************
-
-HOOKS TO DYNAMICALLY INSTALL INTERRUPT AND EXCEPTION HANDLERS PER LEVEL.
-
-This Xtensa RTOS port provides hooks for dynamically installing exception
-and interrupt handlers to facilitate automated testing where each test
-case can install its own handler for user exceptions and each interrupt
-priority (level). This consists of an array of function pointers indexed
-by interrupt priority, with index 0 being the user exception handler hook.
-Each entry in the array is initially 0, and may be replaced by a function 
-pointer of type XT_INTEXC_HOOK. A handler may be uninstalled by installing 0.
-
-The handler for low and medium priority obeys ABI conventions so may be coded
-in C. For the exception handler, the cause is the contents of the EXCCAUSE
-reg, and the result is -1 if handled, else the cause (still needs handling).
-For interrupt handlers, the cause is a mask of pending enabled interrupts at
-that level, and the result is the same mask with the bits for the handled
-interrupts cleared (those not cleared still need handling). This allows a test
-case to either pre-handle or override the default handling for the exception
-or interrupt level (see xtensa_vectors.S).
-
-High priority handlers (including NMI) must be coded in assembly, are always
-called by 'call0' regardless of ABI, must preserve all registers except a0,
-and must not use or modify the interrupted stack. The hook argument 'cause'
-is not passed and the result is ignored, so as not to burden the caller with
-saving and restoring a2 (it assumes only one interrupt per level - see the
-discussion in high priority interrupts in xtensa_vectors.S). The handler
-therefore should be coded to prototype 'void h(void)' even though it plugs
-into an array of handlers of prototype 'unsigned h(unsigned)'.
-
-To enable interrupt/exception hooks, compile the RTOS with '-DXT_INTEXC_HOOKS'.
-
-*******************************************************************************/
-
-#define XT_INTEXC_HOOK_NUM  (1 + XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI)
-
-#ifndef __ASSEMBLER__
-typedef unsigned (*XT_INTEXC_HOOK)(unsigned cause);
-extern  volatile XT_INTEXC_HOOK _xt_intexc_hooks[XT_INTEXC_HOOK_NUM];
-#endif
-
-
-/*******************************************************************************
-
-CONVENIENCE INCLUSIONS.
-
-Ensures RTOS specific files need only include this one Xtensa-generic header.
-These headers are included last so they can use the RTOS definitions above.
-
-*******************************************************************************/
-
-#include    "xtensa_context.h"
-
-#ifdef XT_RTOS_TIMER_INT
-#include    "xtensa_timer.h"
-#endif
-
-
-/*******************************************************************************
-
-Xtensa Port Version.
-
-*******************************************************************************/
-
-#define XTENSA_PORT_VERSION             1.7
-#define XTENSA_PORT_VERSION_STRING      "1.7"
-
-#endif /* XTENSA_RTOS_H */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
deleted file mode 100755
index 0fb2eff..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_timer.h
+++ /dev/null
@@ -1,160 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
- * XTENSA INFORMATION FOR RTOS TICK TIMER AND CLOCK FREQUENCY
- *
- * This header contains definitions and macros for use primarily by Xtensa
- * RTOS assembly coded source files. It includes and uses the Xtensa hardware
- * abstraction layer (HAL) to deal with config specifics. It may also be
- * included in C source files.
- *
- * Edit this file to modify timer selection and to specify clock frequency and
- * tick duration to match timer interrupt to the real-time tick duration.
- *
- * If the RTOS has no timer interrupt, then there is no tick timer and the
- * clock frequency is irrelevant, so all of these macros are left undefined
- * and the Xtensa core configuration need not have a timer.
- */
-
-#ifndef XTENSA_TIMER_H
-#define XTENSA_TIMER_H
-
-#ifdef __ASSEMBLER__
-#include    
-#endif
-
-#include    
-#include    
-
-#include    "xtensa_rtos.h"     /* in case this wasn't included directly */
-
-#include    
-
-/*
-Select timer to use for periodic tick, and determine its interrupt number 
-and priority. User may specify a timer by defining XT_TIMER_INDEX with -D,
-in which case its validity is checked (it must exist in this core and must 
-not be on a high priority interrupt - an error will be reported in invalid).
-Otherwise select the first low or medium priority interrupt timer available.
-*/
-#if XCHAL_NUM_TIMERS == 0
-
-  #error "This Xtensa configuration is unsupported, it has no timers."
-
-#else
-
-#ifndef XT_TIMER_INDEX
-  #if XCHAL_TIMER3_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER3_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    3
-    #endif
-  #endif
-  #if XCHAL_TIMER2_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER2_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    2
-    #endif
-  #endif
-  #if XCHAL_TIMER1_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER1_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    1
-    #endif
-  #endif
-  #if XCHAL_TIMER0_INTERRUPT != XTHAL_TIMER_UNCONFIGURED
-    #if XCHAL_INT_LEVEL(XCHAL_TIMER0_INTERRUPT) <= XCHAL_EXCM_LEVEL
-      #undef  XT_TIMER_INDEX
-      #define XT_TIMER_INDEX    0
-    #endif
-  #endif
-#endif
-#ifndef XT_TIMER_INDEX
-  #error "There is no suitable timer in this Xtensa configuration."
-#endif
-
-#define XT_CCOMPARE             (CCOMPARE + XT_TIMER_INDEX)
-#define XT_TIMER_INTNUM         XCHAL_TIMER_INTERRUPT(XT_TIMER_INDEX)
-#define XT_TIMER_INTPRI         XCHAL_INT_LEVEL(XT_TIMER_INTNUM)
-#define XT_TIMER_INTEN          (1 << XT_TIMER_INTNUM)
-
-#if XT_TIMER_INTNUM == XTHAL_TIMER_UNCONFIGURED
-  #error "The timer selected by XT_TIMER_INDEX does not exist in this core."
-#elif XT_TIMER_INTPRI > XCHAL_EXCM_LEVEL
-  #error "The timer interrupt cannot be high priority (use medium or low)."
-#endif
-
-#endif /* XCHAL_NUM_TIMERS */
-
-/*
-Set processor clock frequency, used to determine clock divisor for timer tick.
-User should BE SURE TO ADJUST THIS for the Xtensa platform being used.
-If using a supported board via the board-independent API defined in xtbsp.h,
-this may be left undefined and frequency and tick divisor will be computed 
-and cached during run-time initialization.
-
-NOTE ON SIMULATOR:
-Under the Xtensa instruction set simulator, the frequency can only be estimated 
-because it depends on the speed of the host and the version of the simulator.
-Also because it runs much slower than hardware, it is not possible to achieve
-real-time performance for most applications under the simulator. A frequency
-too low does not allow enough time between timer interrupts, starving threads.
-To obtain a more convenient but non-real-time tick duration on the simulator, 
-compile with xt-xcc option "-DXT_SIMULATOR".
-Adjust this frequency to taste (it's not real-time anyway!).
-*/
-#if defined(XT_SIMULATOR) && !defined(XT_CLOCK_FREQ)
-#define XT_CLOCK_FREQ       configCPU_CLOCK_HZ
-#endif
-
-#if !defined(XT_CLOCK_FREQ) && !defined(XT_BOARD)
-  #error "XT_CLOCK_FREQ must be defined for the target platform."
-#endif
-
-/*
-Default number of timer "ticks" per second (default 100 for 10ms tick).
-RTOS may define this in its own way (if applicable) in xtensa_rtos.h.
-User may redefine this to an optimal value for the application, either by
-editing this here or in xtensa_rtos.h, or compiling with xt-xcc option
-"-DXT_TICK_PER_SEC=" where  is a suitable number.
-*/
-#ifndef XT_TICK_PER_SEC
-#define XT_TICK_PER_SEC    configTICK_RATE_HZ        /* 10 ms tick = 100 ticks per second */
-#endif
-
-/*
-Derivation of clock divisor for timer tick and interrupt (one per tick).
-*/
-#ifdef XT_CLOCK_FREQ
-#define XT_TICK_DIVISOR     (XT_CLOCK_FREQ / XT_TICK_PER_SEC)
-#endif
-
-#ifndef __ASSEMBLER__
-extern unsigned _xt_tick_divisor;
-extern void     _xt_tick_divisor_init(void);
-#endif
-
-#endif  /* XTENSA_TIMER_H */
-
diff --git a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S b/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S
deleted file mode 100755
index 953205c..0000000
--- a/FreeRTOS/Source/portable/ThirdParty/XCC/Xtensa/xtensa_vectors.S
+++ /dev/null
@@ -1,1905 +0,0 @@
-
-/*
- * Copyright (c) 2015-2019 Cadence Design Systems, Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/*
-        XTENSA VECTORS AND LOW LEVEL HANDLERS FOR AN RTOS
-
-  Xtensa low level exception and interrupt vectors and handlers for an RTOS.
-
-  Interrupt handlers and user exception handlers support interaction with
-  the RTOS by calling XT_RTOS_INT_ENTER and XT_RTOS_INT_EXIT before and
-  after user's specific interrupt handlers. These macros are defined in
-  xtensa_.h to call suitable functions in a specific RTOS.
-
-  Users can install application-specific interrupt handlers for low and
-  medium level interrupts, by calling xt_set_interrupt_handler(). These
-  handlers can be written in C, and must obey C calling convention. The
-  handler table is indexed by the interrupt number. Each handler may be
-  provided with an argument. 
-
-  Note that the system timer interrupt is handled specially, and is
-  dispatched to the RTOS-specific handler. This timer cannot be hooked
-  by application code.
-
-  Optional hooks are also provided to install a handler per level at 
-  run-time, made available by compiling this source file with 
-  '-DXT_INTEXC_HOOKS' (useful for automated testing).
-
-!!  This file is a template that usually needs to be modified to handle       !!
-!!  application specific interrupts. Search USER_EDIT for helpful comments    !!
-!!  on where to insert handlers and how to write them.                        !!
-
-  Users can also install application-specific exception handlers in the
-  same way, by calling xt_set_exception_handler(). One handler slot is
-  provided for each exception type. Note that some exceptions are handled
-  by the porting layer itself, and cannot be taken over by application
-  code in this manner. These are the alloca, syscall, and coprocessor
-  exceptions.
-
-  The exception handlers can be written in C, and must follow C calling
-  convention. Each handler is passed a pointer to an exception frame as
-  its single argument. The exception frame is created on the stack, and
-  holds the saved context of the thread that took the exception. If the
-  handler returns, the context will be restored and the instruction that
-  caused the exception will be retried. If the handler makes any changes
-  to the saved state in the exception frame, the changes will be applied
-  when restoring the context.
-
-  Because Xtensa is a configurable architecture, this port supports all user
-  generated configurations (except restrictions stated in the release notes).
-  This is accomplished by conditional compilation using macros and functions
-  defined in the Xtensa HAL (hardware adaptation layer) for your configuration.
-  Only the relevant parts of this file will be included in your RTOS build.
-  For example, this file provides interrupt vector templates for all types and
-  all priority levels, but only the ones in your configuration are built.
-
-  NOTES on the use of 'call0' for long jumps instead of 'j':
-   1. This file should be assembled with the -mlongcalls option to xt-xcc.
-   2. The -mlongcalls compiler option causes 'call0 dest' to be expanded to
-      a sequence 'l32r a0, dest' 'callx0 a0' which works regardless of the
-      distance from the call to the destination. The linker then relaxes
-      it back to 'call0 dest' if it determines that dest is within range.
-      This allows more flexibility in locating code without the performance
-      overhead of the 'l32r' literal data load in cases where the destination
-      is in range of 'call0'. There is an additional benefit in that 'call0'
-      has a longer range than 'j' due to the target being word-aligned, so 
-      the 'l32r' sequence is less likely needed.
-   3. The use of 'call0' with -mlongcalls requires that register a0 not be 
-      live at the time of the call, which is always the case for a function 
-      call but needs to be ensured if 'call0' is used as a jump in lieu of 'j'.
-   4. This use of 'call0' is independent of the C function call ABI.
-
- */
-
-#include "xtensa_rtos.h"
-
-
-/* Enable stack backtrace across exception/interrupt - see below */
-#define XT_DEBUG_BACKTRACE    1
-
-
-/*
---------------------------------------------------------------------------------
-  Defines used to access _xtos_interrupt_table.
---------------------------------------------------------------------------------
-*/
-#define XIE_HANDLER     0
-#define XIE_ARG         4
-#define XIE_SIZE        8
-
-/*
---------------------------------------------------------------------------------
-  Macro extract_msb - return the input with only the highest bit set.
-
-  Input  : "ain"  - Input value, clobbered.
-  Output : "aout" - Output value, has only one bit set, MSB of "ain".
-  The two arguments must be different AR registers.
---------------------------------------------------------------------------------
-*/
-
-    .macro  extract_msb     aout ain
-1:
-    addi    \aout, \ain, -1         /* aout = ain - 1        */
-    and     \ain, \ain, \aout       /* ain  = ain & aout     */
-    bnez    \ain, 1b                /* repeat until ain == 0 */
-    addi    \aout, \aout, 1         /* return aout + 1       */
-    .endm
-
-/*
---------------------------------------------------------------------------------
-  Macro dispatch_c_isr - dispatch interrupts to user ISRs.
-  This will dispatch to user handlers (if any) that are registered in the
-  XTOS dispatch table (_xtos_interrupt_table). These handlers would have
-  been registered by calling _xtos_set_interrupt_handler(). There is one
-  exception - the timer interrupt used by the OS will not be dispatched
-  to a user handler - this must be handled by the caller of this macro.
-
-  Level triggered and software interrupts are automatically deasserted by
-  this code.
-
-  ASSUMPTIONS:
-    -- PS.INTLEVEL is set to "level" at entry
-    -- PS.EXCM = 0, C calling enabled
-
-  NOTE: For CALL0 ABI, a12-a15 have not yet been saved.
-
-  NOTE: This macro will use registers a0 and a2-a6. The arguments are:
-    level -- interrupt level
-    mask  -- interrupt bitmask for this level
---------------------------------------------------------------------------------
-*/
-
-    .macro  dispatch_c_isr    level  mask
-
-    /* Get mask of pending, enabled interrupts at this level into a2. */
-
-.L_xt_user_int_&level&:
-    rsr     a2, INTENABLE
-    rsr     a3, INTERRUPT
-    movi    a4, \mask
-    and     a2, a2, a3
-    and     a2, a2, a4
-    beqz    a2, 9f                          /* nothing to do */
-
-    /* This bit of code provides a nice debug backtrace in the debugger.
-       It does take a few more instructions, so undef XT_DEBUG_BACKTRACE
-       if you want to save the cycles.
-    */
-    #if XT_DEBUG_BACKTRACE
-    #ifndef __XTENSA_CALL0_ABI__
-    rsr     a0, EPC_1 + \level - 1          /* return address */
-    movi    a4, 0xC0000000                  /* constant with top 2 bits set (call size) */
-    or      a0, a0, a4                      /* set top 2 bits */
-    addx2   a0, a4, a0                      /* clear top bit -- simulating call4 size   */
-    #endif
-    #endif
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a4, _xt_intexc_hooks
-    l32i    a4, a4, \level << 2
-    beqz    a4, 2f
-    #ifdef __XTENSA_CALL0_ABI__
-    callx0  a4
-    beqz    a2, 9f
-    #else
-    mov     a6, a2
-    callx4  a4
-    beqz    a6, 9f
-    mov     a2, a6
-    #endif
-2:
-    #endif
-
-    /* Now look up in the dispatch table and call user ISR if any. */
-    /* If multiple bits are set then MSB has highest priority.     */
-
-    extract_msb  a4, a2                     /* a4 = MSB of a2, a2 trashed */
-
-    #ifdef XT_USE_SWPRI
-    /* Enable all interrupts at this level that are numerically higher
-       than the one we just selected, since they are treated as higher
-       priority.
-    */
-    movi    a3, \mask                       /* a3 = all interrupts at this level */
-    add     a2, a4, a4                      /* a2 = a4 << 1 */
-    addi    a2, a2, -1                      /* a2 = mask of 1's <= a4 bit */
-    and     a2, a2, a3                      /* a2 = mask of all bits <= a4 at this level */
-    movi    a3, _xt_intdata
-    l32i    a6, a3, 4                       /* a6 = _xt_vpri_mask */
-    neg     a2, a2
-    addi    a2, a2, -1                      /* a2 = mask to apply */
-    and     a5, a6, a2                      /* mask off all bits <= a4 bit */
-    s32i    a5, a3, 4                       /* update _xt_vpri_mask */
-    rsr     a3, INTENABLE
-    and     a3, a3, a2                      /* mask off all bits <= a4 bit */
-    wsr     a3, INTENABLE
-    rsil    a3, \level - 1                  /* lower interrupt level by 1 */
-    #endif
-
-    movi    a3, XT_TIMER_INTEN              /* a3 = timer interrupt bit */
-    wsr     a4, INTCLEAR                    /* clear sw or edge-triggered interrupt */
-    beq     a3, a4, 7f                      /* if timer interrupt then skip table */
-
-    find_ms_setbit a3, a4, a3, 0            /* a3 = interrupt number */
-
-    movi    a4, _xt_interrupt_table
-    addx8   a3, a3, a4                      /* a3 = address of interrupt table entry */
-    l32i    a4, a3, XIE_HANDLER             /* a4 = handler address */
-    #ifdef __XTENSA_CALL0_ABI__
-    mov     a12, a6                         /* save in callee-saved reg */
-    l32i    a2, a3, XIE_ARG                 /* a2 = handler arg */
-    callx0  a4                              /* call handler */
-    mov     a2, a12
-    #else
-    mov     a2, a6                          /* save in windowed reg */
-    l32i    a6, a3, XIE_ARG                 /* a6 = handler arg */
-    callx4  a4                              /* call handler */
-    #endif
-
-    #ifdef XT_USE_SWPRI
-    j       8f
-    #else
-    j       .L_xt_user_int_&level&          /* check for more interrupts */
-    #endif
-
-7:
-
-    .ifeq XT_TIMER_INTPRI - \level
-.L_xt_user_int_timer_&level&:
-    /*
-    Interrupt handler for the RTOS tick timer if at this level.
-    We'll be reading the interrupt state again after this call
-    so no need to preserve any registers except a6 (vpri_mask).
-    */
-
-    #ifdef __XTENSA_CALL0_ABI__
-    mov     a12, a6
-    call0   XT_RTOS_TIMER_INT
-    mov     a2, a12
-    #else
-    mov     a2, a6
-    call4   XT_RTOS_TIMER_INT
-    #endif
-    .endif
-
-    #ifdef XT_USE_SWPRI
-    j       8f
-    #else
-    j       .L_xt_user_int_&level&          /* check for more interrupts */
-    #endif
-
-    #ifdef XT_USE_SWPRI
-8:
-    /* Restore old value of _xt_vpri_mask from a2. Also update INTENABLE from
-       virtual _xt_intenable which _could_ have changed during interrupt
-       processing. */
-
-    movi    a3, _xt_intdata
-    l32i    a4, a3, 0                       /* a4 = _xt_intenable    */
-    s32i    a2, a3, 4                       /* update _xt_vpri_mask  */
-    and     a4, a4, a2                      /* a4 = masked intenable */
-    wsr     a4, INTENABLE                   /* update INTENABLE      */
-    #endif
-
-9:
-    /* done */
-
-    .endm
-
-
-/*
---------------------------------------------------------------------------------
-  Panic handler.
-  Should be reached by call0 (preferable) or jump only. If call0, a0 says where 
-  from. If on simulator, display panic message and abort, else loop indefinitely.
---------------------------------------------------------------------------------
-*/
-
-    .text
-    .global     _xt_panic
-    .type       _xt_panic,@function
-    .align      4
-
-_xt_panic:
-    #ifdef XT_SIMULATOR
-    addi    a4, a0, -3                      /* point to call0 */
-    movi    a3, _xt_panic_message
-    movi    a2, SYS_log_msg
-    simcall
-    movi    a2, SYS_gdb_abort
-    simcall
-    #else
-    rsil    a2, XCHAL_EXCM_LEVEL            /* disable all low & med ints */
-1:  j       1b                              /* loop infinitely */
-    #endif
-
-    .section    .rodata, "a"
-    .align      4
-
-_xt_panic_message:
-    .string "\n*** _xt_panic() was called from 0x%08x or jumped to. ***\n"
-
-
-/*
---------------------------------------------------------------------------------
-    Hooks to dynamically install handlers for exceptions and interrupts.
-    Allows automated regression frameworks to install handlers per test.
-    Consists of an array of function pointers indexed by interrupt level, 
-    with index 0 containing the entry for user exceptions.
-    Initialized with all 0s, meaning no handler is installed at each level.
-    See comment in xtensa_rtos.h for more details.
---------------------------------------------------------------------------------
-*/
-
-    #ifdef XT_INTEXC_HOOKS
-    .data
-    .global     _xt_intexc_hooks
-    .type       _xt_intexc_hooks,@object
-    .align      4
-
-_xt_intexc_hooks:
-    .fill       XT_INTEXC_HOOK_NUM, 4, 0
-    #endif
-
-
-/*
---------------------------------------------------------------------------------
-  EXCEPTION AND LEVEL 1 INTERRUPT VECTORS AND LOW LEVEL HANDLERS
-  (except window exception vectors).
-
-  Each vector goes at a predetermined location according to the Xtensa
-  hardware configuration, which is ensured by its placement in a special
-  section known to the Xtensa linker support package (LSP). It performs
-  the minimum necessary before jumping to the handler in the .text section.
-
-  The corresponding handler goes in the normal .text section. It sets up
-  the appropriate stack frame, saves a few vector-specific registers and
-  calls XT_RTOS_INT_ENTER to save the rest of the interrupted context
-  and enter the RTOS, then sets up a C environment. It then calls the
-  user's interrupt handler code (which may be coded in C) and finally 
-  calls XT_RTOS_INT_EXIT to transfer control to the RTOS for scheduling.
-
-  While XT_RTOS_INT_EXIT does not return directly to the interruptee,
-  eventually the RTOS scheduler will want to dispatch the interrupted
-  task or handler. The scheduler will return to the exit point that was
-  saved in the interrupt stack frame at XT_STK_EXIT.
---------------------------------------------------------------------------------
-*/
-
-
-/*
---------------------------------------------------------------------------------
-Debug Exception.
---------------------------------------------------------------------------------
-*/
-
-#if XCHAL_HAVE_DEBUG
-
-    .begin      literal_prefix .DebugExceptionVector
-    .section    .DebugExceptionVector.text, "ax"
-    .global     _DebugExceptionVector
-    .align      4
-
-_DebugExceptionVector:
-
-    #ifdef XT_SIMULATOR
-    /*
-    In the simulator, let the debugger (if any) handle the debug exception,
-    or simply stop the simulation:
-    */
-    wsr     a2, EXCSAVE+XCHAL_DEBUGLEVEL    /* save a2 where sim expects it */
-    movi    a2, SYS_gdb_enter_sktloop
-    simcall                                 /* have ISS handle debug exc. */
-    #elif 0 /* change condition to 1 to use the HAL minimal debug handler */
-    wsr     a3, EXCSAVE+XCHAL_DEBUGLEVEL
-    movi    a3, xthal_debugexc_defhndlr_nw  /* use default debug handler */
-    jx      a3
-    #else
-    wsr     a0, EXCSAVE+XCHAL_DEBUGLEVEL    /* save original a0 somewhere */
-    call0   _xt_panic                       /* does not return */
-    rfi     XCHAL_DEBUGLEVEL                /* make a0 point here not later */
-    #endif
-
-    .end        literal_prefix
-
-#endif
-
-/*
---------------------------------------------------------------------------------
-Double Exception.
-Double exceptions are not a normal occurrence. They indicate a bug of some kind.
---------------------------------------------------------------------------------
-*/
-
-#ifdef XCHAL_DOUBLEEXC_VECTOR_VADDR
-
-    .begin      literal_prefix .DoubleExceptionVector
-    .section    .DoubleExceptionVector.text, "ax"
-    .global     _DoubleExceptionVector
-    .align      4
-
-_DoubleExceptionVector:
-
-    #if XCHAL_HAVE_DEBUG
-    break   1, 4                            /* unhandled double exception */
-    #endif
-    call0   _xt_panic                       /* does not return */
-    rfde                                    /* make a0 point here not later */
-
-    .end        literal_prefix
-
-#endif /* XCHAL_DOUBLEEXC_VECTOR_VADDR */
-
-/*
---------------------------------------------------------------------------------
-Kernel Exception (including Level 1 Interrupt from kernel mode).
---------------------------------------------------------------------------------
-*/
-
-    .begin      literal_prefix .KernelExceptionVector
-    .section    .KernelExceptionVector.text, "ax"
-    .global     _KernelExceptionVector
-    .align      4
-
-_KernelExceptionVector:
-
-    wsr     a0, EXCSAVE_1                   /* preserve a0 */
-    call0   _xt_kernel_exc                  /* kernel exception handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .align      4
-
-_xt_kernel_exc:
-    #if XCHAL_HAVE_DEBUG
-    break   1, 0                            /* unhandled kernel exception */
-    #endif
-    call0   _xt_panic                       /* does not return */
-    rfe                                     /* make a0 point here not there */
-
-
-/*
---------------------------------------------------------------------------------
-User Exception (including Level 1 Interrupt from user mode).
---------------------------------------------------------------------------------
-*/
-
-    .begin      literal_prefix .UserExceptionVector
-    .section    .UserExceptionVector.text, "ax"
-    .global     _UserExceptionVector
-    .type       _UserExceptionVector,@function
-    .align      4
-
-_UserExceptionVector:
-
-    wsr     a0, EXCSAVE_1                   /* preserve a0 */
-    call0   _xt_user_exc                    /* user exception handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-/*
---------------------------------------------------------------------------------
-  Insert some waypoints for jumping beyond the signed 8-bit range of
-  conditional branch instructions, so the conditional branchces to specific
-  exception handlers are not taken in the mainline. Saves some cycles in the
-  mainline.
---------------------------------------------------------------------------------
-*/
-
-    .text
-
-    #if XCHAL_HAVE_WINDOWED
-    .align      4
-_xt_to_alloca_exc:
-    call0   _xt_alloca_exc                  /* in window vectors section */
-    /* never returns here - call0 is used as a jump (see note at top) */
-    #endif
-
-    .align      4
-_xt_to_syscall_exc:
-    call0   _xt_syscall_exc
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    #if XCHAL_CP_NUM > 0
-    .align      4
-_xt_to_coproc_exc:
-    call0   _xt_coproc_exc
-    /* never returns here - call0 is used as a jump (see note at top) */
-    #endif
-
-
-/*
---------------------------------------------------------------------------------
-  User exception handler.
---------------------------------------------------------------------------------
-*/
-
-    .type       _xt_user_exc,@function
-    .align      4
-
-_xt_user_exc:
-
-    /* If level 1 interrupt then jump to the dispatcher */
-    rsr     a0, EXCCAUSE
-    beqi    a0, EXCCAUSE_LEVEL1INTERRUPT, _xt_lowint1
-
-    /* Handle any coprocessor exceptions. Rely on the fact that exception
-       numbers above EXCCAUSE_CP0_DISABLED all relate to the coprocessors.
-    */
-    #if XCHAL_CP_NUM > 0
-    bgeui   a0, EXCCAUSE_CP0_DISABLED, _xt_to_coproc_exc
-    #endif
-
-    /* Handle alloca and syscall exceptions */
-    #if XCHAL_HAVE_WINDOWED
-    beqi    a0, EXCCAUSE_ALLOCA,  _xt_to_alloca_exc
-    #endif
-    beqi    a0, EXCCAUSE_SYSCALL, _xt_to_syscall_exc
-
-    /* Handle all other exceptions. All can have user-defined handlers. */
-    /* NOTE: we'll stay on the user stack for exception handling.       */
-
-    /* Allocate exception frame and save minimal context. */
-    mov     a0, sp
-    addi    sp, sp, -XT_STK_FRMSZ
-    s32i    a0, sp, XT_STK_A1
-    #if XCHAL_HAVE_WINDOWED
-    s32e    a0, sp, -12                     /* for debug backtrace */
-    #endif
-    rsr     a0, PS                          /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_1                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_1                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    #if XCHAL_HAVE_WINDOWED
-    s32e    a0, sp, -16                     /* for debug backtrace */
-    #endif
-    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
-    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
-    call0   _xt_context_save
-
-    /* Save exc cause and vaddr into exception frame */
-    rsr     a0, EXCCAUSE
-    s32i    a0, sp, XT_STK_EXCCAUSE
-    rsr     a0, EXCVADDR
-    s32i    a0, sp, XT_STK_EXCVADDR
-
-    /* Set up PS for C, reenable hi-pri interrupts, and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(XCHAL_EXCM_LEVEL) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-
-    #ifdef XT_DEBUG_BACKTRACE
-    #ifndef __XTENSA_CALL0_ABI__
-    rsr     a0, EPC_1                       /* return address for debug backtrace */
-    movi    a5, 0xC0000000                  /* constant with top 2 bits set (call size) */
-    rsync                                   /* wait for WSR.PS to complete */
-    or      a0, a0, a5                      /* set top 2 bits */
-    addx2   a0, a5, a0                      /* clear top bit -- thus simulating call4 size */
-    #else
-    rsync                                   /* wait for WSR.PS to complete */
-    #endif
-    #endif
-
-    rsr     a2, EXCCAUSE                    /* recover exc cause */
-
-    #ifdef XT_INTEXC_HOOKS
-    /*
-    Call exception hook to pre-handle exceptions (if installed).
-    Pass EXCCAUSE in a2, and check result in a2 (if -1, skip default handling).
-    */
-    movi    a4, _xt_intexc_hooks
-    l32i    a4, a4, 0                       /* user exception hook index 0 */
-    beqz    a4, 1f
-.Ln_xt_user_exc_call_hook:
-    #ifdef __XTENSA_CALL0_ABI__
-    callx0  a4
-    beqi    a2, -1, .L_xt_user_done
-    #else
-    mov     a6, a2
-    callx4  a4
-    beqi    a6, -1, .L_xt_user_done
-    mov     a2, a6
-    #endif
-1:
-    #endif
-
-    rsr     a2, EXCCAUSE                    /* recover exc cause */
-    movi    a3, _xt_exception_table
-    addx4   a4, a2, a3                      /* a4 = address of exception table entry */
-    l32i    a4, a4, 0                       /* a4 = handler address */
-    #ifdef __XTENSA_CALL0_ABI__
-    mov     a2, sp                          /* a2 = pointer to exc frame */
-    callx0  a4                              /* call handler */
-    #else
-    mov     a6, sp                          /* a6 = pointer to exc frame */
-    callx4  a4                              /* call handler */
-    #endif
-
-.L_xt_user_done:
-
-    /* Restore context and return */
-    call0   _xt_context_restore
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, PS
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_1
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove exception frame */
-    rsync                                   /* ensure PS and EPC written */
-    rfe                                     /* PS.EXCM is cleared */
-
-
-/*
---------------------------------------------------------------------------------
-  Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-  on entry and used to return to a thread or interrupted interrupt handler.
---------------------------------------------------------------------------------
-*/
-
-    .global     _xt_user_exit
-    .type       _xt_user_exit,@function
-    .align      4
-_xt_user_exit:
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, PS
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_1
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure PS and EPC written */
-    rfe                                     /* PS.EXCM is cleared */
-
-
-/*
---------------------------------------------------------------------------------
-Syscall Exception Handler (jumped to from User Exception Handler).
-Syscall 0 is required to spill the register windows (no-op in Call 0 ABI).
-Only syscall 0 is handled here. Other syscalls return -1 to caller in a2.
---------------------------------------------------------------------------------
-*/
-
-    .text
-    .type       _xt_syscall_exc,@function
-    .align      4
-_xt_syscall_exc:
-
-    #ifdef __XTENSA_CALL0_ABI__
-    /*
-    Save minimal regs for scratch. Syscall 0 does nothing in Call0 ABI.
-    Use a minimal stack frame (16B) to save A2 & A3 for scratch.
-    PS.EXCM could be cleared here, but unlikely to improve worst-case latency.
-    rsr     a0, PS
-    addi    a0, a0, -PS_EXCM_MASK
-    wsr     a0, PS
-    */
-    addi    sp, sp, -16
-    s32i    a2, sp, 8
-    s32i    a3, sp, 12
-    #else   /* Windowed ABI */
-    /*
-    Save necessary context and spill the register windows.
-    PS.EXCM is still set and must remain set until after the spill.
-    Reuse context save function though it saves more than necessary.
-    For this reason, a full interrupt stack frame is allocated.
-    */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a12, sp, XT_STK_A12             /* _xt_context_save requires A12- */
-    s32i    a13, sp, XT_STK_A13             /* A13 to have already been saved */
-    call0   _xt_context_save
-    #endif
-
-    /*
-    Grab the interruptee's PC and skip over the 'syscall' instruction.
-    If it's at the end of a zero-overhead loop and it's not on the last
-    iteration, decrement loop counter and skip to beginning of loop.
-    */
-    rsr     a2, EPC_1                       /* a2 = PC of 'syscall' */
-    addi    a3, a2, 3                       /* ++PC                 */
-    #if XCHAL_HAVE_LOOPS
-    rsr     a0, LEND                        /* if (PC == LEND       */
-    bne     a3, a0, 1f
-    rsr     a0, LCOUNT                      /*     && LCOUNT != 0)  */
-    beqz    a0, 1f                          /* {                    */
-    addi    a0, a0, -1                      /*   --LCOUNT           */
-    rsr     a3, LBEG                        /*   PC = LBEG          */
-    wsr     a0, LCOUNT                      /* }                    */
-    #endif
-1:  wsr     a3, EPC_1                       /* update PC            */
-
-    /* Restore interruptee's context and return from exception. */
-    #ifdef __XTENSA_CALL0_ABI__
-    l32i    a2, sp, 8
-    l32i    a3, sp, 12
-    addi    sp, sp, 16
-    #else
-    call0   _xt_context_restore
-    addi    sp, sp, XT_STK_FRMSZ
-    #endif
-    movi    a0, -1
-    movnez  a2, a0, a2                      /* return -1 if not syscall 0 */
-    rsr     a0, EXCSAVE_1
-    rfe
-
-/*
---------------------------------------------------------------------------------
-Co-Processor Exception Handler (jumped to from User Exception Handler).
-These exceptions are generated by co-processor instructions, which are only
-allowed in thread code (not in interrupts or kernel code). This restriction is 
-deliberately imposed to reduce the burden of state-save/restore in interrupts.
---------------------------------------------------------------------------------
-*/
-#if XCHAL_CP_NUM > 0
-
-    .section .rodata, "a"
-
-/* Offset to CP n save area in thread's CP save area. */
-    .global _xt_coproc_sa_offset
-    .type   _xt_coproc_sa_offset,@object
-    .align  16                      /* minimize crossing cache boundaries */
-_xt_coproc_sa_offset:
-    .word   XT_CP0_SA, XT_CP1_SA, XT_CP2_SA, XT_CP3_SA
-    .word   XT_CP4_SA, XT_CP5_SA, XT_CP6_SA, XT_CP7_SA
-
-/* Bitmask for CP n's CPENABLE bit. */
-    .type   _xt_coproc_mask,@object
-    .align  16,,8                   /* try to keep it all in one cache line */
-    .set    i, 0
-_xt_coproc_mask:
-    .rept   XCHAL_CP_MAX
-    .long   (i<<16) | (1<= 2
-
-    .begin      literal_prefix .Level2InterruptVector
-    .section    .Level2InterruptVector.text, "ax"
-    .global     _Level2Vector
-    .type       _Level2Vector,@function
-    .align      4
-_Level2Vector:
-    wsr     a0, EXCSAVE_2                   /* preserve a0 */
-    call0   _xt_medint2                     /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_medint2,@function
-    .align      4
-_xt_medint2:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_2                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_2                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_2                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint2_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(2) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(2) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 2 XCHAL_INTLEVEL2_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint2_exit
-    .type       _xt_medint2_exit,@function
-    .align      4
-_xt_medint2_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_2
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_2
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     2
-
-#endif  /* Level 2 */
-
-#if XCHAL_EXCM_LEVEL >= 3
-
-    .begin      literal_prefix .Level3InterruptVector
-    .section    .Level3InterruptVector.text, "ax"
-    .global     _Level3Vector
-    .type       _Level3Vector,@function
-    .align      4
-_Level3Vector:
-    wsr     a0, EXCSAVE_3                   /* preserve a0 */
-    call0   _xt_medint3                     /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_medint3,@function
-    .align      4
-_xt_medint3:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_3                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_3                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_3                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint3_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(3) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(3) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 3 XCHAL_INTLEVEL3_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint3_exit
-    .type       _xt_medint3_exit,@function
-    .align      4
-_xt_medint3_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_3
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_3
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     3
-
-#endif  /* Level 3 */
-
-#if XCHAL_EXCM_LEVEL >= 4
-
-    .begin      literal_prefix .Level4InterruptVector
-    .section    .Level4InterruptVector.text, "ax"
-    .global     _Level4Vector
-    .type       _Level4Vector,@function
-    .align      4
-_Level4Vector:
-    wsr     a0, EXCSAVE_4                   /* preserve a0 */
-    call0   _xt_medint4                     /* load interrupt handler */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_medint4,@function
-    .align      4
-_xt_medint4:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_4                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_4                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_4                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint4_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(4) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(4) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 4 XCHAL_INTLEVEL4_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint4_exit
-    .type       _xt_medint4_exit,@function
-    .align      4
-_xt_medint4_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_4
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_4
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     4
-
-#endif  /* Level 4 */
-
-#if XCHAL_EXCM_LEVEL >= 5
-
-    .begin      literal_prefix .Level5InterruptVector
-    .section    .Level5InterruptVector.text, "ax"
-    .global     _Level5Vector
-    .type       _Level5Vector,@function
-    .align      4
-_Level5Vector:
-    wsr     a0, EXCSAVE_5                   /* preserve a0 */
-    call0   _xt_medint5                     /* load interrupt handler */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_medint5,@function
-    .align      4
-_xt_medint5:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_5                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_5                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_5                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint5_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(5) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(5) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 5 XCHAL_INTLEVEL5_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint5_exit
-    .type       _xt_medint5_exit,@function
-    .align      4
-_xt_medint5_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_5
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_5
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     5
-
-#endif  /* Level 5 */
-
-#if XCHAL_EXCM_LEVEL >= 6
-
-    .begin      literal_prefix .Level6InterruptVector
-    .section    .Level6InterruptVector.text, "ax"
-    .global     _Level6Vector
-    .type       _Level6Vector,@function
-    .align      4
-_Level6Vector:
-    wsr     a0, EXCSAVE_6                   /* preserve a0 */
-    call0   _xt_medint6                     /* load interrupt handler */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_medint6,@function
-    .align      4
-_xt_medint6:
-    mov     a0, sp                          /* sp == a1 */
-    addi    sp, sp, -XT_STK_FRMSZ           /* allocate interrupt stack frame */
-    s32i    a0, sp, XT_STK_A1               /* save pre-interrupt SP */
-    rsr     a0, EPS_6                       /* save interruptee's PS */
-    s32i    a0, sp, XT_STK_PS
-    rsr     a0, EPC_6                       /* save interruptee's PC */
-    s32i    a0, sp, XT_STK_PC
-    rsr     a0, EXCSAVE_6                   /* save interruptee's a0 */
-    s32i    a0, sp, XT_STK_A0
-    movi    a0, _xt_medint6_exit            /* save exit point for dispatch */
-    s32i    a0, sp, XT_STK_EXIT
-
-    /* Save rest of interrupt context and enter RTOS. */
-    call0   XT_RTOS_INT_ENTER               /* common RTOS interrupt entry */
-
-    /* !! We are now on the RTOS system stack !! */
-
-    /* Set up PS for C, enable interrupts above this level and clear EXCM. */
-    #ifdef __XTENSA_CALL0_ABI__
-    movi    a0, PS_INTLEVEL(6) | PS_UM
-    #else
-    movi    a0, PS_INTLEVEL(6) | PS_UM | PS_WOE
-    #endif
-    wsr     a0, PS
-    rsync
-
-    /* OK to call C code at this point, dispatch user ISRs */
-
-    dispatch_c_isr 6 XCHAL_INTLEVEL6_MASK
-
-    /* Done handling interrupts, transfer control to OS */
-    call0   XT_RTOS_INT_EXIT                /* does not return directly here */
-
-    /*
-    Exit point for dispatch. Saved in interrupt stack frame at XT_STK_EXIT
-    on entry and used to return to a thread or interrupted interrupt handler.
-    */
-    .global     _xt_medint6_exit
-    .type       _xt_medint6_exit,@function
-    .align      4
-_xt_medint6_exit:
-    /* Restore only level-specific regs (the rest were already restored) */
-    l32i    a0, sp, XT_STK_PS               /* retrieve interruptee's PS */
-    wsr     a0, EPS_6
-    l32i    a0, sp, XT_STK_PC               /* retrieve interruptee's PC */
-    wsr     a0, EPC_6
-    l32i    a0, sp, XT_STK_A0               /* retrieve interruptee's A0 */
-    l32i    sp, sp, XT_STK_A1               /* remove interrupt stack frame */
-    rsync                                   /* ensure EPS and EPC written */
-    rfi     6
-
-#endif  /* Level 6 */
-
-
-/*******************************************************************************
-
-HIGH PRIORITY (LEVEL > XCHAL_EXCM_LEVEL) INTERRUPT VECTORS AND HANDLERS
-
-High priority interrupts are by definition those with priorities greater
-than XCHAL_EXCM_LEVEL. This includes non-maskable (NMI). High priority
-interrupts cannot interact with the RTOS, that is they must save all regs
-they use and not call any RTOS function.
-
-A further restriction imposed by the Xtensa windowed architecture is that
-high priority interrupts must not modify the stack area even logically
-"above" the top of the interrupted stack (they need to provide their
-own stack or static save area).
-
-Cadence Design Systems recommends high priority interrupt handlers be coded in assembly
-and used for purposes requiring very short service times.
-
-Here are templates for high priority (level 2+) interrupt vectors.
-They assume only one interrupt per level to avoid the burden of identifying
-which interrupts at this level are pending and enabled. This allows for 
-minimum latency and avoids having to save/restore a2 in addition to a0.
-If more than one interrupt per high priority level is configured, this burden
-is on the handler which in any case must provide a way to save and restore
-registers it uses without touching the interrupted stack.
-
-Each vector goes at a predetermined location according to the Xtensa
-hardware configuration, which is ensured by its placement in a special
-section known to the Xtensa linker support package (LSP). It performs
-the minimum necessary before jumping to the handler in the .text section.
-
-*******************************************************************************/
-
-/*
-Currently only shells for high priority interrupt handlers are provided
-here. However a template and example can be found in the Cadence Design Systems tools
-documentation: "Microprocessor Programmer's Guide".
-*/
-
-#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
-
-    .begin      literal_prefix .Level2InterruptVector
-    .section    .Level2InterruptVector.text, "ax"
-    .global     _Level2Vector
-    .type       _Level2Vector,@function
-    .align      4
-_Level2Vector:
-    wsr     a0, EXCSAVE_2                   /* preserve a0 */
-    call0   _xt_highint2                    /* load interrupt handler */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_highint2,@function
-    .align      4
-_xt_highint2:
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a0, _xt_intexc_hooks
-    l32i    a0, a0, 2<<2
-    beqz    a0, 1f
-.Ln_xt_highint2_call_hook:
-    callx0  a0                              /* must NOT disturb stack! */
-1:
-    #endif
-
-    /* USER_EDIT:
-    ADD HIGH PRIORITY LEVEL 2 INTERRUPT HANDLER CODE HERE.
-    */
-
-    .align  4
-.L_xt_highint2_exit:
-    rsr     a0, EXCSAVE_2                   /* restore a0 */
-    rfi     2
-
-#endif  /* Level 2 */
-
-#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
-
-    .begin      literal_prefix .Level3InterruptVector
-    .section    .Level3InterruptVector.text, "ax"
-    .global     _Level3Vector
-    .type       _Level3Vector,@function
-    .align      4
-_Level3Vector:
-    wsr     a0, EXCSAVE_3                   /* preserve a0 */
-    call0   _xt_highint3                    /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_highint3,@function
-    .align      4
-_xt_highint3:
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a0, _xt_intexc_hooks
-    l32i    a0, a0, 3<<2
-    beqz    a0, 1f
-.Ln_xt_highint3_call_hook:
-    callx0  a0                              /* must NOT disturb stack! */
-1:
-    #endif
-
-    /* USER_EDIT:
-    ADD HIGH PRIORITY LEVEL 3 INTERRUPT HANDLER CODE HERE.
-    */
-
-    .align  4
-.L_xt_highint3_exit:
-    rsr     a0, EXCSAVE_3                   /* restore a0 */
-    rfi     3
-
-#endif  /* Level 3 */
-
-#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
-
-    .begin      literal_prefix .Level4InterruptVector
-    .section    .Level4InterruptVector.text, "ax"
-    .global     _Level4Vector
-    .type       _Level4Vector,@function
-    .align      4
-_Level4Vector:
-    wsr     a0, EXCSAVE_4                   /* preserve a0 */
-    call0   _xt_highint4                    /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_highint4,@function
-    .align      4
-_xt_highint4:
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a0, _xt_intexc_hooks
-    l32i    a0, a0, 4<<2
-    beqz    a0, 1f
-.Ln_xt_highint4_call_hook:
-    callx0  a0                              /* must NOT disturb stack! */
-1:
-    #endif
-
-    /* USER_EDIT:
-    ADD HIGH PRIORITY LEVEL 4 INTERRUPT HANDLER CODE HERE.
-    */
-
-    .align  4
-.L_xt_highint4_exit:
-    rsr     a0, EXCSAVE_4                   /* restore a0 */
-    rfi     4
-
-#endif  /* Level 4 */
-
-#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
-
-    .begin      literal_prefix .Level5InterruptVector
-    .section    .Level5InterruptVector.text, "ax"
-    .global     _Level5Vector
-    .type       _Level5Vector,@function
-    .align      4
-_Level5Vector:
-    wsr     a0, EXCSAVE_5                   /* preserve a0 */
-    call0   _xt_highint5                    /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_highint5,@function
-    .align      4
-_xt_highint5:
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a0, _xt_intexc_hooks
-    l32i    a0, a0, 5<<2
-    beqz    a0, 1f
-.Ln_xt_highint5_call_hook:
-    callx0  a0                              /* must NOT disturb stack! */
-1:
-    #endif
-
-    /* USER_EDIT:
-    ADD HIGH PRIORITY LEVEL 5 INTERRUPT HANDLER CODE HERE.
-    */
-
-    .align  4
-.L_xt_highint5_exit:
-    rsr     a0, EXCSAVE_5                   /* restore a0 */
-    rfi     5
-
-#endif  /* Level 5 */
-
-#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
-
-    .begin      literal_prefix .Level6InterruptVector
-    .section    .Level6InterruptVector.text, "ax"
-    .global     _Level6Vector
-    .type       _Level6Vector,@function
-    .align      4
-_Level6Vector:
-    wsr     a0, EXCSAVE_6                   /* preserve a0 */
-    call0   _xt_highint6                    /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_highint6,@function
-    .align      4
-_xt_highint6:
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a0, _xt_intexc_hooks
-    l32i    a0, a0, 6<<2
-    beqz    a0, 1f
-.Ln_xt_highint6_call_hook:
-    callx0  a0                              /* must NOT disturb stack! */
-1:
-    #endif
-
-    /* USER_EDIT:
-    ADD HIGH PRIORITY LEVEL 6 INTERRUPT HANDLER CODE HERE.
-    */
-
-    .align  4
-.L_xt_highint6_exit:
-    rsr     a0, EXCSAVE_6                   /* restore a0 */
-    rfi     6
-
-#endif  /* Level 6 */
-
-#if XCHAL_HAVE_NMI
-
-    .begin      literal_prefix .NMIExceptionVector
-    .section    .NMIExceptionVector.text, "ax"
-    .global     _NMIExceptionVector
-    .type       _NMIExceptionVector,@function
-    .align      4
-_NMIExceptionVector:
-    wsr     a0, EXCSAVE + XCHAL_NMILEVEL  _ /* preserve a0 */
-    call0   _xt_nmi                         /* load interrupt handler */
-    /* never returns here - call0 is used as a jump (see note at top) */
-
-    .end        literal_prefix
-
-    .text
-    .type       _xt_nmi,@function
-    .align      4
-_xt_nmi:
-
-    #ifdef XT_INTEXC_HOOKS
-    /* Call interrupt hook if present to (pre)handle interrupts. */
-    movi    a0, _xt_intexc_hooks
-    l32i    a0, a0, XCHAL_NMILEVEL<<2
-    beqz    a0, 1f
-.Ln_xt_nmi_call_hook:
-    callx0  a0                              /* must NOT disturb stack! */
-1:
-    #endif
-
-    /* USER_EDIT:
-    ADD HIGH PRIORITY NON-MASKABLE INTERRUPT (NMI) HANDLER CODE HERE.
-    */
-
-    .align  4
-.L_xt_nmi_exit:
-    rsr     a0, EXCSAVE + XCHAL_NMILEVEL    /* restore a0 */
-    rfi     XCHAL_NMILEVEL
-
-#endif  /* NMI */
-
-
-/*******************************************************************************
-
-WINDOW OVERFLOW AND UNDERFLOW EXCEPTION VECTORS AND ALLOCA EXCEPTION HANDLER
-
-Here is the code for each window overflow/underflow exception vector and 
-(interspersed) efficient code for handling the alloca exception cause.
-Window exceptions are handled entirely in the vector area and are very
-tight for performance. The alloca exception is also handled entirely in 
-the window vector area so comes at essentially no cost in code size.
-Users should never need to modify them and Cadence Design Systems recommends 
-they do not.
-
-Window handlers go at predetermined vector locations according to the
-Xtensa hardware configuration, which is ensured by their placement in a
-special section known to the Xtensa linker support package (LSP). Since
-their offsets in that section are always the same, the LSPs do not define
-a section per vector.
-
-These things are coded for XEA2 only (XEA1 is not supported).
-
-Note on Underflow Handlers:
-The underflow handler for returning from call[i+1] to call[i]
-must preserve all the registers from call[i+1]'s window.
-In particular, a0 and a1 must be preserved because the RETW instruction
-will be reexecuted (and may even underflow if an intervening exception
-has flushed call[i]'s registers).
-Registers a2 and up may contain return values.
-
-*******************************************************************************/
-
-#if XCHAL_HAVE_WINDOWED
-
-    .section .WindowVectors.text, "ax"
-
-/*
---------------------------------------------------------------------------------
-Window Overflow Exception for Call4.
-
-Invoked if a call[i] referenced a register (a4-a15)
-that contains data from ancestor call[j];
-call[j] had done a call4 to call[j+1].
-On entry here:
-    window rotated to call[j] start point;
-        a0-a3 are registers to be saved;
-        a4-a15 must be preserved;
-        a5 is call[j+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0x0
-    .global _WindowOverflow4
-_WindowOverflow4:
-
-    s32e    a0, a5, -16     /* save a0 to call[j+1]'s stack frame */
-    s32e    a1, a5, -12     /* save a1 to call[j+1]'s stack frame */
-    s32e    a2, a5,  -8     /* save a2 to call[j+1]'s stack frame */
-    s32e    a3, a5,  -4     /* save a3 to call[j+1]'s stack frame */
-    rfwo                    /* rotates back to call[i] position */
-
-/*
---------------------------------------------------------------------------------
-Window Underflow Exception for Call4
-
-Invoked by RETW returning from call[i+1] to call[i]
-where call[i]'s registers must be reloaded (not live in ARs);
-where call[i] had done a call4 to call[i+1].
-On entry here:
-        window rotated to call[i] start point;
-        a0-a3 are undefined, must be reloaded with call[i].reg[0..3];
-        a4-a15 must be preserved (they are call[i+1].reg[0..11]);
-        a5 is call[i+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0x40
-    .global _WindowUnderflow4
-_WindowUnderflow4:
-
-    l32e    a0, a5, -16     /* restore a0 from call[i+1]'s stack frame */
-    l32e    a1, a5, -12     /* restore a1 from call[i+1]'s stack frame */
-    l32e    a2, a5,  -8     /* restore a2 from call[i+1]'s stack frame */
-    l32e    a3, a5,  -4     /* restore a3 from call[i+1]'s stack frame */
-    rfwu
-
-/*
---------------------------------------------------------------------------------
-Handle alloca exception generated by interruptee executing 'movsp'.
-This uses space between the window vectors, so is essentially "free".
-All interruptee's regs are intact except a0 which is saved in EXCSAVE_1,
-and PS.EXCM has been set by the exception hardware (can't be interrupted).
-The fact the alloca exception was taken means the registers associated with
-the base-save area have been spilled and will be restored by the underflow
-handler, so those 4 registers are available for scratch.
-The code is optimized to avoid unaligned branches and minimize cache misses.
---------------------------------------------------------------------------------
-*/
-
-    .align  4
-    .global _xt_alloca_exc
-_xt_alloca_exc:
-
-    rsr     a0, WINDOWBASE  /* grab WINDOWBASE before rotw changes it */
-    rotw    -1              /* WINDOWBASE goes to a4, new a0-a3 are scratch */
-    rsr     a2, PS
-    extui   a3, a2, XCHAL_PS_OWB_SHIFT, XCHAL_PS_OWB_BITS
-    xor     a3, a3, a4      /* bits changed from old to current windowbase */
-    rsr     a4, EXCSAVE_1   /* restore original a0 (now in a4) */
-    slli    a3, a3, XCHAL_PS_OWB_SHIFT
-    xor     a2, a2, a3      /* flip changed bits in old window base */
-    wsr     a2, PS          /* update PS.OWB to new window base */
-    rsync
-
-    _bbci.l a4, 31, _WindowUnderflow4
-    rotw    -1              /* original a0 goes to a8 */
-    _bbci.l a8, 30, _WindowUnderflow8
-    rotw    -1
-    j               _WindowUnderflow12
-
-/*
---------------------------------------------------------------------------------
-Window Overflow Exception for Call8
-
-Invoked if a call[i] referenced a register (a4-a15)
-that contains data from ancestor call[j];
-call[j] had done a call8 to call[j+1].
-On entry here:
-    window rotated to call[j] start point;
-        a0-a7 are registers to be saved;
-        a8-a15 must be preserved;
-        a9 is call[j+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0x80
-    .global _WindowOverflow8
-_WindowOverflow8:
-
-    s32e    a0, a9, -16     /* save a0 to call[j+1]'s stack frame */
-    l32e    a0, a1, -12     /* a0 <- call[j-1]'s sp
-                               (used to find end of call[j]'s frame) */
-    s32e    a1, a9, -12     /* save a1 to call[j+1]'s stack frame */
-    s32e    a2, a9,  -8     /* save a2 to call[j+1]'s stack frame */
-    s32e    a3, a9,  -4     /* save a3 to call[j+1]'s stack frame */
-    s32e    a4, a0, -32     /* save a4 to call[j]'s stack frame */
-    s32e    a5, a0, -28     /* save a5 to call[j]'s stack frame */
-    s32e    a6, a0, -24     /* save a6 to call[j]'s stack frame */
-    s32e    a7, a0, -20     /* save a7 to call[j]'s stack frame */
-    rfwo                    /* rotates back to call[i] position */
-
-/*
---------------------------------------------------------------------------------
-Window Underflow Exception for Call8
-
-Invoked by RETW returning from call[i+1] to call[i]
-where call[i]'s registers must be reloaded (not live in ARs);
-where call[i] had done a call8 to call[i+1].
-On entry here:
-        window rotated to call[i] start point;
-        a0-a7 are undefined, must be reloaded with call[i].reg[0..7];
-        a8-a15 must be preserved (they are call[i+1].reg[0..7]);
-        a9 is call[i+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0xC0
-    .global _WindowUnderflow8
-_WindowUnderflow8:
-
-    l32e    a0, a9, -16     /* restore a0 from call[i+1]'s stack frame */
-    l32e    a1, a9, -12     /* restore a1 from call[i+1]'s stack frame */
-    l32e    a2, a9,  -8     /* restore a2 from call[i+1]'s stack frame */
-    l32e    a7, a1, -12     /* a7 <- call[i-1]'s sp
-                               (used to find end of call[i]'s frame) */
-    l32e    a3, a9,  -4     /* restore a3 from call[i+1]'s stack frame */
-    l32e    a4, a7, -32     /* restore a4 from call[i]'s stack frame */
-    l32e    a5, a7, -28     /* restore a5 from call[i]'s stack frame */
-    l32e    a6, a7, -24     /* restore a6 from call[i]'s stack frame */
-    l32e    a7, a7, -20     /* restore a7 from call[i]'s stack frame */
-    rfwu
-
-/*
---------------------------------------------------------------------------------
-Window Overflow Exception for Call12
-
-Invoked if a call[i] referenced a register (a4-a15)
-that contains data from ancestor call[j];
-call[j] had done a call12 to call[j+1].
-On entry here:
-    window rotated to call[j] start point;
-        a0-a11 are registers to be saved;
-        a12-a15 must be preserved;
-        a13 is call[j+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org    0x100
-    .global _WindowOverflow12
-_WindowOverflow12:
-
-    s32e    a0,  a13, -16   /* save a0 to call[j+1]'s stack frame */
-    l32e    a0,  a1,  -12   /* a0 <- call[j-1]'s sp
-                               (used to find end of call[j]'s frame) */
-    s32e    a1,  a13, -12   /* save a1 to call[j+1]'s stack frame */
-    s32e    a2,  a13,  -8   /* save a2 to call[j+1]'s stack frame */
-    s32e    a3,  a13,  -4   /* save a3 to call[j+1]'s stack frame */
-    s32e    a4,  a0,  -48   /* save a4 to end of call[j]'s stack frame */
-    s32e    a5,  a0,  -44   /* save a5 to end of call[j]'s stack frame */
-    s32e    a6,  a0,  -40   /* save a6 to end of call[j]'s stack frame */
-    s32e    a7,  a0,  -36   /* save a7 to end of call[j]'s stack frame */
-    s32e    a8,  a0,  -32   /* save a8 to end of call[j]'s stack frame */
-    s32e    a9,  a0,  -28   /* save a9 to end of call[j]'s stack frame */
-    s32e    a10, a0,  -24   /* save a10 to end of call[j]'s stack frame */
-    s32e    a11, a0,  -20   /* save a11 to end of call[j]'s stack frame */
-    rfwo                    /* rotates back to call[i] position */
-
-/*
---------------------------------------------------------------------------------
-Window Underflow Exception for Call12
-
-Invoked by RETW returning from call[i+1] to call[i]
-where call[i]'s registers must be reloaded (not live in ARs);
-where call[i] had done a call12 to call[i+1].
-On entry here:
-        window rotated to call[i] start point;
-        a0-a11 are undefined, must be reloaded with call[i].reg[0..11];
-        a12-a15 must be preserved (they are call[i+1].reg[0..3]);
-        a13 is call[i+1]'s stack pointer.
---------------------------------------------------------------------------------
-*/
-
-    .org 0x140
-    .global _WindowUnderflow12
-_WindowUnderflow12:
-
-    l32e    a0,  a13, -16   /* restore a0 from call[i+1]'s stack frame */
-    l32e    a1,  a13, -12   /* restore a1 from call[i+1]'s stack frame */
-    l32e    a2,  a13,  -8   /* restore a2 from call[i+1]'s stack frame */
-    l32e    a11, a1,  -12   /* a11 <- call[i-1]'s sp
-                               (used to find end of call[i]'s frame) */
-    l32e    a3,  a13,  -4   /* restore a3 from call[i+1]'s stack frame */
-    l32e    a4,  a11, -48   /* restore a4 from end of call[i]'s stack frame */
-    l32e    a5,  a11, -44   /* restore a5 from end of call[i]'s stack frame */
-    l32e    a6,  a11, -40   /* restore a6 from end of call[i]'s stack frame */
-    l32e    a7,  a11, -36   /* restore a7 from end of call[i]'s stack frame */
-    l32e    a8,  a11, -32   /* restore a8 from end of call[i]'s stack frame */
-    l32e    a9,  a11, -28   /* restore a9 from end of call[i]'s stack frame */
-    l32e    a10, a11, -24   /* restore a10 from end of call[i]'s stack frame */
-    l32e    a11, a11, -20   /* restore a11 from end of call[i]'s stack frame */
-    rfwu
-
-#endif /* XCHAL_HAVE_WINDOWED */
-
diff --git a/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c b/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c
deleted file mode 100755
index 532b8f0..0000000
--- a/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/Tick.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* 
-Changes from V3.0.0
-	+ ISRcode is pulled inline and portTICKisr() is therefore
-	  deleted from this file.
-
-	+ Prescaler logic for Timer1 added to allow for a wider
-	  range of TickRates.
-
-Changes from V3.0.1
-*/
-
-#include 
-#include 
-
-/* IO port constants. */
-#define portBIT_SET		(1)
-#define portBIT_CLEAR	(0)
-
-/* 
- * Hardware setup for the tick.
- * We use a compare match on timer1. Depending on MPU-frequency
- * and requested tickrate, a prescaled value with a matching
- * prescaler are determined.
- */
-#define	portTIMER_COMPARE_BASE			((APROCFREQ/4)/configTICK_RATE_HZ)
-
-#if portTIMER_COMPARE_BASE   < 0x10000
-	#define	portTIMER_COMPARE_VALUE		(portTIMER_COMPARE_BASE)
-	#define portTIMER_COMPARE_PS1		(portBIT_CLEAR)
-	#define portTIMER_COMPARE_PS0		(portBIT_CLEAR)
-#elif portTIMER_COMPARE_BASE < 0x20000
-	#define	portTIMER_COMPARE_VALUE		(portTIMER_COMPARE_BASE / 2)
-	#define portTIMER_COMPARE_PS1		(portBIT_CLEAR)
-	#define portTIMER_COMPARE_PS0		(portBIT_SET)
-#elif portTIMER_COMPARE_BASE < 0x40000
-	#define	portTIMER_COMPARE_VALUE		(portTIMER_COMPARE_BASE / 4)
-	#define portTIMER_COMPARE_PS1		(portBIT_SET)
-	#define portTIMER_COMPARE_PS0		(portBIT_CLEAR)
-#elif portTIMER_COMPARE_BASE < 0x80000
-	#define	portTIMER_COMPARE_VALUE		(portTIMER_COMPARE_BASE / 8)
-	#define portTIMER_COMPARE_PS1		(portBIT_SET)
-	#define portTIMER_COMPARE_PS0		(portBIT_SET)
-#else
-	#error "TickRate out of range"
-#endif
-
-/*-----------------------------------------------------------*/
-
-/*
- * Setup a timer for a regular tick.
- */
-void portSetupTick( void )
-{
-	/*
-	 * Interrupts are disabled when this function is called.
-	 */
-
-	/*
-	 * Setup CCP1
-	 * Provide the tick interrupt using a compare match on timer1.
-	 */
-
-	/*
-	 * Set the compare match value.
-	 */
-	CCPR1H = ( uint8_t ) ( ( portTIMER_COMPARE_VALUE >> 8 ) & 0xff );
-	CCPR1L = ( uint8_t )   ( portTIMER_COMPARE_VALUE & 0xff );
-
-	/*
-	 * Set Compare Special Event Trigger Mode
-	 */
-	bCCP1M3 	= portBIT_SET;
-	bCCP1M2 	= portBIT_CLEAR;
-	bCCP1M1 	= portBIT_SET;
-	bCCP1M0		= portBIT_SET;
-
-	/*
-	 * Enable CCP1 interrupt
-	 */
-	bCCP1IE 	= portBIT_SET;
-
-	/*
-	 * We are only going to use the global interrupt bit, so disable
-	 * interruptpriorities and enable peripheral interrupts.
-	 */
-	bIPEN		= portBIT_CLEAR;
-	bPEIE		= portBIT_SET;
-
-	/*
-	 * Set up timer1
-	 * It will produce the system tick.
-	 */
-
-	/*
-	 * Clear the time count
-	 */
-	TMR1H = ( uint8_t ) 0x00;
-	TMR1L = ( uint8_t ) 0x00;
-
-	/*
-	 * Setup the timer
-	 */
-	bRD16		= portBIT_SET;				// 16-bit
-	bT1CKPS1	= portTIMER_COMPARE_PS1;	// prescaler
-	bT1CKPS0	= portTIMER_COMPARE_PS0;	// prescaler
-	bT1OSCEN	= portBIT_SET;				// Oscillator enable
-	bT1SYNC		= portBIT_SET;				// No external clock sync
-	bTMR1CS		= portBIT_CLEAR;			// Internal clock
-	
-	bTMR1ON		= portBIT_SET;				// Start timer1
-}
diff --git a/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c b/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c
deleted file mode 100755
index 7ce2f61..0000000
--- a/FreeRTOS/Source/portable/WizC/PIC18/Drivers/Tick/isrTick.c
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* 
-Changes from V3.0.0
-	+ ISRcode pulled inline to reduce stack-usage.
-
-	+ Added functionality to only call vTaskSwitchContext() once
-	  when handling multiple interruptsources in a single interruptcall.
-
-	+ Filename changed to a .c extension to allow stepping through code
-	  using F7.
-
-Changes from V3.0.1
-*/
-
-/*
- * ISR for the tick.
- * This increments the tick count and, if using the preemptive scheduler, 
- * performs a context switch.  This must be identical to the manual 
- * context switch in how it stores the context of a task. 
- */
-
-#ifndef _FREERTOS_DRIVERS_TICK_ISRTICK_C
-#define _FREERTOS_DRIVERS_TICK_ISRTICK_C
-
-{
-	/*
-	 * Was the interrupt the SystemClock?
-	 */
-	if( bCCP1IF && bCCP1IE )
-	{
-		/*
-		 * Reset the interrupt flag
-		 */
-		bCCP1IF = 0;
-	
-		/*
-	 	 * Maintain the tick count.
-	 	 */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/*
-		 	 * Ask for a switch to the highest priority task
-		 	 * that is ready to run.
-		 	 */
-			uxSwitchRequested = pdTRUE;
-		}
-	}
-}
-
-#pragma wizcpp uselib     "$__PATHNAME__/Tick.c"
-
-#endif	/* _FREERTOS_DRIVERS_TICK_ISRTICK_C */
diff --git a/FreeRTOS/Source/portable/WizC/PIC18/Install.bat b/FreeRTOS/Source/portable/WizC/PIC18/Install.bat
deleted file mode 100755
index 7259ead..0000000
--- a/FreeRTOS/Source/portable/WizC/PIC18/Install.bat
+++ /dev/null
@@ -1,172 +0,0 @@
-
-@echo off
-cls
-
-SET PACKAGENAME=the FreeRTOS port for fedC and wizC
-
-echo.
-echo Hello, I'm the installationscript for %PACKAGENAME%.
-echo.
-
-:CHECKFEDC
-  set FED=C:\Program Files\FED\PIC_C
-  echo.
-  echo I'm checking your system for fedC
-  if not exist "%FED%" goto NOFEDC
-  echo YES, I found a fedC-installation!
-  goto FOUNDFED
-:NOFEDC
-  echo I could not find a fedC-installation.
-
-
-:CHECKWIZC
-  set FED=C:\Program Files\FED\PIXIE
-  echo.
-  echo I'm checking your system for wizC
-  if not exist "%FED%" goto NOWIZC
-  echo YES, I found a wizC-installation!
-  goto FOUNDFED
-:noWIZC
-  echo I could not find a wizC-installation.
-
-
-:ERROR
-  echo.
-  echo.
-  echo I could not find a FED C-compiler installation on your system.
-  echo.
-  echo Perhaps I got confused because you installed fedC or wizC in a non-default directory.
-  echo If this is the case, please change the path at the top of this install-script.
-  echo After that rerun the script and I will be happy to try again.
-  echo.
-  goto ENDIT
-
-
-:FOUNDFED
-  echo.
-  echo.
-
-  set FEDLIBS=%FED%\Libs
-  set FEDLIBSUSER=%FEDLIBS%\LibsUser
-
-  if exist "%FEDLIBS%" goto INSTALL
-  echo The FED installationdirectory "%FED%"
-  echo contains no Libs subdirectory. This is weird!
-  echo.
-  echo Installation is aborted, sorry...
-  goto ENDIT
-
-
-:INSTALL
-  echo I am about to install %PACKAGENAME%
-  echo into directory %FEDLIBSUSER%
-  echo.
-  echo   Press 'enter'  to let me do my thing
-  echo   Press 'ctrl-c' to stop me
-  pause >nul
-  echo.
-  echo Installing...
-
-
-:RESET_READONLY
-  echo.
-  echo   Removing ReadOnly attributes
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c"     >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c"         >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c"         >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c"        >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c"        >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c"    >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h"    >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h"     >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h"         >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h"     >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h"     >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h"        >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h"       >nul
-  attrib -R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h"         >nul
-  attrib -R "%FEDLIBSUSER%\FreeRTOS.h"                         >nul
-  echo   Done
-
-:CREATE_DIRECTORIES
-  echo.
-  echo   Creating directories (if necessary)...
-  if not exist "%FEDLIBSUSER%"                          mkdir "%FEDLIBSUSER%"
-  if not exist "%FEDLIBSUSER%\libFreeRTOS"              mkdir "%FEDLIBSUSER%\libFreeRTOS"
-  if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers"      mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers"
-  if not exist "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick" mkdir "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick"
-  if not exist "%FEDLIBSUSER%\libFreeRTOS\Include"      mkdir "%FEDLIBSUSER%\libFreeRTOS\Include"
-  if not exist "%FEDLIBSUSER%\libFreeRTOS\Modules"      mkdir "%FEDLIBSUSER%\libFreeRTOS\Modules"
-  echo   Done
-
-
-  echo.
-  echo   Copying Files...
-:COPY_MODULES
-  echo     Modules...
-  copy /V /Y "Port.c"                      "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c"         >nul
-  copy /V /Y "..\..\..\Croutine.c"         "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c"     >nul
-  copy /V /Y "..\..\..\List.c"             "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c"         >nul
-  copy /V /Y "..\..\..\Queue.c"            "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c"        >nul
-  copy /V /Y "..\..\..\Tasks.c"            "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c"        >nul
-
-:COPY_DRIVERS
-  echo     Drivers...
-  copy /V /Y "Drivers\Tick\Tick.c"         "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c"    >nul
-  copy /V /Y "Drivers\Tick\isrTick.c"      "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul
-
-:COPY_HEADERS
-  echo     Headers...
-  copy /V /Y "portmacro.h"                 "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h"    >nul
-  copy /V /Y "..\..\..\include\Croutine.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h"     >nul
-  copy /V /Y "..\..\..\include\List.h"     "%FEDLIBSUSER%\libFreeRTOS\Include\List.h"         >nul
-  copy /V /Y "..\..\..\include\Portable.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h"     >nul
-  copy /V /Y "..\..\..\include\Projdefs.h" "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h"     >nul
-  copy /V /Y "..\..\..\include\Queue.h"    "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h"        >nul
-  copy /V /Y "..\..\..\include\Semphr.h"   "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h"       >nul
-  copy /V /Y "..\..\..\include\Task.h"     "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h"         >nul
-  copy /V /Y "addFreeRTOS.h" + "..\..\..\include\FreeRTOS.h" "%FEDLIBSUSER%\FreeRTOS.h"       >nul
-
-
-  echo   Done
-
-
-:SET_READONLY
-  echo.
-  echo   Setting files to ReadOnly
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Port.c"         >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Croutine.c"     >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\List.c"         >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Queue.c"        >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Modules\Tasks.c"        >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\Tick.c"    >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Drivers\Tick\isrTick.c" >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portmacro.h"    >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Croutine.h"     >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\List.h"         >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Portable.h"     >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Projdefs.h"     >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Queue.h"        >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Semphr.h"       >nul
-  attrib +R "%FEDLIBSUSER%\libFreeRTOS\Include\Task.h"         >nul
-  attrib +R "%FEDLIBSUSER%\FreeRTOS.h"                         >nul
-  echo   Done
-
-
-:FINISHED
-  echo.
-  echo The installation of %PACKAGENAME% is completed.
-  echo.
-  echo Please review the installation instructions as additional libraries
-  echo  and fedC/wizC configuration settings may be needed for FreeRTOS
-  echo  to function correctly.
-
-  goto ENDIT
-
-
-:ENDIT
-  echo.
-  echo.
-  echo Press 'enter' to close this window
-  pause >nul
diff --git a/FreeRTOS/Source/portable/WizC/PIC18/addFreeRTOS.h b/FreeRTOS/Source/portable/WizC/PIC18/addFreeRTOS.h
deleted file mode 100755
index 713ae70..0000000
--- a/FreeRTOS/Source/portable/WizC/PIC18/addFreeRTOS.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-Changes from V3.0.0
-
-Changes from V3.0.1
-
-Changes from V4.0.1
-    Uselib pragma added for Croutine.c
-*/
-
-/*
- * The installation script will automatically prepend this file to the default FreeRTOS.h.
- */
-
-#ifndef WIZC_FREERTOS_H
-#define WIZC_FREERTOS_H
-
-#pragma	noheap
-#pragma wizcpp expandnl   on
-#pragma wizcpp searchpath "$__PATHNAME__/libFreeRTOS/Include/"
-#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Croutine.c"
-#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Tasks.c"
-#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Queue.c"
-#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/List.c"
-#pragma wizcpp uselib     "$__PATHNAME__/libFreeRTOS/Modules/Port.c"
-
-#endif	/* WIZC_FREERTOS_H */
diff --git a/FreeRTOS/Source/portable/WizC/PIC18/port.c b/FreeRTOS/Source/portable/WizC/PIC18/port.c
deleted file mode 100755
index 2417675..0000000
--- a/FreeRTOS/Source/portable/WizC/PIC18/port.c
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-Changes from V3.2.1
-	+ CallReturn Depth increased from 8 to 10 levels to accomodate wizC/fedC V12.
-
-Changes from V3.2.0
-	+ TBLPTRU is now initialised to zero during the initial stack creation of a new task. This solves
-	an error on devices with more than 64kB ROM.
-
-Changes from V3.0.0
-	+ ucCriticalNesting is now initialised to 0x7F to prevent interrupts from being
-          handled before the scheduler is started.
-
-Changes from V3.0.1
-*/
-
-/* Scheduler include files. */
-#include 
-#include 
-
-#include 
-
-/*---------------------------------------------------------------------------
- * Implementation of functions defined in portable.h for the WizC PIC18 port.
- *---------------------------------------------------------------------------*/
-
-/*
- * We require the address of the pxCurrentTCB variable, but don't want to
- * know any details of its type.
- */
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-
-/*
- * Define minimal-stack constants
- * -----
- * FSR's:
- *		STATUS, WREG, BSR, PRODH, PRODL, FSR0H, FSR0L,
- *		FSR1H, FSR1L,TABLAT, (TBLPTRU), TBLPTRH, TBLPTRL,
- *		(PCLATU), PCLATH
- *		sfr's within parenthesis only on devices > 64kB
- * -----
- * Call/Return stack:
- *		 2 bytes per entry on devices <= 64kB
- *		 3 bytes per entry on devices >  64kB
- * -----
- * Other bytes:
- *		 2 bytes: FunctionParameter for initial taskcode
- *		 1 byte : Number of entries on call/return stack
- *		 1 byte : ucCriticalNesting
- *		16 bytes: Free space on stack
- */
-#if _ROMSIZE > 0x8000
-	#define portSTACK_FSR_BYTES				( 15 )
-	#define portSTACK_CALLRETURN_ENTRY_SIZE	(  3 )
-#else
-	#define portSTACK_FSR_BYTES				( 13 )
-	#define portSTACK_CALLRETURN_ENTRY_SIZE	(  2 )
-#endif
-
-#define portSTACK_MINIMAL_CALLRETURN_DEPTH	( 10 )
-#define portSTACK_OTHER_BYTES				( 20 )
-
-uint16_t usCalcMinStackSize		= 0;
-
-/*-----------------------------------------------------------*/
-
-/*
- * We initialise ucCriticalNesting to the middle value an
- * uint8_t can contain. This way portENTER_CRITICAL()
- * and portEXIT_CRITICAL() can be called without interrupts
- * being enabled before the scheduler starts.
- */
-register uint8_t ucCriticalNesting = 0x7F;
-
-/*-----------------------------------------------------------*/
-
-/*
- * Initialise the stack of a new task.
- * See portSAVE_CONTEXT macro for description.
- */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-uint8_t ucScratch;
-	/*
-	 * Get the size of the RAMarea in page 0 used by the compiler
-	 * We do this here already to avoid W-register conflicts.
-	 */
-	_Pragma("asm")
-		movlw	OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE
-		movwf	PRODL,ACCESS		; PRODL is used as temp register
-	_Pragma("asmend")
-	ucScratch = PRODL;
-
-	/*
-	 * Place a few bytes of known values on the bottom of the stack.
-	 * This is just useful for debugging.
-	 */
-//	*pxTopOfStack--	= 0x11;
-//	*pxTopOfStack-- = 0x22;
-//	*pxTopOfStack-- = 0x33;
-
-	/*
-	 * Simulate how the stack would look after a call to vPortYield()
-	 * generated by the compiler.
-	 */
-
-	/*
-	 * First store the function parameters.  This is where the task expects
-	 * to find them when it starts running.
-	 */
-	*pxTopOfStack-- = ( StackType_t ) ( (( uint16_t ) pvParameters >> 8) & 0x00ff );
-	*pxTopOfStack-- = ( StackType_t ) (  ( uint16_t ) pvParameters       & 0x00ff );
-
-	/*
-	 * Next are all the registers that form part of the task context.
-	 */
-	*pxTopOfStack-- = ( StackType_t ) 0x11; /* STATUS. */
-	*pxTopOfStack-- = ( StackType_t ) 0x22; /* WREG. */
-	*pxTopOfStack-- = ( StackType_t ) 0x33; /* BSR. */
-	*pxTopOfStack-- = ( StackType_t ) 0x44; /* PRODH. */
-	*pxTopOfStack-- = ( StackType_t ) 0x55; /* PRODL. */
-	*pxTopOfStack-- = ( StackType_t ) 0x66; /* FSR0H. */
-	*pxTopOfStack-- = ( StackType_t ) 0x77; /* FSR0L. */
-	*pxTopOfStack-- = ( StackType_t ) 0x88; /* FSR1H. */
-	*pxTopOfStack-- = ( StackType_t ) 0x99; /* FSR1L. */
-	*pxTopOfStack-- = ( StackType_t ) 0xAA; /* TABLAT. */
-#if _ROMSIZE > 0x8000
-	*pxTopOfStack-- = ( StackType_t ) 0x00; /* TBLPTRU. */
-#endif
-	*pxTopOfStack-- = ( StackType_t ) 0xCC; /* TBLPTRH. */
-	*pxTopOfStack-- = ( StackType_t ) 0xDD; /* TBLPTRL. */
-#if _ROMSIZE > 0x8000
-	*pxTopOfStack-- = ( StackType_t ) 0xEE; /* PCLATU. */
-#endif
-	*pxTopOfStack-- = ( StackType_t ) 0xFF; /* PCLATH. */
-
-	/*
-	 * Next the compiler's scratchspace.
-	 */
-	while(ucScratch-- > 0)
-	{
-		*pxTopOfStack-- = ( StackType_t ) 0;
-	}
-
-	/*
-	 * The only function return address so far is the address of the task entry.
-	 * The order is TOSU/TOSH/TOSL. For devices > 64kB, TOSU is put on the
-	 * stack, too. TOSU is always written as zero here because wizC does not allow
-	 * functionpointers to point above 64kB in ROM.
-	 */
-#if _ROMSIZE > 0x8000
-	*pxTopOfStack-- = ( StackType_t ) 0;
-#endif
-	*pxTopOfStack-- = ( StackType_t ) ( ( ( uint16_t ) pxCode >> 8 ) & 0x00ff );
-	*pxTopOfStack-- = ( StackType_t ) ( (   uint16_t ) pxCode        & 0x00ff );
-
-	/*
-	 * Store the number of return addresses on the hardware stack.
-	 * So far only the address of the task entry point.
-	 */
-	*pxTopOfStack-- = ( StackType_t ) 1;
-
-	/*
-	 * The code generated by wizC does not maintain separate
-	 * stack and frame pointers. Therefore the portENTER_CRITICAL macro cannot
-	 * use the stack as per other ports.  Instead a variable is used to keep
-	 * track of the critical section nesting.  This variable has to be stored
-	 * as part of the task context and is initially set to zero.
-	 */
-	*pxTopOfStack-- = ( StackType_t ) portNO_CRITICAL_SECTION_NESTING;
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void )
-{
-	/*
-	 * Fetch the size of compiler's scratchspace.
-	 */
-	_Pragma("asm")
-		movlw	OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE
-		movlb	usCalcMinStackSize>>8
-		movwf	usCalcMinStackSize,BANKED
-	_Pragma("asmend")
-
-	/*
-	 * Add minimum needed stackspace
-	 */
-	usCalcMinStackSize	+=	( portSTACK_FSR_BYTES )
-		+	( portSTACK_MINIMAL_CALLRETURN_DEPTH * portSTACK_CALLRETURN_ENTRY_SIZE )
-		+	( portSTACK_OTHER_BYTES );
-
-	return(usCalcMinStackSize);
-}
-
-/*-----------------------------------------------------------*/
-
-BaseType_t xPortStartScheduler( void )
-{
-	extern void portSetupTick( void );
-
-	/*
-	 * Setup a timer for the tick ISR for the preemptive scheduler.
-	 */
-	portSetupTick();
-
-	/*
-	 * Restore the context of the first task to run.
-	 */
-	portRESTORE_CONTEXT();
-
-	/*
-	 * This point should never be reached during execution.
-	 */
-	return pdTRUE;
-}
-
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/*
-	 * It is unlikely that the scheduler for the PIC port will get stopped
-	 * once running. When called a reset is done which is probably the
-	 * most valid action.
-	 */
-	_Pragma(asmline reset);
-}
-
-/*-----------------------------------------------------------*/
-
-/*
- * Manual context switch.  This is similar to the tick context switch,
- * but does not increment the tick count.  It must be identical to the
- * tick context switch in how it stores the stack of a task.
- */
-void vPortYield( void )
-{
-	/*
-	 * Save the context of the current task.
-	 */
-	portSAVE_CONTEXT( portINTERRUPTS_UNCHANGED );
-
-	/*
-	 * Switch to the highest priority task that is ready to run.
-	 */
-	vTaskSwitchContext();
-
-	/*
-	 * Start executing the task we have just switched to.
-	 */
-	portRESTORE_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-	void *pvPortMalloc( uint16_t usWantedSize )
-	{
-	void *pvReturn;
-
-		vTaskSuspendAll();
-		{
-			pvReturn = malloc( ( malloc_t ) usWantedSize );
-		}
-		xTaskResumeAll();
-
-		return pvReturn;
-	}
-
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-	void vPortFree( void *pv )
-	{
-		if( pv )
-		{
-			vTaskSuspendAll();
-			{
-				free( pv );
-			}
-			xTaskResumeAll();
-		}
-	}
-
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
\ No newline at end of file
diff --git a/FreeRTOS/Source/portable/WizC/PIC18/portmacro.h b/FreeRTOS/Source/portable/WizC/PIC18/portmacro.h
deleted file mode 100755
index 1a69275..0000000
--- a/FreeRTOS/Source/portable/WizC/PIC18/portmacro.h
+++ /dev/null
@@ -1,423 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-Changes from V3.0.0
-
-Changes from V3.0.1
-*/
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#if !defined(_SERIES) || _SERIES != 18
-	#error "WizC supports FreeRTOS on the Microchip PIC18-series only"
-#endif
-
-#if !defined(QUICKCALL) || QUICKCALL != 1
-	#error "QuickCall must be enabled (see ProjectOptions/Optimisations)"
-#endif
-
-#include 
-#include 
-
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		portFLOAT
-#define portLONG		long
-#define portSHORT		short
-#define portSTACK_TYPE	uint8_t
-#define portBASE_TYPE	char
-
-typedef portSTACK_TYPE StackType_t;
-typedef signed char BaseType_t;
-typedef unsigned char UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )	( 0xFFFF )
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t )	( 0xFFFFFFFF )
-#endif
-
-#define portBYTE_ALIGNMENT			1
-
-/*-----------------------------------------------------------*/
-
-/*
- * Constant used for context switch macro when we require the interrupt
- * enable state to be forced when the interrupted task is switched back in.
- */
-#define portINTERRUPTS_FORCED				(0x01)
-
-/*
- * Constant used for context switch macro when we require the interrupt
- * enable state to be unchanged when the interrupted task is switched back in.
- */
-#define portINTERRUPTS_UNCHANGED			(0x00)
-
-/* Initial interrupt enable state for newly created tasks.  This value is
- * used when a task switches in for the first time.
- */
-#define portINTERRUPTS_INITIAL_STATE		(portINTERRUPTS_FORCED)
-
-/*
- * Macros to modify the global interrupt enable bit in INTCON.
- */
-#define portDISABLE_INTERRUPTS()	\
-	do								\
-	{								\
-		bGIE=0;						\
-	} while(bGIE)	// MicroChip recommends this check!
-
-#define portENABLE_INTERRUPTS()		\
-	do								\
-	{								\
-		bGIE=1;						\
-	} while(0)
-
-/*-----------------------------------------------------------*/
-
-/*
- * Critical section macros.
- */
-extern uint8_t ucCriticalNesting;
-
-#define portNO_CRITICAL_SECTION_NESTING		( ( uint8_t ) 0 )
-
-#define portENTER_CRITICAL()										\
-	do																\
-	{																\
-		portDISABLE_INTERRUPTS();									\
-																	\
-		/*															\
-		 * Now interrupts are disabled ucCriticalNesting			\
-		 * can be accessed directly. Increment						\
-		 * ucCriticalNesting to keep a count of how					\
-		 * many times portENTER_CRITICAL() has been called. 		\
-		 */															\
-		ucCriticalNesting++;										\
-	} while(0)
-
-#define portEXIT_CRITICAL()											\
-	do																\
-	{																\
-		if(ucCriticalNesting > portNO_CRITICAL_SECTION_NESTING)		\
-		{															\
-			/*														\
-			 * Decrement the nesting count as we are leaving a		\
-			 * critical section.									\
-			 */														\
-			ucCriticalNesting--;									\
-		}															\
-																	\
-		/*															\
-		 * If the nesting level has reached zero then				\
-		 * interrupts should be re-enabled.							\
-		 */															\
-		if( ucCriticalNesting == portNO_CRITICAL_SECTION_NESTING )	\
-		{															\
-			portENABLE_INTERRUPTS();								\
-		}															\
-	} while(0)
-
-/*-----------------------------------------------------------*/
-
-/*
- * The minimal stacksize is calculated on the first reference of
- * portMINIMAL_STACK_SIZE. Some input to this calculation is
- * compiletime determined, other input is port-defined (see port.c)
- */
-extern uint16_t usPortCALCULATE_MINIMAL_STACK_SIZE( void );
-extern uint16_t usCalcMinStackSize;
-
-#define portMINIMAL_STACK_SIZE					\
-	((usCalcMinStackSize == 0)					\
-		? usPortCALCULATE_MINIMAL_STACK_SIZE()	\
-		: usCalcMinStackSize )
-
-/*
- * WizC uses a downgrowing stack
- */
-#define portSTACK_GROWTH			( -1 )
-
-/*-----------------------------------------------------------*/
-
-/*
- * Macro's that pushes all the registers that make up the context of a task onto
- * the stack, then saves the new top of stack into the TCB. TOSU and TBLPTRU
- * are only saved/restored on devices with more than 64kB (32k Words) ROM.
- *
- * The stackpointer is helt by WizC in FSR2 and points to the first free byte.
- * WizC uses a "downgrowing" stack. There is no framepointer.
- *
- * We keep track of the interruptstatus using ucCriticalNesting. When this
- * value equals zero, interrupts have to be enabled upon exit from the
- * portRESTORE_CONTEXT macro.
- *
- * If this is called from an ISR then the interrupt enable bits must have been
- * set for the ISR to ever get called.  Therefore we want to save
- * ucCriticalNesting with value zero. This means the interrupts will again be
- * re-enabled when the interrupted task is switched back in.
- *
- * If this is called from a manual context switch (i.e. from a call to yield),
- * then we want to keep the current value of ucCritialNesting so it is restored
- * with its current value. This allows a yield from within a critical section.
- *
- * The compiler uses some locations at the bottom of RAM for temporary
- * storage. The compiler may also have been instructed to optimize
- * function-parameters and local variables to global storage. The compiler
- * uses an area called LocOpt for this wizC feature.
- * The total overheadstorage has to be saved in it's entirety as part of
- * a task context. These macro's store/restore from data address 0x0000 to
- * (OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE - 1).
- * OVERHEADPAGE0, LOCOPTSIZE and MAXLOCOPTSIZE are compiler-generated
- * assembler definitions.
- */
-
-#define	portSAVE_CONTEXT( ucInterruptForced )						\
-	do																\
-	{																\
-		portDISABLE_INTERRUPTS();									\
-																	\
-		_Pragma("asm")												\
-			;														\
-			; Push the relevant SFR's onto the task's stack			\
-			;														\
-			movff   STATUS,POSTDEC2									\
-			movff	WREG,POSTDEC2									\
-			movff	BSR,POSTDEC2									\
-			movff	PRODH,POSTDEC2									\
-			movff	PRODL,POSTDEC2									\
-			movff	FSR0H,POSTDEC2									\
-			movff	FSR0L,POSTDEC2									\
-			movff	FSR1H,POSTDEC2									\
-			movff	FSR1L,POSTDEC2									\
-			movff	TABLAT,POSTDEC2									\
-			if __ROMSIZE > 0x8000									\
-				movff	TBLPTRU,POSTDEC2							\
-			endif													\
-			movff	TBLPTRH,POSTDEC2								\
-			movff	TBLPTRL,POSTDEC2								\
-			if __ROMSIZE > 0x8000									\
-				movff	PCLATU,POSTDEC2								\
-			endif													\
-			movff	PCLATH,POSTDEC2									\
-			;														\
-			; Store the compiler-scratch-area as described above.	\
-			;														\
-			movlw	OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE			\
-			clrf	FSR0L,ACCESS									\
-			clrf	FSR0H,ACCESS									\
-		_rtos_S1:													\
-			movff	POSTINC0,POSTDEC2								\
-			decfsz	WREG,W,ACCESS									\
-			SMARTJUMP _rtos_S1										\
-			;														\
-			; Save the pic call/return-stack belonging to the		\
-			; current task by copying it to the task's software-	\
-			; stack. We save the hardware stack pointer (which		\
-			; is the number of addresses on the stack) in the		\
-			; W-register first because we need it later and it		\
-			; is modified in the save-loop by executing pop's.		\
-			; After the loop the W-register is stored on the		\
-			; stack, too.											\
-			;														\
-			movf	STKPTR,W,ACCESS									\
-			bz		_rtos_s3										\
-		_rtos_S2:													\
-			if __ROMSIZE > 0x8000									\
-				movff	TOSU,POSTDEC2								\
-			endif													\
-			movff	TOSH,POSTDEC2									\
-			movff	TOSL,POSTDEC2									\
-			pop														\
-			tstfsz	STKPTR,ACCESS									\
-			SMARTJUMP _rtos_S2										\
-		_rtos_s3:													\
-			movwf	POSTDEC2,ACCESS									\
-			;														\
-			; Next the value for ucCriticalNesting used by the		\
-			; task is stored on the stack. When						\
-			; (ucInterruptForced == portINTERRUPTS_FORCED), we save	\
-			; it as 0 (portNO_CRITICAL_SECTION_NESTING).			\
-			;														\
-			if ucInterruptForced == portINTERRUPTS_FORCED			\
-				clrf POSTDEC2,ACCESS								\
-			else													\
-				movff	ucCriticalNesting,POSTDEC2					\
-			endif													\
-			;														\
-			; Save the new top of the software stack in the TCB.	\
-			;														\
-			movff	pxCurrentTCB,FSR0L								\
-			movff	pxCurrentTCB+1,FSR0H							\
-			movff	FSR2L,POSTINC0									\
-			movff	FSR2H,POSTINC0									\
-		_Pragma("asmend")											\
-	} while(0)
-
-/************************************************************/
-
-/*
- * This is the reverse of portSAVE_CONTEXT.
- */
-#define portRESTORE_CONTEXT()										\
-	do																\
-	{																\
-		_Pragma("asm")												\
-			;														\
-			; Set FSR0 to point to pxCurrentTCB->pxTopOfStack.		\
-			;														\
-			movff	pxCurrentTCB,FSR0L								\
-			movff	pxCurrentTCB+1,FSR0H							\
-			;														\
-			; De-reference FSR0 to set the address it holds into	\
-			; FSR2 (i.e. *( pxCurrentTCB->pxTopOfStack ) ). FSR2	\
-			; is used by wizC as stackpointer.						\
-			;														\
-			movff	POSTINC0,FSR2L									\
-			movff	POSTINC0,FSR2H									\
-			;														\
-			; Next, the value for ucCriticalNesting used by the		\
-			; task is retrieved from the stack.						\
-			;														\
-			movff	PREINC2,ucCriticalNesting						\
-			;														\
-			; Rebuild the pic call/return-stack. The number of		\
-			; return addresses is the next item on the task stack.	\
-			; Save this number in PRODL. Then fetch the addresses	\
-			; and store them on the hardwarestack.					\
-			; The datasheets say we can't use movff here...			\
-			;														\
-			movff	PREINC2,PRODL	// Use PRODL as tempregister	\
-			clrf	STKPTR,ACCESS									\
-		_rtos_R1:													\
-			push													\
-			movf	PREINC2,W,ACCESS								\
-			movwf	TOSL,ACCESS										\
-			movf	PREINC2,W,ACCESS								\
-			movwf	TOSH,ACCESS										\
-			if __ROMSIZE > 0x8000									\
-				movf	PREINC2,W,ACCESS							\
-				movwf	TOSU,ACCESS									\
-			else													\
-				clrf	TOSU,ACCESS									\
-			endif													\
-			decfsz	PRODL,F,ACCESS									\
-			SMARTJUMP _rtos_R1										\
-			;														\
-			; Restore the compiler's working storage area to page 0	\
-			;														\
-			movlw	OVERHEADPAGE0-LOCOPTSIZE+MAXLOCOPTSIZE			\
-			movwf	FSR0L,ACCESS									\
-			clrf	FSR0H,ACCESS									\
-		_rtos_R2:													\
-			decf	FSR0L,F,ACCESS									\
-			movff	PREINC2,INDF0									\
-			tstfsz	FSR0L,ACCESS									\
-			SMARTJUMP _rtos_R2										\
-			;														\
-			; Restore the sfr's forming the tasks context.			\
-			; We cannot yet restore bsr, w and status because		\
-			; we need these	registers for a final test.				\
-			;														\
-			movff	PREINC2,PCLATH									\
-			if __ROMSIZE > 0x8000									\
-				movff	PREINC2,PCLATU								\
-			else													\
-				clrf	PCLATU,ACCESS								\
-			endif													\
-			movff	PREINC2,TBLPTRL									\
-			movff	PREINC2,TBLPTRH									\
-			if __ROMSIZE > 0x8000									\
-				movff	PREINC2,TBLPTRU								\
-			else													\
-				clrf	TBLPTRU,ACCESS								\
-			endif													\
-			movff	PREINC2,TABLAT									\
-			movff	PREINC2,FSR1L									\
-			movff	PREINC2,FSR1H									\
-			movff	PREINC2,FSR0L									\
-			movff	PREINC2,FSR0H									\
-			movff	PREINC2,PRODL									\
-			movff	PREINC2,PRODH									\
-			;														\
-			; The return from portRESTORE_CONTEXT() depends on		\
-			; the value of ucCriticalNesting. When it is zero,		\
-			; interrupts need to be enabled. This is done via a		\
-			; retfie instruction because we need the				\
-			; interrupt-enabling and the return to the restored		\
-			; task to be uninterruptable.							\
-	 		; Because bsr, status and W are affected by the test	\
-	 		; they are restored after the test.						\
-			;														\
-			movlb	ucCriticalNesting>>8							\
-			tstfsz	ucCriticalNesting,BANKED						\
-			SMARTJUMP _rtos_R4										\
-		_rtos_R3:													\
-			movff	PREINC2,BSR										\
-			movff	PREINC2,WREG									\
-			movff	PREINC2,STATUS									\
-			retfie	0		; Return enabling interrupts			\
-		_rtos_R4:													\
-			movff	PREINC2,BSR										\
-			movff	PREINC2,WREG									\
-			movff	PREINC2,STATUS									\
-			return	0		; Return without affecting interrupts	\
-		_Pragma("asmend")											\
-	} while(0)
-
-/*-----------------------------------------------------------*/
-
-#define portTICK_PERIOD_MS	( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-
-/*-----------------------------------------------------------*/
-
-extern void vPortYield( void );
-#define portYIELD()				vPortYield()
-
-#define portNOP()	_Pragma("asm")									\
-						nop											\
-					_Pragma("asmend")
-
-/*-----------------------------------------------------------*/
-
-#define portTASK_FUNCTION( xFunction, pvParameters )	 	\
-	void pointed xFunction( void *pvParameters )		\
-	_Pragma(asmfunc xFunction)
-
-#define portTASK_FUNCTION_PROTO		portTASK_FUNCTION
-/*-----------------------------------------------------------*/
-
-
-#define volatile
-#define register
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/port.c b/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/port.c
deleted file mode 100755
index ea6931f..0000000
--- a/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/port.c
+++ /dev/null
@@ -1,246 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-Changes from V1.00:
-	
-	+ Call to taskYIELD() from within tick ISR has been replaced by the more
-	  efficient portSWITCH_CONTEXT().
-	+ ISR function definitions renamed to include the prv prefix.
-
-Changes from V1.2.0:
-
-	+ portRESET_PIC() is now called last thing before the end of the preemptive
-	  tick routine.
-
-Changes from V2.6.1
-
-	+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
-	  macro to be consistent with the later ports.
-*/
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the Flashlite 186
- * port.
- *----------------------------------------------------------*/
-
-#include 
-#include 
-#include 
-#include 
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "portasm.h"
-
-/*lint -e950 Non ANSI reserved words okay in this file only. */
-
-#define portTIMER_EOI_TYPE		( 8 )
-#define portRESET_PIC()			portOUTPUT_WORD( ( uint16_t ) 0xff22, portTIMER_EOI_TYPE )
-#define portTIMER_INT_NUMBER	0x12
-
-#define portTIMER_1_CONTROL_REGISTER	( ( uint16_t ) 0xff5e )
-#define portTIMER_0_CONTROL_REGISTER	( ( uint16_t ) 0xff56 )
-#define portTIMER_INTERRUPT_ENABLE		( ( uint16_t ) 0x2000 )
-
-/* Setup the hardware to generate the required tick frequency. */
-static void prvSetTickFrequency( uint32_t ulTickRateHz );
-
-/* Set the hardware back to the state as per before the scheduler started. */
-static void prvExitFunction( void );
-
-#if configUSE_PREEMPTION == 1
-	/* Tick service routine used by the scheduler when preemptive scheduling is
-	being used. */
-	static void __interrupt __far prvPreemptiveTick( void );
-#else
-	/* Tick service routine used by the scheduler when cooperative scheduling is 
-	being used. */
-	static void __interrupt __far prvNonPreemptiveTick( void );
-#endif
-
-/* Trap routine used by taskYIELD() to manually cause a context switch. */
-static void __interrupt __far prvYieldProcessor( void );
-
-/*lint -e956 File scopes necessary here. */
-
-/* Set true when the vectors are set so the scheduler will service the tick. */
-static int16_t sSchedulerRunning = pdFALSE;
-
-/* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
-static void ( __interrupt __far *pxOldSwitchISR )();
-
-/* Used to restore the original DOS context when the scheduler is ended. */
-static jmp_buf xJumpBuf;
-
-/*lint +e956 */
-
-/*-----------------------------------------------------------*/
-BaseType_t xPortStartScheduler( void )
-{
-	/* This is called with interrupts already disabled. */
-
-	/* Remember what was on the interrupts we are going to use
-	so we can put them back later if required. */
-	pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
-
-	/* Put our manual switch (yield) function on a known
-	vector. */
-	_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
-
-	#if configUSE_PREEMPTION == 1
-	{		
-		/* Put our tick switch function on the timer interrupt. */
-		_dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
-	}
-	#else
-	{
-		/* We want the timer interrupt to just increment the tick count. */
-		_dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
-	}
-	#endif
-
-	prvSetTickFrequency( configTICK_RATE_HZ );
-
-	/* Clean up function if we want to return to DOS. */
-	if( setjmp( xJumpBuf ) != 0 )
-	{
-		prvExitFunction();
-		sSchedulerRunning = pdFALSE;
-	}
-	else
-	{
-		sSchedulerRunning = pdTRUE;
-
-		/* Kick off the scheduler by setting up the context of the first task. */
-		portFIRST_CONTEXT();
-	}
-
-	return sSchedulerRunning;
-}
-/*-----------------------------------------------------------*/
-
-/* The tick ISR used depend on whether or not the preemptive or cooperative
-kernel is being used. */
-#if configUSE_PREEMPTION == 1
-	static void __interrupt __far prvPreemptiveTick( void )
-	{
-		/* Get the scheduler to update the task states following the tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Switch in the context of the next task to be run. */
-			portSWITCH_CONTEXT();
-		}
-
-		/* Reset the PIC ready for the next time. */
-		portRESET_PIC();
-	}
-#else
-	static void __interrupt __far prvNonPreemptiveTick( void )
-	{
-		/* Same as preemptive tick, but the cooperative scheduler is being used
-		so we don't have to switch in the context of the next task. */
-		xTaskIncrementTick();
-		portRESET_PIC();
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-static void __interrupt __far prvYieldProcessor( void )
-{
-	/* Switch in the context of the next task to be run. */
-	portSWITCH_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Jump back to the processor state prior to starting the
-	scheduler.  This means we are not going to be using a
-	task stack frame so the task can be deleted. */
-	longjmp( xJumpBuf, 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvExitFunction( void )
-{
-const uint16_t usTimerDisable = 0x0000;
-uint16_t usTimer0Control;
-
-	/* Interrupts should be disabled here anyway - but no 
-	harm in making sure. */
-	portDISABLE_INTERRUPTS();
-	if( sSchedulerRunning == pdTRUE )
-	{
-		/* Put back the switch interrupt routines that was in place
-		before the scheduler started. */
-		_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
-	}
-
-	/* Disable the timer used for the tick to ensure the scheduler is
-	not called before restoring interrupts.  There was previously nothing
-	on this timer so there is no old ISR to restore. */
-	portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerDisable );
-
-	/* Restart the DOS tick. */
-	usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
-	usTimer0Control |= portTIMER_INTERRUPT_ENABLE;
-	portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
-
-
-	portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetTickFrequency( uint32_t ulTickRateHz )
-{
-const uint16_t usMaxCountRegister = 0xff5a;
-const uint16_t usTimerPriorityRegister = 0xff32;
-const uint16_t usTimerEnable = 0xC000;
-const uint16_t usRetrigger = 0x0001;
-const uint16_t usTimerHighPriority = 0x0000;
-uint16_t usTimer0Control;
-
-/* ( CPU frequency / 4 ) / clock 2 max count [inpw( 0xff62 ) = 7] */
-
-const uint32_t ulClockFrequency = 0x7f31a0;
-
-uint32_t ulTimerCount = ulClockFrequency / ulTickRateHz;
-
-	portOUTPUT_WORD( portTIMER_1_CONTROL_REGISTER, usTimerEnable | portTIMER_INTERRUPT_ENABLE | usRetrigger );
-	portOUTPUT_WORD( usMaxCountRegister, ( uint16_t ) ulTimerCount );
-	portOUTPUT_WORD( usTimerPriorityRegister, usTimerHighPriority );
-
-	/* Stop the DOS tick - don't do this if you want to maintain a TOD clock. */
-	usTimer0Control = portINPUT_WORD( portTIMER_0_CONTROL_REGISTER );
-	usTimer0Control &= ~portTIMER_INTERRUPT_ENABLE;
-	portOUTPUT_WORD( portTIMER_0_CONTROL_REGISTER, usTimer0Control );
-}
-
-
-/*lint +e950 */
-
diff --git a/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h b/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
deleted file mode 100755
index 2433c6b..0000000
--- a/FreeRTOS/Source/portable/oWatcom/16BitDOS/Flsh186/portmacro.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-
-/* Type definitions. */
-#define portCHAR        char
-#define portFLOAT       float
-#define portDOUBLE      long
-#define portLONG        long
-#define portSHORT       int
-#define portSTACK_TYPE  uint16_t
-#define portBASE_TYPE	short
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-        typedef uint16_t TickType_t;
-        #define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-        typedef uint32_t TickType_t;
-        #define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Critical section management. */
-void portENTER_CRITICAL( void );
-#pragma aux portENTER_CRITICAL = "pushf" \
-                                 "cli";
-
-void portEXIT_CRITICAL( void );
-#pragma aux portEXIT_CRITICAL   = "popf";
-
-void portDISABLE_INTERRUPTS( void );
-#pragma aux portDISABLE_INTERRUPTS = "cli";
-
-void portENABLE_INTERRUPTS( void );
-#pragma aux portENABLE_INTERRUPTS = "sti";
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH        ( -1 )
-#define portSWITCH_INT_NUMBER   0x80
-#define portYIELD()             __asm{ int portSWITCH_INT_NUMBER }
-#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portBYTE_ALIGNMENT      2
-#define portINITIAL_SW          ( ( portSTACK_TYPE ) 0x0202 )   /* Start the tasks with interrupts enabled. */
-#define portNOP()				__asm{ nop }
-/*-----------------------------------------------------------*/
-
-/* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )                 inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )       outp( xAddr, ucValue )
-#define portINPUT_WORD( xAddr )                 inpw( xAddr )
-#define portOUTPUT_WORD( xAddr, usValue )       outpw( xAddr, usValue )
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
-#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/port.c b/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/port.c
deleted file mode 100755
index 09fcf9d..0000000
--- a/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/port.c
+++ /dev/null
@@ -1,302 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-Changes from V1.00:
-	
-	+ Call to taskYIELD() from within tick ISR has been replaced by the more
-	  efficient portSWITCH_CONTEXT().
-	+ ISR function definitions renamed to include the prv prefix.
-
-Changes from V1.2.0:
-
-	+ prvPortResetPIC() is now called last thing before the end of the 
-	  preemptive tick routine.
-
-Changes from V2.6.1
-
-	+ Replaced the sUsingPreemption variable with the configUSE_PREEMPTION
-	  macro to be consistent with the later ports.
-
-Changes from V4.0.1
-	
-	+ Add function prvSetTickFrequencyDefault() to set the DOS tick back to
-	  its proper value when the scheduler exits. 
-*/
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "portasm.h"
-
-/*-----------------------------------------------------------
- * Implementation of functions defined in portable.h for the industrial
- * PC port.
- *----------------------------------------------------------*/
-
-/*lint -e950 Non ANSI reserved words okay in this file only. */
-
-#define portTIMER_INT_NUMBER	0x08
-
-/* Setup hardware for required tick interrupt rate. */
-static void prvSetTickFrequency( uint32_t ulTickRateHz );
-
-/* Restore hardware to as it was prior to starting the scheduler. */
-static void prvExitFunction( void );
-
-/* Either chain to the DOS tick (which itself clears the PIC) or clear the PIC
-directly.  We chain to the DOS tick as close as possible to the standard DOS
-tick rate. */
-static void prvPortResetPIC( void );
-
-/* The tick ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if configUSE_PREEMPTION == 1
-	/* Tick service routine used by the scheduler when preemptive scheduling is
-	being used. */
-	static void __interrupt __far prvPreemptiveTick( void );
-#else
-	/* Tick service routine used by the scheduler when cooperative scheduling is 
-	being used. */
-	static void __interrupt __far prvNonPreemptiveTick( void );
-#endif
-/* Trap routine used by taskYIELD() to manually cause a context switch. */
-static void __interrupt __far prvYieldProcessor( void );
-
-/* Set the tick frequency back so the floppy drive works correctly when the
-scheduler exits. */
-static void prvSetTickFrequencyDefault( void );
-
-/*lint -e956 File scopes necessary here. */
-
-/* Used to signal when to chain to the DOS tick, and when to just clear the PIC ourselves. */
-static int16_t sDOSTickCounter;							
-
-/* Set true when the vectors are set so the scheduler will service the tick. */
-static int16_t sSchedulerRunning = pdFALSE;				
-
-/* Points to the original routine installed on the vector we use for manual context switches.  This is then used to restore the original routine during prvExitFunction(). */
-static void ( __interrupt __far *pxOldSwitchISR )();		
-
-/* Points to the original routine installed on the vector we use to chain to the DOS tick.  This is then used to restore the original routine during prvExitFunction(). */
-static void ( __interrupt __far *pxOldSwitchISRPlus1 )();	
-
-/* Used to restore the original DOS context when the scheduler is ended. */
-static jmp_buf xJumpBuf;
-
-/*lint +e956 */
-
-/*-----------------------------------------------------------*/
-BaseType_t xPortStartScheduler( void )
-{
-pxISR pxOriginalTickISR;
-	
-	/* This is called with interrupts already disabled. */
-
-	/* Remember what was on the interrupts we are going to use
-	so we can put them back later if required. */
-	pxOldSwitchISR = _dos_getvect( portSWITCH_INT_NUMBER );
-	pxOriginalTickISR = _dos_getvect( portTIMER_INT_NUMBER );
-	pxOldSwitchISRPlus1 = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
-
-	prvSetTickFrequency( configTICK_RATE_HZ );
-
-	/* Put our manual switch (yield) function on a known
-	vector. */
-	_dos_setvect( portSWITCH_INT_NUMBER, prvYieldProcessor );
-
-	/* Put the old tick on a different interrupt number so we can
-	call it when we want. */
-	_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOriginalTickISR );
-
-	#if configUSE_PREEMPTION == 1
-	{		
-		/* Put our tick switch function on the timer interrupt. */
-		_dos_setvect( portTIMER_INT_NUMBER, prvPreemptiveTick );
-	}
-	#else
-	{
-		/* We want the timer interrupt to just increment the tick count. */
-		_dos_setvect( portTIMER_INT_NUMBER, prvNonPreemptiveTick );
-	}
-	#endif
-
-	/* Setup a counter that is used to call the DOS interrupt as close
-	to it's original frequency as can be achieved given our chosen tick
-	frequency. */
-	sDOSTickCounter = portTICKS_PER_DOS_TICK;
-
-	/* Clean up function if we want to return to DOS. */
-	if( setjmp( xJumpBuf ) != 0 )
-	{
-		prvExitFunction();
-		sSchedulerRunning = pdFALSE;
-	}
-	else
-	{
-		sSchedulerRunning = pdTRUE;
-
-		/* Kick off the scheduler by setting up the context of the first task. */
-		portFIRST_CONTEXT();
-	}
-
-	return sSchedulerRunning;
-}
-/*-----------------------------------------------------------*/
-
-/* The tick ISR used depends on whether the preemptive or cooperative scheduler
-is being used. */
-#if configUSE_PREEMPTION == 1
-	/* Tick service routine used by the scheduler when preemptive scheduling is
-	being used. */
-	static void __interrupt __far prvPreemptiveTick( void )
-	{
-		/* Get the scheduler to update the task states following the tick. */
-		if( xTaskIncrementTick() != pdFALSE )
-		{
-			/* Switch in the context of the next task to be run. */
-			portSWITCH_CONTEXT();
-		}
-
-		/* Reset the PIC ready for the next time. */
-		prvPortResetPIC();
-	}
-#else
-	static void __interrupt __far prvNonPreemptiveTick( void )
-	{
-		/* Same as preemptive tick, but the cooperative scheduler is being used
-		so we don't have to switch in the context of the next task. */
-		xTaskIncrementTick();
-		prvPortResetPIC();
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-
-static void __interrupt __far prvYieldProcessor( void )
-{
-	/* Switch in the context of the next task to be run. */
-	portSWITCH_CONTEXT();
-}
-/*-----------------------------------------------------------*/
-
-static void prvPortResetPIC( void )
-{
-	/* We are going to call the DOS tick interrupt at as close a
-	frequency to the normal DOS tick as possible. */
-
-	/* WE SHOULD NOT DO THIS IF YIELD WAS CALLED. */
-	--sDOSTickCounter;
-	if( sDOSTickCounter <= 0 )
-	{
-		sDOSTickCounter = ( int16_t ) portTICKS_PER_DOS_TICK;
-		__asm{ int	portSWITCH_INT_NUMBER + 1 };		 
-	}
-	else
-	{
-		/* Reset the PIC as the DOS tick is not being called to
-		do it. */
-		__asm
-		{
-			mov	al, 20H
-			out 20H, al
-		};
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vPortEndScheduler( void )
-{
-	/* Jump back to the processor state prior to starting the
-	scheduler.  This means we are not going to be using a
-	task stack frame so the task can be deleted. */
-	longjmp( xJumpBuf, 1 );
-}
-/*-----------------------------------------------------------*/
-
-static void prvExitFunction( void )
-{
-void ( __interrupt __far *pxOriginalTickISR )();
-
-	/* Interrupts should be disabled here anyway - but no 
-	harm in making sure. */
-	portDISABLE_INTERRUPTS();
-	if( sSchedulerRunning == pdTRUE )
-	{
-		/* Set the DOS tick back onto the timer ticker. */
-		pxOriginalTickISR = _dos_getvect( portSWITCH_INT_NUMBER + 1 );
-		_dos_setvect( portTIMER_INT_NUMBER, pxOriginalTickISR );
-		prvSetTickFrequencyDefault();
-
-		/* Put back the switch interrupt routines that was in place
-		before the scheduler started. */
-		_dos_setvect( portSWITCH_INT_NUMBER, pxOldSwitchISR );
-		_dos_setvect( portSWITCH_INT_NUMBER + 1, pxOldSwitchISRPlus1 );
-	}
-	/* The tick timer is back how DOS wants it.  We can re-enable
-	interrupts without the scheduler being called. */
-	portENABLE_INTERRUPTS();
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetTickFrequency( uint32_t ulTickRateHz )
-{
-const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
-const uint16_t usPIT0 = ( uint16_t ) 0x40;
-const uint32_t ulPIT_CONST = ( uint32_t ) 1193180;
-const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
-uint32_t ulOutput;
-
-	/* Setup the 8245 to tick at the wanted frequency. */
-	portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
-	ulOutput = ulPIT_CONST / ulTickRateHz;
-   
-	portOUTPUT_BYTE( usPIT0, ( uint16_t )( ulOutput & ( uint32_t ) 0xff ) );
-	ulOutput >>= 8;
-	portOUTPUT_BYTE( usPIT0, ( uint16_t ) ( ulOutput & ( uint32_t ) 0xff ) );
-}
-/*-----------------------------------------------------------*/
-
-static void prvSetTickFrequencyDefault( void )
-{
-const uint16_t usPIT_MODE = ( uint16_t ) 0x43;
-const uint16_t usPIT0 = ( uint16_t ) 0x40;
-const uint16_t us8254_CTR0_MODE3 = ( uint16_t ) 0x36;
-
-	portOUTPUT_BYTE( usPIT_MODE, us8254_CTR0_MODE3 );
-	portOUTPUT_BYTE( usPIT0,0 );
-	portOUTPUT_BYTE( usPIT0,0 );
-}
-
-
-/*lint +e950 */
-
diff --git a/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/portmacro.h b/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/portmacro.h
deleted file mode 100755
index 811829d..0000000
--- a/FreeRTOS/Source/portable/oWatcom/16BitDOS/PC/portmacro.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#ifndef PORTMACRO_H
-#define PORTMACRO_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/*-----------------------------------------------------------
- * Port specific definitions.
- *
- * The settings in this file configure FreeRTOS correctly for the
- * given hardware and compiler.
- *
- * These settings should not be altered.
- *-----------------------------------------------------------
- */
-
-/* Type definitions. */
-#define portCHAR		char
-#define portFLOAT		float
-#define portDOUBLE		double
-#define portLONG		long
-#define portSHORT		int
-#define portSTACK_TYPE	uint16_t
-#define portBASE_TYPE	short
-
-typedef portSTACK_TYPE StackType_t;
-typedef short BaseType_t;
-typedef unsigned short UBaseType_t;
-
-
-#if( configUSE_16_BIT_TICKS == 1 )
-	typedef uint16_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffff
-#else
-	typedef uint32_t TickType_t;
-	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
-#endif
-/*-----------------------------------------------------------*/
-
-/* Critical section definitions.  portENTER_CRITICAL() must be defined as a
-macro for portable.h to work properly. */
-void portLOCAL_ENTER_CRITICAL( void );
-#pragma aux portLOCAL_ENTER_CRITICAL = 	"pushf" \
-										"cli";
-#define portENTER_CRITICAL() portLOCAL_ENTER_CRITICAL()
-
-void portEXIT_CRITICAL( void );
-#pragma aux portEXIT_CRITICAL	=		"popf";
-
-void portDISABLE_INTERRUPTS( void );
-#pragma aux portDISABLE_INTERRUPTS =	"cli";
-
-void portENABLE_INTERRUPTS( void );
-#pragma aux portENABLE_INTERRUPTS =		"sti";
-/*-----------------------------------------------------------*/
-
-/* Architecture specifics. */
-#define portSTACK_GROWTH		( -1 )
-#define portSWITCH_INT_NUMBER 	0x80
-#define portYIELD()				__asm{ int portSWITCH_INT_NUMBER }
-#define portDOS_TICK_RATE		( 18.20648 )
-#define portTICK_PERIOD_MS        ( ( TickType_t ) 1000 / configTICK_RATE_HZ )
-#define portTICKS_PER_DOS_TICK	( ( uint16_t ) ( ( ( portDOUBLE ) configTICK_RATE_HZ / portDOS_TICK_RATE ) + 0.5 ) )
-#define portINITIAL_SW			( ( portSTACK_TYPE ) 0x0202 )	/* Start the tasks with interrupts enabled. */
-#define portBYTE_ALIGNMENT		( 2 )
-/*-----------------------------------------------------------*/
-
-/* Compiler specifics. */
-#define portINPUT_BYTE( xAddr )				inp( xAddr )
-#define portOUTPUT_BYTE( xAddr, ucValue )	outp( xAddr, ucValue )
-#define portNOP() __asm{ nop }
-/*-----------------------------------------------------------*/
-
-/* Task function macros as described on the FreeRTOS.org WEB site. */
-#define portTASK_FUNCTION_PROTO( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
-#define portTASK_FUNCTION( vTaskFunction, pvParameters ) void vTaskFunction( void *pvParameters )
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* PORTMACRO_H */
-
diff --git a/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portasm.h b/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portasm.h
deleted file mode 100755
index 587d2f7..0000000
--- a/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portasm.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-typedef void TCB_t;
-extern volatile TCB_t * volatile pxCurrentTCB;
-extern void vTaskSwitchContext( void );
-
-/* 
- * Saves the stack pointer for one task into its TCB, calls 
- * vTaskSwitchContext() to update the TCB being used, then restores the stack 
- * from the new TCB read to run the task. 
- */
-void portSWITCH_CONTEXT( void );
-
-/*
- * Load the stack pointer from the TCB of the task which is going to be first
- * to execute.  Then force an IRET so the registers and IP are popped off the
- * stack.
- */
-void portFIRST_CONTEXT( void );
-
-/* There are slightly different versions depending on whether you are building
-to include debugger information.  If debugger information is used then there
-are a couple of extra bytes left of the ISR stack (presumably for use by the
-debugger).  The true stack pointer is then stored in the bp register.  We add
-2 to the stack pointer to remove the extra bytes before we restore our context. */
-
-#ifdef DEBUG_BUILD
-
-	#pragma aux portSWITCH_CONTEXT =	"mov	ax, seg pxCurrentTCB"														\
-										"mov	ds, ax"																		\
-										"les	bx, pxCurrentTCB"			/* Save the stack pointer into the TCB. */		\
-										"mov	es:0x2[ bx ], ss"															\
-										"mov	es:[ bx ], sp"																\
-										"call	vTaskSwitchContext"			/* Perform the switch. */						\
-										"mov	ax, seg pxCurrentTCB"		/* Restore the stack pointer from the TCB. */	\
-										"mov	ds, ax"																		\
-										"les	bx, dword ptr pxCurrentTCB"													\
-										"mov	ss, es:[ bx + 2 ]"															\
-										"mov	sp, es:[ bx ]"																\
-										"mov	bp, sp"						/* Prepair the bp register for the restoration of the SP in the compiler generated portion of the ISR */	\
-										"add	bp, 0x0002"
-
-										
-
-	#pragma aux portFIRST_CONTEXT =		"mov	ax, seg pxCurrentTCB"			\
-										"mov	ds, ax"							\
-										"les	bx, dword ptr pxCurrentTCB"		\
-										"mov	ss, es:[ bx + 2 ]"				\
-										"mov	sp, es:[ bx ]"					\
-										"add	sp, 0x0002"						/* Remove the extra bytes that exist in debug builds before restoring the context. */ \
-										"pop	ax"								\
-										"pop	ax"								\
-										"pop	es"								\
-										"pop	ds"								\
-										"popa"									\
-										"iret"									
-#else
-
-	#pragma aux portSWITCH_CONTEXT =	"mov	ax, seg pxCurrentTCB"														\
-										"mov	ds, ax"																		\
-										"les	bx, pxCurrentTCB"			/* Save the stack pointer into the TCB. */		\
-										"mov	es:0x2[ bx ], ss"															\
-										"mov	es:[ bx ], sp"																\
-										"call	vTaskSwitchContext"			/* Perform the switch. */						\
-										"mov	ax, seg pxCurrentTCB"		/* Restore the stack pointer from the TCB. */	\
-										"mov	ds, ax"																		\
-										"les	bx, dword ptr pxCurrentTCB"													\
-										"mov	ss, es:[ bx + 2 ]"															\
-										"mov	sp, es:[ bx ]"
-										
-
-	#pragma aux portFIRST_CONTEXT =		"mov	ax, seg pxCurrentTCB"			\
-										"mov	ds, ax"							\
-										"les	bx, dword ptr pxCurrentTCB"		\
-										"mov	ss, es:[ bx + 2 ]"				\
-										"mov	sp, es:[ bx ]"					\
-										"pop	ax"								\
-										"pop	ax"								\
-										"pop	es"								\
-										"pop	ds"								\
-										"popa"									\
-										"iret"									
-#endif
-
-
diff --git a/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portcomn.c b/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portcomn.c
deleted file mode 100755
index d51e3ae..0000000
--- a/FreeRTOS/Source/portable/oWatcom/16BitDOS/common/portcomn.c
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/*
-Changes from V1.00:
-	
-	+ pxPortInitialiseStack() now initialises the stack of new tasks to the 
-	  same format used by the compiler.  This allows the compiler generated
-	  interrupt mechanism to be used for context switches.
-
-Changes from V2.4.2:
-
-	+ pvPortMalloc and vPortFree have been removed.  The projects now use
-	  the definitions from the source/portable/MemMang directory.
-
-Changes from V2.6.1:
-
-	+ usPortCheckFreeStackSpace() has been moved to tasks.c.
-*/
-
-	
-
-#include 
-#include "FreeRTOS.h"
-
-/*-----------------------------------------------------------*/
-
-/* See header file for description. */
-StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
-{
-StackType_t DS_Reg = 0, *pxOriginalSP;
-
-	/* Place a few bytes of known values on the bottom of the stack. 
-	This is just useful for debugging. */
-
-	*pxTopOfStack = 0x1111;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x2222;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x3333;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x4444;
-	pxTopOfStack--;
-	*pxTopOfStack = 0x5555;
-	pxTopOfStack--;
-
-
-	/*lint -e950 -e611 -e923 Lint doesn't like this much - but nothing I can do about it. */
-
-	/* We are going to start the scheduler using a return from interrupt
-	instruction to load the program counter, so first there would be the
-	status register and interrupt return address.  We make this the start 
-	of the task. */
-	*pxTopOfStack = portINITIAL_SW; 
-	pxTopOfStack--;
-	*pxTopOfStack = FP_SEG( pxCode );
-	pxTopOfStack--;
-	*pxTopOfStack = FP_OFF( pxCode );
-	pxTopOfStack--;
-
-	/* We are going to setup the stack for the new task to look like
-	the stack frame was setup by a compiler generated ISR.  We need to know
-	the address of the existing stack top to place in the SP register within
-	the stack frame.  pxOriginalSP holds SP before (simulated) pusha was 
-	called. */
-	pxOriginalSP = pxTopOfStack;
-
-	/* The remaining registers would be pushed on the stack by our context 
-	switch function.  These are loaded with values simply to make debugging
-	easier. */
-	*pxTopOfStack = FP_OFF( pvParameters );		/* AX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xCCCC;	/* CX */
-	pxTopOfStack--;
-	*pxTopOfStack = FP_SEG( pvParameters );		/* DX */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BX */
-	pxTopOfStack--;
-	*pxTopOfStack = FP_OFF( pxOriginalSP );		/* SP */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xBBBB;	/* BP */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0x0123;	/* SI */
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xDDDD;	/* DI */
-
-	/* We need the true data segment. */
-	__asm{	MOV DS_Reg, DS };
-
-	pxTopOfStack--;
-	*pxTopOfStack = DS_Reg;	/* DS */
-
-	pxTopOfStack--;
-	*pxTopOfStack = ( StackType_t ) 0xEEEE;	/* ES */
-
-	/* The AX register is pushed again twice - don't know why. */
-	pxTopOfStack--;
-	*pxTopOfStack = FP_OFF( pvParameters );		/* AX */
-	pxTopOfStack--;
-	*pxTopOfStack = FP_OFF( pvParameters );		/* AX */
-
-
-	#ifdef DEBUG_BUILD
-		/* The compiler adds space to each ISR stack if building to
-		include debug information.  Presumably this is used by the
-		debugger - we don't need to initialise it to anything just
-		make sure it is there. */
-		pxTopOfStack--;
-	#endif
-
-	/*lint +e950 +e611 +e923 */
-
-	return pxTopOfStack;
-}
-/*-----------------------------------------------------------*/
-
-
diff --git a/FreeRTOS/Source/portable/readme.txt b/FreeRTOS/Source/portable/readme.txt
deleted file mode 100755
index b68d2d5..0000000
--- a/FreeRTOS/Source/portable/readme.txt
+++ /dev/null
@@ -1,20 +0,0 @@
-Each real time kernel port consists of three files that contain the core kernel
-components and are common to every port, and one or more files that are
-specific to a particular microcontroller and/or compiler.
-
-
-+ The FreeRTOS/Source/Portable/MemMang directory contains the five sample
-memory allocators as described on the http://www.FreeRTOS.org WEB site.
-
-+ The other directories each contain files specific to a particular
-microcontroller or compiler, where the directory name denotes the compiler
-specific files the directory contains.
-
-
-
-For example, if you are interested in the [compiler] port for the [architecture]
-microcontroller, then the port specific files are contained in
-FreeRTOS/Source/Portable/[compiler]/[architecture] directory.  If this is the
-only port you are interested in then all the other directories can be
-ignored.
-
diff --git a/FreeRTOS/Source/queue.c b/FreeRTOS/Source/queue.c
deleted file mode 100755
index d882bf6..0000000
--- a/FreeRTOS/Source/queue.c
+++ /dev/null
@@ -1,2941 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-#include 
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-
-#if ( configUSE_CO_ROUTINES == 1 )
-	#include "croutine.h"
-#endif
-
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
-because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
-for the header files above, but not in this file, in order to generate the
-correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
-
-
-/* Constants used with the cRxLock and cTxLock structure members. */
-#define queueUNLOCKED					( ( int8_t ) -1 )
-#define queueLOCKED_UNMODIFIED			( ( int8_t ) 0 )
-
-/* When the Queue_t structure is used to represent a base queue its pcHead and
-pcTail members are used as pointers into the queue storage area.  When the
-Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
-not necessary, and the pcHead pointer is set to NULL to indicate that the
-structure instead holds a pointer to the mutex holder (if any).  Map alternative
-names to the pcHead and structure member to ensure the readability of the code
-is maintained.  The QueuePointers_t and SemaphoreData_t types are used to form
-a union as their usage is mutually exclusive dependent on what the queue is
-being used for. */
-#define uxQueueType						pcHead
-#define queueQUEUE_IS_MUTEX				NULL
-
-typedef struct QueuePointers
-{
-	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
-	int8_t *pcReadFrom;				/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
-} QueuePointers_t;
-
-typedef struct SemaphoreData
-{
-	TaskHandle_t xMutexHolder;		 /*< The handle of the task that holds the mutex. */
-	UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
-} SemaphoreData_t;
-
-/* Semaphores do not actually store or copy data, so have an item size of
-zero. */
-#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
-#define queueMUTEX_GIVE_BLOCK_TIME		 ( ( TickType_t ) 0U )
-
-#if( configUSE_PREEMPTION == 0 )
-	/* If the cooperative scheduler is being used then a yield should not be
-	performed just because a higher priority task has been woken. */
-	#define queueYIELD_IF_USING_PREEMPTION()
-#else
-	#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
-#endif
-
-/*
- * Definition of the queue used by the scheduler.
- * Items are queued by copy, not reference.  See the following link for the
- * rationale: https://www.freertos.org/Embedded-RTOS-Queues.html
- */
-typedef struct QueueDefinition 		/* The old naming convention is used to prevent breaking kernel aware debuggers. */
-{
-	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
-	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
-
-	union
-	{
-		QueuePointers_t xQueue;		/*< Data required exclusively when this structure is used as a queue. */
-		SemaphoreData_t xSemaphore; /*< Data required exclusively when this structure is used as a semaphore. */
-	} u;
-
-	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
-	List_t xTasksWaitingToReceive;	/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
-
-	volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
-	UBaseType_t uxLength;			/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
-	UBaseType_t uxItemSize;			/*< The size of each items that the queue will hold. */
-
-	volatile int8_t cRxLock;		/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
-	volatile int8_t cTxLock;		/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
-
-	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-		uint8_t ucStaticallyAllocated;	/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
-	#endif
-
-	#if ( configUSE_QUEUE_SETS == 1 )
-		struct QueueDefinition *pxQueueSetContainer;
-	#endif
-
-	#if ( configUSE_TRACE_FACILITY == 1 )
-		UBaseType_t uxQueueNumber;
-		uint8_t ucQueueType;
-	#endif
-
-} xQUEUE;
-
-/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
-name below to enable the use of older kernel aware debuggers. */
-typedef xQUEUE Queue_t;
-
-/*-----------------------------------------------------------*/
-
-/*
- * The queue registry is just a means for kernel aware debuggers to locate
- * queue structures.  It has no other purpose so is an optional component.
- */
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-	/* The type stored within the queue registry array.  This allows a name
-	to be assigned to each queue making kernel aware debugging a little
-	more user friendly. */
-	typedef struct QUEUE_REGISTRY_ITEM
-	{
-		const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-		QueueHandle_t xHandle;
-	} xQueueRegistryItem;
-
-	/* The old xQueueRegistryItem name is maintained above then typedefed to the
-	new xQueueRegistryItem name below to enable the use of older kernel aware
-	debuggers. */
-	typedef xQueueRegistryItem QueueRegistryItem_t;
-
-	/* The queue registry is simply an array of QueueRegistryItem_t structures.
-	The pcQueueName member of a structure being NULL is indicative of the
-	array position being vacant. */
-	PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
-
-#endif /* configQUEUE_REGISTRY_SIZE */
-
-/*
- * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
- * prevent an ISR from adding or removing items to the queue, but does prevent
- * an ISR from removing tasks from the queue event lists.  If an ISR finds a
- * queue is locked it will instead increment the appropriate queue lock count
- * to indicate that a task may require unblocking.  When the queue in unlocked
- * these lock counts are inspected, and the appropriate action taken.
- */
-static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * Uses a critical section to determine if there is any data in a queue.
- *
- * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
- */
-static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * Uses a critical section to determine if there is any space in a queue.
- *
- * @return pdTRUE if there is no space, otherwise pdFALSE;
- */
-static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * Copies an item into the queue, either at the front of the queue or the
- * back of the queue.
- */
-static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
-
-/*
- * Copies an item out of a queue.
- */
-static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
-
-#if ( configUSE_QUEUE_SETS == 1 )
-	/*
-	 * Checks to see if a queue is a member of a queue set, and if so, notifies
-	 * the queue set that the queue contains data.
-	 */
-	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
-#endif
-
-/*
- * Called after a Queue_t structure has been allocated either statically or
- * dynamically to fill in the structure's members.
- */
-static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
-
-/*
- * Mutexes are a special type of queue.  When a mutex is created, first the
- * queue is created, then prvInitialiseMutex() is called to configure the queue
- * as a mutex.
- */
-#if( configUSE_MUTEXES == 1 )
-	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
-#endif
-
-#if( configUSE_MUTEXES == 1 )
-	/*
-	 * If a task waiting for a mutex causes the mutex holder to inherit a
-	 * priority, but the waiting task times out, then the holder should
-	 * disinherit the priority - but only down to the highest priority of any
-	 * other tasks that are waiting for the same mutex.  This function returns
-	 * that priority.
-	 */
-	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
-#endif
-/*-----------------------------------------------------------*/
-
-/*
- * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
- * accessing the queue event lists.
- */
-#define prvLockQueue( pxQueue )								\
-	taskENTER_CRITICAL();									\
-	{														\
-		if( ( pxQueue )->cRxLock == queueUNLOCKED )			\
-		{													\
-			( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;	\
-		}													\
-		if( ( pxQueue )->cTxLock == queueUNLOCKED )			\
-		{													\
-			( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;	\
-		}													\
-	}														\
-	taskEXIT_CRITICAL()
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
-{
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-
-	taskENTER_CRITICAL();
-	{
-		pxQueue->u.xQueue.pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
-		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
-		pxQueue->pcWriteTo = pxQueue->pcHead;
-		pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - 1U ) * pxQueue->uxItemSize ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
-		pxQueue->cRxLock = queueUNLOCKED;
-		pxQueue->cTxLock = queueUNLOCKED;
-
-		if( xNewQueue == pdFALSE )
-		{
-			/* If there are tasks blocked waiting to read from the queue, then
-			the tasks will remain blocked as after this function exits the queue
-			will still be empty.  If there are tasks blocked waiting to write to
-			the queue, then one should be unblocked as after this function exits
-			it will be possible to write to it. */
-			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-			{
-				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-				{
-					queueYIELD_IF_USING_PREEMPTION();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			/* Ensure the event queues start in the correct state. */
-			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
-			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	/* A value is returned for calling semantic consistency with previous
-	versions. */
-	return pdPASS;
-}
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
-	{
-	Queue_t *pxNewQueue;
-
-		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
-
-		/* The StaticQueue_t structure and the queue storage area must be
-		supplied. */
-		configASSERT( pxStaticQueue != NULL );
-
-		/* A queue storage area should be provided if the item size is not 0, and
-		should not be provided if the item size is 0. */
-		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
-		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
-
-		#if( configASSERT_DEFINED == 1 )
-		{
-			/* Sanity check that the size of the structure used to declare a
-			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
-			the real queue and semaphore structures. */
-			volatile size_t xSize = sizeof( StaticQueue_t );
-			configASSERT( xSize == sizeof( Queue_t ) );
-			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
-		}
-		#endif /* configASSERT_DEFINED */
-
-		/* The address of a statically allocated queue was passed in, use it.
-		The address of a statically allocated storage area was also passed in
-		but is already set. */
-		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
-
-		if( pxNewQueue != NULL )
-		{
-			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-			{
-				/* Queues can be allocated wither statically or dynamically, so
-				note this queue was allocated statically in case the queue is
-				later deleted. */
-				pxNewQueue->ucStaticallyAllocated = pdTRUE;
-			}
-			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-
-			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
-		}
-		else
-		{
-			traceQUEUE_CREATE_FAILED( ucQueueType );
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return pxNewQueue;
-	}
-
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
-	{
-	Queue_t *pxNewQueue;
-	size_t xQueueSizeInBytes;
-	uint8_t *pucQueueStorage;
-
-		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
-
-		if( uxItemSize == ( UBaseType_t ) 0 )
-		{
-			/* There is not going to be a queue storage area. */
-			xQueueSizeInBytes = ( size_t ) 0;
-		}
-		else
-		{
-			/* Allocate enough space to hold the maximum number of items that
-			can be in the queue at any time. */
-			xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-		}
-
-		/* Allocate the queue and storage area.  Justification for MISRA
-		deviation as follows:  pvPortMalloc() always ensures returned memory
-		blocks are aligned per the requirements of the MCU stack.  In this case
-		pvPortMalloc() must return a pointer that is guaranteed to meet the
-		alignment requirements of the Queue_t structure - which in this case
-		is an int8_t *.  Therefore, whenever the stack alignment requirements
-		are greater than or equal to the pointer to char requirements the cast
-		is safe.  In other cases alignment requirements are not strict (one or
-		two bytes). */
-		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes ); /*lint !e9087 !e9079 see comment above. */
-
-		if( pxNewQueue != NULL )
-		{
-			/* Jump past the queue structure to find the location of the queue
-			storage area. */
-			pucQueueStorage = ( uint8_t * ) pxNewQueue;
-			pucQueueStorage += sizeof( Queue_t ); /*lint !e9016 Pointer arithmetic allowed on char types, especially when it assists conveying intent. */
-
-			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-			{
-				/* Queues can be created either statically or dynamically, so
-				note this task was created dynamically in case it is later
-				deleted. */
-				pxNewQueue->ucStaticallyAllocated = pdFALSE;
-			}
-			#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
-		}
-		else
-		{
-			traceQUEUE_CREATE_FAILED( ucQueueType );
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return pxNewQueue;
-	}
-
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
-{
-	/* Remove compiler warnings about unused parameters should
-	configUSE_TRACE_FACILITY not be set to 1. */
-	( void ) ucQueueType;
-
-	if( uxItemSize == ( UBaseType_t ) 0 )
-	{
-		/* No RAM was allocated for the queue storage area, but PC head cannot
-		be set to NULL because NULL is used as a key to say the queue is used as
-		a mutex.  Therefore just set pcHead to point to the queue as a benign
-		value that is known to be within the memory map. */
-		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
-	}
-	else
-	{
-		/* Set the head to the start of the queue storage area. */
-		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
-	}
-
-	/* Initialise the queue members as described where the queue type is
-	defined. */
-	pxNewQueue->uxLength = uxQueueLength;
-	pxNewQueue->uxItemSize = uxItemSize;
-	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
-
-	#if ( configUSE_TRACE_FACILITY == 1 )
-	{
-		pxNewQueue->ucQueueType = ucQueueType;
-	}
-	#endif /* configUSE_TRACE_FACILITY */
-
-	#if( configUSE_QUEUE_SETS == 1 )
-	{
-		pxNewQueue->pxQueueSetContainer = NULL;
-	}
-	#endif /* configUSE_QUEUE_SETS */
-
-	traceQUEUE_CREATE( pxNewQueue );
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_MUTEXES == 1 )
-
-	static void prvInitialiseMutex( Queue_t *pxNewQueue )
-	{
-		if( pxNewQueue != NULL )
-		{
-			/* The queue create function will set all the queue structure members
-			correctly for a generic queue, but this function is creating a
-			mutex.  Overwrite those members that need to be set differently -
-			in particular the information required for priority inheritance. */
-			pxNewQueue->u.xSemaphore.xMutexHolder = NULL;
-			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
-
-			/* In case this is a recursive mutex. */
-			pxNewQueue->u.xSemaphore.uxRecursiveCallCount = 0;
-
-			traceCREATE_MUTEX( pxNewQueue );
-
-			/* Start with the semaphore in the expected state. */
-			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
-		}
-		else
-		{
-			traceCREATE_MUTEX_FAILED();
-		}
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
-	{
-	QueueHandle_t xNewQueue;
-	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
-
-		xNewQueue = xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
-		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
-
-		return xNewQueue;
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
-	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
-	{
-	QueueHandle_t xNewQueue;
-	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
-
-		/* Prevent compiler warnings about unused parameters if
-		configUSE_TRACE_FACILITY does not equal 1. */
-		( void ) ucQueueType;
-
-		xNewQueue = xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
-		prvInitialiseMutex( ( Queue_t * ) xNewQueue );
-
-		return xNewQueue;
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
-
-	TaskHandle_t xQueueGetMutexHolder( QueueHandle_t xSemaphore )
-	{
-	TaskHandle_t pxReturn;
-	Queue_t * const pxSemaphore = ( Queue_t * ) xSemaphore;
-
-		/* This function is called by xSemaphoreGetMutexHolder(), and should not
-		be called directly.  Note:  This is a good way of determining if the
-		calling task is the mutex holder, but not a good way of determining the
-		identity of the mutex holder, as the holder may change between the
-		following critical section exiting and the function returning. */
-		taskENTER_CRITICAL();
-		{
-			if( pxSemaphore->uxQueueType == queueQUEUE_IS_MUTEX )
-			{
-				pxReturn = pxSemaphore->u.xSemaphore.xMutexHolder;
-			}
-			else
-			{
-				pxReturn = NULL;
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		return pxReturn;
-	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
-
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
-
-	TaskHandle_t xQueueGetMutexHolderFromISR( QueueHandle_t xSemaphore )
-	{
-	TaskHandle_t pxReturn;
-
-		configASSERT( xSemaphore );
-
-		/* Mutexes cannot be used in interrupt service routines, so the mutex
-		holder should not change in an ISR, and therefore a critical section is
-		not required here. */
-		if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
-		{
-			pxReturn = ( ( Queue_t * ) xSemaphore )->u.xSemaphore.xMutexHolder;
-		}
-		else
-		{
-			pxReturn = NULL;
-		}
-
-		return pxReturn;
-	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
-
-#endif
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-
-	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
-	{
-	BaseType_t xReturn;
-	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
-
-		configASSERT( pxMutex );
-
-		/* If this is the task that holds the mutex then xMutexHolder will not
-		change outside of this task.  If this task does not hold the mutex then
-		pxMutexHolder can never coincidentally equal the tasks handle, and as
-		this is the only condition we are interested in it does not matter if
-		pxMutexHolder is accessed simultaneously by another task.  Therefore no
-		mutual exclusion is required to test the pxMutexHolder variable. */
-		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
-		{
-			traceGIVE_MUTEX_RECURSIVE( pxMutex );
-
-			/* uxRecursiveCallCount cannot be zero if xMutexHolder is equal to
-			the task handle, therefore no underflow check is required.  Also,
-			uxRecursiveCallCount is only modified by the mutex holder, and as
-			there can only be one, no mutual exclusion is required to modify the
-			uxRecursiveCallCount member. */
-			( pxMutex->u.xSemaphore.uxRecursiveCallCount )--;
-
-			/* Has the recursive call count unwound to 0? */
-			if( pxMutex->u.xSemaphore.uxRecursiveCallCount == ( UBaseType_t ) 0 )
-			{
-				/* Return the mutex.  This will automatically unblock any other
-				task that might be waiting to access the mutex. */
-				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			xReturn = pdPASS;
-		}
-		else
-		{
-			/* The mutex cannot be given because the calling task is not the
-			holder. */
-			xReturn = pdFAIL;
-
-			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_RECURSIVE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_RECURSIVE_MUTEXES == 1 )
-
-	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
-	{
-	BaseType_t xReturn;
-	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
-
-		configASSERT( pxMutex );
-
-		/* Comments regarding mutual exclusion as per those within
-		xQueueGiveMutexRecursive(). */
-
-		traceTAKE_MUTEX_RECURSIVE( pxMutex );
-
-		if( pxMutex->u.xSemaphore.xMutexHolder == xTaskGetCurrentTaskHandle() )
-		{
-			( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
-			xReturn = pdPASS;
-		}
-		else
-		{
-			xReturn = xQueueSemaphoreTake( pxMutex, xTicksToWait );
-
-			/* pdPASS will only be returned if the mutex was successfully
-			obtained.  The calling task may have entered the Blocked state
-			before reaching here. */
-			if( xReturn != pdFAIL )
-			{
-				( pxMutex->u.xSemaphore.uxRecursiveCallCount )++;
-			}
-			else
-			{
-				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
-			}
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_RECURSIVE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
-	QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
-	{
-	QueueHandle_t xHandle;
-
-		configASSERT( uxMaxCount != 0 );
-		configASSERT( uxInitialCount <= uxMaxCount );
-
-		xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
-
-		if( xHandle != NULL )
-		{
-			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
-
-			traceCREATE_COUNTING_SEMAPHORE();
-		}
-		else
-		{
-			traceCREATE_COUNTING_SEMAPHORE_FAILED();
-		}
-
-		return xHandle;
-	}
-
-#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-	QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
-	{
-	QueueHandle_t xHandle;
-
-		configASSERT( uxMaxCount != 0 );
-		configASSERT( uxInitialCount <= uxMaxCount );
-
-		xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
-
-		if( xHandle != NULL )
-		{
-			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
-
-			traceCREATE_COUNTING_SEMAPHORE();
-		}
-		else
-		{
-			traceCREATE_COUNTING_SEMAPHORE_FAILED();
-		}
-
-		return xHandle;
-	}
-
-#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
-{
-BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
-TimeOut_t xTimeOut;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
-	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-	{
-		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-	}
-	#endif
-
-
-	/*lint -save -e904 This function relaxes the coding standard somewhat to
-	allow return statements within the function itself.  This is done in the
-	interest of execution time efficiency. */
-	for( ;; )
-	{
-		taskENTER_CRITICAL();
-		{
-			/* Is there room on the queue now?  The running task must be the
-			highest priority task wanting to access the queue.  If the head item
-			in the queue is to be overwritten then it does not matter if the
-			queue is full. */
-			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
-			{
-				traceQUEUE_SEND( pxQueue );
-
-				#if ( configUSE_QUEUE_SETS == 1 )
-				{
-				UBaseType_t uxPreviousMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
-
-					if( pxQueue->pxQueueSetContainer != NULL )
-					{
-						if( ( xCopyPosition == queueOVERWRITE ) && ( uxPreviousMessagesWaiting != ( UBaseType_t ) 0 ) )
-						{
-							/* Do not notify the queue set as an existing item
-							was overwritten in the queue so the number of items
-							in the queue has not changed. */
-							mtCOVERAGE_TEST_MARKER();
-						}
-						else if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
-						{
-							/* The queue is a member of a queue set, and posting
-							to the queue set caused a higher priority task to
-							unblock. A context switch is required. */
-							queueYIELD_IF_USING_PREEMPTION();
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						/* If there was a task waiting for data to arrive on the
-						queue then unblock it now. */
-						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-						{
-							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-							{
-								/* The unblocked task has a priority higher than
-								our own so yield immediately.  Yes it is ok to
-								do this from within the critical section - the
-								kernel takes care of that. */
-								queueYIELD_IF_USING_PREEMPTION();
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else if( xYieldRequired != pdFALSE )
-						{
-							/* This path is a special case that will only get
-							executed if the task was holding multiple mutexes
-							and the mutexes were given back in an order that is
-							different to that in which they were taken. */
-							queueYIELD_IF_USING_PREEMPTION();
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-				}
-				#else /* configUSE_QUEUE_SETS */
-				{
-					xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
-
-					/* If there was a task waiting for data to arrive on the
-					queue then unblock it now. */
-					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-					{
-						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-						{
-							/* The unblocked task has a priority higher than
-							our own so yield immediately.  Yes it is ok to do
-							this from within the critical section - the kernel
-							takes care of that. */
-							queueYIELD_IF_USING_PREEMPTION();
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else if( xYieldRequired != pdFALSE )
-					{
-						/* This path is a special case that will only get
-						executed if the task was holding multiple mutexes and
-						the mutexes were given back in an order that is
-						different to that in which they were taken. */
-						queueYIELD_IF_USING_PREEMPTION();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				#endif /* configUSE_QUEUE_SETS */
-
-				taskEXIT_CRITICAL();
-				return pdPASS;
-			}
-			else
-			{
-				if( xTicksToWait == ( TickType_t ) 0 )
-				{
-					/* The queue was full and no block time is specified (or
-					the block time has expired) so leave now. */
-					taskEXIT_CRITICAL();
-
-					/* Return to the original privilege level before exiting
-					the function. */
-					traceQUEUE_SEND_FAILED( pxQueue );
-					return errQUEUE_FULL;
-				}
-				else if( xEntryTimeSet == pdFALSE )
-				{
-					/* The queue was full and a block time was specified so
-					configure the timeout structure. */
-					vTaskInternalSetTimeOutState( &xTimeOut );
-					xEntryTimeSet = pdTRUE;
-				}
-				else
-				{
-					/* Entry time was already set. */
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		/* Interrupts and other tasks can send to and receive from the queue
-		now the critical section has been exited. */
-
-		vTaskSuspendAll();
-		prvLockQueue( pxQueue );
-
-		/* Update the timeout state to see if it has expired yet. */
-		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
-		{
-			if( prvIsQueueFull( pxQueue ) != pdFALSE )
-			{
-				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
-				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
-
-				/* Unlocking the queue means queue events can effect the
-				event list.  It is possible that interrupts occurring now
-				remove this task from the event list again - but as the
-				scheduler is suspended the task will go onto the pending
-				ready last instead of the actual ready list. */
-				prvUnlockQueue( pxQueue );
-
-				/* Resuming the scheduler will move tasks from the pending
-				ready list into the ready list - so it is feasible that this
-				task is already in a ready list before it yields - in which
-				case the yield will not cause a context switch unless there
-				is also a higher priority task in the pending ready list. */
-				if( xTaskResumeAll() == pdFALSE )
-				{
-					portYIELD_WITHIN_API();
-				}
-			}
-			else
-			{
-				/* Try again. */
-				prvUnlockQueue( pxQueue );
-				( void ) xTaskResumeAll();
-			}
-		}
-		else
-		{
-			/* The timeout has expired. */
-			prvUnlockQueue( pxQueue );
-			( void ) xTaskResumeAll();
-
-			traceQUEUE_SEND_FAILED( pxQueue );
-			return errQUEUE_FULL;
-		}
-	} /*lint -restore */
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
-{
-BaseType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
-
-	/* RTOS ports that support interrupt nesting have the concept of a maximum
-	system call (or maximum API call) interrupt priority.  Interrupts that are
-	above the maximum system call priority are kept permanently enabled, even
-	when the RTOS kernel is in a critical section, but cannot make any calls to
-	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-	failure if a FreeRTOS API function is called from an interrupt that has been
-	assigned a priority above the configured maximum system call priority.
-	Only FreeRTOS functions that end in FromISR can be called from interrupts
-	that have been assigned a priority at or (logically) below the maximum
-	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
-	safe API to ensure interrupt entry is as fast and as simple as possible.
-	More information (albeit Cortex-M specific) is provided on the following
-	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
-	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-	/* Similar to xQueueGenericSend, except without blocking if there is no room
-	in the queue.  Also don't directly wake a task that was blocked on a queue
-	read, instead return a flag to say whether a context switch is required or
-	not (i.e. has a task with a higher priority than us been woken by this
-	post). */
-	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
-		{
-			const int8_t cTxLock = pxQueue->cTxLock;
-
-			traceQUEUE_SEND_FROM_ISR( pxQueue );
-
-			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
-			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
-			in a task disinheriting a priority and prvCopyDataToQueue() can be
-			called here even though the disinherit function does not check if
-			the scheduler is suspended before accessing the ready lists. */
-			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
-
-			/* The event list is not altered if the queue is locked.  This will
-			be done when the queue is unlocked later. */
-			if( cTxLock == queueUNLOCKED )
-			{
-				#if ( configUSE_QUEUE_SETS == 1 )
-				{
-					if( pxQueue->pxQueueSetContainer != NULL )
-					{
-						if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
-						{
-							/* The queue is a member of a queue set, and posting
-							to the queue set caused a higher priority task to
-							unblock.  A context switch is required. */
-							if( pxHigherPriorityTaskWoken != NULL )
-							{
-								*pxHigherPriorityTaskWoken = pdTRUE;
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-						{
-							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-							{
-								/* The task waiting has a higher priority so
-								record that a context switch is required. */
-								if( pxHigherPriorityTaskWoken != NULL )
-								{
-									*pxHigherPriorityTaskWoken = pdTRUE;
-								}
-								else
-								{
-									mtCOVERAGE_TEST_MARKER();
-								}
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-				}
-				#else /* configUSE_QUEUE_SETS */
-				{
-					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-					{
-						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-						{
-							/* The task waiting has a higher priority so record that a
-							context	switch is required. */
-							if( pxHigherPriorityTaskWoken != NULL )
-							{
-								*pxHigherPriorityTaskWoken = pdTRUE;
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				#endif /* configUSE_QUEUE_SETS */
-			}
-			else
-			{
-				/* Increment the lock count so the task that unlocks the queue
-				knows that data was posted while it was locked. */
-				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
-			}
-
-			xReturn = pdPASS;
-		}
-		else
-		{
-			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
-			xReturn = errQUEUE_FULL;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
-{
-BaseType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = xQueue;
-
-	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
-	item size is 0.  Don't directly wake a task that was blocked on a queue
-	read, instead return a flag to say whether a context switch is required or
-	not (i.e. has a task with a higher priority than us been woken by this
-	post). */
-
-	configASSERT( pxQueue );
-
-	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
-	if the item size is not 0. */
-	configASSERT( pxQueue->uxItemSize == 0 );
-
-	/* Normally a mutex would not be given from an interrupt, especially if
-	there is a mutex holder, as priority inheritance makes no sense for an
-	interrupts, only tasks. */
-	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->u.xSemaphore.xMutexHolder != NULL ) ) );
-
-	/* RTOS ports that support interrupt nesting have the concept of a maximum
-	system call (or maximum API call) interrupt priority.  Interrupts that are
-	above the maximum system call priority are kept permanently enabled, even
-	when the RTOS kernel is in a critical section, but cannot make any calls to
-	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-	failure if a FreeRTOS API function is called from an interrupt that has been
-	assigned a priority above the configured maximum system call priority.
-	Only FreeRTOS functions that end in FromISR can be called from interrupts
-	that have been assigned a priority at or (logically) below the maximum
-	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
-	safe API to ensure interrupt entry is as fast and as simple as possible.
-	More information (albeit Cortex-M specific) is provided on the following
-	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
-	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-		/* When the queue is used to implement a semaphore no data is ever
-		moved through the queue but it is still valid to see if the queue 'has
-		space'. */
-		if( uxMessagesWaiting < pxQueue->uxLength )
-		{
-			const int8_t cTxLock = pxQueue->cTxLock;
-
-			traceQUEUE_SEND_FROM_ISR( pxQueue );
-
-			/* A task can only have an inherited priority if it is a mutex
-			holder - and if there is a mutex holder then the mutex cannot be
-			given from an ISR.  As this is the ISR version of the function it
-			can be assumed there is no mutex holder and no need to determine if
-			priority disinheritance is needed.  Simply increase the count of
-			messages (semaphores) available. */
-			pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
-
-			/* The event list is not altered if the queue is locked.  This will
-			be done when the queue is unlocked later. */
-			if( cTxLock == queueUNLOCKED )
-			{
-				#if ( configUSE_QUEUE_SETS == 1 )
-				{
-					if( pxQueue->pxQueueSetContainer != NULL )
-					{
-						if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
-						{
-							/* The semaphore is a member of a queue set, and
-							posting	to the queue set caused a higher priority
-							task to	unblock.  A context switch is required. */
-							if( pxHigherPriorityTaskWoken != NULL )
-							{
-								*pxHigherPriorityTaskWoken = pdTRUE;
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-						{
-							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-							{
-								/* The task waiting has a higher priority so
-								record that a context switch is required. */
-								if( pxHigherPriorityTaskWoken != NULL )
-								{
-									*pxHigherPriorityTaskWoken = pdTRUE;
-								}
-								else
-								{
-									mtCOVERAGE_TEST_MARKER();
-								}
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-				}
-				#else /* configUSE_QUEUE_SETS */
-				{
-					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-					{
-						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-						{
-							/* The task waiting has a higher priority so record that a
-							context	switch is required. */
-							if( pxHigherPriorityTaskWoken != NULL )
-							{
-								*pxHigherPriorityTaskWoken = pdTRUE;
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				#endif /* configUSE_QUEUE_SETS */
-			}
-			else
-			{
-				/* Increment the lock count so the task that unlocks the queue
-				knows that data was posted while it was locked. */
-				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
-			}
-
-			xReturn = pdPASS;
-		}
-		else
-		{
-			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
-			xReturn = errQUEUE_FULL;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
-{
-BaseType_t xEntryTimeSet = pdFALSE;
-TimeOut_t xTimeOut;
-Queue_t * const pxQueue = xQueue;
-
-	/* Check the pointer is not NULL. */
-	configASSERT( ( pxQueue ) );
-
-	/* The buffer into which data is received can only be NULL if the data size
-	is zero (so no data is copied into the buffer. */
-	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
-
-	/* Cannot block if the scheduler is suspended. */
-	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-	{
-		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-	}
-	#endif
-
-
-	/*lint -save -e904  This function relaxes the coding standard somewhat to
-	allow return statements within the function itself.  This is done in the
-	interest of execution time efficiency. */
-	for( ;; )
-	{
-		taskENTER_CRITICAL();
-		{
-			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-			/* Is there data in the queue now?  To be running the calling task
-			must be the highest priority task wanting to access the queue. */
-			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
-			{
-				/* Data available, remove one item. */
-				prvCopyDataFromQueue( pxQueue, pvBuffer );
-				traceQUEUE_RECEIVE( pxQueue );
-				pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
-
-				/* There is now space in the queue, were any tasks waiting to
-				post to the queue?  If so, unblock the highest priority waiting
-				task. */
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-				{
-					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-					{
-						queueYIELD_IF_USING_PREEMPTION();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				taskEXIT_CRITICAL();
-				return pdPASS;
-			}
-			else
-			{
-				if( xTicksToWait == ( TickType_t ) 0 )
-				{
-					/* The queue was empty and no block time is specified (or
-					the block time has expired) so leave now. */
-					taskEXIT_CRITICAL();
-					traceQUEUE_RECEIVE_FAILED( pxQueue );
-					return errQUEUE_EMPTY;
-				}
-				else if( xEntryTimeSet == pdFALSE )
-				{
-					/* The queue was empty and a block time was specified so
-					configure the timeout structure. */
-					vTaskInternalSetTimeOutState( &xTimeOut );
-					xEntryTimeSet = pdTRUE;
-				}
-				else
-				{
-					/* Entry time was already set. */
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		/* Interrupts and other tasks can send to and receive from the queue
-		now the critical section has been exited. */
-
-		vTaskSuspendAll();
-		prvLockQueue( pxQueue );
-
-		/* Update the timeout state to see if it has expired yet. */
-		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
-		{
-			/* The timeout has not expired.  If the queue is still empty place
-			the task on the list of tasks waiting to receive from the queue. */
-			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-			{
-				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
-				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
-				prvUnlockQueue( pxQueue );
-				if( xTaskResumeAll() == pdFALSE )
-				{
-					portYIELD_WITHIN_API();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				/* The queue contains data again.  Loop back to try and read the
-				data. */
-				prvUnlockQueue( pxQueue );
-				( void ) xTaskResumeAll();
-			}
-		}
-		else
-		{
-			/* Timed out.  If there is no data in the queue exit, otherwise loop
-			back and attempt to read the data. */
-			prvUnlockQueue( pxQueue );
-			( void ) xTaskResumeAll();
-
-			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-			{
-				traceQUEUE_RECEIVE_FAILED( pxQueue );
-				return errQUEUE_EMPTY;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-	} /*lint -restore */
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueSemaphoreTake( QueueHandle_t xQueue, TickType_t xTicksToWait )
-{
-BaseType_t xEntryTimeSet = pdFALSE;
-TimeOut_t xTimeOut;
-Queue_t * const pxQueue = xQueue;
-
-#if( configUSE_MUTEXES == 1 )
-	BaseType_t xInheritanceOccurred = pdFALSE;
-#endif
-
-	/* Check the queue pointer is not NULL. */
-	configASSERT( ( pxQueue ) );
-
-	/* Check this really is a semaphore, in which case the item size will be
-	0. */
-	configASSERT( pxQueue->uxItemSize == 0 );
-
-	/* Cannot block if the scheduler is suspended. */
-	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-	{
-		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-	}
-	#endif
-
-
-	/*lint -save -e904 This function relaxes the coding standard somewhat to allow return
-	statements within the function itself.  This is done in the interest
-	of execution time efficiency. */
-	for( ;; )
-	{
-		taskENTER_CRITICAL();
-		{
-			/* Semaphores are queues with an item size of 0, and where the
-			number of messages in the queue is the semaphore's count value. */
-			const UBaseType_t uxSemaphoreCount = pxQueue->uxMessagesWaiting;
-
-			/* Is there data in the queue now?  To be running the calling task
-			must be the highest priority task wanting to access the queue. */
-			if( uxSemaphoreCount > ( UBaseType_t ) 0 )
-			{
-				traceQUEUE_RECEIVE( pxQueue );
-
-				/* Semaphores are queues with a data size of zero and where the
-				messages waiting is the semaphore's count.  Reduce the count. */
-				pxQueue->uxMessagesWaiting = uxSemaphoreCount - ( UBaseType_t ) 1;
-
-				#if ( configUSE_MUTEXES == 1 )
-				{
-					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
-					{
-						/* Record the information required to implement
-						priority inheritance should it become necessary. */
-						pxQueue->u.xSemaphore.xMutexHolder = pvTaskIncrementMutexHeldCount();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				#endif /* configUSE_MUTEXES */
-
-				/* Check to see if other tasks are blocked waiting to give the
-				semaphore, and if so, unblock the highest priority such task. */
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-				{
-					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-					{
-						queueYIELD_IF_USING_PREEMPTION();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				taskEXIT_CRITICAL();
-				return pdPASS;
-			}
-			else
-			{
-				if( xTicksToWait == ( TickType_t ) 0 )
-				{
-					/* For inheritance to have occurred there must have been an
-					initial timeout, and an adjusted timeout cannot become 0, as
-					if it were 0 the function would have exited. */
-					#if( configUSE_MUTEXES == 1 )
-					{
-						configASSERT( xInheritanceOccurred == pdFALSE );
-					}
-					#endif /* configUSE_MUTEXES */
-
-					/* The semaphore count was 0 and no block time is specified
-					(or the block time has expired) so exit now. */
-					taskEXIT_CRITICAL();
-					traceQUEUE_RECEIVE_FAILED( pxQueue );
-					return errQUEUE_EMPTY;
-				}
-				else if( xEntryTimeSet == pdFALSE )
-				{
-					/* The semaphore count was 0 and a block time was specified
-					so configure the timeout structure ready to block. */
-					vTaskInternalSetTimeOutState( &xTimeOut );
-					xEntryTimeSet = pdTRUE;
-				}
-				else
-				{
-					/* Entry time was already set. */
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		/* Interrupts and other tasks can give to and take from the semaphore
-		now the critical section has been exited. */
-
-		vTaskSuspendAll();
-		prvLockQueue( pxQueue );
-
-		/* Update the timeout state to see if it has expired yet. */
-		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
-		{
-			/* A block time is specified and not expired.  If the semaphore
-			count is 0 then enter the Blocked state to wait for a semaphore to
-			become available.  As semaphores are implemented with queues the
-			queue being empty is equivalent to the semaphore count being 0. */
-			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-			{
-				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
-
-				#if ( configUSE_MUTEXES == 1 )
-				{
-					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
-					{
-						taskENTER_CRITICAL();
-						{
-							xInheritanceOccurred = xTaskPriorityInherit( pxQueue->u.xSemaphore.xMutexHolder );
-						}
-						taskEXIT_CRITICAL();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				#endif
-
-				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
-				prvUnlockQueue( pxQueue );
-				if( xTaskResumeAll() == pdFALSE )
-				{
-					portYIELD_WITHIN_API();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				/* There was no timeout and the semaphore count was not 0, so
-				attempt to take the semaphore again. */
-				prvUnlockQueue( pxQueue );
-				( void ) xTaskResumeAll();
-			}
-		}
-		else
-		{
-			/* Timed out. */
-			prvUnlockQueue( pxQueue );
-			( void ) xTaskResumeAll();
-
-			/* If the semaphore count is 0 exit now as the timeout has
-			expired.  Otherwise return to attempt to take the semaphore that is
-			known to be available.  As semaphores are implemented by queues the
-			queue being empty is equivalent to the semaphore count being 0. */
-			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-			{
-				#if ( configUSE_MUTEXES == 1 )
-				{
-					/* xInheritanceOccurred could only have be set if
-					pxQueue->uxQueueType == queueQUEUE_IS_MUTEX so no need to
-					test the mutex type again to check it is actually a mutex. */
-					if( xInheritanceOccurred != pdFALSE )
-					{
-						taskENTER_CRITICAL();
-						{
-							UBaseType_t uxHighestWaitingPriority;
-
-							/* This task blocking on the mutex caused another
-							task to inherit this task's priority.  Now this task
-							has timed out the priority should be disinherited
-							again, but only as low as the next highest priority
-							task that is waiting for the same mutex. */
-							uxHighestWaitingPriority = prvGetDisinheritPriorityAfterTimeout( pxQueue );
-							vTaskPriorityDisinheritAfterTimeout( pxQueue->u.xSemaphore.xMutexHolder, uxHighestWaitingPriority );
-						}
-						taskEXIT_CRITICAL();
-					}
-				}
-				#endif /* configUSE_MUTEXES */
-
-				traceQUEUE_RECEIVE_FAILED( pxQueue );
-				return errQUEUE_EMPTY;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-	} /*lint -restore */
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueuePeek( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait )
-{
-BaseType_t xEntryTimeSet = pdFALSE;
-TimeOut_t xTimeOut;
-int8_t *pcOriginalReadPosition;
-Queue_t * const pxQueue = xQueue;
-
-	/* Check the pointer is not NULL. */
-	configASSERT( ( pxQueue ) );
-
-	/* The buffer into which data is received can only be NULL if the data size
-	is zero (so no data is copied into the buffer. */
-	configASSERT( !( ( ( pvBuffer ) == NULL ) && ( ( pxQueue )->uxItemSize != ( UBaseType_t ) 0U ) ) );
-
-	/* Cannot block if the scheduler is suspended. */
-	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-	{
-		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
-	}
-	#endif
-
-
-	/*lint -save -e904  This function relaxes the coding standard somewhat to
-	allow return statements within the function itself.  This is done in the
-	interest of execution time efficiency. */
-	for( ;; )
-	{
-		taskENTER_CRITICAL();
-		{
-			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-			/* Is there data in the queue now?  To be running the calling task
-			must be the highest priority task wanting to access the queue. */
-			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
-			{
-				/* Remember the read position so it can be reset after the data
-				is read from the queue as this function is only peeking the
-				data, not removing it. */
-				pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
-
-				prvCopyDataFromQueue( pxQueue, pvBuffer );
-				traceQUEUE_PEEK( pxQueue );
-
-				/* The data is not being removed, so reset the read pointer. */
-				pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
-
-				/* The data is being left in the queue, so see if there are
-				any other tasks waiting for the data. */
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-				{
-					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-					{
-						/* The task waiting has a higher priority than this task. */
-						queueYIELD_IF_USING_PREEMPTION();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				taskEXIT_CRITICAL();
-				return pdPASS;
-			}
-			else
-			{
-				if( xTicksToWait == ( TickType_t ) 0 )
-				{
-					/* The queue was empty and no block time is specified (or
-					the block time has expired) so leave now. */
-					taskEXIT_CRITICAL();
-					traceQUEUE_PEEK_FAILED( pxQueue );
-					return errQUEUE_EMPTY;
-				}
-				else if( xEntryTimeSet == pdFALSE )
-				{
-					/* The queue was empty and a block time was specified so
-					configure the timeout structure ready to enter the blocked
-					state. */
-					vTaskInternalSetTimeOutState( &xTimeOut );
-					xEntryTimeSet = pdTRUE;
-				}
-				else
-				{
-					/* Entry time was already set. */
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		/* Interrupts and other tasks can send to and receive from the queue
-		now the critical section has been exited. */
-
-		vTaskSuspendAll();
-		prvLockQueue( pxQueue );
-
-		/* Update the timeout state to see if it has expired yet. */
-		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
-		{
-			/* Timeout has not expired yet, check to see if there is data in the
-			queue now, and if not enter the Blocked state to wait for data. */
-			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-			{
-				traceBLOCKING_ON_QUEUE_PEEK( pxQueue );
-				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
-				prvUnlockQueue( pxQueue );
-				if( xTaskResumeAll() == pdFALSE )
-				{
-					portYIELD_WITHIN_API();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				/* There is data in the queue now, so don't enter the blocked
-				state, instead return to try and obtain the data. */
-				prvUnlockQueue( pxQueue );
-				( void ) xTaskResumeAll();
-			}
-		}
-		else
-		{
-			/* The timeout has expired.  If there is still no data in the queue
-			exit, otherwise go back and try to read the data again. */
-			prvUnlockQueue( pxQueue );
-			( void ) xTaskResumeAll();
-
-			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
-			{
-				traceQUEUE_PEEK_FAILED( pxQueue );
-				return errQUEUE_EMPTY;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-	} /*lint -restore */
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
-{
-BaseType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-
-	/* RTOS ports that support interrupt nesting have the concept of a maximum
-	system call (or maximum API call) interrupt priority.  Interrupts that are
-	above the maximum system call priority are kept permanently enabled, even
-	when the RTOS kernel is in a critical section, but cannot make any calls to
-	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-	failure if a FreeRTOS API function is called from an interrupt that has been
-	assigned a priority above the configured maximum system call priority.
-	Only FreeRTOS functions that end in FromISR can be called from interrupts
-	that have been assigned a priority at or (logically) below the maximum
-	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
-	safe API to ensure interrupt entry is as fast and as simple as possible.
-	More information (albeit Cortex-M specific) is provided on the following
-	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
-	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-		/* Cannot block in an ISR, so check there is data available. */
-		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
-		{
-			const int8_t cRxLock = pxQueue->cRxLock;
-
-			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
-
-			prvCopyDataFromQueue( pxQueue, pvBuffer );
-			pxQueue->uxMessagesWaiting = uxMessagesWaiting - ( UBaseType_t ) 1;
-
-			/* If the queue is locked the event list will not be modified.
-			Instead update the lock count so the task that unlocks the queue
-			will know that an ISR has removed data while the queue was
-			locked. */
-			if( cRxLock == queueUNLOCKED )
-			{
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-				{
-					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-					{
-						/* The task waiting has a higher priority than us so
-						force a context switch. */
-						if( pxHigherPriorityTaskWoken != NULL )
-						{
-							*pxHigherPriorityTaskWoken = pdTRUE;
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				/* Increment the lock count so the task that unlocks the queue
-				knows that data was removed while it was locked. */
-				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
-			}
-
-			xReturn = pdPASS;
-		}
-		else
-		{
-			xReturn = pdFAIL;
-			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
-{
-BaseType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-int8_t *pcOriginalReadPosition;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
-	configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
-
-	/* RTOS ports that support interrupt nesting have the concept of a maximum
-	system call (or maximum API call) interrupt priority.  Interrupts that are
-	above the maximum system call priority are kept permanently enabled, even
-	when the RTOS kernel is in a critical section, but cannot make any calls to
-	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-	failure if a FreeRTOS API function is called from an interrupt that has been
-	assigned a priority above the configured maximum system call priority.
-	Only FreeRTOS functions that end in FromISR can be called from interrupts
-	that have been assigned a priority at or (logically) below the maximum
-	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
-	safe API to ensure interrupt entry is as fast and as simple as possible.
-	More information (albeit Cortex-M specific) is provided on the following
-	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
-	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		/* Cannot block in an ISR, so check there is data available. */
-		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
-		{
-			traceQUEUE_PEEK_FROM_ISR( pxQueue );
-
-			/* Remember the read position so it can be reset as nothing is
-			actually being removed from the queue. */
-			pcOriginalReadPosition = pxQueue->u.xQueue.pcReadFrom;
-			prvCopyDataFromQueue( pxQueue, pvBuffer );
-			pxQueue->u.xQueue.pcReadFrom = pcOriginalReadPosition;
-
-			xReturn = pdPASS;
-		}
-		else
-		{
-			xReturn = pdFAIL;
-			traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
-{
-UBaseType_t uxReturn;
-
-	configASSERT( xQueue );
-
-	taskENTER_CRITICAL();
-	{
-		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
-	}
-	taskEXIT_CRITICAL();
-
-	return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
-{
-UBaseType_t uxReturn;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-
-	taskENTER_CRITICAL();
-	{
-		uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
-	}
-	taskEXIT_CRITICAL();
-
-	return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
-{
-UBaseType_t uxReturn;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	uxReturn = pxQueue->uxMessagesWaiting;
-
-	return uxReturn;
-} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
-/*-----------------------------------------------------------*/
-
-void vQueueDelete( QueueHandle_t xQueue )
-{
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	traceQUEUE_DELETE( pxQueue );
-
-	#if ( configQUEUE_REGISTRY_SIZE > 0 )
-	{
-		vQueueUnregisterQueue( pxQueue );
-	}
-	#endif
-
-	#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
-	{
-		/* The queue can only have been allocated dynamically - free it
-		again. */
-		vPortFree( pxQueue );
-	}
-	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-	{
-		/* The queue could have been allocated statically or dynamically, so
-		check before attempting to free the memory. */
-		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
-		{
-			vPortFree( pxQueue );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#else
-	{
-		/* The queue must have been statically allocated, so is not going to be
-		deleted.  Avoid compiler warnings about the unused parameter. */
-		( void ) pxQueue;
-	}
-	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
-	{
-		return ( ( Queue_t * ) xQueue )->uxQueueNumber;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
-	{
-		( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
-	{
-		return ( ( Queue_t * ) xQueue )->ucQueueType;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if( configUSE_MUTEXES == 1 )
-
-	static UBaseType_t prvGetDisinheritPriorityAfterTimeout( const Queue_t * const pxQueue )
-	{
-	UBaseType_t uxHighestPriorityOfWaitingTasks;
-
-		/* If a task waiting for a mutex causes the mutex holder to inherit a
-		priority, but the waiting task times out, then the holder should
-		disinherit the priority - but only down to the highest priority of any
-		other tasks that are waiting for the same mutex.  For this purpose,
-		return the priority of the highest priority task that is waiting for the
-		mutex. */
-		if( listCURRENT_LIST_LENGTH( &( pxQueue->xTasksWaitingToReceive ) ) > 0U )
-		{
-			uxHighestPriorityOfWaitingTasks = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) listGET_ITEM_VALUE_OF_HEAD_ENTRY( &( pxQueue->xTasksWaitingToReceive ) );
-		}
-		else
-		{
-			uxHighestPriorityOfWaitingTasks = tskIDLE_PRIORITY;
-		}
-
-		return uxHighestPriorityOfWaitingTasks;
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
-{
-BaseType_t xReturn = pdFALSE;
-UBaseType_t uxMessagesWaiting;
-
-	/* This function is called from a critical section. */
-
-	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
-
-	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
-	{
-		#if ( configUSE_MUTEXES == 1 )
-		{
-			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
-			{
-				/* The mutex is no longer being held. */
-				xReturn = xTaskPriorityDisinherit( pxQueue->u.xSemaphore.xMutexHolder );
-				pxQueue->u.xSemaphore.xMutexHolder = NULL;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* configUSE_MUTEXES */
-	}
-	else if( xPosition == queueSEND_TO_BACK )
-	{
-		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
-		pxQueue->pcWriteTo += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
-		if( pxQueue->pcWriteTo >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
-		{
-			pxQueue->pcWriteTo = pxQueue->pcHead;
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		( void ) memcpy( ( void * ) pxQueue->u.xQueue.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e9087 !e418 MISRA exception as the casts are only redundant for some ports.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes.  Assert checks null pointer only used when length is 0. */
-		pxQueue->u.xQueue.pcReadFrom -= pxQueue->uxItemSize;
-		if( pxQueue->u.xQueue.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
-		{
-			pxQueue->u.xQueue.pcReadFrom = ( pxQueue->u.xQueue.pcTail - pxQueue->uxItemSize );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		if( xPosition == queueOVERWRITE )
-		{
-			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
-			{
-				/* An item is not being added but overwritten, so subtract
-				one from the recorded number of items in the queue so when
-				one is added again below the number of recorded items remains
-				correct. */
-				--uxMessagesWaiting;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-	pxQueue->uxMessagesWaiting = uxMessagesWaiting + ( UBaseType_t ) 1;
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
-{
-	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
-	{
-		pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize; /*lint !e9016 Pointer arithmetic on char types ok, especially in this use case where it is the clearest way of conveying intent. */
-		if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
-		{
-			pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 !e9087 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0.  Cast to void required by function signature and safe as no alignment requirement and copy length specified in bytes. */
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvUnlockQueue( Queue_t * const pxQueue )
-{
-	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
-
-	/* The lock counts contains the number of extra data items placed or
-	removed from the queue while the queue was locked.  When a queue is
-	locked items can be added or removed, but the event lists cannot be
-	updated. */
-	taskENTER_CRITICAL();
-	{
-		int8_t cTxLock = pxQueue->cTxLock;
-
-		/* See if data was added to the queue while it was locked. */
-		while( cTxLock > queueLOCKED_UNMODIFIED )
-		{
-			/* Data was posted while the queue was locked.  Are any tasks
-			blocked waiting for data to become available? */
-			#if ( configUSE_QUEUE_SETS == 1 )
-			{
-				if( pxQueue->pxQueueSetContainer != NULL )
-				{
-					if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
-					{
-						/* The queue is a member of a queue set, and posting to
-						the queue set caused a higher priority task to unblock.
-						A context switch is required. */
-						vTaskMissedYield();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					/* Tasks that are removed from the event list will get
-					added to the pending ready list as the scheduler is still
-					suspended. */
-					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-					{
-						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-						{
-							/* The task waiting has a higher priority so record that a
-							context	switch is required. */
-							vTaskMissedYield();
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						break;
-					}
-				}
-			}
-			#else /* configUSE_QUEUE_SETS */
-			{
-				/* Tasks that are removed from the event list will get added to
-				the pending ready list as the scheduler is still suspended. */
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-				{
-					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-					{
-						/* The task waiting has a higher priority so record that
-						a context switch is required. */
-						vTaskMissedYield();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					break;
-				}
-			}
-			#endif /* configUSE_QUEUE_SETS */
-
-			--cTxLock;
-		}
-
-		pxQueue->cTxLock = queueUNLOCKED;
-	}
-	taskEXIT_CRITICAL();
-
-	/* Do the same for the Rx lock. */
-	taskENTER_CRITICAL();
-	{
-		int8_t cRxLock = pxQueue->cRxLock;
-
-		while( cRxLock > queueLOCKED_UNMODIFIED )
-		{
-			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-			{
-				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-				{
-					vTaskMissedYield();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				--cRxLock;
-			}
-			else
-			{
-				break;
-			}
-		}
-
-		pxQueue->cRxLock = queueUNLOCKED;
-	}
-	taskEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
-{
-BaseType_t xReturn;
-
-	taskENTER_CRITICAL();
-	{
-		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
-		{
-			xReturn = pdTRUE;
-		}
-		else
-		{
-			xReturn = pdFALSE;
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
-{
-BaseType_t xReturn;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
-	{
-		xReturn = pdTRUE;
-	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
-
-	return xReturn;
-} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
-{
-BaseType_t xReturn;
-
-	taskENTER_CRITICAL();
-	{
-		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
-		{
-			xReturn = pdTRUE;
-		}
-		else
-		{
-			xReturn = pdFALSE;
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
-{
-BaseType_t xReturn;
-Queue_t * const pxQueue = xQueue;
-
-	configASSERT( pxQueue );
-	if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
-	{
-		xReturn = pdTRUE;
-	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
-
-	return xReturn;
-} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_CO_ROUTINES == 1 )
-
-	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
-	{
-	BaseType_t xReturn;
-	Queue_t * const pxQueue = xQueue;
-
-		/* If the queue is already full we may have to block.  A critical section
-		is required to prevent an interrupt removing something from the queue
-		between the check to see if the queue is full and blocking on the queue. */
-		portDISABLE_INTERRUPTS();
-		{
-			if( prvIsQueueFull( pxQueue ) != pdFALSE )
-			{
-				/* The queue is full - do we want to block or just leave without
-				posting? */
-				if( xTicksToWait > ( TickType_t ) 0 )
-				{
-					/* As this is called from a coroutine we cannot block directly, but
-					return indicating that we need to block. */
-					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
-					portENABLE_INTERRUPTS();
-					return errQUEUE_BLOCKED;
-				}
-				else
-				{
-					portENABLE_INTERRUPTS();
-					return errQUEUE_FULL;
-				}
-			}
-		}
-		portENABLE_INTERRUPTS();
-
-		portDISABLE_INTERRUPTS();
-		{
-			if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
-			{
-				/* There is room in the queue, copy the data into the queue. */
-				prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
-				xReturn = pdPASS;
-
-				/* Were any co-routines waiting for data to become available? */
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-				{
-					/* In this instance the co-routine could be placed directly
-					into the ready list as we are within a critical section.
-					Instead the same pending ready list mechanism is used as if
-					the event were caused from within an interrupt. */
-					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-					{
-						/* The co-routine waiting has a higher priority so record
-						that a yield might be appropriate. */
-						xReturn = errQUEUE_YIELD;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				xReturn = errQUEUE_FULL;
-			}
-		}
-		portENABLE_INTERRUPTS();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_CO_ROUTINES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_CO_ROUTINES == 1 )
-
-	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
-	{
-	BaseType_t xReturn;
-	Queue_t * const pxQueue = xQueue;
-
-		/* If the queue is already empty we may have to block.  A critical section
-		is required to prevent an interrupt adding something to the queue
-		between the check to see if the queue is empty and blocking on the queue. */
-		portDISABLE_INTERRUPTS();
-		{
-			if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
-			{
-				/* There are no messages in the queue, do we want to block or just
-				leave with nothing? */
-				if( xTicksToWait > ( TickType_t ) 0 )
-				{
-					/* As this is a co-routine we cannot block directly, but return
-					indicating that we need to block. */
-					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
-					portENABLE_INTERRUPTS();
-					return errQUEUE_BLOCKED;
-				}
-				else
-				{
-					portENABLE_INTERRUPTS();
-					return errQUEUE_FULL;
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		portENABLE_INTERRUPTS();
-
-		portDISABLE_INTERRUPTS();
-		{
-			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
-			{
-				/* Data is available from the queue. */
-				pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
-				if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
-				{
-					pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-				--( pxQueue->uxMessagesWaiting );
-				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
-
-				xReturn = pdPASS;
-
-				/* Were any co-routines waiting for space to become available? */
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-				{
-					/* In this instance the co-routine could be placed directly
-					into the ready list as we are within a critical section.
-					Instead the same pending ready list mechanism is used as if
-					the event were caused from within an interrupt. */
-					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-					{
-						xReturn = errQUEUE_YIELD;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				xReturn = pdFAIL;
-			}
-		}
-		portENABLE_INTERRUPTS();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_CO_ROUTINES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_CO_ROUTINES == 1 )
-
-	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
-	{
-	Queue_t * const pxQueue = xQueue;
-
-		/* Cannot block within an ISR so if there is no space on the queue then
-		exit without doing anything. */
-		if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
-		{
-			prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
-
-			/* We only want to wake one co-routine per ISR, so check that a
-			co-routine has not already been woken. */
-			if( xCoRoutinePreviouslyWoken == pdFALSE )
-			{
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
-				{
-					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
-					{
-						return pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return xCoRoutinePreviouslyWoken;
-	}
-
-#endif /* configUSE_CO_ROUTINES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_CO_ROUTINES == 1 )
-
-	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
-	{
-	BaseType_t xReturn;
-	Queue_t * const pxQueue = xQueue;
-
-		/* We cannot block from an ISR, so check there is data available. If
-		not then just leave without doing anything. */
-		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
-		{
-			/* Copy the data from the queue. */
-			pxQueue->u.xQueue.pcReadFrom += pxQueue->uxItemSize;
-			if( pxQueue->u.xQueue.pcReadFrom >= pxQueue->u.xQueue.pcTail )
-			{
-				pxQueue->u.xQueue.pcReadFrom = pxQueue->pcHead;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-			--( pxQueue->uxMessagesWaiting );
-			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.xQueue.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
-
-			if( ( *pxCoRoutineWoken ) == pdFALSE )
-			{
-				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
-				{
-					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
-					{
-						*pxCoRoutineWoken = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			xReturn = pdPASS;
-		}
-		else
-		{
-			xReturn = pdFAIL;
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_CO_ROUTINES */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	{
-	UBaseType_t ux;
-
-		/* See if there is an empty space in the registry.  A NULL name denotes
-		a free slot. */
-		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
-		{
-			if( xQueueRegistry[ ux ].pcQueueName == NULL )
-			{
-				/* Store the information on this queue. */
-				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
-				xQueueRegistry[ ux ].xHandle = xQueue;
-
-				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
-				break;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-	}
-
-#endif /* configQUEUE_REGISTRY_SIZE */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-	const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	{
-	UBaseType_t ux;
-	const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-		/* Note there is nothing here to protect against another task adding or
-		removing entries from the registry while it is being searched. */
-		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
-		{
-			if( xQueueRegistry[ ux ].xHandle == xQueue )
-			{
-				pcReturn = xQueueRegistry[ ux ].pcQueueName;
-				break;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-
-		return pcReturn;
-	} /*lint !e818 xQueue cannot be a pointer to const because it is a typedef. */
-
-#endif /* configQUEUE_REGISTRY_SIZE */
-/*-----------------------------------------------------------*/
-
-#if ( configQUEUE_REGISTRY_SIZE > 0 )
-
-	void vQueueUnregisterQueue( QueueHandle_t xQueue )
-	{
-	UBaseType_t ux;
-
-		/* See if the handle of the queue being unregistered in actually in the
-		registry. */
-		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
-		{
-			if( xQueueRegistry[ ux ].xHandle == xQueue )
-			{
-				/* Set the name to NULL to show that this slot if free again. */
-				xQueueRegistry[ ux ].pcQueueName = NULL;
-
-				/* Set the handle to NULL to ensure the same queue handle cannot
-				appear in the registry twice if it is added, removed, then
-				added again. */
-				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
-				break;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-
-	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
-
-#endif /* configQUEUE_REGISTRY_SIZE */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TIMERS == 1 )
-
-	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
-	{
-	Queue_t * const pxQueue = xQueue;
-
-		/* This function should not be called by application code hence the
-		'Restricted' in its name.  It is not part of the public API.  It is
-		designed for use by kernel code, and has special calling requirements.
-		It can result in vListInsert() being called on a list that can only
-		possibly ever have one item in it, so the list will be fast, but even
-		so it should be called with the scheduler locked and not from a critical
-		section. */
-
-		/* Only do anything if there are no messages in the queue.  This function
-		will not actually cause the task to block, just place it on a blocked
-		list.  It will not block until the scheduler is unlocked - at which
-		time a yield will be performed.  If an item is added to the queue while
-		the queue is locked, and the calling task blocks on the queue, then the
-		calling task will be immediately unblocked when the queue is unlocked. */
-		prvLockQueue( pxQueue );
-		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
-		{
-			/* There is nothing in the queue, block for the specified period. */
-			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-		prvUnlockQueue( pxQueue );
-	}
-
-#endif /* configUSE_TIMERS */
-/*-----------------------------------------------------------*/
-
-#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-	QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
-	{
-	QueueSetHandle_t pxQueue;
-
-		pxQueue = xQueueGenericCreate( uxEventQueueLength, ( UBaseType_t ) sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
-
-		return pxQueue;
-	}
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-	BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
-	{
-	BaseType_t xReturn;
-
-		taskENTER_CRITICAL();
-		{
-			if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
-			{
-				/* Cannot add a queue/semaphore to more than one queue set. */
-				xReturn = pdFAIL;
-			}
-			else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
-			{
-				/* Cannot add a queue/semaphore to a queue set if there are already
-				items in the queue/semaphore. */
-				xReturn = pdFAIL;
-			}
-			else
-			{
-				( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
-				xReturn = pdPASS;
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-	BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
-	{
-	BaseType_t xReturn;
-	Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
-
-		if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
-		{
-			/* The queue was not a member of the set. */
-			xReturn = pdFAIL;
-		}
-		else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
-		{
-			/* It is dangerous to remove a queue from a set when the queue is
-			not empty because the queue set will still hold pending events for
-			the queue. */
-			xReturn = pdFAIL;
-		}
-		else
-		{
-			taskENTER_CRITICAL();
-			{
-				/* The queue is no longer contained in the set. */
-				pxQueueOrSemaphore->pxQueueSetContainer = NULL;
-			}
-			taskEXIT_CRITICAL();
-			xReturn = pdPASS;
-		}
-
-		return xReturn;
-	} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-	QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
-	{
-	QueueSetMemberHandle_t xReturn = NULL;
-
-		( void ) xQueueReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait ); /*lint !e961 Casting from one typedef to another is not redundant. */
-		return xReturn;
-	}
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-	QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
-	{
-	QueueSetMemberHandle_t xReturn = NULL;
-
-		( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
-		return xReturn;
-	}
-
-#endif /* configUSE_QUEUE_SETS */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_QUEUE_SETS == 1 )
-
-	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )
-	{
-	Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
-	BaseType_t xReturn = pdFALSE;
-
-		/* This function must be called form a critical section. */
-
-		configASSERT( pxQueueSetContainer );
-		configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
-
-		if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
-		{
-			const int8_t cTxLock = pxQueueSetContainer->cTxLock;
-
-			traceQUEUE_SEND( pxQueueSetContainer );
-
-			/* The data copied is the handle of the queue that contains data. */
-			xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );
-
-			if( cTxLock == queueUNLOCKED )
-			{
-				if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
-				{
-					if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
-					{
-						/* The task waiting has a higher priority. */
-						xReturn = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_QUEUE_SETS */
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/FreeRTOS/Source/stream_buffer.c b/FreeRTOS/Source/stream_buffer.c
deleted file mode 100755
index 8551970..0000000
--- a/FreeRTOS/Source/stream_buffer.c
+++ /dev/null
@@ -1,1263 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* FreeRTOS includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "stream_buffer.h"
-
-#if( configUSE_TASK_NOTIFICATIONS != 1 )
-	#error configUSE_TASK_NOTIFICATIONS must be set to 1 to build stream_buffer.c
-#endif
-
-/* Lint e961, e9021 and e750 are suppressed as a MISRA exception justified
-because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
-for the header files above, but not in this file, in order to generate the
-correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
-
-/* If the user has not provided application specific Rx notification macros,
-or #defined the notification macros away, them provide default implementations
-that uses task notifications. */
-/*lint -save -e9026 Function like macros allowed and needed here so they can be overidden. */
-#ifndef sbRECEIVE_COMPLETED
-	#define sbRECEIVE_COMPLETED( pxStreamBuffer )										\
-		vTaskSuspendAll();																\
-		{																				\
-			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
-			{																			\
-				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToSend,			\
-									  ( uint32_t ) 0,									\
-									  eNoAction );										\
-				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
-			}																			\
-		}																				\
-		( void ) xTaskResumeAll();
-#endif /* sbRECEIVE_COMPLETED */
-
-#ifndef sbRECEIVE_COMPLETED_FROM_ISR
-	#define sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer,								\
-										  pxHigherPriorityTaskWoken )					\
-	{																					\
-	UBaseType_t uxSavedInterruptStatus;													\
-																						\
-		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
-		{																				\
-			if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )						\
-			{																			\
-				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,	\
-											 ( uint32_t ) 0,							\
-											 eNoAction,									\
-											 pxHigherPriorityTaskWoken );				\
-				( pxStreamBuffer )->xTaskWaitingToSend = NULL;							\
-			}																			\
-		}																				\
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
-	}
-#endif /* sbRECEIVE_COMPLETED_FROM_ISR */
-
-/* If the user has not provided an application specific Tx notification macro,
-or #defined the notification macro away, them provide a default implementation
-that uses task notifications. */
-#ifndef sbSEND_COMPLETED
-	#define sbSEND_COMPLETED( pxStreamBuffer )											\
-		vTaskSuspendAll();																\
-		{																				\
-			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
-			{																			\
-				( void ) xTaskNotify( ( pxStreamBuffer )->xTaskWaitingToReceive,		\
-									  ( uint32_t ) 0,									\
-									  eNoAction );										\
-				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
-			}																			\
-		}																				\
-		( void ) xTaskResumeAll();
-#endif /* sbSEND_COMPLETED */
-
-#ifndef sbSEND_COMPLETE_FROM_ISR
-	#define sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken )		\
-	{																					\
-	UBaseType_t uxSavedInterruptStatus;													\
-																						\
-		uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();		\
-		{																				\
-			if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )						\
-			{																			\
-				( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,	\
-											 ( uint32_t ) 0,							\
-											 eNoAction,									\
-											 pxHigherPriorityTaskWoken );				\
-				( pxStreamBuffer )->xTaskWaitingToReceive = NULL;						\
-			}																			\
-		}																				\
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );					\
-	}
-#endif /* sbSEND_COMPLETE_FROM_ISR */
-/*lint -restore (9026) */
-
-/* The number of bytes used to hold the length of a message in the buffer. */
-#define sbBYTES_TO_STORE_MESSAGE_LENGTH ( sizeof( configMESSAGE_BUFFER_LENGTH_TYPE ) )
-
-/* Bits stored in the ucFlags field of the stream buffer. */
-#define sbFLAGS_IS_MESSAGE_BUFFER		( ( uint8_t ) 1 ) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */
-#define sbFLAGS_IS_STATICALLY_ALLOCATED ( ( uint8_t ) 2 ) /* Set if the stream buffer was created using statically allocated memory. */
-
-/*-----------------------------------------------------------*/
-
-/* Structure that hold state information on the buffer. */
-typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */
-{
-	volatile size_t xTail;				/* Index to the next item to read within the buffer. */
-	volatile size_t xHead;				/* Index to the next item to write within the buffer. */
-	size_t xLength;						/* The length of the buffer pointed to by pucBuffer. */
-	size_t xTriggerLevelBytes;			/* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */
-	volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */
-	volatile TaskHandle_t xTaskWaitingToSend;	/* Holds the handle of a task waiting to send data to a message buffer that is full. */
-	uint8_t *pucBuffer;					/* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */
-	uint8_t ucFlags;
-
-	#if ( configUSE_TRACE_FACILITY == 1 )
-		UBaseType_t uxStreamBufferNumber;		/* Used for tracing purposes. */
-	#endif
-} StreamBuffer_t;
-
-/*
- * The number of bytes available to be read from the buffer.
- */
-static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer ) PRIVILEGED_FUNCTION;
-
-/*
- * Add xCount bytes from pucData into the pxStreamBuffer message buffer.
- * Returns the number of bytes written, which will either equal xCount in the
- * success case, or 0 if there was not enough space in the buffer (in which case
- * no data is written into the buffer).
- */
-static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount ) PRIVILEGED_FUNCTION;
-
-/*
- * If the stream buffer is being used as a message buffer, then reads an entire
- * message out of the buffer.  If the stream buffer is being used as a stream
- * buffer then read as many bytes as possible from the buffer.
- * prvReadBytesFromBuffer() is called to actually extract the bytes from the
- * buffer's data storage area.
- */
-static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
-										void *pvRxData,
-										size_t xBufferLengthBytes,
-										size_t xBytesAvailable,
-										size_t xBytesToStoreMessageLength ) PRIVILEGED_FUNCTION;
-
-/*
- * If the stream buffer is being used as a message buffer, then writes an entire
- * message to the buffer.  If the stream buffer is being used as a stream
- * buffer then write as many bytes as possible to the buffer.
- * prvWriteBytestoBuffer() is called to actually send the bytes to the buffer's
- * data storage area.
- */
-static size_t prvWriteMessageToBuffer(  StreamBuffer_t * const pxStreamBuffer,
-										const void * pvTxData,
-										size_t xDataLengthBytes,
-										size_t xSpace,
-										size_t xRequiredSpace ) PRIVILEGED_FUNCTION;
-
-/*
- * Read xMaxCount bytes from the pxStreamBuffer message buffer and write them
- * to pucData.
- */
-static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer,
-									  uint8_t *pucData,
-									  size_t xMaxCount,
-									  size_t xBytesAvailable ) PRIVILEGED_FUNCTION;
-
-/*
- * Called by both pxStreamBufferCreate() and pxStreamBufferCreateStatic() to
- * initialise the members of the newly created stream buffer structure.
- */
-static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
-										  uint8_t * const pucBuffer,
-										  size_t xBufferSizeBytes,
-										  size_t xTriggerLevelBytes,
-										  uint8_t ucFlags ) PRIVILEGED_FUNCTION;
-
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-	StreamBufferHandle_t xStreamBufferGenericCreate( size_t xBufferSizeBytes, size_t xTriggerLevelBytes, BaseType_t xIsMessageBuffer )
-	{
-	uint8_t *pucAllocatedMemory;
-	uint8_t ucFlags;
-
-		/* In case the stream buffer is going to be used as a message buffer
-		(that is, it will hold discrete messages with a little meta data that
-		says how big the next message is) check the buffer will be large enough
-		to hold at least one message. */
-		if( xIsMessageBuffer == pdTRUE )
-		{
-			/* Is a message buffer but not statically allocated. */
-			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER;
-			configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
-		}
-		else
-		{
-			/* Not a message buffer and not statically allocated. */
-			ucFlags = 0;
-			configASSERT( xBufferSizeBytes > 0 );
-		}
-		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
-
-		/* A trigger level of 0 would cause a waiting task to unblock even when
-		the buffer was empty. */
-		if( xTriggerLevelBytes == ( size_t ) 0 )
-		{
-			xTriggerLevelBytes = ( size_t ) 1;
-		}
-
-		/* A stream buffer requires a StreamBuffer_t structure and a buffer.
-		Both are allocated in a single call to pvPortMalloc().  The
-		StreamBuffer_t structure is placed at the start of the allocated memory
-		and the buffer follows immediately after.  The requested size is
-		incremented so the free space is returned as the user would expect -
-		this is a quirk of the implementation that means otherwise the free
-		space would be reported as one byte smaller than would be logically
-		expected. */
-		xBufferSizeBytes++;
-		pucAllocatedMemory = ( uint8_t * ) pvPortMalloc( xBufferSizeBytes + sizeof( StreamBuffer_t ) ); /*lint !e9079 malloc() only returns void*. */
-
-		if( pucAllocatedMemory != NULL )
-		{
-			prvInitialiseNewStreamBuffer( ( StreamBuffer_t * ) pucAllocatedMemory, /* Structure at the start of the allocated memory. */ /*lint !e9087 Safe cast as allocated memory is aligned. */ /*lint !e826 Area is not too small and alignment is guaranteed provided malloc() behaves as expected and returns aligned buffer. */
-										   pucAllocatedMemory + sizeof( StreamBuffer_t ),  /* Storage area follows. */ /*lint !e9016 Indexing past structure valid for uint8_t pointer, also storage area has no alignment requirement. */
-										   xBufferSizeBytes,
-										   xTriggerLevelBytes,
-										   ucFlags );
-
-			traceSTREAM_BUFFER_CREATE( ( ( StreamBuffer_t * ) pucAllocatedMemory ), xIsMessageBuffer );
-		}
-		else
-		{
-			traceSTREAM_BUFFER_CREATE_FAILED( xIsMessageBuffer );
-		}
-
-		return ( StreamBufferHandle_t ) pucAllocatedMemory; /*lint !e9087 !e826 Safe cast as allocated memory is aligned. */
-	}
-
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-	StreamBufferHandle_t xStreamBufferGenericCreateStatic( size_t xBufferSizeBytes,
-														   size_t xTriggerLevelBytes,
-														   BaseType_t xIsMessageBuffer,
-														   uint8_t * const pucStreamBufferStorageArea,
-														   StaticStreamBuffer_t * const pxStaticStreamBuffer )
-	{
-	StreamBuffer_t * const pxStreamBuffer = ( StreamBuffer_t * ) pxStaticStreamBuffer; /*lint !e740 !e9087 Safe cast as StaticStreamBuffer_t is opaque Streambuffer_t. */
-	StreamBufferHandle_t xReturn;
-	uint8_t ucFlags;
-
-		configASSERT( pucStreamBufferStorageArea );
-		configASSERT( pxStaticStreamBuffer );
-		configASSERT( xTriggerLevelBytes <= xBufferSizeBytes );
-
-		/* A trigger level of 0 would cause a waiting task to unblock even when
-		the buffer was empty. */
-		if( xTriggerLevelBytes == ( size_t ) 0 )
-		{
-			xTriggerLevelBytes = ( size_t ) 1;
-		}
-
-		if( xIsMessageBuffer != pdFALSE )
-		{
-			/* Statically allocated message buffer. */
-			ucFlags = sbFLAGS_IS_MESSAGE_BUFFER | sbFLAGS_IS_STATICALLY_ALLOCATED;
-		}
-		else
-		{
-			/* Statically allocated stream buffer. */
-			ucFlags = sbFLAGS_IS_STATICALLY_ALLOCATED;
-		}
-
-		/* In case the stream buffer is going to be used as a message buffer
-		(that is, it will hold discrete messages with a little meta data that
-		says how big the next message is) check the buffer will be large enough
-		to hold at least one message. */
-		configASSERT( xBufferSizeBytes > sbBYTES_TO_STORE_MESSAGE_LENGTH );
-
-		#if( configASSERT_DEFINED == 1 )
-		{
-			/* Sanity check that the size of the structure used to declare a
-			variable of type StaticStreamBuffer_t equals the size of the real
-			message buffer structure. */
-			volatile size_t xSize = sizeof( StaticStreamBuffer_t );
-			configASSERT( xSize == sizeof( StreamBuffer_t ) );
-		} /*lint !e529 xSize is referenced is configASSERT() is defined. */
-		#endif /* configASSERT_DEFINED */
-
-		if( ( pucStreamBufferStorageArea != NULL ) && ( pxStaticStreamBuffer != NULL ) )
-		{
-			prvInitialiseNewStreamBuffer( pxStreamBuffer,
-										  pucStreamBufferStorageArea,
-										  xBufferSizeBytes,
-										  xTriggerLevelBytes,
-										  ucFlags );
-
-			/* Remember this was statically allocated in case it is ever deleted
-			again. */
-			pxStreamBuffer->ucFlags |= sbFLAGS_IS_STATICALLY_ALLOCATED;
-
-			traceSTREAM_BUFFER_CREATE( pxStreamBuffer, xIsMessageBuffer );
-
-			xReturn = ( StreamBufferHandle_t ) pxStaticStreamBuffer; /*lint !e9087 Data hiding requires cast to opaque type. */
-		}
-		else
-		{
-			xReturn = NULL;
-			traceSTREAM_BUFFER_CREATE_STATIC_FAILED( xReturn, xIsMessageBuffer );
-		}
-
-		return xReturn;
-	}
-
-#endif /* ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-/*-----------------------------------------------------------*/
-
-void vStreamBufferDelete( StreamBufferHandle_t xStreamBuffer )
-{
-StreamBuffer_t * pxStreamBuffer = xStreamBuffer;
-
-	configASSERT( pxStreamBuffer );
-
-	traceSTREAM_BUFFER_DELETE( xStreamBuffer );
-
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) pdFALSE )
-	{
-		#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-		{
-			/* Both the structure and the buffer were allocated using a single call
-			to pvPortMalloc(), hence only one call to vPortFree() is required. */
-			vPortFree( ( void * ) pxStreamBuffer ); /*lint !e9087 Standard free() semantics require void *, plus pxStreamBuffer was allocated by pvPortMalloc(). */
-		}
-		#else
-		{
-			/* Should not be possible to get here, ucFlags must be corrupt.
-			Force an assert. */
-			configASSERT( xStreamBuffer == ( StreamBufferHandle_t ) ~0 );
-		}
-		#endif
-	}
-	else
-	{
-		/* The structure and buffer were not allocated dynamically and cannot be
-		freed - just scrub the structure so future use will assert. */
-		( void ) memset( pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) );
-	}
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferReset( StreamBufferHandle_t xStreamBuffer )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-BaseType_t xReturn = pdFAIL;
-
-#if( configUSE_TRACE_FACILITY == 1 )
-	UBaseType_t uxStreamBufferNumber;
-#endif
-
-	configASSERT( pxStreamBuffer );
-
-	#if( configUSE_TRACE_FACILITY == 1 )
-	{
-		/* Store the stream buffer number so it can be restored after the
-		reset. */
-		uxStreamBufferNumber = pxStreamBuffer->uxStreamBufferNumber;
-	}
-	#endif
-
-	/* Can only reset a message buffer if there are no tasks blocked on it. */
-	taskENTER_CRITICAL();
-	{
-		if( pxStreamBuffer->xTaskWaitingToReceive == NULL )
-		{
-			if( pxStreamBuffer->xTaskWaitingToSend == NULL )
-			{
-				prvInitialiseNewStreamBuffer( pxStreamBuffer,
-											  pxStreamBuffer->pucBuffer,
-											  pxStreamBuffer->xLength,
-											  pxStreamBuffer->xTriggerLevelBytes,
-											  pxStreamBuffer->ucFlags );
-				xReturn = pdPASS;
-
-				#if( configUSE_TRACE_FACILITY == 1 )
-				{
-					pxStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
-				}
-				#endif
-
-				traceSTREAM_BUFFER_RESET( xStreamBuffer );
-			}
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferSetTriggerLevel( StreamBufferHandle_t xStreamBuffer, size_t xTriggerLevel )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-BaseType_t xReturn;
-
-	configASSERT( pxStreamBuffer );
-
-	/* It is not valid for the trigger level to be 0. */
-	if( xTriggerLevel == ( size_t ) 0 )
-	{
-		xTriggerLevel = ( size_t ) 1;
-	}
-
-	/* The trigger level is the number of bytes that must be in the stream
-	buffer before a task that is waiting for data is unblocked. */
-	if( xTriggerLevel <= pxStreamBuffer->xLength )
-	{
-		pxStreamBuffer->xTriggerLevelBytes = xTriggerLevel;
-		xReturn = pdPASS;
-	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferSpacesAvailable( StreamBufferHandle_t xStreamBuffer )
-{
-const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xSpace;
-
-	configASSERT( pxStreamBuffer );
-
-	xSpace = pxStreamBuffer->xLength + pxStreamBuffer->xTail;
-	xSpace -= pxStreamBuffer->xHead;
-	xSpace -= ( size_t ) 1;
-
-	if( xSpace >= pxStreamBuffer->xLength )
-	{
-		xSpace -= pxStreamBuffer->xLength;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	return xSpace;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferBytesAvailable( StreamBufferHandle_t xStreamBuffer )
-{
-const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xReturn;
-
-	configASSERT( pxStreamBuffer );
-
-	xReturn = prvBytesInBuffer( pxStreamBuffer );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferSend( StreamBufferHandle_t xStreamBuffer,
-						  const void *pvTxData,
-						  size_t xDataLengthBytes,
-						  TickType_t xTicksToWait )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xReturn, xSpace = 0;
-size_t xRequiredSpace = xDataLengthBytes;
-TimeOut_t xTimeOut;
-
-	configASSERT( pvTxData );
-	configASSERT( pxStreamBuffer );
-
-	/* This send function is used to write to both message buffers and stream
-	buffers.  If this is a message buffer then the space needed must be
-	increased by the amount of bytes needed to store the length of the
-	message. */
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-	{
-		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
-
-		/* Overflow? */
-		configASSERT( xRequiredSpace > xDataLengthBytes );
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	if( xTicksToWait != ( TickType_t ) 0 )
-	{
-		vTaskSetTimeOutState( &xTimeOut );
-
-		do
-		{
-			/* Wait until the required number of bytes are free in the message
-			buffer. */
-			taskENTER_CRITICAL();
-			{
-				xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
-
-				if( xSpace < xRequiredSpace )
-				{
-					/* Clear notification state as going to wait for space. */
-					( void ) xTaskNotifyStateClear( NULL );
-
-					/* Should only be one writer. */
-					configASSERT( pxStreamBuffer->xTaskWaitingToSend == NULL );
-					pxStreamBuffer->xTaskWaitingToSend = xTaskGetCurrentTaskHandle();
-				}
-				else
-				{
-					taskEXIT_CRITICAL();
-					break;
-				}
-			}
-			taskEXIT_CRITICAL();
-
-			traceBLOCKING_ON_STREAM_BUFFER_SEND( xStreamBuffer );
-			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
-			pxStreamBuffer->xTaskWaitingToSend = NULL;
-
-		} while( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE );
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	if( xSpace == ( size_t ) 0 )
-	{
-		xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
-
-	if( xReturn > ( size_t ) 0 )
-	{
-		traceSTREAM_BUFFER_SEND( xStreamBuffer, xReturn );
-
-		/* Was a task waiting for the data? */
-		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
-		{
-			sbSEND_COMPLETED( pxStreamBuffer );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-		traceSTREAM_BUFFER_SEND_FAILED( xStreamBuffer );
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferSendFromISR( StreamBufferHandle_t xStreamBuffer,
-								 const void *pvTxData,
-								 size_t xDataLengthBytes,
-								 BaseType_t * const pxHigherPriorityTaskWoken )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xReturn, xSpace;
-size_t xRequiredSpace = xDataLengthBytes;
-
-	configASSERT( pvTxData );
-	configASSERT( pxStreamBuffer );
-
-	/* This send function is used to write to both message buffers and stream
-	buffers.  If this is a message buffer then the space needed must be
-	increased by the amount of bytes needed to store the length of the
-	message. */
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-	{
-		xRequiredSpace += sbBYTES_TO_STORE_MESSAGE_LENGTH;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	xSpace = xStreamBufferSpacesAvailable( pxStreamBuffer );
-	xReturn = prvWriteMessageToBuffer( pxStreamBuffer, pvTxData, xDataLengthBytes, xSpace, xRequiredSpace );
-
-	if( xReturn > ( size_t ) 0 )
-	{
-		/* Was a task waiting for the data? */
-		if( prvBytesInBuffer( pxStreamBuffer ) >= pxStreamBuffer->xTriggerLevelBytes )
-		{
-			sbSEND_COMPLETE_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	traceSTREAM_BUFFER_SEND_FROM_ISR( xStreamBuffer, xReturn );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvWriteMessageToBuffer( StreamBuffer_t * const pxStreamBuffer,
-									   const void * pvTxData,
-									   size_t xDataLengthBytes,
-									   size_t xSpace,
-									   size_t xRequiredSpace )
-{
-	BaseType_t xShouldWrite;
-	size_t xReturn;
-
-	if( xSpace == ( size_t ) 0 )
-	{
-		/* Doesn't matter if this is a stream buffer or a message buffer, there
-		is no space to write. */
-		xShouldWrite = pdFALSE;
-	}
-	else if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) == ( uint8_t ) 0 )
-	{
-		/* This is a stream buffer, as opposed to a message buffer, so writing a
-		stream of bytes rather than discrete messages.  Write as many bytes as
-		possible. */
-		xShouldWrite = pdTRUE;
-		xDataLengthBytes = configMIN( xDataLengthBytes, xSpace );
-	}
-	else if( xSpace >= xRequiredSpace )
-	{
-		/* This is a message buffer, as opposed to a stream buffer, and there
-		is enough space to write both the message length and the message itself
-		into the buffer.  Start by writing the length of the data, the data
-		itself will be written later in this function. */
-		xShouldWrite = pdTRUE;
-		( void ) prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) &( xDataLengthBytes ), sbBYTES_TO_STORE_MESSAGE_LENGTH );
-	}
-	else
-	{
-		/* There is space available, but not enough space. */
-		xShouldWrite = pdFALSE;
-	}
-
-	if( xShouldWrite != pdFALSE )
-	{
-		/* Writes the data itself. */
-		xReturn = prvWriteBytesToBuffer( pxStreamBuffer, ( const uint8_t * ) pvTxData, xDataLengthBytes ); /*lint !e9079 Storage buffer is implemented as uint8_t for ease of sizing, alighment and access. */
-	}
-	else
-	{
-		xReturn = 0;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferReceive( StreamBufferHandle_t xStreamBuffer,
-							 void *pvRxData,
-							 size_t xBufferLengthBytes,
-							 TickType_t xTicksToWait )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
-
-	configASSERT( pvRxData );
-	configASSERT( pxStreamBuffer );
-
-	/* This receive function is used by both message buffers, which store
-	discrete messages, and stream buffers, which store a continuous stream of
-	bytes.  Discrete messages include an additional
-	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
-	message. */
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-	{
-		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
-	}
-	else
-	{
-		xBytesToStoreMessageLength = 0;
-	}
-
-	if( xTicksToWait != ( TickType_t ) 0 )
-	{
-		/* Checking if there is data and clearing the notification state must be
-		performed atomically. */
-		taskENTER_CRITICAL();
-		{
-			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-
-			/* If this function was invoked by a message buffer read then
-			xBytesToStoreMessageLength holds the number of bytes used to hold
-			the length of the next discrete message.  If this function was
-			invoked by a stream buffer read then xBytesToStoreMessageLength will
-			be 0. */
-			if( xBytesAvailable <= xBytesToStoreMessageLength )
-			{
-				/* Clear notification state as going to wait for data. */
-				( void ) xTaskNotifyStateClear( NULL );
-
-				/* Should only be one reader. */
-				configASSERT( pxStreamBuffer->xTaskWaitingToReceive == NULL );
-				pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		if( xBytesAvailable <= xBytesToStoreMessageLength )
-		{
-			/* Wait for data to be available. */
-			traceBLOCKING_ON_STREAM_BUFFER_RECEIVE( xStreamBuffer );
-			( void ) xTaskNotifyWait( ( uint32_t ) 0, ( uint32_t ) 0, NULL, xTicksToWait );
-			pxStreamBuffer->xTaskWaitingToReceive = NULL;
-
-			/* Recheck the data available after blocking. */
-			xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-	}
-
-	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
-	holds the number of bytes used to store the message length) or a stream of
-	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
-	available must be greater than xBytesToStoreMessageLength to be able to
-	read bytes from the buffer. */
-	if( xBytesAvailable > xBytesToStoreMessageLength )
-	{
-		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
-
-		/* Was a task waiting for space in the buffer? */
-		if( xReceivedLength != ( size_t ) 0 )
-		{
-			traceSTREAM_BUFFER_RECEIVE( xStreamBuffer, xReceivedLength );
-			sbRECEIVE_COMPLETED( pxStreamBuffer );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		traceSTREAM_BUFFER_RECEIVE_FAILED( xStreamBuffer );
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	return xReceivedLength;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferNextMessageLengthBytes( StreamBufferHandle_t xStreamBuffer )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xReturn, xBytesAvailable, xOriginalTail;
-configMESSAGE_BUFFER_LENGTH_TYPE xTempReturn;
-
-	configASSERT( pxStreamBuffer );
-
-	/* Ensure the stream buffer is being used as a message buffer. */
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-	{
-		xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-		if( xBytesAvailable > sbBYTES_TO_STORE_MESSAGE_LENGTH )
-		{
-			/* The number of bytes available is greater than the number of bytes
-			required to hold the length of the next message, so another message
-			is available.  Return its length without removing the length bytes
-			from the buffer.  A copy of the tail is stored so the buffer can be
-			returned to its prior state as the message is not actually being
-			removed from the buffer. */
-			xOriginalTail = pxStreamBuffer->xTail;
-			( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempReturn, sbBYTES_TO_STORE_MESSAGE_LENGTH, xBytesAvailable );
-			xReturn = ( size_t ) xTempReturn;
-			pxStreamBuffer->xTail = xOriginalTail;
-		}
-		else
-		{
-			/* The minimum amount of bytes in a message buffer is
-			( sbBYTES_TO_STORE_MESSAGE_LENGTH + 1 ), so if xBytesAvailable is
-			less than sbBYTES_TO_STORE_MESSAGE_LENGTH the only other valid
-			value is 0. */
-			configASSERT( xBytesAvailable == 0 );
-			xReturn = 0;
-		}
-	}
-	else
-	{
-		xReturn = 0;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-size_t xStreamBufferReceiveFromISR( StreamBufferHandle_t xStreamBuffer,
-									void *pvRxData,
-									size_t xBufferLengthBytes,
-									BaseType_t * const pxHigherPriorityTaskWoken )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-size_t xReceivedLength = 0, xBytesAvailable, xBytesToStoreMessageLength;
-
-	configASSERT( pvRxData );
-	configASSERT( pxStreamBuffer );
-
-	/* This receive function is used by both message buffers, which store
-	discrete messages, and stream buffers, which store a continuous stream of
-	bytes.  Discrete messages include an additional
-	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the
-	message. */
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-	{
-		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
-	}
-	else
-	{
-		xBytesToStoreMessageLength = 0;
-	}
-
-	xBytesAvailable = prvBytesInBuffer( pxStreamBuffer );
-
-	/* Whether receiving a discrete message (where xBytesToStoreMessageLength
-	holds the number of bytes used to store the message length) or a stream of
-	bytes (where xBytesToStoreMessageLength is zero), the number of bytes
-	available must be greater than xBytesToStoreMessageLength to be able to
-	read bytes from the buffer. */
-	if( xBytesAvailable > xBytesToStoreMessageLength )
-	{
-		xReceivedLength = prvReadMessageFromBuffer( pxStreamBuffer, pvRxData, xBufferLengthBytes, xBytesAvailable, xBytesToStoreMessageLength );
-
-		/* Was a task waiting for space in the buffer? */
-		if( xReceivedLength != ( size_t ) 0 )
-		{
-			sbRECEIVE_COMPLETED_FROM_ISR( pxStreamBuffer, pxHigherPriorityTaskWoken );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	traceSTREAM_BUFFER_RECEIVE_FROM_ISR( xStreamBuffer, xReceivedLength );
-
-	return xReceivedLength;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvReadMessageFromBuffer( StreamBuffer_t *pxStreamBuffer,
-										void *pvRxData,
-										size_t xBufferLengthBytes,
-										size_t xBytesAvailable,
-										size_t xBytesToStoreMessageLength )
-{
-size_t xOriginalTail, xReceivedLength, xNextMessageLength;
-configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength;
-
-	if( xBytesToStoreMessageLength != ( size_t ) 0 )
-	{
-		/* A discrete message is being received.  First receive the length
-		of the message.  A copy of the tail is stored so the buffer can be
-		returned to its prior state if the length of the message is too
-		large for the provided buffer. */
-		xOriginalTail = pxStreamBuffer->xTail;
-		( void ) prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) &xTempNextMessageLength, xBytesToStoreMessageLength, xBytesAvailable );
-		xNextMessageLength = ( size_t ) xTempNextMessageLength;
-
-		/* Reduce the number of bytes available by the number of bytes just
-		read out. */
-		xBytesAvailable -= xBytesToStoreMessageLength;
-
-		/* Check there is enough space in the buffer provided by the
-		user. */
-		if( xNextMessageLength > xBufferLengthBytes )
-		{
-			/* The user has provided insufficient space to read the message
-			so return the buffer to its previous state (so the length of
-			the message is in the buffer again). */
-			pxStreamBuffer->xTail = xOriginalTail;
-			xNextMessageLength = 0;
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		/* A stream of bytes is being received (as opposed to a discrete
-		message), so read as many bytes as possible. */
-		xNextMessageLength = xBufferLengthBytes;
-	}
-
-	/* Read the actual data. */
-	xReceivedLength = prvReadBytesFromBuffer( pxStreamBuffer, ( uint8_t * ) pvRxData, xNextMessageLength, xBytesAvailable ); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */
-
-	return xReceivedLength;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferIsEmpty( StreamBufferHandle_t xStreamBuffer )
-{
-const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-BaseType_t xReturn;
-size_t xTail;
-
-	configASSERT( pxStreamBuffer );
-
-	/* True if no bytes are available. */
-	xTail = pxStreamBuffer->xTail;
-	if( pxStreamBuffer->xHead == xTail )
-	{
-		xReturn = pdTRUE;
-	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferIsFull( StreamBufferHandle_t xStreamBuffer )
-{
-BaseType_t xReturn;
-size_t xBytesToStoreMessageLength;
-const StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-
-	configASSERT( pxStreamBuffer );
-
-	/* This generic version of the receive function is used by both message
-	buffers, which store discrete messages, and stream buffers, which store a
-	continuous stream of bytes.  Discrete messages include an additional
-	sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the message. */
-	if( ( pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER ) != ( uint8_t ) 0 )
-	{
-		xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH;
-	}
-	else
-	{
-		xBytesToStoreMessageLength = 0;
-	}
-
-	/* True if the available space equals zero. */
-	if( xStreamBufferSpacesAvailable( xStreamBuffer ) <= xBytesToStoreMessageLength )
-	{
-		xReturn = pdTRUE;
-	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferSendCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-BaseType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-
-	configASSERT( pxStreamBuffer );
-
-	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		if( ( pxStreamBuffer )->xTaskWaitingToReceive != NULL )
-		{
-			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToReceive,
-										 ( uint32_t ) 0,
-										 eNoAction,
-										 pxHigherPriorityTaskWoken );
-			( pxStreamBuffer )->xTaskWaitingToReceive = NULL;
-			xReturn = pdTRUE;
-		}
-		else
-		{
-			xReturn = pdFALSE;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xStreamBufferReceiveCompletedFromISR( StreamBufferHandle_t xStreamBuffer, BaseType_t *pxHigherPriorityTaskWoken )
-{
-StreamBuffer_t * const pxStreamBuffer = xStreamBuffer;
-BaseType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-
-	configASSERT( pxStreamBuffer );
-
-	uxSavedInterruptStatus = ( UBaseType_t ) portSET_INTERRUPT_MASK_FROM_ISR();
-	{
-		if( ( pxStreamBuffer )->xTaskWaitingToSend != NULL )
-		{
-			( void ) xTaskNotifyFromISR( ( pxStreamBuffer )->xTaskWaitingToSend,
-										 ( uint32_t ) 0,
-										 eNoAction,
-										 pxHigherPriorityTaskWoken );
-			( pxStreamBuffer )->xTaskWaitingToSend = NULL;
-			xReturn = pdTRUE;
-		}
-		else
-		{
-			xReturn = pdFALSE;
-		}
-	}
-	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvWriteBytesToBuffer( StreamBuffer_t * const pxStreamBuffer, const uint8_t *pucData, size_t xCount )
-{
-size_t xNextHead, xFirstLength;
-
-	configASSERT( xCount > ( size_t ) 0 );
-
-	xNextHead = pxStreamBuffer->xHead;
-
-	/* Calculate the number of bytes that can be added in the first write -
-	which may be less than the total number of bytes that need to be added if
-	the buffer will wrap back to the beginning. */
-	xFirstLength = configMIN( pxStreamBuffer->xLength - xNextHead, xCount );
-
-	/* Write as many bytes as can be written in the first write. */
-	configASSERT( ( xNextHead + xFirstLength ) <= pxStreamBuffer->xLength );
-	( void ) memcpy( ( void* ) ( &( pxStreamBuffer->pucBuffer[ xNextHead ] ) ), ( const void * ) pucData, xFirstLength ); /*lint !e9087 memcpy() requires void *. */
-
-	/* If the number of bytes written was less than the number that could be
-	written in the first write... */
-	if( xCount > xFirstLength )
-	{
-		/* ...then write the remaining bytes to the start of the buffer. */
-		configASSERT( ( xCount - xFirstLength ) <= pxStreamBuffer->xLength );
-		( void ) memcpy( ( void * ) pxStreamBuffer->pucBuffer, ( const void * ) &( pucData[ xFirstLength ] ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	xNextHead += xCount;
-	if( xNextHead >= pxStreamBuffer->xLength )
-	{
-		xNextHead -= pxStreamBuffer->xLength;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	pxStreamBuffer->xHead = xNextHead;
-
-	return xCount;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvReadBytesFromBuffer( StreamBuffer_t *pxStreamBuffer, uint8_t *pucData, size_t xMaxCount, size_t xBytesAvailable )
-{
-size_t xCount, xFirstLength, xNextTail;
-
-	/* Use the minimum of the wanted bytes and the available bytes. */
-	xCount = configMIN( xBytesAvailable, xMaxCount );
-
-	if( xCount > ( size_t ) 0 )
-	{
-		xNextTail = pxStreamBuffer->xTail;
-
-		/* Calculate the number of bytes that can be read - which may be
-		less than the number wanted if the data wraps around to the start of
-		the buffer. */
-		xFirstLength = configMIN( pxStreamBuffer->xLength - xNextTail, xCount );
-
-		/* Obtain the number of bytes it is possible to obtain in the first
-		read.  Asserts check bounds of read and write. */
-		configASSERT( xFirstLength <= xMaxCount );
-		configASSERT( ( xNextTail + xFirstLength ) <= pxStreamBuffer->xLength );
-		( void ) memcpy( ( void * ) pucData, ( const void * ) &( pxStreamBuffer->pucBuffer[ xNextTail ] ), xFirstLength ); /*lint !e9087 memcpy() requires void *. */
-
-		/* If the total number of wanted bytes is greater than the number
-		that could be read in the first read... */
-		if( xCount > xFirstLength )
-		{
-			/*...then read the remaining bytes from the start of the buffer. */
-			configASSERT( xCount <= xMaxCount );
-			( void ) memcpy( ( void * ) &( pucData[ xFirstLength ] ), ( void * ) ( pxStreamBuffer->pucBuffer ), xCount - xFirstLength ); /*lint !e9087 memcpy() requires void *. */
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		/* Move the tail pointer to effectively remove the data read from
-		the buffer. */
-		xNextTail += xCount;
-
-		if( xNextTail >= pxStreamBuffer->xLength )
-		{
-			xNextTail -= pxStreamBuffer->xLength;
-		}
-
-		pxStreamBuffer->xTail = xNextTail;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	return xCount;
-}
-/*-----------------------------------------------------------*/
-
-static size_t prvBytesInBuffer( const StreamBuffer_t * const pxStreamBuffer )
-{
-/* Returns the distance between xTail and xHead. */
-size_t xCount;
-
-	xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead;
-	xCount -= pxStreamBuffer->xTail;
-	if ( xCount >= pxStreamBuffer->xLength )
-	{
-		xCount -= pxStreamBuffer->xLength;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	return xCount;
-}
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseNewStreamBuffer( StreamBuffer_t * const pxStreamBuffer,
-										  uint8_t * const pucBuffer,
-										  size_t xBufferSizeBytes,
-										  size_t xTriggerLevelBytes,
-										  uint8_t ucFlags )
-{
-	/* Assert here is deliberately writing to the entire buffer to ensure it can
-	be written to without generating exceptions, and is setting the buffer to a
-	known value to assist in development/debugging. */
-	#if( configASSERT_DEFINED == 1 )
-	{
-		/* The value written just has to be identifiable when looking at the
-		memory.  Don't use 0xA5 as that is the stack fill value and could
-		result in confusion as to what is actually being observed. */
-		const BaseType_t xWriteValue = 0x55;
-		configASSERT( memset( pucBuffer, ( int ) xWriteValue, xBufferSizeBytes ) == pucBuffer );
-	} /*lint !e529 !e438 xWriteValue is only used if configASSERT() is defined. */
-	#endif
-
-	( void ) memset( ( void * ) pxStreamBuffer, 0x00, sizeof( StreamBuffer_t ) ); /*lint !e9087 memset() requires void *. */
-	pxStreamBuffer->pucBuffer = pucBuffer;
-	pxStreamBuffer->xLength = xBufferSizeBytes;
-	pxStreamBuffer->xTriggerLevelBytes = xTriggerLevelBytes;
-	pxStreamBuffer->ucFlags = ucFlags;
-}
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	UBaseType_t uxStreamBufferGetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer )
-	{
-		return xStreamBuffer->uxStreamBufferNumber;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	void vStreamBufferSetStreamBufferNumber( StreamBufferHandle_t xStreamBuffer, UBaseType_t uxStreamBufferNumber )
-	{
-		xStreamBuffer->uxStreamBufferNumber = uxStreamBufferNumber;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	uint8_t ucStreamBufferGetStreamBufferType( StreamBufferHandle_t xStreamBuffer )
-	{
-		return ( xStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER );
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
diff --git a/FreeRTOS/Source/tasks.c b/FreeRTOS/Source/tasks.c
deleted file mode 100755
index 660039c..0000000
--- a/FreeRTOS/Source/tasks.c
+++ /dev/null
@@ -1,5214 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-/* FreeRTOS includes. */
-#include "FreeRTOS.h"
-#include "task.h"
-#include "timers.h"
-#include "stack_macros.h"
-
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
-because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
-for the header files above, but not in this file, in order to generate the
-correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750 !e9021. */
-
-/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
-functions but without including stdio.h here. */
-#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
-	/* At the bottom of this file are two optional functions that can be used
-	to generate human readable text from the raw data generated by the
-	uxTaskGetSystemState() function.  Note the formatting functions are provided
-	for convenience only, and are NOT considered part of the kernel. */
-	#include 
-#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
-
-#if( configUSE_PREEMPTION == 0 )
-	/* If the cooperative scheduler is being used then a yield should not be
-	performed just because a higher priority task has been woken. */
-	#define taskYIELD_IF_USING_PREEMPTION()
-#else
-	#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
-#endif
-
-/* Values that can be assigned to the ucNotifyState member of the TCB. */
-#define taskNOT_WAITING_NOTIFICATION	( ( uint8_t ) 0 )
-#define taskWAITING_NOTIFICATION		( ( uint8_t ) 1 )
-#define taskNOTIFICATION_RECEIVED		( ( uint8_t ) 2 )
-
-/*
- * The value used to fill the stack of a task when the task is created.  This
- * is used purely for checking the high water mark for tasks.
- */
-#define tskSTACK_FILL_BYTE	( 0xa5U )
-
-/* Bits used to recored how a task's stack and TCB were allocated. */
-#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
-#define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
-#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
-
-/* If any of the following are set then task stacks are filled with a known
-value so the high water mark can be determined.  If none of the following are
-set then don't fill the stack so there is no unnecessary dependency on memset. */
-#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
-	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	1
-#else
-	#define tskSET_NEW_STACKS_TO_KNOWN_VALUE	0
-#endif
-
-/*
- * Macros used by vListTask to indicate which state a task is in.
- */
-#define tskRUNNING_CHAR		( 'X' )
-#define tskBLOCKED_CHAR		( 'B' )
-#define tskREADY_CHAR		( 'R' )
-#define tskDELETED_CHAR		( 'D' )
-#define tskSUSPENDED_CHAR	( 'S' )
-
-/*
- * Some kernel aware debuggers require the data the debugger needs access to be
- * global, rather than file scope.
- */
-#ifdef portREMOVE_STATIC_QUALIFIER
-	#define static
-#endif
-
-/* The name allocated to the Idle task.  This can be overridden by defining
-configIDLE_TASK_NAME in FreeRTOSConfig.h. */
-#ifndef configIDLE_TASK_NAME
-	#define configIDLE_TASK_NAME "IDLE"
-#endif
-
-#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
-
-	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
-	performed in a generic way that is not optimised to any particular
-	microcontroller architecture. */
-
-	/* uxTopReadyPriority holds the priority of the highest priority ready
-	state task. */
-	#define taskRECORD_READY_PRIORITY( uxPriority )														\
-	{																									\
-		if( ( uxPriority ) > uxTopReadyPriority )														\
-		{																								\
-			uxTopReadyPriority = ( uxPriority );														\
-		}																								\
-	} /* taskRECORD_READY_PRIORITY */
-
-	/*-----------------------------------------------------------*/
-
-	#define taskSELECT_HIGHEST_PRIORITY_TASK()															\
-	{																									\
-	UBaseType_t uxTopPriority = uxTopReadyPriority;														\
-																										\
-		/* Find the highest priority queue that contains ready tasks. */								\
-		while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )							\
-		{																								\
-			configASSERT( uxTopPriority );																\
-			--uxTopPriority;																			\
-		}																								\
-																										\
-		/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of						\
-		the	same priority get an equal share of the processor time. */									\
-		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );			\
-		uxTopReadyPriority = uxTopPriority;																\
-	} /* taskSELECT_HIGHEST_PRIORITY_TASK */
-
-	/*-----------------------------------------------------------*/
-
-	/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
-	they are only required when a port optimised method of task selection is
-	being used. */
-	#define taskRESET_READY_PRIORITY( uxPriority )
-	#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
-
-#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
-	performed in a way that is tailored to the particular microcontroller
-	architecture being used. */
-
-	/* A port optimised version is provided.  Call the port defined macros. */
-	#define taskRECORD_READY_PRIORITY( uxPriority )	portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
-
-	/*-----------------------------------------------------------*/
-
-	#define taskSELECT_HIGHEST_PRIORITY_TASK()														\
-	{																								\
-	UBaseType_t uxTopPriority;																		\
-																									\
-		/* Find the highest priority list that contains ready tasks. */								\
-		portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );								\
-		configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );		\
-		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );		\
-	} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
-
-	/*-----------------------------------------------------------*/
-
-	/* A port optimised version is provided, call it only if the TCB being reset
-	is being referenced from a ready list.  If it is referenced from a delayed
-	or suspended list then it won't be in a ready list. */
-	#define taskRESET_READY_PRIORITY( uxPriority )														\
-	{																									\
-		if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )	\
-		{																								\
-			portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );							\
-		}																								\
-	}
-
-#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
-
-/*-----------------------------------------------------------*/
-
-/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
-count overflows. */
-#define taskSWITCH_DELAYED_LISTS()																	\
-{																									\
-	List_t *pxTemp;																					\
-																									\
-	/* The delayed tasks list should be empty when the lists are switched. */						\
-	configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );										\
-																									\
-	pxTemp = pxDelayedTaskList;																		\
-	pxDelayedTaskList = pxOverflowDelayedTaskList;													\
-	pxOverflowDelayedTaskList = pxTemp;																\
-	xNumOfOverflows++;																				\
-	prvResetNextTaskUnblockTime();																	\
-}
-
-/*-----------------------------------------------------------*/
-
-/*
- * Place the task represented by pxTCB into the appropriate ready list for
- * the task.  It is inserted at the end of the list.
- */
-#define prvAddTaskToReadyList( pxTCB )																\
-	traceMOVED_TASK_TO_READY_STATE( pxTCB );														\
-	taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );												\
-	vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
-	tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
-/*-----------------------------------------------------------*/
-
-/*
- * Several functions take an TaskHandle_t parameter that can optionally be NULL,
- * where NULL is used to indicate that the handle of the currently executing
- * task should be used in place of the parameter.  This macro simply checks to
- * see if the parameter is NULL and returns a pointer to the appropriate TCB.
- */
-#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? pxCurrentTCB : ( pxHandle ) )
-
-/* The item value of the event list item is normally used to hold the priority
-of the task to which it belongs (coded to allow it to be held in reverse
-priority order).  However, it is occasionally borrowed for other purposes.  It
-is important its value is not updated due to a task priority change while it is
-being used for another purpose.  The following bit definition is used to inform
-the scheduler that the value should not be changed - in which case it is the
-responsibility of whichever module is using the value to ensure it gets set back
-to its original value when it is released. */
-#if( configUSE_16_BIT_TICKS == 1 )
-	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x8000U
-#else
-	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x80000000UL
-#endif
-
-/*
- * Task control block.  A task control block (TCB) is allocated for each task,
- * and stores task state information, including a pointer to the task's context
- * (the task's run time environment, including register values)
- */
-typedef struct tskTaskControlBlock 			/* The old naming convention is used to prevent breaking kernel aware debuggers. */
-{
-	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
-
-	#if ( portUSING_MPU_WRAPPERS == 1 )
-		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
-	#endif
-
-	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
-	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
-	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
-	StackType_t			*pxStack;			/*< Points to the start of the stack. */
-	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-
-	#if ( ( portSTACK_GROWTH > 0 ) || ( configRECORD_STACK_HIGH_ADDRESS == 1 ) )
-		StackType_t		*pxEndOfStack;		/*< Points to the highest valid address for the stack. */
-	#endif
-
-	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
-		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
-	#endif
-
-	#if ( configUSE_TRACE_FACILITY == 1 )
-		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
-		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
-	#endif
-
-	#if ( configUSE_MUTEXES == 1 )
-		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
-		UBaseType_t		uxMutexesHeld;
-	#endif
-
-	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-		TaskHookFunction_t pxTaskTag;
-	#endif
-
-	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
-		void			*pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
-	#endif
-
-	#if( configGENERATE_RUN_TIME_STATS == 1 )
-		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
-	#endif
-
-	#if ( configUSE_NEWLIB_REENTRANT == 1 )
-		/* Allocate a Newlib reent structure that is specific to this task.
-		Note Newlib support has been included by popular demand, but is not
-		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
-		responsible for resulting newlib operation.  User must be familiar with
-		newlib and must provide system-wide implementations of the necessary
-		stubs. Be warned that (at the time of writing) the current newlib design
-		implements a system-wide malloc() that must be provided with locks. */
-		struct	_reent xNewLib_reent;
-	#endif
-
-	#if( configUSE_TASK_NOTIFICATIONS == 1 )
-		volatile uint32_t ulNotifiedValue;
-		volatile uint8_t ucNotifyState;
-	#endif
-
-	/* See the comments in FreeRTOS.h with the definition of
-	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
-	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
-		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
-	#endif
-
-	#if( INCLUDE_xTaskAbortDelay == 1 )
-		uint8_t ucDelayAborted;
-	#endif
-
-	#if( configUSE_POSIX_ERRNO == 1 )
-		int iTaskErrno;
-	#endif
-
-} tskTCB;
-
-/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
-below to enable the use of older kernel aware debuggers. */
-typedef tskTCB TCB_t;
-
-/*lint -save -e956 A manual analysis and inspection has been used to determine
-which static variables must be declared volatile. */
-PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
-
-/* Lists for ready and blocked tasks. --------------------
-xDelayedTaskList1 and xDelayedTaskList2 could be move to function scople but
-doing so breaks some kernel aware debuggers and debuggers that rely on removing
-the static qualifier. */
-PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */
-PRIVILEGED_DATA static List_t xDelayedTaskList1;						/*< Delayed tasks. */
-PRIVILEGED_DATA static List_t xDelayedTaskList2;						/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
-PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;				/*< Points to the delayed task list currently being used. */
-PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;		/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
-PRIVILEGED_DATA static List_t xPendingReadyList;						/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
-
-#if( INCLUDE_vTaskDelete == 1 )
-
-	PRIVILEGED_DATA static List_t xTasksWaitingTermination;				/*< Tasks that have been deleted - but their memory not yet freed. */
-	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
-
-#endif
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-	PRIVILEGED_DATA static List_t xSuspendedTaskList;					/*< Tasks that are currently suspended. */
-
-#endif
-
-/* Global POSIX errno. Its value is changed upon context switching to match
-the errno of the currently running task. */
-#if ( configUSE_POSIX_ERRNO == 1 )
-	int FreeRTOS_errno = 0;
-#endif
-
-/* Other file private variables. --------------------------------*/
-PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
-PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) configINITIAL_TICK_COUNT;
-PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
-PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
-PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks 			= ( UBaseType_t ) 0U;
-PRIVILEGED_DATA static volatile BaseType_t xYieldPending 			= pdFALSE;
-PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows 			= ( BaseType_t ) 0;
-PRIVILEGED_DATA static UBaseType_t uxTaskNumber 					= ( UBaseType_t ) 0U;
-PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime		= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
-PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle					= NULL;			/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
-
-/* Context switches are held pending while the scheduler is suspended.  Also,
-interrupts must not manipulate the xStateListItem of a TCB, or any of the
-lists the xStateListItem can be referenced from, if the scheduler is suspended.
-If an interrupt needs to unblock a task while the scheduler is suspended then it
-moves the task's event list item into the xPendingReadyList, ready for the
-kernel to move the task from the pending ready list into the real ready list
-when the scheduler is unsuspended.  The pending ready list itself can only be
-accessed from a critical section. */
-PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t ) pdFALSE;
-
-#if ( configGENERATE_RUN_TIME_STATS == 1 )
-
-	/* Do not move these variables to function scope as doing so prevents the
-	code working with debuggers that need to remove the static qualifier. */
-	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
-	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
-
-#endif
-
-/*lint -restore */
-
-/*-----------------------------------------------------------*/
-
-/* Callback function prototypes. --------------------------*/
-#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
-
-	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
-
-#endif
-
-#if( configUSE_TICK_HOOK > 0 )
-
-	extern void vApplicationTickHook( void ); /*lint !e526 Symbol not defined as it is an application callback. */
-
-#endif
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize ); /*lint !e526 Symbol not defined as it is an application callback. */
-
-#endif
-
-/* File private functions. --------------------------------*/
-
-/**
- * Utility task that simply returns pdTRUE if the task referenced by xTask is
- * currently in the Suspended state, or pdFALSE if the task referenced by xTask
- * is in any other state.
- */
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
-
-#endif /* INCLUDE_vTaskSuspend */
-
-/*
- * Utility to ready all the lists used by the scheduler.  This is called
- * automatically upon the creation of the first task.
- */
-static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
-
-/*
- * The idle task, which as all tasks is implemented as a never ending loop.
- * The idle task is automatically created and added to the ready lists upon
- * creation of the first user task.
- *
- * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
- * language extensions.  The equivalent prototype for this function is:
- *
- * void prvIdleTask( void *pvParameters );
- *
- */
-static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
-
-/*
- * Utility to free all memory allocated by the scheduler to hold a TCB,
- * including the stack pointed to by the TCB.
- *
- * This does not free memory allocated by the task itself (i.e. memory
- * allocated by calls to pvPortMalloc from within the tasks application code).
- */
-#if ( INCLUDE_vTaskDelete == 1 )
-
-	static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Used only by the idle task.  This checks to see if anything has been placed
- * in the list of tasks waiting to be deleted.  If so the task is cleaned up
- * and its TCB deleted.
- */
-static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
-
-/*
- * The currently executing task is entering the Blocked state.  Add the task to
- * either the current or the overflow delayed task list.
- */
-static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
-
-/*
- * Fills an TaskStatus_t structure with information on each task that is
- * referenced from the pxList list (which may be a ready list, a delayed list,
- * a suspended list, etc.).
- *
- * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
- * NORMAL APPLICATION CODE.
- */
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Searches pxList for a task with name pcNameToQuery - returning a handle to
- * the task if it is found, or NULL if the task is not found.
- */
-#if ( INCLUDE_xTaskGetHandle == 1 )
-
-	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * When a task is created, the stack of the task is filled with a known value.
- * This function determines the 'high water mark' of the task stack by
- * determining how much of the stack remains at the original preset value.
- */
-#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
-
-	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Return the amount of time, in ticks, that will pass before the kernel will
- * next move a task from the Blocked state to the Running state.
- *
- * This conditional compilation should use inequality to 0, not equality to 1.
- * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
- * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
- * set to a value other than 1.
- */
-#if ( configUSE_TICKLESS_IDLE != 0 )
-
-	static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Set xNextTaskUnblockTime to the time at which the next Blocked state task
- * will exit the Blocked state.
- */
-static void prvResetNextTaskUnblockTime( void );
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
-
-	/*
-	 * Helper function used to pad task names with spaces when printing out
-	 * human readable tables of task information.
-	 */
-	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*
- * Called after a Task_t structure has been allocated either statically or
- * dynamically to fill in the structure's members.
- */
-static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
-									const char * const pcName, 		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-									const uint32_t ulStackDepth,
-									void * const pvParameters,
-									UBaseType_t uxPriority,
-									TaskHandle_t * const pxCreatedTask,
-									TCB_t *pxNewTCB,
-									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION;
-
-/*
- * Called after a new task has been created and initialised to place the task
- * under the control of the scheduler.
- */
-static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
-
-/*
- * freertos_tasks_c_additions_init() should only be called if the user definable
- * macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is the only macro
- * called by the function.
- */
-#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
-
-	static void freertos_tasks_c_additions_init( void ) PRIVILEGED_FUNCTION;
-
-#endif
-
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
-									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-									const uint32_t ulStackDepth,
-									void * const pvParameters,
-									UBaseType_t uxPriority,
-									StackType_t * const puxStackBuffer,
-									StaticTask_t * const pxTaskBuffer )
-	{
-	TCB_t *pxNewTCB;
-	TaskHandle_t xReturn;
-
-		configASSERT( puxStackBuffer != NULL );
-		configASSERT( pxTaskBuffer != NULL );
-
-		#if( configASSERT_DEFINED == 1 )
-		{
-			/* Sanity check that the size of the structure used to declare a
-			variable of type StaticTask_t equals the size of the real task
-			structure. */
-			volatile size_t xSize = sizeof( StaticTask_t );
-			configASSERT( xSize == sizeof( TCB_t ) );
-			( void ) xSize; /* Prevent lint warning when configASSERT() is not used. */
-		}
-		#endif /* configASSERT_DEFINED */
-
-
-		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
-		{
-			/* The memory used for the task's TCB and stack are passed into this
-			function - use them. */
-			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 !e9087 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
-			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
-
-			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
-			{
-				/* Tasks can be created statically or dynamically, so note this
-				task was created statically in case the task is later deleted. */
-				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
-			}
-			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
-
-			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
-			prvAddNewTaskToReadyList( pxNewTCB );
-		}
-		else
-		{
-			xReturn = NULL;
-		}
-
-		return xReturn;
-	}
-
-#endif /* SUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
-
-	BaseType_t xTaskCreateRestrictedStatic( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
-	{
-	TCB_t *pxNewTCB;
-	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
-
-		configASSERT( pxTaskDefinition->puxStackBuffer != NULL );
-		configASSERT( pxTaskDefinition->pxTaskBuffer != NULL );
-
-		if( ( pxTaskDefinition->puxStackBuffer != NULL ) && ( pxTaskDefinition->pxTaskBuffer != NULL ) )
-		{
-			/* Allocate space for the TCB.  Where the memory comes from depends
-			on the implementation of the port malloc function and whether or
-			not static allocation is being used. */
-			pxNewTCB = ( TCB_t * ) pxTaskDefinition->pxTaskBuffer;
-
-			/* Store the stack location in the TCB. */
-			pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
-
-			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
-			{
-				/* Tasks can be created statically or dynamically, so note this
-				task was created statically in case the task is later deleted. */
-				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
-			}
-			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
-
-			prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
-									pxTaskDefinition->pcName,
-									( uint32_t ) pxTaskDefinition->usStackDepth,
-									pxTaskDefinition->pvParameters,
-									pxTaskDefinition->uxPriority,
-									pxCreatedTask, pxNewTCB,
-									pxTaskDefinition->xRegions );
-
-			prvAddNewTaskToReadyList( pxNewTCB );
-			xReturn = pdPASS;
-		}
-
-		return xReturn;
-	}
-
-#endif /* ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) */
-/*-----------------------------------------------------------*/
-
-#if( ( portUSING_MPU_WRAPPERS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
-	{
-	TCB_t *pxNewTCB;
-	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
-
-		configASSERT( pxTaskDefinition->puxStackBuffer );
-
-		if( pxTaskDefinition->puxStackBuffer != NULL )
-		{
-			/* Allocate space for the TCB.  Where the memory comes from depends
-			on the implementation of the port malloc function and whether or
-			not static allocation is being used. */
-			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
-
-			if( pxNewTCB != NULL )
-			{
-				/* Store the stack location in the TCB. */
-				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
-
-				#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
-				{
-					/* Tasks can be created statically or dynamically, so note
-					this task had a statically allocated stack in case it is
-					later deleted.  The TCB was allocated dynamically. */
-					pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
-				}
-				#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
-
-				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
-										pxTaskDefinition->pcName,
-										( uint32_t ) pxTaskDefinition->usStackDepth,
-										pxTaskDefinition->pvParameters,
-										pxTaskDefinition->uxPriority,
-										pxCreatedTask, pxNewTCB,
-										pxTaskDefinition->xRegions );
-
-				prvAddNewTaskToReadyList( pxNewTCB );
-				xReturn = pdPASS;
-			}
-		}
-
-		return xReturn;
-	}
-
-#endif /* portUSING_MPU_WRAPPERS */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
-							const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-							const configSTACK_DEPTH_TYPE usStackDepth,
-							void * const pvParameters,
-							UBaseType_t uxPriority,
-							TaskHandle_t * const pxCreatedTask )
-	{
-	TCB_t *pxNewTCB;
-	BaseType_t xReturn;
-
-		/* If the stack grows down then allocate the stack then the TCB so the stack
-		does not grow into the TCB.  Likewise if the stack grows up then allocate
-		the TCB then the stack. */
-		#if( portSTACK_GROWTH > 0 )
-		{
-			/* Allocate space for the TCB.  Where the memory comes from depends on
-			the implementation of the port malloc function and whether or not static
-			allocation is being used. */
-			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
-
-			if( pxNewTCB != NULL )
-			{
-				/* Allocate space for the stack used by the task being created.
-				The base of the stack memory stored in the TCB so the task can
-				be deleted later if required. */
-				pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
-				if( pxNewTCB->pxStack == NULL )
-				{
-					/* Could not allocate the stack.  Delete the allocated TCB. */
-					vPortFree( pxNewTCB );
-					pxNewTCB = NULL;
-				}
-			}
-		}
-		#else /* portSTACK_GROWTH */
-		{
-		StackType_t *pxStack;
-
-			/* Allocate space for the stack used by the task being created. */
-			pxStack = pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation is the stack. */
-
-			if( pxStack != NULL )
-			{
-				/* Allocate space for the TCB. */
-				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of TCB_t is always a pointer to the task's stack. */
-
-				if( pxNewTCB != NULL )
-				{
-					/* Store the stack location in the TCB. */
-					pxNewTCB->pxStack = pxStack;
-				}
-				else
-				{
-					/* The stack cannot be used as the TCB was not created.  Free
-					it again. */
-					vPortFree( pxStack );
-				}
-			}
-			else
-			{
-				pxNewTCB = NULL;
-			}
-		}
-		#endif /* portSTACK_GROWTH */
-
-		if( pxNewTCB != NULL )
-		{
-			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e9029 !e731 Macro has been consolidated for readability reasons. */
-			{
-				/* Tasks can be created statically or dynamically, so note this
-				task was created dynamically in case it is later deleted. */
-				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
-			}
-			#endif /* tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE */
-
-			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
-			prvAddNewTaskToReadyList( pxNewTCB );
-			xReturn = pdPASS;
-		}
-		else
-		{
-			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
-		}
-
-		return xReturn;
-	}
-
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
-									const char * const pcName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-									const uint32_t ulStackDepth,
-									void * const pvParameters,
-									UBaseType_t uxPriority,
-									TaskHandle_t * const pxCreatedTask,
-									TCB_t *pxNewTCB,
-									const MemoryRegion_t * const xRegions )
-{
-StackType_t *pxTopOfStack;
-UBaseType_t x;
-
-	#if( portUSING_MPU_WRAPPERS == 1 )
-		/* Should the task be created in privileged mode? */
-		BaseType_t xRunPrivileged;
-		if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
-		{
-			xRunPrivileged = pdTRUE;
-		}
-		else
-		{
-			xRunPrivileged = pdFALSE;
-		}
-		uxPriority &= ~portPRIVILEGE_BIT;
-	#endif /* portUSING_MPU_WRAPPERS == 1 */
-
-	/* Avoid dependency on memset() if it is not required. */
-	#if( tskSET_NEW_STACKS_TO_KNOWN_VALUE == 1 )
-	{
-		/* Fill the stack with a known value to assist debugging. */
-		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
-	}
-	#endif /* tskSET_NEW_STACKS_TO_KNOWN_VALUE */
-
-	/* Calculate the top of stack address.  This depends on whether the stack
-	grows from high memory to low (as per the 80x86) or vice versa.
-	portSTACK_GROWTH is used to make the result positive or negative as required
-	by the port. */
-	#if( portSTACK_GROWTH < 0 )
-	{
-		pxTopOfStack = &( pxNewTCB->pxStack[ ulStackDepth - ( uint32_t ) 1 ] );
-		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 !e9033 !e9078 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type.  Checked by assert(). */
-
-		/* Check the alignment of the calculated top of stack is correct. */
-		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
-
-		#if( configRECORD_STACK_HIGH_ADDRESS == 1 )
-		{
-			/* Also record the stack's high address, which may assist
-			debugging. */
-			pxNewTCB->pxEndOfStack = pxTopOfStack;
-		}
-		#endif /* configRECORD_STACK_HIGH_ADDRESS */
-	}
-	#else /* portSTACK_GROWTH */
-	{
-		pxTopOfStack = pxNewTCB->pxStack;
-
-		/* Check the alignment of the stack buffer is correct. */
-		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
-
-		/* The other extreme of the stack space is required if stack checking is
-		performed. */
-		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
-	}
-	#endif /* portSTACK_GROWTH */
-
-	/* Store the task name in the TCB. */
-	if( pcName != NULL )
-	{
-		for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
-		{
-			pxNewTCB->pcTaskName[ x ] = pcName[ x ];
-
-			/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
-			configMAX_TASK_NAME_LEN characters just in case the memory after the
-			string is not accessible (extremely unlikely). */
-			if( pcName[ x ] == ( char ) 0x00 )
-			{
-				break;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-
-		/* Ensure the name string is terminated in the case that the string length
-		was greater or equal to configMAX_TASK_NAME_LEN. */
-		pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
-	}
-	else
-	{
-		/* The task has not been given a name, so just ensure there is a NULL
-		terminator when it is read out. */
-		pxNewTCB->pcTaskName[ 0 ] = 0x00;
-	}
-
-	/* This is used as an array index so must ensure it's not too large.  First
-	remove the privilege bit if one is present. */
-	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
-	{
-		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	pxNewTCB->uxPriority = uxPriority;
-	#if ( configUSE_MUTEXES == 1 )
-	{
-		pxNewTCB->uxBasePriority = uxPriority;
-		pxNewTCB->uxMutexesHeld = 0;
-	}
-	#endif /* configUSE_MUTEXES */
-
-	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
-	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
-
-	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
-	back to	the containing TCB from a generic item in a list. */
-	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
-
-	/* Event lists are always in priority order. */
-	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
-
-	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
-	{
-		pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
-	}
-	#endif /* portCRITICAL_NESTING_IN_TCB */
-
-	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-	{
-		pxNewTCB->pxTaskTag = NULL;
-	}
-	#endif /* configUSE_APPLICATION_TASK_TAG */
-
-	#if ( configGENERATE_RUN_TIME_STATS == 1 )
-	{
-		pxNewTCB->ulRunTimeCounter = 0UL;
-	}
-	#endif /* configGENERATE_RUN_TIME_STATS */
-
-	#if ( portUSING_MPU_WRAPPERS == 1 )
-	{
-		vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
-	}
-	#else
-	{
-		/* Avoid compiler warning about unreferenced parameter. */
-		( void ) xRegions;
-	}
-	#endif
-
-	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-	{
-		for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
-		{
-			pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
-		}
-	}
-	#endif
-
-	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
-	{
-		pxNewTCB->ulNotifiedValue = 0;
-		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
-	}
-	#endif
-
-	#if ( configUSE_NEWLIB_REENTRANT == 1 )
-	{
-		/* Initialise this task's Newlib reent structure. */
-		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
-	}
-	#endif
-
-	#if( INCLUDE_xTaskAbortDelay == 1 )
-	{
-		pxNewTCB->ucDelayAborted = pdFALSE;
-	}
-	#endif
-
-	/* Initialize the TCB stack to look as if the task was already running,
-	but had been interrupted by the scheduler.  The return address is set
-	to the start of the task function. Once the stack has been initialised
-	the top of stack variable is updated. */
-	#if( portUSING_MPU_WRAPPERS == 1 )
-	{
-		/* If the port has capability to detect stack overflow,
-		pass the stack end address to the stack initialization
-		function as well. */
-		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-		{
-			#if( portSTACK_GROWTH < 0 )
-			{
-				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters, xRunPrivileged );
-			}
-			#else /* portSTACK_GROWTH */
-			{
-				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters, xRunPrivileged );
-			}
-			#endif /* portSTACK_GROWTH */
-		}
-		#else /* portHAS_STACK_OVERFLOW_CHECKING */
-		{
-			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
-		}
-		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
-	}
-	#else /* portUSING_MPU_WRAPPERS */
-	{
-		/* If the port has capability to detect stack overflow,
-		pass the stack end address to the stack initialization
-		function as well. */
-		#if( portHAS_STACK_OVERFLOW_CHECKING == 1 )
-		{
-			#if( portSTACK_GROWTH < 0 )
-			{
-				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxStack, pxTaskCode, pvParameters );
-			}
-			#else /* portSTACK_GROWTH */
-			{
-				pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxNewTCB->pxEndOfStack, pxTaskCode, pvParameters );
-			}
-			#endif /* portSTACK_GROWTH */
-		}
-		#else /* portHAS_STACK_OVERFLOW_CHECKING */
-		{
-			pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
-		}
-		#endif /* portHAS_STACK_OVERFLOW_CHECKING */
-	}
-	#endif /* portUSING_MPU_WRAPPERS */
-
-	if( pxCreatedTask != NULL )
-	{
-		/* Pass the handle out in an anonymous way.  The handle can be used to
-		change the created task's priority, delete the created task, etc.*/
-		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
-{
-	/* Ensure interrupts don't access the task lists while the lists are being
-	updated. */
-	taskENTER_CRITICAL();
-	{
-		uxCurrentNumberOfTasks++;
-		if( pxCurrentTCB == NULL )
-		{
-			/* There are no other tasks, or all the other tasks are in
-			the suspended state - make this the current task. */
-			pxCurrentTCB = pxNewTCB;
-
-			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
-			{
-				/* This is the first task to be created so do the preliminary
-				initialisation required.  We will not recover if this call
-				fails, but we will report the failure. */
-				prvInitialiseTaskLists();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			/* If the scheduler is not already running, make this task the
-			current task if it is the highest priority task to be created
-			so far. */
-			if( xSchedulerRunning == pdFALSE )
-			{
-				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
-				{
-					pxCurrentTCB = pxNewTCB;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-
-		uxTaskNumber++;
-
-		#if ( configUSE_TRACE_FACILITY == 1 )
-		{
-			/* Add a counter into the TCB for tracing only. */
-			pxNewTCB->uxTCBNumber = uxTaskNumber;
-		}
-		#endif /* configUSE_TRACE_FACILITY */
-		traceTASK_CREATE( pxNewTCB );
-
-		prvAddTaskToReadyList( pxNewTCB );
-
-		portSETUP_TCB( pxNewTCB );
-	}
-	taskEXIT_CRITICAL();
-
-	if( xSchedulerRunning != pdFALSE )
-	{
-		/* If the created task is of a higher priority than the current task
-		then it should run now. */
-		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
-		{
-			taskYIELD_IF_USING_PREEMPTION();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelete == 1 )
-
-	void vTaskDelete( TaskHandle_t xTaskToDelete )
-	{
-	TCB_t *pxTCB;
-
-		taskENTER_CRITICAL();
-		{
-			/* If null is passed in here then it is the calling task that is
-			being deleted. */
-			pxTCB = prvGetTCBFromHandle( xTaskToDelete );
-
-			/* Remove task from the ready list. */
-			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-			{
-				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			/* Is the task waiting on an event also? */
-			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-			{
-				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			/* Increment the uxTaskNumber also so kernel aware debuggers can
-			detect that the task lists need re-generating.  This is done before
-			portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
-			not return. */
-			uxTaskNumber++;
-
-			if( pxTCB == pxCurrentTCB )
-			{
-				/* A task is deleting itself.  This cannot complete within the
-				task itself, as a context switch to another task is required.
-				Place the task in the termination list.  The idle task will
-				check the termination list and free up any memory allocated by
-				the scheduler for the TCB and stack of the deleted task. */
-				vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
-
-				/* Increment the ucTasksDeleted variable so the idle task knows
-				there is a task that has been deleted and that it should therefore
-				check the xTasksWaitingTermination list. */
-				++uxDeletedTasksWaitingCleanUp;
-
-				/* The pre-delete hook is primarily for the Windows simulator,
-				in which Windows specific clean up operations are performed,
-				after which it is not possible to yield away from this task -
-				hence xYieldPending is used to latch that a context switch is
-				required. */
-				portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
-			}
-			else
-			{
-				--uxCurrentNumberOfTasks;
-				prvDeleteTCB( pxTCB );
-
-				/* Reset the next expected unblock time in case it referred to
-				the task that has just been deleted. */
-				prvResetNextTaskUnblockTime();
-			}
-
-			traceTASK_DELETE( pxTCB );
-		}
-		taskEXIT_CRITICAL();
-
-		/* Force a reschedule if it is the currently running task that has just
-		been deleted. */
-		if( xSchedulerRunning != pdFALSE )
-		{
-			if( pxTCB == pxCurrentTCB )
-			{
-				configASSERT( uxSchedulerSuspended == 0 );
-				portYIELD_WITHIN_API();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-	}
-
-#endif /* INCLUDE_vTaskDelete */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelayUntil == 1 )
-
-	void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
-	{
-	TickType_t xTimeToWake;
-	BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
-
-		configASSERT( pxPreviousWakeTime );
-		configASSERT( ( xTimeIncrement > 0U ) );
-		configASSERT( uxSchedulerSuspended == 0 );
-
-		vTaskSuspendAll();
-		{
-			/* Minor optimisation.  The tick count cannot change in this
-			block. */
-			const TickType_t xConstTickCount = xTickCount;
-
-			/* Generate the tick time at which the task wants to wake. */
-			xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
-
-			if( xConstTickCount < *pxPreviousWakeTime )
-			{
-				/* The tick count has overflowed since this function was
-				lasted called.  In this case the only time we should ever
-				actually delay is if the wake time has also	overflowed,
-				and the wake time is greater than the tick time.  When this
-				is the case it is as if neither time had overflowed. */
-				if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
-				{
-					xShouldDelay = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				/* The tick time has not overflowed.  In this case we will
-				delay if either the wake time has overflowed, and/or the
-				tick time is less than the wake time. */
-				if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
-				{
-					xShouldDelay = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-
-			/* Update the wake time ready for the next call. */
-			*pxPreviousWakeTime = xTimeToWake;
-
-			if( xShouldDelay != pdFALSE )
-			{
-				traceTASK_DELAY_UNTIL( xTimeToWake );
-
-				/* prvAddCurrentTaskToDelayedList() needs the block time, not
-				the time to wake, so subtract the current tick count. */
-				prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		xAlreadyYielded = xTaskResumeAll();
-
-		/* Force a reschedule if xTaskResumeAll has not already done so, we may
-		have put ourselves to sleep. */
-		if( xAlreadyYielded == pdFALSE )
-		{
-			portYIELD_WITHIN_API();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* INCLUDE_vTaskDelayUntil */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelay == 1 )
-
-	void vTaskDelay( const TickType_t xTicksToDelay )
-	{
-	BaseType_t xAlreadyYielded = pdFALSE;
-
-		/* A delay time of zero just forces a reschedule. */
-		if( xTicksToDelay > ( TickType_t ) 0U )
-		{
-			configASSERT( uxSchedulerSuspended == 0 );
-			vTaskSuspendAll();
-			{
-				traceTASK_DELAY();
-
-				/* A task that is removed from the event list while the
-				scheduler is suspended will not get placed in the ready
-				list or removed from the blocked list until the scheduler
-				is resumed.
-
-				This task cannot be in an event list as it is the currently
-				executing task. */
-				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
-			}
-			xAlreadyYielded = xTaskResumeAll();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		/* Force a reschedule if xTaskResumeAll has not already done so, we may
-		have put ourselves to sleep. */
-		if( xAlreadyYielded == pdFALSE )
-		{
-			portYIELD_WITHIN_API();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* INCLUDE_vTaskDelay */
-/*-----------------------------------------------------------*/
-
-#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_xTaskAbortDelay == 1 ) )
-
-	eTaskState eTaskGetState( TaskHandle_t xTask )
-	{
-	eTaskState eReturn;
-	List_t const * pxStateList, *pxDelayedList, *pxOverflowedDelayedList;
-	const TCB_t * const pxTCB = xTask;
-
-		configASSERT( pxTCB );
-
-		if( pxTCB == pxCurrentTCB )
-		{
-			/* The task calling this function is querying its own state. */
-			eReturn = eRunning;
-		}
-		else
-		{
-			taskENTER_CRITICAL();
-			{
-				pxStateList = listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
-				pxDelayedList = pxDelayedTaskList;
-				pxOverflowedDelayedList = pxOverflowDelayedTaskList;
-			}
-			taskEXIT_CRITICAL();
-
-			if( ( pxStateList == pxDelayedList ) || ( pxStateList == pxOverflowedDelayedList ) )
-			{
-				/* The task being queried is referenced from one of the Blocked
-				lists. */
-				eReturn = eBlocked;
-			}
-
-			#if ( INCLUDE_vTaskSuspend == 1 )
-				else if( pxStateList == &xSuspendedTaskList )
-				{
-					/* The task being queried is referenced from the suspended
-					list.  Is it genuinely suspended or is it blocked
-					indefinitely? */
-					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
-					{
-						#if( configUSE_TASK_NOTIFICATIONS == 1 )
-						{
-							/* The task does not appear on the event list item of
-							and of the RTOS objects, but could still be in the
-							blocked state if it is waiting on its notification
-							rather than waiting on an object. */
-							if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
-							{
-								eReturn = eBlocked;
-							}
-							else
-							{
-								eReturn = eSuspended;
-							}
-						}
-						#else
-						{
-							eReturn = eSuspended;
-						}
-						#endif
-					}
-					else
-					{
-						eReturn = eBlocked;
-					}
-				}
-			#endif
-
-			#if ( INCLUDE_vTaskDelete == 1 )
-				else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
-				{
-					/* The task being queried is referenced from the deleted
-					tasks list, or it is not referenced from any lists at
-					all. */
-					eReturn = eDeleted;
-				}
-			#endif
-
-			else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
-			{
-				/* If the task is not in any other state, it must be in the
-				Ready (including pending ready) state. */
-				eReturn = eReady;
-			}
-		}
-
-		return eReturn;
-	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
-
-#endif /* INCLUDE_eTaskGetState */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
-
-	UBaseType_t uxTaskPriorityGet( const TaskHandle_t xTask )
-	{
-	TCB_t const *pxTCB;
-	UBaseType_t uxReturn;
-
-		taskENTER_CRITICAL();
-		{
-			/* If null is passed in here then it is the priority of the task
-			that called uxTaskPriorityGet() that is being queried. */
-			pxTCB = prvGetTCBFromHandle( xTask );
-			uxReturn = pxTCB->uxPriority;
-		}
-		taskEXIT_CRITICAL();
-
-		return uxReturn;
-	}
-
-#endif /* INCLUDE_uxTaskPriorityGet */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskPriorityGet == 1 )
-
-	UBaseType_t uxTaskPriorityGetFromISR( const TaskHandle_t xTask )
-	{
-	TCB_t const *pxTCB;
-	UBaseType_t uxReturn, uxSavedInterruptState;
-
-		/* RTOS ports that support interrupt nesting have the concept of a
-		maximum	system call (or maximum API call) interrupt priority.
-		Interrupts that are	above the maximum system call priority are keep
-		permanently enabled, even when the RTOS kernel is in a critical section,
-		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
-		is defined in FreeRTOSConfig.h then
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-		failure if a FreeRTOS API function is called from an interrupt that has
-		been assigned a priority above the configured maximum system call
-		priority.  Only FreeRTOS functions that end in FromISR can be called
-		from interrupts	that have been assigned a priority at or (logically)
-		below the maximum system call interrupt priority.  FreeRTOS maintains a
-		separate interrupt safe API to ensure interrupt entry is as fast and as
-		simple as possible.  More information (albeit Cortex-M specific) is
-		provided on the following link:
-		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
-		{
-			/* If null is passed in here then it is the priority of the calling
-			task that is being queried. */
-			pxTCB = prvGetTCBFromHandle( xTask );
-			uxReturn = pxTCB->uxPriority;
-		}
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
-
-		return uxReturn;
-	}
-
-#endif /* INCLUDE_uxTaskPriorityGet */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskPrioritySet == 1 )
-
-	void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
-	{
-	TCB_t *pxTCB;
-	UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
-	BaseType_t xYieldRequired = pdFALSE;
-
-		configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
-
-		/* Ensure the new priority is valid. */
-		if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
-		{
-			uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		taskENTER_CRITICAL();
-		{
-			/* If null is passed in here then it is the priority of the calling
-			task that is being changed. */
-			pxTCB = prvGetTCBFromHandle( xTask );
-
-			traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
-
-			#if ( configUSE_MUTEXES == 1 )
-			{
-				uxCurrentBasePriority = pxTCB->uxBasePriority;
-			}
-			#else
-			{
-				uxCurrentBasePriority = pxTCB->uxPriority;
-			}
-			#endif
-
-			if( uxCurrentBasePriority != uxNewPriority )
-			{
-				/* The priority change may have readied a task of higher
-				priority than the calling task. */
-				if( uxNewPriority > uxCurrentBasePriority )
-				{
-					if( pxTCB != pxCurrentTCB )
-					{
-						/* The priority of a task other than the currently
-						running task is being raised.  Is the priority being
-						raised above that of the running task? */
-						if( uxNewPriority >= pxCurrentTCB->uxPriority )
-						{
-							xYieldRequired = pdTRUE;
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						/* The priority of the running task is being raised,
-						but the running task must already be the highest
-						priority task able to run so no yield is required. */
-					}
-				}
-				else if( pxTCB == pxCurrentTCB )
-				{
-					/* Setting the priority of the running task down means
-					there may now be another task of higher priority that
-					is ready to execute. */
-					xYieldRequired = pdTRUE;
-				}
-				else
-				{
-					/* Setting the priority of any other task down does not
-					require a yield as the running task must be above the
-					new priority of the task being modified. */
-				}
-
-				/* Remember the ready list the task might be referenced from
-				before its uxPriority member is changed so the
-				taskRESET_READY_PRIORITY() macro can function correctly. */
-				uxPriorityUsedOnEntry = pxTCB->uxPriority;
-
-				#if ( configUSE_MUTEXES == 1 )
-				{
-					/* Only change the priority being used if the task is not
-					currently using an inherited priority. */
-					if( pxTCB->uxBasePriority == pxTCB->uxPriority )
-					{
-						pxTCB->uxPriority = uxNewPriority;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* The base priority gets set whatever. */
-					pxTCB->uxBasePriority = uxNewPriority;
-				}
-				#else
-				{
-					pxTCB->uxPriority = uxNewPriority;
-				}
-				#endif
-
-				/* Only reset the event list item value if the value is not
-				being used for anything else. */
-				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
-				{
-					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* If the task is in the blocked or suspended list we need do
-				nothing more than change its priority variable. However, if
-				the task is in a ready list it needs to be removed and placed
-				in the list appropriate to its new priority. */
-				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
-				{
-					/* The task is currently in its ready list - remove before
-					adding it to it's new ready list.  As we are in a critical
-					section we can do this even if the scheduler is suspended. */
-					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-					{
-						/* It is known that the task is in its ready list so
-						there is no need to check again and the port level
-						reset macro can be called directly. */
-						portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-					prvAddTaskToReadyList( pxTCB );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				if( xYieldRequired != pdFALSE )
-				{
-					taskYIELD_IF_USING_PREEMPTION();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* Remove compiler warning about unused variables when the port
-				optimised task selection is not being used. */
-				( void ) uxPriorityUsedOnEntry;
-			}
-		}
-		taskEXIT_CRITICAL();
-	}
-
-#endif /* INCLUDE_vTaskPrioritySet */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-	void vTaskSuspend( TaskHandle_t xTaskToSuspend )
-	{
-	TCB_t *pxTCB;
-
-		taskENTER_CRITICAL();
-		{
-			/* If null is passed in here then it is the running task that is
-			being suspended. */
-			pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
-
-			traceTASK_SUSPEND( pxTCB );
-
-			/* Remove task from the ready/delayed list and place in the
-			suspended list. */
-			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-			{
-				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			/* Is the task waiting on an event also? */
-			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-			{
-				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
-
-			#if( configUSE_TASK_NOTIFICATIONS == 1 )
-			{
-				if( pxTCB->ucNotifyState == taskWAITING_NOTIFICATION )
-				{
-					/* The task was blocked to wait for a notification, but is
-					now suspended, so no notification was received. */
-					pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
-				}
-			}
-			#endif
-		}
-		taskEXIT_CRITICAL();
-
-		if( xSchedulerRunning != pdFALSE )
-		{
-			/* Reset the next expected unblock time in case it referred to the
-			task that is now in the Suspended state. */
-			taskENTER_CRITICAL();
-			{
-				prvResetNextTaskUnblockTime();
-			}
-			taskEXIT_CRITICAL();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		if( pxTCB == pxCurrentTCB )
-		{
-			if( xSchedulerRunning != pdFALSE )
-			{
-				/* The current task has just been suspended. */
-				configASSERT( uxSchedulerSuspended == 0 );
-				portYIELD_WITHIN_API();
-			}
-			else
-			{
-				/* The scheduler is not running, but the task that was pointed
-				to by pxCurrentTCB has just been suspended and pxCurrentTCB
-				must be adjusted to point to a different task. */
-				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks ) /*lint !e931 Right has no side effect, just volatile. */
-				{
-					/* No other tasks are ready, so set pxCurrentTCB back to
-					NULL so when the next task is created pxCurrentTCB will
-					be set to point to it no matter what its relative priority
-					is. */
-					pxCurrentTCB = NULL;
-				}
-				else
-				{
-					vTaskSwitchContext();
-				}
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* INCLUDE_vTaskSuspend */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
-	{
-	BaseType_t xReturn = pdFALSE;
-	const TCB_t * const pxTCB = xTask;
-
-		/* Accesses xPendingReadyList so must be called from a critical
-		section. */
-
-		/* It does not make sense to check if the calling task is suspended. */
-		configASSERT( xTask );
-
-		/* Is the task being resumed actually in the suspended list? */
-		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
-		{
-			/* Has the task already been resumed from within an ISR? */
-			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
-			{
-				/* Is it in the suspended list because it is in the	Suspended
-				state, or because is is blocked with no timeout? */
-				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE ) /*lint !e961.  The cast is only redundant when NULL is used. */
-				{
-					xReturn = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return xReturn;
-	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
-
-#endif /* INCLUDE_vTaskSuspend */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskSuspend == 1 )
-
-	void vTaskResume( TaskHandle_t xTaskToResume )
-	{
-	TCB_t * const pxTCB = xTaskToResume;
-
-		/* It does not make sense to resume the calling task. */
-		configASSERT( xTaskToResume );
-
-		/* The parameter cannot be NULL as it is impossible to resume the
-		currently executing task. */
-		if( ( pxTCB != pxCurrentTCB ) && ( pxTCB != NULL ) )
-		{
-			taskENTER_CRITICAL();
-			{
-				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
-				{
-					traceTASK_RESUME( pxTCB );
-
-					/* The ready list can be accessed even if the scheduler is
-					suspended because this is inside a critical section. */
-					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
-					prvAddTaskToReadyList( pxTCB );
-
-					/* A higher priority task may have just been resumed. */
-					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
-					{
-						/* This yield may not cause the task just resumed to run,
-						but will leave the lists in the correct state for the
-						next yield. */
-						taskYIELD_IF_USING_PREEMPTION();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			taskEXIT_CRITICAL();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* INCLUDE_vTaskSuspend */
-
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
-
-	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
-	{
-	BaseType_t xYieldRequired = pdFALSE;
-	TCB_t * const pxTCB = xTaskToResume;
-	UBaseType_t uxSavedInterruptStatus;
-
-		configASSERT( xTaskToResume );
-
-		/* RTOS ports that support interrupt nesting have the concept of a
-		maximum	system call (or maximum API call) interrupt priority.
-		Interrupts that are	above the maximum system call priority are keep
-		permanently enabled, even when the RTOS kernel is in a critical section,
-		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
-		is defined in FreeRTOSConfig.h then
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-		failure if a FreeRTOS API function is called from an interrupt that has
-		been assigned a priority above the configured maximum system call
-		priority.  Only FreeRTOS functions that end in FromISR can be called
-		from interrupts	that have been assigned a priority at or (logically)
-		below the maximum system call interrupt priority.  FreeRTOS maintains a
-		separate interrupt safe API to ensure interrupt entry is as fast and as
-		simple as possible.  More information (albeit Cortex-M specific) is
-		provided on the following link:
-		https://www.freertos.org/RTOS-Cortex-M3-M4.html */
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-		{
-			if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
-			{
-				traceTASK_RESUME_FROM_ISR( pxTCB );
-
-				/* Check the ready lists can be accessed. */
-				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-				{
-					/* Ready lists can be accessed so move the task from the
-					suspended list to the ready list directly. */
-					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
-					{
-						xYieldRequired = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-					prvAddTaskToReadyList( pxTCB );
-				}
-				else
-				{
-					/* The delayed or ready lists cannot be accessed so the task
-					is held in the pending ready list until the scheduler is
-					unsuspended. */
-					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-		return xYieldRequired;
-	}
-
-#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-void vTaskStartScheduler( void )
-{
-BaseType_t xReturn;
-
-	/* Add the idle task at the lowest priority. */
-	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-	{
-		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
-		StackType_t *pxIdleTaskStackBuffer = NULL;
-		uint32_t ulIdleTaskStackSize;
-
-		/* The Idle task is created using user provided RAM - obtain the
-		address of the RAM then create the idle task. */
-		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
-		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
-												configIDLE_TASK_NAME,
-												ulIdleTaskStackSize,
-												( void * ) NULL, /*lint !e961.  The cast is not redundant for all compilers. */
-												portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-												pxIdleTaskStackBuffer,
-												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-
-		if( xIdleTaskHandle != NULL )
-		{
-			xReturn = pdPASS;
-		}
-		else
-		{
-			xReturn = pdFAIL;
-		}
-	}
-	#else
-	{
-		/* The Idle task is being created using dynamically allocated RAM. */
-		xReturn = xTaskCreate(	prvIdleTask,
-								configIDLE_TASK_NAME,
-								configMINIMAL_STACK_SIZE,
-								( void * ) NULL,
-								portPRIVILEGE_BIT, /* In effect ( tskIDLE_PRIORITY | portPRIVILEGE_BIT ), but tskIDLE_PRIORITY is zero. */
-								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
-	}
-	#endif /* configSUPPORT_STATIC_ALLOCATION */
-
-	#if ( configUSE_TIMERS == 1 )
-	{
-		if( xReturn == pdPASS )
-		{
-			xReturn = xTimerCreateTimerTask();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif /* configUSE_TIMERS */
-
-	if( xReturn == pdPASS )
-	{
-		/* freertos_tasks_c_additions_init() should only be called if the user
-		definable macro FREERTOS_TASKS_C_ADDITIONS_INIT() is defined, as that is
-		the only macro called by the function. */
-		#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
-		{
-			freertos_tasks_c_additions_init();
-		}
-		#endif
-
-		/* Interrupts are turned off here, to ensure a tick does not occur
-		before or during the call to xPortStartScheduler().  The stacks of
-		the created tasks contain a status word with interrupts switched on
-		so interrupts will automatically get re-enabled when the first task
-		starts to run. */
-		portDISABLE_INTERRUPTS();
-
-		#if ( configUSE_NEWLIB_REENTRANT == 1 )
-		{
-			/* Switch Newlib's _impure_ptr variable to point to the _reent
-			structure specific to the task that will run first. */
-			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
-		}
-		#endif /* configUSE_NEWLIB_REENTRANT */
-
-		xNextTaskUnblockTime = portMAX_DELAY;
-		xSchedulerRunning = pdTRUE;
-		xTickCount = ( TickType_t ) configINITIAL_TICK_COUNT;
-
-		/* If configGENERATE_RUN_TIME_STATS is defined then the following
-		macro must be defined to configure the timer/counter used to generate
-		the run time counter time base.   NOTE:  If configGENERATE_RUN_TIME_STATS
-		is set to 0 and the following line fails to build then ensure you do not
-		have portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() defined in your
-		FreeRTOSConfig.h file. */
-		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
-
-		traceTASK_SWITCHED_IN();
-
-		/* Setting up the timer tick is hardware specific and thus in the
-		portable interface. */
-		if( xPortStartScheduler() != pdFALSE )
-		{
-			/* Should not reach here as if the scheduler is running the
-			function will not return. */
-		}
-		else
-		{
-			/* Should only reach here if a task calls xTaskEndScheduler(). */
-		}
-	}
-	else
-	{
-		/* This line will only be reached if the kernel could not be started,
-		because there was not enough FreeRTOS heap to create the idle task
-		or the timer task. */
-		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
-	}
-
-	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
-	meaning xIdleTaskHandle is not used anywhere else. */
-	( void ) xIdleTaskHandle;
-}
-/*-----------------------------------------------------------*/
-
-void vTaskEndScheduler( void )
-{
-	/* Stop the scheduler interrupts and call the portable scheduler end
-	routine so the original ISRs can be restored if necessary.  The port
-	layer must ensure interrupts enable	bit is left in the correct state. */
-	portDISABLE_INTERRUPTS();
-	xSchedulerRunning = pdFALSE;
-	vPortEndScheduler();
-}
-/*----------------------------------------------------------*/
-
-void vTaskSuspendAll( void )
-{
-	/* A critical section is not required as the variable is of type
-	BaseType_t.  Please read Richard Barry's reply in the following link to a
-	post in the FreeRTOS support forum before reporting this as a bug! -
-	http://goo.gl/wu4acr */
-	++uxSchedulerSuspended;
-	portMEMORY_BARRIER();
-}
-/*----------------------------------------------------------*/
-
-#if ( configUSE_TICKLESS_IDLE != 0 )
-
-	static TickType_t prvGetExpectedIdleTime( void )
-	{
-	TickType_t xReturn;
-	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
-
-		/* uxHigherPriorityReadyTasks takes care of the case where
-		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
-		task that are in the Ready state, even though the idle task is
-		running. */
-		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
-		{
-			if( uxTopReadyPriority > tskIDLE_PRIORITY )
-			{
-				uxHigherPriorityReadyTasks = pdTRUE;
-			}
-		}
-		#else
-		{
-			const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
-
-			/* When port optimised task selection is used the uxTopReadyPriority
-			variable is used as a bit map.  If bits other than the least
-			significant bit are set then there are tasks that have a priority
-			above the idle priority that are in the Ready state.  This takes
-			care of the case where the co-operative scheduler is in use. */
-			if( uxTopReadyPriority > uxLeastSignificantBit )
-			{
-				uxHigherPriorityReadyTasks = pdTRUE;
-			}
-		}
-		#endif
-
-		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
-		{
-			xReturn = 0;
-		}
-		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
-		{
-			/* There are other idle priority tasks in the ready state.  If
-			time slicing is used then the very next tick interrupt must be
-			processed. */
-			xReturn = 0;
-		}
-		else if( uxHigherPriorityReadyTasks != pdFALSE )
-		{
-			/* There are tasks in the Ready state that have a priority above the
-			idle priority.  This path can only be reached if
-			configUSE_PREEMPTION is 0. */
-			xReturn = 0;
-		}
-		else
-		{
-			xReturn = xNextTaskUnblockTime - xTickCount;
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*----------------------------------------------------------*/
-
-BaseType_t xTaskResumeAll( void )
-{
-TCB_t *pxTCB = NULL;
-BaseType_t xAlreadyYielded = pdFALSE;
-
-	/* If uxSchedulerSuspended is zero then this function does not match a
-	previous call to vTaskSuspendAll(). */
-	configASSERT( uxSchedulerSuspended );
-
-	/* It is possible that an ISR caused a task to be removed from an event
-	list while the scheduler was suspended.  If this was the case then the
-	removed task will have been added to the xPendingReadyList.  Once the
-	scheduler has been resumed it is safe to move all the pending ready
-	tasks from this list into their appropriate ready list. */
-	taskENTER_CRITICAL();
-	{
-		--uxSchedulerSuspended;
-
-		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-		{
-			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
-			{
-				/* Move any readied tasks from the pending list into the
-				appropriate ready list. */
-				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
-				{
-					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-					prvAddTaskToReadyList( pxTCB );
-
-					/* If the moved task has a priority higher than the current
-					task then a yield must be performed. */
-					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
-					{
-						xYieldPending = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-
-				if( pxTCB != NULL )
-				{
-					/* A task was unblocked while the scheduler was suspended,
-					which may have prevented the next unblock time from being
-					re-calculated, in which case re-calculate it now.  Mainly
-					important for low power tickless implementations, where
-					this can prevent an unnecessary exit from low power
-					state. */
-					prvResetNextTaskUnblockTime();
-				}
-
-				/* If any ticks occurred while the scheduler was suspended then
-				they should be processed now.  This ensures the tick count does
-				not	slip, and that any delayed tasks are resumed at the correct
-				time. */
-				{
-					UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
-
-					if( uxPendedCounts > ( UBaseType_t ) 0U )
-					{
-						do
-						{
-							if( xTaskIncrementTick() != pdFALSE )
-							{
-								xYieldPending = pdTRUE;
-							}
-							else
-							{
-								mtCOVERAGE_TEST_MARKER();
-							}
-							--uxPendedCounts;
-						} while( uxPendedCounts > ( UBaseType_t ) 0U );
-
-						uxPendedTicks = 0;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-
-				if( xYieldPending != pdFALSE )
-				{
-					#if( configUSE_PREEMPTION != 0 )
-					{
-						xAlreadyYielded = pdTRUE;
-					}
-					#endif
-					taskYIELD_IF_USING_PREEMPTION();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	return xAlreadyYielded;
-}
-/*-----------------------------------------------------------*/
-
-TickType_t xTaskGetTickCount( void )
-{
-TickType_t xTicks;
-
-	/* Critical section required if running on a 16 bit processor. */
-	portTICK_TYPE_ENTER_CRITICAL();
-	{
-		xTicks = xTickCount;
-	}
-	portTICK_TYPE_EXIT_CRITICAL();
-
-	return xTicks;
-}
-/*-----------------------------------------------------------*/
-
-TickType_t xTaskGetTickCountFromISR( void )
-{
-TickType_t xReturn;
-UBaseType_t uxSavedInterruptStatus;
-
-	/* RTOS ports that support interrupt nesting have the concept of a maximum
-	system call (or maximum API call) interrupt priority.  Interrupts that are
-	above the maximum system call priority are kept permanently enabled, even
-	when the RTOS kernel is in a critical section, but cannot make any calls to
-	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
-	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-	failure if a FreeRTOS API function is called from an interrupt that has been
-	assigned a priority above the configured maximum system call priority.
-	Only FreeRTOS functions that end in FromISR can be called from interrupts
-	that have been assigned a priority at or (logically) below the maximum
-	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
-	safe API to ensure interrupt entry is as fast and as simple as possible.
-	More information (albeit Cortex-M specific) is provided on the following
-	link: https://www.freertos.org/RTOS-Cortex-M3-M4.html */
-	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
-	{
-		xReturn = xTickCount;
-	}
-	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-UBaseType_t uxTaskGetNumberOfTasks( void )
-{
-	/* A critical section is not required because the variables are of type
-	BaseType_t. */
-	return uxCurrentNumberOfTasks;
-}
-/*-----------------------------------------------------------*/
-
-char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-{
-TCB_t *pxTCB;
-
-	/* If null is passed in here then the name of the calling task is being
-	queried. */
-	pxTCB = prvGetTCBFromHandle( xTaskToQuery );
-	configASSERT( pxTCB );
-	return &( pxTCB->pcTaskName[ 0 ] );
-}
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetHandle == 1 )
-
-	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
-	{
-	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
-	UBaseType_t x;
-	char cNextChar;
-	BaseType_t xBreakLoop;
-
-		/* This function is called with the scheduler suspended. */
-
-		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
-		{
-			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );  /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
-			do
-			{
-				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
-				/* Check each character in the name looking for a match or
-				mismatch. */
-				xBreakLoop = pdFALSE;
-				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
-				{
-					cNextChar = pxNextTCB->pcTaskName[ x ];
-
-					if( cNextChar != pcNameToQuery[ x ] )
-					{
-						/* Characters didn't match. */
-						xBreakLoop = pdTRUE;
-					}
-					else if( cNextChar == ( char ) 0x00 )
-					{
-						/* Both strings terminated, a match must have been
-						found. */
-						pxReturn = pxNextTCB;
-						xBreakLoop = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					if( xBreakLoop != pdFALSE )
-					{
-						break;
-					}
-				}
-
-				if( pxReturn != NULL )
-				{
-					/* The handle has been found. */
-					break;
-				}
-
-			} while( pxNextTCB != pxFirstTCB );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return pxReturn;
-	}
-
-#endif /* INCLUDE_xTaskGetHandle */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetHandle == 1 )
-
-	TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	{
-	UBaseType_t uxQueue = configMAX_PRIORITIES;
-	TCB_t* pxTCB;
-
-		/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
-		configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
-
-		vTaskSuspendAll();
-		{
-			/* Search the ready lists. */
-			do
-			{
-				uxQueue--;
-				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
-
-				if( pxTCB != NULL )
-				{
-					/* Found the handle. */
-					break;
-				}
-
-			} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
-			/* Search the delayed lists. */
-			if( pxTCB == NULL )
-			{
-				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
-			}
-
-			if( pxTCB == NULL )
-			{
-				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
-			}
-
-			#if ( INCLUDE_vTaskSuspend == 1 )
-			{
-				if( pxTCB == NULL )
-				{
-					/* Search the suspended list. */
-					pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
-				}
-			}
-			#endif
-
-			#if( INCLUDE_vTaskDelete == 1 )
-			{
-				if( pxTCB == NULL )
-				{
-					/* Search the deleted list. */
-					pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
-				}
-			}
-			#endif
-		}
-		( void ) xTaskResumeAll();
-
-		return pxTCB;
-	}
-
-#endif /* INCLUDE_xTaskGetHandle */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
-	{
-	UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
-
-		vTaskSuspendAll();
-		{
-			/* Is there a space in the array for each task in the system? */
-			if( uxArraySize >= uxCurrentNumberOfTasks )
-			{
-				/* Fill in an TaskStatus_t structure with information on each
-				task in the Ready state. */
-				do
-				{
-					uxQueue--;
-					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
-
-				} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
-				/* Fill in an TaskStatus_t structure with information on each
-				task in the Blocked state. */
-				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
-				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
-
-				#if( INCLUDE_vTaskDelete == 1 )
-				{
-					/* Fill in an TaskStatus_t structure with information on
-					each task that has been deleted but not yet cleaned up. */
-					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
-				}
-				#endif
-
-				#if ( INCLUDE_vTaskSuspend == 1 )
-				{
-					/* Fill in an TaskStatus_t structure with information on
-					each task in the Suspended state. */
-					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
-				}
-				#endif
-
-				#if ( configGENERATE_RUN_TIME_STATS == 1)
-				{
-					if( pulTotalRunTime != NULL )
-					{
-						#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
-							portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
-						#else
-							*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
-						#endif
-					}
-				}
-				#else
-				{
-					if( pulTotalRunTime != NULL )
-					{
-						*pulTotalRunTime = 0;
-					}
-				}
-				#endif
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		( void ) xTaskResumeAll();
-
-		return uxTask;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
-
-	TaskHandle_t xTaskGetIdleTaskHandle( void )
-	{
-		/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
-		started, then xIdleTaskHandle will be NULL. */
-		configASSERT( ( xIdleTaskHandle != NULL ) );
-		return xIdleTaskHandle;
-	}
-
-#endif /* INCLUDE_xTaskGetIdleTaskHandle */
-/*----------------------------------------------------------*/
-
-/* This conditional compilation should use inequality to 0, not equality to 1.
-This is to ensure vTaskStepTick() is available when user defined low power mode
-implementations require configUSE_TICKLESS_IDLE to be set to a value other than
-1. */
-#if ( configUSE_TICKLESS_IDLE != 0 )
-
-	void vTaskStepTick( const TickType_t xTicksToJump )
-	{
-		/* Correct the tick count value after a period during which the tick
-		was suppressed.  Note this does *not* call the tick hook function for
-		each stepped tick. */
-		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
-		xTickCount += xTicksToJump;
-		traceINCREASE_TICK_COUNT( xTicksToJump );
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*----------------------------------------------------------*/
-
-#if ( INCLUDE_xTaskAbortDelay == 1 )
-
-	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
-	{
-	TCB_t *pxTCB = xTask;
-	BaseType_t xReturn;
-
-		configASSERT( pxTCB );
-
-		vTaskSuspendAll();
-		{
-			/* A task can only be prematurely removed from the Blocked state if
-			it is actually in the Blocked state. */
-			if( eTaskGetState( xTask ) == eBlocked )
-			{
-				xReturn = pdPASS;
-
-				/* Remove the reference to the task from the blocked list.  An
-				interrupt won't touch the xStateListItem because the
-				scheduler is suspended. */
-				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-
-				/* Is the task waiting on an event also?  If so remove it from
-				the event list too.  Interrupts can touch the event list item,
-				even though the scheduler is suspended, so a critical section
-				is used. */
-				taskENTER_CRITICAL();
-				{
-					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-					{
-						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-						pxTCB->ucDelayAborted = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				taskEXIT_CRITICAL();
-
-				/* Place the unblocked task into the appropriate ready list. */
-				prvAddTaskToReadyList( pxTCB );
-
-				/* A task being unblocked cannot cause an immediate context
-				switch if preemption is turned off. */
-				#if (  configUSE_PREEMPTION == 1 )
-				{
-					/* Preemption is on, but a context switch should only be
-					performed if the unblocked task has a priority that is
-					equal to or higher than the currently executing task. */
-					if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-					{
-						/* Pend the yield to be performed when the scheduler
-						is unsuspended. */
-						xYieldPending = pdTRUE;
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				#endif /* configUSE_PREEMPTION */
-			}
-			else
-			{
-				xReturn = pdFAIL;
-			}
-		}
-		( void ) xTaskResumeAll();
-
-		return xReturn;
-	}
-
-#endif /* INCLUDE_xTaskAbortDelay */
-/*----------------------------------------------------------*/
-
-BaseType_t xTaskIncrementTick( void )
-{
-TCB_t * pxTCB;
-TickType_t xItemValue;
-BaseType_t xSwitchRequired = pdFALSE;
-
-	/* Called by the portable layer each time a tick interrupt occurs.
-	Increments the tick then checks to see if the new tick value will cause any
-	tasks to be unblocked. */
-	traceTASK_INCREMENT_TICK( xTickCount );
-	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-	{
-		/* Minor optimisation.  The tick count cannot change in this
-		block. */
-		const TickType_t xConstTickCount = xTickCount + ( TickType_t ) 1;
-
-		/* Increment the RTOS tick, switching the delayed and overflowed
-		delayed lists if it wraps to 0. */
-		xTickCount = xConstTickCount;
-
-		if( xConstTickCount == ( TickType_t ) 0U ) /*lint !e774 'if' does not always evaluate to false as it is looking for an overflow. */
-		{
-			taskSWITCH_DELAYED_LISTS();
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		/* See if this tick has made a timeout expire.  Tasks are stored in
-		the	queue in the order of their wake time - meaning once one task
-		has been found whose block time has not expired there is no need to
-		look any further down the list. */
-		if( xConstTickCount >= xNextTaskUnblockTime )
-		{
-			for( ;; )
-			{
-				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
-				{
-					/* The delayed list is empty.  Set xNextTaskUnblockTime
-					to the maximum possible value so it is extremely
-					unlikely that the
-					if( xTickCount >= xNextTaskUnblockTime ) test will pass
-					next time through. */
-					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-					break;
-				}
-				else
-				{
-					/* The delayed list is not empty, get the value of the
-					item at the head of the delayed list.  This is the time
-					at which the task at the head of the delayed list must
-					be removed from the Blocked state. */
-					pxTCB = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
-
-					if( xConstTickCount < xItemValue )
-					{
-						/* It is not time to unblock this item yet, but the
-						item value is the time at which the task at the head
-						of the blocked list must be removed from the Blocked
-						state -	so record the item value in
-						xNextTaskUnblockTime. */
-						xNextTaskUnblockTime = xItemValue;
-						break; /*lint !e9011 Code structure here is deedmed easier to understand with multiple breaks. */
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* It is time to remove the item from the Blocked state. */
-					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-
-					/* Is the task waiting on an event also?  If so remove
-					it from the event list. */
-					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-					{
-						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* Place the unblocked task into the appropriate ready
-					list. */
-					prvAddTaskToReadyList( pxTCB );
-
-					/* A task being unblocked cannot cause an immediate
-					context switch if preemption is turned off. */
-					#if (  configUSE_PREEMPTION == 1 )
-					{
-						/* Preemption is on, but a context switch should
-						only be performed if the unblocked task has a
-						priority that is equal to or higher than the
-						currently executing task. */
-						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
-						{
-							xSwitchRequired = pdTRUE;
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					#endif /* configUSE_PREEMPTION */
-				}
-			}
-		}
-
-		/* Tasks of equal priority to the currently running task will share
-		processing time (time slice) if preemption is on, and the application
-		writer has not explicitly turned time slicing off. */
-		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
-		{
-			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
-			{
-				xSwitchRequired = pdTRUE;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
-
-		#if ( configUSE_TICK_HOOK == 1 )
-		{
-			/* Guard against the tick hook being called when the pended tick
-			count is being unwound (when the scheduler is being unlocked). */
-			if( uxPendedTicks == ( UBaseType_t ) 0U )
-			{
-				vApplicationTickHook();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* configUSE_TICK_HOOK */
-	}
-	else
-	{
-		++uxPendedTicks;
-
-		/* The tick hook gets called at regular intervals, even if the
-		scheduler is locked. */
-		#if ( configUSE_TICK_HOOK == 1 )
-		{
-			vApplicationTickHook();
-		}
-		#endif
-	}
-
-	#if ( configUSE_PREEMPTION == 1 )
-	{
-		if( xYieldPending != pdFALSE )
-		{
-			xSwitchRequired = pdTRUE;
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	#endif /* configUSE_PREEMPTION */
-
-	return xSwitchRequired;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-
-	void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
-	{
-	TCB_t *xTCB;
-
-		/* If xTask is NULL then it is the task hook of the calling task that is
-		getting set. */
-		if( xTask == NULL )
-		{
-			xTCB = ( TCB_t * ) pxCurrentTCB;
-		}
-		else
-		{
-			xTCB = xTask;
-		}
-
-		/* Save the hook function in the TCB.  A critical section is required as
-		the value can be accessed from an interrupt. */
-		taskENTER_CRITICAL();
-		{
-			xTCB->pxTaskTag = pxHookFunction;
-		}
-		taskEXIT_CRITICAL();
-	}
-
-#endif /* configUSE_APPLICATION_TASK_TAG */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-
-	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
-	{
-	TCB_t *pxTCB;
-	TaskHookFunction_t xReturn;
-
-		/* If xTask is NULL then set the calling task's hook. */
-		pxTCB = prvGetTCBFromHandle( xTask );
-
-		/* Save the hook function in the TCB.  A critical section is required as
-		the value can be accessed from an interrupt. */
-		taskENTER_CRITICAL();
-		{
-			xReturn = pxTCB->pxTaskTag;
-		}
-		taskEXIT_CRITICAL();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_APPLICATION_TASK_TAG */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-
-	TaskHookFunction_t xTaskGetApplicationTaskTagFromISR( TaskHandle_t xTask )
-	{
-	TCB_t *pxTCB;
-	TaskHookFunction_t xReturn;
-	UBaseType_t uxSavedInterruptStatus;
-
-		/* If xTask is NULL then set the calling task's hook. */
-		pxTCB = prvGetTCBFromHandle( xTask );
-
-		/* Save the hook function in the TCB.  A critical section is required as
-		the value can be accessed from an interrupt. */
-		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-		{
-			xReturn = pxTCB->pxTaskTag;
-		}
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-		return xReturn;
-	}
-
-#endif /* configUSE_APPLICATION_TASK_TAG */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_APPLICATION_TASK_TAG == 1 )
-
-	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
-	{
-	TCB_t *xTCB;
-	BaseType_t xReturn;
-
-		/* If xTask is NULL then we are calling our own task hook. */
-		if( xTask == NULL )
-		{
-			xTCB = pxCurrentTCB;
-		}
-		else
-		{
-			xTCB = xTask;
-		}
-
-		if( xTCB->pxTaskTag != NULL )
-		{
-			xReturn = xTCB->pxTaskTag( pvParameter );
-		}
-		else
-		{
-			xReturn = pdFAIL;
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_APPLICATION_TASK_TAG */
-/*-----------------------------------------------------------*/
-
-void vTaskSwitchContext( void )
-{
-	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
-	{
-		/* The scheduler is currently suspended - do not allow a context
-		switch. */
-		xYieldPending = pdTRUE;
-	}
-	else
-	{
-		xYieldPending = pdFALSE;
-		traceTASK_SWITCHED_OUT();
-
-		#if ( configGENERATE_RUN_TIME_STATS == 1 )
-		{
-			#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
-				portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
-			#else
-				ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
-			#endif
-
-			/* Add the amount of time the task has been running to the
-			accumulated time so far.  The time the task started running was
-			stored in ulTaskSwitchedInTime.  Note that there is no overflow
-			protection here so count values are only valid until the timer
-			overflows.  The guard against negative values is to protect
-			against suspect run time stat counter implementations - which
-			are provided by the application, not the kernel. */
-			if( ulTotalRunTime > ulTaskSwitchedInTime )
-			{
-				pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-			ulTaskSwitchedInTime = ulTotalRunTime;
-		}
-		#endif /* configGENERATE_RUN_TIME_STATS */
-
-		/* Check for stack overflow, if configured. */
-		taskCHECK_FOR_STACK_OVERFLOW();
-
-		/* Before the currently running task is switched out, save its errno. */
-		#if( configUSE_POSIX_ERRNO == 1 )
-		{
-			pxCurrentTCB->iTaskErrno = FreeRTOS_errno;
-		}
-		#endif
-
-		/* Select a new task to run using either the generic C or port
-		optimised asm code. */
-		taskSELECT_HIGHEST_PRIORITY_TASK(); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-		traceTASK_SWITCHED_IN();
-
-		/* After the new task is switched in, update the global errno. */
-		#if( configUSE_POSIX_ERRNO == 1 )
-		{
-			FreeRTOS_errno = pxCurrentTCB->iTaskErrno;
-		}
-		#endif
-
-		#if ( configUSE_NEWLIB_REENTRANT == 1 )
-		{
-			/* Switch Newlib's _impure_ptr variable to point to the _reent
-			structure specific to this task. */
-			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
-		}
-		#endif /* configUSE_NEWLIB_REENTRANT */
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
-{
-	configASSERT( pxEventList );
-
-	/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
-	SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
-
-	/* Place the event list item of the TCB in the appropriate event list.
-	This is placed in the list in priority order so the highest priority task
-	is the first to be woken by the event.  The queue that contains the event
-	list is locked, preventing simultaneous access from interrupts. */
-	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
-
-	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-}
-/*-----------------------------------------------------------*/
-
-void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
-{
-	configASSERT( pxEventList );
-
-	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
-	the event groups implementation. */
-	configASSERT( uxSchedulerSuspended != 0 );
-
-	/* Store the item value in the event list item.  It is safe to access the
-	event list item here as interrupts won't access the event list item of a
-	task that is not in the Blocked state. */
-	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
-
-	/* Place the event list item of the TCB at the end of the appropriate event
-	list.  It is safe to access the event list here because it is part of an
-	event group implementation - and interrupts don't access event groups
-	directly (instead they access them indirectly by pending function calls to
-	the task level). */
-	vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
-
-	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TIMERS == 1 )
-
-	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
-	{
-		configASSERT( pxEventList );
-
-		/* This function should not be called by application code hence the
-		'Restricted' in its name.  It is not part of the public API.  It is
-		designed for use by kernel code, and has special calling requirements -
-		it should be called with the scheduler suspended. */
-
-
-		/* Place the event list item of the TCB in the appropriate event list.
-		In this case it is assume that this is the only task that is going to
-		be waiting on this event list, so the faster vListInsertEnd() function
-		can be used in place of vListInsert. */
-		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
-
-		/* If the task should block indefinitely then set the block time to a
-		value that will be recognised as an indefinite delay inside the
-		prvAddCurrentTaskToDelayedList() function. */
-		if( xWaitIndefinitely != pdFALSE )
-		{
-			xTicksToWait = portMAX_DELAY;
-		}
-
-		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
-		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
-	}
-
-#endif /* configUSE_TIMERS */
-/*-----------------------------------------------------------*/
-
-BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
-{
-TCB_t *pxUnblockedTCB;
-BaseType_t xReturn;
-
-	/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
-	called from a critical section within an ISR. */
-
-	/* The event list is sorted in priority order, so the first in the list can
-	be removed as it is known to be the highest priority.  Remove the TCB from
-	the delayed list, and add it to the ready list.
-
-	If an event is for a queue that is locked then this function will never
-	get called - the lock count on the queue will get modified instead.  This
-	means exclusive access to the event list is guaranteed here.
-
-	This function assumes that a check has already been made to ensure that
-	pxEventList is not empty. */
-	pxUnblockedTCB = listGET_OWNER_OF_HEAD_ENTRY( pxEventList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-	configASSERT( pxUnblockedTCB );
-	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
-
-	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-	{
-		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
-		prvAddTaskToReadyList( pxUnblockedTCB );
-
-		#if( configUSE_TICKLESS_IDLE != 0 )
-		{
-			/* If a task is blocked on a kernel object then xNextTaskUnblockTime
-			might be set to the blocked task's time out time.  If the task is
-			unblocked for a reason other than a timeout xNextTaskUnblockTime is
-			normally left unchanged, because it is automatically reset to a new
-			value when the tick count equals xNextTaskUnblockTime.  However if
-			tickless idling is used it might be more important to enter sleep mode
-			at the earliest possible time - so reset xNextTaskUnblockTime here to
-			ensure it is updated at the earliest possible time. */
-			prvResetNextTaskUnblockTime();
-		}
-		#endif
-	}
-	else
-	{
-		/* The delayed and ready lists cannot be accessed, so hold this task
-		pending until the scheduler is resumed. */
-		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
-	}
-
-	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
-	{
-		/* Return true if the task removed from the event list has a higher
-		priority than the calling task.  This allows the calling task to know if
-		it should force a context switch now. */
-		xReturn = pdTRUE;
-
-		/* Mark that a yield is pending in case the user is not using the
-		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
-		xYieldPending = pdTRUE;
-	}
-	else
-	{
-		xReturn = pdFALSE;
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
-{
-TCB_t *pxUnblockedTCB;
-
-	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
-	the event flags implementation. */
-	configASSERT( uxSchedulerSuspended != pdFALSE );
-
-	/* Store the new item value in the event list. */
-	listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
-
-	/* Remove the event list form the event flag.  Interrupts do not access
-	event flags. */
-	pxUnblockedTCB = listGET_LIST_ITEM_OWNER( pxEventListItem ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-	configASSERT( pxUnblockedTCB );
-	( void ) uxListRemove( pxEventListItem );
-
-	/* Remove the task from the delayed list and add it to the ready list.  The
-	scheduler is suspended so interrupts will not be accessing the ready
-	lists. */
-	( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
-	prvAddTaskToReadyList( pxUnblockedTCB );
-
-	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
-	{
-		/* The unblocked task has a priority above that of the calling task, so
-		a context switch is required.  This function is called with the
-		scheduler suspended so xYieldPending is set so the context switch
-		occurs immediately that the scheduler is resumed (unsuspended). */
-		xYieldPending = pdTRUE;
-	}
-}
-/*-----------------------------------------------------------*/
-
-void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
-{
-	configASSERT( pxTimeOut );
-	taskENTER_CRITICAL();
-	{
-		pxTimeOut->xOverflowCount = xNumOfOverflows;
-		pxTimeOut->xTimeOnEntering = xTickCount;
-	}
-	taskEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-void vTaskInternalSetTimeOutState( TimeOut_t * const pxTimeOut )
-{
-	/* For internal use only as it does not use a critical section. */
-	pxTimeOut->xOverflowCount = xNumOfOverflows;
-	pxTimeOut->xTimeOnEntering = xTickCount;
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
-{
-BaseType_t xReturn;
-
-	configASSERT( pxTimeOut );
-	configASSERT( pxTicksToWait );
-
-	taskENTER_CRITICAL();
-	{
-		/* Minor optimisation.  The tick count cannot change in this block. */
-		const TickType_t xConstTickCount = xTickCount;
-		const TickType_t xElapsedTime = xConstTickCount - pxTimeOut->xTimeOnEntering;
-
-		#if( INCLUDE_xTaskAbortDelay == 1 )
-			if( pxCurrentTCB->ucDelayAborted != ( uint8_t ) pdFALSE )
-			{
-				/* The delay was aborted, which is not the same as a time out,
-				but has the same result. */
-				pxCurrentTCB->ucDelayAborted = pdFALSE;
-				xReturn = pdTRUE;
-			}
-			else
-		#endif
-
-		#if ( INCLUDE_vTaskSuspend == 1 )
-			if( *pxTicksToWait == portMAX_DELAY )
-			{
-				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
-				specified is the maximum block time then the task should block
-				indefinitely, and therefore never time out. */
-				xReturn = pdFALSE;
-			}
-			else
-		#endif
-
-		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
-		{
-			/* The tick count is greater than the time at which
-			vTaskSetTimeout() was called, but has also overflowed since
-			vTaskSetTimeOut() was called.  It must have wrapped all the way
-			around and gone past again. This passed since vTaskSetTimeout()
-			was called. */
-			xReturn = pdTRUE;
-		}
-		else if( xElapsedTime < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
-		{
-			/* Not a genuine timeout. Adjust parameters for time remaining. */
-			*pxTicksToWait -= xElapsedTime;
-			vTaskInternalSetTimeOutState( pxTimeOut );
-			xReturn = pdFALSE;
-		}
-		else
-		{
-			*pxTicksToWait = 0;
-			xReturn = pdTRUE;
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vTaskMissedYield( void )
-{
-	xYieldPending = pdTRUE;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
-	{
-	UBaseType_t uxReturn;
-	TCB_t const *pxTCB;
-
-		if( xTask != NULL )
-		{
-			pxTCB = xTask;
-			uxReturn = pxTCB->uxTaskNumber;
-		}
-		else
-		{
-			uxReturn = 0U;
-		}
-
-		return uxReturn;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
-	{
-	TCB_t * pxTCB;
-
-		if( xTask != NULL )
-		{
-			pxTCB = xTask;
-			pxTCB->uxTaskNumber = uxHandle;
-		}
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-
-/*
- * -----------------------------------------------------------
- * The Idle task.
- * ----------------------------------------------------------
- *
- * The portTASK_FUNCTION() macro is used to allow port/compiler specific
- * language extensions.  The equivalent prototype for this function is:
- *
- * void prvIdleTask( void *pvParameters );
- *
- */
-static portTASK_FUNCTION( prvIdleTask, pvParameters )
-{
-	/* Stop warnings. */
-	( void ) pvParameters;
-
-	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
-	SCHEDULER IS STARTED. **/
-
-	/* In case a task that has a secure context deletes itself, in which case
-	the idle task is responsible for deleting the task's secure context, if
-	any. */
-	portALLOCATE_SECURE_CONTEXT( configMINIMAL_SECURE_STACK_SIZE );
-
-	for( ;; )
-	{
-		/* See if any tasks have deleted themselves - if so then the idle task
-		is responsible for freeing the deleted task's TCB and stack. */
-		prvCheckTasksWaitingTermination();
-
-		#if ( configUSE_PREEMPTION == 0 )
-		{
-			/* If we are not using preemption we keep forcing a task switch to
-			see if any other task has become available.  If we are using
-			preemption we don't need to do this as any task becoming available
-			will automatically get the processor anyway. */
-			taskYIELD();
-		}
-		#endif /* configUSE_PREEMPTION */
-
-		#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
-		{
-			/* When using preemption tasks of equal priority will be
-			timesliced.  If a task that is sharing the idle priority is ready
-			to run then the idle task should yield before the end of the
-			timeslice.
-
-			A critical region is not required here as we are just reading from
-			the list, and an occasional incorrect value will not matter.  If
-			the ready list at the idle priority contains more than one task
-			then a task other than the idle task is ready to execute. */
-			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
-			{
-				taskYIELD();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
-
-		#if ( configUSE_IDLE_HOOK == 1 )
-		{
-			extern void vApplicationIdleHook( void );
-
-			/* Call the user defined function from within the idle task.  This
-			allows the application designer to add background functionality
-			without the overhead of a separate task.
-			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
-			CALL A FUNCTION THAT MIGHT BLOCK. */
-			vApplicationIdleHook();
-		}
-		#endif /* configUSE_IDLE_HOOK */
-
-		/* This conditional compilation should use inequality to 0, not equality
-		to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
-		user defined low power mode	implementations require
-		configUSE_TICKLESS_IDLE to be set to a value other than 1. */
-		#if ( configUSE_TICKLESS_IDLE != 0 )
-		{
-		TickType_t xExpectedIdleTime;
-
-			/* It is not desirable to suspend then resume the scheduler on
-			each iteration of the idle task.  Therefore, a preliminary
-			test of the expected idle time is performed without the
-			scheduler suspended.  The result here is not necessarily
-			valid. */
-			xExpectedIdleTime = prvGetExpectedIdleTime();
-
-			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
-			{
-				vTaskSuspendAll();
-				{
-					/* Now the scheduler is suspended, the expected idle
-					time can be sampled again, and this time its value can
-					be used. */
-					configASSERT( xNextTaskUnblockTime >= xTickCount );
-					xExpectedIdleTime = prvGetExpectedIdleTime();
-
-					/* Define the following macro to set xExpectedIdleTime to 0
-					if the application does not want
-					portSUPPRESS_TICKS_AND_SLEEP() to be called. */
-					configPRE_SUPPRESS_TICKS_AND_SLEEP_PROCESSING( xExpectedIdleTime );
-
-					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
-					{
-						traceLOW_POWER_IDLE_BEGIN();
-						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
-						traceLOW_POWER_IDLE_END();
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				( void ) xTaskResumeAll();
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* configUSE_TICKLESS_IDLE */
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TICKLESS_IDLE != 0 )
-
-	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
-	{
-	/* The idle task exists in addition to the application tasks. */
-	const UBaseType_t uxNonApplicationTasks = 1;
-	eSleepModeStatus eReturn = eStandardSleep;
-
-		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
-		{
-			/* A task was made ready while the scheduler was suspended. */
-			eReturn = eAbortSleep;
-		}
-		else if( xYieldPending != pdFALSE )
-		{
-			/* A yield was pended while the scheduler was suspended. */
-			eReturn = eAbortSleep;
-		}
-		else
-		{
-			/* If all the tasks are in the suspended list (which might mean they
-			have an infinite block time rather than actually being suspended)
-			then it is safe to turn all clocks off and just wait for external
-			interrupts. */
-			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
-			{
-				eReturn = eNoTasksWaitingTimeout;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-
-		return eReturn;
-	}
-
-#endif /* configUSE_TICKLESS_IDLE */
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-
-	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
-	{
-	TCB_t *pxTCB;
-
-		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
-		{
-			pxTCB = prvGetTCBFromHandle( xTaskToSet );
-			pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
-		}
-	}
-
-#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
-/*-----------------------------------------------------------*/
-
-#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
-
-	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
-	{
-	void *pvReturn = NULL;
-	TCB_t *pxTCB;
-
-		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
-		{
-			pxTCB = prvGetTCBFromHandle( xTaskToQuery );
-			pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
-		}
-		else
-		{
-			pvReturn = NULL;
-		}
-
-		return pvReturn;
-	}
-
-#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
-/*-----------------------------------------------------------*/
-
-#if ( portUSING_MPU_WRAPPERS == 1 )
-
-	void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
-	{
-	TCB_t *pxTCB;
-
-		/* If null is passed in here then we are modifying the MPU settings of
-		the calling task. */
-		pxTCB = prvGetTCBFromHandle( xTaskToModify );
-
-		vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
-	}
-
-#endif /* portUSING_MPU_WRAPPERS */
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseTaskLists( void )
-{
-UBaseType_t uxPriority;
-
-	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
-	{
-		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
-	}
-
-	vListInitialise( &xDelayedTaskList1 );
-	vListInitialise( &xDelayedTaskList2 );
-	vListInitialise( &xPendingReadyList );
-
-	#if ( INCLUDE_vTaskDelete == 1 )
-	{
-		vListInitialise( &xTasksWaitingTermination );
-	}
-	#endif /* INCLUDE_vTaskDelete */
-
-	#if ( INCLUDE_vTaskSuspend == 1 )
-	{
-		vListInitialise( &xSuspendedTaskList );
-	}
-	#endif /* INCLUDE_vTaskSuspend */
-
-	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
-	using list2. */
-	pxDelayedTaskList = &xDelayedTaskList1;
-	pxOverflowDelayedTaskList = &xDelayedTaskList2;
-}
-/*-----------------------------------------------------------*/
-
-static void prvCheckTasksWaitingTermination( void )
-{
-
-	/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
-
-	#if ( INCLUDE_vTaskDelete == 1 )
-	{
-		TCB_t *pxTCB;
-
-		/* uxDeletedTasksWaitingCleanUp is used to prevent taskENTER_CRITICAL()
-		being called too often in the idle task. */
-		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
-		{
-			taskENTER_CRITICAL();
-			{
-				pxTCB = listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-				--uxCurrentNumberOfTasks;
-				--uxDeletedTasksWaitingCleanUp;
-			}
-			taskEXIT_CRITICAL();
-
-			prvDeleteTCB( pxTCB );
-		}
-	}
-	#endif /* INCLUDE_vTaskDelete */
-}
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TRACE_FACILITY == 1 )
-
-	void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
-	{
-	TCB_t *pxTCB;
-
-		/* xTask is NULL then get the state of the calling task. */
-		pxTCB = prvGetTCBFromHandle( xTask );
-
-		pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
-		pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
-		pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
-		pxTaskStatus->pxStackBase = pxTCB->pxStack;
-		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
-
-		#if ( configUSE_MUTEXES == 1 )
-		{
-			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
-		}
-		#else
-		{
-			pxTaskStatus->uxBasePriority = 0;
-		}
-		#endif
-
-		#if ( configGENERATE_RUN_TIME_STATS == 1 )
-		{
-			pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
-		}
-		#else
-		{
-			pxTaskStatus->ulRunTimeCounter = 0;
-		}
-		#endif
-
-		/* Obtaining the task state is a little fiddly, so is only done if the
-		value of eState passed into this function is eInvalid - otherwise the
-		state is just set to whatever is passed in. */
-		if( eState != eInvalid )
-		{
-			if( pxTCB == pxCurrentTCB )
-			{
-				pxTaskStatus->eCurrentState = eRunning;
-			}
-			else
-			{
-				pxTaskStatus->eCurrentState = eState;
-
-				#if ( INCLUDE_vTaskSuspend == 1 )
-				{
-					/* If the task is in the suspended list then there is a
-					chance it is actually just blocked indefinitely - so really
-					it should be reported as being in the Blocked state. */
-					if( eState == eSuspended )
-					{
-						vTaskSuspendAll();
-						{
-							if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
-							{
-								pxTaskStatus->eCurrentState = eBlocked;
-							}
-						}
-						( void ) xTaskResumeAll();
-					}
-				}
-				#endif /* INCLUDE_vTaskSuspend */
-			}
-		}
-		else
-		{
-			pxTaskStatus->eCurrentState = eTaskGetState( pxTCB );
-		}
-
-		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
-		parameter is provided to allow it to be skipped. */
-		if( xGetFreeStackSpace != pdFALSE )
-		{
-			#if ( portSTACK_GROWTH > 0 )
-			{
-				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
-			}
-			#else
-			{
-				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
-			}
-			#endif
-		}
-		else
-		{
-			pxTaskStatus->usStackHighWaterMark = 0;
-		}
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
-	{
-	configLIST_VOLATILE TCB_t *pxNextTCB, *pxFirstTCB;
-	UBaseType_t uxTask = 0;
-
-		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
-		{
-			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
-			/* Populate an TaskStatus_t structure within the
-			pxTaskStatusArray array for each task that is referenced from
-			pxList.  See the definition of TaskStatus_t in task.h for the
-			meaning of each TaskStatus_t structure member. */
-			do
-			{
-				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
-				uxTask++;
-			} while( pxNextTCB != pxFirstTCB );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return uxTask;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) )
-
-	static configSTACK_DEPTH_TYPE prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
-	{
-	uint32_t ulCount = 0U;
-
-		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
-		{
-			pucStackByte -= portSTACK_GROWTH;
-			ulCount++;
-		}
-
-		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
-
-		return ( configSTACK_DEPTH_TYPE ) ulCount;
-	}
-
-#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark2 == 1 )
-
-	/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are the
-	same except for their return type.  Using configSTACK_DEPTH_TYPE allows the
-	user to determine the return type.  It gets around the problem of the value
-	overflowing on 8-bit types without breaking backward compatibility for
-	applications that expect an 8-bit return type. */
-	configSTACK_DEPTH_TYPE uxTaskGetStackHighWaterMark2( TaskHandle_t xTask )
-	{
-	TCB_t *pxTCB;
-	uint8_t *pucEndOfStack;
-	configSTACK_DEPTH_TYPE uxReturn;
-
-		/* uxTaskGetStackHighWaterMark() and uxTaskGetStackHighWaterMark2() are
-		the same except for their return type.  Using configSTACK_DEPTH_TYPE
-		allows the user to determine the return type.  It gets around the
-		problem of the value overflowing on 8-bit types without breaking
-		backward compatibility for applications that expect an 8-bit return
-		type. */
-
-		pxTCB = prvGetTCBFromHandle( xTask );
-
-		#if portSTACK_GROWTH < 0
-		{
-			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
-		}
-		#else
-		{
-			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
-		}
-		#endif
-
-		uxReturn = prvTaskCheckFreeStackSpace( pucEndOfStack );
-
-		return uxReturn;
-	}
-
-#endif /* INCLUDE_uxTaskGetStackHighWaterMark2 */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
-
-	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
-	{
-	TCB_t *pxTCB;
-	uint8_t *pucEndOfStack;
-	UBaseType_t uxReturn;
-
-		pxTCB = prvGetTCBFromHandle( xTask );
-
-		#if portSTACK_GROWTH < 0
-		{
-			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
-		}
-		#else
-		{
-			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
-		}
-		#endif
-
-		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
-
-		return uxReturn;
-	}
-
-#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
-/*-----------------------------------------------------------*/
-
-#if ( INCLUDE_vTaskDelete == 1 )
-
-	static void prvDeleteTCB( TCB_t *pxTCB )
-	{
-		/* This call is required specifically for the TriCore port.  It must be
-		above the vPortFree() calls.  The call is also used by ports/demos that
-		want to allocate and clean RAM statically. */
-		portCLEAN_UP_TCB( pxTCB );
-
-		/* Free up the memory allocated by the scheduler for the task.  It is up
-		to the task to free any memory allocated at the application level. */
-		#if ( configUSE_NEWLIB_REENTRANT == 1 )
-		{
-			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
-		}
-		#endif /* configUSE_NEWLIB_REENTRANT */
-
-		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
-		{
-			/* The task can only have been allocated dynamically - free both
-			the stack and TCB. */
-			vPortFree( pxTCB->pxStack );
-			vPortFree( pxTCB );
-		}
-		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 ) /*lint !e731 !e9029 Macro has been consolidated for readability reasons. */
-		{
-			/* The task could have been allocated statically or dynamically, so
-			check what was statically allocated before trying to free the
-			memory. */
-			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
-			{
-				/* Both the stack and TCB were allocated dynamically, so both
-				must be freed. */
-				vPortFree( pxTCB->pxStack );
-				vPortFree( pxTCB );
-			}
-			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
-			{
-				/* Only the stack was statically allocated, so the TCB is the
-				only memory that must be freed. */
-				vPortFree( pxTCB );
-			}
-			else
-			{
-				/* Neither the stack nor the TCB were allocated dynamically, so
-				nothing needs to be freed. */
-				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	);
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-	}
-
-#endif /* INCLUDE_vTaskDelete */
-/*-----------------------------------------------------------*/
-
-static void prvResetNextTaskUnblockTime( void )
-{
-TCB_t *pxTCB;
-
-	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
-	{
-		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
-		the maximum possible value so it is	extremely unlikely that the
-		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
-		there is an item in the delayed list. */
-		xNextTaskUnblockTime = portMAX_DELAY;
-	}
-	else
-	{
-		/* The new current delayed list is not empty, get the value of
-		the item at the head of the delayed list.  This is the time at
-		which the task at the head of the delayed list should be removed
-		from the Blocked state. */
-		( pxTCB ) = listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList ); /*lint !e9079 void * is used as this macro is used with timers and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
-	}
-}
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
-
-	TaskHandle_t xTaskGetCurrentTaskHandle( void )
-	{
-	TaskHandle_t xReturn;
-
-		/* A critical section is not required as this is not called from
-		an interrupt and the current TCB will always be the same for any
-		individual execution thread. */
-		xReturn = pxCurrentTCB;
-
-		return xReturn;
-	}
-
-#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
-
-	BaseType_t xTaskGetSchedulerState( void )
-	{
-	BaseType_t xReturn;
-
-		if( xSchedulerRunning == pdFALSE )
-		{
-			xReturn = taskSCHEDULER_NOT_STARTED;
-		}
-		else
-		{
-			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-			{
-				xReturn = taskSCHEDULER_RUNNING;
-			}
-			else
-			{
-				xReturn = taskSCHEDULER_SUSPENDED;
-			}
-		}
-
-		return xReturn;
-	}
-
-#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-	BaseType_t xTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
-	{
-	TCB_t * const pxMutexHolderTCB = pxMutexHolder;
-	BaseType_t xReturn = pdFALSE;
-
-		/* If the mutex was given back by an interrupt while the queue was
-		locked then the mutex holder might now be NULL.  _RB_ Is this still
-		needed as interrupts can no longer use mutexes? */
-		if( pxMutexHolder != NULL )
-		{
-			/* If the holder of the mutex has a priority below the priority of
-			the task attempting to obtain the mutex then it will temporarily
-			inherit the priority of the task attempting to obtain the mutex. */
-			if( pxMutexHolderTCB->uxPriority < pxCurrentTCB->uxPriority )
-			{
-				/* Adjust the mutex holder state to account for its new
-				priority.  Only reset the event list item value if the value is
-				not being used for anything else. */
-				if( ( listGET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
-				{
-					listSET_LIST_ITEM_VALUE( &( pxMutexHolderTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-
-				/* If the task being modified is in the ready state it will need
-				to be moved into a new list. */
-				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxMutexHolderTCB->uxPriority ] ), &( pxMutexHolderTCB->xStateListItem ) ) != pdFALSE )
-				{
-					if( uxListRemove( &( pxMutexHolderTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-					{
-						taskRESET_READY_PRIORITY( pxMutexHolderTCB->uxPriority );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* Inherit the priority before being moved into the new list. */
-					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
-					prvAddTaskToReadyList( pxMutexHolderTCB );
-				}
-				else
-				{
-					/* Just inherit the priority. */
-					pxMutexHolderTCB->uxPriority = pxCurrentTCB->uxPriority;
-				}
-
-				traceTASK_PRIORITY_INHERIT( pxMutexHolderTCB, pxCurrentTCB->uxPriority );
-
-				/* Inheritance occurred. */
-				xReturn = pdTRUE;
-			}
-			else
-			{
-				if( pxMutexHolderTCB->uxBasePriority < pxCurrentTCB->uxPriority )
-				{
-					/* The base priority of the mutex holder is lower than the
-					priority of the task attempting to take the mutex, but the
-					current priority of the mutex holder is not lower than the
-					priority of the task attempting to take the mutex.
-					Therefore the mutex holder must have already inherited a
-					priority, but inheritance would have occurred if that had
-					not been the case. */
-					xReturn = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
-	{
-	TCB_t * const pxTCB = pxMutexHolder;
-	BaseType_t xReturn = pdFALSE;
-
-		if( pxMutexHolder != NULL )
-		{
-			/* A task can only have an inherited priority if it holds the mutex.
-			If the mutex is held by a task then it cannot be given from an
-			interrupt, and if a mutex is given by the holding task then it must
-			be the running state task. */
-			configASSERT( pxTCB == pxCurrentTCB );
-			configASSERT( pxTCB->uxMutexesHeld );
-			( pxTCB->uxMutexesHeld )--;
-
-			/* Has the holder of the mutex inherited the priority of another
-			task? */
-			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
-			{
-				/* Only disinherit if no other mutexes are held. */
-				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
-				{
-					/* A task can only have an inherited priority if it holds
-					the mutex.  If the mutex is held by a task then it cannot be
-					given from an interrupt, and if a mutex is given by the
-					holding task then it must be the running state task.  Remove
-					the holding task from the ready list. */
-					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-					{
-						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* Disinherit the priority before adding the task into the
-					new	ready list. */
-					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
-					pxTCB->uxPriority = pxTCB->uxBasePriority;
-
-					/* Reset the event list item value.  It cannot be in use for
-					any other purpose if this task is running, and it must be
-					running to give back the mutex. */
-					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-					prvAddTaskToReadyList( pxTCB );
-
-					/* Return true to indicate that a context switch is required.
-					This is only actually required in the corner case whereby
-					multiple mutexes were held and the mutexes were given back
-					in an order different to that in which they were taken.
-					If a context switch did not occur when the first mutex was
-					returned, even if a task was waiting on it, then a context
-					switch should occur when the last mutex is returned whether
-					a task is waiting on it or not. */
-					xReturn = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-
-		return xReturn;
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-	void vTaskPriorityDisinheritAfterTimeout( TaskHandle_t const pxMutexHolder, UBaseType_t uxHighestPriorityWaitingTask )
-	{
-	TCB_t * const pxTCB = pxMutexHolder;
-	UBaseType_t uxPriorityUsedOnEntry, uxPriorityToUse;
-	const UBaseType_t uxOnlyOneMutexHeld = ( UBaseType_t ) 1;
-
-		if( pxMutexHolder != NULL )
-		{
-			/* If pxMutexHolder is not NULL then the holder must hold at least
-			one mutex. */
-			configASSERT( pxTCB->uxMutexesHeld );
-
-			/* Determine the priority to which the priority of the task that
-			holds the mutex should be set.  This will be the greater of the
-			holding task's base priority and the priority of the highest
-			priority task that is waiting to obtain the mutex. */
-			if( pxTCB->uxBasePriority < uxHighestPriorityWaitingTask )
-			{
-				uxPriorityToUse = uxHighestPriorityWaitingTask;
-			}
-			else
-			{
-				uxPriorityToUse = pxTCB->uxBasePriority;
-			}
-
-			/* Does the priority need to change? */
-			if( pxTCB->uxPriority != uxPriorityToUse )
-			{
-				/* Only disinherit if no other mutexes are held.  This is a
-				simplification in the priority inheritance implementation.  If
-				the task that holds the mutex is also holding other mutexes then
-				the other mutexes may have caused the priority inheritance. */
-				if( pxTCB->uxMutexesHeld == uxOnlyOneMutexHeld )
-				{
-					/* If a task has timed out because it already holds the
-					mutex it was trying to obtain then it cannot of inherited
-					its own priority. */
-					configASSERT( pxTCB != pxCurrentTCB );
-
-					/* Disinherit the priority, remembering the previous
-					priority to facilitate determining the subject task's
-					state. */
-					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
-					uxPriorityUsedOnEntry = pxTCB->uxPriority;
-					pxTCB->uxPriority = uxPriorityToUse;
-
-					/* Only reset the event list item value if the value is not
-					being used for anything else. */
-					if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
-					{
-						listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriorityToUse ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-
-					/* If the running task is not the task that holds the mutex
-					then the task that holds the mutex could be in either the
-					Ready, Blocked or Suspended states.  Only remove the task
-					from its current state list if it is in the Ready state as
-					the task's priority is going to change and there is one
-					Ready list per priority. */
-					if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
-					{
-						if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-						{
-							taskRESET_READY_PRIORITY( pxTCB->uxPriority );
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-
-						prvAddTaskToReadyList( pxTCB );
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if ( portCRITICAL_NESTING_IN_TCB == 1 )
-
-	void vTaskEnterCritical( void )
-	{
-		portDISABLE_INTERRUPTS();
-
-		if( xSchedulerRunning != pdFALSE )
-		{
-			( pxCurrentTCB->uxCriticalNesting )++;
-
-			/* This is not the interrupt safe version of the enter critical
-			function so	assert() if it is being called from an interrupt
-			context.  Only API functions that end in "FromISR" can be used in an
-			interrupt.  Only assert if the critical nesting count is 1 to
-			protect against recursive calls if the assert function also uses a
-			critical section. */
-			if( pxCurrentTCB->uxCriticalNesting == 1 )
-			{
-				portASSERT_IF_IN_ISR();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* portCRITICAL_NESTING_IN_TCB */
-/*-----------------------------------------------------------*/
-
-#if ( portCRITICAL_NESTING_IN_TCB == 1 )
-
-	void vTaskExitCritical( void )
-	{
-		if( xSchedulerRunning != pdFALSE )
-		{
-			if( pxCurrentTCB->uxCriticalNesting > 0U )
-			{
-				( pxCurrentTCB->uxCriticalNesting )--;
-
-				if( pxCurrentTCB->uxCriticalNesting == 0U )
-				{
-					portENABLE_INTERRUPTS();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* portCRITICAL_NESTING_IN_TCB */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
-
-	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
-	{
-	size_t x;
-
-		/* Start by copying the entire string. */
-		strcpy( pcBuffer, pcTaskName );
-
-		/* Pad the end of the string with spaces to ensure columns line up when
-		printed out. */
-		for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
-		{
-			pcBuffer[ x ] = ' ';
-		}
-
-		/* Terminate. */
-		pcBuffer[ x ] = ( char ) 0x00;
-
-		/* Return the new end of string. */
-		return &( pcBuffer[ x ] );
-	}
-
-#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
-/*-----------------------------------------------------------*/
-
-#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-	void vTaskList( char * pcWriteBuffer )
-	{
-	TaskStatus_t *pxTaskStatusArray;
-	UBaseType_t uxArraySize, x;
-	char cStatus;
-
-		/*
-		 * PLEASE NOTE:
-		 *
-		 * This function is provided for convenience only, and is used by many
-		 * of the demo applications.  Do not consider it to be part of the
-		 * scheduler.
-		 *
-		 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
-		 * uxTaskGetSystemState() output into a human readable table that
-		 * displays task names, states and stack usage.
-		 *
-		 * vTaskList() has a dependency on the sprintf() C library function that
-		 * might bloat the code size, use a lot of stack, and provide different
-		 * results on different platforms.  An alternative, tiny, third party,
-		 * and limited functionality implementation of sprintf() is provided in
-		 * many of the FreeRTOS/Demo sub-directories in a file called
-		 * printf-stdarg.c (note printf-stdarg.c does not provide a full
-		 * snprintf() implementation!).
-		 *
-		 * It is recommended that production systems call uxTaskGetSystemState()
-		 * directly to get access to raw stats data, rather than indirectly
-		 * through a call to vTaskList().
-		 */
-
-
-		/* Make sure the write buffer does not contain a string. */
-		*pcWriteBuffer = ( char ) 0x00;
-
-		/* Take a snapshot of the number of tasks in case it changes while this
-		function is executing. */
-		uxArraySize = uxCurrentNumberOfTasks;
-
-		/* Allocate an array index for each task.  NOTE!  if
-		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
-		equate to NULL. */
-		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
-
-		if( pxTaskStatusArray != NULL )
-		{
-			/* Generate the (binary) data. */
-			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
-
-			/* Create a human readable table from the binary data. */
-			for( x = 0; x < uxArraySize; x++ )
-			{
-				switch( pxTaskStatusArray[ x ].eCurrentState )
-				{
-					case eRunning:		cStatus = tskRUNNING_CHAR;
-										break;
-
-					case eReady:		cStatus = tskREADY_CHAR;
-										break;
-
-					case eBlocked:		cStatus = tskBLOCKED_CHAR;
-										break;
-
-					case eSuspended:	cStatus = tskSUSPENDED_CHAR;
-										break;
-
-					case eDeleted:		cStatus = tskDELETED_CHAR;
-										break;
-
-					case eInvalid:		/* Fall through. */
-					default:			/* Should not get here, but it is included
-										to prevent static checking errors. */
-										cStatus = ( char ) 0x00;
-										break;
-				}
-
-				/* Write the task name to the string, padding with spaces so it
-				can be printed in tabular form more easily. */
-				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
-
-				/* Write the rest of the string. */
-				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
-				pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
-			}
-
-			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
-			is 0 then vPortFree() will be #defined to nothing. */
-			vPortFree( pxTaskStatusArray );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
-/*----------------------------------------------------------*/
-
-#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
-
-	void vTaskGetRunTimeStats( char *pcWriteBuffer )
-	{
-	TaskStatus_t *pxTaskStatusArray;
-	UBaseType_t uxArraySize, x;
-	uint32_t ulTotalTime, ulStatsAsPercentage;
-
-		#if( configUSE_TRACE_FACILITY != 1 )
-		{
-			#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
-		}
-		#endif
-
-		/*
-		 * PLEASE NOTE:
-		 *
-		 * This function is provided for convenience only, and is used by many
-		 * of the demo applications.  Do not consider it to be part of the
-		 * scheduler.
-		 *
-		 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
-		 * of the uxTaskGetSystemState() output into a human readable table that
-		 * displays the amount of time each task has spent in the Running state
-		 * in both absolute and percentage terms.
-		 *
-		 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
-		 * function that might bloat the code size, use a lot of stack, and
-		 * provide different results on different platforms.  An alternative,
-		 * tiny, third party, and limited functionality implementation of
-		 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
-		 * a file called printf-stdarg.c (note printf-stdarg.c does not provide
-		 * a full snprintf() implementation!).
-		 *
-		 * It is recommended that production systems call uxTaskGetSystemState()
-		 * directly to get access to raw stats data, rather than indirectly
-		 * through a call to vTaskGetRunTimeStats().
-		 */
-
-		/* Make sure the write buffer does not contain a string. */
-		*pcWriteBuffer = ( char ) 0x00;
-
-		/* Take a snapshot of the number of tasks in case it changes while this
-		function is executing. */
-		uxArraySize = uxCurrentNumberOfTasks;
-
-		/* Allocate an array index for each task.  NOTE!  If
-		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
-		equate to NULL. */
-		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) ); /*lint !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack and this allocation allocates a struct that has the alignment requirements of a pointer. */
-
-		if( pxTaskStatusArray != NULL )
-		{
-			/* Generate the (binary) data. */
-			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
-
-			/* For percentage calculations. */
-			ulTotalTime /= 100UL;
-
-			/* Avoid divide by zero errors. */
-			if( ulTotalTime > 0UL )
-			{
-				/* Create a human readable table from the binary data. */
-				for( x = 0; x < uxArraySize; x++ )
-				{
-					/* What percentage of the total run time has the task used?
-					This will always be rounded down to the nearest integer.
-					ulTotalRunTimeDiv100 has already been divided by 100. */
-					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
-
-					/* Write the task name to the string, padding with
-					spaces so it can be printed in tabular form more
-					easily. */
-					pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
-
-					if( ulStatsAsPercentage > 0UL )
-					{
-						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
-						{
-							sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
-						}
-						#else
-						{
-							/* sizeof( int ) == sizeof( long ) so a smaller
-							printf() library can be used. */
-							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
-						}
-						#endif
-					}
-					else
-					{
-						/* If the percentage is zero here then the task has
-						consumed less than 1% of the total run time. */
-						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
-						{
-							sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
-						}
-						#else
-						{
-							/* sizeof( int ) == sizeof( long ) so a smaller
-							printf() library can be used. */
-							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter ); /*lint !e586 sprintf() allowed as this is compiled with many compilers and this is a utility function only - not part of the core kernel implementation. */
-						}
-						#endif
-					}
-
-					pcWriteBuffer += strlen( pcWriteBuffer ); /*lint !e9016 Pointer arithmetic ok on char pointers especially as in this case where it best denotes the intent of the code. */
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
-			is 0 then vPortFree() will be #defined to nothing. */
-			vPortFree( pxTaskStatusArray );
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) ) */
-/*-----------------------------------------------------------*/
-
-TickType_t uxTaskResetEventItemValue( void )
-{
-TickType_t uxReturn;
-
-	uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
-
-	/* Reset the event list item to its normal value - so it can be used with
-	queues and semaphores. */
-	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-
-	return uxReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_MUTEXES == 1 )
-
-	TaskHandle_t pvTaskIncrementMutexHeldCount( void )
-	{
-		/* If xSemaphoreCreateMutex() is called before any tasks have been created
-		then pxCurrentTCB will be NULL. */
-		if( pxCurrentTCB != NULL )
-		{
-			( pxCurrentTCB->uxMutexesHeld )++;
-		}
-
-		return pxCurrentTCB;
-	}
-
-#endif /* configUSE_MUTEXES */
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-
-	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
-	{
-	uint32_t ulReturn;
-
-		taskENTER_CRITICAL();
-		{
-			/* Only block if the notification count is not already non-zero. */
-			if( pxCurrentTCB->ulNotifiedValue == 0UL )
-			{
-				/* Mark this task as waiting for a notification. */
-				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
-
-				if( xTicksToWait > ( TickType_t ) 0 )
-				{
-					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-					traceTASK_NOTIFY_TAKE_BLOCK();
-
-					/* All ports are written to allow a yield in a critical
-					section (some will yield immediately, others wait until the
-					critical section exits) - but it is not something that
-					application code should ever do. */
-					portYIELD_WITHIN_API();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		taskENTER_CRITICAL();
-		{
-			traceTASK_NOTIFY_TAKE();
-			ulReturn = pxCurrentTCB->ulNotifiedValue;
-
-			if( ulReturn != 0UL )
-			{
-				if( xClearCountOnExit != pdFALSE )
-				{
-					pxCurrentTCB->ulNotifiedValue = 0UL;
-				}
-				else
-				{
-					pxCurrentTCB->ulNotifiedValue = ulReturn - ( uint32_t ) 1;
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
-		}
-		taskEXIT_CRITICAL();
-
-		return ulReturn;
-	}
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-
-	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
-	{
-	BaseType_t xReturn;
-
-		taskENTER_CRITICAL();
-		{
-			/* Only block if a notification is not already pending. */
-			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
-			{
-				/* Clear bits in the task's notification value as bits may get
-				set	by the notifying task or interrupt.  This can be used to
-				clear the value to zero. */
-				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
-
-				/* Mark this task as waiting for a notification. */
-				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
-
-				if( xTicksToWait > ( TickType_t ) 0 )
-				{
-					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
-					traceTASK_NOTIFY_WAIT_BLOCK();
-
-					/* All ports are written to allow a yield in a critical
-					section (some will yield immediately, others wait until the
-					critical section exits) - but it is not something that
-					application code should ever do. */
-					portYIELD_WITHIN_API();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		taskENTER_CRITICAL();
-		{
-			traceTASK_NOTIFY_WAIT();
-
-			if( pulNotificationValue != NULL )
-			{
-				/* Output the current notification value, which may or may not
-				have changed. */
-				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
-			}
-
-			/* If ucNotifyValue is set then either the task never entered the
-			blocked state (because a notification was already pending) or the
-			task unblocked because of a notification.  Otherwise the task
-			unblocked because of a timeout. */
-			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
-			{
-				/* A notification was not received. */
-				xReturn = pdFALSE;
-			}
-			else
-			{
-				/* A notification was already pending or a notification was
-				received while the task was waiting. */
-				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
-				xReturn = pdTRUE;
-			}
-
-			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
-		}
-		taskEXIT_CRITICAL();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-
-	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
-	{
-	TCB_t * pxTCB;
-	BaseType_t xReturn = pdPASS;
-	uint8_t ucOriginalNotifyState;
-
-		configASSERT( xTaskToNotify );
-		pxTCB = xTaskToNotify;
-
-		taskENTER_CRITICAL();
-		{
-			if( pulPreviousNotificationValue != NULL )
-			{
-				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
-			}
-
-			ucOriginalNotifyState = pxTCB->ucNotifyState;
-
-			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
-
-			switch( eAction )
-			{
-				case eSetBits	:
-					pxTCB->ulNotifiedValue |= ulValue;
-					break;
-
-				case eIncrement	:
-					( pxTCB->ulNotifiedValue )++;
-					break;
-
-				case eSetValueWithOverwrite	:
-					pxTCB->ulNotifiedValue = ulValue;
-					break;
-
-				case eSetValueWithoutOverwrite :
-					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
-					{
-						pxTCB->ulNotifiedValue = ulValue;
-					}
-					else
-					{
-						/* The value could not be written to the task. */
-						xReturn = pdFAIL;
-					}
-					break;
-
-				case eNoAction:
-					/* The task is being notified without its notify value being
-					updated. */
-					break;
-
-				default:
-					/* Should not get here if all enums are handled.
-					Artificially force an assert by testing a value the
-					compiler can't assume is const. */
-					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
-
-					break;
-			}
-
-			traceTASK_NOTIFY();
-
-			/* If the task is in the blocked state specifically to wait for a
-			notification then unblock it now. */
-			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
-			{
-				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-				prvAddTaskToReadyList( pxTCB );
-
-				/* The task should not have been on an event list. */
-				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
-
-				#if( configUSE_TICKLESS_IDLE != 0 )
-				{
-					/* If a task is blocked waiting for a notification then
-					xNextTaskUnblockTime might be set to the blocked task's time
-					out time.  If the task is unblocked for a reason other than
-					a timeout xNextTaskUnblockTime is normally left unchanged,
-					because it will automatically get reset to a new value when
-					the tick count equals xNextTaskUnblockTime.  However if
-					tickless idling is used it might be more important to enter
-					sleep mode at the earliest possible time - so reset
-					xNextTaskUnblockTime here to ensure it is updated at the
-					earliest possible time. */
-					prvResetNextTaskUnblockTime();
-				}
-				#endif
-
-				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-				{
-					/* The notified task has a priority above the currently
-					executing task so a yield is required. */
-					taskYIELD_IF_USING_PREEMPTION();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-
-	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
-	{
-	TCB_t * pxTCB;
-	uint8_t ucOriginalNotifyState;
-	BaseType_t xReturn = pdPASS;
-	UBaseType_t uxSavedInterruptStatus;
-
-		configASSERT( xTaskToNotify );
-
-		/* RTOS ports that support interrupt nesting have the concept of a
-		maximum	system call (or maximum API call) interrupt priority.
-		Interrupts that are	above the maximum system call priority are keep
-		permanently enabled, even when the RTOS kernel is in a critical section,
-		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
-		is defined in FreeRTOSConfig.h then
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-		failure if a FreeRTOS API function is called from an interrupt that has
-		been assigned a priority above the configured maximum system call
-		priority.  Only FreeRTOS functions that end in FromISR can be called
-		from interrupts	that have been assigned a priority at or (logically)
-		below the maximum system call interrupt priority.  FreeRTOS maintains a
-		separate interrupt safe API to ensure interrupt entry is as fast and as
-		simple as possible.  More information (albeit Cortex-M specific) is
-		provided on the following link:
-		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-		pxTCB = xTaskToNotify;
-
-		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-		{
-			if( pulPreviousNotificationValue != NULL )
-			{
-				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
-			}
-
-			ucOriginalNotifyState = pxTCB->ucNotifyState;
-			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
-
-			switch( eAction )
-			{
-				case eSetBits	:
-					pxTCB->ulNotifiedValue |= ulValue;
-					break;
-
-				case eIncrement	:
-					( pxTCB->ulNotifiedValue )++;
-					break;
-
-				case eSetValueWithOverwrite	:
-					pxTCB->ulNotifiedValue = ulValue;
-					break;
-
-				case eSetValueWithoutOverwrite :
-					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
-					{
-						pxTCB->ulNotifiedValue = ulValue;
-					}
-					else
-					{
-						/* The value could not be written to the task. */
-						xReturn = pdFAIL;
-					}
-					break;
-
-				case eNoAction :
-					/* The task is being notified without its notify value being
-					updated. */
-					break;
-
-				default:
-					/* Should not get here if all enums are handled.
-					Artificially force an assert by testing a value the
-					compiler can't assume is const. */
-					configASSERT( pxTCB->ulNotifiedValue == ~0UL );
-					break;
-			}
-
-			traceTASK_NOTIFY_FROM_ISR();
-
-			/* If the task is in the blocked state specifically to wait for a
-			notification then unblock it now. */
-			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
-			{
-				/* The task should not have been on an event list. */
-				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
-
-				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-				{
-					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-					prvAddTaskToReadyList( pxTCB );
-				}
-				else
-				{
-					/* The delayed and ready lists cannot be accessed, so hold
-					this task pending until the scheduler is resumed. */
-					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
-				}
-
-				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-				{
-					/* The notified task has a priority above the currently
-					executing task so a yield is required. */
-					if( pxHigherPriorityTaskWoken != NULL )
-					{
-						*pxHigherPriorityTaskWoken = pdTRUE;
-					}
-
-					/* Mark that a yield is pending in case the user is not
-					using the "xHigherPriorityTaskWoken" parameter to an ISR
-					safe FreeRTOS function. */
-					xYieldPending = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-
-		return xReturn;
-	}
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-
-	void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
-	{
-	TCB_t * pxTCB;
-	uint8_t ucOriginalNotifyState;
-	UBaseType_t uxSavedInterruptStatus;
-
-		configASSERT( xTaskToNotify );
-
-		/* RTOS ports that support interrupt nesting have the concept of a
-		maximum	system call (or maximum API call) interrupt priority.
-		Interrupts that are	above the maximum system call priority are keep
-		permanently enabled, even when the RTOS kernel is in a critical section,
-		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
-		is defined in FreeRTOSConfig.h then
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
-		failure if a FreeRTOS API function is called from an interrupt that has
-		been assigned a priority above the configured maximum system call
-		priority.  Only FreeRTOS functions that end in FromISR can be called
-		from interrupts	that have been assigned a priority at or (logically)
-		below the maximum system call interrupt priority.  FreeRTOS maintains a
-		separate interrupt safe API to ensure interrupt entry is as fast and as
-		simple as possible.  More information (albeit Cortex-M specific) is
-		provided on the following link:
-		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
-		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
-
-		pxTCB = xTaskToNotify;
-
-		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
-		{
-			ucOriginalNotifyState = pxTCB->ucNotifyState;
-			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
-
-			/* 'Giving' is equivalent to incrementing a count in a counting
-			semaphore. */
-			( pxTCB->ulNotifiedValue )++;
-
-			traceTASK_NOTIFY_GIVE_FROM_ISR();
-
-			/* If the task is in the blocked state specifically to wait for a
-			notification then unblock it now. */
-			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
-			{
-				/* The task should not have been on an event list. */
-				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
-
-				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
-				{
-					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
-					prvAddTaskToReadyList( pxTCB );
-				}
-				else
-				{
-					/* The delayed and ready lists cannot be accessed, so hold
-					this task pending until the scheduler is resumed. */
-					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
-				}
-
-				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
-				{
-					/* The notified task has a priority above the currently
-					executing task so a yield is required. */
-					if( pxHigherPriorityTaskWoken != NULL )
-					{
-						*pxHigherPriorityTaskWoken = pdTRUE;
-					}
-
-					/* Mark that a yield is pending in case the user is not
-					using the "xHigherPriorityTaskWoken" parameter in an ISR
-					safe FreeRTOS function. */
-					xYieldPending = pdTRUE;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
-	}
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-
-/*-----------------------------------------------------------*/
-
-#if( configUSE_TASK_NOTIFICATIONS == 1 )
-
-	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
-	{
-	TCB_t *pxTCB;
-	BaseType_t xReturn;
-
-		/* If null is passed in here then it is the calling task that is having
-		its notification state cleared. */
-		pxTCB = prvGetTCBFromHandle( xTask );
-
-		taskENTER_CRITICAL();
-		{
-			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
-			{
-				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
-				xReturn = pdPASS;
-			}
-			else
-			{
-				xReturn = pdFAIL;
-			}
-		}
-		taskEXIT_CRITICAL();
-
-		return xReturn;
-	}
-
-#endif /* configUSE_TASK_NOTIFICATIONS */
-/*-----------------------------------------------------------*/
-
-#if( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( INCLUDE_xTaskGetIdleTaskHandle == 1 ) )
-	TickType_t xTaskGetIdleRunTimeCounter( void )
-	{
-		return xIdleTaskHandle->ulRunTimeCounter;
-	}
-#endif
-/*-----------------------------------------------------------*/
-
-static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
-{
-TickType_t xTimeToWake;
-const TickType_t xConstTickCount = xTickCount;
-
-	#if( INCLUDE_xTaskAbortDelay == 1 )
-	{
-		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
-		reset to pdFALSE so it can be detected as having been set to pdTRUE
-		when the task leaves the Blocked state. */
-		pxCurrentTCB->ucDelayAborted = pdFALSE;
-	}
-	#endif
-
-	/* Remove the task from the ready list before adding it to the blocked list
-	as the same list item is used for both lists. */
-	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
-	{
-		/* The current task must be in a ready list, so there is no need to
-		check, and the port reset macro can be called directly. */
-		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority ); /*lint !e931 pxCurrentTCB cannot change as it is the calling task.  pxCurrentTCB->uxPriority and uxTopReadyPriority cannot change as called with scheduler suspended or in a critical section. */
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	#if ( INCLUDE_vTaskSuspend == 1 )
-	{
-		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
-		{
-			/* Add the task to the suspended task list instead of a delayed task
-			list to ensure it is not woken by a timing event.  It will block
-			indefinitely. */
-			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
-		}
-		else
-		{
-			/* Calculate the time at which the task should be woken if the event
-			does not occur.  This may overflow but this doesn't matter, the
-			kernel will manage it correctly. */
-			xTimeToWake = xConstTickCount + xTicksToWait;
-
-			/* The list item will be inserted in wake time order. */
-			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
-
-			if( xTimeToWake < xConstTickCount )
-			{
-				/* Wake time has overflowed.  Place this item in the overflow
-				list. */
-				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
-			}
-			else
-			{
-				/* The wake time has not overflowed, so the current block list
-				is used. */
-				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
-
-				/* If the task entering the blocked state was placed at the
-				head of the list of blocked tasks then xNextTaskUnblockTime
-				needs to be updated too. */
-				if( xTimeToWake < xNextTaskUnblockTime )
-				{
-					xNextTaskUnblockTime = xTimeToWake;
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-	}
-	#else /* INCLUDE_vTaskSuspend */
-	{
-		/* Calculate the time at which the task should be woken if the event
-		does not occur.  This may overflow but this doesn't matter, the kernel
-		will manage it correctly. */
-		xTimeToWake = xConstTickCount + xTicksToWait;
-
-		/* The list item will be inserted in wake time order. */
-		listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
-
-		if( xTimeToWake < xConstTickCount )
-		{
-			/* Wake time has overflowed.  Place this item in the overflow list. */
-			vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
-		}
-		else
-		{
-			/* The wake time has not overflowed, so the current block list is used. */
-			vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
-
-			/* If the task entering the blocked state was placed at the head of the
-			list of blocked tasks then xNextTaskUnblockTime needs to be updated
-			too. */
-			if( xTimeToWake < xNextTaskUnblockTime )
-			{
-				xNextTaskUnblockTime = xTimeToWake;
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-
-		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
-		( void ) xCanBlockIndefinitely;
-	}
-	#endif /* INCLUDE_vTaskSuspend */
-}
-
-/* Code below here allows additional code to be inserted into this source file,
-especially where access to file scope functions and data is needed (for example
-when performing module tests). */
-
-#ifdef FREERTOS_MODULE_TEST
-	#include "tasks_test_access_functions.h"
-#endif
-
-
-#if( configINCLUDE_FREERTOS_TASK_C_ADDITIONS_H == 1 )
-
-	#include "freertos_tasks_c_additions.h"
-
-	#ifdef FREERTOS_TASKS_C_ADDITIONS_INIT
-		static void freertos_tasks_c_additions_init( void )
-		{
-			FREERTOS_TASKS_C_ADDITIONS_INIT();
-		}
-	#endif
-
-#endif
-
-
diff --git a/FreeRTOS/Source/timers.c b/FreeRTOS/Source/timers.c
deleted file mode 100755
index ad18f3e..0000000
--- a/FreeRTOS/Source/timers.c
+++ /dev/null
@@ -1,1102 +0,0 @@
-/*
- * FreeRTOS Kernel V10.2.1
- * Copyright (C) 2019 Amazon.com, Inc. or its affiliates.  All Rights Reserved.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy of
- * this software and associated documentation files (the "Software"), to deal in
- * the Software without restriction, including without limitation the rights to
- * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
- * the Software, and to permit persons to whom the Software is furnished to do so,
- * subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in all
- * copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
- * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
- * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
- * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- *
- * http://www.FreeRTOS.org
- * http://aws.amazon.com/freertos
- *
- * 1 tab == 4 spaces!
- */
-
-/* Standard includes. */
-#include 
-
-/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
-all the API functions to use the MPU wrappers.  That should only be done when
-task.h is included from an application file. */
-#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
-
-#include "FreeRTOS.h"
-#include "task.h"
-#include "queue.h"
-#include "timers.h"
-
-#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
-	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
-#endif
-
-/* Lint e9021, e961 and e750 are suppressed as a MISRA exception justified
-because the MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined
-for the header files above, but not in this file, in order to generate the
-correct privileged Vs unprivileged linkage and placement. */
-#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e9021 !e961 !e750. */
-
-
-/* This entire source file will be skipped if the application is not configured
-to include software timer functionality.  This #if is closed at the very bottom
-of this file.  If you want to include software timer functionality then ensure
-configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
-#if ( configUSE_TIMERS == 1 )
-
-/* Misc definitions. */
-#define tmrNO_DELAY		( TickType_t ) 0U
-
-/* The name assigned to the timer service task.  This can be overridden by
-defining trmTIMER_SERVICE_TASK_NAME in FreeRTOSConfig.h. */
-#ifndef configTIMER_SERVICE_TASK_NAME
-	#define configTIMER_SERVICE_TASK_NAME "Tmr Svc"
-#endif
-
-/* Bit definitions used in the ucStatus member of a timer structure. */
-#define tmrSTATUS_IS_ACTIVE					( ( uint8_t ) 0x01 )
-#define tmrSTATUS_IS_STATICALLY_ALLOCATED	( ( uint8_t ) 0x02 )
-#define tmrSTATUS_IS_AUTORELOAD				( ( uint8_t ) 0x04 )
-
-/* The definition of the timers themselves. */
-typedef struct tmrTimerControl /* The old naming convention is used to prevent breaking kernel aware debuggers. */
-{
-	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
-	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
-	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
-	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
-	#if( configUSE_TRACE_FACILITY == 1 )
-		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
-	#endif
-	uint8_t 				ucStatus;			/*<< Holds bits to say if the timer was statically allocated or not, and if it is active or not. */
-} xTIMER;
-
-/* The old xTIMER name is maintained above then typedefed to the new Timer_t
-name below to enable the use of older kernel aware debuggers. */
-typedef xTIMER Timer_t;
-
-/* The definition of messages that can be sent and received on the timer queue.
-Two types of message can be queued - messages that manipulate a software timer,
-and messages that request the execution of a non-timer related callback.  The
-two message types are defined in two separate structures, xTimerParametersType
-and xCallbackParametersType respectively. */
-typedef struct tmrTimerParameters
-{
-	TickType_t			xMessageValue;		/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
-	Timer_t *			pxTimer;			/*<< The timer to which the command will be applied. */
-} TimerParameter_t;
-
-
-typedef struct tmrCallbackParameters
-{
-	PendedFunction_t	pxCallbackFunction;	/* << The callback function to execute. */
-	void *pvParameter1;						/* << The value that will be used as the callback functions first parameter. */
-	uint32_t ulParameter2;					/* << The value that will be used as the callback functions second parameter. */
-} CallbackParameters_t;
-
-/* The structure that contains the two message types, along with an identifier
-that is used to determine which message type is valid. */
-typedef struct tmrTimerQueueMessage
-{
-	BaseType_t			xMessageID;			/*<< The command being sent to the timer service task. */
-	union
-	{
-		TimerParameter_t xTimerParameters;
-
-		/* Don't include xCallbackParameters if it is not going to be used as
-		it makes the structure (and therefore the timer queue) larger. */
-		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
-			CallbackParameters_t xCallbackParameters;
-		#endif /* INCLUDE_xTimerPendFunctionCall */
-	} u;
-} DaemonTaskMessage_t;
-
-/*lint -save -e956 A manual analysis and inspection has been used to determine
-which static variables must be declared volatile. */
-
-/* The list in which active timers are stored.  Timers are referenced in expire
-time order, with the nearest expiry time at the front of the list.  Only the
-timer service task is allowed to access these lists.
-xActiveTimerList1 and xActiveTimerList2 could be at function scope but that
-breaks some kernel aware debuggers, and debuggers that reply on removing the
-static qualifier. */
-PRIVILEGED_DATA static List_t xActiveTimerList1;
-PRIVILEGED_DATA static List_t xActiveTimerList2;
-PRIVILEGED_DATA static List_t *pxCurrentTimerList;
-PRIVILEGED_DATA static List_t *pxOverflowTimerList;
-
-/* A queue that is used to send commands to the timer service task. */
-PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
-PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
-
-/*lint -restore */
-
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-	/* If static allocation is supported then the application must provide the
-	following callback function - which enables the application to optionally
-	provide the memory that will be used by the timer task as the task's stack
-	and TCB. */
-	extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
-
-#endif
-
-/*
- * Initialise the infrastructure used by the timer service task if it has not
- * been initialised already.
- */
-static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
-
-/*
- * The timer service task (daemon).  Timer functionality is controlled by this
- * task.  Other tasks communicate with the timer service task using the
- * xTimerQueue queue.
- */
-static portTASK_FUNCTION_PROTO( prvTimerTask, pvParameters ) PRIVILEGED_FUNCTION;
-
-/*
- * Called by the timer service task to interpret and process a command it
- * received on the timer queue.
- */
-static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
- * depending on if the expire time causes a timer counter overflow.
- */
-static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
-
-/*
- * An active timer has reached its expire time.  Reload the timer if it is an
- * auto reload timer, then call its callback.
- */
-static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
-
-/*
- * The tick count has overflowed.  Switch the timer lists after ensuring the
- * current timer list does not still reference some timers.
- */
-static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
-
-/*
- * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
- * if a tick count overflow occurred since prvSampleTimeNow() was last called.
- */
-static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
-
-/*
- * If the timer list contains any active timers then return the expire time of
- * the timer that will expire first and set *pxListWasEmpty to false.  If the
- * timer list does not contain any timers then return 0 and set *pxListWasEmpty
- * to pdTRUE.
- */
-static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
-
-/*
- * If a timer has expired, process it.  Otherwise, block the timer service task
- * until either a timer does expire or a command is received.
- */
-static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
-
-/*
- * Called after a Timer_t structure has been allocated either statically or
- * dynamically to fill in the structure's members.
- */
-static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-									const TickType_t xTimerPeriodInTicks,
-									const UBaseType_t uxAutoReload,
-									void * const pvTimerID,
-									TimerCallbackFunction_t pxCallbackFunction,
-									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION;
-/*-----------------------------------------------------------*/
-
-BaseType_t xTimerCreateTimerTask( void )
-{
-BaseType_t xReturn = pdFAIL;
-
-	/* This function is called when the scheduler is started if
-	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
-	timer service task has been created/initialised.  If timers have already
-	been created then the initialisation will already have been performed. */
-	prvCheckForValidListAndQueue();
-
-	if( xTimerQueue != NULL )
-	{
-		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-		{
-			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
-			StackType_t *pxTimerTaskStackBuffer = NULL;
-			uint32_t ulTimerTaskStackSize;
-
-			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
-			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
-													configTIMER_SERVICE_TASK_NAME,
-													ulTimerTaskStackSize,
-													NULL,
-													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
-													pxTimerTaskStackBuffer,
-													pxTimerTaskTCBBuffer );
-
-			if( xTimerTaskHandle != NULL )
-			{
-				xReturn = pdPASS;
-			}
-		}
-		#else
-		{
-			xReturn = xTaskCreate(	prvTimerTask,
-									configTIMER_SERVICE_TASK_NAME,
-									configTIMER_TASK_STACK_DEPTH,
-									NULL,
-									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
-									&xTimerTaskHandle );
-		}
-		#endif /* configSUPPORT_STATIC_ALLOCATION */
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	configASSERT( xReturn );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-
-	TimerHandle_t xTimerCreate(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-								const TickType_t xTimerPeriodInTicks,
-								const UBaseType_t uxAutoReload,
-								void * const pvTimerID,
-								TimerCallbackFunction_t pxCallbackFunction )
-	{
-	Timer_t *pxNewTimer;
-
-		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) ); /*lint !e9087 !e9079 All values returned by pvPortMalloc() have at least the alignment required by the MCU's stack, and the first member of Timer_t is always a pointer to the timer's mame. */
-
-		if( pxNewTimer != NULL )
-		{
-			/* Status is thus far zero as the timer is not created statically
-			and has not been started.  The autoreload bit may get set in
-			prvInitialiseNewTimer. */
-			pxNewTimer->ucStatus = 0x00;
-			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
-		}
-
-		return pxNewTimer;
-	}
-
-#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-
-	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,		/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-										const TickType_t xTimerPeriodInTicks,
-										const UBaseType_t uxAutoReload,
-										void * const pvTimerID,
-										TimerCallbackFunction_t pxCallbackFunction,
-										StaticTimer_t *pxTimerBuffer )
-	{
-	Timer_t *pxNewTimer;
-
-		#if( configASSERT_DEFINED == 1 )
-		{
-			/* Sanity check that the size of the structure used to declare a
-			variable of type StaticTimer_t equals the size of the real timer
-			structure. */
-			volatile size_t xSize = sizeof( StaticTimer_t );
-			configASSERT( xSize == sizeof( Timer_t ) );
-			( void ) xSize; /* Keeps lint quiet when configASSERT() is not defined. */
-		}
-		#endif /* configASSERT_DEFINED */
-
-		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
-		configASSERT( pxTimerBuffer );
-		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 !e9087 StaticTimer_t is a pointer to a Timer_t, so guaranteed to be aligned and sized correctly (checked by an assert()), so this is safe. */
-
-		if( pxNewTimer != NULL )
-		{
-			/* Timers can be created statically or dynamically so note this
-			timer was created statically in case it is later deleted.  The
-			autoreload bit may get set in prvInitialiseNewTimer(). */
-			pxNewTimer->ucStatus = tmrSTATUS_IS_STATICALLY_ALLOCATED;
-
-			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
-		}
-
-		return pxNewTimer;
-	}
-
-#endif /* configSUPPORT_STATIC_ALLOCATION */
-/*-----------------------------------------------------------*/
-
-static void prvInitialiseNewTimer(	const char * const pcTimerName,			/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-									const TickType_t xTimerPeriodInTicks,
-									const UBaseType_t uxAutoReload,
-									void * const pvTimerID,
-									TimerCallbackFunction_t pxCallbackFunction,
-									Timer_t *pxNewTimer )
-{
-	/* 0 is not a valid value for xTimerPeriodInTicks. */
-	configASSERT( ( xTimerPeriodInTicks > 0 ) );
-
-	if( pxNewTimer != NULL )
-	{
-		/* Ensure the infrastructure used by the timer service task has been
-		created/initialised. */
-		prvCheckForValidListAndQueue();
-
-		/* Initialise the timer structure members using the function
-		parameters. */
-		pxNewTimer->pcTimerName = pcTimerName;
-		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
-		pxNewTimer->pvTimerID = pvTimerID;
-		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
-		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
-		if( uxAutoReload != pdFALSE )
-		{
-			pxNewTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
-		}
-		traceTIMER_CREATE( pxNewTimer );
-	}
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
-{
-BaseType_t xReturn = pdFAIL;
-DaemonTaskMessage_t xMessage;
-
-	configASSERT( xTimer );
-
-	/* Send a message to the timer service task to perform a particular action
-	on a particular timer definition. */
-	if( xTimerQueue != NULL )
-	{
-		/* Send a command to the timer service task to start the xTimer timer. */
-		xMessage.xMessageID = xCommandID;
-		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
-		xMessage.u.xTimerParameters.pxTimer = xTimer;
-
-		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
-		{
-			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
-			{
-				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
-			}
-			else
-			{
-				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
-			}
-		}
-		else
-		{
-			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
-		}
-
-		traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
-	}
-	else
-	{
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
-{
-	/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
-	started, then xTimerTaskHandle will be NULL. */
-	configASSERT( ( xTimerTaskHandle != NULL ) );
-	return xTimerTaskHandle;
-}
-/*-----------------------------------------------------------*/
-
-TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
-{
-Timer_t *pxTimer = xTimer;
-
-	configASSERT( xTimer );
-	return pxTimer->xTimerPeriodInTicks;
-}
-/*-----------------------------------------------------------*/
-
-void vTimerSetReloadMode( TimerHandle_t xTimer, const UBaseType_t uxAutoReload )
-{
-Timer_t * pxTimer =  xTimer;
-
-	configASSERT( xTimer );
-	taskENTER_CRITICAL();
-	{
-		if( uxAutoReload != pdFALSE )
-		{
-			pxTimer->ucStatus |= tmrSTATUS_IS_AUTORELOAD;
-		}
-		else
-		{
-			pxTimer->ucStatus &= ~tmrSTATUS_IS_AUTORELOAD;
-		}
-	}
-	taskEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
-{
-Timer_t * pxTimer =  xTimer;
-TickType_t xReturn;
-
-	configASSERT( xTimer );
-	xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
-	return xReturn;
-}
-/*-----------------------------------------------------------*/
-
-const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
-{
-Timer_t *pxTimer = xTimer;
-
-	configASSERT( xTimer );
-	return pxTimer->pcTimerName;
-}
-/*-----------------------------------------------------------*/
-
-static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
-{
-BaseType_t xResult;
-Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-
-	/* Remove the timer from the list of active timers.  A check has already
-	been performed to ensure the list is not empty. */
-	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
-	traceTIMER_EXPIRED( pxTimer );
-
-	/* If the timer is an auto reload timer then calculate the next
-	expiry time and re-insert the timer in the list of active timers. */
-	if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
-	{
-		/* The timer is inserted into a list using a time relative to anything
-		other than the current time.  It will therefore be inserted into the
-		correct list relative to the time this task thinks it is now. */
-		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
-		{
-			/* The timer expired before it was added to the active timer
-			list.  Reload it now.  */
-			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
-			configASSERT( xResult );
-			( void ) xResult;
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	else
-	{
-		pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
-		mtCOVERAGE_TEST_MARKER();
-	}
-
-	/* Call the timer callback. */
-	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
-}
-/*-----------------------------------------------------------*/
-
-static portTASK_FUNCTION( prvTimerTask, pvParameters )
-{
-TickType_t xNextExpireTime;
-BaseType_t xListWasEmpty;
-
-	/* Just to avoid compiler warnings. */
-	( void ) pvParameters;
-
-	#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
-	{
-		extern void vApplicationDaemonTaskStartupHook( void );
-
-		/* Allow the application writer to execute some code in the context of
-		this task at the point the task starts executing.  This is useful if the
-		application includes initialisation code that would benefit from
-		executing after the scheduler has been started. */
-		vApplicationDaemonTaskStartupHook();
-	}
-	#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
-
-	for( ;; )
-	{
-		/* Query the timers list to see if it contains any timers, and if so,
-		obtain the time at which the next timer will expire. */
-		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
-
-		/* If a timer has expired, process it.  Otherwise, block this task
-		until either a timer does expire, or a command is received. */
-		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
-
-		/* Empty the command queue. */
-		prvProcessReceivedCommands();
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
-{
-TickType_t xTimeNow;
-BaseType_t xTimerListsWereSwitched;
-
-	vTaskSuspendAll();
-	{
-		/* Obtain the time now to make an assessment as to whether the timer
-		has expired or not.  If obtaining the time causes the lists to switch
-		then don't process this timer as any timers that remained in the list
-		when the lists were switched will have been processed within the
-		prvSampleTimeNow() function. */
-		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
-		if( xTimerListsWereSwitched == pdFALSE )
-		{
-			/* The tick count has not overflowed, has the timer expired? */
-			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
-			{
-				( void ) xTaskResumeAll();
-				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
-			}
-			else
-			{
-				/* The tick count has not overflowed, and the next expire
-				time has not been reached yet.  This task should therefore
-				block to wait for the next expire time or a command to be
-				received - whichever comes first.  The following line cannot
-				be reached unless xNextExpireTime > xTimeNow, except in the
-				case when the current timer list is empty. */
-				if( xListWasEmpty != pdFALSE )
-				{
-					/* The current timer list is empty - is the overflow list
-					also empty? */
-					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
-				}
-
-				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
-
-				if( xTaskResumeAll() == pdFALSE )
-				{
-					/* Yield to wait for either a command to arrive, or the
-					block time to expire.  If a command arrived between the
-					critical section being exited and this yield then the yield
-					will not cause the task to block. */
-					portYIELD_WITHIN_API();
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-		}
-		else
-		{
-			( void ) xTaskResumeAll();
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
-{
-TickType_t xNextExpireTime;
-
-	/* Timers are listed in expiry time order, with the head of the list
-	referencing the task that will expire first.  Obtain the time at which
-	the timer with the nearest expiry time will expire.  If there are no
-	active timers then just set the next expire time to 0.  That will cause
-	this task to unblock when the tick count overflows, at which point the
-	timer lists will be switched and the next expiry time can be
-	re-assessed.  */
-	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
-	if( *pxListWasEmpty == pdFALSE )
-	{
-		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
-	}
-	else
-	{
-		/* Ensure the task unblocks when the tick count rolls over. */
-		xNextExpireTime = ( TickType_t ) 0U;
-	}
-
-	return xNextExpireTime;
-}
-/*-----------------------------------------------------------*/
-
-static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
-{
-TickType_t xTimeNow;
-PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
-
-	xTimeNow = xTaskGetTickCount();
-
-	if( xTimeNow < xLastTime )
-	{
-		prvSwitchTimerLists();
-		*pxTimerListsWereSwitched = pdTRUE;
-	}
-	else
-	{
-		*pxTimerListsWereSwitched = pdFALSE;
-	}
-
-	xLastTime = xTimeNow;
-
-	return xTimeNow;
-}
-/*-----------------------------------------------------------*/
-
-static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
-{
-BaseType_t xProcessTimerNow = pdFALSE;
-
-	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
-	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
-
-	if( xNextExpiryTime <= xTimeNow )
-	{
-		/* Has the expiry time elapsed between the command to start/reset a
-		timer was issued, and the time the command was processed? */
-		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
-		{
-			/* The time between a command being issued and the command being
-			processed actually exceeds the timers period.  */
-			xProcessTimerNow = pdTRUE;
-		}
-		else
-		{
-			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
-		}
-	}
-	else
-	{
-		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
-		{
-			/* If, since the command was issued, the tick count has overflowed
-			but the expiry time has not, then the timer must have already passed
-			its expiry time and should be processed immediately. */
-			xProcessTimerNow = pdTRUE;
-		}
-		else
-		{
-			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
-		}
-	}
-
-	return xProcessTimerNow;
-}
-/*-----------------------------------------------------------*/
-
-static void	prvProcessReceivedCommands( void )
-{
-DaemonTaskMessage_t xMessage;
-Timer_t *pxTimer;
-BaseType_t xTimerListsWereSwitched, xResult;
-TickType_t xTimeNow;
-
-	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
-	{
-		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
-		{
-			/* Negative commands are pended function calls rather than timer
-			commands. */
-			if( xMessage.xMessageID < ( BaseType_t ) 0 )
-			{
-				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
-
-				/* The timer uses the xCallbackParameters member to request a
-				callback be executed.  Check the callback is not NULL. */
-				configASSERT( pxCallback );
-
-				/* Call the function. */
-				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-		}
-		#endif /* INCLUDE_xTimerPendFunctionCall */
-
-		/* Commands that are positive are timer commands rather than pended
-		function calls. */
-		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
-		{
-			/* The messages uses the xTimerParameters member to work on a
-			software timer. */
-			pxTimer = xMessage.u.xTimerParameters.pxTimer;
-
-			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE ) /*lint !e961. The cast is only redundant when NULL is passed into the macro. */
-			{
-				/* The timer is in a list, remove it. */
-				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
-			}
-			else
-			{
-				mtCOVERAGE_TEST_MARKER();
-			}
-
-			traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
-
-			/* In this case the xTimerListsWereSwitched parameter is not used, but
-			it must be present in the function call.  prvSampleTimeNow() must be
-			called after the message is received from xTimerQueue so there is no
-			possibility of a higher priority task adding a message to the message
-			queue with a time that is ahead of the timer daemon task (because it
-			pre-empted the timer daemon task after the xTimeNow value was set). */
-			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
-
-			switch( xMessage.xMessageID )
-			{
-				case tmrCOMMAND_START :
-				case tmrCOMMAND_START_FROM_ISR :
-				case tmrCOMMAND_RESET :
-				case tmrCOMMAND_RESET_FROM_ISR :
-				case tmrCOMMAND_START_DONT_TRACE :
-					/* Start or restart a timer. */
-					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
-					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
-					{
-						/* The timer expired before it was added to the active
-						timer list.  Process it now. */
-						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
-						traceTIMER_EXPIRED( pxTimer );
-
-						if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
-						{
-							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
-							configASSERT( xResult );
-							( void ) xResult;
-						}
-						else
-						{
-							mtCOVERAGE_TEST_MARKER();
-						}
-					}
-					else
-					{
-						mtCOVERAGE_TEST_MARKER();
-					}
-					break;
-
-				case tmrCOMMAND_STOP :
-				case tmrCOMMAND_STOP_FROM_ISR :
-					/* The timer has already been removed from the active list. */
-					pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
-					break;
-
-				case tmrCOMMAND_CHANGE_PERIOD :
-				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
-					pxTimer->ucStatus |= tmrSTATUS_IS_ACTIVE;
-					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
-					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
-
-					/* The new period does not really have a reference, and can
-					be longer or shorter than the old one.  The command time is
-					therefore set to the current time, and as the period cannot
-					be zero the next expiry time can only be in the future,
-					meaning (unlike for the xTimerStart() case above) there is
-					no fail case that needs to be handled here. */
-					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
-					break;
-
-				case tmrCOMMAND_DELETE :
-					#if ( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
-					{
-						/* The timer has already been removed from the active list,
-						just free up the memory if the memory was dynamically
-						allocated. */
-						if( ( pxTimer->ucStatus & tmrSTATUS_IS_STATICALLY_ALLOCATED ) == ( uint8_t ) 0 )
-						{
-							vPortFree( pxTimer );
-						}
-						else
-						{
-							pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
-						}
-					}
-					#else
-					{
-						/* If dynamic allocation is not enabled, the memory
-						could not have been dynamically allocated. So there is
-						no need to free the memory - just mark the timer as
-						"not active". */
-						pxTimer->ucStatus &= ~tmrSTATUS_IS_ACTIVE;
-					}
-					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
-					break;
-
-				default	:
-					/* Don't expect to get here. */
-					break;
-			}
-		}
-	}
-}
-/*-----------------------------------------------------------*/
-
-static void prvSwitchTimerLists( void )
-{
-TickType_t xNextExpireTime, xReloadTime;
-List_t *pxTemp;
-Timer_t *pxTimer;
-BaseType_t xResult;
-
-	/* The tick count has overflowed.  The timer lists must be switched.
-	If there are any timers still referenced from the current timer list
-	then they must have expired and should be processed before the lists
-	are switched. */
-	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
-	{
-		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
-
-		/* Remove the timer from the list. */
-		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList ); /*lint !e9087 !e9079 void * is used as this macro is used with tasks and co-routines too.  Alignment is known to be fine as the type of the pointer stored and retrieved is the same. */
-		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
-		traceTIMER_EXPIRED( pxTimer );
-
-		/* Execute its callback, then send a command to restart the timer if
-		it is an auto-reload timer.  It cannot be restarted here as the lists
-		have not yet been switched. */
-		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
-
-		if( ( pxTimer->ucStatus & tmrSTATUS_IS_AUTORELOAD ) != 0 )
-		{
-			/* Calculate the reload value, and if the reload value results in
-			the timer going into the same timer list then it has already expired
-			and the timer should be re-inserted into the current list so it is
-			processed again within this loop.  Otherwise a command should be sent
-			to restart the timer to ensure it is only inserted into a list after
-			the lists have been swapped. */
-			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
-			if( xReloadTime > xNextExpireTime )
-			{
-				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
-				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
-				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
-			}
-			else
-			{
-				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
-				configASSERT( xResult );
-				( void ) xResult;
-			}
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-
-	pxTemp = pxCurrentTimerList;
-	pxCurrentTimerList = pxOverflowTimerList;
-	pxOverflowTimerList = pxTemp;
-}
-/*-----------------------------------------------------------*/
-
-static void prvCheckForValidListAndQueue( void )
-{
-	/* Check that the list from which active timers are referenced, and the
-	queue used to communicate with the timer service, have been
-	initialised. */
-	taskENTER_CRITICAL();
-	{
-		if( xTimerQueue == NULL )
-		{
-			vListInitialise( &xActiveTimerList1 );
-			vListInitialise( &xActiveTimerList2 );
-			pxCurrentTimerList = &xActiveTimerList1;
-			pxOverflowTimerList = &xActiveTimerList2;
-
-			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
-			{
-				/* The timer queue is allocated statically in case
-				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
-				static StaticQueue_t xStaticTimerQueue; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
-				static uint8_t ucStaticTimerQueueStorage[ ( size_t ) configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ]; /*lint !e956 Ok to declare in this manner to prevent additional conditional compilation guards in other locations. */
-
-				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, ( UBaseType_t ) sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
-			}
-			#else
-			{
-				xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
-			}
-			#endif
-
-			#if ( configQUEUE_REGISTRY_SIZE > 0 )
-			{
-				if( xTimerQueue != NULL )
-				{
-					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
-				}
-				else
-				{
-					mtCOVERAGE_TEST_MARKER();
-				}
-			}
-			#endif /* configQUEUE_REGISTRY_SIZE */
-		}
-		else
-		{
-			mtCOVERAGE_TEST_MARKER();
-		}
-	}
-	taskEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
-{
-BaseType_t xReturn;
-Timer_t *pxTimer = xTimer;
-
-	configASSERT( xTimer );
-
-	/* Is the timer in the list of active timers? */
-	taskENTER_CRITICAL();
-	{
-		if( ( pxTimer->ucStatus & tmrSTATUS_IS_ACTIVE ) == 0 )
-		{
-			xReturn = pdFALSE;
-		}
-		else
-		{
-			xReturn = pdTRUE;
-		}
-	}
-	taskEXIT_CRITICAL();
-
-	return xReturn;
-} /*lint !e818 Can't be pointer to const due to the typedef. */
-/*-----------------------------------------------------------*/
-
-void *pvTimerGetTimerID( const TimerHandle_t xTimer )
-{
-Timer_t * const pxTimer = xTimer;
-void *pvReturn;
-
-	configASSERT( xTimer );
-
-	taskENTER_CRITICAL();
-	{
-		pvReturn = pxTimer->pvTimerID;
-	}
-	taskEXIT_CRITICAL();
-
-	return pvReturn;
-}
-/*-----------------------------------------------------------*/
-
-void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
-{
-Timer_t * const pxTimer = xTimer;
-
-	configASSERT( xTimer );
-
-	taskENTER_CRITICAL();
-	{
-		pxTimer->pvTimerID = pvNewID;
-	}
-	taskEXIT_CRITICAL();
-}
-/*-----------------------------------------------------------*/
-
-#if( INCLUDE_xTimerPendFunctionCall == 1 )
-
-	BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
-	{
-	DaemonTaskMessage_t xMessage;
-	BaseType_t xReturn;
-
-		/* Complete the message with the function parameters and post it to the
-		daemon task. */
-		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
-		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
-		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
-		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
-
-		xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
-
-		tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
-
-		return xReturn;
-	}
-
-#endif /* INCLUDE_xTimerPendFunctionCall */
-/*-----------------------------------------------------------*/
-
-#if( INCLUDE_xTimerPendFunctionCall == 1 )
-
-	BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
-	{
-	DaemonTaskMessage_t xMessage;
-	BaseType_t xReturn;
-
-		/* This function can only be called after a timer has been created or
-		after the scheduler has been started because, until then, the timer
-		queue does not exist. */
-		configASSERT( xTimerQueue );
-
-		/* Complete the message with the function parameters and post it to the
-		daemon task. */
-		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
-		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
-		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
-		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
-
-		xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
-
-		tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
-
-		return xReturn;
-	}
-
-#endif /* INCLUDE_xTimerPendFunctionCall */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	UBaseType_t uxTimerGetTimerNumber( TimerHandle_t xTimer )
-	{
-		return ( ( Timer_t * ) xTimer )->uxTimerNumber;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-#if ( configUSE_TRACE_FACILITY == 1 )
-
-	void vTimerSetTimerNumber( TimerHandle_t xTimer, UBaseType_t uxTimerNumber )
-	{
-		( ( Timer_t * ) xTimer )->uxTimerNumber = uxTimerNumber;
-	}
-
-#endif /* configUSE_TRACE_FACILITY */
-/*-----------------------------------------------------------*/
-
-/* This entire source file will be skipped if the application is not configured
-to include software timer functionality.  If you want to include software timer
-functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
-#endif /* configUSE_TIMERS == 1 */
-
-
-