39 lines
982 B
XML
39 lines
982 B
XML
#Please do not modify this file by hand
|
|
XmpVersion: 13.1
|
|
VerMgmt: 13.1
|
|
IntStyle: default
|
|
MHS File: system.mhs
|
|
Architecture: spartan6
|
|
Device: xc6slx45t
|
|
Package: fgg484
|
|
SpeedGrade: -3
|
|
UserCmd1:
|
|
UserCmd1Type: 0
|
|
UserCmd2:
|
|
UserCmd2Type: 0
|
|
GenSimTB: 0
|
|
SdkExportBmmBit: 1
|
|
SdkExportDir: SDK/SDK_Export
|
|
InsertNoPads: 0
|
|
WarnForEAArch: 1
|
|
HdlLang: VHDL
|
|
SimModel: BEHAVIORAL
|
|
UcfFile: data/system.ucf
|
|
EnableParTimingError: 1
|
|
ShowLicenseDialog: 1
|
|
ICacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR
|
|
ICacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR
|
|
ICacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR
|
|
ICacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR
|
|
ICacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR
|
|
ICacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR
|
|
DCacheAddr: MCB_DDR3,C_S0_AXI_BASEADDR
|
|
DCacheAddr: MCB_DDR3,C_S1_AXI_BASEADDR
|
|
DCacheAddr: MCB_DDR3,C_S2_AXI_BASEADDR
|
|
DCacheAddr: MCB_DDR3,C_S3_AXI_BASEADDR
|
|
DCacheAddr: MCB_DDR3,C_S4_AXI_BASEADDR
|
|
DCacheAddr: MCB_DDR3,C_S5_AXI_BASEADDR
|
|
Processor: microblaze_0
|
|
ElfImp:
|
|
ElfSim:
|