161 lines
5.8 KiB
C
161 lines
5.8 KiB
C
/*
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FreeRTOS.org V4.0.4 - Copyright (C) 2003-2006 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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FreeRTOS.org is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FreeRTOS.org; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes FreeRTOS.org, without being obliged to provide
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the source code for any proprietary components. See the licensing section
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of http://www.FreeRTOS.org for full details of how and when the exception
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can be applied.
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***************************************************************************
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See http://www.FreeRTOS.org for documentation, latest information, license
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and contact details. Please ensure to read the configuration and relevant
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port sections of the online documentation.
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***************************************************************************
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*/
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/*
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BASIC INTERRUPT DRIVEN DRIVER FOR USB.
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This file contains all the usb components that must be compiled
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to ARM mode. The components that can be compiled to either ARM or THUMB
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mode are contained in USB-CDC.c.
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*/
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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#include "queue.h"
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/* Demo application includes. */
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#include "Board.h"
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#include "usb.h"
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#include "USB-CDC.h"
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#define usbINT_CLEAR_MASK (AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 )
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/*-----------------------------------------------------------*/
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/* Messages and queue used to communicate between the ISR and the USB task. */
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static xISRStatus xISRMessages[ usbQUEUE_LENGTH + 1 ];
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extern xQueueHandle xUSBInterruptQueue;
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/*-----------------------------------------------------------*/
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/* The ISR can cause a context switch so is declared naked. */
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void vUSB_ISR( void ) __attribute__ ((naked));
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/*-----------------------------------------------------------*/
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void vUSB_ISR( void )
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{
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/* This ISR can cause a context switch. Therefore a call to the
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portENTER_SWITCHING_ISR() macro is made. This must come BEFORE any
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stack variable declarations. */
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portENTER_SWITCHING_ISR();
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/* Now variables can be declared. */
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portCHAR cTaskWokenByPost = pdFALSE;
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static volatile unsigned portLONG ulNextMessage = 0;
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xISRStatus *pxMessage;
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unsigned portLONG ulRxBytes;
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unsigned portCHAR ucFifoIndex;
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/* Use the next message from the array. */
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pxMessage = &( xISRMessages[ ( ulNextMessage & usbQUEUE_LENGTH ) ] );
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ulNextMessage++;
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/* Save UDP ISR state for task-level processing. */
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pxMessage->ulISR = AT91C_BASE_UDP->UDP_ISR;
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pxMessage->ulCSR0 = AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ];
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/* Clear interrupts from ICR. */
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AT91C_BASE_UDP->UDP_ICR = AT91C_BASE_UDP->UDP_IMR | AT91C_UDP_ENDBUSRES;
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/* Process incoming FIFO data. Must set DIR (if needed) and clear RXSETUP
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before exit. */
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/* Read CSR and get incoming byte count. */
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ulRxBytes = ( pxMessage->ulCSR0 >> 16 ) & usbRX_COUNT_MASK;
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/* Receive control transfers on endpoint 0. */
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if( pxMessage->ulCSR0 & ( AT91C_UDP_RXSETUP | AT91C_UDP_RX_DATA_BK0 ) )
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{
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/* Save FIFO data buffer for either a SETUP or DATA stage */
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for( ucFifoIndex = 0; ucFifoIndex < ulRxBytes; ucFifoIndex++ )
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{
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pxMessage->ucFifoData[ ucFifoIndex ] = AT91C_BASE_UDP->UDP_FDR[ usbEND_POINT_0 ];
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}
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/* Set direction for data stage. Must be done before RXSETUP is
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cleared. */
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if( ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RXSETUP ) )
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{
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if( ulRxBytes && ( pxMessage->ucFifoData[ usbREQUEST_TYPE_INDEX ] & 0x80 ) )
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{
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] |= AT91C_UDP_DIR;
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/* Might not be wise in an ISR! */
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while( !(AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_DIR) );
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}
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/* Clear RXSETUP */
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~AT91C_UDP_RXSETUP;
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/* Might not be wise in an ISR! */
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while ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RXSETUP );
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}
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else
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{
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/* Clear RX_DATA_BK0 */
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~AT91C_UDP_RX_DATA_BK0;
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/* Might not be wise in an ISR! */
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while ( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] & AT91C_UDP_RX_DATA_BK0 );
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}
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}
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/* If we received data on endpoint 1, disable its interrupts until it is
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processed in the main loop */
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if( AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] & ( AT91C_UDP_RX_DATA_BK0 | AT91C_UDP_RX_DATA_BK1 ) )
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{
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AT91C_BASE_UDP->UDP_IDR = AT91C_UDP_EPINT1;
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}
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_0 ] &= ~( AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT );
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/* Clear interrupts for the other endpoints, retain data flags for endpoint
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1. */
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_1 ] &= ~( AT91C_UDP_TXCOMP | AT91C_UDP_STALLSENT | AT91C_UDP_RXSETUP );
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_2 ] &= ~usbINT_CLEAR_MASK;
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AT91C_BASE_UDP->UDP_CSR[ usbEND_POINT_3 ] &= ~usbINT_CLEAR_MASK;
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/* Post ISR data to queue for task-level processing */
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cTaskWokenByPost = xQueueSendFromISR( xUSBInterruptQueue, &pxMessage, cTaskWokenByPost );
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/* Clear AIC to complete ISR processing */
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AT91C_BASE_AIC->AIC_EOICR = 0;
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/* Do a task switch if needed */
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portEXIT_SWITCHING_ISR( cTaskWokenByPost )
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}
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