c4b4156fcf
When Link Time Optimization (LTO) is enabled, some of the LDR instructions result in out of range access. The reason is that the default generated literal pool is too far and not within the permissible range of 4K. This commit adds LTORG assembly instructions at required places to ensure that access to literals remain in the permissible range of 4K. Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com> |
||
|---|---|---|
| .. | ||
| ARM7_AT91FR40008 | ||
| ARM7_AT91SAM7S | ||
| ARM7_LPC23xx | ||
| ARM7_LPC2000 | ||
| ARM_CA9 | ||
| ARM_CA53_64_BIT | ||
| ARM_CM0 | ||
| ARM_CM3 | ||
| ARM_CM3_MPU | ||
| ARM_CM4_MPU | ||
| ARM_CM4F | ||
| ARM_CM7 | ||
| ARM_CM23 | ||
| ARM_CM23_NTZ/non_secure | ||
| ARM_CM33 | ||
| ARM_CM33_NTZ/non_secure | ||
| ARM_CR5 | ||
| ARM_CRx_No_GIC | ||
| ATMega323 | ||
| AVR32_UC3 | ||
| ColdFire_V2 | ||
| CORTUS_APS3 | ||
| H8S2329 | ||
| HCS12 | ||
| IA32_flat | ||
| MCF5235 | ||
| MicroBlaze | ||
| MicroBlazeV8 | ||
| MicroBlazeV9 | ||
| MSP430F449 | ||
| NiosII | ||
| PPC405_Xilinx | ||
| PPC440_Xilinx | ||
| RISC-V | ||
| RL78 | ||
| RX100 | ||
| RX600 | ||
| RX600v2 | ||
| STR75x | ||
| TriCore_1782 | ||