128 lines
4.1 KiB
Plaintext
128 lines
4.1 KiB
Plaintext
#include "FreeRTOSConfig.h"
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IVR_ADDR DEFINE 0xFFFFF818
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;*******************************************************************************
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; Import the Reset_Handler address from 71x_init.s
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;*******************************************************************************
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IMPORT __program_start
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;*******************************************************************************
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; Import exception handlers
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;*******************************************************************************
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IMPORT vPortYieldProcessor ; FreeRTOS SWI handler
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;*******************************************************************************
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; Import IRQ handlers from 71x_it.c
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;*******************************************************************************
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IMPORT vPortNonPreemptiveTick ; Cooperative FreeRTOS tick handler
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IMPORT vPortPreemptiveTickISR ; Preemptive FreeRTOS tick handler
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IMPORT vSerialISREntry ; Demo serial port handler
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;*******************************************************************************
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; Export Peripherals IRQ handlers table address
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;*******************************************************************************
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CODE32
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LDR PC, Reset_Addr
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LDR PC, Undefined_Addr
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LDR PC, SWI_Addr
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LDR PC, Prefetch_Addr
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LDR PC, Abort_Addr
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NOP ; Reserved vector
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LDR PC, =IVR_ADDR
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LDR PC, FIQ_Addr
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;*******************************************************************************
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; Exception handlers address table
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;*******************************************************************************
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Reset_Addr DCD __program_start
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Undefined_Addr DCD UndefinedHandler
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SWI_Addr DCD vPortYieldProcessor
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Prefetch_Addr DCD PrefetchAbortHandler
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Abort_Addr DCD DataAbortHandler
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DCD 0 ; Reserved vector
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IRQ_Addr DCD IRQHandler
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FIQ_Addr DCD FIQHandler
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;*******************************************************************************
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; Peripherals IRQ handlers address table
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;*******************************************************************************
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EXPORT T0TIMI_Addr
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T0TIMI_Addr DCD DefaultISR
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FLASH_Addr DCD DefaultISR
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RCCU_Addr DCD DefaultISR
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RTC_Addr DCD DefaultISR
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#if configUSE_PREEMPTION == 0
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WDG_Addr DCD vPortNonPreemptiveTick ; Tick ISR if the cooperative scheduler is used.
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#else
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WDG_Addr DCD vPortPreemptiveTickISR ; Tick ISR if the preemptive scheduler is used.
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#endif
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XTI_Addr DCD DefaultISR
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USBHP_Addr DCD DefaultISR
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I2C0ITERR_Addr DCD DefaultISR
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I2C1ITERR_ADDR DCD DefaultISR
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UART0_Addr DCD vSerialISREntry
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UART1_Addr DCD DefaultISR
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UART2_ADDR DCD DefaultISR
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UART3_ADDR DCD DefaultISR
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BSPI0_ADDR DCD DefaultISR
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BSPI1_Addr DCD DefaultISR
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I2C0_Addr DCD DefaultISR
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I2C1_Addr DCD DefaultISR
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CAN_Addr DCD DefaultISR
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ADC12_Addr DCD DefaultISR
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T1TIMI_Addr DCD DefaultISR
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T2TIMI_Addr DCD DefaultISR
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T3TIMI_Addr DCD DefaultISR
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DCD 0 ; reserved
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DCD 0 ; reserved
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DCD 0 ; reserved
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HDLC_Addr DCD DefaultISR
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USBLP_Addr DCD DefaultISR
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DCD 0 ; reserved
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DCD 0 ; reserved
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T0TOI_Addr DCD DefaultISR
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T0OC1_Addr DCD DefaultISR
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T0OC2_Addr DCD DefaultISR
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;*******************************************************************************
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; Exception Handlers
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;*******************************************************************************
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UndefinedHandler
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b UndefinedHandler
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PrefetchAbortHandler
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b PrefetchAbortHandler
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DataAbortHandler
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b DataAbortHandler
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IRQHandler
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b DefaultISR
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FIQHandler
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b FIQHandler
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DefaultISR
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b DefaultISR
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LTORG
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END
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