262 lines
9.1 KiB
C
262 lines
9.1 KiB
C
/*
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FreeRTOS.org V4.8.0 - Copyright (C) 2003-2008 Richard Barry.
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This file is part of the FreeRTOS.org distribution.
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FreeRTOS.org is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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FreeRTOS.org is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with FreeRTOS.org; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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A special exception to the GPL can be applied should you wish to distribute
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a combined work that includes FreeRTOS.org, without being obliged to provide
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the source code for any proprietary components. See the licensing section
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of http://www.FreeRTOS.org for full details of how and when the exception
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can be applied.
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***************************************************************************
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***************************************************************************
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* *
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* SAVE TIME AND MONEY! We can port FreeRTOS.org to your own hardware, *
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* and even write all or part of your application on your behalf. *
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* See http://www.OpenRTOS.com for details of the services we provide to *
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* expedite your project. *
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* *
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***************************************************************************
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***************************************************************************
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Please ensure to read the configuration and relevant port sections of the
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online documentation.
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http://www.FreeRTOS.org - Documentation, latest information, license and
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contact details.
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http://www.SafeRTOS.com - A version that is certified for use in safety
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critical systems.
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http://www.OpenRTOS.com - Commercial support, development, porting,
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licensing and training services.
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*/
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/*-----------------------------------------------------------
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* Components that can be compiled to either ARM or THUMB mode are
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* contained in port.c The ISR routines, which can only be compiled
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* to ARM mode, are contained in this file.
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*----------------------------------------------------------*/
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/* This file must always be compiled to ARM mode as it contains ISR
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definitions. */
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#pragma ARM
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/* Scheduler includes. */
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#include "FreeRTOS.h"
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#include "task.h"
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/* Constants required to handle interrupts. */
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#define portTIMER_MATCH_ISR_BIT ( ( unsigned portCHAR ) 0x01 )
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#define portCLEAR_VIC_INTERRUPT ( ( unsigned portLONG ) 0 )
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/*-----------------------------------------------------------*/
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/* The code generated by the Keil compiler does not maintain separate
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stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
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use the stack as per other ports. Instead a variable is used to keep
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track of the critical section nesting. This variable has to be stored
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as part of the task context and must be initialised to a non zero value. */
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#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
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volatile unsigned portLONG ulCriticalNesting = 9999UL;
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/*-----------------------------------------------------------*/
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/* ISR to handle manual context switches (from a call to taskYIELD()). */
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void vPortYieldProcessor( void );
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/*
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* The scheduler can only be started from ARM mode, hence the inclusion of this
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* function here.
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*/
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void vPortISRStartFirstTask( void );
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/*-----------------------------------------------------------*/
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void vPortISRStartFirstTask( void )
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{
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/* Simply start the scheduler. This is included here as it can only be
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called from ARM mode. */
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portRESTORE_CONTEXT();
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}
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/*-----------------------------------------------------------*/
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/*
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* Interrupt service routine for the SWI interrupt. The vector table is
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* configured within startup.s.
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*
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* vPortYieldProcessor() is used to manually force a context switch. The
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* SWI interrupt is generated by a call to taskYIELD() or portYIELD().
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*/
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void vPortYieldProcessor( void ) __task
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{
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/* Within an IRQ ISR the link register has an offset from the true return
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address, but an SWI ISR does not. Add the offset manually so the same
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ISR return code can be used in both cases. */
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__asm{ ADD LR, LR, #4 };
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/* Perform the context switch. */
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portSAVE_CONTEXT();
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vTaskSwitchContext();
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portRESTORE_CONTEXT();
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}
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/*-----------------------------------------------------------*/
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/*
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* The ISR used for the scheduler tick depends on whether the cooperative or
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* the preemptive scheduler is being used.
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*/
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#if configUSE_PREEMPTION == 0
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/*
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* The cooperative scheduler requires a normal IRQ service routine to
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* simply increment the system tick.
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*/
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void vNonPreemptiveTick( void );
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void vNonPreemptiveTick( void ) __irq
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{
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/* Increment the tick count - this may make a delaying task ready
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to run - but a context switch is not performed. */
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vTaskIncrementTick();
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/* Ready for the next interrupt. */
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T0IR = portTIMER_MATCH_ISR_BIT;
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VICVectAddr = portCLEAR_VIC_INTERRUPT;
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}
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#else
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/*
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* The preemptive scheduler ISR is defined as "naked" as the full context
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* is saved on entry as part of the context switch.
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*/
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void vPreemptiveTick( void );
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void vPreemptiveTick( void ) __task
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{
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/* Save the context of the current task. */
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portSAVE_CONTEXT();
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/* Increment the tick count - this may make a delayed task ready to
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run. */
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vTaskIncrementTick();
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/* Find the highest priority task that is ready to run. */
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vTaskSwitchContext();
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/* Ready for the next interrupt. */
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T0IR = portTIMER_MATCH_ISR_BIT;
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VICVectAddr = portCLEAR_VIC_INTERRUPT;
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/* Restore the context of the highest priority task that is ready to
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run. */
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portRESTORE_CONTEXT();
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}
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#endif
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/*-----------------------------------------------------------*/
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/*
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* The interrupt management utilities can only be called from ARM mode. When
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* KEIL_THUMB_INTERWORK is defined the utilities are defined as functions here
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* to ensure a switch to ARM mode. When KEIL_THUMB_INTERWORK is not defined
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* then the utilities are defined as macros in portmacro.h - as per other
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* ports.
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*/
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#ifdef KEIL_THUMB_INTERWORK
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void vPortDisableInterruptsFromThumb( void ) __task;
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void vPortEnableInterruptsFromThumb( void ) __task;
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void vPortDisableInterruptsFromThumb( void ) __task
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{
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__asm{ STMDB SP!, {R0} }; /* Push R0. */
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__asm{ MRS R0, CPSR }; /* Get CPSR. */
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__asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */
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__asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */
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__asm{ LDMIA SP!, {R0} }; /* Pop R0. */
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__asm{ BX R14 }; /* Return back to thumb. */
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}
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void vPortEnableInterruptsFromThumb( void ) __task
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{
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__asm{ STMDB SP!, {R0} }; /* Push R0. */
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__asm{ MRS R0, CPSR }; /* Get CPSR. */
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__asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */
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__asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */
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__asm{ LDMIA SP!, {R0} }; /* Pop R0. */
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__asm{ BX R14 }; /* Return back to thumb. */
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}
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#endif /* KEIL_THUMB_INTERWORK */
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/* The code generated by the Keil compiler does not maintain separate
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stack and frame pointers. The portENTER_CRITICAL macro cannot therefore
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use the stack as per other ports. Instead a variable is used to keep
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track of the critical section nesting. This necessitates the use of a
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function in place of the macro. */
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void vPortEnterCritical( void )
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{
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/* Disable interrupts as per portDISABLE_INTERRUPTS(); */
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__asm{ STMDB SP!, {R0} }; /* Push R0. */
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__asm{ MRS R0, CPSR }; /* Get CPSR. */
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__asm{ ORR R0, R0, #0xC0 }; /* Disable IRQ, FIQ. */
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__asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */
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__asm{ LDMIA SP!, {R0} }; /* Pop R0. */
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/* Now interrupts are disabled ulCriticalNesting can be accessed
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directly. Increment ulCriticalNesting to keep a count of how many times
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portENTER_CRITICAL() has been called. */
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ulCriticalNesting++;
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}
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void vPortExitCritical( void )
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{
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if( ulCriticalNesting > portNO_CRITICAL_NESTING )
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{
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/* Decrement the nesting count as we are leaving a critical section. */
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ulCriticalNesting--;
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/* If the nesting level has reached zero then interrupts should be
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re-enabled. */
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if( ulCriticalNesting == portNO_CRITICAL_NESTING )
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{
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/* Enable interrupts as per portEXIT_CRITICAL(). */
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__asm{ STMDB SP!, {R0} }; /* Push R0. */
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__asm{ MRS R0, CPSR }; /* Get CPSR. */
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__asm{ BIC R0, R0, #0xC0 }; /* Enable IRQ, FIQ. */
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__asm{ MSR CPSR_CXSF, R0 }; /* Write back modified value. */
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__asm{ LDMIA SP!, {R0} }; /* Pop R0. */
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}
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}
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}
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