bac101c988
* fix: CLEAR MIE BIT IN INITIAL RISC-V MSTATUS VALUE The MIE bit in the RISC-V MSTATUS register is used to globally enable or disable interrupts. It is copied into the MPIE bit and cleared on entry to an interrupt, and then copied back from the MPIE bit on exit from an interrupt. When a task is created it is given an initial MSTATUS value that is derived from the current MSTATUS value with the MPIE bit force to 1, but the MIE bit is not forced into any state. This change forces the MIE bit to 0 (interrupts disabled). Why: If a task is created before the scheduler is started the MIE bit will happen to be 0 (interrupts disabled), which is fine. If a task is created after the scheduler has been started the MIE bit is set (interrupts enabled), causing interrupts to unintentionally become enabled inside the interrupt in which the task is first moved to the running state - effectively breaking a critical section which in turn could cause a crash if enabling interrupts causes interrupts to nest. It is only an issue when starting a newly created task that was created after the scheduler was started. Related Issues: https://forums.freertos.org/t/risc-v-port-pxportinitialisestack-issue-about-mstatus-value-onto-the-stack/9622 Co-authored-by: Cobus van Eeden <35851496+cobusve@users.noreply.github.com> |
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| .. | ||
| ARM7_AT91FR40008 | ||
| ARM7_AT91SAM7S | ||
| ARM7_LPC23xx | ||
| ARM7_LPC2000 | ||
| ARM_CA9 | ||
| ARM_CA53_64_BIT | ||
| ARM_CM0 | ||
| ARM_CM3 | ||
| ARM_CM3_MPU | ||
| ARM_CM4_MPU | ||
| ARM_CM4F | ||
| ARM_CM7 | ||
| ARM_CM23 | ||
| ARM_CM23_NTZ/non_secure | ||
| ARM_CM33 | ||
| ARM_CM33_NTZ/non_secure | ||
| ARM_CR5 | ||
| ARM_CRx_No_GIC | ||
| ATMega323 | ||
| AVR32_UC3 | ||
| ColdFire_V2 | ||
| CORTUS_APS3 | ||
| H8S2329 | ||
| HCS12 | ||
| IA32_flat | ||
| MCF5235 | ||
| MicroBlaze | ||
| MicroBlazeV8 | ||
| MicroBlazeV9 | ||
| MSP430F449 | ||
| NiosII | ||
| PPC405_Xilinx | ||
| PPC440_Xilinx | ||
| RISC-V | ||
| RL78 | ||
| RX100 | ||
| RX600 | ||
| RX600v2 | ||
| STR75x | ||
| TriCore_1782 | ||