145 lines
5.2 KiB
INI
145 lines
5.2 KiB
INI
// 186.cfg
|
||
// You must select RAM, ROM for your controller 04-26-2000
|
||
// Your TERN controller is installed with SRAM and ROM with different sizes.
|
||
// For debug, 128K or 512K SRAM can be selected
|
||
// For build a ROM, you need to select the ROM size.
|
||
// How to select ?
|
||
// 1) commend out the unwanted #define RAM size line with "//"
|
||
// 2) delete the "//" preceding the wanted #define RAM size line
|
||
//
|
||
|
||
// #define RAM 32 // 32KB SRAM installed
|
||
#define RAM 128 // 128KB SRAM installed
|
||
// #define RAM 512 // 512KB SRAM installed
|
||
|
||
// #define ROM 32 // Use 32KB ROM chip 27C256-70
|
||
#define ROM 64 // Use 64KB ROM chip 27C512-70
|
||
// #define ROM 128 // Use 128KB ROM chip 27C010-70
|
||
// #define ROM 256 // Use 256KB ROM chip 27C020-70
|
||
// #define ROM 512 // Use 512KB ROM chip 27C040-70, Change Jumper on board
|
||
|
||
|
||
cputype Am186ES // AMD188/6 based controllers
|
||
|
||
#if defined(__PDREMOTE__)
|
||
|
||
#if RAM == 32
|
||
map 0x00000 to 0x00fff as reserved // interrupt vector table
|
||
map 0x01000 to 0x03fff as rdwr // System RAM area (60KB RAM)
|
||
map 0x04000 to 0x07fff as rdonly // Simulated EPROM area (64KB RAM)
|
||
map 0x08000 to 0xfffff as reserved // No access allowed
|
||
#define CODE_START 0x0400 // Start of application code, STEP2 !
|
||
|
||
#elif RAM == 128
|
||
map 0x00000 to 0x00fff as reserved // interrupt vector table
|
||
map 0x01000 to 0x07fff as rdwr // System RAM area (60KB RAM)
|
||
map 0x08000 to 0x1ffff as rdonly // Simulated EPROM area (64KB RAM)
|
||
map 0x20000 to 0xfffff as reserved // No access allowed
|
||
#define CODE_START 0x0800 // Start of application code
|
||
|
||
#elif RAM == 512
|
||
map 0x00000 to 0x00fff as reserved // interrupt vector table
|
||
map 0x01000 to 0x07fff as rdwr // System RAM area (60KB RAM)
|
||
map 0x08000 to 0x7ffff as rdonly // Simulated EPROM area(480KB RAM)
|
||
map 0x80000 to 0xfffff as reserved // No access allowed
|
||
#define CODE_START 0x0800 // Start of application code
|
||
#endif
|
||
|
||
#define DATA_START 0x0100 // Start of application data
|
||
#define BOOT_START 0x1fc0 // Start of initialization code
|
||
|
||
#else
|
||
#if ROM == 32
|
||
map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
|
||
map 0x20000 to 0xf7fff as reserved // No access
|
||
map 0xF8000 to 0xfffff as rdonly // 32KB EPROM address space
|
||
#define CODE_START 0xF800 // Start of application code
|
||
#elif ROM == 64
|
||
map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
|
||
map 0x20000 to 0xEffff as reserved // No access
|
||
map 0xF0000 to 0xfffff as rdonly // 64KB EPROM address space
|
||
#define CODE_START 0xF000 // Start of application code
|
||
#elif ROM == 128
|
||
map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
|
||
map 0x20000 to 0xDffff as reserved // No access
|
||
map 0xE0000 to 0xfffff as rdonly // 128KB EPROM address space
|
||
#define CODE_START 0xE000 // Start of application code
|
||
#elif ROM == 256
|
||
map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
|
||
map 0x20000 to 0xBffff as reserved // No access
|
||
map 0xC0000 to 0xfffff as rdonly // 256KB EPROM address space
|
||
#define CODE_START 0xC000 // Start of application code
|
||
#elif ROM == 512
|
||
map 0x00000 to 0x1ffff as rdwr // 128KB RAM address space
|
||
map 0x20000 to 0x7ffff as reserved // No access
|
||
map 0x80000 to 0xfffff as rdonly // 512KB EPROM address space
|
||
#define CODE_START 0x8000 // Start of application code
|
||
#endif
|
||
|
||
#define DATA_START 0x0040 // Start of application data
|
||
#define BOOT_START 0xffc0 // Start of initialization code
|
||
|
||
initcode reset \ // Reset vector to program entry point
|
||
umcs = 0x80bf \ // 512K ROM, 3 wait states
|
||
lmcs = 0x7fbf \ // 512K RAM, 3 wait states
|
||
mpcs = 0xa0bf \
|
||
mmcs = 0x81ff \
|
||
pacs = 0x007f
|
||
|
||
class ??LOCATE = BOOT_START // Chip select initialization
|
||
output ??LOCATE
|
||
|
||
#if ROM == 32 // 27C256-90 EPROM or FLASH
|
||
hexfile binary offset=0xf8000 size=32 // for 27C256, bin file
|
||
#elif ROM == 64 // 27C512-90 EPROM or FLASH
|
||
hexfile binary offset=0xF0000 size=64 // for 27C512
|
||
#elif ROM == 128 // 27C010-90 EPROM or FLASH
|
||
hexfile binary offset=0xE0000 size=128 // for 27C010
|
||
#elif ROM == 256 // 27C020-90 EPROM or FLASH
|
||
hexfile binary offset=0xC0000 size=256 // for 27C020
|
||
#elif ROM == 512 // 27C040-90 EPROM or FLASH
|
||
hexfile Intel86 offset=0x80000 size=512 // for 27C040, output .HEX file
|
||
#endif
|
||
|
||
#endif
|
||
|
||
|
||
//
|
||
// Start of common configuration file settings.
|
||
//
|
||
|
||
absfile axe86 // Paradigm C++ debugging output
|
||
listfile segments // Absolute segment map
|
||
|
||
dup DATA ROMDATA // Make a copy of initialized data
|
||
dup FAR_DATA ROMFARDATA // Make a copy of far initialized data
|
||
|
||
#if defined(__COMPFARDATA__) // Compress and display results
|
||
compress ROMFARDATA
|
||
display compression
|
||
#endif
|
||
|
||
class CODE = CODE_START // Application code
|
||
class DATA = DATA_START // Application data
|
||
|
||
order DATA \ // RAM class organization
|
||
BSS \
|
||
NVRAM \
|
||
EDATA \
|
||
STACK \
|
||
FAR_DATA ENDFAR_DATA \
|
||
FAR_BSS ENDFAR_BSS \
|
||
FAR_HEAP ENDFAR_HEAP
|
||
|
||
order CODE \ // EPROM class organization
|
||
INITDATA EXITDATA \
|
||
FAR_CONST ENDFAR_CONST \
|
||
ROMDATA ENDROMDATA \
|
||
ROMFARDATA ENDROMFARDATA
|
||
|
||
output CODE \ // Classes in the output file(s)
|
||
INITDATA EXITDATA \
|
||
FAR_CONST ENDFAR_CONST \
|
||
ROMDATA ENDROMDATA \
|
||
ROMFARDATA ENDROMFARDATA
|
||
|