1b7a2e40a3
Change configCHECK_FOR_STACK_OVERFLOW to 3 to also check the interrupt stack. Add a build configuration to allow use on the PIC32 USBII starter kit. Increase some delays when talking to the LCD to ensure it always displays correctly. Rewrite the register test tasks.
264 lines
8.4 KiB
C
264 lines
8.4 KiB
C
/*
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FreeRTOS V7.5.3 - Copyright (C) 2013 Real Time Engineers Ltd.
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All rights reserved
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VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
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***************************************************************************
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* *
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* FreeRTOS provides completely free yet professionally developed, *
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* robust, strictly quality controlled, supported, and cross *
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* platform software that has become a de facto standard. *
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* *
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* Help yourself get started quickly and support the FreeRTOS *
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* project by purchasing a FreeRTOS tutorial book, reference *
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* manual, or both from: http://www.FreeRTOS.org/Documentation *
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* *
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* Thank you! *
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* *
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***************************************************************************
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This file is part of the FreeRTOS distribution.
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FreeRTOS is free software; you can redistribute it and/or modify it under
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the terms of the GNU General Public License (version 2) as published by the
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Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
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>>! NOTE: The modification to the GPL is included to allow you to distribute
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>>! a combined work that includes FreeRTOS without being obliged to provide
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>>! the source code for proprietary components outside of the FreeRTOS
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>>! kernel.
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FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
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WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
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FOR A PARTICULAR PURPOSE. Full license text is available from the following
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link: http://www.freertos.org/a00114.html
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1 tab == 4 spaces!
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***************************************************************************
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* *
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* Having a problem? Start by reading the FAQ "My application does *
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* not run, what could be wrong?" *
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* *
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* http://www.FreeRTOS.org/FAQHelp.html *
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* *
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***************************************************************************
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http://www.FreeRTOS.org - Documentation, books, training, latest versions,
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license and Real Time Engineers Ltd. contact details.
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http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
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including FreeRTOS+Trace - an indispensable productivity tool, a DOS
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compatible FAT file system, and our tiny thread aware UDP/IP stack.
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http://www.OpenRTOS.com - Real Time Engineers ltd license FreeRTOS to High
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Integrity Systems to sell under the OpenRTOS brand. Low cost OpenRTOS
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licenses offer ticketed support, indemnification and middleware.
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http://www.SafeRTOS.com - High Integrity Systems also provide a safety
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engineered and independently SIL3 certified version for use in safety and
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mission critical applications that require provable dependability.
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1 tab == 4 spaces!
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*/
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/*
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* This file implements functions to access and manipulate the PIC32 hardware
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* without reliance on third party library functions that may be liable to
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* change.
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*/
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/* FreeRTOS includes. */
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#include "FreeRTOS.h"
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/* Demo includes. */
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#include "ConfigPerformance.h"
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/* Hardware specific definitions. */
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#define hwCHECON_PREFEN_BITS ( 0x03UL << 0x04UL )
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#define hwCHECON_WAIT_STAT_BITS ( 0x07UL << 0UL )
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#define hwMAX_FLASH_SPEED ( 30000000UL )
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#define hwPERIPHERAL_CLOCK_DIV_BY_2 ( 1UL << 0x13UL )
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#define hwUNLOCK_KEY_0 ( 0xAA996655UL )
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#define hwUNLOCK_KEY_1 ( 0x556699AAUL )
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#define hwLOCK_KEY ( 0x33333333UL )
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#define hwGLOBAL_INTERRUPT_BIT ( 0x01UL )
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#define hwBEV_BIT ( 0x00400000 )
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#define hwEXL_BIT ( 0x00000002 )
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#define hwIV_BIT ( 0x00800000 )
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/*
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* Set the flash wait states for the configured CPU clock speed.
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*/
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static void prvConfigureWaitStates( void );
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/*
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* Use a divisor of 2 on the peripheral bus.
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*/
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static void prvConfigurePeripheralBus( void );
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/*
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* Enable the cache.
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*/
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static void __attribute__ ((nomips16)) prvKSeg0CacheOn( void );
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/*-----------------------------------------------------------*/
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void vHardwareConfigurePerformance( void )
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{
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unsigned long ulStatus;
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#ifdef _PCACHE
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unsigned long ulCacheStatus;
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#endif
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/* Disable interrupts - note taskDISABLE_INTERRUPTS() cannot be used here as
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FreeRTOS does not globally disable interrupt. */
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ulStatus = _CP0_GET_STATUS();
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_CP0_SET_STATUS( ulStatus & ~hwGLOBAL_INTERRUPT_BIT );
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prvConfigurePeripheralBus();
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prvConfigureWaitStates();
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/* Disable DRM wait state. */
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BMXCONCLR = _BMXCON_BMXWSDRM_MASK;
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#ifdef _PCACHE
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{
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/* Read the current CHECON value. */
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ulCacheStatus = CHECON;
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/* All the PREFEN bits are being set, so no need to clear first. */
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ulCacheStatus |= hwCHECON_PREFEN_BITS;
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/* Write back the new value. */
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CHECON = ulCacheStatus;
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prvKSeg0CacheOn();
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}
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#endif
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/* Reset the status register back to its original value so the original
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interrupt enable status is retored. */
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_CP0_SET_STATUS( ulStatus );
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}
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/*-----------------------------------------------------------*/
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void vHardwareUseMultiVectoredInterrupts( void )
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{
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unsigned long ulStatus, ulCause;
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extern unsigned long _ebase_address[];
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/* Get current status. */
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ulStatus = _CP0_GET_STATUS();
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/* Disable interrupts. */
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ulStatus &= ~hwGLOBAL_INTERRUPT_BIT;
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/* Set BEV bit. */
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ulStatus |= hwBEV_BIT;
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/* Write status back. */
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_CP0_SET_STATUS( ulStatus );
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/* Setup EBase. */
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_CP0_SET_EBASE( ( unsigned long ) _ebase_address );
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/* Space vectors by 0x20 bytes. */
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_CP0_XCH_INTCTL( 0x20 );
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/* Set the IV bit in the CAUSE register. */
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ulCause = _CP0_GET_CAUSE();
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ulCause |= hwIV_BIT;
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_CP0_SET_CAUSE( ulCause );
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/* Clear BEV and EXL bits in status. */
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ulStatus &= ~( hwBEV_BIT | hwEXL_BIT );
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_CP0_SET_STATUS( ulStatus );
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/* Set MVEC bit. */
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INTCONbits.MVEC = 1;
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/* Finally enable interrupts again. */
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ulStatus |= hwGLOBAL_INTERRUPT_BIT;
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_CP0_SET_STATUS( ulStatus );
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}
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/*-----------------------------------------------------------*/
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static void prvConfigurePeripheralBus( void )
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{
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unsigned long ulDMAStatus;
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__OSCCONbits_t xOSCCONBits;
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/* Unlock after suspending. */
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ulDMAStatus = DMACONbits.SUSPEND;
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if( ulDMAStatus == 0 )
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{
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DMACONSET = _DMACON_SUSPEND_MASK;
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/* Wait until actually suspended. */
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while( DMACONbits.SUSPEND == 0 );
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}
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SYSKEY = 0;
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SYSKEY = hwUNLOCK_KEY_0;
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SYSKEY = hwUNLOCK_KEY_1;
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/* Read to start in sync. */
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xOSCCONBits.w = OSCCON;
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xOSCCONBits.PBDIV = 0;
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xOSCCONBits.w |= hwPERIPHERAL_CLOCK_DIV_BY_2;
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/* Write back. */
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OSCCON = xOSCCONBits.w;
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/* Ensure the write occurred. */
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xOSCCONBits.w = OSCCON;
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/* Lock again. */
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SYSKEY = hwLOCK_KEY;
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/* Resume DMA activity. */
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if( ulDMAStatus == 0 )
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{
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DMACONCLR=_DMACON_SUSPEND_MASK;
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}
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}
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/*-----------------------------------------------------------*/
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static void prvConfigureWaitStates( void )
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{
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unsigned long ulSystemClock = configCPU_CLOCK_HZ - 1;
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unsigned long ulWaitStates, ulCHECONVal;
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/* 1 wait state for every hwMAX_FLASH_SPEED MHz. */
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ulWaitStates = 0;
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while( ulSystemClock > hwMAX_FLASH_SPEED )
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{
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ulWaitStates++;
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ulSystemClock -= hwMAX_FLASH_SPEED;
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}
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/* Obtain current CHECON value. */
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ulCHECONVal = CHECON;
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/* Clear the wait state bits, then set the calculated wait state bits. */
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ulCHECONVal &= ~hwCHECON_WAIT_STAT_BITS;
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ulCHECONVal |= ulWaitStates;
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/* Write back the new value. */
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CHECON = ulWaitStates;
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}
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/*-----------------------------------------------------------*/
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static void __attribute__ ((nomips16)) prvKSeg0CacheOn( void )
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{
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unsigned long ulValue;
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__asm volatile( "mfc0 %0, $16, 0" : "=r"( ulValue ) );
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ulValue = ( ulValue & ~0x07) | 0x03;
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__asm volatile( "mtc0 %0, $16, 0" :: "r" ( ulValue ) );
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}
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