cd1f51cb5e
* Add support for the configUSE_TASK_FPU_SUPPORT in the GCC/ARM_CR5 port This is done almost identically as in the GCC/ARM_CA9 port * Adjust task stack initialitation of the GCC/ARM_CR5 port Ensure that the task stack initialization is done correctly for the different options of configUSE_TASK_FPU_SUPPORT. This is very similar to the GCC/ARM_CA9 port. The only meaningful difference is, that the FPU of the Cortex-R5 has just sixteen 64-bit floating point registers as it implements the VFPv3-D16 architecture. You may also refer to the ARM documentation * Add support for FPU safe interrupts to the GCC/ARM_CR5 port Similar to GCC/ARM_CA9 port * Clarify comment about the size of the FPU registers of Cortex R5 |
||
|---|---|---|
| .. | ||
| ARM7_AT91FR40008 | ||
| ARM7_AT91SAM7S | ||
| ARM7_LPC23xx | ||
| ARM7_LPC2000 | ||
| ARM_CA9 | ||
| ARM_CA53_64_BIT | ||
| ARM_CA53_64_BIT_SRE | ||
| ARM_CM0 | ||
| ARM_CM3 | ||
| ARM_CM3_MPU | ||
| ARM_CM4_MPU | ||
| ARM_CM4F | ||
| ARM_CM7 | ||
| ARM_CM23 | ||
| ARM_CM23_NTZ/non_secure | ||
| ARM_CM33 | ||
| ARM_CM33_NTZ/non_secure | ||
| ARM_CM55 | ||
| ARM_CM55_NTZ/non_secure | ||
| ARM_CM85 | ||
| ARM_CM85_NTZ/non_secure | ||
| ARM_CR5 | ||
| ARM_CRx_No_GIC | ||
| ATMega323 | ||
| AVR32_UC3 | ||
| AVR_AVRDx | ||
| AVR_Mega0 | ||
| ColdFire_V2 | ||
| CORTUS_APS3 | ||
| H8S2329 | ||
| HCS12 | ||
| IA32_flat | ||
| MCF5235 | ||
| MicroBlaze | ||
| MicroBlazeV8 | ||
| MicroBlazeV9 | ||
| MSP430F449 | ||
| NiosII | ||
| PPC405_Xilinx | ||
| PPC440_Xilinx | ||
| RISC-V | ||
| RL78 | ||
| RX100 | ||
| RX200 | ||
| RX600 | ||
| RX600v2 | ||
| RX700v3_DPFPU | ||
| STR75x | ||
| TriCore_1782 | ||