236 lines
7.1 KiB
Plaintext
236 lines
7.1 KiB
Plaintext
#
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# ##############################################################################
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#
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# Created by Base System Builder Wizard for Xilinx EDK 8.2.02 Build EDK_Im_Sp2.4
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#
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# Tue Mar 04 08:41:46 2008
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#
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# Target Board: Xilinx Virtex 4 ML403 Evaluation Platform Rev 1
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# Family: virtex4
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# Device: xc4vfx12
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# Package: ff668
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# Speed Grade: -10
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#
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# Processor: PPC 405
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# Processor clock frequency: 100.000000 MHz
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# Bus clock frequency: 100.000000 MHz
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# Debug interface: FPGA JTAG
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# Data Cache: 16 KB
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# Instruction Cache: 16 KB
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# On Chip Memory : 4 KB
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# Total Off Chip Memory : 1 MB
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# - SRAM_256Kx32 = 1 MB
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#
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# ##############################################################################
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PARAMETER VERSION = 2.1.0
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PORT fpga_0_RS232_Uart_RX_pin = fpga_0_RS232_Uart_RX, DIR = I
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PORT fpga_0_RS232_Uart_TX_pin = fpga_0_RS232_Uart_TX, DIR = O
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PORT fpga_0_LEDs_4Bit_GPIO_IO_pin = fpga_0_LEDs_4Bit_GPIO_IO, DIR = IO, VEC = [0:3]
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PORT fpga_0_LEDs_Positions_GPIO_IO_pin = fpga_0_LEDs_Positions_GPIO_IO, DIR = IO, VEC = [0:4]
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PORT fpga_0_SRAM_256Kx32_Mem_A_pin = fpga_0_SRAM_256Kx32_Mem_A, DIR = O, VEC = [9:29]
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PORT fpga_0_SRAM_256Kx32_Mem_BEN_pin = fpga_0_SRAM_256Kx32_Mem_BEN, DIR = O, VEC = [0:3]
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PORT fpga_0_SRAM_256Kx32_Mem_WEN_pin = fpga_0_SRAM_256Kx32_Mem_WEN, DIR = O
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PORT fpga_0_SRAM_256Kx32_Mem_DQ_pin = fpga_0_SRAM_256Kx32_Mem_DQ, DIR = IO, VEC = [0:31]
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PORT fpga_0_SRAM_256Kx32_Mem_OEN_pin = fpga_0_SRAM_256Kx32_Mem_OEN, DIR = O, VEC = [0:0]
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PORT fpga_0_SRAM_256Kx32_Mem_CEN_pin = fpga_0_SRAM_256Kx32_Mem_CEN, DIR = O, VEC = [0:0]
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PORT fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin = fpga_0_SRAM_256Kx32_Mem_ADV_LDN, DIR = O
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PORT fpga_0_SRAM_CLOCK = sys_clk_s, DIR = O
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PORT sys_clk_pin = dcm_clk_s, DIR = I, SIGIS = CLK, CLK_FREQ = 100000000
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PORT sys_rst_pin = sys_rst_s, DIR = I, RST_POLARITY = 0, SIGIS = RST
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BEGIN ppc405_virtex4
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PARAMETER INSTANCE = ppc405_0
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PARAMETER HW_VER = 1.01.a
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BUS_INTERFACE JTAGPPC = jtagppc_0_0
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BUS_INTERFACE IPLB = plb
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BUS_INTERFACE DPLB = plb
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PORT PLBCLK = sys_clk_s
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PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ
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PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ
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PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ
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PORT RSTC405RESETCHIP = RSTC405RESETCHIP
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PORT RSTC405RESETCORE = RSTC405RESETCORE
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PORT RSTC405RESETSYS = RSTC405RESETSYS
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PORT EICC405EXTINPUTIRQ = EICC405EXTINPUTIRQ
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PORT CPMC405CLOCK = sys_clk_s
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END
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BEGIN jtagppc_cntlr
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PARAMETER INSTANCE = jtagppc_0
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PARAMETER HW_VER = 2.00.a
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BUS_INTERFACE JTAGPPC0 = jtagppc_0_0
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END
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BEGIN proc_sys_reset
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PARAMETER INSTANCE = reset_block
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_EXT_RESET_HIGH = 0
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PORT Ext_Reset_In = sys_rst_s
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PORT Slowest_sync_clk = sys_clk_s
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PORT Chip_Reset_Req = C405RSTCHIPRESETREQ
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PORT Core_Reset_Req = C405RSTCORERESETREQ
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PORT System_Reset_Req = C405RSTSYSRESETREQ
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PORT Rstc405resetchip = RSTC405RESETCHIP
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PORT Rstc405resetcore = RSTC405RESETCORE
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PORT Rstc405resetsys = RSTC405RESETSYS
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PORT Bus_Struct_Reset = sys_bus_reset
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PORT Dcm_locked = dcm_0_lock
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END
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BEGIN plb_v34
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PARAMETER INSTANCE = plb
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PARAMETER HW_VER = 1.02.a
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PARAMETER C_DCR_INTFCE = 0
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PARAMETER C_EXT_RESET_HIGH = 1
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PORT SYS_Rst = sys_bus_reset
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PORT PLB_Clk = sys_clk_s
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END
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BEGIN opb_v20
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PARAMETER INSTANCE = opb
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PARAMETER HW_VER = 1.10.c
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PARAMETER C_EXT_RESET_HIGH = 1
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PORT SYS_Rst = sys_bus_reset
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PORT OPB_Clk = sys_clk_s
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END
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BEGIN plb2opb_bridge
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PARAMETER INSTANCE = plb2opb
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PARAMETER HW_VER = 1.01.a
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PARAMETER C_DCR_INTFCE = 0
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PARAMETER C_NUM_ADDR_RNG = 1
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PARAMETER C_RNG0_BASEADDR = 0x40000000
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PARAMETER C_RNG0_HIGHADDR = 0x7fffffff
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BUS_INTERFACE SPLB = plb
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BUS_INTERFACE MOPB = opb
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END
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BEGIN opb_uartlite
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PARAMETER INSTANCE = RS232_Uart
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PARAMETER HW_VER = 1.00.b
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PARAMETER C_BAUDRATE = 115200
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PARAMETER C_DATA_BITS = 8
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PARAMETER C_ODD_PARITY = 0
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PARAMETER C_USE_PARITY = 0
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PARAMETER C_CLK_FREQ = 100000000
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PARAMETER C_BASEADDR = 0x40600000
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PARAMETER C_HIGHADDR = 0x4060ffff
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BUS_INTERFACE SOPB = opb
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PORT Interrupt = RS232_Uart_Interrupt
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PORT RX = fpga_0_RS232_Uart_RX
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PORT TX = fpga_0_RS232_Uart_TX
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END
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BEGIN opb_gpio
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PARAMETER INSTANCE = LEDs_4Bit
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PARAMETER HW_VER = 3.01.b
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PARAMETER C_GPIO_WIDTH = 4
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PARAMETER C_IS_DUAL = 0
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PARAMETER C_IS_BIDIR = 1
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PARAMETER C_ALL_INPUTS = 0
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PARAMETER C_BASEADDR = 0x40000000
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PARAMETER C_HIGHADDR = 0x4000ffff
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BUS_INTERFACE SOPB = opb
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PORT GPIO_IO = fpga_0_LEDs_4Bit_GPIO_IO
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END
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BEGIN opb_gpio
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PARAMETER INSTANCE = LEDs_Positions
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PARAMETER HW_VER = 3.01.b
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PARAMETER C_GPIO_WIDTH = 5
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PARAMETER C_IS_DUAL = 0
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PARAMETER C_IS_BIDIR = 1
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PARAMETER C_ALL_INPUTS = 0
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PARAMETER C_BASEADDR = 0x40020000
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PARAMETER C_HIGHADDR = 0x4002ffff
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BUS_INTERFACE SOPB = opb
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PORT GPIO_IO = fpga_0_LEDs_Positions_GPIO_IO
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END
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BEGIN plb_emc
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PARAMETER INSTANCE = SRAM_256Kx32
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PARAMETER HW_VER = 2.00.a
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PARAMETER C_INCLUDE_BURST_CACHELN_SUPPORT = 1
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PARAMETER C_PLB_CLK_PERIOD_PS = 10000
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PARAMETER C_NUM_BANKS_MEM = 1
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PARAMETER C_MAX_MEM_WIDTH = 32
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PARAMETER C_INCLUDE_NEGEDGE_IOREGS = 1
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PARAMETER C_INCLUDE_DATAWIDTH_MATCHING_0 = 1
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PARAMETER C_MEM0_WIDTH = 32
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PARAMETER C_SYNCH_MEM_0 = 1
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PARAMETER C_TCEDV_PS_MEM_0 = 0
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PARAMETER C_TWC_PS_MEM_0 = 0
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PARAMETER C_TAVDV_PS_MEM_0 = 0
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PARAMETER C_TWP_PS_MEM_0 = 0
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PARAMETER C_THZCE_PS_MEM_0 = 0
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PARAMETER C_TLZWE_PS_MEM_0 = 0
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PARAMETER C_MEM0_BASEADDR = 0x00000000
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PARAMETER C_MEM0_HIGHADDR = 0x000fffff
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BUS_INTERFACE SPLB = plb
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PORT Mem_A = fpga_0_SRAM_256Kx32_Mem_A_split
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PORT Mem_BEN = fpga_0_SRAM_256Kx32_Mem_BEN
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PORT Mem_WEN = fpga_0_SRAM_256Kx32_Mem_WEN
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PORT Mem_DQ = fpga_0_SRAM_256Kx32_Mem_DQ
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PORT Mem_OEN = fpga_0_SRAM_256Kx32_Mem_OEN
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PORT Mem_CEN = fpga_0_SRAM_256Kx32_Mem_CEN
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PORT Mem_ADV_LDN = fpga_0_SRAM_256Kx32_Mem_ADV_LDN
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END
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BEGIN plb_bram_if_cntlr
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PARAMETER INSTANCE = plb_bram_if_cntlr_1
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PARAMETER HW_VER = 1.00.b
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PARAMETER c_include_burst_cacheln_support = 0
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PARAMETER c_plb_clk_period_ps = 10000
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PARAMETER c_baseaddr = 0xfffff000
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PARAMETER c_highaddr = 0xffffffff
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BUS_INTERFACE SPLB = plb
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BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
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END
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BEGIN bram_block
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PARAMETER INSTANCE = plb_bram_if_cntlr_1_bram
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PARAMETER HW_VER = 1.00.a
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BUS_INTERFACE PORTA = plb_bram_if_cntlr_1_port
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END
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BEGIN opb_intc
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PARAMETER INSTANCE = opb_intc_0
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PARAMETER HW_VER = 1.00.c
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PARAMETER C_BASEADDR = 0x41200000
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PARAMETER C_HIGHADDR = 0x4120ffff
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BUS_INTERFACE SOPB = opb
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PORT Irq = EICC405EXTINPUTIRQ
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PORT Intr = RS232_Uart_Interrupt
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END
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BEGIN util_bus_split
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PARAMETER INSTANCE = SRAM_256Kx32_util_bus_split_0
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_SIZE_IN = 32
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PARAMETER C_LEFT_POS = 9
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PARAMETER C_SPLIT = 30
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PORT Sig = fpga_0_SRAM_256Kx32_Mem_A_split
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PORT Out1 = fpga_0_SRAM_256Kx32_Mem_A
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END
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BEGIN dcm_module
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PARAMETER INSTANCE = dcm_0
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PARAMETER HW_VER = 1.00.a
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PARAMETER C_CLK0_BUF = TRUE
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PARAMETER C_CLKIN_PERIOD = 10.000000
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PARAMETER C_CLK_FEEDBACK = 1X
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PARAMETER C_DLL_FREQUENCY_MODE = LOW
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PARAMETER C_EXT_RESET_HIGH = 1
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PORT CLKIN = dcm_clk_s
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PORT CLK0 = sys_clk_s
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PORT CLKFB = sys_clk_s
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PORT RST = net_gnd
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PORT LOCKED = dcm_0_lock
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END
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