0d95aca202Introduce a port for T-HEAD CK802. A simple demo for T-HEAD CB2201 is also included.
Yuhui.Zheng
2020-01-10 07:53:14 +0000
d2914041f8Update the GCC and IAR SiFive HiFive rev-b demos to use the new configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS constants in place of the deprecated configCLINT_BASE_ADDRESS constant. Update the IAR RISC-V HiFive demo to use the latest IAR Embedded Workbench version.
Richard Barry
2020-01-09 02:28:45 +0000
066e2bc7d2Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the IAR RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old.
Richard Barry
2020-01-09 02:23:51 +0000
75b81a1fabWork in progress update of LPC51U68 MCUXpresso project to rearrange the folder structure and names.
Richard Barry
2020-01-09 00:19:36 +0000
fbb23055cdReplace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the GCC RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old.
Richard Barry
2020-01-07 01:14:36 +0000
eaf9318df8Add Source/portable/ARMClang file that directs users to the GCC port if they which to use the ARMClang compiler.
Richard Barry
2020-01-04 00:14:18 +0000
881958514bIf tickless idle mode is in use then ensure prvResetNextTaskUnblockTime() is called after a task is unblocked due to a bit being set in an event group. This allows the MCU to re-enter sleep mode at the earliest possible time (rather than waiting until the timeout that would occur had the task not being unblocked be the event group) and matches a similar change made for queues and derivative objects (semaphores, etc.) some time ago.
Richard Barry
2020-01-03 22:50:31 +0000
853856e8ccCorrect #error text in multiple fat file system files.
Richard Barry
2020-01-03 20:53:27 +0000
9e86cb95a7Add xPortIsInsideInterrupt() to the IAR ARMv7-M ports.
Richard Barry
2020-01-03 01:17:29 +0000
be3561ed53Added xTaskAbortDelayFromISR() and ulTaskNotifyValueClear() API functions. Added tests for xTaskAbortDelayFromISR() into Demo/Common/Minimal/AbortDelay.c. Added tests for ulTaskNotifyValueClear() into Demo/Common/Minimal/TaskNotify.c.
Richard Barry
2020-01-02 18:55:20 +0000
0a29d350b1Renamed RISC-V_RV32_SiFive_HiFive1_IAR directory to RISC-V_RV32_SiFive_HiFive1-RevB_IAR as it targets the RevB hardware.
Richard Barry
2020-01-01 22:38:23 +0000
62b413627aMinor updates to comment block for xTaskCheckForTimeOut().
Richard Barry
2020-01-01 22:24:44 +0000
dfc1bf8ec3Rename RISC-V_RV32_SiFive_HiFive1-FreedomStudio directory to RISC-V_RV32_SiFive_HiFive1-RevB-FreedomStudio as it targets Rev B of the hardware.
Richard Barry
2020-01-01 22:05:35 +0000
4b943b35e0Update RISCC-V-RV32-SiFive_HiFive1_FreedomStudio project to latest tools and metal library versions.
Richard Barry
2020-01-01 22:02:06 +0000
cfa83672efRename STM32Cube to GCC for STM32L4 Discovery projects as GCC is the compiler used.
Gaurav Aggarwal
2020-01-01 00:35:42 +0000
474182ab39Make vSetupTimerInterrupt weak in the RVDS M4 MPU port to give the application writer a chance to override this function. This gives the application write ability to use a different timer.
Gaurav Aggarwal
2020-01-01 00:04:10 +0000
22dd9a55abUpdate documentation of xTaskCheckForTimeOut function to reflect the intended use of this API.
Gaurav Aggarwal
2019-12-31 20:49:07 +0000
8f0eaf274c- Updates to projects due to demo folder name change. (IAR source file paths and assembler path were fixed. Keil source file paths were fixed.) - Added back power static library for GCC and IAR. (Power management related interface definitions are in drivers/fsl_power.h. power.c is empty due to "implementation is in header file and power library") - Note for GCC link: the command used for linking is arm-none-eabi-gcc -nostdlib -L<additional lib search path> -Xlinker ... -o "CORTEX_M0+_LPC51U68_LPCXpresso.axf" <all *.o> -lpower. Per GCC doc, static library name in file system is libpower.a.
Yuhui.Zheng
2019-12-31 08:06:33 +0000
3203c5cc85Previously the STM32F0518 compiler setting was changed to enable the use of the __weak attribute - however changing the port layer to use #pragma weak in place of __weak means the compiler setting change is not required and removes the risk of introducing incompatibilities - so this check in reverts the compiler settings change.
Richard Barry
2019-12-30 22:24:58 +0000
cc673eb6a5Ensure the CORTEX_M0_STM32F0518_IAR demo builds after updates to the Cortex-M0 port layer - required an update to the project settings to allow IAR extensions as the port layer now uses the _weak qualifier.
Richard Barry
2019-12-30 22:07:33 +0000
801e63bd10Ensure the LPC1114 demo still builds after updates to the Cortex-M0 port layer - includes minor update to remove compiler warning that resulted from a newer compiler version.
Richard Barry
2019-12-30 22:00:26 +0000
53c98357b0Ensure the LPC1114 demo still builds after updates to the Cortex-M0 port layer - includes minor update to remove compiler warning that resulted from a newer compiler version.
Richard Barry
2019-12-30 21:59:11 +0000
49052a6581Ensure the XMC1000_IAR_KEIL_GCC projects still build after updates to the Cortex-M0 port layer - minor change to remove warning related to using a newer version of the IAR tools.
Richard Barry
2019-12-30 21:44:22 +0000
e292c67933Replace the static prvSetupTimerInterrupt() function in the Cortex-M port layers that still used it (other than MPU ports so far) with a weakly defined function call vPortSetupTimerInterrupt() - which allows application writers to override the function with one that uses a different clock.
Richard Barry
2019-12-30 21:16:09 +0000
e23d638afdCorrect use of xStreamBufferRead() to xStreamBufferReceive() in code comments - no source code changes.
Richard Barry
2019-12-30 20:00:49 +0000
c72df2f98dTidy up comments only.
Richard Barry
2019-12-27 21:22:07 +0000
7ddea8fc8bEnable the Win32 comprehensive test/demo build and run when configUSE_QUEUE_SETS is set to 0.
Richard Barry
2019-12-27 21:02:23 +0000
70dbc12579Update the LM3Sxxxx_IAR_Keil demo so the IAR project writes to the UART and executes in QEMU.
Richard Barry
2019-12-27 20:59:57 +0000
cef6548e8bUpdates to CM4_MPU RCDS port
Gaurav Aggarwal
2019-12-24 22:45:32 +0000
18c3e5e02aRemove local paths from the URL files
Gaurav Aggarwal
2019-12-24 19:16:19 +0000
05adf564f6Add readme into the third party RISC-V port that points to the directories that contains the official ports.
Richard Barry
2019-12-24 17:24:23 +0000
ce7e8b87d8Add IAR MPU project for STM32L475 Discovery Kit IoT Node
Gaurav Aggarwal
2019-12-21 00:04:04 +0000
96b6746364Updates to CM4_MPU IAR port
Gaurav Aggarwal
2019-12-21 00:02:31 +0000
b27fb82bc1Increase test coverage for queue sets. Rename the CORTEX_M0+_LPC51U68_LPCXpresso demo to CORTEX_M0+_LPC51U68_GCC_IAR_KEIL as it supports all three compilers.
Richard Barry
2019-12-20 02:54:30 +0000
b55bbe55acRemove build files accidentally checked in. Remove the CMSIS math library as it is large and not used.
Richard Barry
2019-12-20 02:49:15 +0000
d58e6a7b09Use linker script variables for MPU setup for Nuvoton M2351 Keil Project
Gaurav Aggarwal
2019-12-17 01:45:53 +0000
d449c8979dUse the linker script variables for MPU setup for Keil Simulator Demo
Gaurav Aggarwal
2019-12-17 00:14:26 +0000
66ce9f7d72Move warning suppression for IAR compiler to portmacro.h for v8M ports
Gaurav Aggarwal
2019-12-07 01:23:17 +0000
1deeb6dd84Check socket binding result before doing anything with socket. (This is to address ARG findings.) Breaking the single return rule here, due to precedent violation at line 1039 and 1144.
Yuhui.Zheng
2019-12-04 07:52:49 +0000
9491af1fd7Fix bug when xQueueOverwrite() and xQueueOverwrite() from ISR are used to overwrite items in two queues that are part of the same set. Minor queue optimisations.
Richard Barry
2019-12-03 01:50:07 +0000
e5708b38e9Add the Labs projects provided in the V10.2.1_191129 zip file.
Richard Barry
2019-12-02 23:39:25 +0000
46e5937529Remove guards against __ARMCC_VERSION version numbers that were previously used to avoid compiler warnings in some GCC ARM Cortex ports.
Richard Barry
2019-11-21 22:35:21 +0000
d1fb8907abAdd software timer to the Win32 blinky demo.
Richard Barry
2019-11-18 17:35:40 +0000
07622ed3eeRemove driver files that generate compiler warnings from the RISC-V_Renode_Emulator_SoftConsole project. Update RISC-V ports so the interrupt stack is set to a known value before the scheduler is started if the interrupt stack is statically defined rather than re-using the main.c() stack.
Richard Barry
2019-11-18 17:23:14 +0000
16639d2d63Update to the latest atomic.h. Improve commenting in RISC-V GCC port. Fix IAR RISC-V port so the first task starts with interrupts enabled. Add references to third party page ref using newlib with FreeRTOS into the tasks.c file in each place newlib is referenced. Move the position of the traceTASK_DELETE() trace macro in case of use with a memory allocator that writes over freed memory even when inside a critical section. Efficiency improvement: Make sure xTaskIncrementTick() does not return pdTRUE when the scheduler is locked. This just prevents an unnecessary yield interrupt (unnecessary as it is ignored) when xYieldPending happens to be pdTRUE.
Richard Barry
2019-11-18 16:28:03 +0000
18916d5820Rename the RISC-V_RV32_SiFive_Hifive1_GCC folder to RISC-V_RV32_SiFive_HiFive1_FreedomStudio as it is built with Freedom Studio.
Richard Barry
2019-10-22 22:30:06 +0000
5306ba245dAdd nano-specs linker option to HiFive1_GCC demo.
Richard Barry
2019-10-22 22:27:55 +0000
c0741e36edFix spelling mistakes copied and pasted into a couple of RISC-V demo main.c files.
Richard Barry
2019-10-22 16:31:57 +0000
fccc445865Change version and license text in RISC-V_RV32_SiFive_HiFive1_GCC FreeRTOSConfig.h file.
Richard Barry
2019-10-22 02:17:15 +0000
11c391dfb3Tidy up main_full.c and change alignment of variable accesses in RegTest.S for the RISC-V_Renode_Emulator_SoftConsole demo.
Richard Barry
2019-10-22 02:15:28 +0000
343fbe795fRework RISC-V QEMU example to use vanilla Eclipse in place of Freedom Studio. NOTE: RISC-V QEMU mtime interrupts are not generated consistently.
Richard Barry
2019-10-22 02:03:15 +0000
ef31243396Add some asserts into the common demo tasks to catch scenarios where the tasks are not being used but the part of the demo/test that gets called from the tick hook is called resultant in an access to objects that were not created.
Richard Barry
2019-10-21 17:17:34 +0000
61a003088dUpdate RISK-V GCC port to ensure the first task starts with interrupts enabled - previously its interrupts were only enabled after it yielded for the first time.
Richard Barry
2019-10-21 04:16:32 +0000
a83244a37eAdd the miv-basic.resc reNode script into the RISC-V_Renode_Emulator_SoftConsole demo as it is no longer shipped with the Microsemi tools.
Richard Barry
2019-10-17 20:39:40 +0000
c7c60cff15Rename RISC-V-Qemu-sive_e_Freedom_Studio directory to RISC-V-Qemu-sifive_e-Eclipse-GCC as it is now using Vanilla Eclipse and vanilla GCC in place of Freedom Studio.
Richard Barry
2019-10-16 04:31:57 +0000
f78ccd077aRecreate the RISC-V-Qemu demo using Vanilla Eclipse in place of Freedom Studio as there is not a new Freedom Studio project that targets the HiFive1 board, and the updated Freedom Studio version didn't work with this project any more anyway.
Richard Barry
2019-10-16 04:28:28 +0000
d435a7b62dMove the call to traceTASK_DELETE() to before port portPRE_TASK_DELETE_HOOK() as in the Windows port portPRE_TASK_DELETE_HOOK() never returns.
Richard Barry
2019-10-15 22:14:40 +0000
4922cff4ceAdd IAR demo for the SiFive RISC-V HiFive Rev B board.
Richard Barry
2019-10-14 03:20:18 +0000
f6edf4adf9Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignment of constant loads from assembly code.
Richard Barry
2019-10-14 00:16:25 +0000
96e61a10a5Tidy up the RISC-V_RV32_SiFive_HiFive1_GCC demo ready for its eventual release.
Richard Barry
2019-10-14 00:04:53 +0000
d4216903d9Added the "full" demo to the RISC-V_RV32_SiFive_HiFive1_GCC demo - backup check in only as still a work in progress.
Richard Barry
2019-10-13 22:53:00 +0000
71d9450836RIS-V_RV32_SiFive_HiFive1_GCC project now running the blinky demo - still a work in progress.
Richard Barry
2019-10-11 02:59:13 +0000
dbac79045cFormatting changes only.
Richard Barry
2019-10-10 17:56:10 +0000
dbbebbfcbcRISC-V-RV32_SiFive_HiFive1_GCC project is now also building the FreeRTOS kernel code - but not using it yet - still a work in progress.
Richard Barry
2019-10-10 17:54:56 +0000
9bb072a2abBase project to replace existing Freedom Studio project using latest Freedom Studio project format - builds and executes but does not yet include RTOS code.
Richard Barry
2019-10-09 04:50:11 +0000
fd118f1888Minor formatting change in comment only.
Richard Barry
2019-10-07 18:56:33 +0000
eb5c60c60bUpdate FreeRTOS.h with the version in GitHub. This is also to test submodule.
Yuhui.Zheng
2019-09-24 22:29:35 +0000
0fe36e497dNordic port. Notes for Richard -- the work items we discussed about for nrf52840-dk and Wiced_CY still remain. The only reason for this commit is we want to test out submodule.
Yuhui.Zheng
2019-09-24 22:26:36 +0000
35bc9d7938Revert 2728. Not because the files are still needed, but because we want to test out submodule.
Yuhui.Zheng
2019-09-24 22:19:54 +0000
f001126ea8Wiced_CY port is not needed anymore. Use GCC/ARM_CRx_No_GIC instead.
Yuhui.Zheng
2019-09-24 20:56:55 +0000
9052882500Adding tickless hooks to GCC/ARM_CRx_No_GIC port.
Yuhui.Zheng
2019-09-24 20:07:40 +0000
80c1cb5de1Correct code comments that referred to taskYIELD_FROM_ISR to portYIELD_FROM_ISR. Update RV32 port to use 16 byte-alignment all the time (only strictly necessary when using FLOP instructions).
Richard Barry
2019-09-24 16:06:21 +0000
c217b68d38sync from github to svn: this version of atomic.h does not have compiler specific symbols. compiler specific optimization is to be merged in each port/<compiler>/<arch> directory.
Yuhui.Zheng
2019-09-23 16:51:03 +0000
6f958bbf80sync from github to svn: Xtensa GCC as-is.
Yuhui.Zheng
2019-09-20 22:09:21 +0000
1c5fcc7f05sync from github to svn: Wiced_CY for AFR Cypress ports.
Yuhui.Zheng
2019-09-20 20:52:30 +0000
74df636c78sync from github to svn: documentation for RISC-V. This may be a temporary parking location.
Yuhui.Zheng
2019-09-20 20:47:29 +0000
cc0aee651esync from github to svn: Renasas/RX100 #pragma _VECT()
Yuhui.Zheng
2019-09-20 20:41:32 +0000
da3d370ff7RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.
Richard Barry
2019-09-04 15:46:45 +0000
96bad0f6c3Minor bug fix in NTPDemo.c -> use of FREERTOS_INVALID_SOCKET in place of NULL. Update trace recorder code to account for uxPendedTicks renaming to xPendedTicks.
Richard Barry
2019-09-04 00:13:17 +0000
ab41d89285Add IAR RISC-V port to SVN - a work in progress.
Richard Barry
2019-09-03 01:39:29 +0000
973a4f9869Correct alignment of stack top in RISC-V port when configISR_STACK_SIZE_WORDS is defined to a non zero value.
Richard Barry
2019-08-27 15:57:45 +0000
7d285f3dcb+ Moved the History.txt file from the website git repo into the source code SVN repo. + Added xTaskCatchUpTicks() which corrects the tick count value after the application code has held interrupts disabled for an extended period. + Updated the xTaskResumeAll() implementation so it uses the new xTaskCatchUpTicks() function mentioned above to unwind ticks that were pended while the scheduler was suspended. + Various maintenance on the message buffer, stream buffer and abort delay demos. + Change type of uxPendedTicks from UBaseType_t to TickType_t to ensure it has same type as variables it is compared to, and therefore also rename the variable xPendingTicks. + Correct spelling mistake within a comment that was common to all the ARMv7-M ports.
Richard Barry
2019-08-25 19:35:59 +0000
72af51cd86Starting point for IAR RISC-V project created some time ago - checking in now so it can be completed - currently work in progress.
Richard Barry
2019-08-04 15:24:15 +0000
5352cb4f45Tidy up Win32 port layer - include addition of new variable that prevents recursive attempts to obtain a mutex when the trace recorder is used inside an interrupt.
Richard Barry
2019-08-04 01:14:43 +0000
b1e35551c4Update the FreeRTOS version number in task.h
Gaurav Aggarwal
2019-07-29 23:48:11 +0000
6bad7d2055Add the default definition of configPRECONDITION to FreeRTOS.h.
Gaurav Aggarwal
2019-07-27 23:03:23 +0000
b4c06085e1Files as per 190725_FreeRTOS_IoT_Libs_Task_Pool_and_MQTT_Preview interim release.
Richard Barry
2019-07-25 20:20:24 +0000
b24ab46d39Delete obsolete makefiles that were causing confusion from RISC-V-Qemu-sifive_e-FreedomStudio demo.
Richard Barry
2019-07-25 20:11:37 +0000
10b7b52995Remove unnecessary include path from the MQTT demo.
Richard Barry
2019-07-24 02:01:43 +0000
38b6553abdCosmetic changes in the MQTT demo - mostly comment updates.
Gaurav Aggarwal
2019-07-24 01:29:01 +0000