Richard Barry
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7bea399061
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Update libraries and sundry check-ins ready for the V10.3.0 kernel release.
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2020-02-06 18:52:35 +00:00 |
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Richard Barry
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fbb23055cd
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Replace portasmHAS_CLINT with configMTIME_BASE_ADDRESS and configMTIMECMP_BASE_ADDRESS definitions in the GCC RISC-V port - portasmHAS_CLIT will still work by deriving the new definitions from the old.
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2020-01-07 01:14:36 +00:00 |
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Richard Barry
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b51529a284
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Update version number ready for next release.
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2019-05-11 01:47:37 +00:00 |
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Richard Barry
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2265d70499
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Correcting spelling mistakes in comments only.
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2019-03-08 17:30:49 +00:00 |
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Richard Barry
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58ba10eee8
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Update version number in readiness for V10.2.0 release.
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2019-02-17 22:36:16 +00:00 |
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Richard Barry
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b2b1b09ea5
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Fix bug in core_cm3.c atomic macros.
Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
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2019-02-16 01:08:38 +00:00 |
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