Commit Graph

10 Commits

Author SHA1 Message Date
Richard Barry
07622ed3ee Remove driver files that generate compiler warnings from the RISC-V_Renode_Emulator_SoftConsole project.
Update RISC-V ports so the interrupt stack is set to a known value before the scheduler is started if the interrupt stack is statically defined rather than re-using the main.c() stack.
2019-11-18 17:23:14 +00:00
Richard Barry
16639d2d63 Update to the latest atomic.h.
Improve commenting in RISC-V GCC port.
Fix IAR RISC-V port so the first task starts with interrupts enabled.
Add references to third party page ref using newlib with FreeRTOS into the tasks.c file in each place newlib is referenced.
Move the position of the traceTASK_DELETE() trace macro in case of use with a memory allocator that writes over freed memory even when inside a critical section.
Efficiency improvement:  Make sure xTaskIncrementTick() does not return pdTRUE when the scheduler is locked.  This just prevents an unnecessary yield interrupt (unnecessary as it is ignored) when xYieldPending happens to be pdTRUE.
2019-11-18 16:28:03 +00:00
Richard Barry
61a003088d Update RISK-V GCC port to ensure the first task starts with interrupts enabled - previously its interrupts were only enabled after it yielded for the first time. 2019-10-21 04:16:32 +00:00
Richard Barry
da3d370ff7 RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores. 2019-09-04 15:46:45 +00:00
Richard Barry
b51529a284 Update version number ready for next release. 2019-05-11 01:47:37 +00:00
Richard Barry
079d081346 Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches between 32-bit and 64-bit. 2019-04-29 00:57:14 +00:00
Richard Barry
606845492b Fix potential memory leak in the Win32 FreeRTOS+TCP network interface initialisation sequence.
Introduce portMEMORY_BARRIER() macro to assist with memory access ordering when suspending the scheduler if link time optimization is used.
2019-04-17 17:16:04 +00:00
Richard Barry
06596c3192 Prepare the RISC-V port layer for addition of 64-bit port. 2019-03-08 17:03:43 +00:00
Richard Barry
58ba10eee8 Update version number in readiness for V10.2.0 release. 2019-02-17 22:36:16 +00:00
Richard Barry
b2b1b09ea5 Fix bug in core_cm3.c atomic macros.
Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
2019-02-16 01:08:38 +00:00