CloudEdge/FreeRTOS-Kernel
Archived
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity
1,991 Commits 1 Branch 0 Tags 112 MiB
e2afb24747
Commit Graph

127 Commits

Author SHA1 Message Date
Richard Barry
eaacbb099a Clear up a few compiler warnings. 
Correct header comments in the UARTCommandConsole.c file used in the SmartFusion2 demo.
Exercise the new xQueueSpacesAvailable() function in the MSVC demo.
Add defaults for the new traceMALLOC and traceFREE trace macros.
Catch tasks trying to exit their functions in the Cortex-M0 ports.
Add additional comments to timers.c in response to a support forum question.
Initialise _impure_ptr prior to the first task being started.
Prior to V7.5.0 a yield pended in the tick hook would have occurred during the same tick interrupt.  Return pdTRUE from xTaskIncrementTick() if a yield is pending to revert to that behaviour.
 2013-10-07 12:06:17 +00:00
Richard Barry
7ec4773131 Add traceMALLOC() and traceFREE() macros. 2013-10-04 20:56:45 +00:00
Richard Barry
1902d2b64a Add the uxQueueSpacesAvailable() API function. 
Move a configASSERT() call in timers.c to prevent a "condition is always true" compiler warning.
 2013-09-10 13:19:12 +00:00
Richard Barry
73606369c4 Make Cortex-M0 set/clear interrupt flag from ISR functions nestable. 
Don't reset the stack location when starting the scheduler in Cortex-M0 ports as the vector offset register is not implemented and XMC1000 devices have their application vector address somewhere other than 0x00.
 2013-09-01 19:53:24 +00:00
Richard Barry
574f5044a6 Starting point for Keil Cortex-M0 port. 2013-08-25 01:01:18 +00:00
Richard Barry
c40370e96a Fix a few typos and remove the "register" keyword. 2013-08-16 13:31:54 +00:00
Richard Barry
63e8044d33 Allow compilation when portALT_GET_RUN_TIME_COUNTER_VALUE() is defined. 2013-08-14 08:35:40 +00:00
Richard Barry
2f754d9b0c Add additional critical section to the default tickless implementations. 
Update version number for maintenance release.
 2013-07-24 09:45:17 +00:00
Richard Barry
3cbe0a724d Update version number. 2013-07-23 10:51:45 +00:00
Richard Barry
8ceb665994 Void a few unused return values and make casting more C++ friendly. 2013-07-23 09:53:24 +00:00
Richard Barry
bb2093cf5d Update the header file included in the PIC32 port_asm.S file to use the header for the latest compiler version. 2013-07-23 09:50:06 +00:00
Richard Barry
679a3c670c Update the Cortex-M vPortValidateInterruptPriority() implementation to ensure compatibility with the STM32 standard peripheral library. 2013-07-23 09:44:00 +00:00
Richard Barry
9054485f1a Tidy up pre-processor as final act before tagging as V7.5.0 2013-07-19 10:22:47 +00:00
Richard Barry
08057fa77f Changes to comments only. 2013-07-19 09:16:36 +00:00
Richard Barry
203ae64600 Rename xTaskGetSystemState() uxTaskGetSystemState(). 2013-07-18 14:41:15 +00:00
Richard Barry
92fae7d262 For consistency change the name of configINCLUDE_STATS_FORMATTING_FUNCTIONS to configUSE_STATS_FORMATTING_FUNCTIONS. 2013-07-18 11:40:32 +00:00
Richard Barry
7d6758ee1a Minor updates and change version number for V7.5.0 release. 2013-07-17 18:32:57 +00:00
Richard Barry
7d1292ced2 Linting and MISRA checking 2013-07-15 14:27:15 +00:00
Richard Barry
e83b93f5fc Tidy up comments only. 2013-07-14 13:09:18 +00:00
Richard Barry
ce9c3b7413 Variable name change in the PIC32 port layer only. 2013-07-14 13:06:17 +00:00
Richard Barry
1e17924fa8 Update doxygen comments. 2013-07-13 19:58:42 +00:00
Richard Barry
da0fff63c9 Update Cortex-M MPU version to include new API functions. 2013-07-13 19:37:35 +00:00
Richard Barry
e5d9640863 Update RX ports to only include additional check on the existing IPL (so it is not lowered) if configASSERT() is defined. 2013-07-13 11:31:35 +00:00
Richard Barry
4b964814de Implement portASSERT_IF_INTERRUPT_PRIORITY_INVALID() for PIC32. 2013-07-12 19:25:21 +00:00
Richard Barry
ad8fa53043 Kernel optimisations. 2013-07-12 11:11:19 +00:00
Richard Barry
c9d9bddc3c Add comments to the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() calls in the core queue.c and tasks.c files. 2013-07-11 10:52:43 +00:00
Richard Barry
5d902f2b9c Complete additions of portASSERT_IF_INTERRUPT_PRIORITY_INVALID() for all RX compiler ports. 2013-07-11 10:05:06 +00:00
Richard Barry
65704174c9 Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the RX ports that use the Renesas compiler. 
Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the Cortex-A9 ports.
 2013-07-09 17:57:59 +00:00
Richard Barry
0f6b0d3a59 Enhance heap_4.c to prevent blocks accidentally being freed twice, or blocks that don't have a valid block link descriptor being freed. 
Update the Cortex-A9 port to include asserts if an ISR safe FreeRTOS function is called from an interrupt that has a higher logical priority than configMAX_SYSCALL_INTERRUPT_PRIORITY (or whatever the CA9 equivalent is called), and also assert if the binary point is not set correctly.
 2013-07-09 12:49:49 +00:00
Richard Barry
c4eef61d39 Added portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to Cortex-M3 and Cortex-M4F ports. 2013-07-04 11:20:28 +00:00
Richard Barry
b521d70e7e Remove compiler warnings. 2013-07-02 12:39:16 +00:00
Richard Barry
c1b4fc58d2 Add new xTaskGetSystemState() API function to return raw data on each task in the system. 
Relegate the vTaskList() and vTaskGetRunTimeStats() functions to "sample" functions demonstrating how to use xTaskGetSystemState() to generate human readable status information.
Introduce and default configINCLUDE_STATS_FORMATTING_FUNCTIONS which must now be defined to use vTaskList() and vTaskGetRunTimeStats().
 2013-07-02 12:10:16 +00:00
Richard Barry
877ce218a4 Add additional comment only. 2013-07-01 09:05:15 +00:00
Richard Barry
0c0b54c175 Refine the default tickless idle implementation in the Cortex-M3 port layers. 2013-06-30 10:38:31 +00:00
Richard Barry
b8a219b30c Update QueueOverwrite.c to include a call to xQueuePeekFromISR(). 
Default new QueuePeekFromISR() trace macros.
 2013-06-28 09:21:39 +00:00
Richard Barry
3b02b4c8f8 Add xQueueOverwriteFromISR() and update the QueueOverwrite.c to demonstrate its use. 2013-06-27 14:25:17 +00:00
Richard Barry
671949ad78 Add xQueueOverwrite() and a common demo task to demonstrate its use. 
Update MSVC Win32 demo to include the xQueueOverwrite() common demo tasks.
 2013-06-27 09:21:43 +00:00
Richard Barry
59f75a12f6 Add Newlib reent support. 2013-06-26 11:37:08 +00:00
Richard Barry
4444b4ee68 Improve efficiency and behaviour of vListInsertEnd(). 2013-06-26 08:58:01 +00:00
Richard Barry
f11635ed91 Remove reliance on strncpy() function. 2013-06-25 14:03:02 +00:00
Richard Barry
a7c47131fa Remove portALIGNMENT_ASSERT_pxCurrentTCB() macro, which serves no purpose. 2013-06-25 13:39:50 +00:00
Richard Barry
6cbbfd2eb5 Slight correction to coding standard in heap_2.c and heap_4.c. 2013-06-25 13:25:08 +00:00
Richard Barry
fb47260e80 Improve efficiency of memory allocation when the memory block is already aligned correctly. 2013-06-25 12:20:29 +00:00
Richard Barry
87049ac37c Re-implement the LPC18xx and SmartFusion2 run time stats implementation to use the free running Cortex-M cycle counter in place of the systick. 
Correct the run-time stats counter implementation in the RZ demo.
Guard against run time counters going backwards in tasks.c.
 2013-06-25 10:44:44 +00:00
Richard Barry
cdae14a8cb Replace the #define that maps the uxRecursiveCallCount to the pcReadFrom pointer with a union - although this is against the coding standard it seemed the best way of ensuring complete adherence to the C standard and allow correct builds with LLVM when the optimiser is on. 2013-06-24 12:20:00 +00:00
Richard Barry
e6903dac61 Add extra debug comment into list.c. 2013-06-23 07:27:46 +00:00
Richard Barry
3a507bdc0c Add missing function prototype. 2013-06-20 14:57:44 +00:00
Richard Barry
c3f9e3c5ff Update RVDS port layer to match IAR port layer. 2013-06-20 14:56:40 +00:00
Richard Barry
5013baa2cd RVDS ARM Cortex-A port layer. 2013-06-20 12:47:21 +00:00
Richard Barry
04dafed839 IAR ARM Cortex-A port layer. 2013-06-20 12:20:40 +00:00