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32 Commits

Author SHA1 Message Date
Richard Barry
0d1e12522b Update Cortex-M3 and Cortex-M4F ports to allow the SysTick to be clocked at a different speed than the system clock (as is done in the recent STM32L demo. ). 
Add additional asserts and isb instructions into the Cortex-M3 and Cortex-M4F ports.
 2013-12-12 14:07:20 +00:00
Richard Barry
00ad1a0200 Multiple tidy up, documentation corrections and typo corrections highlighted by Tamas Kleiber's diligent review. 2013-11-28 10:48:33 +00:00
Richard Barry
0cd79ad81d Change version numbers in preparation for V7.6.0 release. 2013-11-08 11:47:35 +00:00
Richard Barry
a12ea2d212 Update FreeRTOS version number to V7.5.3 
Update FreeRTOS+CLI version number to V1.0.2
Update FreeRTOS+UDP version number to V1.0.1
 2013-10-14 19:56:47 +00:00
Richard Barry
0c56f5018d Add some defensive programming in the default tickless mode in case the application supplied post tick hook takes a long time to complete. 2013-10-08 12:33:46 +00:00
Richard Barry
aedf7824cb Introduce the prvTaskExitError() function for all ARM_CMn ports. 
Introduce the configTASK_RETURN_ADDRESS macro for the GCC ARM_CMn ports.
Improve time slippage penalty when entering tickless mode is abandoned.
 2013-10-08 11:30:40 +00:00
Richard Barry
c40370e96a Fix a few typos and remove the "register" keyword. 2013-08-16 13:31:54 +00:00
Richard Barry
2f754d9b0c Add additional critical section to the default tickless implementations. 
Update version number for maintenance release.
 2013-07-24 09:45:17 +00:00
Richard Barry
3cbe0a724d Update version number. 2013-07-23 10:51:45 +00:00
Richard Barry
679a3c670c Update the Cortex-M vPortValidateInterruptPriority() implementation to ensure compatibility with the STM32 standard peripheral library. 2013-07-23 09:44:00 +00:00
Richard Barry
7d6758ee1a Minor updates and change version number for V7.5.0 release. 2013-07-17 18:32:57 +00:00
Richard Barry
65704174c9 Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the RX ports that use the Renesas compiler. 
Add portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to the Cortex-A9 ports.
 2013-07-09 17:57:59 +00:00
Richard Barry
c4eef61d39 Added portASSERT_IF_INTERRUPT_PRIORITY_INVALID() implementation to Cortex-M3 and Cortex-M4F ports. 2013-07-04 11:20:28 +00:00
Richard Barry
0c0b54c175 Refine the default tickless idle implementation in the Cortex-M3 port layers. 2013-06-30 10:38:31 +00:00
Richard Barry
c04b074707 Convert the remaining ports to use xTaskIncrementTick() in place of vTaskIncremenTick(). 2013-06-07 12:16:58 +00:00
Richard Barry
686d190798 Convert some ports to use xTaskIncrementTick() in place of vTaskIncrementTick(). 
Move DSB instructions to before WFI instructions in line with ARM recommendations.
 2013-06-06 15:46:40 +00:00
Richard Barry
a03b171992 Fix compiler warning in psp_test.c when compiled with ARM compiler. 
Add portYIELD_FROM_ISR() macros to Cortex-M ports.  The new macro just calls the exiting portEND_SWITCHING_ISR() macro.
Remove code from the MSVC port layer that was left over from a previous implementation and become obsolete.
 2013-05-19 09:43:00 +00:00
Richard Barry
96ceae8edd Update version number ready to release the FAT file system demo. 2013-04-30 21:42:41 +00:00
Richard Barry
f9918345e1 Update version numbers to V7.4.1. 2013-04-18 12:58:17 +00:00
Richard Barry
7132e88685 Add memory barrier instructions to the RVDS CM3 ports. 2013-04-16 15:30:43 +00:00
Richard Barry
a5d0e3f0c1 Prepare for V7.4.0 release. 2013-02-19 18:36:58 +00:00
Richard Barry
902f9e1a58 Update PIC32 demo application to remove reliance on PLIB functions. 
Update the default low power implementation in all the Cortex-M port layers to add a small critical section.
 2013-02-18 16:41:11 +00:00
Richard Barry
ac78adae4b Added INCLUDE_xSemaphoreGetMutexHolder() default. 
Changed eTaskStateGet() to eTaskGetState() and added #define to ensure backward compatibility.
Added configEXPECTED_IDLE_TIME_BEFORE_SLEEP definition - was previously hard coded to 2.
Slight change to the default CM3 tickless sleep function to allow the idle time to be set to zero in the pre-sleep processing macro.
Changed stack alignment for the FreeRTOS-MPU port to ensure it didn't trigger the assert() in the generic create function.
 2013-01-31 14:18:03 +00:00
Richard Barry
ba686260ca Make CM3/4 tick configuration a weak function to allow application writers to use an alternative tick source. 2012-10-29 15:56:26 +00:00
Richard Barry
f5c52bdb1d Re-jig some of the new functions to correctly assign them public or private linkage, and remove some functions that were added in but never used. 2012-10-22 16:40:45 +00:00
Richard Barry
f06a945444 Prepare for V7.3.0 release. 2012-10-16 12:17:47 +00:00
Richard Barry
e03ab659f3 Add tickless idle support in Cortex-M ports. 
Change CCS R4 directory name.
 2012-10-16 07:55:40 +00:00
Richard Barry
87f663a461 Correct #if( configMAX_PRIORITIES >= 32 ) check performed when configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 to instead be #if( configMAX_PRIORITIES > 32 ). 2012-09-24 12:10:08 +00:00
Richard Barry
92f1699055 Added Cortex-M optimised code to the IAR, GCC and Keil Cortex-M port layers. 
Tested and updated a few Cortex-M projects to use configUSE_PORT_OPTIMISED_TASK_SELECTION set to 1.
 2012-09-24 11:01:17 +00:00
Richard Barry
0c7af1c2d3 Put comments in the code that give a reference to people who think that setting BASE_PRI to zero is the wrong thing to to in an ISR. 2012-08-14 13:04:22 +00:00
Richard Barry
e0bab5981a Prepare for V7.2.0 release. 2012-08-14 12:14:48 +00:00
Richard Barry
f508a5f653 Add FreeRTOS-Plus directory. 2012-08-11 21:34:11 +00:00