Gaurav Aggarwal
d58e6a7b09
Use linker script variables for MPU setup for Nuvoton M2351 Keil Project
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Earlier we were using hard-coded addresses for MPU setup which
were ensured to be the same as linker script setup. This change
updates the Keil uVision project for Nuvoton Numaker-PFM-M2351
to use the variables exported from the linker script. This ensures
that the MPU setup never goes out of sync with linker script.
2019-12-17 01:45:53 +00:00
Gaurav Aggarwal
d449c8979d
Use the linker script variables for MPU setup for Keil Simulator Demo
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Earlier we were using hard-coded addresses for MPU setup which
were ensured to be the same as linker script setup. This change
updates the Keil Simulator demo to use the variables exported
from the linker script. This ensures that the MPU setup does not
go out of sync with linker script.
2019-12-17 00:14:26 +00:00
Gaurav Aggarwal
66ce9f7d72
Move warning suppression for IAR compiler to portmacro.h for v8M ports
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IAR produces some warnings which can not be fixed in the source code because
then other compilers start generating warnings. We suppressed those warnings
in the project file before. This change moves the warning suppression from
project files to portmacro.h.
2019-12-07 01:23:17 +00:00
Yuhui.Zheng
1deeb6dd84
Check socket binding result before doing anything with socket. (This is to address ARG findings.) Breaking the single return rule here, due to precedent violation at line 1039 and 1144.
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prvTransferConnect() now returns:
- pdTRUE: everything's good. pdTRUE = 1.
- -pdFREERTOS_ERRNO_ENOMEM: FreeRTOS_socket() failed. -pdFREERTOS_ERRNO_ENOMEM = -12.
- -pdFREERTOS_ERRNO_EINVAL || -pdFREERTOS_ERRNO_ECANCELED: FreeRTOS_bind() failed. Negative values.
Thus, at line 569 and line 617, needs to check != pdTRUE instead of == pdFALSE.
This commit is done on behalf of Alfred.
2019-12-04 07:52:49 +00:00
Richard Barry
9491af1fd7
Fix bug when xQueueOverwrite() and xQueueOverwrite() from ISR are used to overwrite items in two queues that are part of the same set.
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Minor queue optimisations.
2019-12-03 01:50:07 +00:00
Richard Barry
e5708b38e9
Add the Labs projects provided in the V10.2.1_191129 zip file.
2019-12-02 23:39:25 +00:00
Richard Barry
46e5937529
Remove guards against __ARMCC_VERSION version numbers that were previously used to avoid compiler warnings in some GCC ARM Cortex ports.
2019-11-21 22:35:21 +00:00
Richard Barry
d1fb8907ab
Add software timer to the Win32 blinky demo.
2019-11-18 17:35:40 +00:00
Richard Barry
07622ed3ee
Remove driver files that generate compiler warnings from the RISC-V_Renode_Emulator_SoftConsole project.
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Update RISC-V ports so the interrupt stack is set to a known value before the scheduler is started if the interrupt stack is statically defined rather than re-using the main.c() stack.
2019-11-18 17:23:14 +00:00
Richard Barry
16639d2d63
Update to the latest atomic.h.
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Improve commenting in RISC-V GCC port.
Fix IAR RISC-V port so the first task starts with interrupts enabled.
Add references to third party page ref using newlib with FreeRTOS into the tasks.c file in each place newlib is referenced.
Move the position of the traceTASK_DELETE() trace macro in case of use with a memory allocator that writes over freed memory even when inside a critical section.
Efficiency improvement: Make sure xTaskIncrementTick() does not return pdTRUE when the scheduler is locked. This just prevents an unnecessary yield interrupt (unnecessary as it is ignored) when xYieldPending happens to be pdTRUE.
2019-11-18 16:28:03 +00:00
Richard Barry
18916d5820
Rename the RISC-V_RV32_SiFive_Hifive1_GCC folder to RISC-V_RV32_SiFive_HiFive1_FreedomStudio as it is built with Freedom Studio.
2019-10-22 22:30:06 +00:00
Richard Barry
5306ba245d
Add nano-specs linker option to HiFive1_GCC demo.
2019-10-22 22:27:55 +00:00
Richard Barry
c0741e36ed
Fix spelling mistakes copied and pasted into a couple of RISC-V demo main.c files.
2019-10-22 16:31:57 +00:00
Richard Barry
fccc445865
Change version and license text in RISC-V_RV32_SiFive_HiFive1_GCC FreeRTOSConfig.h file.
2019-10-22 02:17:15 +00:00
Richard Barry
11c391dfb3
Tidy up main_full.c and change alignment of variable accesses in RegTest.S for the RISC-V_Renode_Emulator_SoftConsole demo.
2019-10-22 02:15:28 +00:00
Richard Barry
343fbe795f
Rework RISC-V QEMU example to use vanilla Eclipse in place of Freedom Studio. NOTE: RISC-V QEMU mtime interrupts are not generated consistently.
2019-10-22 02:03:15 +00:00
Richard Barry
ef31243396
Add some asserts into the common demo tasks to catch scenarios where the tasks are not being used but the part of the demo/test that gets called from the tick hook is called resultant in an access to objects that were not created.
2019-10-21 17:17:34 +00:00
Richard Barry
61a003088d
Update RISK-V GCC port to ensure the first task starts with interrupts enabled - previously its interrupts were only enabled after it yielded for the first time.
2019-10-21 04:16:32 +00:00
Richard Barry
a83244a37e
Add the miv-basic.resc reNode script into the RISC-V_Renode_Emulator_SoftConsole demo as it is no longer shipped with the Microsemi tools.
2019-10-17 20:39:40 +00:00
Richard Barry
c7c60cff15
Rename RISC-V-Qemu-sive_e_Freedom_Studio directory to RISC-V-Qemu-sifive_e-Eclipse-GCC as it is now using Vanilla Eclipse and vanilla GCC in place of Freedom Studio.
2019-10-16 04:31:57 +00:00
Richard Barry
f78ccd077a
Recreate the RISC-V-Qemu demo using Vanilla Eclipse in place of Freedom Studio as there is not a new Freedom Studio project that targets the HiFive1 board, and the updated Freedom Studio version didn't work with this project any more anyway.
2019-10-16 04:28:28 +00:00
Richard Barry
d435a7b62d
Move the call to traceTASK_DELETE() to before port portPRE_TASK_DELETE_HOOK() as in the Windows port portPRE_TASK_DELETE_HOOK() never returns.
2019-10-15 22:14:40 +00:00
Richard Barry
4922cff4ce
Add IAR demo for the SiFive RISC-V HiFive Rev B board.
2019-10-14 03:20:18 +00:00
Richard Barry
f6edf4adf9
Update the RegTest.S file used by several GCC RISC-V demos to ensure correct alignment of constant loads from assembly code.
2019-10-14 00:16:25 +00:00
Richard Barry
96e61a10a5
Tidy up the RISC-V_RV32_SiFive_HiFive1_GCC demo ready for its eventual release.
2019-10-14 00:04:53 +00:00
Richard Barry
d4216903d9
Added the "full" demo to the RISC-V_RV32_SiFive_HiFive1_GCC demo - backup check in only as still a work in progress.
2019-10-13 22:53:00 +00:00
Richard Barry
71d9450836
RIS-V_RV32_SiFive_HiFive1_GCC project now running the blinky demo - still a work in progress.
2019-10-11 02:59:13 +00:00
Richard Barry
dbac79045c
Formatting changes only.
2019-10-10 17:56:10 +00:00
Richard Barry
dbbebbfcbc
RISC-V-RV32_SiFive_HiFive1_GCC project is now also building the FreeRTOS kernel code - but not using it yet - still a work in progress.
2019-10-10 17:54:56 +00:00
Richard Barry
9bb072a2ab
Base project to replace existing Freedom Studio project using latest Freedom Studio project format - builds and executes but does not yet include RTOS code.
2019-10-09 04:50:11 +00:00
Richard Barry
fd118f1888
Minor formatting change in comment only.
2019-10-07 18:56:33 +00:00
Yuhui.Zheng
eb5c60c60b
Update FreeRTOS.h with the version in GitHub. This is also to test submodule.
2019-09-24 22:29:35 +00:00
Yuhui.Zheng
0fe36e497d
Nordic port. Notes for Richard -- the work items we discussed about for nrf52840-dk and Wiced_CY still remain. The only reason for this commit is we want to test out submodule.
2019-09-24 22:26:36 +00:00
Yuhui.Zheng
35bc9d7938
Revert 2728. Not because the files are still needed, but because we want to test out submodule.
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Before further updating project files in GitHub, keeping an additional copy.
2019-09-24 22:19:54 +00:00
Yuhui.Zheng
f001126ea8
Wiced_CY port is not needed anymore. Use GCC/ARM_CRx_No_GIC instead.
2019-09-24 20:56:55 +00:00
Yuhui.Zheng
9052882500
Adding tickless hooks to GCC/ARM_CRx_No_GIC port.
2019-09-24 20:07:40 +00:00
Richard Barry
80c1cb5de1
Correct code comments that referred to taskYIELD_FROM_ISR to portYIELD_FROM_ISR.
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Update RV32 port to use 16 byte-alignment all the time (only strictly necessary when using FLOP instructions).
2019-09-24 16:06:21 +00:00
Yuhui.Zheng
c217b68d38
sync from github to svn: this version of atomic.h does not have compiler specific symbols. compiler specific optimization is to be merged in each port/<compiler>/<arch> directory.
2019-09-23 16:51:03 +00:00
Yuhui.Zheng
6f958bbf80
sync from github to svn: Xtensa GCC as-is.
2019-09-20 22:09:21 +00:00
Yuhui.Zheng
1c5fcc7f05
sync from github to svn: Wiced_CY for AFR Cypress ports.
2019-09-20 20:52:30 +00:00
Yuhui.Zheng
74df636c78
sync from github to svn: documentation for RISC-V. This may be a temporary parking location.
2019-09-20 20:47:29 +00:00
Yuhui.Zheng
cc0aee651e
sync from github to svn: Renasas/RX100 #pragma _VECT()
2019-09-20 20:41:32 +00:00
Richard Barry
da3d370ff7
RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.
2019-09-04 15:46:45 +00:00
Richard Barry
96bad0f6c3
Minor bug fix in NTPDemo.c -> use of FREERTOS_INVALID_SOCKET in place of NULL.
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Update trace recorder code to account for uxPendedTicks renaming to xPendedTicks.
2019-09-04 00:13:17 +00:00
Richard Barry
ab41d89285
Add IAR RISC-V port to SVN - a work in progress.
2019-09-03 01:39:29 +00:00
Yuhui Zheng
2b546b1984
Atollic project update for CORTEX_M0_Infineon_XMC1000_IAR_Keil_GCC, GCC port.
2019-08-30 00:18:41 +00:00
Richard Barry
973a4f9869
Correct alignment of stack top in RISC-V port when configISR_STACK_SIZE_WORDS is defined to a non zero value.
2019-08-27 15:57:45 +00:00
Richard Barry
7d285f3dcb
+ Moved the History.txt file from the website git repo into the source code SVN repo.
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+ Added xTaskCatchUpTicks() which corrects the tick count value after the application code has held interrupts disabled for an extended period.
+ Updated the xTaskResumeAll() implementation so it uses the new xTaskCatchUpTicks() function mentioned above to unwind ticks that were pended while the scheduler was suspended.
+ Various maintenance on the message buffer, stream buffer and abort delay demos.
+ Change type of uxPendedTicks from UBaseType_t to TickType_t to ensure it has same type as variables it is compared to, and therefore also rename the variable xPendingTicks.
+ Correct spelling mistake within a comment that was common to all the ARMv7-M ports.
2019-08-25 19:35:59 +00:00
Richard Barry
72af51cd86
Starting point for IAR RISC-V project created some time ago - checking in now so it can be completed - currently work in progress.
2019-08-04 15:24:15 +00:00
Richard Barry
5352cb4f45
Tidy up Win32 port layer - include addition of new variable that prevents recursive attempts to obtain a mutex when the trace recorder is used inside an interrupt.
2019-08-04 01:14:43 +00:00
