Commit Graph

33 Commits

Author SHA1 Message Date
Richard Barry
7132e88685 Add memory barrier instructions to the RVDS CM3 ports. 2013-04-16 15:30:43 +00:00
Richard Barry
895ee2bb3e Add barrier instructions to IAR CM3 ports. 2013-04-16 14:56:49 +00:00
Richard Barry
d135e45676 Replace the read back of the software interrupt register with barrier instructions (CCS/RM48/TMS570). 2013-04-16 14:17:35 +00:00
Richard Barry
0527099b51 Add barrier instructions to the GCC CM3 ports. 2013-04-16 14:16:30 +00:00
Richard Barry
6d20e2b5cd Add barrier instructions to GCC CM3/4 code. 2013-04-07 19:43:52 +00:00
Richard Barry
3762630f27 RL78/IAR port - Allow the end user to define their own tick interrupt configuration by defining configSETUP_TIMER_INTERRUPT(). 2013-03-25 17:00:13 +00:00
Richard Barry
a9b8f0ca69 Minor mods common files to fix warnings generated by Renesas compiler.
Correct the header comments in het.c and het.h (RM48/TMS570 demo) which were corrupt.
Correct version numbers in RX63N Renesas compiler demo.
Ensure stacks set up for tasks in the RX200 port layer end on 8 byte boundaries (was 4, which didn't matter but didn't match the definition).
Replaced unqualified (unsigned) in calls to standard functions with (size_t).
2013-03-25 16:30:42 +00:00
Richard Barry
caf1fbc899 Ensure IAR RL port layer works on devices using two different naming conventions for the interval timer registers. 2013-03-18 16:40:47 +00:00
Richard Barry
8c66fdbb8c Updated IAR RL78 port layer. 2013-03-17 16:54:17 +00:00
Richard Barry
17bba16fa6 Added YRDKRL78G14 build configuration to the IAR RL78 demo. 2013-02-24 19:48:26 +00:00
Richard Barry
a5d0e3f0c1 Prepare for V7.4.0 release. 2013-02-19 18:36:58 +00:00
Richard Barry
902f9e1a58 Update PIC32 demo application to remove reliance on PLIB functions.
Update the default low power implementation in all the Cortex-M port layers to add a small critical section.
2013-02-18 16:41:11 +00:00
Richard Barry
a7eae6bed3 Added more files to the Rowley and IAR LM3S demos to test building the newer files and queue sets.
Made queue function prototypes consistent so xQueueHandle parameters are always xQueue, and xQUEUE * parameters pxQueue.
Likewise make the task API using px for pointers to TCBs, and just x for task handles.
Heap_x functions now automatically align the start of the heap without using the portDOUBLE union member.
Queue.c now includes queue.h.
2013-02-12 17:35:43 +00:00
Richard Barry
b671bf368a Improve QueueSet.c test coverage by reading the queue set from an ISR to force paths through the queue locking and unlocking.
Add the FreeRTOS+Trace recorder into the Win32 MSVC demo.
Added more functions, including the queue set functions, to the MPU port.
2013-02-12 10:09:36 +00:00
Richard Barry
b5b518571e remove the additional line added to the MPU port.c as the original code was correct. Instead remove the alignment assert by adding #define portALIGNMENT_ASSERT_pxCurrentTCB ( void )
to the portmacor.h file.
2013-01-31 15:27:00 +00:00
Richard Barry
ac78adae4b Added INCLUDE_xSemaphoreGetMutexHolder() default.
Changed eTaskStateGet() to eTaskGetState() and added #define to ensure backward compatibility.
Added configEXPECTED_IDLE_TIME_BEFORE_SLEEP definition - was previously hard coded to 2.
Slight change to the default CM3 tickless sleep function to allow the idle time to be set to zero in the pre-sleep processing macro.
Changed stack alignment for the FreeRTOS-MPU port to ensure it didn't trigger the assert() in the generic create function.
2013-01-31 14:18:03 +00:00
Richard Barry
4e7b460eaf Replace the CLZ function with a CLZ intrinsic in the Cortex-R4 port layer.
Add EDS support in the PIC24 port layer.
Remove unnecessary EHB instructions from PIC32 port.
In the PIC32 port assembly code, replace the &= code with a single ins instruction.
2013-01-23 16:06:45 +00:00
Richard Barry
96f93690ce Add warning suppression to IAR header. 2012-10-31 13:30:44 +00:00
Richard Barry
ba686260ca Make CM3/4 tick configuration a weak function to allow application writers to use an alternative tick source. 2012-10-29 15:56:26 +00:00
Richard Barry
9fe5156b53 Work around compiler bug in CCS5 by replacing the _call_swi() function with a #pragma SWI_ALIAS. 2012-10-29 11:38:19 +00:00
Richard Barry
f5c52bdb1d Re-jig some of the new functions to correctly assign them public or private linkage, and remove some functions that were added in but never used. 2012-10-22 16:40:45 +00:00
Richard Barry
f06a945444 Prepare for V7.3.0 release. 2012-10-16 12:17:47 +00:00
Richard Barry
f446f77fd4 Make the timer used for the PIC32 port layer user configurable. 2012-10-16 09:48:45 +00:00
Richard Barry
e03ab659f3 Add tickless idle support in Cortex-M ports.
Change CCS R4 directory name.
2012-10-16 07:55:40 +00:00
Richard Barry
c403e974ee Update PIC32 port to make use of configUSE_PORT_OPTIMISED_TASK_SELECTION.
Make small modification in GCC CM3 port when configUSE_PORT_OPTIMISED_TASK_SELECTION is set to 1 to remove compiler warning.
2012-09-25 18:18:37 +00:00
Richard Barry
87f663a461 Correct #if( configMAX_PRIORITIES >= 32 ) check performed when configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 to instead be #if( configMAX_PRIORITIES > 32 ). 2012-09-24 12:10:08 +00:00
Richard Barry
92f1699055 Added Cortex-M optimised code to the IAR, GCC and Keil Cortex-M port layers.
Tested and updated a few Cortex-M projects to use configUSE_PORT_OPTIMISED_TASK_SELECTION set to 1.
2012-09-24 11:01:17 +00:00
Richard Barry
670d172cfc Introduced configUSE_PORT_OPTIMISED_TASK_SELECTION, and updated the MSVC simulator port as the first implementation. 2012-09-23 14:35:12 +00:00
Richard Barry
8ef7f03536 Add eTaskStateGet() to FreeRTOS-MPU. 2012-09-23 09:35:53 +00:00
Richard Barry
0c7af1c2d3 Put comments in the code that give a reference to people who think that setting BASE_PRI to zero is the wrong thing to to in an ISR. 2012-08-14 13:04:22 +00:00
Richard Barry
e0bab5981a Prepare for V7.2.0 release. 2012-08-14 12:14:48 +00:00
Richard Barry
73ad4387e2 Remove the remnants of the legacy trace functionality (since replaced with FreeRTOS+Trace).
Replaced the #error that traps configMAX_SYSCALL_INTERRUPT_PRIORITY being set to 0 with a configASSERT() for GCC Cortex-M3/4 ports as the #error does not work if configMAX_SYSCALL_INTERRUPT_PRIORITY includes any casting.  Not a problem for other compilers as they cannot have casting anyway as that would break the assembly code.
2012-08-12 17:05:23 +00:00
Richard Barry
f508a5f653 Add FreeRTOS-Plus directory. 2012-08-11 21:34:11 +00:00