2 Commits

Author	SHA1	Message	Date
Stephane Viau	68ddb32b55	Handle interrupt acknowledge register in Cortex-A53 SRE port (#392) ... Let the FreeRTOS IRQ handler properly store and restore the ICCIAR register value around the vApplicationIRQHandler() call. Signed-off-by: Stephane Viau <stephane.viau@oss.nxp.com> Co-authored-by: Stephane Viau <stephane.viau@oss.nxp.com> Co-authored-by: Gaurav-Aggarwal-AWS <33462878+aggarg@users.noreply.github.com>	2021-10-15 09:21:56 -07:00
Gaurav-Aggarwal-AWS	4e3bf0f5c0	Add Cortex-A53 port with system register interface for CPU interface access (#357) ... The difference between this port and portable/GCC/ARM_CA53_64_BIT is that this port uses System Register interface to access CPU interface while the other one uses Memory-mapped interface. Signed-off-by: Gaurav Aggarwal Co-authored-by: Cobus van Eeden <35851496+cobusve@users.noreply.github.com>	2021-06-22 18:51:58 -07:00