Richard Barry
|
da3d370ff7
|
RISC-V port updates: The machine timer compare register can now be for any HART, and correct the sequence used to update the 64-bit machine timer compare register on 32-bit cores.
|
2019-09-04 15:46:45 +00:00 |
|
Richard Barry
|
973a4f9869
|
Correct alignment of stack top in RISC-V port when configISR_STACK_SIZE_WORDS is defined to a non zero value.
|
2019-08-27 15:57:45 +00:00 |
|
Richard Barry
|
b51529a284
|
Update version number ready for next release.
|
2019-05-11 01:47:37 +00:00 |
|
Richard Barry
|
079d081346
|
Basic 64-bit RISC-V port now functional. RISC-V port layer automatically switches between 32-bit and 64-bit.
|
2019-04-29 00:57:14 +00:00 |
|
Richard Barry
|
58ba10eee8
|
Update version number in readiness for V10.2.0 release.
|
2019-02-17 22:36:16 +00:00 |
|
Richard Barry
|
b2b1b09ea5
|
Fix bug in core_cm3.c atomic macros.
Rename the portable/GCC/RISC-V-RV32 directory to just RISC-V as also adding support for 64-bit cores.
|
2019-02-16 01:08:38 +00:00 |
|