Richard Barry
3762630f27
RL78/IAR port - Allow the end user to define their own tick interrupt configuration by defining configSETUP_TIMER_INTERRUPT().
2013-03-25 17:00:13 +00:00
Richard Barry
caf1fbc899
Ensure IAR RL port layer works on devices using two different naming conventions for the interval timer registers.
2013-03-18 16:40:47 +00:00
Richard Barry
8c66fdbb8c
Updated IAR RL78 port layer.
2013-03-17 16:54:17 +00:00
Richard Barry
17bba16fa6
Added YRDKRL78G14 build configuration to the IAR RL78 demo.
2013-02-24 19:48:26 +00:00
Richard Barry
a5d0e3f0c1
Prepare for V7.4.0 release.
2013-02-19 18:36:58 +00:00
Richard Barry
902f9e1a58
Update PIC32 demo application to remove reliance on PLIB functions.
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Update the default low power implementation in all the Cortex-M port layers to add a small critical section.
2013-02-18 16:41:11 +00:00
Richard Barry
ac78adae4b
Added INCLUDE_xSemaphoreGetMutexHolder() default.
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Changed eTaskStateGet() to eTaskGetState() and added #define to ensure backward compatibility.
Added configEXPECTED_IDLE_TIME_BEFORE_SLEEP definition - was previously hard coded to 2.
Slight change to the default CM3 tickless sleep function to allow the idle time to be set to zero in the pre-sleep processing macro.
Changed stack alignment for the FreeRTOS-MPU port to ensure it didn't trigger the assert() in the generic create function.
2013-01-31 14:18:03 +00:00
Richard Barry
96f93690ce
Add warning suppression to IAR header.
2012-10-31 13:30:44 +00:00
Richard Barry
ba686260ca
Make CM3/4 tick configuration a weak function to allow application writers to use an alternative tick source.
2012-10-29 15:56:26 +00:00
Richard Barry
f5c52bdb1d
Re-jig some of the new functions to correctly assign them public or private linkage, and remove some functions that were added in but never used.
2012-10-22 16:40:45 +00:00
Richard Barry
f06a945444
Prepare for V7.3.0 release.
2012-10-16 12:17:47 +00:00
Richard Barry
e03ab659f3
Add tickless idle support in Cortex-M ports.
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Change CCS R4 directory name.
2012-10-16 07:55:40 +00:00
Richard Barry
87f663a461
Correct #if( configMAX_PRIORITIES >= 32 ) check performed when configUSE_PORT_OPTIMISED_TASK_SELECTION == 1 to instead be #if( configMAX_PRIORITIES > 32 ).
2012-09-24 12:10:08 +00:00
Richard Barry
92f1699055
Added Cortex-M optimised code to the IAR, GCC and Keil Cortex-M port layers.
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Tested and updated a few Cortex-M projects to use configUSE_PORT_OPTIMISED_TASK_SELECTION set to 1.
2012-09-24 11:01:17 +00:00
Richard Barry
0c7af1c2d3
Put comments in the code that give a reference to people who think that setting BASE_PRI to zero is the wrong thing to to in an ISR.
2012-08-14 13:04:22 +00:00
Richard Barry
e0bab5981a
Prepare for V7.2.0 release.
2012-08-14 12:14:48 +00:00
Richard Barry
73ad4387e2
Remove the remnants of the legacy trace functionality (since replaced with FreeRTOS+Trace).
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Replaced the #error that traps configMAX_SYSCALL_INTERRUPT_PRIORITY being set to 0 with a configASSERT() for GCC Cortex-M3/4 ports as the #error does not work if configMAX_SYSCALL_INTERRUPT_PRIORITY includes any casting. Not a problem for other compilers as they cannot have casting anyway as that would break the assembly code.
2012-08-12 17:05:23 +00:00
Richard Barry
f508a5f653
Add FreeRTOS-Plus directory.
2012-08-11 21:34:11 +00:00
