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Simplify and improve GIC-less Cortex-R4 port.

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Add final tests into RZ/T demo.
This commit is contained in:
Richard Barry 2015-09-12 12:14:58 +00:00
parent b9f235846f
commit f19497c3d6
12 changed files with 152 additions and 505 deletions
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29
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/.cproject
View File

@ -74,23 +74,23 @@
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<option id="com.renesas.cdt.core.Compiler.option.warning29.1388878801" name="Issue Warning if a bad g++ synthesiser(-Wsynth)" superClass="com.renesas.cdt.core.Compiler.option.warning29" value="false" valueType="boolean"/>
<option id="com.renesas.cdt.core.Compiler.option.warning30.1994659686" name="Issue Warning about c and ansi c construct incompatibility(-Wtraditional)" superClass="com.renesas.cdt.core.Compiler.option.warning30" value="false" valueType="boolean"/>
<option id="com.renesas.cdt.core.Compiler.option.warning31.531473224" name="Give string constants the type 'const char[length]'(-Wwrite-strings)" superClass="com.renesas.cdt.core.Compiler.option.warning31" value="true" valueType="boolean"/>
<option id="com.renesas.cdt.core.Compiler.option.warning31.531473224" name="Give string constants the type 'const char[length]'(-Wwrite-strings)" superClass="com.renesas.cdt.core.Compiler.option.warning31" value="false" valueType="boolean"/>
<option id="com.renesas.cdt.core.Compiler.option.CPUSeries.114360178" name="Cpu Series" superClass="com.renesas.cdt.core.Compiler.option.CPUSeries"/>
<inputType id="%Base.Compiler.C.InputType.Id.321945067" name="C Input" superClass="%Base.Compiler.C.InputType.Id"/>
<inputType id="Base.Compiler.CPP.InputType.Id.678276075" name="C++ Input" superClass="Base.Compiler.CPP.InputType.Id"/>
@ -143,9 +143,6 @@
<tool id="com.renesas.cdt.rz.hardwaredebug.win32.tool.objcopy.Id.1674695683" name="Objcopy" superClass="com.renesas.cdt.rz.hardwaredebug.win32.tool.objcopy.Id"/>
</toolChain>
</folderInfo>
<fileInfo id="com.renesas.cdt.rz.hardwaredebug.win32.configuration.Id.137003302.1852356998" name="IntQueue.c" rcbsApplicability="disable" resourcePath="src/Full_Demo/Standard_Demo_Tasks/IntQueue.c" toolsToInvoke="com.renesas.cdt.rz.hardwaredebug.win32.tool.compiler.Id.542544613.1778364722">
<tool id="com.renesas.cdt.rz.hardwaredebug.win32.tool.compiler.Id.542544613.1778364722" name="Compiler" superClass="com.renesas.cdt.rz.hardwaredebug.win32.tool.compiler.Id.542544613"/>
</fileInfo>
<sourceEntries>
<entry excluding="System/GCC/src/gnu_io.c|System/GCC/src/syscalls.c" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>

3
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/System/GCC/src/loader_init2.c
View File

@ -98,8 +98,7 @@ void loader_init2 (void)
R_ATCM_WaitSet(ATCM_WAIT_1_OPT);
/* Initialise I1, D1 Cache and MPU setting */
#warning Cache not enabled.
// cache_init();
cache_init();
/* Set RZ/T1 to Low-vector (SCTLR.V = 0) */
set_low_vec();

67
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/FreeRTOS_tick_config.c
View File

@ -69,7 +69,6 @@
/* FreeRTOS includes. */
#include "FreeRTOS.h"
#include "ISR_Support.h"
/* Renesas includes. */
#include "r_cg_macrodriver.h"
@ -79,11 +78,31 @@
/*-----------------------------------------------------------*/
/*
* Entry point for the FreeRTOS tick interrupt. This provides the prolog code
* necessary to support interrupt nesting.
* Entry point for the FreeRTOS tick interrupt. This sets the pxISRFunction
* variable to point to the RTOS tick handler, then branches to the FreeRTOS
* IRQ handler.
*/
static void FreeRTOS_Tick_Handler_Entry( void ) __attribute__((naked));
/*
* The FreeRTOS IRQ handler, which is implemented in the RTOS port layer.
*/
extern void FreeRTOS_IRQ_Handler( void );
/*
* The function called by the FreeRTOS_IRQ_Handler() to call the actual
* peripheral handler.
*/
void vApplicationIRQHandler( void );
/*-----------------------------------------------------------*/
/*
* Variable used to hold the address of the interrupt handler the FreeRTOS IRQ
* handler will branch to.
*/
ISRFunction_t pxISRFunction = NULL;
/*-----------------------------------------------------------*/
/*
@ -107,7 +126,6 @@ const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL;
/* Interrupt on compare match. */
CMT5.CMCR.BIT.CMIE = 1;
#warning Tick rate is not yet accurate.
/* Calculate the compare match value. */
ulCompareMatchValue = configCPU_CLOCK_HZ / ulPeripheralClockDivider;
ulCompareMatchValue /= ulCMTClockDivider;
@ -139,14 +157,43 @@ const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL;
}
/*-----------------------------------------------------------*/
/*
* The function called by the FreeRTOS IRQ handler, after it has managed
* interrupt entry. This function creates a local copy of pxISRFunction before
* re-enabling interrupts and actually calling the handler pointed to by
* pxISRFunction.
*/
void vApplicationIRQHandler( void )
{
ISRFunction_t pxISRToCall = pxISRFunction;
portENABLE_INTERRUPTS();
/* Call the installed ISR. */
pxISRToCall();
}
/*-----------------------------------------------------------*/
/*
* The RZ/T vectors directly to a peripheral specific interrupt handler, rather
* than using the Cortex-R IRQ vector. Therefore each interrupt handler
* installed by the application must follow the example below, which saves a
* pointer to a standard C function in the pxISRFunction variable, before
* branching to the FreeRTOS IRQ handler. The FreeRTOS IRQ handler then manages
* interrupt entry (including interrupt nesting), before calling the C function
* saved in the pxISRFunction variable. NOTE: This entry point is a naked
* function - do not add C code to this function.
*/
static void FreeRTOS_Tick_Handler_Entry( void )
{
/* This is a naked function, and should not include any C code. */
portNESTING_INTERRUPT_ENTRY();
__asm volatile( " LDR r1, vTickHandlerConst \t\n"
" BLX r1 \t\n"
" vTickHandlerConst: .word FreeRTOS_Tick_Handler " );
portNESTING_INTERRUPT_EXIT();
__asm volatile ( \
"PUSH {r0-r1} \t\n" \
"LDR r0, =pxISRFunction \t\n" \
"LDR R1, =FreeRTOS_Tick_Handler \t\n" \
"STR R1, [r0] \t\n" \
"POP {r0-r1} \t\n" \
"B FreeRTOS_IRQ_Handler "
);
}
/*-----------------------------------------------------------*/

69
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/IntQueueTimer.c
View File

@ -86,22 +86,30 @@
#include "r_cg_cmt.h"
#include "r_reset.h"
#define tmrCMT_1_CHANNEL_0_HZ ( 2000UL )
#define tmrCMT_1_CHANNEL_0_HZ ( 4000UL )
#define tmrCMT_1_CHANNEL_1_HZ ( 2011UL )
/* Handlers for the two timers used. See the documentation page
for this port on http://www.FreeRTOS.org for more information on writing
interrupt handlers. */
/*
* Handlers for the two timers used. See the documentation page
* for this port on TBD for more information on writing
* interrupt handlers.
*/
void vCMT_1_Channel_0_ISR( void );
void vCMT_1_Channel_1_ISR( void );
/*
* Entry point for the handlers. These set the pxISRFunction variable to point
* to the C handler for each timer, then branch to the FreeRTOS IRQ handler.
*/
static void vCMT_1_Channel_0_ISR_Entry( void ) __attribute__((naked));
static void vCMT_1_Channel_1_ISR_Entry( void ) __attribute__((naked));
/*-----------------------------------------------------------*/
void vInitialiseTimerForIntQueueTest( void )
{
uint32_t ulCompareMatchValue;
const uint32_t ulPeripheralClockDivider = 6UL, ulCMTClockDivider = 8UL;
extern void FreeRTOS_IRQ_Handler( void );
/* Disable CMI2 and CMI3 interrupts. */
VIC.IEC0.LONG = ( 1UL << 23UL ) | ( 1UL << 24UL );
@ -140,16 +148,15 @@ extern void FreeRTOS_IRQ_Handler( void );
VIC.PLS0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL );
/* Set CMI2 and CMI3 priority levels so they nest. */
VIC.PRL23.LONG = _CMT_PRIORITY_LEVEL10;
VIC.PRL23.LONG = _CMT_PRIORITY_LEVEL2;
VIC.PRL24.LONG = _CMT_PRIORITY_LEVEL9;
/* Set CMI2 and CMI3 interrupt address. */
#warning Int 1 timer handler addresses not set.
VIC.VAD23.LONG = ( uint32_t ) NULL;
VIC.VAD24.LONG = ( uint32_t ) NULL;
VIC.VAD23.LONG = ( uint32_t ) vCMT_1_Channel_0_ISR_Entry;
VIC.VAD24.LONG = ( uint32_t ) vCMT_1_Channel_1_ISR_Entry;
/* Enable CMI2 and CMI3 interrupts in ICU. */
VIC.IEN0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL );
VIC.IEN0.LONG |= ( 1UL << 23UL ) | ( 1UL << 24UL );
/* Start CMT1 channel 0 and 1 count. */
CMT.CMSTR1.BIT.STR2 = 1U;
@ -159,8 +166,8 @@ extern void FreeRTOS_IRQ_Handler( void );
void vCMT_1_Channel_0_ISR( void )
{
/* Re-enabled interrupts. */
taskENABLE_INTERRUPTS();
/* Clear the interrupt. */
VIC.PIC0.LONG = ( 1UL << 23UL );
/* Call the handler that is part of the common code - this is where the
non-portable code ends and the actual test is performed. */
@ -170,8 +177,8 @@ void vCMT_1_Channel_0_ISR( void )
void vCMT_1_Channel_1_ISR( void )
{
/* Re-enabled interrupts. */
portENABLE_INTERRUPTS();
/* Clear the interrupt. */
VIC.PIC0.LONG = ( 1UL << 24UL );
/* Call the handler that is part of the common code - this is where the
non-portable code ends and the actual test is performed. */
@ -179,6 +186,40 @@ void vCMT_1_Channel_1_ISR( void )
}
/*-----------------------------------------------------------*/
/*
* The RZ/T vectors directly to a peripheral specific interrupt handler, rather
* than using the Cortex-R IRQ vector. Therefore each interrupt handler
* installed by the application must follow the examples below, which save a
* pointer to a standard C function in the pxISRFunction variable, before
* branching to the FreeRTOS IRQ handler. The FreeRTOS IRQ handler then manages
* interrupt entry (including interrupt nesting), before calling the C function
* saved in the pxISRFunction variable. NOTE: The entry points are naked
* functions - do not add C code to these functions.
*/
static void vCMT_1_Channel_0_ISR_Entry( void )
{
__asm volatile ( \
"PUSH {r0-r1} \t\n" \
"LDR r0, =pxISRFunction \t\n" \
"LDR r1, =vCMT_1_Channel_0_ISR \t\n" \
"STR r1, [r0] \t\n" \
"POP {r0-r1} \t\n" \
"B FreeRTOS_IRQ_Handler "
);
}
/*-----------------------------------------------------------*/
static void vCMT_1_Channel_1_ISR_Entry( void )
{
__asm volatile ( \
"PUSH {r0-r1} \t\n" \
"LDR r0, =pxISRFunction \t\n" \
"LDR r1, =vCMT_1_Channel_1_ISR \t\n" \
"STR r1, [r0] \t\n" \
"POP {r0-r1} \t\n" \
"B FreeRTOS_IRQ_Handler "
);
}

6
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/Full_Demo/main_full.c
View File

@ -248,8 +248,7 @@ void main_full( void )
/* Start all the other standard demo/test tasks. They have no particular
functionality, but do demonstrate how to use the FreeRTOS API and test the
kernel port. */
#warning IntQ tasks not included.
// vStartInterruptQueueTasks();
vStartInterruptQueueTasks();
vStartDynamicPriorityTasks();
vStartBlockingQueueTasks( mainBLOCK_Q_PRIORITY );
vCreateBlockTimeTasks();
@ -331,8 +330,7 @@ unsigned long ulErrorFound = pdFALSE;
/* Check all the demo tasks (other than the flash tasks) to ensure
that they are all still running, and that none have detected an error. */
#warning Int q tasks not created.
if( 0 )// if( xAreIntQueueTasksStillRunning() != pdTRUE )
if( xAreIntQueueTasksStillRunning() != pdTRUE )
{
ulErrorFound |= 1UL << 0UL;
}

1
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/cg_src/r_cg_systeminit.c
View File

@ -58,7 +58,6 @@ void R_Systeminit(void);
/* End user code. Do not edit comment generated here */
extern void r_set_exception_handler(void);
/***********************************************************************************************************************
* Function Name: R_Systeminit
* Description : This function initializes every macro.

291
FreeRTOS/Demo/CORTEX_R4F_RZ_T_GCC_IAR_ARM/src/main.c
View File

@ -1,4 +1,3 @@
#if 1
/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
@ -110,6 +109,11 @@ or 0 to run the more comprehensive test and demo application. */
/*-----------------------------------------------------------*/
/*
* The start up code does not include a routine to clear the BSS segment to 0
* (as would be normal before calling main()), so the BSS is cleared manually
* using the following function.
*/
static void prvClearBSS( void );
/*
@ -143,15 +147,13 @@ extern void R_Systeminit( void );
/*-----------------------------------------------------------*/
volatile uint32_t ultest = 0, ultest2 = 9999;
int main( void )
{
/* The start up code does not include a routine to clear the BSS segment to
0 (as would be normal before calling main()), so the BSS is cleared manually
using the following function. */
prvClearBSS();
configASSERT( ultest == 0 );
configASSERT( ultest2 == 9999 );
/* Configure the hardware ready to run the demo. */
prvSetupHardware();
@ -247,46 +249,6 @@ void vApplicationTickHook( void )
}
/*-----------------------------------------------------------*/
/* The function called by the RTOS port layer after it has managed interrupt
entry. */
void vApplicationIRQHandler( void )
{
#if 1
extern void FreeRTOS_Tick_Handler( void );
/* Clear the interrupt source CMI5. */
VIC.PIC9.LONG = 0x00001000UL;
FreeRTOS_Tick_Handler();
/* Dummy write */
portDISABLE_INTERRUPTS();
// Done in the epilogue code VIC.HVA0.LONG = 0x00000000UL;
#else
typedef void (*ISRFunction_t)( void );
ISRFunction_t pxISRFunction;
volatile uint32_t * pulAIC_IVR = ( uint32_t * ) configINTERRUPT_VECTOR_ADDRESS;
/* Obtain the address of the interrupt handler from the AIR. */
pxISRFunction = ( ISRFunction_t ) *pulAIC_IVR;
/* Write back to the SAMA5's interrupt controller's IVR register in case the
CPU is in protect mode. If the interrupt controller is not in protect mode
then this write is not necessary. */
*pulAIC_IVR = ( uint32_t ) pxISRFunction;
/* Ensure the write takes before re-enabling interrupts. */
__DSB();
__ISB();
__enable_irq();
/* Call the installed ISR. */
pxISRFunction();
#endif
}
/*-----------------------------------------------------------*/
static void prvClearBSS( void )
{
extern uint32_t __bss_start__[];
@ -300,240 +262,3 @@ size_t xSize;
#else
#include "FreeRTOS.h"
#include "task.h"
/***********************************************************************************************************************
Includes
***********************************************************************************************************************/
#include "r_cg_macrodriver.h"
#include "r_cg_cgc.h"
#include "r_cg_icu.h"
#include "r_cg_port.h"
#include "r_cg_tpu.h"
#include "r_cg_cmt.h"
#include "r_cg_scifa.h"
#include "r_cg_rspi.h"
#include "r_cg_s12ad.h"
/* Start user code for include. Do not edit comment generated here */
#include "r_cg_mpc.h"
#include "r_system.h"
#include "r_reset.h"
#include "lcd_pmod.h"
#include "logo_data.h"
#include "stdio.h"
#include "siochar.h"
/* End user code. Do not edit comment generated here */
#include "r_cg_userdefine.h"
/* Start user code for global. Do not edit comment generated here */
#define LZ_ENABLE (1)
#define LZ_DISABLE (0)
/* Welcome banner - displayed on serial port at startup*/
static uint8_t welcome_banner[] = "\n\n\rRSK+RZT1 \n\n\r- Tutorial - Press 'c' or SW3 for ADC Conversion\r\n\0";
/* Used as a Data Transmit counter */
static uint8_t uart_buffer[] = " ADC count: x. Value: xxxxx\r\n";
/* Used as a Data Transmit counter */
static uint8_t lcd_buffer[] = " ADC = xxxx ";
/* Function prototype for displaying the 2 bit binary counter using LEDs */
static void led_display_count (const uint8_t count);
extern void R_Systeminit(void);
void R_MAIN_UserInit(void);
/* Prototypes for the standard FreeRTOS callback/hook functions implemented
within this file. */
void vApplicationMallocFailedHook( void );
void vApplicationIdleHook( void );
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName );
void vApplicationTickHook( void );
/* Prototype for the IRQ handler called by the generic Cortex-A5 RTOS port
layer. */
void vApplicationIRQHandler( void );
void main(void)
{
uint32_t adc_count = 0;
R_Systeminit();
R_MAIN_UserInit();
/* SW3 interrupts */
R_ICU_IRQ12_Start();
/* Clear flags */
g_switch_press_flg = 0;
g_terminal_request = 0;
/* Display the welcome banner on the serial terminal */
R_SCIFA2_Serial_Send((uint8_t *)&welcome_banner, sizeof(welcome_banner));
/* Data transmission and reception done in the infinite loop */
while (1U)
{
/* Check for a valid request from the switch or serial terminal */
if ((g_terminal_request) || (g_switch_press_flg & SW3_PRESS_FLG))
{
/* Update the binary count using LED2 and LED3 */
led_display_count(adc_count);
while(0u == SCIFA2.FSR.BIT.TDFE)
{
/* Wait for previous transmission to complete */
}
/* Write send data */
R_SCIFA2_Serial_Send((uint8_t *)&uart_buffer, sizeof(uart_buffer));
/* Clear TDFE */
SCIFA2.FSR.BIT.TDFE = 0U;
if (g_terminal_request)
{
/* Clear the request */
g_terminal_request = 0U;
}
if (g_switch_press_flg & SW3_PRESS_FLG)
{
/* Clear the request */
g_switch_press_flg &= ((uint8_t)~SW3_PRESS_FLG);
}
adc_count++;
}
}
}
/***********************************************************************************************************************
* Function Name: R_MAIN_UserInit
* Description : This function adds user code before implementing main function.
* Arguments : None
* Return Value : None
***********************************************************************************************************************/
void R_MAIN_UserInit(void)
{
/* Enable RSPI1 operations */
R_RSPI1_Start();
/* Configure UART channel for communication with host PC via RL78/G1C device */
io_init_scifa2();
/* Enable SCIFA2 operations */
R_SCIFA2_Start();
}
static void led_display_count (const uint8_t count)
{
/* Set LEDs according to lower nibble of count parameter */
LED2 = (uint8_t) ((count & 0x01) ? LED_ON : LED_OFF);
LED3 = (uint8_t) ((count & 0x02) ? LED_ON : LED_OFF);
}
/*-----------------------------------------------------------*/
void vApplicationMallocFailedHook( void )
{
/* Called if a call to pvPortMalloc() fails because there is insufficient
free memory available in the FreeRTOS heap. pvPortMalloc() is called
internally by FreeRTOS API functions that create tasks, queues, software
timers, and semaphores. The size of the FreeRTOS heap is set by the
configTOTAL_HEAP_SIZE configuration constant in FreeRTOSConfig.h. */
/* Force an assert. */
configASSERT( ( volatile void * ) NULL );
}
/*-----------------------------------------------------------*/
void vApplicationStackOverflowHook( TaskHandle_t pxTask, char *pcTaskName )
{
( void ) pcTaskName;
( void ) pxTask;
/* Run time stack overflow checking is performed if
configCHECK_FOR_STACK_OVERFLOW is defined to 1 or 2. This hook
function is called if a stack overflow is detected. */
/* Force an assert. */
configASSERT( ( volatile void * ) NULL );
}
/*-----------------------------------------------------------*/
void vApplicationIdleHook( void )
{
volatile size_t xFreeHeapSpace;
/* This is just a trivial example of an idle hook. It is called on each
cycle of the idle task. It must *NOT* attempt to block. In this case the
idle task just queries the amount of FreeRTOS heap that remains. See the
memory management section on the http://www.FreeRTOS.org web site for memory
management options. If there is a lot of heap memory free then the
configTOTAL_HEAP_SIZE value in FreeRTOSConfig.h can be reduced to free up
RAM. */
xFreeHeapSpace = xPortGetFreeHeapSize();
/* Remove compiler warning about xFreeHeapSpace being set but never used. */
( void ) xFreeHeapSpace;
}
/*-----------------------------------------------------------*/
void vApplicationTickHook( void )
{
}
/*-----------------------------------------------------------*/
void vApplicationIRQHandler( void )
{
}
#endif

2
FreeRTOS/Demo/Common/Minimal/EventGroupsDemo.c
View File

@ -1021,7 +1021,7 @@ BaseType_t xMessagePosted;
else if( xCallCount == xClearBitsCount )
{
/* Clear the bits again. */
uxReturned = xEventGroupClearBitsFromISR( xISREventGroup, uxBitsToSet );
uxReturned = ( EventBits_t ) xEventGroupClearBitsFromISR( xISREventGroup, uxBitsToSet );
/* Check the message was posted. */
if( uxReturned != pdPASS )

2
FreeRTOS/Demo/Common/Minimal/TaskNotify.c
View File

@ -556,6 +556,6 @@ const uint32_t ulMultiplier = 0x015a4e35UL, ulIncrement = 1UL;
/* Utility function to generate a pseudo random number. */
ulNextRand = ( ulMultiplier * ulNextRand ) + ulIncrement;
return( ( int ) ( ulNextRand >> 16UL ) & 0x7fffUL );
return( ( ulNextRand >> 16UL ) & 0x7fffUL );
}
/*-----------------------------------------------------------*/

159
FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/ISR_Support.h
View File

@ -1,159 +0,0 @@
/*
FreeRTOS V8.2.2 - Copyright (C) 2015 Real Time Engineers Ltd.
All rights reserved
***************************************************************************
* *
* FreeRTOS tutorial books are available in pdf and paperback. *
* Complete, revised, and edited pdf reference manuals are also *
* available. *
* *
* Purchasing FreeRTOS documentation will not only help you, by *
* ensuring you get running as quickly as possible and with an *
* in-depth knowledge of how to use FreeRTOS, it will also help *
* the FreeRTOS project to continue with its mission of providing *
* professional grade, cross platform, de facto standard solutions *
* for microcontrollers - completely free of charge! *
* *
* >>> See http://www.FreeRTOS.org/Documentation for details. <<< *
* *
* Thank you for using FreeRTOS, and thank you for your support! *
* *
***************************************************************************
This file is part of the FreeRTOS distribution.
FreeRTOS is free software; you can redistribute it and/or modify it under
the terms of the GNU General Public License (version 2) as published by the
Free Software Foundation AND MODIFIED BY the FreeRTOS exception.
>>>NOTE<<< The modification to the GPL is included to allow you to
distribute a combined work that includes FreeRTOS without being obliged to
provide the source code for proprietary components outside of the FreeRTOS
kernel. FreeRTOS is distributed in the hope that it will be useful, but
WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
more details. You should have received a copy of the GNU General Public
License and the FreeRTOS license exception along with FreeRTOS; if not it
can be viewed here: http://www.freertos.org/a00114.html and also obtained
by writing to Richard Barry, contact details for whom are available on the
FreeRTOS WEB site.
1 tab == 4 spaces!
http://www.FreeRTOS.org - Documentation, latest information, license and
contact details.
http://www.SafeRTOS.com - A version that is certified for use in safety
critical systems.
http://www.OpenRTOS.com - Commercial support, development, porting,
licensing and training services.
*/
#define portNESTING_INTERRUPT_ENTRY() \
__asm volatile ( \
".extern ulPortYieldRequired \t\n" \
".extern ulPortInterruptNesting \t\n" \
".extern FreeRTOS_SVC_Handler \t\n" \
/* Return to the interrupted instruction. */ \
"SUB LR, LR, #4 \t\n" \
\
/* Push the return address and SPSR. */ \
"PUSH {LR} \t\n" \
"MRS LR, SPSR \t\n" \
"PUSH {LR} \t\n" \
\
/* Change to supervisor mode to allow reentry. */ \
"CPS #0x13 \t\n" \
\
/* Push used registers. */ \
"PUSH {r0-r4, r12} \t\n" \
\
/* Increment nesting count. r3 holds the address */ \
/* of ulPortInterruptNesting future use. */ \
"LDR r2, =ulPortInterruptNestingConst \t\n" \
"LDR r3, [r2] \t\n" \
\
"LDR r1, [r3] \t\n" \
"ADD r4, r1, #1 \t\n" \
"STR r4, [r3] \t\n" \
\
/* Ensure bit 2 of the stack pointer is clear. */ \
/* r2 holds the bit 2 value for future use. */ \
"MOV r2, sp \t\n" \
"AND r2, r2, #4 \t\n" \
"SUB sp, sp, r2 \t\n" \
\
/* Call the interrupt handler. */ \
"PUSH {r0-r3, LR} " \
);
#warning Why is ulPortYieldRequired accessed differently to the other variables?
#warning R0 seems to being pushed even though it is not used.
#warning Writing to the EOI register uses R4 on consecutive lines.
#define portNESTING_INTERRUPT_EXIT() \
__asm volatile ( \
"POP {r0-r3, LR} \t\n" \
"ADD sp, sp, r2 \t\n" \
" \t\n" \
"CPSID i \t\n" \
"DSB \t\n" \
"ISB \t\n" \
" \t\n" \
/* Write to the EOI register. */ \
"LDR r4, ulICCEOIRConst \t\n" \
"LDR r4, [r4] \t\n" \
"STR r0, [r4] \t\n" \
\
/* Restore the old nesting count. */ \
"STR r1, [r3] \t\n" \
\
/* A context switch is never performed if the */ \
/* nesting count is not 0. */ \
"CMP r1, #0 \t\n" \
"BNE 1f \t\n" \
\
/* Did the interrupt request a context switch? */ \
/* r1 holds the address of ulPortYieldRequired */ \
/* and r0 the value of ulPortYieldRequired for */ \
/* future use. */ \
"LDR r1, =ulPortYieldRequired \t\n" \
"LDR r0, [r1] \t\n" \
"CMP r0, #0 \t\n" \
"BNE 2f \t\n" \
\
"1: \t\n" \
/* No context switch. Restore used registers, */ \
/* LR_irq and SPSR before returning. 0x12 is IRQ */ \
/* mode. */ \
"POP {r0-r4, r12} \t\n" \
"CPS #0x12 \t\n" \
"POP {LR} \t\n" \
"MSR SPSR_cxsf, LR \t\n" \
"POP {LR} \t\n" \
"MOVS PC, LR \t\n" \
\
"2: \t\n" \
/* A context switch is to be performed. */ \
/* Clear the context switch pending flag. */ \
"MOV r0, #0 \t\n" \
"STR r0, [r1] \t\n" \
\
/* Restore used registers, LR-irq and */ \
/* SPSR before saving the context to the */ \
/* task stack. 0x12 is IRQ mode. */ \
"POP {r0-r4, r12} \t\n" \
"CPS #0x12 \t\n" \
"POP {LR} \t\n" \
"MSR SPSR_cxsf, LR \t\n" \
"POP {LR} \t\n" \
"b FreeRTOS_SVC_Handler \t\n" \
"ISB \t\n" \
"ulICCEOIRConst: .word ulICCEOIR \t\n" \
" ulPortInterruptNestingConst: .word ulPortInterruptNesting " \
);

26
FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portASM.S
View File

@ -75,8 +75,6 @@
.global vPortRestoreTaskContext
.macro portSAVE_CONTEXT
/* Save the LR and SPSR onto the system mode stack before switching to
@ -190,22 +188,23 @@ FreeRTOS_IRQ_Handler:
PUSH {lr}
/* Change to supervisor mode to allow reentry. */
CPS #0x13
/* Push used registers. */
PUSH {r0-r4, r12}
PUSH {r0-r3, r12}
/* Increment nesting count. r3 holds the address of ulPortInterruptNesting
for future use. r1 holds the original ulPortInterruptNesting value for
future use. */
LDR r3, ulPortInterruptNestingConst
LDR r1, [r3]
ADD r4, r1, #1
STR r4, [r3]
ADD r0, r1, #1
STR r0, [r3]
/* Ensure bit 2 of the stack pointer is clear. r2 holds the bit 2 value for
future use. */
MOV r2, sp
AND r2, r2, #4
MOV r0, sp
AND r2, r0, #4
SUB sp, sp, r2
/* Call the interrupt handler. */
@ -220,9 +219,9 @@ FreeRTOS_IRQ_Handler:
ISB
/* Write to the EOI register. */
LDR r4, ulICCEOIRConst
LDR r4, [r4]
STR r0, [r4]
LDR r0, ulICCEOIRConst
LDR r2, [r0]
STR r0, [r2]
/* Restore the old nesting count. */
STR r1, [r3]
@ -234,7 +233,7 @@ FreeRTOS_IRQ_Handler:
/* Did the interrupt request a context switch? r1 holds the address of
ulPortYieldRequired and r0 the value of ulPortYieldRequired for future
use. */
LDR r1, =ulPortYieldRequired
LDR r1, ulPortYieldRequiredConst
LDR r0, [r1]
CMP r0, #0
BNE switch_before_exit
@ -242,7 +241,7 @@ FreeRTOS_IRQ_Handler:
exit_without_switch:
/* No context switch. Restore used registers, LR_irq and SPSR before
returning. */
POP {r0-r4, r12}
POP {r0-r3, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
@ -257,7 +256,7 @@ switch_before_exit:
/* Restore used registers, LR-irq and SPSR before saving the context
to the task stack. */
POP {r0-r4, r12}
POP {r0-r3, r12}
CPS #IRQ_MODE
POP {LR}
MSR SPSR_cxsf, LR
@ -282,6 +281,7 @@ ulPortTaskHasFPUContextConst: .word ulPortTaskHasFPUContext
vTaskSwitchContextConst: .word vTaskSwitchContext
vApplicationIRQHandlerConst: .word vApplicationIRQHandler
ulPortInterruptNestingConst: .word ulPortInterruptNesting
ulPortYieldRequiredConst: .word ulPortYieldRequired
.end

2
FreeRTOS/Source/portable/GCC/ARM_CRx_No_GIC/portmacro.h
View File

@ -118,7 +118,7 @@ not need to be guarded with a critical section. */
/* Called at the end of an ISR that can cause a context switch. */
#define portEND_SWITCHING_ISR( xSwitchRequired )\
{ \
extern uint32_t ulPortYieldRequired; \
extern volatile uint32_t ulPortYieldRequired; \
\
if( xSwitchRequired != pdFALSE ) \
{ \